AVAGO ACPL-M62L So-5 package Datasheet

ACPL-M62L
Ultra Low Power 10 MBd Digital Optocoupler
Data Sheet
Description
Features
The ACPL-M62L is an optically-coupled optocoupler that
combines an AlGaAs light-emitting diode and an integrated high-gain photo detector addresses the low power
need. The optocoupler consumes low power at maximum
1.5 mA IDD across temperature. The forward current is as
low as 2 mA, and so allows direct current drive by most
microprocessors.
• Ultra-low current IDD consumption: 1.5 mA max.
ACPL-M62L support both 3.3 V and 5 V supply voltage
with guaranteed AC and DC operational parameters from
-40 °C to +105 °C. The output of the detector IC is an
open-drain type. The internal Faraday shield provides a
guaranteed common mode transient immunity specification of 20 kV/μs.
• High Speed: 10 MBd min.
• Low input current capability: 2 mA
• Open-drain output
• SO-5 package
• 20 kV/µs minimum Common Mode Rejection (CMR) at
VCM = 1000 V
• Guaranteed AC and DC performance over wide
temperature: -40 °C to +105 °C
• Safety and regulatory approval (pending):
– UL 1577 recognized - 3750 Vrms for 1 minute
This unique design provides maximum AC and DC circuit
isolation while achieving TTL/CMOS compatibility. These
optocouplers are suitable for high speed logic interfacing,
while consuming extremely low power.
Applications
Functional Diagram
• Communication interface: I2C-bus, CAN Bus
6 VDD
Anode 1
5 Vo
Cathode 3
Shield
4 GND
– CSA Approval
– IEC/EN/DIN EN 60747-5-5 for Reinforced Insulation
• Microprocessor system interfaces
Truth table (Positive Logic)
LED
OUTPUT
ON
L
OFF
H
• Digital isolation for A/D, D/A conversion
A 0.1 µF bypass capacitor must be connected between
pins VDD and GND.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation, which may be induced by ESD.
Ordering Information
ACPL-M62L is UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part number
RoHS Compliant
Package
Surface Mount
ACPL-M62L
-000E
SO-5
X
IEC/EN/DIN EN
60747-5-5
Tape & Reel
Quantity
100 per tube
-060E
X
X
-500E
X
X
-560E
X
X
100 per tube
1500 per reel
X
1500 per reel
To order, choose a part number from the Part number column and combine with the desired option from the Option
column to form an order entry.
Example:
ACPL-M62L-560E: to order product of Small Outline SO-5 package in Tape and Reel packaging with IEC/EN/DIN EN
60747-5-5 Safety Approval in RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Package Outline Drawing
ACPL-M62L SO-5 Package
LAND PATTERN RECOMMENDATION
1.27
(0.05)
RoHS-COMPLIANCE
INDICATOR
0.64
(0.025)
PART NUMBER
DATE CODE
MXXX
XXX
4.4 ± 0.1
(0.173 ± 0.004)
7.0 ± 0.2
(0.276 ± 0.008)
2.54
(0.10)
3.6 ± 0.1*
(0.142 ± 0.004)
0.102 ± 0.102
(0.004 ± 0.004)
1.27 BSC
(0.050)
Dimensions in millimeters (inches).
Note: Floating Lead Protrusion is 0.15 mm (6 mils) max.
* Maximum Mold Flash on each side is 0.15 mm (0.006).
2
8.26
(0.325)
1.80
(0.071)
0.4 ± 0.05
(0.016 ± 0.002)
2.5 ± 0.1
(0.098 ± 0.004)
4.39
(0.17)
0.15 ± 0.025
(0.006 ± 0.001)
7° MAX.
0.71 MIN
(0.028)
MAX. LEAD COPLANARITY
= 0.102 (0.004)
Solder Reflow Profile
Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.
Regulatory Information
ACPL-M62L is pending approval by the following organizations:
UL
CSA
IEC/EN/DIN EN 60747-5-5
UL 1577, component recognition
program up to VISO = 3750 VRMS File
E55361.
Approved under CSA Component
Acceptance Notice #5, File CA 88324.
(Option 060E only)
Insulation and Safety Related Specifications
Parameter
Symbol ACPL-M62L Units Conditions
Minimum External Air Gap
(External Clearance)
L(101)
5
mm
Measured from input terminals to output terminals,
shortest distance through air.
Minimum External Tracking
(External Creepage)
L(102)
5
mm
Measured from input terminals to output terminals,
shortest distance path along body.
0.08
mm
Through insulation distance conductor to conductor, usually the
straight line distance thickness between the emitter and detector.
175
V
DIN IEC 112/VDE 0303 Part 1
Minimum Internal Plastic Gap
(Internal Clearance)
Tracking Resistance
(Comparative Tracking Index)
CTI
Isolation Group
IIIa
Material Group (DIN VDE 0110, 1/89, Table 1)
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics* (Option 060E)
Description
Symbol
Characteristic Unit
Installation classification per DIN VDE 0110/39, Table 1
for rated mains voltage ≤ 150 Vrms
for rated mains voltage ≤ 300 Vrms
for rated mains voltage ≤ 600 Vrms
I – IV
I – IV
I – III
Climatic Classification
40/105/21
Pollution Degree (DIN VDE 0110/39)
2
Maximum Working Insulation Voltage
VIORM
567
Vpeak
Input to Output Test Voltage, Method b*
VIORM × 1.875=VPR, 100% Production Test with tm=1 sec, Partial discharge < 5 pC
VPR
1063
Vpeak
Input to Output Test Voltage, Method a*
VIORM × 1.6=VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
VPR
907
Vpeak
Highest Allowable Overvoltage
(Transient Overvoltage tini = 60 sec)
VIOTM
6000
Vpeak
Safety-limiting values – maximum values allowed in the event of a failure
Case Temperature
Input Current
Output Power
TS
150
IS, INPUT
150
PS, OUTPUT 600
Insulation Resistance at TS, VIO = 500 V
RS
>109
°C
mA
mW
Ω
* Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section, (IEC/EN/DIN
EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test profiles.
3
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storage Temperature
TS
-55
125
°C
Operating Temperature
TA
-40
105
°C
Reverse Input Voltage
VR
5
V
Supply Voltage
VDD
6.5
V
Average Forward Input Current
IF
8
mA
Output Current
IO
10
mA
Output Voltage
VO
VDD + 0.5
V
Input Power Dissipation
PI
14
mW
Output Power Dissipation
PO
20
mW
Lead Solder Temperature
TLS
260 °C for 10 sec., 1.6 mm below seating plane
–0.5
Solder Reflow Temperature Profile
Condition
Refer to Solder Reflow Profile section
Recommended Operating Conditions
Parameter
Symbol
Min.
Max.
Units
Operating Temperature
TA
-40
105
°C
Input Current, Low Level
IFL
0
250
µA
Input Current, High Level
IFH
2
6
mA
Power Supply Voltage
VDD
2.7
5.5
V
Forward Input Voltage
VF(OFF)
0.8
V
Electrical Specifications (DC)
Over recommended temperature (TA = –40 °C to +105 °C) and supply voltage (2.7 V ≤ VDD ≤ 3.6 V). All typical specifications are at VDD = 3.3 V, TA = 25 °C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Input Forward Voltage
VF
0.95
1.3
1.7
V
IF = 2.2 mA, Figure 1, Figure 2
Input Reverse Breakdown Voltage
BVR
3
5
V
IR = 10 µA
Logic High Output Current
IOH
4.5
50
µA
VDD = 3.3 V, IF = 250 µA, VO = 3.3 V
Logic Low Output Voltage
VOL
0.3
0.6
V
IF= 2.2 mA, IO =10 mA, RL=390 Ω
Input Threshold Current
ITH
0.7
1.5
mA
Figure 3
Logic Low Output Supply Current
IDDL
0.8
1.5
mA
Figure 4
Logic High Output Supply Current
IDDH
0.8
1.5
mA
Figure 5
Input Capacitance
CIN
60
pF
f = 1 MHz, VF = 0 V
Input Diode Temperature Coefficient
ΔVF/ΔTA
-1.6
mV/°C
IF = 2.2 mA
Over recommended temperature (TA = –40 °C to +10 5°C) and supply voltage (4.5 V ≤ VDD ≤ 5.5 V). All typical specifications are at VDD = 5 V, TA = 25 °C.
Parameter
Symbol
Min.
Typ.
Max.
Units
Test Conditions
Input Forward Voltage
VF
0.95
1.3
1.7
V
IF = 2.2 mA, Figure 1, Figure 2
Input Reverse Breakdown Voltage
BVR
3
5
V
IR = 10 µA
Logic High Output Current
IOH
5.5
100
µA
VDD = 5.5 V, IF = 250 µA, VO = 5.5 V
Logic Low Output Voltage
VOL
0.3
0.6
V
IF = 2.2 mA, IO = 8.4 mA, RL= 560 Ω
Input Threshold Current
ITH
0.7
1.5
mA
Figure 3
Logic Low Output Supply Current
IDDL
0.8
1.5
mA
Figure 4
Logic High Output Supply Current
IDDH
0.8
1.5
mA
Figure 5
Input Capacitance
CIN
60
pF
f = 1 MHz, VF = 0 V
Input Diode Temperature Coefficient
ΔVF/ΔTA
-1.6
mV/°C
IF = 2.2 mA
4
Switching Specifications (AC)
Over recommended temperature (TA = –40 °C to +105 °C), supply voltage (2.7 V ≤ VDD ≤ 3.6 V). All typical specifications
are at VDD = 3.3 V, TA = 25 °C.
Parameter
Symbol Min.
Typ.
Max. Units Test Conditions
Propagation Delay Time to Logic
Low Output [1]
tPHL
46
80
ns
Propagation Delay Time to Logic
High Output [1]
tPLH
40
80
ns
Pulse Width
tPW
Pulse Width Distortion [2]
PWD
Propagation Delay Skew [3]
tPSK
Output Rise Time (10% – 90%)
tR
Output Fall Time (90% - 10%)
100
ns
6
tF
30
ns
30
ns
IF = 2.2 mA, VI = 5 V, RT = 1.5 kΩ, CL= 15 pF
IF = 2.2 mA, VI = 3.3 V, RT = 700 Ω, CL= 15 pF
RL = 390 Ω, Figure 6a, Figure 7a
12
ns
IF = 2.2 mA, VI = 5 V, RT = 1.5 kΩ, CL= 15 pF, RL = 390 Ω
10
ns
IF = 2.2 mA, VI = 3.3 V, RT = 700 Ω, CL = 15 pF, RL =390Ω
12
ns
IF = 2.2 mA, VI = 5 V, RT = 1.5 kΩ, CL = 15 pF, RL= 390 Ω
10
ns
IF = 2.2 mA, VI = 3.3 V, RT = 700 Ω, CL= 15 pF, RL =390 Ω
Static Common Mode Transient
Immunity at Logic High Output [4]
| CMH | 20
35
kV/µs VCM = 1000 V, TA = 25 °C, IF = 0 mA, CL= 15 pF,
RL = 390 Ω, Figure 8
Static Common Mode Transient
Immunity at Logic Low Output [5]
| CML |
35
kV/µs VCM = 1000 V, TA = 25 °C, VI = 5 V (RT =1.5 kΩ) or VI =
3.3 V (RT=700Ω), IF = 2.2 mA, CL= 15 pF, RL= 390 Ω,
Figure 8
35
kV/µs VCM = 1000 V, TA = 25 °C, IF = 2.2 mA, VI = 5 V (RT =1.5
kΩ) or VI = 3.3 V (RT=700 Ω), 10 MBd data rate, the
absolute increase of PWD <10 ns, RL= 390 Ω
20
Dynamic Common Mode Transient CMRD
Immunity [6]
Over recommended temperature (TA = –40 °C to +105 °C), supply voltage (4.5 V ≤ VDD ≤ 5.5 V). All typical specifications
are at VDD = 5 V, TA = 25 °C.
Parameter
Symbol Min.
Typ.
Max. Units
Propagation Delay Time to Logic
Low Output [1]
tPHL
46
80
ns
Propagation Delay Time to Logic
High Output [1]
tPLH
40
80
ns
Pulse Width
tPW
Pulse Width Distortion [2]
PWD
6
30
ns
Propagation Delay Skew [3]
tPSK
30
ns
Output Rise Time (10% – 90%)
tR
Output Fall Time (90% - 10%)
tF
100
ns
Test Conditions
IF = 2.2 mA, VI = 5 V, RT=1.5 kΩ, CL= 15 pF
IF = 2.2 mA, VI = 3.3 V, RT = 700 Ω, CL= 15 pF
RL= 560 Ω, Figure 6b, Figure 7b
12
ns
IF = 2.2 mA, VI = 5 V, RT =1.5 kΩ, CL = 15 pF, RL= 560 Ω
10
ns
IF = 2.2 mA, VI = 3.3 V, RT = 700 Ω, CL= 15 pF, RL =560 Ω
12
ns
IF = 2.2 mA, VI= 5 V, RT = 1.5 kΩ, CL = 15 pF, RL= 560 Ω
10
ns
IF = 2.2 mA, VI = 3.3 V, RT = 700 Ω, CL= 15 pF, RL= 560 Ω
Static Common Mode Transient
Immunity at Logic High Output [4]
|CMH|
20
35
kV/µs VCM = 1000 V, TA = 25 °C, IF = 0 mA, CL= 15 pF,
RL = 560 Ω, Figure 8
Static Common Mode Transient
Immunity at Logic Low Output [5]
|CML|
20
35
kV/µs VCM = 1000 V, TA = 25 °C, VI = 5 V (RT = 1.5 kΩ) or VI =
3.3 V (RT = 700 Ω), IF = 2.2 mA, CL= 15 pF,
RL= 560 Ω, Figure 8
35
kV/µs VCM = 1000 V, TA = 25 °C, IF = 2.2 mA, VI = 5 V (RT = 1.5
kΩ) or VI = 3.3 V (RT =700 Ω), 10 MBd data rate, the
absolute increase of PWD <10 ns, RL = 560 Ω
Dynamic Common Mode Transient CMRD
Immunity [6]
5
1.8
10
TA=25 °C
1
IF
0.1
1.6
VF - Forward Voltage - V
IF - Forward Current - mA
1.7
VF
1.5
1.4
1.3
1.2
1.1
1.2
1.3
1.4
VF - Forward Voltage - V
Figure 1. Typical input diode forward characteristic
Itc - Input Threshold Current - A
0.8
0.6
0.4
ITH_3.3V
ITH_5.0V
0.2
-40
-20
0
20
40
60
TA -Tem perature - °C
80
100
120
IDDH - Logic High Output Supply Current - mA
Figure 3. Typical input threshold current ITH vs. temperature
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
40
80
TA -Tem perature - °C
Figure 5. Typical logic high output supply current IDDH vs. temperature
6
-20
0
20
40
60
TA -Tem perature - °C
80
100
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-40
3.3 V
5V
0
40
TA -Tem perature - °C
80
Figure 4. Typical logic low output supply current IDDL vs. temperature
3.3 V
5V
0
-40
Figure 2. Typical VF vs. temperature
1
0
1
1.5
IDDL - Logic Low Output Supply Current - mA
0.01
1.1
120
120
tp - Propagation Delay;
PWD Pulse Width Distortion - ns
tp - Propagation Delay;
PWD Pulse Width Distortion - ns
60
50
40
30
TPHL_3.3V
TPLH_3.3V
PWD_3.3V
20
10
0
1.5
2
2.5
3
3.5 4
4.5
IF - Input Current - mA
5
5.5
6
Figure 6a. Typical switching speed vs. input current at 3.3 V supply voltage
50
45
40
35
30
25
20
15
10
5
0
1.5
50
tp - Propagation Delay;
PWD Pulse Width Distortion - ns
tp - Propagation Delay;
PWD Pulse Width Distortion - ns
60
40
30
20
10
-40
IF
-20
0
20
40
60
80
TA -Tem perature - °C
VDD
6
C=0.1µF
R1
1
Anode
B
5
100
3
3.5
4
4.5
IF - Input Current - mA
5
5.5
6
3
Cathode
4
Shield
VCM
Pulse Gen
+
–
Figure 8. Common Mode Transient Immunity Test Setup
50
40
30
20
10
-40
-20
0
20
40
60
TA -Tem perature - °C
80
100
120
Figure 7b. Typical propagation delay v s. temperature at 5 V supply voltage
3.3 V / 5 V
RL
Output
Monitoring
node
GND
TPHL_5.0V
TPLH_5.0V
PWD_5.0V
60
0
120
V CM
Vo
R2
7
2.5
70
TPHL_3.3V
TPLH_3.3V
PWD_3.3V
Figure 7a. Typical propagation delay v s. temperature at 3.3V supply voltage
A
2
Figure 6b. Typical switching speed vs. input current at 5 V supply voltage
70
0
TPHL_5.0V
TPLH_5.0V
PWD_5.0V
VO
V CM (PEAK)
0V
V DD
SWITCH AT A: I F = 0 mA
SWITCH AT B: IF = 2.2 mA
VO
GND
CM H
V O (min.)
V O (max.)
CM L
Package Characteristics
All typical at TA = 25 °C.
Parameter
Symbol
Min.
Input-Output Insulation
VISO
3750
Typ.
Input-Output Resistance
RI-O
1012
Input-Output Capacitance
CI-O
0.6
Max.
Units
Test Conditions
Vrms
RH < 50% for 1 min. TA = 25 °C
Ω
VI-O = 500 V
pF
f =1 MHz, TA = 25 °C
Notes:
1. tPHL propagation delay is measured from the 50% (Vin or IF) on the rising edge of the input pulse to the 50% VDD of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% (Vin or IF) on the falling edge of the input pulse to the 50% level of the rising edge of the VO signal.
2. PWD is defined as |tPHL - tPLH|.
3. tPSK is equal to the magnitude of the worst-case difference in tPHL and/or tPLH that will be seen between units at any given temperature within the
recommended operating conditions.
4. CMH is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.
5. CML is the maximum tolerable rate of fall of the common mode voltage to assure that the output will remain in a low logic state.
6. CMD is the maximum tolerable rate of the common mode voltage during data transmission to assure that the absolute increase of the PWD is less
than 10 ns.
Supply Bypassing, LED Bias Resistors and PC Board Layout
The ACPL-M62L optocouplers are extremely easy to use and feature high speed, open-drain outputs.
The external components required for proper operation are the input limiting resistors and the output bypass capacitor.
Capacitor values should be 0.1 µF.
For each capacitor, the total lead length connecting the capacitor to the VDD and GND pins should not exceed 20 mm.
VDD = 3.3 V: R1 = 420 Ω ± 1%, R2 = 280 Ω ± 1%
VDD = 5.0 V: R1 = 900 Ω ± 1%, R2 = 600 Ω ± 1%
RT = R1 + R2; R1/R2 ≈ 1.5
VDD
IF
6
R1
1
VI
C =0.1µF
RL
Vo
5
R2
GND 1
3
Shield
4
GND 2
Figure 9. Recommended printed circuit board layout and input current limiting resistor selection
8
Optocoupler CMR Performance
The principal protection against common mode noise,
comes from the fundamental isolation properties of the
optocoupler, and this in turn is directly related to the Input-Output leakage capacitance of the optocoupler.
To provide maximum protection to circuitry connected
to the input or output of the optocoupler the leakage
capac¬itance is minimized by having large separation
distances at all points in the optocoupler construction, including the LED/photodiode interface.
In addition to the optocouplers basic physical
construc¬tion, additional circuit design steps mitigate
the effects of common mode noise. The most important
of these is the Faraday shield on the photodetector stage.
A Faraday shield is effective in optocouplers because
the internal modulation frequency (light) is many orders
of magnitude higher than the common mode noise frequency.
Improving CMR Performance at the Application Level
In an end application it desirable that the optocouplers
common mode isolation be as close as possible to that
indicated in the data sheet specifications. The first step in
meeting this goal is to ensure maximum separation between PCB interconnects on either side of the opto-coupler is maintained and that PCB tracks beneath the optocoupler are avoided.
It is inevitable that a certain amount of CMR noise will be
coupled into the inputs and this can potentially result in
false-triggering of the input. This problem is frequently
observed in devices with input high input impedance. In
some cases this can cause momentary missing pulses and
may even cause input circuitry to latch-up in some alternate technologies.
The ACPL-M62L optocoupler family does not have an input latch-up issue. Even at very high CMR levels such as
those experienced in end equipment level tests (for example IEC61000-4-4) the ACPL-M62L series is immune to
latch-up because of the simple diode structure of the LED.
In some cases achieving the rated data sheet CMR
per¬formance level is not possible in an application. This
is often because of the practical need to actually connect
the isolator input to the output of a dynamically changing signal rather than tying the input statically to VDD or
GND. A data sheet CMR “specmanship” issue is often seen
with alternative technology isolators that are based on AC
encoding techniques.
For product information and a complete list of distributors, please go to our web site:
To address the need to define achievable end application
performance on data sheets, the ACPL-M62L optocouplers
include an additional typical performance specification
for dynamic CMR in the electrical parameter table. The dynamic CMR specification indicates the typical achievable
CMR performance as the input is being toggled on or off
during a CMR transient.
The logic output the ACPL-M62L optocouplers is mainly
controlled by LED current level, and since the LED current
features very fast rise and fall times, dynamic noise immunity is essentially the same as static noise immunity.
Despite their immunity to input latch-up and the excellent dynamic CMR immunity, ACPL-M62L opto¬coupler
devices are still potentially vulnerable to miss-operation
caused by the LED being turned either on or off during a
CMR disturbance. If the LED status could be ensured by
design, the overall application level CMR performance
would be that of the photodetector. To benefit from the
inherently high CMR capabilities of the ACPL-M62L family,
some simple steps about operating the LED at the application level should be taken.
In particular, ensure that the LED stays either on or off during a CMR transient. Some common design techniques to
accomplish this are:
• Keep the LED on:
– Overdrive the LED with a higher than required
forward current.
• Keep the LED off:
During the Off state:
i) Reverse bias the LED.
ii) Minimize the off-state impedance across the anode
and cathode of the LED.
All these methods allow the full CMR capability of the ACPL-M62L family to be achieved, but they do have practical
implementation issues or require a compromise on power
consumption.
There is, however, an effective method to meet the goal
of maintaining the LED status during a CMR event with
no other design compromises other than adding a single
resistor.
This CMR optimization takes advantage of the differential
connection to the LED. By ensuring the common mode
impedances at both the cathode and anode of the LED
are equal, the CMR transient on the LED is effectively canceled. As shown in Figure 9, this is easily achieved by using
two, instead of one, input bias resistors.
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AV02-4059EN - April 19, 2013