Rohm BD9134MUV 0909 Output 2a or more high-efficiency step-down switching regulator with built-in power mosfet Datasheet

Single-chip Type with Built-in FET Switching Regulator Series
Output 2A or More High-efficiency
Step-down Switching Regulator
with Built-in Power MOSFET
BD9134MUV
No.09027EBT15
●Description
ROHM’s high efficiency step-down switching regulator BD9134MUV is a power supply designed to produce 3.3 volts from
5 volts power supply line. Offers high efficiency with our original pulse skip control technology and synchronous rectifier.
Employs a current mode control system to provide faster transient response to sudden change in load.
●Features
1) Offers fast transient response with current mode PWM control system.
2) Offers highly efficiency for all load range with synchronous rectifier (Nch/Nch FET)
TM
and SLLM (Simple Light Load Mode)
3) Incorporates soft-start function.
4) Incorporates thermal protection and UVLO functions.
5) Incorporates short-current protection circuit with time delay function.
6) Incorporates shutdown function Icc=0μA(Typ.)
7) Employs small surface mount package : VQFN020V4040
●Use
Power supply for LSI including DSP, Micro computer and ASIC
●Absolute Maximum Rating (Ta=25℃)
Parameter
VCC Voltage
PVCC Voltage
BST Voltage
BST_SW Voltage
EN Voltage
SW,ITH Voltage
Power Dissipation 1
Power Dissipation 2
Power Dissipation 3
Power Dissipation 4
Operating temperature range
Storage temperature range
Maximum junction temperature
*1
*2
*3
*4
*5
Symbol
Limits
Unit
1
VCC
PVCC
VBST
VBST-SW
VEN
VSW, VITH
Pd1
Pd2
Pd3
Pd4
Topr
Tstg
Tj
-0.3~+7 *
-0.3~+7 *1
-0.3~+13
-0.3~+7
-0.3~+7
-0.3~+7
0.34 *2
0.70 *3
1.21 *4
3.56 *5
-40~+105
-55~+150
+150
V
V
V
V
V
V
W
W
W
W
℃
℃
℃
Pd should not be exceeded.
IC only
1-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 10.29mm2 , in each layers
4-layer. mounted on a 74.2mm×74.2mm×1.6mm glass-epoxy board, occupied area by copper foil : 5505mm2, in each layers
●Operating Conditions (Ta=-40~+105℃)
Parameter
Power Supply Voltage
EN Voltage
Output Current
*6
Symbol
VCC
PVCC
VEN
ISW
Min.
4.5
4.5
0
-
Limits
Typ.
5
5
-
Max.
5.5
5.5
5.5
3.0*6
Unit
V
V
V
A
Pd should not be exceeded.
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1/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Electrical Characteristics
◎(Ta=25℃ VCC=PVCC=5V, EN=VCC, unless otherwise specified.)
Parameter
Symbol
Limits
Unit
Min.
Typ.
Max.
Conditions
Standby current
ISTB
-
0
10
μA
Active current
EN Low voltage
ICC
-
250
500
μA
VENL
-
GND
0.8
V
Standby mode
EN High voltage
VENH
2.0
Vcc
-
V
Active mode
VEN=5V
EN input current
EN=GND
IEN
-
1
10
μA
Oscillation frequency
FOSC
0.8
1
1.2
MHz
High side FET ON resistance
RONH
-
82
115
mΩ
PVCC=5V
Low side FET ON resistance
RONL
-
70
98
mΩ
PVCC=5V
OUTPUT Voltage
VOUT
3.25
3.3
3.35
V
ITH SInk current
ITHSI
10
18
-
μA
VOUT=4.1V
ITH Source Current
ITHSO
10
18
-
μA
VOUT=2.5V
UVLO threshold voltage
VUVLO1
3.6
3.8
4.0
V
VCC=5V→0V
UVLO release voltage
VUVLO2
3.65
3.9
4.2
V
VCC=0V→5V
TSS
2.5
5
10
ms
TLATCH
0.5
1
2
ms
VSCP
-
1.65
2.4
V
Soft start time
Timer latch time
Output Short circuit Threshold Voltage
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2/17
VOUT =3.3V→0V
2009.09 - Rev.B
Technical Note
BD9134MUV
●Block Diagram, Application Circuit
VCC
【BD9134MUV】
EN
4.0
VCC
VREF
4.0
D9134
BST
Current
Comp
1.0Max.
R Q
+
Lot No.
S
Gm Amp
S
C0.2 2.1±0.1
0.3±0.1
1
5
20
6
16
10
1.0
15
VOUT
5V
Input
+
Driver
Logic
SW
Output
PVCC
UVLO
PGND
TSD
GND
SCP
ITH
RITH
11
0.25 +0.05
-0.04
0.5
PVCC
VCC
Soft
Start
2.1±0.1
0.1±0.07
0.08 S
0.01 +0.03
-0.01
(0.21)
+
SLOPE
CLK
OSC
Current
Sense/
Protect
CITH
Fig.2
BD9134MUV Block Diagram
VQFN020V4040(Unit : mm)
Fig.1
BD9134MUV TOP View
●Pin No. & function table
Pin
Pin
No.
name
Function
Pin
No.
Pin
name
Function
1
SW
SW pin
11
GND
Ground
2
SW
SW pin
12
VOUT
Output voltage detect pin
3
SW
SW pin
13
ITH
GmAmp output pin/Connected phase
compensation capacitor
4
SW
SW pin
14
N.C.
Non Connection
5
SW
SW pin
15
N.C.
Non Connection
6
PVCC
Highside FET source pin
16
N.C.
Non Connection
7
PVCC
Highside FET source pin
17
EN
Enable pin(High Active)
8
PVCC
Highside FET source pin
18
PGND
Lowside FET source pin
9
BST
Bootstrapped voltage input pin
19
PGND
Lowside FET source pin
10
VCC
VCC power supply input pin
20
PGND
Lowside FET source pin
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○
3/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Characteristics data
5.0
4.0
4.0
【VOUT=3.3V】
3.0
2.0
1.0
Ta=25℃
Io=3A
0.0
0
1
2
3
4
INPUT VOLTAGE:VCC[V]
3.0
2.0
VCC=5V
Ta=25℃
Io=0A
1.0
0
1
4
0
3.31
3.30
3.29
3.28
0
20
40
60
TEMPERATURE:Ta[℃]
80
70
60
50
40
【VOUT=3.3V】
30
0
100
1
10
100
1000
OUTPUT CURRENT:IOUT[mA]
125
VCC=5V
10000
-40
-20
High side
50
Low side
VCC=5V
EN VOLTAGE:VEN[V]
100
400
1.8
350
1.4
1.2
1.0
0.8
0.6
0.4
VCC=5V
100
Fig.9 Ta – RONN, RONP
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○
40
60
80
100
300
250
200
150
100
VCC=5V
50
0
0.0
80
20
Fig.8 Ta - Fosc
2.0
0.2
0
TEMPERATURE:Ta[℃]
1.6
0
20
40
60
TEMPERATURE:Ta[℃]
400
0
CIRCUIT CURRENT:I CC [μA]
150
-20
600
Fig.7 Efficiency
Fig. 6 Ta - VOUT
0
-40
800
200
VCC=5V
Ta=25℃
10
3.25
25
8
1000
20
VCC=5V
Io=0A
75
7
1200
FREQUENCY:FOSC[MHz]
EFFICIENCY:η[%]
3.32
-20
2
3
4
5
6
OUTPUT CURRENT:IOUT [A]
Fig.5 IOUT - VOUT
80
-40
1
90
3.33
3.26
VCC=5V
Ta=25℃
5
100
3.27
1.0
Fig.4 VEN - VOUT
【VOUT=3.3V】
3.34
OUTPUT VOLTAGE:VOUT[V]
3
2.0
EN VOLTAGE:VEN[V]
3.35
ON [Ω]
2
3.0
0.0
0.0
5
Fig.3 Vcc - VOUT
ON RESISTANCE:R
【VOUT=3.3V】
4.0
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
OUTPUT VOLTAGE:VOUT[V]
【VOUT=3.3V】
-40
-20
0
20
40
60
80
TEMPERATURE:Ta[℃]
Fig.10 Fig.11 Ta - VEN
4/17
100
-40
-20
0
20
40
60
80
100
TEMPERATURE:Ta[℃]
Fig.11 Ta - Icc
2009.09 - Rev.B
Technical Note
BD9134MUV
●Characteristics data
1.1
FREQUENCY:FOSC[MHz]
【VOUT=3.3V】
【SLLM
VCC=PVCC
=EN
1
TM
VOUT=3.3V】
SW
0.9
0.8
Ta=25℃
0.7
4.5
4.75
5
5.25
INPUT VOLTAGE:VCC [V]
5.5
Fig.12 Vcc - Fosc
【PWM
VCC=5V
Ta=25℃
Io=0A
VOUT
VOUT
VCC=5V
Ta=25℃
Fig.13 Soft start waveform
VOUT=3.3V】
Fig.14 SW waveform Io=10mA
【VOUT=3.3V】
【VOUT=3.3V】
VOUT
VOUT
SW
VOUT
IOUT
IOUT
VCC=5V
Ta=25℃
VCC=5V
Ta=25℃
Fig.15 SW waveform Io=3A
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○
Fig. 16 Transient Response
Io=1→3A(10μs)
5/17
VCC=5V
Ta=25℃
Fig.17 Transient Response
Io=3→1A(10μs)
2009.09 - Rev.B
Technical Note
BD9134MUV
●Information on advantages
Advantage 1:Offers fast transient response with current mode control system.
BD9134MUV (Load response IO=1A→3A)
Conventional product (Load response IO=1A→3A)
VOUT
VOUT
328mV
572mV
IOUT
IOUT
Voltage drop due to sudden change in load was reduced by about 50%.
Fig.18 Comparison of transient response
Advantage 2: Offers high efficiency for all load range.
・For lighter load:
TM
Utilizes the current mode control mode called SLLM for lighter load, which reduces various dissipation such as
switching dissipation (PSW), gate charge/discharge dissipation, ESR dissipation of output capacitor (PESR) and
on-resistance dissipation (PRON) that may otherwise cause degradation in efficiency for lighter load.
Achieves efficiency improvement for lighter load.
・For heavier load:
Utilizes the synchronous rectifying mode and the low on-resistance MOS FETs incorporated as power transistor.
ON resistance of Highside MOS FET : 82mΩ(Typ.)
ON resistance of Lowside MOS FET : 70mΩ(Typ.)
Efficiency η[%]
100
Achieves efficiency improvement for heavier load.
Offers high efficiency for all load range with the improvements mentioned above.
SLLMTM
②
50
①
PWM
TM
①inprovement by SLLM
system
②improvement by synchronous rectifier
0
0.001
0.01
0.1
Output current Io[A]
1
Fig.19 Efficiency
Advantage 3:・Supplied in smaller package due to small-sized power MOS FET incorporated.
・Output capacitor Co required for current mode control: 22μF ceramic capacitor
・Inductance L required for the operating frequency of 1 MHz: 2.2μH inductor
・Incorporates FET + Boot strap diode
Reduces a mounting area required.
VCC
EN
VCC
VREF
20mm
BST
Current
Comp
+
Gm Amp
+
Soft
Start
SLOPE
VCC
OSC
UVLO
RQ
S
CLK
PVCC
Current
Sense/
Protect
+
SW
3.3V
Input
Cf
Rf
Output
PVCC
Driver
Logic
CBST
R2
15mm
PGND
R1
L
CIN
RITH
TSD
SCP
CITH
GND
Co
VOUT
ITH
RITH CITH
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○
Fig.20 Example application
6/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Operation
BD9134MUV is a synchronous rectifying step-down switching regulator that achieves faster transient response by employing
current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation) mode for heavier load,
TM
while it utilizes SLLM (Simple Light Load Mode) operation for lighter load to improve efficiency.
○Synchronous rectifier
It does not require the power to be dissipated by a rectifier externally connected to a conventional DC/DC converter IC, and
its P.N junction shoot-through protection circuit limits the shoot-through current during operation, by which the power
dissipation of the set is reduced.
○Current mode PWM control
Synthesizes a PWM control signal with a inductor current feedback loop added to the voltage feedback.
・PWM (Pulse Width Modulation) control
The oscillation frequency for PWM is 1 MHz. SET signal form OSC turns ON a highside MOS FET (while a lowside MOS
FET is turned OFF), and an inductor current IL increases. The current comparator (Current Comp) receives two signals,
a current feedback control signal (SENSE: Voltage converted from IL) and a voltage feedback control signal (FB), and
issues a RESET signal if both input signals are identical to each other, and turns OFF the highside MOS FET (while a
lowside MOS FET is turned ON) for the rest of the fixed period. The PWM control repeat this operation.
TM
・SLLM (Simple Light Load Mode) control
When the control mode is shifted from PWM for heavier load to the one for lighter load or vise versa, the switching pulse is
designed to turn OFF with the device held operated in normal PWM control loop, which allows linear operation without
voltage drop or deterioration in transient response during the mode switching from light load to heavy load or vise versa.
Although the PWM control loop continues to operate with a SET signal from OSC and a RESET signal from Current Comp,
it is so designed that the RESET signal is held issued if shifted to the light load mode, with which the switching is tuned
OFF and the switching pulses are thinned out under control. Activating the switching intermittently reduces the switching
dissipation and improves the efficiency.
SENSE
Current
Comp
RESET
VOUT
Level
Shift
R Q
FB
SET
Gm Amp.
ITH
S
IL
Driver
Logic
VOUT
SW
Load
OSC
Fig.21 Diagram of current mode PWM control
PVCC
Current
Comp
SENSE
PVCC
SENSE
Current
Comp
FB
SET
FB
GND
SET
GND
RESET
GND
RESET
GND
SW
GND
SW
IL
GND
IL(AVE)
IL
0A
VOUT
VOUT
VOUT(AVE)
Not switching
Fig.22 PWM switching timing chart
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VOUT(AVE)
Fig.23 SLLMTM switching timing chart
7/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Description of operations
・Soft-start function
EN terminal shifted to “High” activates a soft-starter to gradually establish the output voltage with the current limited during
startup, by which it is possible to prevent an overshoot of output voltage and an inrush current.
・Shutdown function
With EN terminal shifted to “Low”, the device turns to Standby Mode, and all the function blocks including reference
voltage circuit, internal oscillator and drivers are turned to OFF. Circuit current during standby is 0μA (Typ.).
・UVLO function
Detects whether the input voltage sufficient to secure the output voltage of this IC is supplied. And the hysteresis width of
100mV (Typ.) is provided to prevent output chattering.
Hysteresis 50mV
VCC
EN
VOUT
Tss
Tss
Tss
Soft start
Standby mode
Operating mode
UVLO
Standby
mode
Operating mode
UVLO
Standby
mode
EN
Operating mode
Standby mode
UVLO
Fig.24 Soft start, Shutdown, UVLO timing chart
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8/17
2009.09 - Rev.B
Technical Note
BD9134MUV
・Short-current protection circuit with time delay function
Turns OFF the output to protect the IC from breakdown when the incorporated current limiter is activated continuously for
the fixed time(TLATCH) or more. The output thus held tuned OFF may be recovered by restarting EN or by re-unlocking
UVLO.
EN
1msec
VOUT
Output Current in non-control
1/2VOUT
Until output voltage goes up the half of Vo or over,
timer latch is not operated.
(No timer latch, only limit to the output current)
Limit
Output voltage OFF Latch
IL
Output Current in control by limit value
(With fall of the output voltage, limit value goes down)
Standby mode
Operated mode
Operated mode
Standby mode
EN
Timer Latch
EN
Fig.25 Short-current protection circuit with time delay timing chart
●Switching regulator efficiency
Efficiency ŋ may be expressed by the equation shown below:
η=
VOUT×IOUT
Vin×Iin
×100[%]=
POUT
Pin
×100[%]=
POUT
POUT+PDα
×100[%]
Efficiency may be improved by reducing the switching regulator power dissipation factors PDα as follows:
Dissipation factors:
2
1) ON resistance dissipation of inductor and FET:PD(I R)
2) Gate charge/discharge dissipation:PD(Gate)
3) Switching dissipation:PD(SW)
4) ESR dissipation of capacitor:PD(ESR)
5) Operating current dissipation of IC:PD(IC)
2
2
1)PD(I R)=IOUT ×(RCOIL+RON) (RCOIL[Ω]:DC resistance of inductor, RON[Ω]:ON resistance of FET, IOUT[A]:Output
current.)
2)PD(Gate)=Cgs×f×V (Cgs[F]:Gate capacitance of FET、f[H]:Switching frequency、V[V]:Gate driving voltage of FET)
2
Vin ×CRSS×IOUT×f
3)PD(SW)=
(CRSS[F]:Reverse transfer capacitance of FET、IDRIVE[A]:Peak current of gate.)
IDRIVE
2
4)PD(ESR)=IRMS ×ESR (IRMS[A]:Ripple current of capacitor、ESR[Ω]:Equivalent series resistance.)
5)PD(IC)=Vin×ICC (ICC[A]:Circuit current.)
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9/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Consideration on permissible dissipation and heat generation
As this IC functions with high efficiency without significant heat generation in most applications, no special consideration is
needed on permissible dissipation or heat generation. In case of extreme conditions, however, including lower input
voltage, higher output voltage, heavier load, and/or higher temperature, the permissible dissipation and/or heat generation
must be carefully considered.
For dissipation, only conduction losses due to DC resistance of inductor and ON resistance of FET are considered.
Because the conduction losses are considered to play the leading role among other dissipation mentioned above including
gate charge/discharge dissipation and switching dissipation.
Power dissipation:Pd [W]
4.0
①3.56W
① 4 layers (Copper foil area : 5505mm2)
copper foil in each layers.
θj-a=35.1℃/W
② 4 layers (Copper foil area : 10.29m2)
copper foil in each layers.
θj-a=103.3℃/W
2
③ 4 layers (Copper foil area : 10.29m )
θj-a=178.6℃/W
④IC only.
3.0
2.0
②1.21W
1.0 ③0.70W
④0.34W
0
0
25
50
75
100105 125
150
Ambient temperature:Ta [℃]
Fig.26 Thermal derating curve
(VQFN020V4040)
P=IOUT2×RON
RON=D×RONP+(1-D)RONN
D:ON duty (=VOUT/VCC)
RONH:ON resistance of Highside MOS FET
RONL:ON resistance of Lowside MOS FET
IOUT:Output current
If VCC=5V, VOUT=3.3V, RONH=82mΩ, RONL=70mΩ
IOUT=3A, for example,
D=VOUT/VCC=3.3/5.0=0.66
RON=0.66×0.082+(1-0.66)×0.07
=0.05412+0.0238
=0.07792[Ω]
2
P=3 ×0.07792=0.70128[W]
As RONH is greater than RONL in this IC, the dissipation increases as the ON duty becomes greater. With the consideration
on the dissipation as above, thermal design must be carried out with sufficient margin allowed.
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10/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Selection of components externally connected
1. Selection of inductor (L)
IL
The inductance significantly depends on output ripple current.
As seen in the equation (1), the ripple current decreases as the
inductor and/or switching frequency increases.
(VCC-VOUT)×VOUT
[A]・・・(1)
ΔIL=
L×VCC×f
ΔIL
VCC
IL
Appropriate ripple current at output should be 20% more or less of the
maximum output current.
VOUT
L
ΔIL=0.2×IOUTmax. [A]・・・(2)
Co
L=
Fig.27 Output ripple current
(VCC-VOUT)×VOUT
ΔIL×VCC×f
[H]・・・(3)
(ΔIL: Output ripple current, and f: Switching frequency)
*Current exceeding the current rating of the inductor results in magnetic saturation of the inductor, which decreases efficiency.
The inductor must be selected allowing sufficient margin with which the peak current may not exceed its current rating.
If VCC=5.0V, VOUT=3.3V, f=1MHz, ΔIL=0.2×3A=0.6A, for example,(BD9134MUV)
L=
(5-3.3)×3.3
0.6×5×1M
=1.87μ → 2.2[μH]
*Select the inductor of low resistance component (such as DCR and ACR) to minimize dissipation in the inductor for better
efficiency.
2. Selection of output capacitor (CO)
VCC
Output capacitor should be selected with the consideration on the stability region
and the equivalent series resistance required to smooth ripple voltage.
VOUT
L
Output ripple voltage is determined by the equation (4):
ESR
ΔVOUT=ΔIL×ESR [V]・・・(4)
Co
(ΔIL: Output ripple current, ESR: Equivalent series resistance of output capacitor)
Fig.28 Output capacitor
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○
※Rating of the capacitor should be determined allowing sufficient margin against
output voltage. A 22μF to 100μF ceramic capacitor is recommended.
Less ESR allows reduction in output ripple voltage.
11/17
2009.09 - Rev.B
Technical Note
BD9134MUV
3. Selection of input capacitor (Cin)
VCC
Input capacitor to select must be a low ESR capacitor of the capacitance
sufficient to cope with high ripple current to prevent high transient voltage. The
ripple current IRMS is given by the equation (5):
Cin
VOUT
L
IRMS=IOUT×
Co
√VOUT(VCC-VOUT)
VCC
[A]・・・(5)
< Worst case > IRMS(max.)
When Vcc=2×VOUT, IRMS=
IOUT
2
If VCC=5V, VOUT=3.3V, and IOUTmax.=3A, (BD9134MUV)
Fig.29 Input capacitor
IRMS=3×
√3.3(5-3.3)
5
=1.42[ARMS]
A low ESR 22μF/10V ceramic capacitor is recommended to reduce ESR dissipation of input capacitor for better efficiency.
4. Determination of RITH, CITH that works as a phase compensator
As the Current Mode Control is designed to limit a inductor current, a pole (phase lag) appears in the low frequency area due
to a CR filter consisting of a output capacitor and a load resistance, while a zero (phase lead) appears in the high frequency
area due to the output capacitor and its ESR. So, the phases are easily compensated by adding a zero to the power
amplifier output with C and R as described below to cancel a pole at the power amplifier.
fp(Min.)
A
Gain
[dB]
0
fz(ESR)
IOUTMin.
Phase
[deg]
1
2π×RO×CO
1
fz(ESR)=
2π×ESR×CO
fp=
fp(Max.)
IOUTMax.
Pole at power amplifier
When the output current decreases, the load resistance Ro
increases and the pole frequency lowers.
0
-90
fp(Min.)=
1
[Hz]←with lighter load
2π×ROMax.×CO
fp(Max.)=
1
2π×ROMin.×CO
Fig.30 Open loop gain characteristics
A
fz(Amp.)
Gain
[dB]
[Hz] ←with heavier load
Zero at power amplifier
Increasing capacitance of the output capacitor lowers the pole
frequency while the zero frequency does not change. (This
is because when the capacitance is doubled, the capacitor
ESR reduces to half.)
0
0
Phase
[deg]
-90
fz(Amp.)=
1
2π×RITH×CITH
Fig.31 Error amp phase compensation characteristics
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○
12/17
2009.09 - Rev.B
Technical Note
BD9134MUV
Rf
Cin
VCC
PVCC
EN
VOUT
Cf
VCC
CBST
ADJ
ITH
L
GND,PGND
SW
VOUT
RITH
ESR
CITH
CO
RO
Fig.32 Typical application
Stable feedback loop may be achieved by canceling the pole fp (Min.) produced by the output capacitor and the load resistance
with CR zero correction by the error amplifier.
fz(Amp.)= fp(Min.)
1
2π×RITH×CITH
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=
1
2π×ROMax.×CO
13/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●BD9134MUV
Cautions on PC Board layout
Fig.33 Layout diagram
①
②
Lay out the input ceramic capacitor CIN closer to the pins PVCC and PGND, and the output capacitor Co closer to the
pin PGND.
Lay out CITH and RITH between the pins ITH and GND as neat as possible with least necessary wiring.
※
VQFN020V4040 (BD9134MUV) has thermal PAD on the reverse of the package.
The package thermal performance may be enhanced by bonding the PAD to GND plane which take a large area of
PCB.
●Recommended components Lists on above application
Symbol
L
Part
Coil
Value
2.0uH
Manufacturer
Sumida
Series
CDR6D28MNP-2R0NC
2.2uH
Sumida
CDR6D26NP-2R2NC
CIN
Ceramic capacitor
22uF
Murata
GRM32EB11A226KE20
CO
Ceramic capacitor
22uF
Murata
GRM31CB30J226KE18
CITH
Ceramic capacitor
1500pF
Murata
GRM18 Serise
RITH
Resistance
5.1kΩ
Rohm
MCR03 Serise
1000 pF
Murata
GRM18 Serise
10Ω
Rohm
MCR03 Serise
Cf
Ceramic capacitor
Rf
Resistance
*The parts list presented above is an example of recommended parts. Although the parts are sound, actual circuit
characteristics should be checked on your application carefully before use. Be sure to allow sufficient margins to
accommodate variations between external devices and this IC when employing the depicted circuit with other circuit
constants modified. Both static and transient characteristics should be considered in establishing these margins. When
switching noise is substantial and may impact the system, a low pass filter should be inserted between the VCC and PVCC
pins, and a schottky barrier diode or snubber established between the SW and PGND pins.
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14/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●I/O equivalence circuit
・EN pin
PVCC
・SW pin
PVCC
PVCC
EN
SW
・VOUT pin
・ITH pin
VCC
VOUT
ITH
・BST pin
PVCC
PVCC
BST
SW
Fig.34 I/O equivalence circuit
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○
15/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Notes for use
1. Absolute Maximum Ratings
While utmost care is taken to quality control of this product, any application that may exceed some of the absolute
maximum ratings including the voltage applied and the operating temperature range may result in breakage. If broken,
short-mode or open-mode may not be identified. So if it is expected to encounter with special mode that may exceed the
absolute maximum ratings, it is requested to take necessary safety measures physically including insertion of fuses.
2. Electrical potential at GND
GND must be designed to have the lowest electrical potential In any operating conditions.
3. Short-circuiting between terminals, and mismounting
When mounting to pc board, care must be taken to avoid mistake in its orientation and alignment. Failure to do so may
result in IC breakdown. Short-circuiting due to foreign matters entered between output terminals, or between output and
power supply or GND may also cause breakdown.
4. Thermal shutdown protection circuit
Thermal shutdown protection circuit is the circuit designed to isolate the IC from thermal runaway, and not intended to
protect and guarantee the IC. So, the IC the thermal shutdown protection circuit of which is once activated should not be
used thereafter for any operation originally intended.
5. Inspection with the IC set to a pc board
If a capacitor must be connected to the pin of lower impedance during inspection with the IC set to a pc board, the
capacitor must be discharged after each process to avoid stress to the IC. For electrostatic protection, provide proper
grounding to assembling processes with special care taken in handling and storage. When connecting to jigs in the
inspection process, be sure to turn OFF the power supply before it is connected and removed.
6. Input to IC terminals
+
This is a monolithic IC with P isolation between P-substrate and each element as illustrated below. This P-layer and the
N-layer of each element form a P-N junction, and various parasitic element are formed.
If a resistor is joined to a transistor terminal as shown in Fig 35.
○P-N junction works as a parasitic diode if the following relationship is satisfied;
GND>Terminal A (at resistor side), or GND>Terminal B (at transistor side); and
○if GND>Terminal B (at NPN transistor side),
a parasitic NPN transistor is activated by N-layer of other element adjacent to the above-mentioned parasitic diode.
The structure of the IC inevitably forms parasitic elements, the activation of which may cause interference among circuits,
and/or malfunctions contributing to breakdown. It is therefore requested to take care not to use the device in such
manner that the voltage lower than GND (at P-substrate) may be applied to the input terminal, which may result in
activation of parasitic elements.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
E
Pin A
N
P+
N
P+
P
N
Parasitic
element
N
P+
P substrate
Parasitic element
GND
B
N
P+
P
N
C
E
Parasitic
element
P substrate
Parasitic element
GND
GND
GND
Other adjacent elements
Fig.35 Simplified structure of monorisic IC
7. Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
8 . Selection of inductor
It is recommended to use an inductor with a series resistance element (DCR) 0.1Ω or less. Especially, note that use of a
high DCR inductor will cause an inductor loss, resulting in decreased output voltage. Should this condition continue for a
specified period (soft start time + timer latch time), output short circuit protection will be activated and output will be latched
OFF. When using an inductor over 0.1Ω, be careful to ensure adequate margins for variation between external devices
and this IC, including transient as well as static characteristics. Furthermore, in any case, it is recommended to start up the
output with EN after supply voltage is within operation range.
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○
16/17
2009.09 - Rev.B
Technical Note
BD9134MUV
●Ordering part number
B
D
9
Part No.
1
3
4
M
Part No.
U
V
-
Package
MUV: VQFN020V4040
E
2
Packaging and forming specification
E2: Embossed tape and reel
VQFN020V4040
<Tape and Reel information>
4.0±0.1
4.0±0.1
2.1±0.1
0.5
0.4±0.1
1
6
16
1.0
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
5
20
10
15
2500pcs
(0.22)
S
C0.2
Embossed carrier tape
Quantity
11
2.1±0.1
0.08
S
+0.03
0.02 -0.02
1.0MAX
1PIN MARK
Tape
+0.05
0.25 -0.04
1pin
(Unit : mm)
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○
Reel
17/17
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.09 - Rev.B
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
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shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
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The Products are not designed or manufactured to be used with any equipment, device or
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may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
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