FDMD82100 Dual N-Channel Power Trench® MOSFET 100 V, 25 A, 19 mΩ Features General Description Max rDS(on) = 19 mΩ at VGS = 10 V, ID = 7 A This device includes two 100V N-Channel MOSFETs in a dual Power (3.3 mm X 5 mm) package. HS source and LS Drain internally connected for half/full bridge, low source inductance package, low rDS(on)/Qg FOM silicon. Max rDS(on) = 33 mΩ at VGS = 6 V, ID = 5.5 A Ideal for flexible layout in primary side of bridge topology Termination is Lead-free and RoHS Compliant Applications 100% UIL tested Synchronous Buck : Primary Switch of Half / Full bridge converter for telecom Kelvin High Side MOSFET drive pin-out capability Motor Bridge : Primary Switch of Half / Full bridge converter for BLDC motor MV POL : 48V Synchronous Buck Switch Pin 1 D1 1 12 G1 D1 2 11 D1 3 10 D2/S1 G2 4 9 D2/S1 S2 5 8 D2/S1 S2 6 7 D2/S1 G1R Power 3.3 x 5 MOSFET Maximum Ratings TA = 25 °C unless otherwise noted Symbol VDS Drain to Source Voltage Parameter VGS Gate to Source Voltage Drain Current ID -Continuous TC = 25 °C -Continuous TA = 25 °C -Pulsed Single Pulse Avalanche Energy EAS PD TJ, TSTG Ratings 100 Units V ±20 V 25 (Note 1a) 7 (Note 4) 80 (Note 3) 121 Power Dissipation TA = 25 °C (Note 1a) 2.1 Power Dissipation TA = 25 °C (Note 1b) 1 Operating and Storage Junction Temperature Range -55 to +150 A mJ W °C Thermal Characteristics RθJC Thermal Resistance, Junction to Case 3.1 RθJA Thermal Resistance, Junction to Ambient (Note 1a) 60 RθJA Thermal Resistance, Junction to Ambient (Note 1b) 130 °C/W Package Marking and Ordering Information Device Marking 82100 Device FDMD82100 ©2013 Fairchild Semiconductor Corporation FDMD82100 Rev.C1 Package Power 3.3 x 5 1 Reel Size 13 ’’ Tape Width 12 mm Quantity 3000 units www.fairchildsemi.com FDMD82100 Dual N-Channel PowerTrench® MOSFET June 2014 Symbol Parameter Test Conditions Min Typ Max Units Off Characteristics BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V ΔBVDSS ΔTJ Breakdown Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C IDSS Zero Gate Voltage Drain Current VDS = 80 V, VGS = 0 V 1 μA IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA 4 V 100 V 70 mV/°C On Characteristics VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA ΔVGS(th) ΔTJ Gate to Source Threshold Voltage Temperature Coefficient ID = 250 μA, referenced to 25 °C VGS = 10 V, ID = 7 A 15 rDS(on) Static Drain to Source On Resistance VGS = 6 V, ID = 5.5 A 23 33 VGS = 10 V, ID = 7 A, TJ = 125 °C 27 35 VDD = 5 V, ID = 7 A 18 gFS Forward Transconductance 2 3.3 -9 mV/°C 19 mΩ S Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance Rg Gate Resistance VDS = 50 V, VGS = 0 V f = 1 MHz 0.1 805 1070 pF 176 235 pF 8 15 pF 1.8 3.6 Ω 9.4 19 ns 3.2 10 ns 15 27 ns 3.3 10 ns 12 17 nC 8 11 Switching Characteristics td(on) Turn-On Delay Time tr Rise Time td(off) Turn-Off Delay Time tf Fall Time Qg(TOT) VDD = 50 V, ID = 7 A VGS = 10 V, RGEN = 6 Ω Total Gate Charge VGS = 0 V to 10 V Total Gate Charge VGS = 0 V to 6 V Qgs Gate to Source Charge Qgd Gate to Drain “Miller” Charge VDD = 50 V ID = 7 A nC 3.9 nC 2.7 nC Drain-Source Diode Characteristics VSD Source to Drain Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = 7 A (Note 2) IF = 7 A, di/dt = 100 A/μs 0.8 1.2 V 46 74 ns 48 77 nC NOTES: 1. RθJA is determined with the device mounted on a 1 in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RθJC is guaranteed by design while RθCA is determined by the user's board design. b. 130 °C/W when mounted on a minimum pad of 2 oz copper a. 60 °C/W when mounted on a 1 in2 pad of 2 oz copper SS SF DS DF G SS SF DS DF G 2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0 %. 3. EAS of 121 mJ is based on starting TJ = 25 oC, L = 3 mH, IAS = 9 A, VDD = 100 V, VGS = 10 V. 100% tested at L = 0.1 mH, IAS = 30 A. 4. Pulse Id refers to Figure.11 Forward Bias Safe Operation Area. ©2013 Fairchild Semiconductor Corporation FDMD82100 Rev.C1 2 www.fairchildsemi.com FDMD82100 Dual N-Channel PowerTrench® MOSFET Electrical Characteristics TJ = 25 °C unless otherwise noted 4 ID, DRAIN CURRENT (A) VGS = 7 V VGS = 8 V VGS = 10 V NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 80 60 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 40 VGS = 6 V 20 VGS = 5 V 0 0 1 2 3 4 VGS = 5 V 3 VGS = 6 V VGS = 7 V 2 VGS = 8 V 1 0 0 5 20 40 ID, DRAIN CURRENT (A) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 1. On Region Characteristics 80 100 ID = 7 A VGS = 10 V 2.0 rDS(on), DRAIN TO 1.8 1.6 1.4 1.2 1.0 0.8 0.6 -75 SOURCE ON-RESISTANCE (mΩ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 60 Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 2.2 ID = 7 A PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 75 50 TJ = 125 oC 25 TJ = 25 oC 0 -50 4 -25 0 25 50 75 100 125 150 TJ, JUNCTION TEMPERATURE (oC) 5 6 7 8 9 10 VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. Normalized On Resistance vs Junction Temperature Figure 4. On-Resistance vs Gate to Source Voltage 100 IS, REVERSE DRAIN CURRENT (A) 80 PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX ID, DRAIN CURRENT (A) VGS = 10 V PULSE DURATION = 80 μs DUTY CYCLE = 0.5% MAX 60 VDS = 5 V 40 TJ = 150 oC 20 TJ = 25 oC TJ = -55 oC 0 2 4 6 8 10 TJ = 150 oC 1 TJ = 25 oC 0.1 TJ = -55 oC 0.01 0.001 0.0 10 VGS, GATE TO SOURCE VOLTAGE (V) 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics ©2013 Fairchild Semiconductor Corporation FDMD82100 Rev.C1 VGS = 0 V Figure 6. Source to Drain Diode Forward Voltage vs Source Current 3 www.fairchildsemi.com FDMD82100 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 10000 ID = 7 A VDD = 50 V 8 VDD = 25 V VDD = 75 V 6 4 Coss 100 Crss 10 2 0 0 2 4 6 8 10 12 Ciss 1000 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 f = 1 MHz VGS = 0 V 1 0.1 14 1 10 100 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 40 50 ID, DRAIN CURRENT (A) IAS, AVALANCHE CURRENT (A) o RθJC = 3.1 C/W TJ = 25 oC 10 TJ = 100 oC TJ = 150 oC 1 0.001 0.01 0.1 1 10 30 VGS = 10 V 20 Limited by Package VGS = 6 V 10 0 25 100 50 150 10000 P(PK), PEAK TRANSIENT POWER (W) 100 ID, DRAIN CURRENT (A) 125 Figure 10. Maximum Continuous Drain Current vs Case Temperature 200 10 μs THIS AREA IS LIMITED BY rDS(on) 100 μs SINGLE PULSE TJ = MAX RATED o RθJC = 3.1 C/W o TC = 25 C CURVE BENT TO MEASURED DATA 1 10 1 ms 10 ms DC 100 300 VDS, DRAIN to SOURCE VOLTAGE (V) TC = 25 oC 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) Figure 11. Forward Bias Safe Operating Area ©2013 Fairchild Semiconductor Corporation FDMD82100 Rev.C1 SINGLE PULSE RθJC = 3.1 oC/W 1000 10 0.1 0.1 100 o Figure 9. Unclamped Inductive Switching Capability 1 75 TC, CASE TEMPERATURE ( C) tAV, TIME IN AVALANCHE (ms) Figure 12. Single Pulse Maximum Power Dissipation 4 www.fairchildsemi.com FDMD82100 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE 2 DUTY CYCLE-DESCENDING ORDER 1 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 NOTES: ZθJC(t) = r(t) x RθJC RθJC = 3.1 oC/W Peak TJ = PDM x ZθJC(t) + TC Duty Cycle, D = t1 / t2 SINGLE PULSE 0.01 0.005 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 13. Junction-to-Case Transient Thermal Response Curve ©2013 Fairchild Semiconductor Corporation FDMD82100 Rev.C1 5 www.fairchildsemi.com FDMD82100 Dual N-Channel PowerTrench® MOSFET Typical Characteristics TJ = 25 °C unless otherwise noted 0.10 C B 5.10 4.90 2X 6 KEEP-OUT AREA A 1 2.35 0.42 (12X) 0.65 6 1 0.42 0.79 (12X) 3.40 3.20 3.70 PIN#1 INDICATOR 7 1.44 0.72 0.10 C 12 0.26 7 12 0.43 SEE DETAIL 'A' 3.67 4.70 5.10 LAND PATTERN RECOMMENDATION 5.00±0.10 0.10 0.05 4.60±0.10 C A B C 0.72 7 12 R0.15 0.36 0.20 3.30±0.10 1.34±0.10 0.52 0.64 0.44 6 1 (12X) 0.37 (12X) 0.27 0.65 0.53 NOTES: UNLESS OTHERWISE SPECIFIED A) DOES NOT FULLY CONFORM TO JEDEC REGISTRATION, MO-229 DATED 8/2012 B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE BURRS OR MOLD FLASH. MOLD FLASH OR BURRS DOES NOT EXCEED 0.10MM. 0.80 0.70 D) DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994. 0.10 C E) IT IS RECOMMENDED TO HAVE NO TRACES OR VIAS WITHIN THE KEEP OUT AREA. 0.08 C C 0.25 0.15 0.05 0.00 SCALE: 2:1 F) DRAWING FILE NAME: SEATING PLANE MKT-PQFN12BREV1 TRADEMARKS The following includes registered and unregistered trademarks and service marks, owned by Fairchild Semiconductor and/or its global subsidiaries, and is not intended to be an exhaustive list of all such trademarks. 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