ISSI IS61VF25618EC-6.5TQ 128k x36/32 and 256k x18 4mb, ecc, synchronous flow-through sram Datasheet

IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x36/32 and 256K x18 4Mb, ECC, SYNCHRONOUS FLOW-THROUGH
SRAM
OCTOBER 2015
FEATURES
DESCRIPTION

Internal self-timed write cycle

Individual Byte Write Control and Global Write

Clock controlled, registered address, data and
The 4Mb product family features high-speed, low-power
synchronous static RAMs designed to provide burstable,
high-performance memory for communication and
networking applications. The IS61(64)LF/VF12836EC are
organized as 131,072 words by 36bits. The
IS61(64)LF/VF12832EC are organized as 131,072 words by
32bits. The IS61(64)LF/VF25618EC are organized as 262,144
words by 18 bits. Fabricated with ISSI's advanced CMOS
technology, the device integrates a 2-bit burst counter,
high-speed SRAM core, and high-drive capability outputs
into a single monolithic circuit. All synchronous inputs pass
through registers controlled by a positive-edge-triggered
single clock input.
control

Burst sequence control using MODE input

Three chip enable option for simple depth
expansion and address pipelining

Common data inputs and data outputs

Auto Power-down during deselect

Single cycle deselect

Snooze MODE for reduced-power standby

JEDEC 100-pin QFP, 165-ball BGA and 119-ball
Write cycles are internally self-timed and are initiated by
the rising edge of the clock input. Write cycles can be one
to four bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
The byte write operation is performed by using the byte
write enable (/BWE) input combined with one or more
individual byte write signals (/BWx). In addition, Global
Write (/GW) is available for writing all bytes at one time,
regardless of the byte write controls.
BGA packages

Power supply:

LF: VDD 3.3V (± 5%), VDDQ 3.3V/2.5V (± 5%)

VF: VDD 2.5V (± 5%), VDDQ 2.5V (± 5%)

JTAG Boundary Scan for BGA packages

Industrial and Automotive temperature support

Lead-free available

Error Detection and Error Correction
Bursts can be initiated with either /ADSP (Address Status
Processor) or /ADSC (Address Status Cache Controller)
input pins. Subsequent burst addresses can be generated
internally and controlled by the /ADV (burst address
advance) input pin.
The mode pin is used to select the burst sequence order.
Linear burst is achieved when this pin is tied LOW.
Interleave burst is achieved when this pin is tied HIGH or
left floating.
FAST ACCESS TIME
Symbol
tKQ
tKC
Parameter
-6.5
-7.5
Units
Clock Access Time
Cycle time
Frequency
6.5
7.5
133
7.5
8.5
117
ns
ns
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to
obtain the latest version of this device specification before relying on any published information and before placing orders for products.
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:
a.) the risk of injury or damage has been minimized;
b.) the user assume all such risks; and
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
1
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
BLOCK DIAGRAM
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
2
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
PIN CONFIGURATION
128K x 36, 165-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
NC
NC
DQPc
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
DQPd
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
/BWc
/BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/BWb
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
7
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
10
11
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
DQPb
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
DQPa
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired
PIN DESCRIPTIONS
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Synchronous Address Status Processor
/ADSC
Synchronous Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Synchronous Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Synchronous Global Write Enable
/OE
Asynchronous Output Enable
DQx
Synchronous Data Inputs/Outputs
DQPx
Synchronous Parity Data I/O
TCK,TDI,TDO,TMS
JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
3
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 32, 165-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
7
8
9
10
11
NC
NC
NC
DQc
DQc
DQc
DQc
NC
DQd
DQd
DQd
DQd
NC
NC
MODE
A
A
NC
DQc
DQc
DQc
DQc
VSS
DQd
DQd
DQd
DQd
NC
NC
NC
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
/BWc
/BWd
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/BWb
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
A
A
NC
DQb
DQb
DQb
DQb
NC
DQa
DQa
DQa
DQa
NC
A
A
NC
NC
NC
DQb
DQb
DQb
DQb
ZZ
DQa
DQa
DQa
DQa
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Synchronous Address Status Processor
/ADSC
Synchronous Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Synchronous Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Synchronous Global Write Enable
/OE
Asynchronous Output Enable
DQx
Synchronous Data Inputs/Outputs
TCK,TDI,TDO,TMS
JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
4
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
256K x 18, 165-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
1
2
3
4
5
6
NC
NC
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQPb
NC
MODE
A
A
NC
DQb
DQb
DQb
DQb
VSS
NC
NC
NC
NC
NC
NC
NC
/CE
CE2
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
/BWb
NC
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
NC
/BWa
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDI
TMS
/CE2
CLK
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
A1*
A0*
7
/BWE
/GW
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
NC
TDO
TCK
8
/ADSC
/OE
VSS
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VSS
A
A
9
10
11
/ADV
/ADSP
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
NC
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
A
A
A
A
NC
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
NC
A
A
A
NC
DQPa
DQa
DQa
DQa
DQa
ZZ
NC
NC
NC
NC
NC
NC
A
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Bottom View
165-Ball, 13 mm x 15mm BGA
11 x 15 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Synchronous Address Status Processor
/ADSC
Synchronous Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Synchronous Byte Write Enable
/BWx (x=a-b)
Synchronous Byte Write Inputs
/GW
Synchronous Global Write Enable
/OE
Asynchronous Output Enable
DQx
Synchronous Data Inputs/Outputs
DQPx
Synchronous Parity Data I/O
TCK,TDI,TDO,TMS
JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
5
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 36, 119-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
VDDQ
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
A
CE2
A
DQPc
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
DQPd
A
NC
TMS
A
A
A
VSS
VSS
VSS
/BWc
VSS
NC
VSS
/BWd
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
A
TCK
5
6
7
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
A
/CE2
A
DQPb
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
DQPa
A
NC
NC
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
Bottom View
119-Ball, 14 mm x 22 mm BGA
7 x 17 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
Symbol
PIN DESCRIPTIONS
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Synchronous Address Status Processor
/ADSC
Synchronous Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Synchronous Byte Write Enable
/BWx (x=a-d)
Synchronous Byte Write Inputs
/GW
Synchronous Global Write Enable
/OE
Asynchronous Output Enable
DQx
Synchronous Data Inputs/Outputs
DQPx
Synchronous Parity Data I/O
TCK,TDI,TDO,TMS
JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
6
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
128K x 32, 119-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
VDDQ
NC
NC
DQc
DQc
VDDQ
DQc
DQc
VDDQ
DQd
DQd
VDDQ
DQd
DQd
NC
NC
VDDQ
A
CE2
A
NC
DQc
DQc
DQc
DQc
VDD
DQd
DQd
DQd
DQd
NC
A
NC
TMS
A
A
A
VSS
VSS
VSS
/BWc
VSS
NC
VSS
/BWd
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
A
TCK
5
6
7
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
A
/CE2
A
NC
DQb
DQb
DQb
DQb
VDD
DQa
DQa
DQa
DQa
NC
A
NC
NC
VDDQ
NC
NC
DQb
DQb
VDDQ
DQb
DQb
VDDQ
DQa
DQa
VDDQ
DQa
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Bottom View
119-Ball, 14 mm x 22 mm BGA
7 x 17 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Synchronous Address Status Processor
/ADSC
Synchronous Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Synchronous Byte Write Enable
/BWx (x=a-b)
Synchronous Byte Write Inputs
/GW
Synchronous Global Write Enable
/OE
Asynchronous Output Enable
DQx
Synchronous Data Inputs/Outputs
TCK,TDI,TDO,TMS
JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
7
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
256K x 18, 119-Ball BGA (Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
1
2
3
VDDQ
NC
NC
DQb
NC
VDDQ
NC
DQb
VDDQ
NC
DQb
VDDQ
DQb
NC
NC
NC
VDDQ
A
CE2
A
NC
DQb
NC
DQb
NC
VDD
DQb
NC
DQb
NC
DQPb
A
A
TMS
A
A
A
VSS
VSS
VSS
/BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
TDI
4
/ADSP
/ADSC
VDD
NC
/CE
/OE
/ADV
/GW
VDD
CLK
NC
/BWE
A1*
A0*
VDD
NC
TCK
5
6
7
A
A
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
/BWa
VSS
VSS
VSS
NC
A
TDO
A
/CE2
A
DQPa
NC
DQa
NC
DQa
VDD
NC
DQa
NC
DQa
NC
A
A
NC
VDDQ
NC
NC
NC
DQa
VDDQ
DQa
NC
VDDQ
DQa
NC
VDDQ
NC
DQa
NC
ZZ
VDDQ
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Bottom View
119-Ball, 14 mm x 22 mm BGA
7 x 17 Ball Array
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
Symbol
Pin Name
CLK
Synchronous Clock
A0,A1
Synchronous Burst Address Inputs
A
Synchronous Address Inputs
/ADV
Synchronous Burst Address Advance
/ADSP
Synchronous Address Status Processor
/ADSC
Synchronous Address Status Controller
MODE
Burst Sequence Selection
/CE,CE2,/CE2
Synchronous Chip Enable
/BWE
Synchronous Byte Write Enable
/BWx (x=a-b)
Synchronous Byte Write Inputs
/GW
Synchronous Global Write Enable
/OE
Asynchronous Output Enable
DQx
Synchronous Data Inputs/Outputs
DQPx
Synchronous Parity Data I/O
TCK,TDI,TDO,TMS
JTAG Pins
ZZ
Asynchronous Power Sleep Mode
NC
No Connect
VDD
Power Supply
VDDQ
I/O Power Supply
VSS
Ground
8
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
/CE
CE2
/BWd
/BWc
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
128K x 36, 100PIN QFP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
128K x 36
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQPb
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
DQPa
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQPc
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
DQPd
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
Pin Name
CLK
Synchronous Clock
/GW
Synchronous Global Write Enable
A0,A1
Synchronous Burst Address Inputs
/OE
Asynchronous Output Enable
A
Synchronous Address Inputs
DQx
Synchronous Data Inputs/Outputs
/ADV
Synchronous Burst Address Advance
DQPx
Synchronous Parity Data I/O
/ADSP
Synchronous Address Status Processor
ZZ
Asynchronous Power Sleep Mode
/ADSC
Synchronous Address Status Controller
NC
No Connect
MODE
Burst Sequence Selection
VDD
Power Supply
/CE,CE2,/CE2
Synchronous Chip Enable
VDDQ
I/O Power Supply
/BWE
Synchronous Byte Write Enable
VSS
Ground
/BWx (x=a-d)
Synchronous Byte Write Inputs
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
9
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
/CE
CE2
/BWd
/BWc
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
128K x 32, 100PIN QFP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
128K x 32
NC
DQb
DQb
VDDQ
VSS
DQb
DQb
DQb
DQb
VSS
VDDQ
DQb
DQb
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
DQa
DQa
VSS
VDDQ
DQa
DQa
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
DQc
DQc
VDDQ
VSS
DQc
DQc
DQc
DQc
VSS
VDDQ
DQc
DQc
NC
VDD
NC
VSS
DQd
DQd
VDDQ
VSS
DQd
DQd
DQd
DQd
VSS
VDDQ
DQd
DQd
NC
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
Pin Name
CLK
Synchronous Clock
/BWx (x=a-d)
Synchronous Byte Write Inputs
A0,A1
Synchronous Burst Address Inputs
/GW
Synchronous Global Write Enable
A
Synchronous Address Inputs
/OE
Asynchronous Output Enable
/ADV
Synchronous Burst Address Advance
DQx
Synchronous Data Inputs/Outputs
/ADSP
Synchronous Address Status Processor
ZZ
Asynchronous Power Sleep Mode
/ADSC
Synchronous Address Status Controller
NC
No Connect
MODE
Burst Sequence Selection
VDD
Power Supply
/CE,CE2,/CE2
Synchronous Chip Enable
VDDQ
I/O Power Supply
/BWE
Synchronous Byte Write Enable
VSS
Ground
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
10
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
/CE
CE2
NC
NC
/BWb
/BWa
/CE2
VDD
VSS
CLK
/GW
/BWE
/OE
/ADSC
/ADSP
/ADV
A
A
256K x 18, 100PIN QFP (Top View)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
256K x 18
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A
NC
NC
VDDQ
VSS
NC
DQPa
DQa
DQa
VSS
VDDQ
DQa
DQa
VSS
NC
VDD
ZZ
DQa
DQa
VDDQ
VSS
DQa
DQa
NC
NC
VSS
VDDQ
NC
NC
NC
MODE
A
A
A
A
A1
A0
NC
NC
VSS
VDD
NC
NC
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
NC
NC
NC
VDDQ
VSS
NC
NC
DQb
DQb
VSS
VDDQ
DQb
DQb
NC
VDD
NC
VSS
DQb
DQb
VDDQ
VSS
DQb
DQb
DQPb
NC
VSS
VDDQ
NC
NC
NC
Note: A0 and A1 are the two least significant bits (LSB) of the address field and set the internal burst counter if burst is desired.
PIN DESCRIPTIONS
Symbol
Pin Name
Symbol
Pin Name
CLK
Synchronous Clock
/GW
Synchronous Global Write Enable
A0,A1
Synchronous Burst Address Inputs
/OE
Asynchronous Output Enable
A
Synchronous Address Inputs
DQx
Synchronous Data Inputs/Outputs
/ADV
Synchronous Burst Address Advance
DQPx
Synchronous Parity Data I/O
/ADSP
Synchronous Address Status Processor
ZZ
Asynchronous Power Sleep Mode
/ADSC
Synchronous Address Status Controller
NC
No Connect
MODE
Burst Sequence Selection
VDD
Power Supply
/CE,CE2,/CE2
Synchronous Chip Enable
VDDQ
I/O Power Supply
/BWE
Synchronous Byte Write Enable
VSS
Ground
/BWx (x=a-b)
Synchronous Byte Write Inputs
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
11
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
TRUTH TABLE
SYNCHRONOUS TRUTH TABLE
OPERATION
ADDRESS
/CE
/CE2
CE2
ZZ
ADSP
ADSC
ADV
WRITE
/OE
CLK
DQ
Deselect Cycle, Power-Down
None
H
X
X
L
X
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
L
X
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
X
L
L
H
L
X
X
X
L-H
High-Z
Deselect Cycle, Power-Down
None
L
H
X
L
H
L
X
X
X
L-H
High-Z
Snooze Mode, Power-Down
None
X
X
X
H
X
X
X
X
X
X
High-Z
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
L
X
X
X
H
L-H
High-Z
Write Cycle, Begin Burst
External
L
L
H
L
H
L
X
L
X
L-H
D
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
L
L-H
Q
Read Cycle, Begin Burst
External
L
L
H
L
H
L
X
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
X
X
X
L
H
H
L
H
H
L-H
High-Z
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
L
L-H
Q
Read Cycle, Continue Burst
Next
H
X
X
L
X
H
L
H
H
L-H
High-Z
Write Cycle, Continue Burst
Next
X
X
X
L
H
H
L
L
X
L-H
D
Write Cycle, Continue Burst
Next
H
X
X
L
X
H
L
L
X
L-H
D
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
H
H
L-H
High-Z
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
L
L-H
Q
Read Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
H
H
L-H
High-Z
Write Cycle, Suspend Burst
Current
X
X
X
L
H
H
H
L
X
L-H
D
Write Cycle, Suspend Burst
Current
H
X
X
L
X
H
H
L
X
L-H
D
NOTE:
1. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
2. For WRITE, L means one or more byte write enable signals (/BWa-d) and /BWE are LOW or /GW is LOW. /WRITE = H for all /BWx, /BWE, /GW HIGH.
3. /BWa enables WRITEs to DQa’s and DQPa. /BWb enables WRITEs to DQb’s and DQPb. /BWc enables WRITEs to DQc’s and DQPc. /BWd enables
WRITEs to DQd’s and DQPd. DQPa and DQPb are available on the x18 version. DQPa-DQPd are available on the x36 version.
4. All inputs except /OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, /OE must be HIGH before the input data setup time and held HIGH during the input data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. /ADSP LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals and
/BWE LOW or /GW LOW for the subsequent L-H edge of CLK. See WRITE timing diagram for clarification.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
12
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
PARTIAL TRUTH TABLE
Operation
/GW
/BWE
/BWa
/BWb
/BWc
/BWd
READ
READ
H
H
H
L
X
H
X
H
X
H
X
H
WRITE BYTE a
WRITE BYTE b
H
H
L
L
L
H
H
L
H
H
H
H
WRITE BYTE c
WRITE BYTE d
H
H
L
L
H
H
H
H
L
H
H
L
WRITE ALL BYTEs
WRITE ALL BYTEs
H
L
L
X
L
X
L
X
L
X
L
X
Notes:
1.
X means "Don't Care".
2.
All inputs in this table must beet setup and hold time around the rising edge of CLK.
ADDRESS SEQUENCE IN BURST MODE
INTERLEAVED BURST ADDRESS TABLE (MODE = Vdd or NC)
External Address
A1 A0
00
01
10
11
1st Burst Address
A1 A0
01
00
11
10
2nd Burst Address
A1 A0
10
11
00
01
3rd Burst Address
A1 A0
11
10
01
00
LINEAR BURST ADDRESS TABLE (MODE = Vss )
0,0
A1', A0' = 1,1
0,1
1,0
Power Up Sequence
Vddq → Vdd1 → I/O Pins2
Notes:
1. Vdd can be applied at the same time as Vddq
2. Applying I/O inputs is recommended after Vddq is stable. The inputs of the I/O pins can be applied at the same time as Vddq as long as Vih (level of I/O
pins) is lower than Vddq.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
13
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
ERROR DETECTION AND CORRECTION




Independent ECC with Hamming code for each byte.
Detect and correct one bit error per byte.
Better reliability than parity code schemes that could detect error bit but NOT correct it.
Backward compatible : Drop in replacement to current in industry standard devices without ECC.
ABSOLUTE MAXIMUM RATINGS AND OPERATING RANGE
ABSOLUTE MAXIMUM RATINGS
Symbol
TSTG
PD
IOUT
VIN, VOUT
VDD
Parameter
Storage Temperature
Power Dissipation
Output Current (per I/O)
Voltage Relative to Vss for I/O Pins
Voltage Relative to Vss for Address and Control
Inputs
LF Value
–65 to +150
1.6
100
–0.5 to VDDQ+0.5
–0.5 to VDD+0.5
VF Value
–65 to +150
1.6
100
–0.3 to VDDQ + 0.3
–0.3 to VDD + 0.3
Unit
°C
W
mA
V
V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. This device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to
avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Option
IS61LFXXXXX
IS61VFXXXXX
IS64LFXXXXX
IS64VFXXXXX
Range
Commercial
Industrial
Commercial
Industrial
Automotive
Automotive
VDD
3.3V ± 5%
3.3V ± 5%
2.5V ± 5%
2.5V ± 5%
3.3V ± 5%
2.5V ± 5%
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
VDDQ
3.3V / 2.5V ± 5%
3.3V / 2.5V ± 5%
2.5V ± 5%
2.5V ± 5%
3.3V / 2.5V ± 5%
2.5V ± 5%
Ambient Temperature
0°C to +70°C
-40°C to +85°C
0°C to +70°C
-40°C to +85°C
-40°C to +125°C
-40°C to +125°C
14
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS (Over operating temperature range)
Symbol
Parameter
Test Conditions
Voh
Output HIGH Voltage
Vol
Output LOW Voltage
Vih
Vil
Ili
Ilo
Input HIGH Voltage
Input LOW Voltage
Input Leakage Current
Output Leakage Current
Ioh=-4.0 mA(3.3V)
Ioh=–1.0 mA(2.5V)
Iol=8.0 mA(3.3V)
Iol=1.0 mA(2.5V)
Vss≤Vin≤Vdd
Vss≤Vout≤Vddq,/OE=Vih
3.3V
2.5V
Unit
Min.
2.4
Max.
—
Min.
2.0
Max.
—
V
—
0.4
—
0.4
V
2.0
–0.3
–5
–5
Vdd+0.3
0.8
5
5
1.7
–0.3
–5
–5
Vdd+0.3
0.7
5
5
V
V
μA
μA
Notes:
1. All voltages referenced to ground.
2. Overshoot:
3.3V and 2.5V: Vih (AC) ≤ Vdd + 1.5V (Pulse width less than tkc /2)
1.8V: Vih (AC) ≤ Vdd + 0.5V (Pulse width less than tkc /2)
3. Undershoot:
3.3V and 2.5V: Vil (AC) ≥ -1.5V (Pulse width less than tkc /2)
1.8V: Vil (AC) ≥ -0.5V (Pulse width less than tkc /2)
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
Test Conditions
Icc
AC Operating,
Supply Current
Device Selected, OE = Vih, ZZ ≤ Vil,All Inputs
≤ 0.2V or ≥ Vdd – 0.2V,Cycle Time ≥ tkc min.
Isb
Standby Current
TTL Input
Device Deselected,Vdd = Max.,All Inputs ≤ Vil
or ≥ Vih,ZZ ≤ Vil, f = Max.
Standby Current
CMOS Input
Device Deselected,Vdd = Max.,Vin ≤ Vss +
0.2V or ≥Vdd – 0.2V,f = 0
Isb1
Temp.
range
-6.5
-7.5
Com.
Ind.
Auto
Com.
x18
175
180
190
100
MAX
x36/32
175
180
190
100
x18
155
160
175
100
MAX
x36/32
155
160
175
100
Ind.
Auto
Com.
Ind.
Auto
110
130
80
85
100
110
130
80
85
100
110
130
80
85
100
110
130
80
85
100
Unit
mA
mA
mA
Note:
1. MODE pin has an internal pullup and should be tied to Vdd or Vss . It exhibits ±100μA maximum leakage current when tied to ≤Vss+0.2V or ≥Vdd–0.2V.
CAPACITANCE
Symbol
Cin
Cout
Parameter
Input Capacitance
Input/Output Capacitance
Conditions
Vin = 0V
Vout = 0V
Max.
6
8
Unit
pF
pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: Ta = 25°C, f = 1 MHz, Vdd = 3.3V.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
15
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol
Parameter
fMAX
tKC
tKH
tKL
tKQ
tKQX(2)
tKQLZ(2,3)
tKQHZ(2,3)
tOEQ
tOELZ(2,3)
tOEHZ(2,3)
tAS
tSS
tWS
tCES
tSE
tADVS
tDS
tAH
tSH
tHE
tWH
tCEH
tADVH
tDH
tPOWER(4)
Clock Frequency
Cycle Time
Clock High Time
Clock Low Time
Clock Access Time
Clock High to Output Invalid
Clock High to Output Low-Z
Clock High to Output High-Z
Output Enable to Output Valid
Output Enable to Output Low-Z
Output Disable to Output High-Z
Address Setup Time
Address Status Setup Time
Read/Write Setup Time
Chip Enable Setup Time
Clock Enable Setup Time
Address Advance Setup Time
Data Setup Time
Address Hold Time
Address Status Hold Time
Clock Enable Hold Time
Write Hold Time
Chip Enable Hold Time
Address Advance Hold Time
Data Hold Time
VDD (typical) to First Access
-6.5
Min.
—
7.5
2.2
2.2
—
2.5
2.5
—
—
0
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
-7.5
Max.
133
—
—
—
6.5
—
—
3.8
3.2
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Min.
—
8.5
2.5
2.5
—
2.5
2.5
—
—
0
—
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
1
Unit
Max.
117
—
—
—
7.5
—
—
4.0
3.4
—
3.5
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Notes:
1. Configuration signal MODE is static and must not change during normal operation.
2. Guaranteed but not 100% tested. This parameter is periodically sampled.
3. Tested with load in Figure 2.
4. tPOWER is the time that the power needs to be supplied above VDD (min) initially before READ or WRITE operation can be initiated.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
16
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
3.3V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
VTT
VLOAD
R1, R2
Output Load
Unit
0V to 3.0V
1.5 ns
1.5V
1.5V
3.3V
317Ω, 351Ω
See Figures 1 and 2
2.5V I/O AC TEST CONDITIONS
Parameter
Input Pulse Level
Input Rise and Fall Times
Input and Output Timing and Reference Level
VTT
VLOAD
R1, R2
Output Load
Unit
0V to 2.5V
1.5 ns
1.25V
1.25V
2.5V
1667Ω, 1538Ω
See Figures 1 and 2
I/O OUTPUT LOAD EQUIVALENT
R1
VLOAD
OUTPUT
ZO =50Ω
OUTPUT
50Ω
R2
5 pF
Including
jig and
scope
VTT
Figure1
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
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Figure2
17
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
READ/WRITE CYCLE TIMING
tKC
CLK
tKH
tSS
tSH
/ADSP is blocked by /CE inactive
tKL
/ADSP
tSS
tSH
/ADSC
/ADV
tAS
tAH
Address
RD1
WR1
tWS
tWH
tWS
tWH
RD2
RD3
/GW
/BWE
tWH
tWS
WR1
/BWd-/BWa
tCES
tCEH
tCES
tCEH
tCES
tCEH
/CE Masks /ADSP
/CE
CE2 and /CE2 only sampled with /ADSP or /ADSC
CE2
Unselected with /CE2
/CE2
tOELZ
tOEQ
/OE
tOEHZ
tKQX
DATAOUT
High-Z
tKQLZ
High-Z
tKQLZ
tKQ
1a
tKQ
DATAIN
2a
2b
tKQX
2c
2d
tKQHZ
1a
High-Z
Single Read
Flow-through
tDH
tDS
Single Write
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Burst Read
Unselected
18
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
WRITE CYCLE TIMING
tKC
CLK
tSS
tKH
tSH
/ADSP is blocked by /CE inactive
tKL
/ADSP
/ADSC initiates Write
/ADSC
/ADV must be inactive for /ADSP Write
tAVS
tAVH
/ADV
tAS
Address
tAH
WR1
WR2
tWS
tWH
tWS
tWH
tWS
tWH
WR3
/GW
/BWE
/BWx
tWS
WR1
tCES
tCEH
tCES
tCEH
tCES
tCEH
tWH
WR2
WR3
/CE Masks /ADSP
/CE
Unselected with CE2
CE2 and /CE2 only sampled with /ADSP or/ ADSC
CE2
/CE2
/OE
DATAOUT
High-Z
tDS
DATAIN
High-Z
tDH
1a
Single Write
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/BW1-/BW4 only are applied to first cycle of WR2
2a
2b
Burst Write
2c
2d
3a
Write
Unselected
19
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol
Parameter
Isb2
Current during SNOOZE MODE
tpds
tpus
tzzi
trzzi
Conditions
ZZ ≥ Vih
ZZ active to input ignored
ZZ inactive to input sampled
ZZ active to SNOOZE current
ZZ inactive to exit SNOOZE current
Temperature Range
Com.
Ind.
Auto.
—
—
—
—
Min.
—
—
—
—
2
—
0
Max.
35
40
60
2
—
2
—
Unit
mA
cycle
cycle
cycle
ns
SLEEP MODE TIMING
CLK
tPDS
ZZ setup cycle
tPUS
ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2
tRZZI
All Inputs
(except ZZ)
Deselect or Read Only
Deselect or Read Only
Normal
operation
cycle
Outputs (Q)
High-Z
Don't Care
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IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
IEEE 1149.1 TAP and Boundary Scan
The SRAM provides a limited set of JTAG functions to test the interconnection between SRAM I/Os and printed
circuit board traces or other components. There is no multiplexer in the path from I/O pins to the RAM core.
In conformance with IEEE Standard 1149.1, the SRAM contains a TAP controller, instruction register, boundary
scan register, bypass register, and ID register.
The TAP controller has a standard 16-state machine that resets internally on power-up. Therefore, a TRST signal
is not required
Disabling the JTAG feature
The SRAM can operate without using the JTAG feature. To disable the TAP controller, TCK must be tied LOW
(VSS) to prevent clocking of the device. TDI and TMS are internally pulled up and may be left disconnected. They
may alternately be connected to VDD through a pull-up resistor. TDO should be left disconnected. On power-up,
the device will come up in a reset state, which will not interfere with device operation.
Test Access Port Signal List:
1. Test Clock (TCK)
This signal uses VDD as a power supply. The test clock is used only with the TAP controller. All inputs are
captured on the rising edge of TCK. All outputs are driven from the falling edge of TCK.
2. Test Mode Select (TMS)
This signal uses VDD as a power supply. The TMS input is used to send commands to the TAP controller and is
sampled on the rising edge of TCK.
3. Test Data-In (TDI)
This signal uses VDD as a power supply. The TDI input is used to serially input test instructions and information
into the registers and can be connected to the input of any of the registers. The register between TDI and TDO is
chosen by the instruction that is loaded into the TAP instruction register. TDI is connected to the most significant
bit (MSB) of any register. For more information regarding instruction register loading, please see the TAP
Controller State Diagram.
4. Test Data-Out (TDO)
This signal uses VDDQ as a power supply. The TDO output ball is used to serially clock test instructions and data
out from the registers. The TDO output driver is only active during the Shift-IR and Shift-DR TAP controller states.
In all other states, the TDO pin is in a High-Z state. The output changes on the falling edge of TCK. TDO is
connected to the least significant bit (LSB) of any register. For more information, please see the TAP Controller
State Diagram.
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IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
TAP Controller State and Block Diagram
...
Boundary Scan Register (75 bits)
TDI
Bypass Register (1 bit)
Identification Register (32 bits)
TDO
Instruction Register (3 bits)
Control Signals
TMS
TAP Controller
TCK
TAP Controller State Machine
1
Test Logic
Reset
0
Run Test
Idle
1
Select DR
1
Select IR
0
1
0
0
1
1
Capture
DR
0
Capture
IR
0
0
Shift DR
1
1
1
1
Exit1 DR
Exit1 IR
0
0
0
Pause DR
1
Exit2 DR
0
Exit2 IR
1
0
1
Update
DR
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0
Pause IR
1
1
0
Shift IR
Update IR
0
1
0
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IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Performing a TAP Reset
A Reset is performed by forcing TMS HIGH (VDD) for five rising edges of TCK. RESET may be performed while
the SRAM is operating and does not affect its operation. At power-up, the TAP is internally reset to ensure that
TDO comes up in a high-Z state.
TAP Registers
Registers are connected between the TDI and TDO pins and allow data to be scanned into and out of the SRAM
test circuitry. Only one register can be selected at a time through the instruction registers. Data is serially loaded
into the TDI pin on the rising edge of TCK and output on the TDO pin on the falling edge of TCK.
1. Instruction Register
This register is loaded during the update-IR state of the TAP controller. At power-up, the instruction register is
loaded with the IDCODE instruction. It is also loaded with the IDCODE instruction if the controller is placed in a
reset state as described in the previous section. When the TAP controller is in the capture-IR state, the two LSBs
are loaded with a binary “01” pattern to allow for fault isolation of the board-level serial test data path.
2. Bypass Register
The bypass register is a single-bit register that can be placed between the TDI and TDO balls. This allows data to
be shifted through the SRAM with minimal delay. The bypass register is set LOW (VSS) when the BYPASS
instruction is executed.
3. Boundary Scan Register
The boundary scan register is connected to all the input and bidirectional balls on the SRAM. Several balls are
also included in the scan register to reserved balls. The boundary scan register is loaded with the contents of the
SRAM Input and Output ring when the TAP controller is in the capture-DR state and is then placed between the
TDI and TDO balls when the controller is moved to the shift-DR state. Each bit corresponds to one of the balls on
the SRAM package. The MSB of the register is connected to TDI, and the LSB is connected to TDO.
4. Identification (ID) Register
The ID register is loaded with a vendor-specific, 32-bit code during the capture-DR state when the IDCODE
command is loaded in the instruction register. The IDCODE is hardwired into the SRAM and can be shifted out
when the TAP controller is in the shift-DR state.
Scan Register Sizes
Register Name
Instruction
Bypass
ID
Boundary Scan
Bit Size
3
1
32
75
TAP Instruction Set
Many instructions are possible with an eight-bit instruction register and all valid combinations are listed in the TAP
Instruction Code Table. All other instruction codes that are not listed on this table are reserved and should not be
used. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is
placed between TDI and TDO. During this state, instructions are shifted from the instruction register through the
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IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
TDI and TDO pins. To execute an instruction once it is shifted in, the TAP controller must be moved into the
Update-IR state.
1. EXTEST
The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register
cells at output balls are used to apply a test vector, while those at input balls capture test results. Typically, the first
test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the
PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output driver is turned on, and the
PRELOAD data is driven onto the output balls.
2. IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. It also
places the instruction register between the TDI and TDO balls and allows the IDCODE to be shifted out of the
device when the TAP controller enters the shift-DR state. The IDCODE instruction is loaded into the instruction
register upon power-up or whenever the TAP controller is given a test logic reset state.
3. SAMPLE Z
If the SAMPLE-Z instruction is loaded in the instruction register, all SRAM outputs are forced to an inactive drive
state (high-Z), moving the TAP controller into the capture-DR state loads the data in the SRAMs input into the
boundary scan register, and the boundary scan register is connected between TDI and TDO when the TAP
controller is moved to the shift-DR state.
4. SAMPLE/PRELOAD
When the SAMPLE/PRELOAD instruction is loaded into the instruction register and the TAP controller is in the
capture-DR state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register.
The user must be aware that the TAP controller clock can only operate at a frequency up to 50 MHz, while the
SRAM clock operates significantly faster. Because there is a large difference between the clock frequencies, it is
possible that during the capture-DR state, an input or output will undergo a transition. The TAP may then try to
capture a signal while in transition. This will not harm the device, but there is no guarantee as to the value that will
be captured. Repeatable results may not be possible. To ensure that the boundary scan register will capture the
correct value of a signal, the SRAM signal must be stabilized long enough to meet the TAP controller’s capture
setup plus hold time. The SRAM clock input might not be captured correctly if there is no way in a design to stop
(or slow) the clock during a SAMPLE/ PRELOAD instruction. If this is an issue, it is still possible to capture all other
signals and simply ignore the value of the CK and CK# captured in the boundary scan register. Once the data is
captured, it is possible to shift out the data by putting the TAP into the shift-DR state. This places the boundary
scan register between the TDI and TDO balls.
6. BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP is placed in a shift-DR state, the
bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens the
boundary scan path when multiple devices are connected together on a board.
7. PRIVATE
Do not use these instructions. They are reserved for future use and engineering mode.
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IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
JTAG TAP DC ELECTRICAL CHARACTERISTICS (VDDQ=3.3V Operating Range)
Parameter
Symbol
Min
Max
Units
JTAG Input High Voltage
VIH1
2.0
VDD+0.3
V
JTAG Input Low Voltage
VIL1
–0.3
0.8
V
JTAG Output High Voltage
VOH1
2.4
V
JTAG Output Low Voltage
VOL1
0.4
V
JTAG Output High Voltage
VOH2
2.9
V
JTAG Output Low Voltage
VOL2
0.2
V
JTAG Input Load Current
-10
+10
uA
IX
Notes
|IOH1|=2mA
IOL1=2mA
|IOH2|=100uA
IOL2=100uA
0 ≤ Vin ≤ VDD
Notes:
1.
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG TAP DC ELECTRICAL CHARACTERISTICS (VDDQ=2.5V Operating Range)
Parameter
Symbol
Min
Max
Units
JTAG Input High Voltage
VIH1
1.7
VDD+0.3
V
JTAG Input Low Voltage
VIL1
–0.3
0.7
V
JTAG Output High Voltage
VOH1
2.0
V
JTAG Output Low Voltage
VOL1
0.4
V
JTAG Output High Voltage
VOH2
2.1
V
JTAG Output Low Voltage
VOL2
0.2
V
JTAG Input Load Current
-10
+10
uA
IX
Notes
|IOH1|=2mA
IOL1=2mA
|IOH2|=100uA
IOL2=100uA
0 ≤ Vin ≤ VDD
Notes:
2.
All voltages referenced to VSS (GND); All JTAG inputs and outputs are LVTTL-compatible.
JTAG AC Test Conditions
(Over the Operating Temperature Range)
Parameter
Input Pulse High Level
Input Pulse Low Level
Input rise and fall time
Test load termination supply voltage
Input and Output Timing Reference Level
Symbol
VIH1
VIL1
TR1
VREF
VREF
2.5V Option
2.5
0
1.5
1.25
1.25
3.3V Option
3.0
0
1.5
1.5
1.5
Units
V
V
ns
V
V
TAP Output Load Equivalent
VREF
50Ω
50Ω
Output
20pF
Test Comparator
VREF
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IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
JTAG AC Characteristics
(Over the Operating Temperature Range)
Parameter
TCK cycle time
TCK high pulse width
TCK low pulse width
TMS Setup
TMS Hold
TDI Setup
TDI Hold
TCK Low to Valid Data*
Symbol
tTHTH
tTHTL
tTLTH
tMVTH
tTHMX
tDVTH
tTHDX
tTLOV
Min
100
40
40
10
10
10
10
–
Max
–
–
–
–
–
–
–
20
Units
ns
ns
ns
ns
ns
ns
ns
ns
JTAG Timing Diagram
tTHTL
tTHTH
tTLTH
TCK
tMVTH
tTHMX
tDVTH
tTHDX
TMS
TDI
tTLOV
TDO
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IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Instruction Set
Code
Instruction
TDO Output
Notes
000
EXTEST
Boundary Scan Register
2, 6
001
010
IDCODE
SAMPLE-Z
32-bit Identification Register
Boundary Scan Register
1, 2
011
PRIVATE
Do Not Use
5
100
SAMPLE(/PRELOAD)
Boundary Scan Register
4
101
PRIVATE
Do Not Use
5
110
PRIVATE
Do Not Use
5
111
BYPASS
Bypass Register
3
Notes:
1. Places Qs in high-Z in order to sample all input data, regardless of other SRAM inputs.
2. TDI is sampled as an input to the first ID register to allow for the serial shift of the external TDI data.
3. BYPASS register is initiated to VSS when BYPASS instruction is invoked. The BYPASS register also holds the last serially loaded TDI when exiting the
shift-DR state.
4. SAMPLE instruction does not place Qs in high-Z.
5. This instruction is reserved. Invoking this instruction will cause improper SRAM functionality.
6.
This EXTEST is not IEEE 1149.1-compliant. By default, it places Q in high-Z. If the internal register on the scan chain is set high, Q will be updated with
information loaded via a previous SAMPLE instruction. The actual transfer occurs during the update IR state after EXTEST is loaded. The value of the
internal register can be changed during SAMPLE and EXTEST only.
ID Register Definition
Instruction Field
Revision Number (31:28)
Device Depth (27:23)
Device Width (22:18)
ISSI Device ID (17:12)
ISSI JEDEC ID (11:1)
ID Register Presence (0)
Description
Reserved for version number.
Defines depth of SRAM. 128K or 256K
Defines Width of the SRAM. x36/32 or x18
Reserved for future use.
Allows unique identification of SRAM vendor.
Indicate the presence of an ID register.
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128K x 36/32
xxxx
00110
00100
xxxxx
00011010101
1
256K x 18
xxxx
00111
00011
xxxxx
00011010101
1
27
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Boundary Scan Order
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Continue next page
165 BGA
X36/32
Signal
Bump ID
MODE
1R
NC
6N
NC
11P
A
8P
A
8R
A
9R
A
9P
A
10P
A
10R
A
11R
ZZ
11H
DQPa
11N
DQa
11M
DQa
11L
DQa
11K
DQa
11J
DQa
10M
DQa
10L
DQa
10K
DQa
10J
DQb
11G
DQb
11F
DQb
11E
DQb
11D
DQb
10G
DQb
10F
DQb
10E
DQb
10D
DQPb
11C
NC
11A
A
10A
A
10B
/ADV
9A
/ADSP
9B
/ADSC
8A
/OE
8B
/BWE
7A
/GW
7B
CLK
6B
NC
11B
Signal
MODE
NC
NC
A
A
A
A
A
A
A
ZZ
NC
NC
NC
NC
NC
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQa
DQPa
NC
NC
NC
NC
A
A
A
/ADV
/ADSP
/ADSC
/OE
/BWE
/GW
CLK
NC
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
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X18
Bump ID
1R
6N
11P
8P
8R
9R
9P
10P
10R
11R
11H
11N
11M
11L
11K
11J
10M
10L
10K
10J
11G
11F
11E
11D
11C
10F
10E
10D
10G
11A
10A
10B
9A
9B
8A
8B
7A
7B
6B
11B
Bit #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
119 BGA
X36/32
Signal
Bump ID
MODE
3R
NC
4L
NC
7R
A
4T
A
3T
A
5B
A
5C
A
5A
A
5T
A
6R
ZZ
7T
DQPa
6P
DQa
7N
DQa
6M
DQPa
7P
DQa
6N
DQa
7L
DQa
6K
DQa
6L
DQa
7K
DQb
6H
DQb
7G
DQb
7H
DQb
6F
DQb
7E
DQb
6G
DQb
6E
DQb
7D
DQPb
6D
NC
6T
A
6A
A
6C
/ADV
4G
/ADSP
4A
/ADSC
4B
/OE
4F
/BWE
4M
/GW
4H
CLK
4K
NC
7C
X18
Signal Bump ID
MODE
3R
NC
4L
NC
7R
A
2T
A
3T
A
5B
A
5C
A
5A
A
5T
A
6R
ZZ
7T
NC
6P
NC
7N
NC
6M
NC
7L
NC
6K
DQa
7P
DQa
6N
DQa
6L
DQa
7K
DQa
6H
DQa
7G
DQa
6F
DQa
7E
DQPa
6D
NC
6G
NC
6E
NC
7D
NC
7H
A
6T
A
6A
A
6C
/ADV
4G
/ADSP
4A
/ADSC
4B
/OE
4F
/BWE
4M
/GW
4H
CLK
4K
NC
7C
28
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
165 BGA
X36/32
Signal
Bump ID
NC
1A
/CE2
6A
/BWa
5B
/BWb
5A
/BWc
4A
/BWd
4B
CE2
3B
/CE
3A
A
2A
A
2B
NC
1B
DQPc
1C
DQc
1D
DQc
1E
DQc
1F
DQc
1G
DQc
2D
DQc
2E
DQc
2F
DQc
2G
DQd
1J
DQd
1K
DQd
1L
DQd
1M
DQd
2J
DQd
2K
DQd
2L
DQd
2M
DQPd
1N
A
3P
A
3R
A
4R
A
4P
A1
6P
A0
6R
119 BGA
Signal
NC
/CE2
/BWa
NC
/BWb
NC
CE2
/CE
A
A
NC
NC
NC
NC
NC
NC
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQb
DQPb
NC
NC
NC
NC
A
A
A
A
A1
A0
X18
Bump ID
1A
6A
5B
5A
4A
4B
3B
3A
2A
2B
1B
1C
1D
1E
1F
1G
2D
2E
2F
2G
1J
1K
1L
1M
1N
2K
2L
2M
2J
3P
3R
4R
4P
6P
6R
X36/32
Bit #
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
Signal
NC
/CE2
/BWa
/BWb
/BWc
/BWd
CE2
/CE
A
A
NC
DQPc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQc
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQd
DQPd
A
A
A
A
A1
A0
Bump ID
1B
6B
5L
5G
3G
3L
2B
4E
3A
2A
1C
2D
1E
2F
1D
2E
1G
2H
2G
1H
2K
1L
1K
2M
1N
2L
2N
1P
2P
2R
2C
3B
3C
4N
4P
X18
Signal Bump ID
NC
1B
/CE2
6B
/BWa
5L
NC
5G
/BWb
3G
NC
3L
CE2
2B
/CE
4E
A
3A
A
2A
NC
1C
NC
2D
NC
1E
NC
2F
NC
1G
NC
2H
DQb
1D
DQb
2E
DQb
2G
DQb
1H
DQb
2K
DQb
1L
DQb
2M
DQb
1N
DQPb
2P
NC
2L
NC
2N
NC
1P
NC
1K
A
2R
A
2C
A
3B
A
3C
A1
4N
A0
4P
Note : DQPa, DQPb, DQPc, and DQPd pins of x36 IO option are NC of x32 IO option.
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
29
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
ORDERING INFORMATION
The ordering code information of the product family
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
30
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Commercial Range: 0°C to 70°C
VDD
VDD =3.3V
VDDQ=2.5V
or
VDDQ=3.3V
SPEED
6.5ns
7.5ns
VDD =2.5V
VDDQ=2.5V
6.5ns
7.5ns
X36
X32
X18
Package
IS61LF12836EC-6.5TQ
IS61LF12836EC-6.5B3
IS61LF12832EC-6.5TQ
IS61LF12832EC-6.5B3
IS61LF25618EC-6.5TQ
IS61LF25618EC-6.5B3
100 QFP
165 BGA
IS61LF12836EC-6.5B2
IS61LF12836EC-6.5TQL
IS61LF12832EC-6.5B2
IS61LF12832EC-6.5TQL
IS61LF25618EC-6.5B2
IS61LF25618EC-6.5TQL
119 BGA
100 QFP, Lead-free
IS61LF12836EC-6.5B3L
IS61LF12836EC-6.5B2L
IS61LF12832EC-6.5B3L
IS61LF12832EC-6.5B2L
IS61LF25618EC-6.5B3L
IS61LF25618EC-6.5B2L
165 BGA, Lead-free
119 BGA, Lead-free
IS61LF12836EC-7.5TQ
IS61LF12836EC-7.5B3
IS61LF12832EC-7.5TQ
IS61LF12832EC-7.5B3
IS61LF25618EC-7.5TQ
IS61LF25618EC-7.5B3
100 QFP
165 BGA
IS61LF12836EC-7.5B2
IS61LF12836EC-7.5TQL
IS61LF12832EC-7.5B2
IS61LF12832EC-7.5TQL
IS61LF25618EC-7.5B2
IS61LF25618EC-7.5TQL
119 BGA
100 QFP, Lead-free
IS61LF12836EC-7.5B3L
IS61LF12836EC-7.5B2L
IS61LF12832EC-7.5B3L
IS61LF12832EC-7.5B2L
IS61LF25618EC-7.5B3L
IS61LF25618EC-7.5B2L
165 BGA, Lead-free
119 BGA, Lead-free
IS61VF12836EC-6.5TQ
IS61VF12836EC-6.5B3
IS61VF12832EC-6.5TQ
IS61VF12832EC-6.5B3
IS61VF25618EC-6.5TQ
IS61VF25618EC-6.5B3
100 QFP
165 BGA
IS61VF12836EC-6.5B2
IS61VF12836EC-6.5TQL
IS61VF12832EC-6.5B2
IS61VF12832EC-6.5TQL
IS61VF25618EC-6.5B2
IS61VF25618EC-6.5TQL
119 BGA
100 QFP, Lead-free
IS61VF12836EC-6.5B3L
IS61VF12836EC-6.5B2L
IS61VF12832EC-6.5B3L
IS61VF12832EC-6.5B2L
IS61VF25618EC-6.5B3L
IS61VF25618EC-6.5B2L
165 BGA, Lead-free
119 BGA, Lead-free
IS61VF12836EC-7.5TQ
IS61VF12836EC-7.5B3
IS61VF12832EC-7.5TQ
IS61VF12832EC-7.5B3
IS61VF25618EC-7.5TQ
IS61VF25618EC-7.5B3
100 QFP
165 BGA
IS61VF12836EC-7.5B2
IS61VF12836EC-7.5TQL
IS61VF12832EC-7.5B2
IS61VF12832EC-7.5TQL
IS61VF25618EC-7.5B2
IS61VF25618EC-7.5TQL
119 BGA
100 QFP, Lead-free
IS61VF12836EC-7.5B3L
IS61VF12836EC-7.5B2L
IS61VF12832EC-7.5B3L
IS61VF12832EC-7.5B2L
IS61VF25618EC-7.5B3L
IS61VF25618EC-7.5B2L
165 BGA, Lead-free
119 BGA, Lead-free
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
31
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Industrial Range: -40°C to 85°C
VDD
VDD =3.3V
VDDQ=2.5V
or
VDDQ=3.3V
SPEED
6.5ns
7.5ns
VDD =2.5V
VDDQ=2.5V
6.5ns
7.5ns
X36
X32
X18
Package
IS61LF12836EC-6.5TQI
IS61LF12836EC-6.5B3I
IS61LF12832EC-6.5TQI
IS61LF12832EC-6.5B3I
IS61LF25618EC-6.5TQI
IS61LF25618EC-6.5B3I
100 QFP
165 BGA
IS61LF12836EC-6.5B2I
IS61LF12836EC-6.5TQLI
IS61LF12832EC-6.5B2I
IS61LF12832EC-6.5TQLI
IS61LF25618EC-6.5B2I
IS61LF25618EC-6.5TQLI
119 BGA
100 QFP, Lead-free
IS61LF12836EC-6.5B3LI
IS61LF12836EC-6.5B2LI
IS61LF12832EC-6.5B3LI
IS61LF12832EC-6.5B2LI
IS61LF25618EC-6.5B3LI
IS61LF25618EC-6.5B2LI
165 BGA, Lead-free
119 BGA, Lead-free
IS61LF12836EC-7.5TQI
IS61LF12836EC-7.5B3I
IS61LF12832EC-7.5TQI
IS61LF12832EC-7.5B3I
IS61LF25618EC-7.5TQI
IS61LF25618EC-7.5B3I
100 QFP
165 BGA
IS61LF12836EC-7.5B2I
IS61LF12836EC-7.5TQLI
IS61LF12832EC-7.5B2I
IS61LF12832EC-7.5TQLI
IS61LF25618EC-7.5B2I
IS61LF25618EC-7.5TQLI
119 BGA
100 QFP, Lead-free
IS61LF12836EC-7.5B3LI
IS61LF12836EC-7.5B2LI
IS61LF12832EC-7.5B3LI
IS61LF12832EC-7.5B2LI
IS61LF25618EC-7.5B3LI
IS61LF25618EC-7.5B2LI
165 BGA, Lead-free
119 BGA, Lead-free
IS61VF12836EC-6.5TQI
IS61VF12836EC-6.5B3I
IS61VF12832EC-6.5TQI
IS61VF12832EC-6.5B3I
IS61VF25618EC-6.5TQI
IS61VF25618EC-6.5B3I
100 QFP
165 BGA
IS61VF12836EC-6.5B2I
IS61VF12836EC-6.5TQLI
IS61VF12832EC-6.5B2I
IS61VF12832EC-6.5TQLI
IS61VF25618EC-6.5B2I
IS61VF25618EC-6.5TQLI
119 BGA
100 QFP, Lead-free
IS61VF12836EC-6.5B3LI
IS61VF12836EC-6.5B2LI
IS61VF12832EC-6.5B3LI
IS61VF12832EC-6.5B2LI
IS61VF25618EC-6.5B3LI
IS61VF25618EC-6.5B2LI
165 BGA, Lead-free
119 BGA, Lead-free
IS61VF12836EC-7.5TQI
IS61VF12836EC-7.5B3I
IS61VF12832EC-7.5TQI
IS61VF12832EC-7.5B3I
IS61VF25618EC-7.5TQI
IS61VF25618EC-7.5B3I
100 QFP
165 BGA
IS61VF12836EC-7.5B2I
IS61VF12836EC-7.5TQLI
IS61VF12832EC-7.5B2I
IS61VF12832EC-7.5TQLI
IS61VF25618EC-7.5B2I
IS61VF25618EC-7.5TQLI
119 BGA
100 QFP, Lead-free
IS61VF12836EC-7.5B3LI
IS61VF12836EC-7.5B2LI
IS61VF12832EC-7.5B3LI
IS61VF12832EC-7.5B2LI
IS61VF25618EC-7.5B3LI
IS61VF25618EC-7.5B2LI
165 BGA, Lead-free
119 BGA, Lead-free
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
32
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
Automotive(A3) Range: -40°C to 125°C
VDD
VDD
=3.3V
VDDQ=2.5V
or
VDDQ=3.3V
SPEED
6.5ns
7.5ns
VDD =2.5V
VDDQ=2.5V
6.5ns
7.5ns
X36
X32
X18
Package
IS64LF12836EC-6.5TQA3
IS64LF12836EC-6.5B3A3
IS64LF12832EC-6.5TQA3
IS64LF12832EC-6.5B3A3
IS64LF25618EC-6.5TQA3
IS64LF25618EC-6.5B3A3
100 QFP
165 BGA
IS64LF12836EC-6.5B2A3
IS64LF12836EC-6.5TQLA3
IS64LF12832EC-6.5B2A3
IS64LF12832EC-6.5TQLA3
IS64LF25618EC-6.5B2A3
IS64LF25618EC-6.5TQLA3
119 BGA
100 QFP, Lead-free
IS64LF12836EC-6.5B3LA3
IS64LF12836EC-6.5B2LA3
IS64LF12832EC-6.5B3LA3
IS64LF12832EC-6.5B2LA3
IS64LF25618EC-6.5B3LA3
IS64LF25618EC-6.5B2LA3
165 BGA, Lead-free
119 BGA, Lead-free
IS64LF12836EC-7.5TQA3
IS64LF12836EC-7.5B3A3
IS64LF12832EC-7.5TQA3
IS64LF12832EC-7.5B3A3
IS64LF25618EC-7.5TQA3
IS64LF25618EC-7.5B3A3
100 QFP
165 BGA
IS64LF12836EC-7.5B2A3
IS64LF12836EC-7.5TQLA3
IS64LF12832EC-7.5B2A3
IS64LF12832EC-7.5TQLA3
IS64LF25618EC-7.5B2A3
IS64LF25618EC-7.5TQLA3
119 BGA
100 QFP, Lead-free
IS64LF12836EC-7.5B3LA3
IS64LF12836EC-7.5B2LA3
IS64LF12832EC-7.5B3LA3
IS64LF12832EC-7.5B2LA3
IS64LF25618EC-7.5B3LA3
IS64LF25618EC-7.5B2LA3
165 BGA, Lead-free
119 BGA, Lead-free
IS64VF12836EC-6.5TQA3
IS64VF12836EC-6.5B3A3
IS64VF12832EC-6.5TQA3
IS64VF12832EC-6.5B3A3
IS64VF25618EC-6.5TQA3
IS64VF25618EC-6.5B3A3
100 QFP
165 BGA
IS64VF12836EC-6.5B2A3
IS64VF12836EC-6.5TQLA3
IS64VF12832EC-6.5B2A3
IS64VF12832EC-6.5TQLA3
IS64VF25618EC-6.5B2A3
IS64VF25618EC-6.5TQLA3
119 BGA
100 QFP, Lead-free
IS64VF12836EC-6.5B3LA3
IS64VF12836EC-6.5B2LA3
IS64VF12832EC-6.5B3LA3
IS64VF12832EC-6.5B2LA3
IS64VF25618EC-6.5B3LA3
IS64VF25618EC-6.5B2LA3
165 BGA, Lead-free
119 BGA, Lead-free
IS64VF12836EC-7.5TQA3
IS64VF12836EC-7.5B3A3
IS64VF12832EC-7.5TQA3
IS64VF12832EC-7.5B3A3
IS64VF25618EC-7.5TQA3
IS64VF25618EC-7.5B3A3
100 QFP
165 BGA
IS64VF12836EC-7.5B2A3
IS64VF12836EC-7.5TQLA3
IS64VF12832EC-7.5B2A3
IS64VF12832EC-7.5TQLA3
IS64VF25618EC-7.5B2A3
IS64VF25618EC-7.5TQLA3
119 BGA
100 QFP, Lead-free
IS64VF12836EC-7.5B3LA3
IS64VF12836EC-7.5B2LA3
IS64VF12832EC-7.5B3LA3
IS64VF12832EC-7.5B2LA3
IS64VF25618EC-7.5B3LA3
IS64VF25618EC-7.5B2LA3
165 BGA, Lead-free
119 BGA, Lead-free
 Note : Not all automotive options listed are currently available. Please contact ISSI for parts
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
33
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
PACKAGE OUTLINE DRAWING
100 QFP (14x20x1.4mm)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
34
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
119 BGA (14x22x2.15mm)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
35
IS61(4)LF12836EC/IS61(4)VF12836EC/IS61(4)LF12832EC
IS61(4)VF12832EC/IS61(4)LF25618EC/IS61(4)VF25618EC
165 BGA (13x15x1.2mm)
Integrated Silicon Solution, Inc.- www.issi.com
Rev. C1
09/30/2015
36
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