ON NCP1093MNRG Integrated ieee 802.3at poe-pd interface controller Datasheet

NCP1093, NCP1094
Integrated IEEE 802.3at
PoE-PD Interface Controller
Description
The NCP1093 and NCP1094 are members of ON Semiconductor’s
high power HIPOt Power over Ethernet Powered Device (PoE−PD)
product family and integrate an IEEE 802.3at PoE−PD interface
controller.
Both variants incorporate the required functions such as detection,
classification, under voltage lockout, inrush and operational current
limit. A power good and NCLASS_AT signal have been added to
guarantee proper enabling/disabling of the DC−DC controller for both
type−I and type−II operation. In addition, the NCP1093 offers a
programmable under−voltage while the NCP1094 provides an
auxiliary pin for applications supporting auxiliary supplies.
The NCP1093 and NCP1094 are fabricated in a robust high voltage
process and integrate a rugged vertical N−channel DMOS suitable for
the most demanding environments and capable of withstanding harsh
environments such as hot swap and cable ESD events.
The NCP1093 and NCP1094 complement ON Semiconductor’s
ASSP portfolio in industrial devices and can be combined with stepper
motor drivers, CAN bus drivers and other high−voltage interfacing
devices to offer complete solutions to the industrial and security
market.
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DFN10
MN SUFFIX
CASE 485C
PIN CONFIGURATION
1
INRUSH
CLASS
DET
VPORTN1
VPORTN2
VPORTP
NCLASS_AT
*
PGOOD
RTN
EP**
(Top View)
*NCP1093 = UVLO
NCP1094 = AUX
** Exposed pad should be
connected to VPORTN
MARKING DIAGRAMS
Features
•
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Fully Supports IEEE 802.3af/at Specifications
Programmable Classification Current
Support Two Event Classification−Signature
Adjustable Under Voltage Lock Out (NCP1094 Only)
Open−Drain Power Good Indicator
120 mA Typical Inrush Current Limit
680 mA Typical Operational Current Limit
Pass Switch Disabling Input for Rear Auxiliary Supply Operation
(NCP1094 Only)
Over−temperature Protection
Industrial Temperature Range −40°C to 85°C with Full Operation up
to 125°C Junction Temperature
0.6 W Hot−swap Pass−switch
Vertical N−channel DMOS Pass−switch Offers the Robustness of
Discrete MOSFETs
NCP10
93MN
ALYWG
G
NCP10
94MN
ALYWG
G
NCP109xMN = Specific Device Code
A
= Assembly Location
L
= Wafer Lot
Y
= Year
W
= Work Week
G
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
Package
Shipping†
NCP1093MNG
DFN10
(Pb−Free)
120 Units / Tube
NCP1093MNRG
DFN10
(Pb−Free)
3000 / Tape & Reel
NCP1094MNG
DFN10
(Pb−Free)
120 Units / Tube
NCP1094MNRG
DFN10
(Pb−Free)
3000 / Tape & Reel
Device
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2014
March, 2014 − Rev. 2
1
Publication Order Number:
NCP1093/D
NCP1093, NCP1094
VPORTP
THERMAL
SHUTDOWN
DETECTION
INTERNAL
SUPPLY
&
VOLTAGE
REFERENCE
DET
nCLASS_AT
DUAL EVENT
CLASSIFICATION
INDICATOR
CLASS
CLASSIFICATION
UVLO
EXTERNAL
SELECTION
VPORT
MONITOR
UVLO
NCP1093 only
OPERATIONAL
CURRENT LIMIT
IEEE Interface
Shutdown
(AUX supply priority)
AUX
HOT SWAP SWITCH
INRUSH
INRUSH
CURRENT LIMIT
NCP1094 only
CONTROL & CURRENT
LIMIT BLOCKS
POWER GOOD
INDICATOR
PGOOD
RTN
VPORTN
Figure 1. NCP1093/94 Functional Block Diagram
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2
NCP1093, NCP1094
Simplified Application Diagrams
RJ−45
VPORTP
Rdet
DB1
DET
Cline
Z_line
Rclass
Rinrush
PGOOD
CLASS
NCP1093
To DC−DC
Converter
INRUSH
Ruvlo1
RTN
DB2
Spare
Pairs
Cpd
Data
Pairs
UVLO
Ruvlo2
NCLASS_AT
VPORTN
Figure 2. Typical Application Circuit using the NCP1093 with External UVLO Setting
RJ−45
VAUX (+)
VPORTP
Rdet
DB1
DET
Cline
Z_line
Rclass
Rinrush
PGOOD
CLASS
Cpd
Data
Pairs
NCP1094
INRUSH
RTN
Spare
Pairs
DB2
AUX
NCLASS_AT
VPORTN
VAUX (−)
Figure 3. Typical Application Circuit using the NCP1094
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3
To DC−DC
Converter
NCP1093, NCP1094
Table 1. PIN DESCRIPTION
Pin No.
Name
NCP1093
NCP1094
Type
INRUSH
1
1
Output
Current limit programming pin. Connect a resistor between INRUSH and
VPORTN.
CLASS
2
2
Output
Classification current programming pin. Connect a resistor between CLASS
and VPORTN.
DET
3
3
Output,
Open Drain
Detection pin. Connect a 24.9 kW resistor between DET and VPORTP for a
valid PD detection signature.
VPORTN1
4
4
Ground
Negative input power. Connected to the source of the internal pass−switch
VPORTN2
5
5
Ground
Negative input power. Connected to the source of the internal pass−switch
RTN
6
6
Ground
DC−DC controller power return. Connected to the drain of the internal pass−
switch
PGOOD
7
7
Output,
Open Drain
Open Drain Power Good Indicator. Pin is in HZ mode when the power good
signal is active.
UVLO
8
−
Input
Undervoltage lockout input. Voltage with respect to VPORTN. Connect a resistor−divider from VPORTP to UVLO to VPORTNx to set an external UVLO
threshold.
AUX
−
8
Input
Auxiliary Pin. When this pin is pulled up, the Pass Switch is disabled and allows
a supply transition from PSE to the rear auxiliary supply connected between
VPORTP and RTN.
NCLASS_AT
9
9
Output
VPORTP
10
10
Input
Exposed Pad
EP
EP
Ground
Description
Active low enable signal used to verify high power operation
Positive input power. Voltage with respect to VPORTN.
Exposed pad should be connected to VPORTN.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
Conditions
VPORTP
Input power supply
−0.3
72
V
Voltage with respect to VPORTN
RTN
Analog ground supply 2
−0.3
72
V
Pass−switch in off−state (voltage with respect to VPORTN)
CLASS
Analog output
−0.3
72
V
Voltage with respect to VPORTN
INRUSH
Analog output
−0.3
3.6
V
Voltage with respect to VPORTN
AUX
Analog input
−0.3
72
V
Voltage with respect to VPORTN
UVLO
Analog input
−0.3
3.6
V
Voltage with respect to VPORTN
PGOOD
Analog output
−0.3
72
V
Voltage with respect to RTN
TA
Ambient temperature
−40
85
°C
TJ
Junction temperature
−
125
°C
TJ, TSD
Junction temperature
(Note 1)
−
175
°C
TSTG
Storage Temperature
−55
150
°C
TqJA
Thermal Resistance,
Junction to Air (Note 2)
50
°C/W
ESD−HBM
Human Body Model
2
kV
per EIA−JESD22−A114 standard
ESD−CDM
Charged Device Model
500
V
per ESD−STM5.3.1 standard
ESD−MM
Machine Model
200
V
per EIA−JESD22−A115−A standard
LU
Latch−up
±100
mA
Thermal shutdown condition
DFN−10
per JEDEC Standard JESD78
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Tj−TSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. Low qJA is obtained with 2S2P test board (2 signal − 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural
convection. Refer to Jedec JESD51 for details. The exposed pad must be connected to the VPORTN ground pin.
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NCP1093, NCP1094
Recommended Operating Conditions
Operating conditions define the limits for functional operation and parametric characteristics of the device. Note that the
functionality of the device outside the operating conditions described in this section is not warranted. Operating outside the
recommended operating conditions for extended periods of time may affect device reliability.
Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.)
Parameter
Symbol
Min
Typ
Max
Units
Conditions
0
−
57
V
VPORT = VPORTP –
VPORTN
INPUT SUPPLY
VPORT
Input supply voltage
SIGNATURE DETECTION
Offset_det1
I(VPORTP) + I(RTN)
−
2
5
mA
VPORTP = RTN = 1.9 V
Rdet = 24.9 KW
Sleep_det1
I(VPORTP) + I(RTN)
−
15
21
mA
VPORTP = RTN = 9.8 V
Rdet = 24.9 KW
Offset_det2
I(VPORTP) + I(RTN) + I(DET)
73
77
81
mA
VPORTP = RTN = 1.9 V
Rdet = 24.9 KW
Sleep_det2
I(VPORTP) + I(RTN) + I(DET)
390
400
412
mA
VPORTP = RTN = 9.8 V
Rdet = 24.9 KW
Vcl_on
Classification current turn−on lower
threshold
9.8
11.3
13
V
VPORTP rising
Vcl_off
Classification current turn−off upper
threshold
21
−
24
V
VPORTP rising
Vclass_reg
Classification buffer output voltage
−
9.8
−
V
13 V < VPORTP < 21 V
Icl_bias
I(vportp) quiescent current during
classification
−
600
−
mA
I(class) excluded
13 V < VPORTP < 21 V
Iclass0
Class 0: Rclass 4420 W (Note 3)
0
−
4
mA
13 V < VPORTP < 21 V
Iclass1
Class 1: Rclass 953 W (Note 3)
9
−
12
mA
13 V < VPORTP < 21 V
Iclass2
Class 2: Rclass 549 W (Note 3)
17
−
20
mA
13 V < VPORTP < 21 V
Iclass3
Class 3: Rclass 357 W (Note 3)
26
−
30
mA
13 V < VPORTP < 21 V
Iclass4
Class 4: Rclass 255 W (Note 3)
36
−
44
mA
13 V < VPORTP < 21 V
V_mark
Mark event voltage range
5.4
9.7
V
I_mark
I(VPORTP) + I(Rdet) during mark event
range
0.5
−
2
mA
−
−
12
kW
4.3
4.9
5.4
V
CLASSIFICATION
dR_mark
Vreset
Input signature during mark event
(Note 4)
Classification Reset range
VPORTP falling
5.4 V ≤ VPORTP ≤ 9.7 V
VPORTP falling
NCLASS_AT 2 EVENT CLASSIFICATION INDICATOR
Inclass
Nclass_low
I(NCLASS_AT) sinking current
−
−
5
mA
NCLASS_AT voltage output low
−
0.2
0.5
V
I(NCLASS_AT) = 2 mA
UVLO − INTERNAL SETTING − NCP1093/94
Vuvlo_on
Default turn on voltage
−
37
40
V
VPORTP rising
Vuvlo_off
Default turn off voltage
29.6
31
−
V
VPORTP falling
Vhyst_int
UVLO internal hysteresis
−
6
−
V
Uvlo_filter
UVLO On / Off filter time
−
100
−
ms
For information only
3. A tolerance of 1% on the Rclass resistor is included in the min/max values.
4. Measured with the 2 Point Measurement defined in the IEEE 802.3af standard with 5.4 V and 9.7 V the extreme values for V2 & V1.
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NCP1093, NCP1094
Table 3. OPERATING CONDITIONS (All values are with respect to VPORTN unless otherwise noted.)
Symbol
Parameter
Min
Typ
Max
Units
25
−
50
V
1.2
1.26
V
Conditions
UVLO − EXTERNAL SETTING – NCP1093 ONLY
Vuvlo_pr
UVLO external programming range
Vuvlo_on2
External UVLO turn on voltage
1.14
Vhyst_off2
External UVLO turn off voltage
0.95
1
1.05
V
−
2.5
−
mA
Uvlo_ipd
UVLO internal pull down current
VPORTP rising
AUXILIARY SUPPLY SETTING – NCP1094 ONLY
Aux_h
AUX input high level voltage
3.1
−
Aux_l
AUX input low level voltage
−
−
0.6
V
100
−
−
kW
For information only
Pass−switch Rds−on
−
0.6
1
W
Measured with I(RTN) =
200 mA
I_inrush
Inrush current with Rinrush = 169 kW
75
120
170
mA
Measured at
RTN−VPORTN = 3 V
I_ilim
Operating current limit with Rinrush =
169 kW
610
680
800
mA
Current limit threshold
Aux_pd
AUX internal pull down resistor
V
PASS−SWITCH AND CURRENT LIMITING
Ron
POWER GOOD INDICATOR
Vds_pgood_on
RTN−VPORTN threshold voltage
required for power good status
0.8
1
1.2
V
RTN−VPORTN falling
Vds_pgood_off
RTN−VPORTN latchoff threshold
voltage
9
10
11
V
RTN−VPORTN rising
ms
Rising and falling /
for information only
Pgood_filter
Ipgood
Vpgood_low
PGOOD filter time
100
I(PGOOD) sinking current
−
−
5
mA
PGOOD voltage output low
−
0.2
0.5
V
I(PGOOD) = 2 mA
Voltage with respect to RTN
−
600
900
mA
VPORTP = 48 V
150
−
−
°C Tj
Tj = junction temperature
−
15
−
°C Tj
Tj = junction temperature
CURRENT CONSUMPTION
IvportP
I(VPORTP) internal current
consumption
THERMAL SHUTDOWN
TSD
Thermal shutdown threshold
Thyst
Thermal hysteresis
THERMAL RATINGS
Ta
Ambient temperature
−40
−
85
°C
Tj
Junction temperature
−
−
125
°C
3. A tolerance of 1% on the Rclass resistor is included in the min/max values.
4. Measured with the 2 Point Measurement defined in the IEEE 802.3af standard with 5.4 V and 9.7 V the extreme values for V2 & V1.
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NCP1093, NCP1094
Description of Operation
Under Voltage Lock Out (UVLO)
The NCP1093/94 incorporate a fixed under voltage lock
out (UVLO) circuit which monitors the input voltage and
determines when to turn on the pass switch and charge the
dc−dc converter input capacitor before the power up of the
application.
The NCP1093 offers a fixed or adjustable Vuvlo_on
threshold depending if the UVLO pin is used or not. In
Figure 5, the UVLO pin is strapped to ground and the
Vuvlo_on threshold is defined by the internal level.
Powered Device Interface
The integrated PD interface supports the IEEE 802.3af
defined operating modes: detection signature, current
source classification, undervoltage lockout, inrush and
operating current limits. The following sections give an
overview of these previous processes.
Detection
During the detection phase, the incremental equivalent
resistance seen by the PSE through the cable must be in the
IEEE 802.3af standard specification range (23.70 kW to
26.30 kW) for a PSE voltage from 2.7 V to 10.1 V. In order
to compensate for the non−linear effect of the diode bridge
and satisfy the specification at low PSE voltage, the
NCP1093/94 present a suitable impedance in parallel with
the 24.9 kW Rdet external resistor. For some types of diodes
(especially Schottky diodes), it may be necessary to adjust
this external resistor.
The Rdet resistor has to be inserted between VPORTP and
DET pins. During the detection phase, the DET pin is pulled
to ground and goes in high impedance mode (open−drain)
once the device exit this mode, reducing thus the current
consumption on the cable.
VPORTP
VPORTN1,2
Figure 5. Default Internal UVLO Configuration
(NCP1093 only)
To define the UVLO threshold externally, the ULVO pin
must be connected to the center of an external resistor
divider between VPORTP and VPORTN as shown in
Figure 6.
In order to guarantee the detection signature, the
equivalent input resistor made of the Ruvlo1, Ruvlo2 and
Rdet should be equal to 24.9 kW.
Classification
Once the PSE device has detected the PD device, the
classification process begins. In classification, the PD
regulates a constant current source that is set by the external
resistor RCLASS value on the CLASS pin. Figure 4 shows
the schematic overview of the classification block. The
current source is defined as:
VPORTP
9.8 V
Iclass +
Rclass
Ruvlo1
Class_enable
VPORTP
Rdet
DET
VPORT
VPORTP
EN
UVLO
VPORT
UVLO
Ruvlo2
1.2 V
VPORTN1,2
CLASS
NCP1093
9.8 V
Figure 6. Default Internal UVLO Configuration
(NCP1093 only)
For a Vuvlo_on desired turn−on voltage threshold,
Ruvlo1 and Ruvlo2 can be calculated using the following
equations:
VPORTN
Ruvlo +
Figure 4. Classification Block Diagram
24.9 k @ Rdet
Rdet * 24.9 k
The NCP1093/94 is able to detect a dual event
classification generated by a type 2 PSE, and flag it using its
nCLASS_AT open drain indicator.
with
Ruvlo1 ) Ruvlo2 + Ruvlo
and
Ruvlo2 +
Power Mode
With:
Vuvlo_on: Desired Turn−On voltage threshold
When the classification hand−shake is completed, the
PSE and PD devices move into the operating mode.
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1.2
@ Ruvlo
Vuvlo_on
NCP1093, NCP1094
Example for a Targeted Uvlo_on of 35 V:
and the PD application against excessive transient current
and failure on the dc−dc converter output.
Once the input supply reached the Vulvo_on level, the
charge of Cpd capacitor starts with a current limitation set to
to the INRUSH level. When this capacitor is fully charged,
the current limit switches without any spikes from the inrush
current to the operational current level and the power good
indicator on PGOOD pin is turned on. The capacitor is
considered to be fully charged once the following conditions
are satisfied:
1. The drain−source voltage of the Pass Switch has
decreased below the Vds_pgood_on level (typical
1 V)
2. The gate−source voltage of the Pass Switch is
sufficiently high (above 2 V typical) which means
the current in the pass switch has decreased below
the current limit.
This mechanism is depicted in the following Figure 7.
Let’s start with a Rdet of 30.1 kΩ. This gives a Ruvlo of
144 kΩ made with a Ruvlo2 of 4.99 kΩ and a Ruvlo1 of
140 kΩ (closest values from E96 series). Note that there is
a pull down current of 2.5 mA typ on the UVLO. Assuming
the previous example, this pull down current will create a
(non critical) systematic offset of 350 mV on the Uvlon_on
level of 35 V.
The external UVLO hysteresis on the NCP1093 is about
15 percent typical.
Inrush and Operational Current Limitations
Both inrush and operational current limit are defined by
an external Rinrush resistor connected between INRUSH
and VPORTN. The low inrush current limit allows smooth
charge of large dc−dc converter input capacitor by limiting
the power dissipation over the internal pass switch. In power
mode, the operational current limit protects the pass switch
PGOOD
Pgood_on
Inrush current limit 0
Operational current limit
1
Pgood_on
Delay
100 mS
&
detector
VDDA1
VDDA1
1 V / 10 V
VDDA1
2V
RTN
Vds_pgood comparator
Vgs_pgood comparator
RTN
VPORTNx
Sense Resistor
Pass Switch
Figure 7. Inrush and Operational Current Limitation Selection Mechanism
PGOOD Indicator
The operational current limit and the power good
indicator stays active as long as RTN voltage stays below the
vds_pgood_off threshold (10 V typical) and the input supply
stay above the Vulvo_off level. Therefore, fast and large
voltage step lower than 10 V are tolerated on the input
without interruption of the converter controller. Higher
input transient will not affect the behavior if RTN does not
exceed 10 V for more than 100 mS. Such input voltage steps
may be introduced by a PSE which is switched to a higher
power supply. In case RTN is still above 10 V after this delay,
the power good is turned off and the pass switch current limit
falls back to the inrush level.
The NCP1093/94 integrate a Power Good indicator
circuitry indicating the end of the dc−dc converter input
capacitor charge, and the enabling of the operational current
limit. This indicator is implemented on the PGOOD pin
which goes in open drain state when active and which is
pulled to ground during turn off.
A possible usage of this PGOOD pin is illustrated in
Figure 8. During the inrush phase, the converter controller
is forced in standby mode due to the PGOOD pin forcing low
the under voltage lock out pin of the controller. Once the Cpd
capacitor is fully charged, PGOOD goes in open drain state,
allowing the start up sequence of the converter controller.
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NCP1093, NCP1094
VPORTP
VDD
Rdet
DET
Rclass
Rinrush
PGOOD
UVLO
NCP103x
DC−DC Converter
Controller
Cpd
CLASS
OVLO
NCP109x
GATE
VSS
INRUSH
RTN
VPORTN
Figure 8. Power GOOD Implementation
NCLASS_AT Dual Event Classification Indicator
nCLASS_AT will be pulled low to RTN (ground connection
of the DC/DC controller converter).
Otherwise, nCLASS_AT will be in high impedance mode.
The following Scheme illustrates how the nCLass_AT pin
may be configured with the processor of the Powered
Device. An optocoupler is here used to guarantee to the full
isolation between the cable and the application.
The nCLASS AT active low open drain output pin should
be used to notify to the microprocessor of the Powered
Device that the PSE did a one or two event Hardware
Classification.
If a 2 event Hardware classification has been done and
once the PD application power has been applied, the
VPORTP
Rdet
VDD
VSUP
DET
UVLO
PGOOD
OVLO
NCP 1094
Rinrush
DC −DC Converter
Controller
Cpd
CLASS
Cl ine
Z_line
Rclass
VBIAS
INRUSH
Type 2PSE
Powered
Application
GATE
VSS
VNEG
RTN
AUX
VPORTN
nCLASS _AT
To
VAUX
Figure 9. nClass AT indicator / possible implementation with the Powered Device
Hereafter are described several scenarios for which the
NCP109x will not enable its nCLASS_AT pin during the
Powered Mode:
♦ The PSE skipped the classification phase
♦ The PSE did a 1 event hardware classification (it
can be a type 1 PSE or a type 2 PSE with Layer 2
only)
♦ The PSE did a 2 event hardware classification but it
didn’t well control the input voltage in the Mark
voltage (it crossed the Reset range for example).
As soon as the application is powered by the DC/DC and
after its initialization, the microprocessor will check if the
PD interface detected a 2 event hardware classification by
reading its digital input (IN1 in this example). If this IN1 pin
is low, the application knows that the type 2 PSE, and
therefore it can consume power till the level specified by the
IEEE802.3at standard. Otherwise the application will have
to perform a Layer 2 classification with the PSE.
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NCP1093, NCP1094
Auxiliary Supply
To support application connected to non−PoE enabled
networks and minimize the bill of materials, the NCP1094
supports drawing power from an external supply and allows
simplified designs with PoE or auxiliary supply priorities.
In most of the cases, the auxiliary supply is connected
between VPORTP and RTN with a serial diode between
VPORTP and VAUX, as shown in Figure 10.
RJ−45
VAUX (+)
VPORTP
Rdet
DB1
DET
Cline
Z_line
Rclass
Rinrush
PGOOD
CLASS
Cpd
Data
Pairs
To DC−DC
Converter
NCP1094
INRUSH
RTN
DB2
Spare
Pairs
AUX
VPORTN
VAUX (−)
Figure 10. Auxiliary Supply Dominant PD Interface
and the application will remain supplied by the auxiliary
supply. The transition will happen without any power
conversion interruption since the PGOOD indicator stays
active (high impedance state).
Figure 11 depicts an other PD application where the POE
supply is dominant over the VAUX supply. A diode D1 has
been added in order to not corrupt the PD detection signature
when the dc−dc converter is supplied by VAUX.
The NCP1094 offers an AUX input pin which turns off the
pass switch when pulled high. This feature is useful for PD
applications where the auxiliary supply has to be dominant
over the PoE supply. When the auxiliary supply is inserted
on a POE powered application, the pass switch
disconnection will move the current path from the PSE to the
rear auxiliary supply. Since the current delivered by the PSE
will goes below the DC MPS level (specified in IEEE
802.3 af/at standard), the PSE will disconnect the PoE−PD
VAUX (+)
RJ−45
D1
VPORTP
Rdet
DB1
DET
Rinrush
PGOOD
CLASS
Cpd
Rclass
Cline
Z_line
Data
Pairs
NCP1094
INRUSH
RTN
Spare
Pairs
DB2
AUX
VPORTN
VAUX (−)
Figure 11. PoE Supply Dominant PD Interface
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To DC−DC
Converter
NCP1093, NCP1094
Thermal Shutdown
Company or Product Inquiries
The NCP1093/94 include a thermal shutdown which
protect the device in case of high junction temperature. Once
the thermal shutdown (TSD) threshold is exceeded, the
classification block, the pass switch and the PGOOD
indicator are disabled. The NCP109X returns automatically
to normal operation once the die temperature has fallen
below the TSD low limit.
For more information about ON Semiconductor’s Power
over Ethernet products visit our Web site at
http://www.onsemi.com.
http://onsemi.com
11
NCP1093, NCP1094
PACKAGE DIMENSIONS
DFN10, 3x3, 0.5P
CASE 485C
ISSUE B
D
PIN 1
REFERENCE
2X
2X
E
DETAIL A
Bottom View
(Optional)
MOLD CMPD
(A3)
DETAIL B
A1
A
10X
SIDE VIEW
A1
D2
10X
L
1
SOLDERING FOOTPRINT*
5
DIM
A
A1
A3
b
D
D2
E
E2
e
K
L
L1
MILLIMETERS
MIN
MAX
0.80
1.00
0.00
0.05
0.20 REF
0.18
0.30
3.00 BSC
2.40
2.60
3.00 BSC
1.70
1.90
0.50 BSC
0.19 TYP
0.35
0.45
0.00
0.03
2.6016
E2
K
10
10X
1.8508
2.1746
6
3.3048
b
0.10 C A B
0.05 C
C
DETAIL A
e
A3
DETAIL B
Side View
(Optional)
SEATING
PLANE
0.08 C
10X
ÉÉÉ
ÉÉÉ
EXPOSED Cu
TOP VIEW
0.15 C
0.10 C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30 MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
5. TERMINAL b MAY HAVE MOLD COMPOUND
MATERIAL ALONG SIDE EDGE. MOLD
FLASHING MAY NOT EXCEED 30 MICRONS
ONTO BOTTOM SURFACE OF TERMINAL b.
6. DETAILS A AND B SHOW OPTIONAL VIEWS
FOR END OF TERMINAL LEAD AT EDGE OF
PACKAGE.
L1
ÇÇÇ
ÇÇÇ
ÇÇÇ
0.15 C
EDGE OF PACKAGE
A
B
BOTTOM VIEW
NOTE 3
10X
0.5651
10X
0.5000 PITCH
0.3008
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
All brand names and product names appearing in this document are registered trademarks or trademarks of their respective holders.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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http://onsemi.com
12
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP1093/D
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