NL3S22S USB 2.0 + Audio Switch The NL3S22S is a double−pole/double−throw (DPDT) analog switch for routing high speed differential data and audio. The high−speed data path is compliant with High Speed USB 2.0, Full Speed USB 1.1, Low Speed USB 1.0 and any generic UART protocol. The multi−purpose audio path is capable of passing signals with negative voltages as low as 2 V below ground and features shunt resistors to reduce Pop and Click noise in the audio system. www.onsemi.com MARKING DIAGRAM Features • • • • • • VCC Range: 2.7 V to 5.5 V Control Pins Compatible with 1.8 V Interfaces ICC: 23 mA (Typ) ESD Performance: 4 kV HBM Available in1.4 mm x 1.8 mm UQFN10 These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Input Signal Range: 0 V to 3.7 V RDS(on): 5 W (Typ) CON: 4.5 pF (Typ) Data Rate: USB 2.0–Compliant – up to 480 Mbps AW M G = = = Device Code Date Code Pb−Free Device ORDERING INFORMATION Device NL3S22SMUTAG Audio Path • • • • 1 AW MG G (Note: Microdot may be in either location) High Speed Data Path • • • • UQFN10 CASE 488AT Input Signal Range: −2.0 V to 2.0 V RDSON: 3 W (Typ) RON(FLAT): 0.002 W (Typ) THD: 0.002% (RL = 16 W / VIS = 0.4 VRMS) Package Shipping† UQFN10 (Pb−Free) 3000 / Tape & Reel †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D. Applications • • • • Smartphones Tablets USB 2.0 Hosts/Peripherals Audio / High−Speeds Data Switching © Semiconductor Components Industries, LLC, 2016 October, 2016 − Rev. 0 1 Publication Order Number: NL3S22S/D NL3S22S VCC HDP D+ AUDP Shunt HDN D− AUDN Shunt EN SEL Control Logic GND Figure 1. Block Diagram FUNCTION TABLE EN SEL Shunt Status D+/D− Function 0 X ON No Connect 1 0 OFF AUDP/AUDN 1 1 ON HDP/HDN Figure 2. UQFN10 – Top Through View PIN DESCRIPTION Pin Name Pin VCC 1 Power Supply Description HDN 2 High Speed Differential Data (−) AUDN 3 Audio Signal (−) SEL 4 Function Select D− 5 Audio/Data Common I/O (−) GND 6 Ground D+ 7 Audio/Data Common I/O (+) EN 8 Chip Enable AUDP 9 Audio Signal (+) HDP 10 High Speed Differential Data (+) www.onsemi.com 2 NL3S22S MAXIMUM RATINGS Rating Symbol VCC Positive DC Supply Voltage VIS Analog Input/Output Voltage HDP, HDN AUDP, AUDN Digital Control Pin Voltage on EN, SEL Unit V −0.3 to +5.5 V −2.5 to VCC + 0.3 D+, D− VIN Value −0.3 to +6 −2.5 to +5.5 −0.3 to VCC + 0.3 V Ts Storage Temperature −55 to +150 °C TL Lead Temperature, 1 mm from Case for 10 seconds 260 °C TJ Junction Temperature Under Bias 150 °C MSL Moisture Sensitivity (Note 1) ILU Latchup Current (Note 2) ESD ESD Protection (Note 3) Level 1 Human Body Model ±100 mA 4000 V Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected. 1. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A. 2. Latch up Current Maximum Rating: ±100 mA per JEDEC standard: JESD78. 3. This device series contains ESD protection and passes the following tests: Human Body Model (HBM) ±4.0 kV per JEDEC standard: JESD22−A114 for all pins. RECOMMENDED OPERATING CONDITIONS Symbol VCCEN VIS Parameter Min Max Unit 2.7 5.5 V 0 3.7 V AUDP, AUDN −2.0 2.0 D+, D− −2.0 3.7 Positive DC Supply Voltage Switch Input / Output Voltage (Note 4) HDP, HDN VIN Digital Control Input Voltage GND VCC V TA Operating Temperature Range −40 +85 °C 4. f the audio channel is not in use, it is recommended that no signals are applied on the audio inputs AUDN and AUDP. www.onsemi.com 3 NL3S22S DC ELECTRICAL CHARACTERISTICS (Typical values are at VCC = +3.6 V and TA = +25 ⁰C) −40 ⁰C to 85 ⁰C Parameter Symbol Test Conditions VCC (V) Min Typ Max Unit 4.2 − 23 105 mA 4.2 1.5 − − V 3.6 1.4 − − 2.7 1.3 − − 4.2 − − 0.4 3.6 − − 0.4 2.7 − − 0.4 POWER SUPPLY ICC Supply Current IIS = 0 mA Control Logic (EN, SEL) VIH VIL Input High Voltage Input Low Voltage V VIHYS Input Hysteresis 2.7 – 5.5 − 250 − mV IIN Leakage Current 2.7 – 5.5 − − ±150 nA AUDIO SWITCH (AUDP/AUDN e D+/D−) ON−Resistance VIS = −2.0 V to 2.0 V, IIS = 50 mA 3.0 − 3 5 W DRON ON−Resistance Matching Between Channels VIS = −2.0 V to 2.0 V, IIS = 50 mA 3.0 − 0.05 − W RFLAT(ON) ON Resistance Flatness VIS = −2.0 V to 2.0 V, IIS = 50 mA 3.0 − 0.002 − W 3.6 − 125 200 W RON RSH Shunt Resistance DATA SWITCH (HDP/HDN e D+/D−) ON−Resistance VIS = 0 V to 1.7 V, IIS = 15 mA 3.0 − 5 7.5 W DRON ON−Resistance Matching Between Channels VIS = 0 V to 1.7 V, IIS = 15 mA 3.0 − 0.02 − W RFLAT(ON) ON Resistance Flatness VIS = 0 V to 1.7 V, IIS = 15 mA 3.0 − 0.003 − W ISW(OFF) OFF−State Leakage VIS = 0 V to 3.6 3.6 − − 200 nA ISW(ON) ON−State Leakage VIS = 0 V to 3.6 3.6 − − ±200 nA RON www.onsemi.com 4 NL3S22S AC ELECTRICAL CHARACTERISTICS (Typical values are at VCC = +3.6 V and TA = +25 ⁰C) −40 ⁰C to 85 ⁰C Test Conditions VCC (V) Min Audio THD f = 20 Hz to 20 kHz, VIS = 0.4 VRMS, DC Bias = 0 V, RL = 16 W 2.7 – 5.5 − 0.002 − % Power Supply Ripple Rejection From VCC unto AUDP/AUDN, f = 217 Hz, RL = 16 W 2.7 – 5.5 − 118 − dB Parameter Symbol Typ Max Unit AUDIO SWITCH (AUDP/AUDN e D+/D−) THD PSRR DATA SWITCH (HDP/HDN e D+/D−) CON Equivalent ON−Capacitance Switch ON, f = 1 MHz 3.6 − 4.84 − pF COFF Equivalent OFF−Capacitance Switch OFF, f = 1 MHz 3.6 − 2.06 − pF Differential Insertion Loss f = 10 MHz 2.7 – 5.5 − −0.42 − dB f = 800 MHz 2.7 – 5.5 − −1.89 − f = 1.1 GHz 2.7 – 5.5 − −3.01 − f = 10 MHz 2.7 – 5.5 − −60 − f = 800 MHz 2.7 – 5.5 − −15 − f = 1.1 GHz 2.7 – 5.5 − −15 − f = 10 MHz 2.7 – 5.5 − −67 − f = 800 MHz 2.7 – 5.5 − −23 − f = 1.1 GHz 2.7 – 5.5 − −19 − From VCC unto D+/D−, f = 217 Hz, RL = 50 W 2.7 – 5.5 − 108 − dB − 0.25 − ns DIL DISO DCTK PSRR Differential Off−Isolation Differential Crosstalk Power Supply Ripple Rejection dB dB DYNAMIC TIMING tPD Propagation Delay (Notes 5 and 6) VNOn or VNCn = 0V, RL = 50 W, 2.7 – 5.5 tON Turn−On Time VIS = 1 V, RL = 50 W, CL = 7 pF (fixture only) 2.7 – 5.5 tOFF tsk(b−b) tsk(ch−ch) Turn−Off Time ms EN or SEL to AUDP/AUDN − 2.2 − EN or SEL to HDP/HDN − 6.2 − VIS = 1 V, RL = 50 W, CL = 7 pF (fixture only) ns 2.7 – 5.5 EN or SEL to AUDP/AUDN − 67 − EN or SEL to HDP/HDN − 1200 − Bit to bit skew Within the same differential channel 2.7 – 5.5 − 5 − ps Channel to channel skew Maximum skew between all channels 2.7 – 5.5 − 5 − ps 5. Guaranteed by design. 6. No other delays than the RC network formed by the load resistance and the load capacitance of the switch are added on the bus. For a 10 pF load, this delay is 5 ns which is much smaller than rise and fall time of typical driving systems. Propagation delays on the bus are determined by the driving circuit on the driving side and its interactions with the load of the driven side. www.onsemi.com 5 NL3S22S PARAMETER MEASUREMENT INFORMATION Figure 3. Differential Insertion Loss (SDD21) Figure 4. Differential Off Isolation (SDD21) Figure 5. Differential Crosstalk (SDD21) Figure 6. Bit−to−Bit and Channel−to−Channel Skew tskew = |tPLH1-tPLH2| or |tPHL1-tPHL2| Figure 7. tON and tOFF Figure 9. On State Leakage Figure 8. Off State Leakage www.onsemi.com 6 NL3S22S TYPICAL OPERATING CHARACTERISTICS Figure 10. USB 2.0 High Speed Eye Diagram Figure 11. USB 1.1 Full Speed Eye Diagram Figure 12. USB 1.0 Low Speed Eye Diagram Figure 13. Product Supply Current Figure 15. Data Switch Differential Insertion Loss Figure 14. Data Path On Resistance www.onsemi.com 7 NL3S22S Figure 17. Data Switch Differential Crosstalk Figure 16. Data Switch Differential Off−Isolation Figure 18. Audio Path On Resistance Figure 19. Audio THD www.onsemi.com 8 NL3S22S PACKAGE DIMENSIONS UQFN10 1.4x1.8, 0.4P CASE 488AT ISSUE A EDGE OF PACKAGE D ÉÉ ÉÉ PIN 1 REFERENCE 2X 2X L1 E DETAIL A Bottom View (Optional) 0.10 C 0.10 C B TOP VIEW A1 0.05 C A1 C SIDE VIEW 3 9X EXPOSED Cu A 0.05 C 10X 5 SEATING PLANE ÉÉ ÉÉ DIM A A1 A3 b D E e L L1 L3 MOLD CMPD A3 DETAIL B Side View (Optional) 1.700 0.0669 0.663 0.0261 6 e 1 0.200 0.0079 10 X L3 b MILLIMETERS MIN MAX 0.45 0.60 0.00 0.05 0.127 REF 0.15 0.25 1.40 BSC 1.80 BSC 0.40 BSC 0.30 0.50 0.00 0.15 0.40 0.60 MOUNTING FOOTPRINT* e/2 L 10 NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. A 1 0.10 C A B 0.05 C 9X 0.563 0.0221 2.100 0.0827 NOTE 3 BOTTOM VIEW 0.400 0.0157 PITCH 10 X 0.225 0.0089 SCALE 20:1 mm Ǔ ǒinches *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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