Micron MT9VDDT6472AG-40B Ddr sdram unbuffered dimm Datasheet

128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
DDR SDRAM
UNBUFFERED DIMM
MT9VDDT1672A – 128MB
MT9VDDT3272A – 256MB
MT9VDDT6472A – 512MB
For the latest data sheet, please refer to the Micron Web
site: www.micron.com/products/modules
Features
Figure 1: 184-Pin DIMM (MO-206)
• JEDEC-standard 184-pin dual in-line memory
module (DIMM)
• Fast data transfer rate: PC3200
• CAS Latency 3
• Utilizes 400 MT/s DDR SDRAM components
• Supports ECC error detection and correction
• 128MB (16 Meg x 72), 256MB (32 Meg x 72), 512MB
(64 Meg x 72)
• VDD= VDDQ= +2.6V
• VDDSPD = +2.3V to +3.6V
• +2.6V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; centeraligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs (CK and CK#)
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Auto Refresh and Self Refresh Modes
• 15.6µs (128MB), 7.8125µs (256MB, 512MB)
maximum average periodic refresh interval
• Serial Presence-Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Gold edge contacts
Table 1:
Standard 1.25in. (31.75mm)
OPTIONS
MARKING
• Package
184-pin DIMM (standard)
184-pin DIMM (lead-free)
• Frequency/CAS Latency
5ns, 400 MT/s (200 MHz), CL = 3
• PCB
1.25in. (31.75mm)
G
Y
-40B
None
Address Table
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
128MB
256MB
512MB
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (16 Meg x 8)
1K (A0–A9)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (32 Meg x 8)
1K (A0–A9)
1 (S0#)
8K
8K (A0–A12)
4 (BA0, BA1)
512Mb (64 Meg x 8)
2K (A0–A9, A11)
1 (S0#)
1
©2004 Micron Technology, Inc.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 2:
Part Numbers and Timing Parameters
PART NUMBER
MT9VDDT1672AG-40B__
MT9VDDT1672AY-40B__
MT9VDDT3272AG-40B__
MT9VDDT3272AY-40B__
MT9VDDT6472AG-40B__
MT9VDDT6472AY-40B__
MODULE
DENSITY
CONFIGURATION
MODULE
BANDWIDTH
MEMORY CLOCK/
DATA RATE
LATENCY
(CL - tRCD - tRP)
128MB
128MB
256MB
256MB
512MB
512MB
16 Meg x 72
16 Meg x 72
32 Meg x 72
32 Meg x 72
64 Meg x 72
64 Meg x 72
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
3.2 GB/s
5ns/400 MT/s
5ns/400 MT/s
5ns/400 MT/s
5ns/400 MT/s
5ns/400 MT/s
5ns/400 MT/s
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
3-3-3
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT9VDDT3272AG-40BA1.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 3:
Pin Assignment
(184-Pin DIMM Front)
Table 4:
Pin Assignment
(184-Pin DIMM Back)
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
93
VSS
94
DQ4
95
DQ5
96
VDDQ
97
DM0
98
DQ6
99
DQ7
100
VSS
101
NC
102
NC
103
NC
104 VDDQ
105 DQ12
106 DQ13
107 DM1
108
VDD
109 DQ14
110 DQ15
111
NC
112 VDDQ
113
NC
114 DQ20
115 NC/A12
VREF
DQ0
VSS
DQ1
DQS0
DQ2
VDD
DQ3
NC
NC
VSS
DQ8
DQ9
DQS1
VDDQ
CK1
CK1#
VSS
DQ10
DQ11
CKE0
VDDQ
DQ16
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
DQ17
DQS2
VSS
A9
DQ18
A7
VDDQ
DQ19
A5
DQ24
VSS
DQ25
DQS3
A4
VDD
DQ26
DQ27
A2
VSS
A1
CB0
CB1
VDD
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
DQS8
A0
CB2
VSS
CB3
BA1
DQ32
VDDQ
DQ33
DQS4
DQ34
VSS
BA0
DQ35
DQ40
VDDQ
WE#
DQ41
CAS#
VSS
DQS5
DQ42
DQ43
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
VDD
NC
DQ48
DQ49
VSS
CK2#
CK2
VDDQ
DQS6
DQ50
DQ51
VSS
NC
DQ56
DQ57
VDD
DQS7
DQ58
DQ59
VSS
NC
SDA
SCL
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
VSS
DQ21
A11
DM2
VDD
DQ22
A8
DQ23
VSS
A6
DQ28
DQ29
VDDQ
DM3
A3
DQ30
VSS
DQ31
CB4
CB5
VDDQ
CK0
CK0#
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
VSS
DM8
A10
CB6
VDDQ
CB7
VSS
DQ36
DQ37
VDD
DM4
DQ38
DQ39
VSS
DQ44
RAS#
DQ45
VDDQ
S0#
NC
DM5
VSS
DQ46
162 DQ47
163
NC
164 VDDQ
165 DQ52
166 DQ53
167
NC
168
VDD
169 DM6
170 DQ54
171 DQ55
172 VDDQ
173
NC
174 DQ60
175 DQ61
176
VSS
177 DM7
178 DQ62
179 DQ63
180 VDDQ
181
SA0
182
SA1
183
SA2
184 VDDSPD
NOTE:
Pin 115 is No Connect (128MB), and A12 (256MB, 512MB).
Figure 2: 184-Pin DIMM Pinouts
FRONT VIEW
U10
U1
U2
U3
U4
U5
U6
PIN 52
PIN 1
U7
PIN 53
Indicates a VDD pin
U8
U9
PIN 92
Indicates a VSS pin
BACK VIEW
No Components This Side
PIN 184
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
PIN 145
PIN 144
3
PIN 93
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 5:
Pin Descriptions
Pin numbers may not correlate with symbols; ; Refer to Pin Assignment Tables on page 3 for more information
PIN NUMBERS
SYMBOL
TYPE
DESCRIPTION
63, 65, 154
WE#, CAS#, RAS#
Input
16, 17, 75, 76, 137, 138
CK0, CK0#, CK1,
CK1#, CK2, CK2#
Input
21
CKE0
Input
157
S0#
Input
52, 59
BA0, BA1
Input
27, 29, 32, 37, 41, 43, 48,
115 (256MB, 512MB), 118,
122, 125, 130, 141
A0–A11
(128MB)
A0–A12
(256MB, 512MB)
Input
44, 45, 49, 51, 134, 135,
142, 144
97, 107, 119, 129, 149, 159,
169, 177
CB0–CB7
Input/Output
Command Inputs: WE#, RAS#, and CAS# (along with S#)
define the command being entered.
Clocks: CK and CK# are differential clock inputs. All
address and control input signals are sampled on the
crossing of the positive edge of CK and negative edge of
CK#. Output data (DQs and DQS) is referenced to the
crossings of CK and CK#.
Clock Enable: CKE activates (HIGH) and deactivates (LOW)
internal clock signals, device input buffers, and output
drivers. Deactivating the clock provides PRECHARGE
POWER-DOWN and SELF REFRESH operation (all device
banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any
device bank). CKE is synchronous for all functions except
for disabling outputs, which is achieved asynchronously.
CKE must be maintained HIGH throughout read and
write accesses. Input buffers (excluding CK, CK# and CKE)
are disabled during POWERDOWN. Input buffers
(excluding CKE) are disabled during SELF REFRESH. CKE is
an SSTL_2 input but will detect an LVCMOS LOW level
after VDD is applied and until CKE is first brought HIGH.
After CKE has been brought HIGH, it is an SSTL_2 input
only.
Chip Select: S# enables (registered LOW) and disable
(registered HIGH) the command decoder. All commands
are masked when S# is registered HIGH. S# is considered
part of the command code.
Bank Addresses: BA0 and BA1 define to which device
bank an ACTIVE, READ, WRITE or PRECHARGE command
is being applied.
Address Inputs: Sampled during the ACTIVE command
(row-address) and READ/WRITE command (columnaddress, with A10 defining auto precharge) to select one
location out of the memory array in the respective device
device bank. A10 is sampled during a PRECHARGE
command to determine whether the PRECHARGE applies
to one device bank (A10 LOW) or all device banks (A10
HIGH). The address inputs also provide the op-code
during a MODE REGISTER SET command.
Data I/Os: Check bits.
DM0–DM7
Input
DQS0-DQS7
Input/Output
5, 14, 25, 36, 56, 67, 78, 86
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
4
Data Write Mask: DM LOW allows WRITE operation. DM
HIGH blocks WRITE operation. DM lines do not affect
READ operation.
Data Strobe: Output with READ data, input with WRITE
data. DQS is edge-aligned with READ data, centered in
WRITE data. Used to capture data.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 5:
Pin Descriptions (Continued)
Pin numbers may not correlate with symbols; ; Refer to Pin Assignment Tables on page 3 for more information
2, 4, 6, 8, 12, 13, 19, 20, 23,
24, 28, 31, 33, 35, 39, 40,
53, 55, 57, 60, 61, 64, 68,
69, 72, 73, 79, 80, 83, 84,
87, 88, 94, 95, 98, 99, 105,
106, 109, 110, 117, 121,
131, 133, 146, 147, 150,
151, 153, 155, 161, 162,
165, 166, 170, 171, 174,
175, 178, 179
92
DQ0–DQ63
Input/Output
SCL
Input
181, 182, 183
SA0–SA2
Input
91
SDA
Input/Output
1
7, 15, 22, 30, 38, 54, 62, 70,
77, 85, 96, 104, 108, 112,
120, 128, 136, 143, 148,156,
164, 168, 172, 180
3, 11, 18, 26, 34, 42, 50, 58,
66, 74, 81, 89, 93, 100, 116,
124, 132, 139, 145, 152,
160, 176
184
VREF
VDD, VDDQ
Supply
Supply
Serial Clock for Presence-Detect: SCL is used to
synchronize the presence-detect data transfer to and
from the module.
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin
used to transfer addresses and data into and out of the
presence- detect portion of the module.
SSTL_2 reference voltage.
Power Supply: +2.6V ±0.1V.
VSS
Supply
Ground.
VDDSPD
Supply
9, 10, 71, 82, 90, 101, 102,
103, 113, 115 (128MB), 163,
167, 173
111, 158
NC
–
Serial EEPROM positive power supply: +2.3V to +3.6V.
This supply is isolated from the VDD/VDDQ supply.
No Connects.
DNU
–
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
Data I/Os: Data bus.
Do Not Use: These pins are not connected on this module
but are assigned pins on other modules in this product
family.
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Figure 3: Functional Block Diagram
S0#
DQS0
DQS4
DM0
DM4
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DM CS# DQS
DQ
DQ
DQ
DQ U1
DQ
DQ
DQ
DQ
DQS1
DM CS# DQS
DQ
DQ
DQ
DQ U2
DQ
DQ
DQ
DQ
DQS2
DM CS# DQS
DQ
DQ
DQ
DQ U3
DQ
DQ
DQ
DQ
DQS3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
DM CS# DQS
DQ
DQ
DQ
DQ U9
DQ
DQ
DQ
DQ
WE#
CKE0
5.1
5.1
5.1
DM CS# DQS
DQ
DQ
DQ
DQ U8
DQ
DQ
DQ
DQ
120
DM8
RAS#
CAS#
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
DM7
DM CS# DQS
DQ
DQ
DQ
DQ U4
DQ
DQ
DQ
DQ
DQS8
A0-A12 (256MB, 512MB)
DM CS# DQS
DQ
DQ
DQ
DQ U7
DQ
DQ
DQ
DQ
DQS7
DM3
5.1
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DM6
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
5.1
DM CS# DQS
DQ
DQ
DQ
DQ U6
DQ
DQ
DQ
DQ
DQS6
DM2
5.1
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DM5
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
BA0, BA1
DM CS# DQS
DQ
DQ
DQ
U5
DQ
DQ
DQ
DQ
DQ
DQS5
DM1
A0-A11 (128MB)
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
BA0, BA1: DDR SDRAMs
A0-A11: DDR SDRAMs
A0-A12: DDR SDRAMs
120
CK0
CK0#
4.5pF
WE#: DDR SDRAMs
SDRAM
X3
4.5pF
120
CK2
CK2#
SDRAM
X3
4.5pF
VDDSPD
VDDQ
VDD
SPD/EEPROM
SDRAMs
SDRAMs
VREF
VSS
RAS#: DDR SDRAMs
CAS#: DDR SDRAMs
CK1
CK1#
SDRAM
X3
SDRAMs
SDRAMs
SERIAL PD
SCL
WP
U10
A0
A1
A2
SDA
CKE0: DDR SDRAMs
SA0 SA1 SA2
Standard modules use the following DDR SDRAM devices:
MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT16V64M8TG
(512MB)
NOTE:
1. All resistor values are 22Ω unless otherwise specified.
2. Per industry standard, Micron modules utilize various component speed
grades, as referenced in the module part number guide at
www.micron.com/numberguide.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
Lead-free modules use the following DDR SDRAM devices:
MT46V16M8TG (128MB); MT46V32M8TG (256MB); MT16V64M8TG
(512MB)
6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
General Description
SDRAM modules allows for concurrent operation,
thereby providing high effective bandwidth by hiding
row precharge and activation time.
An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible
with the JEDEC Standard for SSTL_2. All outputs are
SSTL_2, Class II compatible. For more information
regarding DDR SDRAM operation, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data sheet.
The MT9VDDT1672A, MT9VDDT3272A, and
MT9VDDT6472A are high-speed CMOS, dynamic random-access, 128MB, 256MB, and 512MB memory
modules organized in a x72 (ECC) configuration. DDR
SDRAM modules use internally configured quad-bank
DDR SDRAM devices.
DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. Double data
rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or
write access for the DDR SDRAM module effectively
consists of a single 2n-bit wide, one-clock-cycle data
transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted
externally, along with data, for use in data capture at
the receiver. DQS is an intermittent strobe transmitted
by the DDR SDRAM during READs and by the memory
controller during WRITEs. DQS is edge-aligned with
data for READs and center-aligned with data for
WRITEs.
DDR SDRAM modules operate from a differential
clock (CK and CK#); the crossing of CK going HIGH
and CK# going LOW will be referred to as the positive
edge of CK. Commands (address and control signals)
are registered at every positive edge of CK. Input data
is registered on both edges of DQS, and output data is
referenced to both edges of DQS, as well as to both
edges of CK.
Read and write accesses to DDR SDRAM modules
are burst oriented; accesses start at a selected location
and continue for a programmed number of locations
in a programmed sequence. Accesses begin with the
registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address
bits registered coincident with the ACTIVE command
are used to select the device bank and row to be
accessed (BA0, BA1 select device bank; A0–A11
(128MB) or A0–A12 (256MB, 512MB) select device row.
The address bits registered coincident with the READ
or WRITE command are used to select the device bank
and the starting device column location for the burst
access.
DDR SDRAM modules provide for programmable
READ or WRITE burst lengths of 2, 4, or 8 locations. An
auto precharge function may be enabled to provide a
self-timed row precharge that is initiated at the end of
the burst access.
The pipelined, multibank architecture of DDR
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using
a 2,048-bit EEPROM. This nonvolatile storage device
contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters.
The remaining 128 bytes of storage are available for
use by the customer. System READ/WRITE operations
between the master (system logic) and the slave
EEPROM device (DIMM) occur via a standard I2C bus
using the DIMM’s SCL (clock) and SDA (data) signals,
together with SA (2:0), which provide eight unique
DIMM/EEPROM addresses. Write protect (WP) is tied
to ground on the module, permanently disabling hardware write protect.
Mode Register Definition
The mode register is used to define the specific
mode of operation of DDR SDRAM devices. This definition includes the selection of a burst length, a burst
type, a CAS latency and an operating mode, as shown
in Figure 4, Mode Register Definition Diagram, on
page 8. The mode register is programmed via the
MODE REGISTER SET command (with BA0 = 0 and
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power (except
for bit A8, which is self-clearing).
Reprogramming the mode register will not alter the
contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded)
when all device banks are idle and no bursts are in
progress, and the controller must wait the specified
time before initiating the subsequent operation. Violating either of these requirements will result in
unspecified operation.
Mode register bits A0–A2 specify the burst length,
A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and A7–A11
(128MB) or A7–A12 (256MB, 512MB) specify the operating mode.
7
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Burst Length
Operating Mode
Read and write accesses to DDR SDRAM devices are
burst oriented, with the burst length being programmable, as shown in Figure 4, Mode Register Definition
Diagram. The burst length determines the maximum
number of column locations that can be accessed for a
given READ or WRITE command. Burst lengths of 2, 4,
or 8 locations are available for both the sequential and
the interleaved burst types.
Reserved states should not be used, as unknown
operation or incompatibility with future versions may
result.
When a READ or WRITE command is issued, a block
of columns equal to the burst length is effectively
selected. All accesses for that burst take place within
this block, meaning that the burst will wrap within the
block if a boundary is reached. The block is uniquely
selected by A1–Ai when the burst length is set to two,
by A2–Ai when the burst length is set to four and by
A3–Ai when the burst length is set to eight (where Ai is
the most significant column address bit for a given
configuration; see note 5 of Table 6, Burst Definition
Table, on page 9). The remaining (least significant)
address bit(s) is (are) used to select the starting location within the block. The programmed burst length
applies to both read and write bursts.
The normal operating mode is selected by issuing a
MODE REGISTER SET command with bits A7–A11
(128MB), or A7–A12 (256MB, 512MB) each set to zero,
and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command
with bits A7 and A9–A11 (128MB), or A7 and A9–A12
(256MB, 512MB) each set to zero, bit A8 set to one, and
bits A0–A6 set to the desired values.
Figure 4: Mode Register Definition
Diagram
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
13 12
0* 0*
11 10 9 8 7 6 5 4 3 2 1 0
Operating Mode CAS Latency BT Burst Length
Mode Register (Mx)
* M13 and M12 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
256MB, 512MB Modules
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
14 13 12 11 10 9 8
Operating Mode
0* 0*
Burst Type
Accesses within a given burst may be programmed
to be either sequential or interleaved; this is referred to
as the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst
Definition Table, on page 9.
7
6 5 4 3 2 1 0
CAS Latency BT Burst Length
* M14 and M13 (BA0 and BA1)
must be “0, 0” to select the
base mode register (vs. the
extended mode register).
The READ latency is the delay, in clock cycles,
between the registration of a READ command and the
availability of the first bit of output data. The latency
can be set to 3, 2.5, or 2 clocks, as shown in Figure 5,
CAS Latency Diagram, on page 9.
If a READ command is registered at clock edge n,
and the latency is m clocks, the data will be available
nominally coincident with clock edge n + m. Table 7,
CAS Latency (CL) Table, on page 9, indicates the operating frequencies at which each CAS latency setting
can be used.
Reserved states should not be used as unknown
operation or incompatibility with future versions may
result.
Burst Length
M3 = 1
0
0
Reserved
Reserved
0
0
1
2
2
0
1
0
4
4
0
1
1
8
8
1
0
0
Reserved
Reserved
1
0
1
Reserved
Reserved
1
1
0
Reserved
Reserved
1
1
1
Reserved
Reserved
Burst Type
0
Sequential
1
Interleaved
CAS Latency
M6 M5 M4
0
0
0
Reserved
0
0
1
Reserved
0
1
0
2
0
1
1
3
1
0
0
Reserved
1
0
1
Reserved
1
1
0
2.5
1
1
1
Reserved
M12 M11 M10 M9 M8 M7
M3 = 0
0
M3
8
Address Bus
Mode Register (Mx)
M2 M1 M0
Read Latency
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
Address Bus
M6-M0
Operating Mode
0
0
0
0
0
0
Valid
Normal Operation
0
0
0
0
1
0
Valid
Normal Operation/Reset DLL
-
-
-
-
-
-
-
All other states reserved
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 6:
STARTING
COLUMN
ADDRESS
BURST
LENGTH
2
4
8
Figure 5: CAS Latency Diagram
Burst Definition Table
A0
0
1
A1 A0
0
0
0
1
1
0
1
1
A2 A1 A0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
ORDER OF ACCESSES WITHIN A
BURST
TYPE =
SEQUENTIAL
TYPE =
INTERLEAVED
0-1
1-0
0-1
1-0
0-1-2-3
1-2-3-0
2-3-0-1
3-0-1-2
0-1-2-3
1-0-3-2
2-3-0-1
3-2-1-0
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
COMMAND
NOP
CL = 3
DQS
DQ
CK#
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK
COMMAND
NOP
CL = 2.5
0-1-2-3-4-5-6-7
1-2-3-4-5-6-7-0
2-3-4-5-6-7-0-1
3-4-5-6-7-0-1-2
4-5-6-7-0-1-2-3
5-6-7-0-1-2-3-4
6-7-0-1-2-3-4-5
7-0-1-2-3-4-5-6
0-.1-2-3-4-5-6-7
1-0-3-2-5-4-7-6
2-3-0-1-6-7-4-5
3-2-1-0-7-6-5-4
4-5-6-7-0-1-2-3
5-4-7-6-1-0-3-2
6-7-4-5-2-3-0-1
7-6-5-4-3-2-1-0
DQS
DQ
T0
T1
T2
READ
NOP
NOP
T2n
T3
T3n
CK#
CK
COMMAND
NOP
CL = 2
DQS
NOTE:
DQ
1. For a burst length of two, A1–Ai select the two-dataelement block; A0 selects the first access within the
block.
2. or a burst length of four, A2–Ai select the four-data-element block; A0–A1 select the first access within the
block.
3. For a burst length of eight, A3–Ai select the eight-dataelement block; A0–A2 select the first access within the
block.
4. Whenever a boundary of the block is reached within a
given sequence above, the following access wraps
within the block.
5. i = 9 (128MB, 256MB)
i = 9, 11 (512MB)
Table 7:
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
TRANSITIONING DATA
Although not required by the Micron device, JEDEC
specifications recommend when a LOAD MODE REGISTER command is issued to reset the DLL, it should
always be followed by a LOAD MODE REGISTER command to select normal operating mode.
All other combinations of values for A7–A11
(128MB), or A7–A12 (256MB, 512MB) are reserved for
future use and/or test modes. Test modes and
reserved states should not be used because unknown
operation or incompatibility with future versions may
result.
CAS Latency (CL) Table
Extended Mode Register
ALLOWABLE OPERATING
FREQUENCY (MHZ)
SPEED
CL = 2
CL = 2.5
CL = 3
-40B
75 ≤ f ≤ 133
75 ≤ f ≤ 167
125 ≤ f ≤ 200
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
DON’T CARE
The extended mode register controls functions
beyond those controlled by the mode register; these
additional functions are DLL enable/disable and output drive strength. These functions are controlled via
the bits shown in Figure 6, Extended Mode Register
Definition Diagram, on page 10. The extended mode
register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and
9
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Figure 6: Extended Mode Register
Definition Diagram
BA1 = 0) and will retain the stored information until it
is programmed again or the device loses power. The
enabling of the DLL should always be followed by a
LOAD MODE REGISTER command to the mode register (BA0/BA1 both low) to reset the DLL.
The extended mode register must be loaded when
all device banks are idle and no bursts are in progress,
and the controller must wait the specified time before
initiating any subsequent operation. Violating either
of these requirements could result in unspecified operation.
128MB Module
BA1 BA0 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
13 12 11 10
01 11
9
8 7 6
5 4
Operating Mode
3
22
1
0
Address Bus
Extended Mode
Register (Ex)
DS DLL
256MB, 512MB Modules
BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Address Bus
DLL Enable/Disable
The DLL must be enabled for normal operation.
DLL enable is required during power-up initialization
and upon returning to normal operation after having
disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL
is enabled automatically.) Any time the DLL is
enabled, 200 clock cycles must occur before a READ
command can be issued.
14 13 12 11 10 9
8 7 6
5
Operating Mode
01 11
E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22
4
3
22
1
0
Extended Mode
Register (Ex)
DS DLL
E1, E0
E0
DLL
0
Enable
1
Disable
E1
Drive Strength
0
Normal
Operating Mode
0
0
0
0
0
0
0
0
0
0
0
Valid
Reserved
–
–
–
–
–
–
–
–
–
–
–
–
Reserved
NOTE:
1. BA1 and BA0 (E13 and E12 for 128MB or E14 and E13
for 256MB, 512MB) must be “0, 1” to select the
Extended Mode Register (vs. the base Mode Register).
2. The QFC# option is not supported.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
10
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Commands
Table 8, Commands Truth Table, and Table 9, DM
Operation Truth Table, provide a general reference of
available commands. For a more detailed description
Table 8:
of commands and operations, refer to the 128Mb,
256Mb, or 512Mb DDR SDRAM component data
sheets.
Commands Truth Table
DESELECT and NOP are functionally interchangeable; all states and sequences not shown are illegal or reserved
NAME (FUNCTION)
CS#
H
L
L
L
L
L
L
L
L
DESELECT (NOP)
NO OPERATION (NOP)
ACTIVE (Select bank and activate row)
READ (Select bank and column, and start READ burst)
WRITE (Select bank and column, and start WRITE burst)
BURST TERMINATE
PRECHARGE (Deactivate row in bank or banks)
AUTO REFRESH or SELF REFRESH (Enter self refresh mode)
LOAD MODE REGISTER
RAS# CAS#
X
H
L
H
H
H
L
L
L
X
H
H
L
L
H
H
L
L
WE#
ADDR
NOTES
X
H
H
H
L
L
L
H
L
X
X
Bank/Row
Bank/Col
Bank/Col
X
Code
X
Op-Code
1
1
2
3
3
4
5
6, 7
8
NOTE:
1. DESELECT and NOP are functionally interchangeable.
2. BA0–BA1 provide device bank address and A0–A11 (128MB) or A0–A12 (256MB, 512MB) provide device row address.
3. BA0–BA1 provide device bank address; A0–A9 (128MB, 256MB) or A0–A9, A11 (512MB) provide device column address;
A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature.
4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for read
bursts with auto precharge enabled and for write bursts.
5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0–
BA1 are “Don’t Care.”
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.
7. Internal refresh counter controls device row addressing; all inputs and I/Os are “Don’t Care” except for CKE.
8. BA0-BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 =
1, BA1 = 0 select extended mode register; other combinations of BA0–BA1 are reserved). A0–A11 (128MB) or A0–A12
(256MB, 512MB) provide the op-code to be written to the selected mode register.
Table 9:
DM Operation Truth Table
Used to mask write data; provided coincident with the corresponding data
NAME (FUNCTION)
WRITE Enable
WRITE Inhibit
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
11
DM
DQS
L
H
Valid
X
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Absolute Maximum Ratings
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only,
and functional operation of the device at these or any
other conditions above those indicated in the opera-
tional sections of this specification is not implied.
Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Voltage on VDD Supply
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VDDQ Supply
Relative to VsSS . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on VREF and Inputs
Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V
Voltage on I/O Pins
Relative to VSS . . . . . . . . . . . . .-0.5V to VDDQ +0.5V
Operating Temperature,
TA (ambient) . . . . . . . . . . . . . . . . . . . . . .0°C to +70°C
Storage Temperature (plastic) . . . . . . -55°C to +150°C
Short Circuit Output Current. . . . . . . . . . . . . . . . 50mA
Table 10: DC Electrical Characteristics and Operating Conditions
Notes: 1–5, 14; notes appear on pages 18–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
PARAMETER/CONDITION
SYMBOL
Supply Voltage
I/O Supply Voltage
I/O Reference Voltage
I/O Termination Voltage (system)
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
INPUT LEAKAGE CURRENT: Any input 0V ≤ Command/Address,
VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V (All
RAS#, CAS#, WE#,
other pins not under test = 0V)
CKE, S#
CK, CK#
DM
DQ, DQS
OUTPUT LEAKAGE CURRENT:
(DQs are disabled; 0V ≤ VOUT ≤ VDDQ)
OUTPUT LEVELS:
High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT)
Low Current (VOUT = 0.373V, maximum VREF, maximum VTT)
VDDQ
VDDQ
VREF
VTT
VIH(DC)
VIL(AC)
MIN
MAX
2.5
2.7
2.5
2.7
0.49 x VDDQ 0.51 x VDDQ
VREF - 0.04 VREF + 0.04
VREF + 0.15
VDD + 0.3
-0.3
VREF - 0.15
-18
18
UNITS
NOTES
V
V
V
V
V
V
µA
32, 36
32, 36, 39
6, 39
7, 39
25
25
IL
47
IOZ
-6
-2
-5
6
2
5
µA
µA
µA
IOH
IOL
-16.8
16.8
–
–
mA
mA
33, 36
47
Table 11: AC Input Operating Conditions
Notes: 1–5, 14; notes appear on pages 18–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
PARAMETER/CONDITION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
I/O Reference Voltage
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
SYMBOL
MIN
MAX
UNITS
NOTES
VIH(AC)
VIL(AC)
VREF(AC)
VREF + 0.310
–
0.49 x VDDQ
–
VREF - 0.310
0.51 x VDDQ
V
V
V
12, 25, 35
12, 25, 35
6
12
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 12: IDD Specifications and Conditions – 128MB
DRAM components only
Notes: 1–5, 8, 10, 12, 48; notes appear on pages 18–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
MAX
PARAMETER/CONDITION
tRC
tRC
OPERATING CURRENT: One device bank; Active-Precharge;
=
t
t
(MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every two clock
cycles;
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 2; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle;
Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK
(MIN); CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device
bank active; Address and control inputs changing once per clock cycle;
tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock
cycle
tREFC = tRFC (MIN)
AUTO REFRESH CURRENT
t
REFC = 15.625µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during Active, READ, or WRITE commands.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
13
SYMBOL
-40B
UNITS
NOTES
IDD0
1,035
mA
20, 42
IDD1
1,215
mA
20, 42
IDD2P
27
mA
21, 28, 44
IDD2F
450
mA
45
IDD3P
225
mA
21, 28, 44
IDD3N
450
mA
20, 41
IDD4R
1,215
mA
20, 42
IDD4W
1,395
mA
20
IDD5
2,160
mA
20, 44
IDD5A
54
mA
24, 44
IDD6
IDD7
36
3,195
mA
mA
9
20, 43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 13: IDD Specifications and Conditions – 256MB
DRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 18–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
MAX
PARAMETER/CONDITION
tRC
tRC
OPERATING CURRENT: One device bank; Active-Precharge;
=
t
t
(MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every two
clock cycles;
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK
(MIN); CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle
tREFC = tRFC (MIN)
AUTO REFRESH CURRENT
t
REFC = 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during Active, READ, or WRITE
commands.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
14
SYMBOL
-40B
UNITS
NOTES
IDD0
1,215
mA
20, 42
IDD1
1,530
mA
20, 42
IDD2P
36
mA
21, 28, 44
IDD2F
540
mA
45
IDD3P
360
mA
21, 28, 44
IDD3N
630
mA
20, 41
IDD4R
1,800
mA
20, 42
IDD4W
1,755
mA
20
IDD5
2,340
mA
20, 44
IDD5A
54
mA
24, 44
IDD6
IDD7
36
3,645
mA
mA
9
20, 43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 14: IDD Specifications and Conditions – 512MB
DRAM components only
Notes: 1–5, 8, 10, 12; notes appear on pages 18–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
MAX
PARAMETER/CONDITION
tRC
tRC
OPERATING CURRENT: One device bank; Active-Precharge;
=
t
t
(MIN); CK = CK (MIN); DQ, DM, and DQS inputs changing once per
clock cycle; Address and control inputs changing once every two
clock cycles;
OPERATING CURRENT: One device bank; Active-Read-Precharge;
Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and
control inputs changing once per clock cycle
PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks
idle; Power-down mode; tCK = tCK (MIN); CKE = LOW;
IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK
(MIN); CKE = HIGH; Address and other control inputs changing once
per clock cycle. VIN = VREF for DQ, DQS, and DM
ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active;
Power-down mode; tCK = tCK (MIN); CKE = LOW
ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device
bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM,
and DQS inputs changing twice per clock cycle; Address and other
control inputs changing once per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One device
bank active; Address and control inputs changing once per clock
cycle; tCK = tCK (MIN); IOUT = 0mA
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
device bank active; Address and control inputs changing once per
clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice
per clock cycle
tREFC = tRFC (MIN)
AUTO REFRESH CURRENT
t
REFC = 7.8125µs
SELF REFRESH CURRENT: CKE ≤ 0.2V
Standard
OPERATING CURRENT: Four device bank interleaving READs (BL = 4)
with auto precharge, tRC =tRC (MIN); tCK = tCK (MIN); Address and
control inputs change only during Active, READ, or WRITE
commands.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
15
SYMBOL
-40B
UNITS
NOTES
IDD0
1,395
mA
20, 42
IDD1
1,665
mA
20, 42
IDD2P
45
mA
21, 28, 44
IDD2F
495
mA
45
IDD3P
405
mA
21, 28, 44
IDD3N
540
mA
20, 41
IDD4R
1,710
mA
20, 42
IDD4W
1,755
mA
20
IDD5
3,105
mA
20, 44
IDD5A
99
mA
24, 44
IDD6
IDD7
45
4,050
mA
mA
9
20, 43
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 15: Capacitance
Note: 11; notes appear on pages 18–20
PARAMETER
SYMBOL
MIN
MAX
UNITS
CIO
CI 1
CI 2
CI 3
4.0
18.0
10.5
18.0
5.0
27.0
13.5
27.0
pF
pF
pF
pF
Input/Output Capacitance: DQs, DQSs
Input Capacitance: Command and Address, S0#
Input Capacitance: CK, CK#
Input Capacitance: CKE
Table 16: DDR SDRAM Component Electrical Characteristics and
Recommended AC Operating Conditions
Notes: 1–5, 8, 12–15, 29, 31; notes appear on page 18–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
AC CHARACTERISTICS
PARAMETER
-40B
SYMBOL
MIN
MAX
UNITS
Access window of DQs from CK/CK#
CK high-level width
tAC
tCH
-0.7
0.45
+0.7
0.55
tCK
26
CK low-level width
tCL
0.45
0.55
tCK
26
(3)
(2.5)
tCK (2)
tDH
tDS
tDIPW
tDQSCK
tDQSH
5
6
7.5
0.4
0.4
1.75
-0.6
0.35
7.5
13
13
ns
ns
ns
ns
ns
ns
ns
40, 46
40, 46
40, 46
23, 27
23, 27
27
DQS input low pulse width
tDQSL
0.35
DQS-DQ skew, DQS to last DQ valid, per group, per access
Write command to first DQS latching transition
tDQSQ
Clock cycle time
CL = 3
CL = 2.5
CL = 2
DQ and DM input hold time relative to DQS
DQ and DM input setup time relative to DQS
DQ and DM input pulse width (for each input)
Access window of DQS from CK/CK#
DQS input high pulse width
tCK
tCK
tDQSS
0.72
DQS falling edge to CK rising - setup time
tDSS
0.2
DQS falling edge from CK rising - hold time
tDSH
0.2
Half clock period
tHP
Data-out high-impedance window from CK/CK#
Data-out low-impedance window from CK/CK#
Address and control input hold time (1 V/ns)
Address and control input setup time (1 V/ns)
Address and control input hold time (0.5 V/ns)
Address and control input setup time (0.5 V/ns)
t
HZ
LZ
tIH
F
tIS
F
tIH
S
t
ISS
t
IPW
t
Address and Control input pulse width (for each input)
LOAD MODE REGISTER command cycle time
DQ-DQS hold, DQS to first DQ to go non-valid, per access
t
Data hold skew factor
ACTIVE to PRECHARGE command
ACTIVE to READ with Auto precharge command
ACTIVE to ACTIVE/AUTO REFRESH command period
AUTO REFRESH command period
t
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
MRD
tQH
tRAP
tRC
tRFC
16
tCK
0.40
1.28
ns
22, 23
tCK
tCK
t
CK
ns
+0.70
-0.70
0.6
0.6
0.6
0.6
2.20
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHP -tQHS
40
15
55
70
ns
tCK
tCH,tCL
QHS
tRAS
+0.6
NOTES
0.50
70,000
ns
ns
ns
ns
ns
30
16, 38
16, 39
12
12
12
12
22, 23
31
46
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 16: DDR SDRAM Component Electrical Characteristics and
Recommended AC Operating Conditions (Continued)
Notes: 1–5, 8, 12–15, 29, 31; notes appear on page 18–20; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.6V ±0.1V
AC CHARACTERISTICS
-40B
PARAMETER
SYMBOL
MIN
tRCD
15
15
0.9
1.1
t
DQS read postamble
t
0.4
0.6
t
ACTIVE bank a to ACTIVE bank b command
DQS write preamble
t
RRD
WPRE
10
0.25
tWPRES
0
0.4
ACTIVE to READ or WRITE delay
PRECHARGE command period
DQS read preamble
t
RP
RPRE
t
RPST
DQS write preamble setup time
DQS write postamble
t
tWPST
tWR
Write recovery time
Internal WRITE to READ command delay
tWTR
na
Data valid output window
REFRESH to REFRESH command interval
Average periodic refresh interval
Terminating voltage delay to VDD
Exit SELF REFRESH to non-READ command
Exit SELF REFRESH to READ command
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
128MB
256MB, 512MB
128MB
256MB, 512MB
tXSNR
tXSRD
17
CK
38
CK
ns
ns
0.6
tCK
18, 19
17
ns
tCK
140.6
70.3
15.6
7.8
0
75
200
NOTES
tCK
tQH -tDQSQ
tREFI
UNITS
ns
ns
15
2
tREFC
tVTD
MAX
ns
µs
µs
µs
µs
ns
ns
22
21
21
tCK
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©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Notes
1. All voltages referenced to VSS.
2. Tests for AC timing, IDD, and electrical AC and DC
characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for
the full voltage range specified.
3. Outputs measured with equivalent load:
12.
13.
VTT
Output
(VOUT)
50Ω
Reference
Point
30pF
14.
15.
4. AC timing and IDD tests may use a VIL-to-VIH
swing of up to 1.5V in the test environment, but
input timing is still referenced to VREF (or to the
crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input
levels under normal use conditions. The minimum slew rate for the input signals used to test
the device is 1V/ns in the range between VIL(AC)
and VIH(AC).
5. The AC and DC input level specifications are as
defined in the SSTL_2 Standard (i.e., the receiver
will effectively switch as a result of the signal
crossing the AC input level, and will remain in that
state as long as the signal does not ring back
above [below] the DC input LOW [HIGH] level).
6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level
of the same. Peak-to-peak noise (non-common
mode) on VREF may not exceed ±2 percent of the
DC value. Thus, from VDDQ/2, VREF is allowed
±25mV for DC error and an additional ±25mV for
AC noise. This measurement is to be taken at the
nearest VREF by-pass capacitor.
7. VTT is not applied directly to the device. VTT is a
system supply for signal termination resistors, is
expected to be set equal to VREF and must track
variations in the DC level of VREF.
8. IDD is dependent on output loading and cycle
rates. Specified values are obtained with minimum cycle time at CL = 3 for -40B with the outputs open.
9. Enables on-chip refresh and address counters.
10. IDD specifications are tested after the device is
properly initialized, and is averaged at the defined
cycle rate.
11. This parameter is sampled. VDD = +2.6V ±0.1V,
VDDQ = +2.6V ±0.1V, VREF = VSS, f = 200 MHz, TA =
25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) =
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
16.
17.
18.
19.
20.
21.
22.
18
0.2V. DM input is grouped with I/O pins, reflecting
the fact that they are matched in loading.
Slew rates less than 0.5V/ns are not allowed. If the
slew rate exceeds 4.5V/ns, functionality is uncertain.
The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and
CK# cross; the input reference level for signals
other than CK/CK# is VREF.
Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF
stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW.
The output timing reference level, as measured at the
timing reference point indicated in Note 3, is VTT.
t
HZ and tLZ transitions occur in the same access
time windows as valid data transitions. These
parameters are not referenced to a specific voltage
level, but specify when the device output is no
longer driving (HZ) or begins driving (LZ).
The intent of the Don’t Care state after completion
of the postamble is the DQS-driven signal should
either be high, low, or high-Z and that any signal
transition within the input switching region must
follow valid input requirements. That is, if DQS
transitions high [above VIH DC (MIN)] then it must
not transition low (below VIHDC) prior to tDQSH
(MIN).
This is not a device limit. The device will operate
with a negative value, but system performance
could be degraded due to bus turnaround.
It is recommended that DQS be valid (HIGH or
LOW) on or before the WRITE command. The
case shown (DQS going from High-Z to logic
LOW) applies when no WRITEs were previously in
progress on the bus. If a previous WRITE was in
progress, DQS could be HIGH during this time,
depending on tDQSS.
MIN (tRC or tRFC) for IDD measurements is the
smallest multiple of tCK that meets the minimum
absolute value for the respective parameter. tRAS
(MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute
value for tRAS.
The refresh period 64ms. This equates to an average refresh rate of 15.625µs (128MB) 7.8125µs
(256MB, 512MB). However, an AUTO REFRESH
command must be asserted at least once every
140.6µs (128MB) or 70.3µs (256MB, 512MB); burst
refreshing or posting by the DRAM controller
greater than eight refresh cycles is not allowed.
The valid data window is derived by achieving
other specifications: tHP (tCK/2), tDQSQ, and tQH
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
23.
24.
25.
26.
27.
28.
29.
30.
31.
(tQH = tHP - tQHS). The data valid window derates
in direct proportion to the clock duty cycle and a
practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of
45/55, beyond which functionality is uncertain.
Each byte lane has a corresponding DQS.
This limit is actually a nominal value and does not
result in a fail value. CKE is HIGH during
REFRESH command period (tRFC [MIN]) else
CKE is LOW (i.e., during standby).
To maintain a valid level, the transitioning edge of
the input must:
a. Sustain a constant slew rate from the current
AC level through to the target AC level, VIL(AC)
or VIH(AC).
b)Reach at least the target AC level.
c)After the AC target level is reached, continue to
maintain at least the target DC level, VIL(DC) or
VIH(DC).
CK and CK# input slew rate must be ≥ 1V/ns (≥
2V/ns if measured differentially).
DQ and DM input slew rates must not deviate from
DQS by more than 10 percent. DQ/DM/DQS slew
rates less than 0.5 V/ns are not allowed. If slew rate
exceeds 4 V/ns, functionality is uncertain.
VDD must not vary more than 4 percent if CKE is
not active while any device bank is active.
The clock is allowed up to ±150ps of jitter. Each
timing parameter is allowed to vary by the same
amount.
t
HP (MIN) is the lesser of tCL minimum and tCH
minimum actually applied to the device CK and
CK# inputs, collectively during bank active.
READs and WRITEs with auto precharge are not
allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command
being issued.
32. Any positive glitch must be less than 1/3 of the
clock cycle and not more than +400mV or 2.9V,
whichever is less. Any negative glitch must be less
than 1/3 of the clock cycle and not exceed either 300mV or 2.4V, whichever is more positive. The
DC average cannot go below 2.5V minimum.
33. Normal Output Drive Curves:
a. The full variation in driver pull-down current
from minimum to maximum process, temperature and voltage will lie within the outer
bounding lines of the V-I curve of Figure 7,
Pull-Down Characteristics.
b)The variation in driver pull-down current
within nominal limits of voltage and temperature is expected, but not guaranteed, to lie
within the inner bounding lines of the V-I curve
of Figure 7, Pull-Down Characteristics.
c)The full variation in driver pull-up current from
minimum to maximum process, temperature and
voltage will lie within the outer bounding lines of
the V-I curve of Figure 8, Pull-Up Characteristics.
d)The variation in driver pull-up current within
nominal limits of voltage and temperature is
expected, but not guaranteed, to lie within the
inner bounding lines of the V-I curve of Figure 8,
Pull-Up Characteristics.
e)The full variation in the ratio of the maximum to
minimum pull-up and pull-down current
should be between 0.71 and 1.4, for device
drain-to-source voltages from 0.1V to 1.0V, and
at the same voltage and temperature.
f ) The full variation in the ratio of the nominal
pull-up to pull-down current should be unity
±10 percent, for device drain-to-source voltages
from 0.1V to 1.0V.
Figure 7: Pull-Down Characteristics
Figure 8: Pull-Up Characteristics
160
0
140
-20
um
Maxim
Maximum
-40
120
IOUT (mA)
IOUT (mA)
80
Nominal low
60
-80
-100
Nom
-120
inal
-140
Minimum
40
Nominal high
-60
high
Nominal
100
Min
imu
-160
20
low
m
-180
-200
0
0.0
0.5
1.0
1.5
2.0
0.0
2.5
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
0.5
1.0
1.5
2.0
2.5
VDDQ - VOUT (V)
VOUT (V)
19
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©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
41. For -40B modules, IDD3N is specified to be 35mA
per DDR SDRAM device at 100 MHz.
42. Random addressing changing and 50 percent of
data changing at every transfer.
43. Random addressing changing and 100 percent of
data changing at every transfer.
44. CKE must be active (high) during the entire time a
refresh command is executed. That is, from the
time the AUTO REFRESH command is registered,
CKE must be active at each rising clock edge, until
tREF later.
45. IDD2N specifies the DQ, DQS and DM to be driven
to a valid high or low logic level. IDD2Q is similar
to IDD2F except IDD2Q specifies the address and
control inputs to remain stable. Although IDD2F,
IDD2N, and IDD2Q are similar, IDD2F is “worst
case.”
46. Whenever the operating frequency is altered, not
including jitter, the DLL is required to be reset.
This is followed by 200 clock cycles.
47. Leakage number reflects the worst case leakage
possible through the module pin, not what each
memory device contributes.
48. When an input signal is HIGH or LOW, it is
defined as a steady state logic HIGH or LOW.
34. The voltage levels used are derived from a minimum VDD level and the referenced test load. In
practice, the voltage levels obtained from a properly terminated bus will provide significantly different voltage values.
35. VIH overshoot: VIH (MAX) = VDDQ+1.5V for a pulse
width ≤ 3ns and the pulse width can not be greater
than 1/3 of the cycle rate. VIL undershoot: VIL (MIN)
= -1.5V for a pulse width ≤ 3ns and the pulse width
can not be greater than 1/3 of the cycle rate.
36. VDD and VDDQ must track each other.
37. tHZ (MAX) will prevail over tDQSCK (MAX) +
t
RPST (MAX) condition. tLZ (MIN) will prevail
over tDQSCK (MIN) + tRPRE (MAX) condition.
38. tRPST end point and tRPRE begin point are not
referenced to a specific voltage level but specify
when the device output is no longer driving
(tRPST), or begins driving (tRPRE).
39. During initialzation, VDDQ, VTT, and VREF must be
equal to or less than VDD + 0.3V. Alternatively, VTT
may be 1.35V maximum during power up, even if
VDD/VDDQ are 0.0V, provided a minimum of 42
ohms of series resistance is used between the VTT
supply and the input pin.
40. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As
such, future die may not reflect this option.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
20
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©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Initialization
Figure 9: Initialization Flow Diagram
To ensure device operation the DRAM must be initialized as described below:
1. Simultaneously apply power to VDD and VDDQ.
2. Apply VREF and then VTT power.
3. Assert and hold CKE at a LVCMOS logic low.
4. Provide stable CLOCK signals.
5. Wait at least 200µs.
6. Bring CKE high and provide at least one NOP or
DESELECT command. At this point the CKE input
changes from a LVCMOS input to a SSTL2 input
only and will remain a SSTL_2 input unless a
power cycle occurs.
7. Perform a PRECHARGE ALL command.
8. Wait at least tRP time, during this time NOPs or
DESELECT commands must be given.
9. Using the LMR command program the Extended
Mode Register (E0 = 0 to enable the DLL and E1 =
0 for normal drive or E1 = 1 for reduced drive, E2
through En must be set to 0; where n = most significant bit).
10. Wait at least tMRD time, only NOPs or DESELECT
commands are allowed.
11. Using the LMR command program the Mode Register to set operating parameters and to reset the
DLL. Note at least 200 clock cycles are required
between a DLL reset and any READ command.
12. Wait at least tMRD time, only NOPs or DESELECT
commands are allowed.
13. Issue a PRECHARGE ALL command.
14. Wait at least tRP time, only NOPs or DESELECT
commands are allowed.
15. Issue an AUTO REFRESH command (Note this
may be moved prior to step 13).
16. Wait at least tRFC time, only NOPs or DESELECT
commands are allowed.
17. Issue an AUTO REFRESH command (Note this
may be moved prior to step 13).
18. Wait at least tRFC time, only NOPs or DESELECT
commands are allowed.
19. Although not required by the Micron device,
JEDEC requires a LMR command to clear the DLL
bit (set M8 = 0). If a LMR command is issued the
same operating parameters should be utilized as
in step 11.
20. Wait at least tMRD time, only NOPs or DESELECT
commands are allowed.
21. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between
step 11 (DLL Reset) and any READ command.
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
Step
21
1
VDD and VDDQ Ramp
2
Apply VREF and VTT
3
CKE must be LVCMOS Low
4
Apply stable CLOCKs
5
Wait at least 200us
6
Bring CKE High with a NOP command
7
PRECHARGE ALL
8
Assert NOP or DESELECT for tRP time
9
Configure Extended Mode Register
10
Assert NOP or DESELECT for tMRD time
11
Configure Load Mode Register and reset DLL
12
Assert NOP or DESELECT for tMRD time
13
PRECHARGE ALL
14
Assert NOP or DESELECT for tRP time
15
Issue AUTO REFRESH command
16
Assert NOP or DESELECT commands for tRFC
17
Issue AUTO REFRESH command
18
Assert NOP or DESELECT for tRFC time
19
Optional LMR command to clear DLL bit
20
Assert NOP or DESELECT for tMRD time
21
DRAM is ready for any valid command
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
SPD Clock and Data Conventions
SPD Acknowledge
Data states on the SDA line can change only during
SCL LOW. SDA state changes during SCL HIGH are
reserved for indicating start and stop conditions (as
shown in Figure 10, Data Validity, and Figure 11, Definition of Start and Stop).
Acknowledge is a software convention used to indicate successful data transfers. The transmitting device,
either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the
receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (as shown in Figure 11, Definition of Start and Stop).
The SPD device will always respond with an
acknowledge after recognition of a start condition and
its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond
with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device
will transmit eight bits of data, release the SDA line and
monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by
the master, the slave will continue to transmit data. If
an acknowledge is not detected, the slave will terminate further data transmissions and await the stop
condition to return to standby power mode.
SPD Start Condition
All commands are preceded by the start condition,
which is a HIGH-to-LOW transition of SDA when SCL
is HIGH. The SPD device continuously monitors the
SDA and SCL lines for the start condition and will not
respond to any command until this condition has been
met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when
SCL is HIGH. The stop condition is also used to place
the SPD device into standby power mode.
Figure 10: Data Validity
Figure 11: Definition of Start and Stop
SCL
SCL
SDA
SDA
DATA STABLE
DATA
CHANGE
DATA STABLE
START
BIT
STOP
BIT
Figure 12: Acknowledge Response from Receiver
SCL from Master
8
9
Data Output
from Transmitter
Data Output
from Receiver
Acknowledge
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
22
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©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 17: EEPROM Device Select Code
Most significant bit (b7) is sent first
DEVICE TYPE IDENTIFIER
SELECT CODE
CHIP ENABLE
RW
b7
b6
b5
b4
b3
b2
b1
b0
1
0
0
1
1
1
0
0
SA2
SA2
SA1
SA1
SA0
SA0
RW
RW
Memory Area Select Code (two arrays)
Protection Register Select Code
Table 18: EEPROM Operating Modes
MODE
Current Address Read
Random Address Read
Sequential Read
Byte Write
Page Write
RW BIT
WC
BYTES
1
0
1
1
0
0
VIH or VIL
VIH or VIL
VIH or VIL
VIH or VIL
VIL
VIL
1
1
1
≥1
1
≤ 16
INITIAL SEQUENCE
START, Device Select, RW = ‘1’
START, Device Select, RW = ‘0’, Address
reSTART, Device Select, RW = ‘1’
Similar to Current or Random Address Read
START, Device Select, RW = ‘0’
START, Device Select, RW = ‘0’
Figure 13: SPD EEPROM Timing Diagram
tF
t HIGH
tR
t LOW
SCL
t SU:STA
t HD:STA
t SU:DAT
t HD:DAT
t SU:STO
SDA IN
t DH
t AA
t BUF
SDA OUT
UNDEFINED
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
23
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©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 19: Serial Presence-Detect EEPROM DC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SYMBOL
SUPPLY VOLTAGE
INPUT HIGH VOLTAGE: Logic 1; All inputs
INPUT LOW VOLTAGE: Logic 0; All inputs
OUTPUT LOW VOLTAGE: IOUT = 3mA
INPUT LEAKAGE CURRENT: VIN = GND to VDD
OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD
STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD OR VSS
POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz
VDD
VIH
VIL
VOL
ILI
ILO
ISB
ICC
MIN
MAX
2.3
3.6
VDD x 0.7 VDD + 0.5
-1
VDD x 0.3
–
0.4
–
10
–
10
–
30
–
2
UNITS
V
V
V
V
µA
µA
µA
mA
Table 20: Serial Presence-Detect EEPROM AC Operating Conditions
All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
Time the bus must be free before a new transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppression time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
SYMBOL
MIN
MAX
UNITS
NOTES
tAA
0.2
1.3
200
0.9
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
1
tBUF
tDH
tF
tHD:DAT
tHD:STA
tHIGH
300
0
0.6
0.6
tI
tLOW
50
1.3
tR
0.3
400
fSCL
tSU:DAT
tSU:STA
t
SU:STO
tWRC
100
0.6
0.6
10
2
2
3
4
NOTE:
1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising
edge of SDA.
2. This parameter is sampled.
3. For a reSTART condition, or following a WRITE cycle.
4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of
the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA
remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
24
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 21: Serial Presence-Detect Matrix
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE
DESCRIPTION
0
1
2
3
4
Number of SPD Bytes Used by Micron
Total Number of Bytes in SPD Device
Fundamental Memory Type
Number of Row Addresses on Assembly
Number of Column Addresses on
Assembly
Number of Physical Ranks on DIMM
Module Data Width
Module Data Width (Continued)
Module Voltage Interface Levels
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
ENTRY (VERSION) MT9VDDT1672A MT9VDDT3272A MT9VDDT6472A
128
256
SDRAM DDR
12 or 13
10 or 11
80
08
07
0C
0A
80
08
07
0D
0A
80
08
07
0D
0B
1
72
0
SSTL 2.5V
5ns (-40B)
01
48
00
04
50
01
48
00
04
50
01
48
00
04
50
0.7ns (-40B)
70
70
70
ECC
15.62µs, 7.8µs/SELF
8
02
80
08
02
82
08
02
82
08
8
08
08
08
1 clock
01
01
01
2, 4, 8
4
0E
04
0E
04
0E
04
3, 2.5, 2
0
1
Unbuffered/Diff.
Clock
Fast/Concurrent AP
SDRAM Device Attributes: General
6ns (for PC2700
SDRAM Cycle Time, tCK (CAS Latency =
system compatibility)
2.5)
1C
01
02
20
1C
01
02
20
1C
01
02
20
C0
60
C0
60
C0
60
0.7ns (for PC 2700
system compatibility)
70
70
70
75
75
75
75
75
75
SDRAM Cycle Time, tCK (CAS Latency =
3)
SDRAM Access from Clock, tAC (CAS
Latency = 3)
Module Configuration Type
Refresh Rate/Type
SDRAM Device Width (Primary DDR
SDRAM)
Error-checking DDR SDRAM Data
Width
Minimum Clock Delay, Back-to-Back
Random Column Access
Burst Lengths Supported
Number of Banks on DDR SDRAM
Device
CAS Latencies Supported
CS Latency
WE Latency
SDRAM Module Attributes
24
SDRAM Access from CK, tAC (CAS
Latency = 2.5)
25
SDRAM Cycle Time, tCK (CAS Latency = 7.5ns (for PC 2100
and PC 1600 system
2)
compatibility)
0.75ns (for PC 2100
SDRAM Access from CK, tAC (CAS
and PC 1600 system
Latency = 2)
compatibility)
t
15ns (-40B)
Minimum Row Precharge Time, RP
26
27
28
Minimum Row Active to Row Active,
3C
3C
3C
10ns (-40B)
28
28
28
15ns (-40B)
3C
3C
3C
tRRD
29
Minimum RAS# to CAS# Delay, tRCD
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DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Table 21: Serial Presence-Detect Matrix (Continued)
“1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”
BYTE
30
DESCRIPTION
ENTRY (VERSION) MT9VDDT1672A MT9VDDT3272A MT9VDDT6472A
40ns (-40B)
28
28
28
20
40
80
60
60
60
31
Minimum RAS# Pulse Width, tRAS
Module Rank Density
32
Address And Command Setup Time, tIS
128MB, 256MB,
512MB
0.6ns (-40B)
33
Address And Command Hold Time, tIH
0.6ns (-40B)
60
60
60
34
Data/ Data Mask Input Setup Time, tDS
0.4ns (-40B)
40
40
40
Data/ Data Mask Input Hold Time, tDH
36-40 Reserved
41 Min Active Auto Refresh Time,tRC
0.4ns (-40B)
40
40
40
55ns (-40B)
00
37
00
37
00
37
35
42
Minimum Auto Refresh to Active/ Auto
Refresh Command Period, tRFC
70ns (-40B)
46
46
46
43
SDRAM Device Max Cycle Time, tCKMAX
SDRAM Device Max DQS-DQ Skew
Time, tDQSQ
SDRAM Device Max Read Data Hold
Skew Factor, tQHS
Reserved
DIMM Height
Reserved
SPD Revision
Checksum for Bytes 0-62
Manufacturer’s JEDEC ID Code
Manufacturer’s JEDEC ID Code
Manufacturing Location
Module Part Number (ASCII)
PCB Identification Code
Identification Code (Continued)
Year of Manufacture in BCD
Week of Manufacture in BCD
Module Serial Number
Manufacturer-Specific Data (RSVD)
12ns (-40B)
30
30
30
0.4ns (-40B)
28
28
28
0.5ns (-40B)
50
50
50
00
01
00
11
6F
2C
FF
01–0C
Variable Data
01-09
00
Variable Data
Variable Data
Variable Data
–
00
01
00
11
92
2C
FF
01–0C
Variable Data
01-09
00
Variable Data
Variable Data
Variable Data
–
00
01
00
11
D3
2C
FF
01–0C
Variable Data
01-09
00
Variable Data
Variable Data
Variable Data
–
44
45
46
47
48–61
62
63
64
65-71
72
73-90
91
92
93
94
95-98
99-127
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
Release 1.1
-40B
MICRON
(Continued)
01–12
1-9
0
26
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc.
128MB, 256MB, 512MB (x72, ECC, SR), PC3200
184-Pin DDR SDRAM UDIMM
Figure 14: 184-Pin DIMM Dimensions
0.125 (3.18)
MAX
FRONT VIEW
5.256 (133.50)
5.244 (133.20)
0.079 (2.00) R
(4X)
U1
U2
U3
U4
U5
U6
U7
U8
U9
U10
1.255 (31.88)
1.245 (31.62)
0.700 (17.78)
TYP.
0.098 (2.50) D
(2X)
0.091 (2.30) TYP.
0.035 (0.90) R
PIN 1
0.091 (2.30)
TYP.
PIN 92
0.250 (6.35) TYP.
0.050 (1.27)
TYP.
0.054 (1.37)
0.046 (1.17)
0.040 (1.02)
TYP.
4.750 (120.65)
BACK VIEW
NO COMPONENTS THIS SIDE
PIN 184
PIN 93
0.150 (3.80)
1.95 (49.53)
2.55 (64.77)
0.150 (3.80) 0.394 (10.00)
TYP.
TYP.
NOTE:
MAX
All dimensions in inches (millimeters); MIN or typical where noted.
Data Sheet Designation
Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete
power supply and temperature range for production
devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
®
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
E-mail: [email protected], Internet: http://www.micron.com, Customer Comment Line: 800-932-4992
Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
pdf: 09005aef80a43e7d, source: 09005aef80a43d77
DDA9C16_32_64x72AG.fm - Rev. B 9/04 EN
27
Micron Technology, Inc., reserves the right to change products or specifications without notice..
©2004 Micron Technology, Inc
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