TI1 OPA2325 Precision, 10-mhz, low-noise, low-power, rrio, cmos operational amplifier Datasheet

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OPA2325
SBOS637 – OCTOBER 2016
OPA2325
Precision, 10-MHz, Low-Noise, Low-Power, RRIO, CMOS Operational Amplifier
1 Features
3 Description
•
The OPA2325 device is a dual, precision, low-voltage
complementary metal oxide semiconductor (CMOS)
operational amplifier optimized for very low noise and
wide bandwidth when operating on a low quiescent
current of only 650 μA.
1
•
•
•
•
•
•
•
Precision with Zero-Crossover Distortion:
– Low Offset Voltage: 150 μV (max)
– High CMRR: 114 dB
– Rail-to-Rail I/O
Wide Bandwidth: 10 MHz
Quiescent Current: 650 μA/ch
Single-Supply Voltage Range: 2.2 V to 5.5 V
Low Input Bias Current: 0.2 pA
Low Noise: 9 nV/√Hz at 10 kHz
Slew Rate: 5 V/μs
Unity-Gain Stable
The OPA2325 features a linear input stage with zerocrossover distortion that delivers excellent commonmode rejection ratio (CMRR) of typically 114 dB over
the entire input range. The input common-mode
range extends 100 mV beyond the negative and
positive supply rails. The output voltage typically
swings within 10 mV of the rails.
The zero-crossover distortion combined with wide
bandwidth (10 MHz), high slew rate (5 V/µs), and low
noise (9 nV/√Hz) make the OPA2325 a very good
successive-approximation register (SAR) analog-todigital converter (ADC) input driver amplifier. The low
offset, and 0.2-pA input bias current make this device
ideal for a wide range of precision applications with
high-impedance sensors. The unique feature of
interfacing to high-impedance sensors on the input
and being able to drive ADC inputs with very little
distortion make the OPA2325 suitable for various
data acquisition and process control applications.
2 Applications
•
•
•
•
•
•
•
•
High-Z Sensor Signal Conditioning
Transimpedance Amplifiers
Test and Measurement Equipment
Programmable Logic Controllers (PLCs)
Motor Control Loops
Communications
Input, Output ADC and DAC Buffers
Active Filters
In addition, the OPA2325 has a wide supply voltage
range from 2.2 V to 5.5 V with excellent power-supply
rejection ratio (PSRR) over the entire supply range,
making the device suitable for precision, low-power
applications that run directly from batteries without
regulation.
Device Information(1)
Offset Voltage vs Input Common-Mode Voltage
PART NUMBER
150
OPA2325
125
100
PACKAGE
SOIC (8)
BODY SIZE (NOM)
3.91 mm × 4.90 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
75
VOS ( V)
50
25
The OPA2325 as an ADC Driver Amplifier
0
±25
3.3 V
±50
±75
VREF
VCM = ±2.85 V
±100
R
VCM = 2.85 V
±125
±3
±2
±1
0
VCM (V)
1
2
ADC
OPA2325
Input
±150
3
+
C
VSS
VDD
C003
5V
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
OPA2325
SBOS637 – OCTOBER 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configurations and Functions .......................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics: VS = 2.2 V to 5.5 V or
±1.1 V to ±2.75 V .......................................................
6.6 Typical Characteristics ..............................................
7
7.4 Device Functional Modes........................................ 16
8
Application and Implementation ........................ 17
8.1 Application Information............................................ 17
8.2 Typical Application .................................................. 18
9 Power Supply Recommendations...................... 23
10 Layout................................................................... 23
10.1 Layout Guidelines ................................................. 23
10.2 Layout Example .................................................... 24
11 Device and Documentation Support ................. 25
11.1
11.2
11.3
11.4
11.5
11.6
5
7
Detailed Description ............................................ 14
7.1 Overview ................................................................. 14
7.2 Functional Block Diagram ....................................... 14
7.3 Feature Description................................................. 15
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
25
25
25
25
25
25
12 Mechanical, Packaging, and Orderable
Information ........................................................... 25
4 Revision History
2
DATE
REVISION
NOTES
October 2016
*
Initial release.
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5 Pin Configurations and Functions
D Package
8-Pin SOIC
Top View
OUT A
1
8
V+
-IN A
2
7
OUT B
+IN A
3
6
-IN B
V-
4
5
+IN B
Pin Functions
PIN
NAME
NO.
I/O
DESCRIPTION
–IN A
2
I
Inverting input, channel A
+IN A
3
I
Noninverting input, channel A
–IN B
6
I
Inverting input, channel B
+IN B
5
I
Noninverting input, channel B
OUT A
1
O
Output, channel A
OUT B
7
O
Output, channel B
V–
4
—
Negative supply voltage
V+
8
—
Positive supply voltage
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1)
MIN
Supply voltage
VS = (V+) – (V–)
Voltage
Signal input pins
(2)
Current (2)
Specified, TA
(V+) + 0.5
V
–10
10
mA
–40
mA
125
Junction, TJ
150
Storage, Tstg
(3)
V
Continuous
Temperature
(2)
UNIT
6
(V–) – 0.5
Output short-circuit (3)
(1)
MAX
–65
°C
150
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Input pins are diode-clamped to the power-supply rails. Input signals that can swing more than 0.5 V beyond the supply rails must be
current limited to 10 mA or less.
Short-circuit to ground, one amplifier per package.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1)
±4000
Charged-device model (CDM), per JEDEC specification JESD22-C101 (2)
±1000
UNIT
V
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
VS
Single supply
Supply voltage
Dual supply
Specified temperature range
NOM
MAX
2.2
5.5
±1.1
±2.75
–40
125
UNIT
V
°C
6.4 Thermal Information
OPA2325
THERMAL METRIC
(1)
D (SOIC)
UNIT
8 PINS
RθJA
Junction-to-ambient thermal resistance
119.1
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
59.5
°C/W
RθJB
Junction-to-board thermal resistance
61.1
°C/W
ψJT
Junction-to-top characterization parameter
15.0
°C/W
ψJB
Junction-to-board characterization parameter
60.4
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
N/A
°C/W
(1)
4
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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6.5 Electrical Characteristics: VS = 2.2 V to 5.5 V or ±1.1 V to ±2.75 V
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
40
150
µV
2
7.5
µV/°C
6
20
OFFSET VOLTAGE
VOS
Input offset voltage
dVOS/dT
Input offset voltage drift
PSRR
Power-supply rejection ratio
Channel separation
VS = 5.5 V, TA = –40°C to +125°C
VS = 2.2 V to +5.5 V
VS = 2.2 V to 5.5 V, TA = –40°C to +125°C
µV/V
15
At 1 kHz
130
dB
INPUT VOLTAGE
VCM
Common-mode voltage range
CMRR
Common-mode rejection ratio
(V–) – 0.1
VS = 5.5 V, (V–) – 0.1 V < VCM < (V+) + 0.1 V
TA = –40°C to +125°C
100
(V+) + 0.1
V
114
dB
95
INPUT BIAS CURRENT
±0.2
IB
Input bias current
TA = –40°C to +85°C
TA = –40°C to +125°C
Input offset current
pA
±10
±0.2
IOS
±10
±500
nA
±10
TA = –40°C to +85°C
±500
TA = –40°C to +125°C
±10
pA
nA
NOISE
Input voltage noise
en
Input voltage noise density
in
Input current noise density
f = 0.1 Hz to 10 Hz
2.8
f = 1 kHz
10
f = 10 kHz
9
f = 1 kHz
1.3
µVPP
nV/√Hz
fA/√Hz
INPUT CAPACITANCE
Differential
5
pF
Common-mode
4
pF
OPEN-LOOP GAIN
AOL
Open-loop voltage gain
PM
Phase margin
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ
105
130
0.1 V < VO < (V+) – 0.1 V, RL = 10 kΩ,
TA = –40°C to +125°C
95
128
100
110
0.2 V < VO < (V+) – 0.2 V, RL = 2 kΩ
dB
G = 1 V/V, VS = 5 V, CL = 15 pF
67
Degrees
10
MHz
5
V/μs
FREQUENCY RESPONSE (VS = 5.0 V, CL = 50 pF)
GBP
Gain bandwidth product
Unity gain
SR
Slew rate
G = +1
tS
Settling time
Overload recovery time
THD+N
(1)
Total harmonic distortion + noise (1)
To 0.1%, 2-V step, G = +1
To 0.01%, 2-V step, G = +1
VIN × G > VS
0.6
1
200
VO = 4 VPP, G = +1, f = 10 kHz, RL = 10 kΩ
0.0005%
VO = 2 VPP, G = +1, f = 10 kHz, RL = 600 Ω
0.005%
µs
ns
Third-order filter; bandwidth = 80 kHz at –3 dB.
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Electrical Characteristics: VS = 2.2 V to 5.5 V or ±1.1 V to ±2.75 V (continued)
at TA = 25°C, RL = 10 kΩ connected to VS / 2, VCM = VS / 2, and VOUT = VS / 2 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
10
20
UNIT
OUTPUT
RL = 10 kΩ
VO
Voltage output swing from both rails
ISC
Short-circuit current
CL
Capacitive load drive
RO
Open-loop output resistance
RL = 10 kΩ, TA = –40°C to +125°C
30
RL = 2 kΩ
25
45
RL = 2 kΩ, TA = –40°C to +125°C
VS = 5.5 V
mV
55
See the Typical Characteristics
mA
See the Typical Characteristics
IO = 0 mA, f = 1 MHz
180
Ω
POWER SUPPLY
VS
IQ
Specified voltage range
Quiescent current per amplifier
Power-on time
2.2
IO = 0 mA, VS = 5.5 V
5.5
0.65
IO = 0 mA, VS = 5.5 V, TA = –40°C to +125°C
0.75
0.8
V+ = 0 V to 5 V, to 90% IQ level
28
V
mA
µs
TEMPERATURE
6
Specified range
–40
125
°C
Operating range
–40
150
°C
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6.6 Typical Characteristics
at TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted)
15
20
Amplifiers (%)
Amplifiers (%)
15
10
5
10
5
7.5
6
4.5
3
1.5
0
-1.5
-3
C001
C002
Figure 1. Offset Voltage Production Distribution Histogram
Figure 2. Offset Voltage Drift Distribution Histogram
150
500
125
400
100
300
75
200
VOS ( V)
50
VOS ( V)
-6
-7.5
150
100
0
-50
-100
-150
50
Offset Voltage Drift (µV/ƒC)
Offset Voltage (µV)
25
0
±25
±50
100
0
±100
±200
±75
±300
VCM = ±2.85 V
±100
VCM = 2.85 V
±125
±400
±500
±150
±3
±2
0
±1
1
2
3
VCM (V)
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
C003
Figure 3. Offset Voltage vs Common-Mode Voltage
150
C010
Figure 4. Offset Voltage vs Temperature
150
180
140
120
100
Gain
135
Phase
90
60
40
Phase (deg)
80
50
VOS ( V)
100
Gain (dB)
-4.5
0
0
0
±50
VS = ± 1.1 V
45
20
VS = ± 2.75 V
±100
0
0
±20
1
10
100
1k
10k
100k
1M
±150
10M
Frequency (Hz)
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
VSUPPLY (V)
C200
3.0
C017
CL = 15 pF
Figure 5. Open-Loop Gain and Phase vs Frequency
Figure 6. Offset Voltage vs Supply Voltage
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted)
40.0
40.0
30.0
30.0
20.0
VS = ± 1.1 V
10.0
AOL (µV/V)
AOL (µV/V)
20.0
0.0
VS = ± 2.75 V
±10.0
VS = ±1.1 V
10.0
0.0
VS = ±2.75 V
±10.0
±20.0
±20.0
±30.0
±30.0
±40.0
±40.0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
±75
150
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
C005
C006
RL = 2 kΩ
RL = 10 kΩ
Figure 8. Open-Loop Gain vs Temperature
Figure 7. Open-Loop Gain vs Temperature
1000
800
900
700
800
500
600
IQ (µA)
IQ (µA)
600
VS = ± 2.75 V
700
VS = ± 1.1 V
500
400
400
300
300
200
200
100
100
0
0
±75
±50
±25
0
25
50
75
100
125
Temperature (ƒC)
150
0
0.5
1
1.5
2
2.5
3
Supply Voltage (V)
C007
Figure 9. Quiescent Current vs Temperature
C004
Figure 10. Quiescent Current vs Supply Voltage
20
10
6
15
4
Amplifiers (%)
Input Bias Current (pA)
8
2
0
±2
±4
10
5
±6
±8
±2
±1
0
VCM (V)
1
2
3
8
2
1
Input Bias Current (pA)
C013
Figure 11. Input Bias Current vs Common-Mode Voltage
0
-2
±3
-1
0
±10
C015
Figure 12. Input Bias Current Distribution Histogram
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted)
2.0
25
Input Bias Current (nA)
Amplifiers (%)
20
15
10
5
1.0
0.5
IOS
0.0
2
1
0
-1
-2
0
1.5
±75
Input Offset Current (pA)
±50
±25
0
3
0
2.5
-0.5
125°C
2
-1
85°C
1.5
VO (V)
VO (V)
50
25°C
125°C
1
100
125
150
C014
-1.5
-2
±40°C
±40°C
85°C
0.5
75
Figure 14. Input Bias Current vs Temperature
Figure 13. Input Offset Current Distribution Histogram
-2.5
0
25°C
-3
0
10
20
30
40
50
60
IO (mA)
0
10
20
30
40
50
IO (mA)
C009A
Figure 15. Output Voltage Swing (Positive) vs
Output Current
60
C009B
Figure 16. Output Voltage Swing (Negative) vs
Output Current
60
Power-Supply Rejection Ratio (dB),
Common-Mode Rejection Ratio (dB)
120
ISC, Sink
50
40
ISC (mA)
25
Temperature (ƒC)
C016
30
20
ISC, Source
10
PSRR+
100
80
60
CMRR
PSRR-
40
20
0
0
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
1
C008
Figure 17. Short-Circuit Current vs Temperature
10
100
1k
10k
100k
Frequency (Hz)
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C203
Figure 18. CMRR and PSRR vs Frequency
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Typical Characteristics (continued)
15
20
Power-Supply Rejection Ratio (µV/V)
Common-Mode Rejection Ratio (µV/V)
at TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted)
10
5
0
-5
-10
-15
15
10
5
0
-5
-10
-15
-20
±75
±50
±25
0
25
50
75
100
125
150
Temperature (ƒC)
±75
±25
0
25
75
100
125
150
C012
Figure 20. PSRR vs Temperature
1k
Voltage
(500 nV/div)
100
10
1
1
10
100
1k
10k
100k
Frequency (Hz)
Time
(1 s/div)
C205
Figure 21. Input Voltage Noise Spectral Density vs
Frequency
60
G = +100
G = +100
40
Gain (dB)
40
Gain (dB)
C204
Figure 22. 0.1-Hz to 10-Hz Input Voltage Noise
60
G = +10
20
G = +10
20
G = +1
G = +1
0
0
-20
-20
100
1k
10k
100k
1M
100
10M
Frequency (Hz)
1k
10k
100k
1M
10M
Frequency (Hz)
C201
VS = 1.8 V, RL = 10 kΩ, CL = 15 pF
C202
VS = 5.5 V, RL = 10 kΩ, CL = 15 pF
Figure 23. Closed-Loop Gain vs Frequency
10
50
Temperature (ƒC)
Figure 19. CMRR vs Temperature
Voltage Noise Spectral Density (nV/¥Hz)
±50
C011
Figure 24. Closed-Loop Gain vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted)
10k
Open-Loop Output Impedance
7
Output Voltage (VPP)
6
VS = ±2.5 V
5
4
3
VS = ±0.9 V
2
1
0
100
1k
10k
100k
1M
100
10m 100m 1
10M
Frequency (Hz)
Overshoot (%)
50
G = 1, VS = 5.5 V
G = 10, VS = 5.5 V
20
10
G = 10, VS = 5.5 V
200
400
600
800
C025
-60
0.1
G = -1, RL = 600 Ÿ
G = +1, RL = 600 Ÿ
0.01
-80
G = -1,
RL = 2 kŸ
0.001
-100
G = -1,
RL = 10 kŸ
G = +1, RL = 10 kŸ
G = +1, RL = 2 kŸ
0.0001
0.001
1000
Capacitive Load (pF)
10k 100k 1M 10M 100M 1G
Figure 26. Open-Loop Output Impedance vs Frequency
0
0
1k
Frequency (Hz)
Total Harmonic Distortion + Noise (%)
60
G = 1, VS = 1.8 V
100
Total Harmonic Distortion + Noise (dB)
70
30
10
C218
Figure 25. Maximum Output Voltage vs Frequency
40
1k
-120
0.01
0.1
1
Output Amplitude (VRMS)
C209
C208
f = 10 kHz, VS = ±2.5 V, filter bandwidth = 500 kHz
G = +1, RL = 600 Ÿ
0.1
-60
G = -1, RL = 2 kŸ
-80
G = -1, RL = 10 kŸ
0.01
-100
G = +1, RL = 2 kŸ
0.001
-120
G = +1, RL = 10 kŸ
-140
100k
0.0001
10
100
1k
10k
Frequency (Hz)
1
G = +1, RL = 600 Ÿ
0.1
-60
G = -1, RL = 2 kŸ
0.01
-80
G = -1, RL = 10 kŸ
G = +1, RL = 2 kŸ
0.001
-100
G = +1,
RL = 10 kŸ
0.0001
10
100
1k
10k
-120
100k
Frequency (Hz)
C206
VIN = 2 VPP, VS = ±2.5 V, filter bandwidth = 500 kHz
-40
G = -1, RL = 600 Ÿ
Total Harmonic Distortion + Noise (dB)
G = -1, RL = 600 Ÿ
Figure 28. THD+N vs Amplitude
Total Harmonic Distortion + Noise (%)
-40
1
Total Harmonic Distortion + Noise (dB)
Total Harmonic Distortion + Noise (%)
Figure 27. Small-Signal Overshoot vs Load Capacitance
C004
VIN = 4 VPP, VS = ±2.5 V, filter bandwidth = 500 kHz
Figure 29. THD+N vs Frequency
Figure 30. THD+N vs Frequency
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted)
VIN
5 V/div
1.25 V/div
VOUT
VIN
VOUT
Time (50 ms/div)
Time (100 µs/div)
C210
C212
Figure 31. No Phase Reversal
Figure 32. Positive Overload Recovery
6
Slew Rate (Rising)
Slew Rate (V/µs)
5.8
1 V/div
VIN
VOUT
5.6
5.4
Slew Rate (Falling)
5.2
5
Time (100 µs/div)
2
2.5
3
3.5
4
4.5
5
Supply Voltage (V)
C211
5.5
C219
CL = 15 pF
Figure 33. Negative Overload Recovery
Figure 34. Slew Rate vs Supply Voltage
VOUT
VIN
2.5 mV/div
100 µV/div
0.01% Settling = “200 µV
Time (1 µs/div)
Time (2.5 µs/div)
C217
C213
VIN = 2-V step
VIN = 10 mVPP, G = +1, CL = 15 pF
Figure 35. Small-Signal Step Response
12
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Figure 36. 0.01% Positive Settling Time
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Typical Characteristics (continued)
at TA = 25°C, VCM = VOUT = mid-supply, and RL = 10 kΩ (unless otherwise noted)
VOUT
1 V/div
100 µV/div
0.01% Settling = “200 µV
VIN
Time (1 µs/div)
Time (2.5 µs/div)
C216
C215
VIN = 2-V step
VIN = 4 VPP, G = +1, CL = 15 pF
1 V/div
Figure 37. 0.01% Negative Settling Time
Figure 38. Large-Signal Step Response
VOUT
VIN
Time (2.5 µs/div)
C214
VIN = 4 VPP, G = –1, CL = 15 pF
Figure 39. Large-Signal Step Response
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7 Detailed Description
7.1 Overview
The OPA2325 belongs to a new generation of low-noise, e-trim™ operational amplifiers that provide outstanding
dc precision. The OPA2325 also has a highly linear input stage with zero-crossover distortion that delivers
excellent CMRR and distortion performance across the full rail-to-rail input range. In addition, this device has a
wide supply range with excellent PSRR. This feature, combined with low quiescent current, makes the OPA2325
suitable for applications that are battery-powered without regulation.
7.2 Functional Block Diagram
V+
OPA2325
Charge
Pump
IN
OUT
+IN
POR
e-trimTM
V
Copyright © 2016, Texas Instruments Incorporated
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7.3 Feature Description
7.3.1 Zero-Crossover Input Stage
Traditional complementary metal oxide semiconductor (CMOS) rail-to-rail input amplifiers use a complementary
input stage: an N-channel input differential pair in parallel with a P-channel differential pair. This configuration
results in sudden change in offset voltage when the input stage transitions from the p-channel metal-oxidesemiconductor field effect transistor (PMOS) to the n-type field effect transistor (NMOS), or vice-versa, as shown
in Figure 40. This transition results in significant degradation of CMRR and PSRR performance of the amplifier.
.
Input Offset Voltage (mV)
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
Figure 40. Input Common-Mode Voltage vs Input Offset Voltage
(Traditional Rail-to-Rail Input CMOS Amplifiers)
The OPA2325 amplifier includes an internal charge pump that powers the amplifier input stage with an internal
supply rail that is higher than the external power supply. The internal supply rail allows a single differential pair to
operate and to be linear across the entire input common-mode voltage range, thus eliminating crossover
distortion. Rail-to-rail amplifiers that use this technique to eliminate crossover distortion are called zero-crossover
amplifiers.
The single differential pair combined with the charge pump allows the OPA2325 to provide superior CMRR
across the entire common-mode input range, which extends 100 mV beyond both power-supply rails. Figure 41
shows the input offset voltage versus input common-mode voltage plot for the OPA2325. Note that unlike
traditional rail-to-rail CMOS amplifiers, there is no transition region for the OPA2325.
150
125
100
75
VOS ( V)
50
25
0
±25
±50
±75
VCM = ±2.85 V
±100
VCM = 2.85 V
±125
±150
±3
±2
±1
0
1
VCM (V)
2
3
C003
Figure 41. Offset Voltage vs Common-Mode Voltage (Zero-Crossover)
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Feature Description (continued)
7.3.2 Low Input Offset Voltage
The OPA2325 is manufactured using TI's e-trim™ technology. Each amplifier is trimmed in production, thereby
minimizing errors associated with input offset voltage. The e-trim™ technology is a TI proprietary method of
trimming internal device parameters during either wafer probing or final testing. This process allows the
OPA2325 to have excellent offset specifications of 150 µV (max). Figure 42 shows the offset voltage distribution
for the OPA2325.
Amplifiers (%)
15
10
5
150
100
50
0
-50
-100
-150
0
Offset Voltage (µV)
C002
Figure 42. Offset Voltage Distribution
7.3.3 Input and ESD Protection
The OPA2325 incorporates internal electrostatic discharge (ESD) protection circuits on all pins. In the case of
input and output pins, this protection primarily consists of current-steering diodes connected between the input
and power-supply pins. These ESD protection diodes also provide in-circuit, input overdrive protection, as long
as the current is limited to 10 mA as stated in the Absolute Maximum Ratings table. Figure 43 shows how a
series input resistor can be added to the driven input to limit the input current. The added resistor contributes
thermal noise at the amplifier input; thus, keep the value to a minimum in noise-sensitive applications.
V+
IOVERLOAD
10-mA max
TI Device
VOUT
VIN
5 kW
Copyright © 2016, Texas Instruments Incorporated
Figure 43. Input Current Protection
7.4 Device Functional Modes
The OPA2325 has a single functional mode and is operational when the power-supply voltage is greater than
2.2 V (±1.1 V). The maximum power-supply voltage for the OPA2325 is 5.5 V (±2.75 V).
16
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The OPA2325 is an e-trim™ operational amplifier built via a proprietary technique in which offset voltage is
adjusted during the final steps of manufacturing. As a result, the OPA2325 delivers excellent offset voltage
(40 μV, typical). Additionally, the amplifier boasts a fast slew rate, low drift, low noise, and excellent PSRR and
AOL. The OPA2325 also features a linear input stage with zero-crossover distortion, resulting in excellent CMRR
over the entire input range, which extends from 100 mV below the negative rail to 100 mV above the positive rail.
8.1.1 Operating Characteristics
The OPA2325 family of amplifiers has parameters that are fully specified from 2.2 V to 5.5 V (±1.1 V to ±2.75 V).
Many of the specifications apply from –40°C to +125°C. Parameters that can exhibit significant variance with
regard to operating voltage or temperature are presented in the Typical Characteristics section.
8.1.2 Basic Amplifier Configurations
The OPA2325 is unity-gain stable. The device does not exhibit output phase inversion when the input is
overdriven. A typical single-supply connection is shown in Figure 44. The OPA2325 is configured as a basic
inverting amplifier with a gain of –10 V/V. This single-supply connection has an output centered on the commonmode voltage, VCM. For the circuit shown, this voltage is 2.5 V, but can be any value within the common-mode
input voltage range.
R2
10 kW
5V
C1
100 nF
R1
1 kW
OPA2325
VOUT
VIN
VCM = 2.5 V
Copyright © 2016, Texas Instruments Incorporated
Figure 44. Basic Single-Supply Connection
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Application Information (continued)
8.1.3 Driving an Analog-to-Digital Converter
The low-noise and wide-gain bandwidth of the OPA2325, combined with rail-to-rail input/output and zerocrossover distortion, make the device an ideal input driver for ADCs. Figure 45 shows the OPA2325 driving an
ADC. The amplifier is connected as a unity-gain, noninverting buffer.
3.3 V
VREF
R
ADC
OPA2325
Input
+
VSS
C
VDD
5V
Copyright © 2016, Texas Instruments Incorporated
Figure 45. The OPA2325 as an Input Driver for ADCs
8.2 Typical Application
Operational amplifiers are commonly used as unity-gain buffers. Figure 46 shows the schematic for an amplifier
configured as a unity-gain buffer. If the input signal range to the amplifier is very close to the rails or includes the
rails, a rail-to-rail amplifier must be used. However, regular rail-to-rail amplifiers introduce significant distortion to
the signal. This design compares the distortion introduced by a typical CMOS input amplifier with that of the
OPA2325 (a zero-crossover amplifier).
2.5 V
±
VOUT
+
4-VPP
Sine Wave
OPA2325
-2.5 V
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 46. The OPA2325 Configured as a Unity-Gain Buffer Amplifier
8.2.1 Design Requirements
The following parameters are used for this design example:
• Gain = +1 V/V (inverting gain)
• V+ = 2.5 V, V– = –2.5 V
• Input signal = 4 VPP, f = 1-kHz sine wave
18
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Typical Application (continued)
8.2.2 Detailed Design Procedure
Traditional CMOS rail-to-rail input amplifiers use a complementary input stage: an N-channel input differential
pair in parallel with a P-channel differential pair, as shown in Figure 47.
+VSUPPLY
IS1
VIN-
PCH1
PCH2
NCH3
NCH4
VIN+
e-TrimTM
-VSUPPLY
Copyright © 2016, Texas Instruments Incorporated
Figure 47. Complementary Input Stage (Traditional Rail-to-Rail Input CMOS Amplifiers)
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Typical Application (continued)
The N-channel pair is active for input voltages close to the positive rail, typically (V+) – 1 V to 200 mV above the
positive supply, and the P-channel pair is on for inputs from 200 mV below the negative supply to approximately
(V+) – 1 V. There is a small transition region, typically (V+) – 1.1 V to (V+) – 0.9 V, in which both pairs are on.
This transition region is shown in Figure 48 for a traditional rail-to-rail input CMOS amplifier. Within this transition
region, PSRR, CMRR, offset voltage, offset drift, and THD can be degraded when compared to device operation
outside of this region.
Input Offset Voltage (mV)
3
2
1
0
-1
-2
-V
+V
-3
-0.5 0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Input Common-Mode Voltage (V)
Figure 48. Input Offset Voltage vs Common-Mode Voltage
(For Traditional Rail-to-Rail Input CMOS Amplifiers)
The OPA2325 amplifier includes an internal charge pump that powers the amplifier input stage with an internal
supply rail that is higher than the external power supply. The internal supply rail allows a single differential pair to
operate and to be linear across the entire input common-mode voltage range, as shown in Figure 49.
+VSUPPLY
Charge Pump
IS1
PCH1
PCH2
VIN+
VIN-
e-TrimTM
-Vsupply
Figure 49. Single Differential Input Pair with a Charge Pump (Zero-Crossover)
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Typical Application (continued)
The unique zero-crossover topology shown in Figure 49 eliminates the input offset transition region, typical of
most rail-to-rail input operational amplifiers. This topology allows the OPA2325 to provide superior CMRR across
the entire common-mode input range that extends 100 mV beyond both power-supply rails. Figure 50 shows the
input offset voltage versus input common-mode voltage plot for the OPA2325.
150
125
100
75
VOS ( V)
50
25
0
±25
±50
±75
VCM = ±2.85 V
±100
VCM = 2.85 V
±125
±150
±3
±2
±1
0
1
2
VCM (V)
3
C003
Figure 50. Offset Voltage vs Common-Mode Voltage (OPA2325, Zero-Crossover Amplifier)
The OPA2325 and a typical CMOS amplifier were used in identical circuits where these amplifiers were
configured as a unity-gain buffer amplifier; see Figure 51 and Figure 52. A pure sine wave with an amplitude of
2 V (4 VPP) was given as input to the two identical circuits of Figure 51 and Figure 52. The outputs of these
circuits were captured on a spectrum analyzer. Figure 53 and Figure 54 illustrate the output voltage spectrum for
the OPA2325 and a typical CMOS rail-to-rail amplifier, respectively. The output of the OPA2325 has very few
spurs and harmonics when compared to the typical rail-to-rail CMOS amplifier, as illustrated in Figure 55.
2.5 V
2.5 V
±
±
+
4-VPP
Sine Wave
VOUT
VOUT
+
OPA2325
Typical CMOS
-2.5 V rail-to-rail amplifiers
4-VPP
Sine Wave
-2.5 V
GND
GND
Copyright © 2016, Texas Instruments Incorporated
Figure 51. OPA2325 as a Unity-Gain Buffer
Figure 52. Typical CMOS Rail-to-Rail Amplifier as a UnityGain Buffer
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Typical Application (continued)
8.2.3 Application Curves
20
0
0
±20
±20
±40
±40
Power (dB)
Power (dB)
20
±60
±80
±100
±60
±80
±100
±120
±120
±140
±140
±160
±160
±180
±180
0.
5k
10k
15k
0.
20k
Frequency (Hz)
5k
10k
15k
Frequency (Hz)
C051
Figure 53. Output Voltage Spectrum (OPA2325)
20k
C053
Figure 54. Output Voltage Spectrum
(Typical CMOS Rail-to-Rail Amplifier)
0
THD + N (dB)
±20
±40
Typical rail-to-rail CMOS amplifier
±60
±80
OPA2325
±100
±120
0.
5k
10k
15k
Frequency (Hz)
20k
C052
Figure 55. THD+N vs Frequency
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9 Power Supply Recommendations
The OPA2325 is specified for operation from 2.2 V to 5.5 V (±1.1 V to ±2.75 V); many specifications apply from
–40°C to +125°C. Parameters that can exhibit significant variance with regard to operating voltage or
temperature are presented in the Typical Characteristics section.
10 Layout
10.1 Layout Guidelines
For best operational performance of the device, use good printed circuit board (PCB) layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and of op amp
itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for singlesupply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground
planes. A ground plane helps distribute heat and reduces electromagnetic interference (EMI) noise
pickup. Make sure to physically separate digital and analog grounds, paying attention to the flow of the
ground current. For more detailed information refer to, see Circuit Board Layout Techniques.
• In order to reduce parasitic coupling, run the input traces as far away from the supply or output traces as
possible. If these traces cannot be kept separate, crossing the sensitive trace perpendicular is much
better as opposed to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As illustrated in Figure 57, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly
reduce leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts resulting from moisture ingress into the
plastic package. Following any aqueous PCB cleaning process, baking the PCB assembly is
recommended to remove moisture introduced into the device packaging during the cleaning process. A
low-temperature, post-cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
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10.2 Layout Example
+
VIN A
+
VIN B
VOUT A
RG
VOUT B
RG
RF
RF
Figure 56. Schematic Representation for Figure 57
Place components
close to device and to
each other to reduce
parasitic errors.
OUT A
VS+
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
OUT A
V+
-IN A
OUT B
+IN A
-IN B
RF
OUT B
GND
RF
RG
VIN A
GND
RG
V±
Use low-ESR,
ceramic bypass
capacitor. Place as
close to the device
as possible.
GND
VS±
+IN B
Ground (GND) plane on another layer
VIN B
Keep input traces short
and run the input traces
as far away from
the supply lines
as possible.
Figure 57. Layout Example
24
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11 Device and Documentation Support
11.1 Documentation Support
11.1.1 Related Documentation
For related documentation see the following:
Circuit Board Layout Techniques (SLOA089)
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
e-trim, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
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18-Oct-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA2325ID
ACTIVE
SOIC
D
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2325
OPA2325IDR
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 125
O2325
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2016
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Oct-2016
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA2325IDR
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.4
B0
(mm)
K0
(mm)
P1
(mm)
5.2
2.1
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
13-Oct-2016
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA2325IDR
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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