ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 16-Bit, High-Speed, 2.7V to 5.5V microPower Sampling ANALOG-TO-DIGITAL CONVERTER Check for Samples: ADS8326 FEATURES APPLICATIONS • • • • • 1 23 • • • • • • • 16 Bits No Missing Codes (Full-Supply Range, High or Low Grade) Very Low Noise: 3LSBPP Excellent Linearity: ±1LSB typ, ±1.5LSB max INL ±0.6LSB typ, ±1LSB max DNL ±1mV max Offset ±12LSB typ Gain Error microPower: 10mW at 5V, 250kHz 4mW at 2.7V, 200kHz 2mW at 2.7V, 100kHz 0.2mW at 2.7V, 10kHz MSOP-8 and SON-8 Packages (SON-8 package same as 3x3 QFN) 16-Bit Upgrade to the 12-Bit ADS7816 and ADS7822 Pin-Compatible with the ADS7816, ADS7822, ADS7826, ADS7827, ADS7829, ADS8320, and ADS8325 Serial ( SPI™/SSI) Interface • • • Battery-Operated Systems Remote Data Acquisition Isolated Data Acquisition Simultaneous Sampling, Multichannel Systems Industrial Controls Robotics Vibration Analysis DESCRIPTION The ADS8326 is a 16-bit, sampling, analog-to-digital (A/D) converter specified for a supply voltage range from 2.7V to 5.5V. It requires very little power, even when operating at the full data rate. At lower data rates, the high speed of the device enables it to spend most of its time in the power-down mode. For example, the average power dissipation is less than 0.2mW at a 10kHz data rate. The ADS8326 offers excellent linearity and very low noise and distortion. It also features a synchronous serial (SPI/SSI-compatible) interface and a differential input. The reference voltage can be set to any level within the range of 0.1V to VDD. Low power and small size make the ADS8326 ideal for portable and battery-operated systems. It is also a perfect fit for remote data-acquisition modules, simultaneous multichannel systems, and isolated data acquisition. The ADS8326 is available in either an MSOP-8 and an SON-8 package. SAR REF ADS8326 DOUT +IN CDAC Serial Interface -IN DCLOCK S/H Amp Comparator CS/SHDN 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. SPI is a trademark of Motorola, Inc. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2007–2009, Texas Instruments Incorporated ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. ORDERING INFORMATION (1) PRODUCT MAXIMUM INTEGRAL LINEARITY ERROR (LSB) (2) NO MISSING CODES ERROR (LSB) PACKAGELEAD PACKAGE DESIGNATOR SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ADS8326I ±3 16 MSOP-8 DGK –40°C to +85°C D26 ADS8326IB ADS8326I ADS8326IB (1) (2) ±1.5 16 ±3 16 ±1.5 16 MSOP-8 DGK SON-8 DRB SON-8 DRB –40°C to +85°C –40°C to +85°C –40°C to +85°C ORDERING NUMBER TRANSPORT MEDIA, QUANTITY ADS8326IDGKT Tape and Reel, 250 ADS8326IDGKR Tape and Reel, 2500 ADS8326IBDGKT Tape and Reel, 250 ADS8326IBDGKR Tape and Reel, 2500 ADS8326IDRBT Tape and Reel, 250 ADS8326IDRBR Tape and Reel, 2500 ADS8326IBDRBT Tape and Reel, 250 ADS8326IBDRBR Tape and Reel, 2500 D26 D26 D26 For the most current package and ordering information, see the Package Option Addendum located at the end of this data sheet, or see the TI website at www.ti.com. Maximum Integral Linearity Error specifies a 5V power supply and reference voltage. ABSOLUTE MAXIMUM RATINGS (1) Over operating free-air temperature range (unless otherwise noted). ADS8326 UNIT –0.3 to +7 V –0.3 to VDD + 0.3 V –0.3 to VDD + 0.3 V Supply voltage, VDD to GND Analog input voltage (2) Reference input voltage (2) Digital input voltage (2) –0.3 to VDD + 0.3 V –20 to +20 mA Input current to any pin except supply Power dissipation See Dissipation Ratings Table Operating virtual junction temperature range, TJ –40 to +150 °C Operating free-air temperature range, TA –40 to +85 °C Storage temperature range, TSTG –65 to +150 °C +260 °C Lead Temperature 1.6mm (1/16 inch) from case for 10sec (1) (2) 2 Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum rated conditions for extended periods may affect device reliability. All voltage values are with respect to ground terminal. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 DISSIPATION RATINGS PACKAGE R θ JC R θ JA DERATING FACTOR ABOVE TA = +25°C DGK +39.1°C/W +206.3°C/W 4.847mW/°C 606mW 388mW 315mW DRB +5°C/W +45.8°C/W 3.7mW/°C 370mW 204mW 148mW TA ≤ +25°C POWER RATING TA = +70°C POWER RATING TA = +85°C POWER RATING RECOMMENDED OPERATING CONDITIONS MIN Supply voltage, GND to VDD Low-voltage levels 2.7 Supply voltage, GND to VDD 5V logic levels 4.5 Reference input voltage TYP 5.0 0.1 Analog input voltage UNIT 3.6 V 5.5 V VDD V –IN to GND –0.3 0.5 V +IN to GND –0.3 VDD + 0.2 V +IN – (–IN) 0 VREF V –40 +125 °C Operating junction temperature, TJ 0 MAX ELECTRICAL CHARACTERISTICS: VDD = +5V At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 250kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER TEST CONDITIONS MIN TYP ADS8326IB MAX MIN TYP MAX UNIT V ANALOG INPUT Full-scale range FSR +IN – (–IN) Operating common-mode signal Input resistance RON 0 VREF 0 VREF –0.3 0.5 –0.3 0.5 –IN = GND, off 5 V 5 50 –IN = GND, during sampling 48 48 pF Input leakage current –IN = GND ±50 ±50 nA Differential input capacitance +IN to –IN, during sampling 20 20 pF 500 500 kHz Full-power bandwidth 50 Ω –IN = GND, on Input capacitance FS sinewave, SINAD = FSBW –60dB 100 GΩ 100 DC ACCURACY Resolution No missing codes Integral linearity error 16 16 NMC 16 16 INL –3 ±2 Bits Bits +3 –1.5 ±1 +1.5 LSB LSB Differential linearity error DNL –1 ±0.5 +2 –1 ±0.4 +1 Offset error VOS –1.5 ±0.75 +1.5 –1 ±0.5 +1 Offset error drift Gain error Gain error drift TCVOS ±0.2 GERR –24 TCGERR +24 –12 ±0.3 Noise 4.75V ≤ VDD ≤ 5.25V Power-supply rejection ±0.2 mV ppm/°C +12 LSB ±0.3 ppm/°C 30 30 μVRMS 0.5 0.5 LSB SAMPLING DYNAMICS Conversion time (16 DCLOCKs) Acquisition time (4.5 DCLOCKs) tCONV 24kHz ≤ fDCLOCK ≤ 6MHz tAQ fDCLOCK = 6MHz 2.667 0.75 Throughput rate (22 DCLOCKs) Clock frequency 666.7 2.667 0.024 6 0.024 250 kSPS 6 MHz Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 μs μs 0.75 250 fDCLOCK 666.7 3 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: VDD = +5V (continued) At –40°C to +85°C, VREF = +5V, –IN = GND, fSAMPLE = 250kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER TEST CONDITIONS MIN TYP ADS8326IB MAX MIN TYP MAX UNIT AC ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio Signal-to-noise + distortion Effective number of bits THD SFDR SNR SINAD ENOB 5VPP sinewave at 2kHz –98 –99 dB 5VPP sinewave at 10kHz –90 –91 dB 5VPP sinewave at 2kHz 102 103 dB 5VPP sinewave at 10kHz 94 95 dB 5VPP sinewave at 2kHz 91 91.5 dB 5VPP sinewave at 10kHz 91 91.5 dB 5VPP sinewave at 2kHz 90 91 dB 5VPP sinewave at 10kHz 87.5 88 dB 5VPP sinewave at 2kHz 14.69 14.86 Bits 5VPP sinewave at 10kHz 14.28 14.35 Bits VOLTAGE REFERENCE INPUT Reference voltage 0.1 CS = GND, fSAMPLE = 0Hz Reference input resistance CS = VDD Reference input capacitance Reference input current VDD 0.1 5 VDD V 5 GΩ 5 5 GΩ 24 24 pF fS = 250kHz 170 220 170 220 μA fS = 200kHz 140 180 140 180 μA fS = 100kHz 70 90 70 90 μA fS = 10kHz 11 14 11 14 μA CS = VDD 0.1 μA 0.1 DIGITAL INPUTS (1) Logic family CMOS CMOS High-level input voltage VIH 0.7 × VDD VDD + 0.3 0.7 × VDD VDD + 0.3 Low-level input voltage VIL –0.3 0.3 × VDD –0.3 0.3 × VDD V Input current IIN VI = VDD or GND –50 +50 –50 +50 nA Input capacitance CI 5 5 V pF DIGITAL OUTPUTS (1) Logic family CMOS High-level output voltage VOH VDD = 4.5V, IOH = –100μA Low-level output voltage VOL VDD = 4.5V, IOL = 100μA High-impedance state output current IOZ CS = VDD, VI = VDD or GND Output capacitance CO Load capacitance CL 4 4.44 V 0.5 –50 +50 5 –50 Straight binary 0.5 V +50 nA 5 30 Data format (1) CMOS 4.44 pF 30 pF Straight binary Applies for 5.0V nominal supply: VDD (min) = 4.5V and VDD (max) = 5.5V. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 ELECTRICAL CHARACTERISTICS: VDD = +2.7V At –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 200kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER TEST CONDITIONS MIN TYP ADS8326IB MAX MIN TYP MAX UNIT V ANALOG INPUT Full-scale range FSR +IN – (–IN) Operating common-mode signal Input resistance RON 0 VREF 0 VREF –0.3 0.5 –0.3 0.5 –IN = GND, off 5 –IN = GND, on 100 Input capacitance –IN = GND, during sampling Input leakage current –IN = GND Differential input capacitance +IN to –IN, during sampling FS sinewave, SINAD = FSBW –60dB Full-power bandwidth V 5 150 100 GΩ Ω 150 48 48 pF ±50 ±50 nA 20 20 pF 60 60 kHz DC ACCURACY Resolution No missing codes Integral linearity error 16 16 NMC 16 16 INL –3 ±2 Bits Bits +3 –2.5 ±1 +2.5 LSB LSB Differential linearity error DNL –1 ±0.5 +2 –1 ±0.4 +1 Offset error VOS –1.5 ±0.75 +1.5 –1 ±0.5 +1 Offset error drift ±0.2 ±0.2 ppm/°C GERR ±33 ±16 LSB TCGERR ±0.3 ±0.3 ppm/°C 30 30 μVRMS 0.5 0.5 LSB Gain error Gain error drift mV TCVOS Noise 2.7V ≤ VDD ≤ 3.6V Power-supply rejection SAMPLING DYNAMICS Conversion time (16 DCLOCKs) Acquisition time (4.5 DCLOCKs) tCONV 24kHz ≤ fDCLOCK ≤ 4.8MHz tAQ fDCLOCK = 4.8MHz 3.333 666.7 0.9375 666.7 200 fDCLOCK 0.024 4.8 μs μs 0.9375 Throughput rate (22 DCLOCKs) Clock frequency 3.333 0.024 200 kSPS 4.8 MHz AC ACCURACY Total harmonic distortion Spurious-free dynamic range Signal-to-noise ratio Signal-to-noise + distortion Effective number of bits THD SFDR SNR SINAD ENOB 2.5VPP sinewave at 2kHz –88 –88.5 dB 2.5VPP sinewave at 10kHz –75 –75.5 dB 2.5VPP sinewave at 2kHz 91 91.5 dB 2.5VPP sinewave at 10kHz 77.5 78 dB 2.5VPP sinewave at 2kHz 86.5 87 dB 2.5VPP sinewave at 10kHz 86 86.5 dB 2.5VPP sinewave at 2kHz 85 85.5 dB 2.5VPP sinewave at 10kHz 74.5 75 dB 2.5VPP sinewave at 2kHz 13.86 13.94 Bits 2.5VPP sinewave at 10kHz 12.12 12.20 Bits VOLTAGE REFERENCE INPUT Reference voltage Reference input resistance 0.1 CS = GND, fSAMPLE = 0Hz CS = VDD Reference input capacitance Reference input current VDD 5 0.1 VDD V 5 GΩ 5 5 GΩ 24 24 pF fS = 200kHz 70 90 70 90 μA fS = 100kHz 25 33 25 33 μA fS = 10kHz 5 7 5 7 μA CS = VDD 0.1 0.1 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 μA 5 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS: VDD = +2.7V (continued) At –40°C to +85°C, VREF = +2.5V, –IN = GND, fSAMPLE = 200kHz, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER TEST CONDITIONS MIN TYP ADS8326IB MAX MIN TYP MAX UNIT DIGITAL INPUTS (1) Logic family LVCMOS LVCMOS High-level input voltage VIH VDD = 3.6V 2 VDD + 0.3 2 VDD + 0.3 Low-level input voltage VIL VDD = 2.7V –0.3 0.8 –0.3 0.8 V Input current IIN VI = VDD or GND –50 +50 –50 +50 nA Input capacitance CI 5 5 V pF DIGITAL OUTPUTS (1) Logic family LVCMOS High-level output voltage VOH VDD = 2.7V, IOH = –100μA Low-level output voltage VOL VDD = 2.7V, IOL = 100μA High-impedance state output current IOZ CS = VDD, VI = VDD or GND Output capacitance CO Load capacitance CL VDD – 0.2 V 0.2 –50 +50 –50 5 0.2 V +50 nA 5 30 pF 30 Straight binary Data format (1) LVCMOS VDD – 0.2 pF Straight binary Applies for 3.0V nominal supply: VDD (min) = 2.7V and VDD (max) = 3.6V. ELECTRICAL CHARACTERISTICS At –40°C to +85°C, –IN = GND, and fDCLOCK = 24 × fSAMPLE, unless otherwise noted. ADS8326I PARAMETER TEST CONDITIONS MIN TYP ADS8326IB MAX MIN TYP MAX UNIT ANALOG INPUT Power supply Operating supply current Power-down supply current Power dissipation Power dissipation in power-down 6 VDD IDD IDD Low-voltage levels 2.7 3.6 2.7 3.6 V 5V logic levels 4.5 5.5 4.5 5.5 V VDD = 2.7V, fS = 10kHz, fDCLOCK = 4.8MHz 0.065 0.085 0.065 0.085 mA VDD = 2.7V, fS = 100kHz, fDCLOCK = 4.8MHz 0.69 1.0 0.69 1.0 mA VDD = 2.7V, fS = 200kHz, fDCLOCK = 4.8MHz 1.38 2.0 1.38 2.0 mA VDD = 5V, fS = 200kHz, fDCLOCK = 6MHz 1.9 2.7 1.9 2.7 mA VDD = 5V, fS = 250kHz, fDCLOCK = 6MHz 2.0 3.0 2.0 3.0 mA VDD = 2.7V 0.1 0.1 μA VDD = 5V 0.2 0.2 μA VDD = 2.7V, fS = 10kHz, fDCLOCK = 4.8MHz 0.18 0.23 0.18 0.23 mW VDD = 2.7V, fS = 100kHz, fDCLOCK = 4.8MHz 1.86 2.7 1.86 2.7 mW VDD = 2.7V, fS = 200kHz, fDCLOCK = 4.8MHz 3.73 5.4 3.73 5.4 mW VDD = 5V, fS = 200kHz, fDCLOCK = 6MHz 9.5 13.5 9.5 13.5 mW VDD = 5V, fS = 250kHz, fDCLOCK = 6MHz 10 15 10 15 mW VDD = 2.7V, CS = VDD 0.3 0.3 μW VDD = 5V, CS = VDD 0.6 0.6 μW Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 PIN CONFIGURATION DGK PACKAGE MSOP-8 (TOP VIEW) REF 1 +IN 2 8 VDD 7 DCLOCK ADS8326 -IN 3 6 DOUT GND 4 5 CS/SHDN DRB PACKAGE SON-8 (TOP VIEW) REF 1 +IN 2 8 VDD 7 DCLOCK 6 DOUT 5 CS/SHDN ADS8326 (1) -IN 3 GND 4 (Thermal Pad) The thermal pad is internally connected to the substrate. This pad can be connected to the analog ground or left floating. Keep the thermal pad separate from the digital ground, if possible. PIN ASSIGNMENTS PIN NAME NO. I/O DESCRIPTION REF 1 Analog input Reference input +IN 2 Analog input Noninverting input –IN 3 Analog input Inverting analog input GND 4 Power-supply connection CS/SHDN 5 Digital input DOUT 6 Digital output DCLOCK 7 Digital input VDD 8 Power-supply connection Ground Chip select when low; Shutdown mode when high. Serial output data word Data clock synchronizes the serial data transfer and determines conversion speed. Power supply Equivalent Input Circuit (VDD = 5.0V) VDD VDD RON 50W C(SAMPLE) 48pF ANALOG IN GND Diode Turn-On Voltage: 0.35V Equivalent Analog Input Circuit VDD RON 50W REF GND Equivalent Reference Input Circuit 24pF I/O GND Equivalent Digital Input/Output Circuit Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 7 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com TIMING INFORMATION tCYC CS/SHDN Sample Power Down Conversion tSUCS DCLOCK tCSD Use positive clock edge for data transfer Hi-Z DOUT 0 tSMPL B7 B15 B14 B13 B12 B11 B10 B9 B8 (MSB) tCONV B6 B5 B4 B3 B2 Hi-Z (1) B1 B0 (LSB) NOTE: (1) A minimum of 22 clock cycles are required for 16-bit conversion; 24 clock cycles are shown. If CS remains low at the end of conversion, a new data stream is shifted out with LSB-first data followed by zeroes indefinitely. tCYC CS/SHDN tSUCS Power Down DCLOCK tCSD Hi-Z DOUT 0 tSMPL B15 B14 B6 (MSB) B5 B4 B3 tCONV B2 B1 B0 B1 B2 B3 B4 B5 (LSB) B0 (2) Hi-Z B11 B12 B13 B14 B15 (MSB) NOTE: (2) After completing the data transfer, if further clocks are applied with CS low, the A/D converter will output zeroes indefinitely. 1.4V 3kW DOUT 90% DOUT 10% Test Point tr 100pF CLOAD tf Voltage Waveforms for DOUT Rise and Fall Times, tr, tf Load Circuit for tdDO, tr, and tf Test Point DCLOCK VDD DOUT tdDO tdis Waveform 2, ten 3kW tdis Waveform 1 100pF CLOAD DOUT thDO Load Circuit for tdis and ten Voltage Waveforms for DOUT Delay Times, tdDO 90% CS/SHDN DOUT Waveform 1(3) CS/SHDN 90% DCLOCK 1 4 5 tdis DOUT Waveform 2(4) 10% DOUT B15 ten Voltage Waveforms for tdis Voltage Waveforms for ten NOTES: (3) Waveform 1 is for an output with internal conditions such that the output is high unless disabled by the output control. (4) Waveform 2 is for an output with internal conditions such that the output is low unless disabled by the output control. Figure 1. Timing Diagrams and Test Circuits for the Parameters in Table 1 8 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 TIMING INFORMATION (continued) Table 1. Timing Characteristics SYMBOL DESCRIPTION tSMPL Analog input sample time tCONV Conversion time tCYC Complete cycle time MIN TYP 4.5 MAX 5.0 16 UNIT DCLOCKs DCLOCKs 22 DCLOCKs tCSD CS falling to DCLOCK low tSUCS CS falling to DCLOCK rising 0 tHDO DCLOCK falling to current DOUT not valid tDIS CS rising to DOUT tri-state 70 100 ns tEN DCLOCK falling to DOUT enabled 20 50 ns tF DOUT fall time 5 25 ns tR DOUT rise time 7 25 ns 20 5 ns ns 15 ns Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 9 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE 3 3 2 2 1 1 DLE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE 0 0 -1 -1 -2 -2 -3 0000h 4000h 8000h C000h -3 0000h FFFFh 4000h 8000h Figure 2. Figure 3. CHANGE IN OFFSET vs TEMPERATURE CHANGE IN GAIN vs TEMPERATURE 0.50 Delta from +25°C (LSB) Delta from +25°C (LSB) FFFFh 0.50 0.25 0 -0.25 -0.50 -0.75 -1.00 0.25 0 -0.25 -0.50 -0.75 -50 -25 0 25 50 75 100 -50 Temperature (°C) -25 0 25 50 75 100 Temperature (°C) Figure 4. 10 C000h Output Code Output Code Figure 5. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. CHANGE IN OFFSET vs COMMON-MODE VOLTAGE CHANGE IN GAIN vs COMMON-MODE VOLTAGE 30 Delta Relative to VCM = 0V (LSB) Delta Relative to VCM = 0V (LSB) 30 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0.5 0.6 0 0.1 0.2 0.3 0.4 0.5 0.6 VCM (V) Figure 6. Figure 7. FREQUENCY SPECTRUM (8192 point FFT, fIN = 1.9836kHz, –0.2dB) FREQUENCY SPECTRUM (8192 point FFT, fIN = 9.9792kHz, –0.2dB) 0 0 -20 -20 -40 -40 Amplitude (dB) Amplitude (dB) VCM (V) -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 25 50 75 Frequency (kHz) 100 125 0 Figure 8. 25 50 75 Frequency (kHz) 100 125 Figure 9. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 11 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY 105 SNR 90 SFDR (dB) SNR and SINAD (dB) 95 85 SINAD 80 -105 100 75 -100 SFDR 95 -95 90 -90 85 -85 THD(1) 80 -80 75 70 THD (dB) 100 -75 70 -70 NOTE: (1) First nine harmonics of the input frequency. 65 65 1 10 100 -65 1 200 100 10 200 Frequency (kHz) Frequency (kHz) Figure 10. Figure 11. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE 16.0 0.25 fIN = 1.98364kHz, -0.2dB 0.20 Delta from +25°C (dB) ENOB (Bits) 15.0 14.0 13.0 12.0 11.0 0.15 0.10 0.05 0 -0.05 -0.10 -0.15 10.0 -0.20 1 10 100 200 -50 Frequency (kHz) 0 25 50 75 100 Temperature (°C) Figure 12. 12 -25 Figure 13. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL PEAK-TO-PEAK NOISE FOR A DC INPUT vs REFERENCE VOLTAGE 100 100 Peak-to-Peak Noise (LSB) 90 200 fIN = 1.98364kHz, -0.2dB SINAD (dB) 80 70 60 50 40 30 10 20 10 1 -80 -70 -60 -50 -40 -30 -20 -10 0 0.1 Figure 14. Figure 15. SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SAMPLING RATE 10 1.84 Supply Current (mA) 1.83 Supply Current (mA) 5 1 Reference Voltage (V) Input Level (dB) 1.82 1.81 1.80 1 0.1 0.01 0.001 1.79 -50 -25 0 25 50 75 100 1 10 100 250 Sampling Rate (kHz) Temperature (°C) Figure 16. Figure 17. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 13 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS: VDD = +5V (continued) At TA = +25°C, VDD = +5V, VREF = +5V. fSAMPLE = 250kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. REFERENCE CURRENT vs SAMPLING RATE POWER-DOWN CURRENT vs TEMPERATURE 30 Power-Down Current (nA) Reference Current (mA) 1000 100 10 1 0.1 28 26 24 22 20 18 1 10 100 250 -50 0 -25 Sampling Rate (kHz) 25 50 75 100 Temperature (°C) Figure 18. Figure 19. OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) Occurrence 6990 592 0 0 7FFC 7FFD 7FFE 610 7FFF 8000 0 0 8001 8002 Code Figure 20. 14 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. DIFFERENTIAL LINEARITY ERROR vs CODE 3 3 2 2 1 1 DLE (LSB) ILE (LSB) INTEGRAL LINEARITY ERROR vs CODE 0 0 -1 -1 -2 -2 -3 0000h 4000h 8000h C000h -3 0000h FFFFh 4000h 8000h C000h FFFFh Output Code Figure 21. Figure 22. CHANGE IN OFFSET vs TEMPERATURE CHANGE IN GAIN vs TEMPERATURE 0.50 0.50 0.25 0.25 Delta from +25°C (LSB) Delta from +25°C (LSB) Output Code 0 -0.25 -0.50 -0.75 0 -0.25 -0.50 -0.75 -1.00 -1.00 -50 -25 0 25 50 75 100 -50 Temperature (°C) -25 0 25 50 75 100 Temperature (°C) Figure 23. Figure 24. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 15 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. CHANGE IN OFFSET vs COMMON-MODE VOLTAGE CHANGE IN GAIN vs COMMON-MODE VOLTAGE 30 Delta Relative to VCM = 0V (LSB) Delta Relative to VCM = 0V (LSB) 30 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0 25 20 15 10 5 0 -5 -10 -0.5 -0.4 -0.3 -0.2 -0.1 0.1 0.2 0.3 0.4 0.5 0.6 0.1 0.2 0.3 0.4 0.5 0.6 Figure 25. Figure 26. FREQUENCY SPECTRUM (8192 point FFT, fIN = 1.9775kHz, –0.2dB) FREQUENCY SPECTRUM (8192 point FFT, fIN = 9.9854kHz, –0.2dB) 0 0 -20 -20 -40 -40 -60 -80 -100 -60 -80 -100 -120 -120 -140 -140 -160 -160 0 10 20 30 40 50 60 70 80 90 100 0 Frequency (kHz) 10 20 30 40 50 60 70 80 90 100 Frequency (kHz) Figure 27. 16 0 VCM (V) Amplitude (dB) Amplitude (dB) VCM (V) Figure 28. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE AND SIGNAL-TO-NOISE + DISTORTION vs INPUT FREQUENCY SPURIOUS-FREE DYNAMIC RANGE AND TOTAL HARMONIC DISTORTION vs INPUT FREQUENCY SNR 85 100 -100 95 -95 90 -90 85 80 SFDR (dB) SNR and SINAD (dB) 90 75 70 SINAD 65 -80 75 -75 70 -70 65 55 -55 50 -50 45 55 40 10 100 -60 55 50 1 200 -45 NOTE: (1) First nine harmonics of the input frequency. -40 1 100 10 Frequency (kHz) 200 Frequency (kHz) Figure 29. Figure 30. EFFECTIVE NUMBER OF BITS vs INPUT FREQUENCY CHANGE IN SIGNAL-TO-NOISE + DISTORTION vs TEMPERATURE 15 0.4 fIN = 1.97754kHz, -0.2dB 14 0.2 Delta from +25°C (dB) 13 ENOB (Bits) -65 THD(1) 60 60 -85 SFDR 80 THD (dB) 95 12 11 10 9 0 -0.2 -0.4 -0.6 8 7 -0.8 1 10 100 200 -50 Frequency (kHz) -25 0 25 50 75 100 Temperature (°C) Figure 31. Figure 32. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 17 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS: VDD = +2.7V (continued) At TA = +25°C, VDD = +2.7V, VREF = +2.5V. fSAMPLE = 200kHz, fCLK = 24 × fSAMPLE, unless otherwise noted. SIGNAL-TO-NOISE + DISTORTION vs INPUT LEVEL 100 SUPPLY CURRENT vs TEMPERATURE 1.38 fIN = 1.97754kHz, -0.2dB 90 1.37 Supply Current (mA) SINAD (dB) 80 70 60 50 40 30 1.36 1.35 1.34 1.33 1.32 1.31 20 10 1.30 -80 -70 -60 -50 -40 -30 -20 -10 0 -50 -25 Input Level (dB) 25 50 75 100 Temperature (°C) Figure 33. Figure 34. SUPPLY CURRENT vs SAMPLING RATE REFERENCE CURRENT vs SAMPLING RATE 10 1000 Reference Current (mA) 1 Supply Current (mA) 0 0.1 0.01 0.001 0.0001 100 10 1 0.1 1 100 10 200 1 10 Sampling Rate (kHz) Sampling Rate (kHz) Figure 35. Figure 36. 100 200 OUTPUT CODE HISTOGRAM FOR A DC INPUT (8192 Conversions) Occurrence 4791 1665 0 53 7FFC 7FFD 7FFE 1643 7FFF 8000 40 0 8001 8002 Code Figure 37. 18 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 THEORY OF OPERATION The ADS8326 is a classic Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The architecture is based on capacitive redistribution that inherently includes a sample-and-hold function. The converter is fabricated on a 0.6μ CMOS process. The architecture and process allow the ADS8326 to acquire and convert an analog signal at up to 250,000 conversions per second while consuming less than 10mW from VDD. Differential linearity for the ADS8326 is factory-adjusted via a package-level trim procedure. The state of the trim elements is stored in non-volatile memory and is continuously updated after each acquisition cycle, just prior to the start of the successive approximation operation. This process ensures that one complete conversion cycle always returns the part to its factory-adjusted state in the event of a power interruption. The ADS8326 requires an external reference, an external clock, and a single power source (VDD). The external reference can be any voltage between 0.1V and VDD. The value of the reference voltage directly sets the range of the analog input. The reference input current depends on the conversion rate of the ADS8326. The external clock can vary between 24kHz (1kHz throughput) and 6.0MHz (250kHz throughput). The duty cycle of the clock is essentially unimportant, as long as the minimum high and low times are at least 200ns (VDD = 4.75V or greater). The minimum clock frequency is set by the leakage on the internal capacitors to the ADS8326. The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected from any internal function. The digital result of the conversion is clocked out by the DCLOCK input and is provided serially (most significant bit first) on the DOUT pin. The digital data that is provided on the DOUT pin is for the conversion currently in progress–there is no pipeline delay. It is possible to continue to clock the ADS8326 after the conversion is complete and to obtain the serial data least significant bit first. See the Timing Information section for more information. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 19 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com ANALOG INPUT 0V to +VREF Peak-to-Peak The analog input of ADS8326 is differential. The +IN and –IN input pins allow for a differential input signal. The amplitude of the input is the difference between the +IN and –IN input, or (+IN) – (–IN). Unlike some converters of this type, the –IN input is not resampled later in the conversion cycle. When the converter goes into Hold mode or conversion, the voltage difference between +IN and –IN is captured on the internal capacitor array. ADS8326 Common-Mode Voltage Figure 38. Methods of Driving the ADS8326 Common Voltage Range (V) The range of the –IN input is limited to –0.3V to +0.5V. As a result of this limitation, the differential input could be used to reject signals that are common to both inputs in the specified range. Thus, the –IN input is best used to sense a remote signal ground that may move slightly with respect to the local ground potential. The general method for driving the analog input of the ADS8326 is shown in Figure 38 and Figure 40. The –IN input is held at the common-mode voltage. The +IN input swings from –IN (or common-mode voltage) to –IN + VREF (or common-mode voltage + VREF ), and the peak-to-peak amplitude is +VREF . The value of VREF determines the range over which the common-mode voltage may vary, as shown in Figure 39. Figure 6 and Figure 7 (+5V), and Figure 25 and Figure 26 (+2.7V) illustrate the typical change in gain and offset as a function of the common-mode voltage applied to the –IN pin. 1 VDD = 5V 0.5 0 -0.3 -1 2 2.5 3 4 4.8 5 6 VREF (V) Figure 39. +IN Analog Input: Common-Mode Voltage Range vs VREF +IN Common-Mode Voltage + VREF +VREF t Common-Mode Voltage -IN = Common-Mode Voltage NOTE: The maximum differential voltage between +IN and –IN of the ADS8326 is VREF. See Figure 39 for a further explanation of the common-mode voltage range for differential inputs. Figure 40. Differential Input Mode of the ADS8326 20 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 The input current required by the analog inputs depends on a number of factors: sample rate, input voltage, source impedance, and power-down mode. Essentially, the current into the ADS8326 charges the internal capacitor array during the sample period. After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage must be able to charge the input capacitance (48pF) to a 16-bit settling level within 4.5 clock cycles (0.750μs). When the converter goes into Hold mode, or while it is in Power-Down mode, the input impedance is greater than 1GΩ. Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the –IN input should not drop below GND – 0.3V or exceed GND + 0.5V. The +IN input should always remain within the range of GND – 0.3V to VDD + 0.3V, or –IN to –IN + VREF , whichever limit is reached first. Outside of these ranges, the converter linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters should be used. In each case, care should be taken to ensure that the output impedance of the sources driving the +IN and –IN inputs are matched. Often, a small capacitor (20pF) between the positive and negative inputs helps to match their impedance. To obtain maximum performance from the ADS8326, the input circuit from Figure 41 is recommended. Single-Ended 10W +IN OPA365 50W 48pF 1000pF ADS8326 -IN 50W 48pF Differential 10W +IN OPA365 50W 48pF 1000pF ADS8326 1nF 10W -IN OPA365 50W 48pF 1000pF Figure 41. Single-Ended and Differential Methods of Interfacing the ADS8326 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 21 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com REFERENCE INPUT ADS8326 The external reference sets the analog input range. The ADS8326 operates with a reference in the range of 0.1V to VDD. There are several important implications to this. As the reference voltage is reduced, the analog voltage weight of each digital output code is reduced. This is often referred to as the least significant bit (LSB) size and is equal to the reference voltage divided by 65,536. This means that any offset or gain error inherent in the A/D converter will appear to increase (in terms of LSB size) as the reference voltage is reduced. For a reference voltage of 2.5V, the value of the LSB is 38.15μV, and for a reference voltage of 5V, the LSB is 76.3μV. The noise inherent in the converter will also appear to increase with a lower LSB size. With a 5V reference, the internal noise of the converter typically contributes only 1.5LSB peak-to-peak of potential error to the output code. When the external reference is 2.5V, the potential error contribution from the internal noise will be two times larger (3LSB). The errors arising from the internal noise are Gaussian in nature and can be reduced by averaging consecutive conversion results. For more information regarding noise, see Figure 15, Peak-to-Peak Noise for a DC Input vs Reference Voltage. Note that the Effective Number Of Bits (ENOB) figure is calculated based on the converter signal-to-(noise + distortion) ratio with a 1kHz, 0dB input signal. SINAD is related to ENOB as follows: SINAD = 6.02 × ENOB + 1.76 With lower reference voltages, extra care should be taken to provide a clean layout including adequate bypassing, a clean power supply, a low-noise reference, and a low-noise input signal. Due to the lower LSB size, the converter is also more sensitive to external sources of error, such as nearby digital signals and electromagnetic interference. The equivalent input circuit for the reference voltage is presented in Figure 42. During the conversion process, an equivalent capacitor of 24pF is switched on. To obtain optimum performance from the ADS8326, special care must be taken in designing the interface circuit to the reference input pin. To ensure a stable reference voltage, a 47μF tantalum capacitor with low ESR should be connected as close as possible to the input pin. If a high output impedance reference source is used, an additional operational amplifier with a current-limiting resistor must be placed in front of the capacitors. VREF 50W 24pF OPA350 47mF Figure 42. Input Reference Circuit and Interface When the ADS8326 is in Power-Down mode, the input resistance of the reference pin will have a value of 5GΩ. Since the input capacitors must be recharged before the next conversion starts, an operational amplifier with good dynamic characteristics must be used to buffer the reference input. Noise The transition noise of the ADS8326 itself is extremely low, as shown in Figure 20 (+5V) and Figure 37 (+2.7V); it is much lower than competing A/D converters. These histograms were generated by applying a low-noise DC input and initiating 8192 conversions. The digital output of the A/D converter will vary in output code because of the internal noise of the ADS8326. This is true for all 16-bit, SAR-type A/D converters. Using a histogram to plot the output codes, the distribution should appear bell-shaped with the peak of the bell curve representing the nominal code for the input value. The ±1σ, ±2σ, and ±3σ distributions will represent 68.3%, 95.5%, and 99.7%, respectively, of all codes. The transition noise can be calculated by dividing the number of codes measured by 6, which yields the ±3σ distribution, or 99.7%, of all codes. Statistically, up to three codes could fall outside the distribution when executing 1000 conversions. The ADS8326, with < 3 output codes for the ±3σ distribution, yields < ±0.5LSB of transition noise. Remember, to achieve this low-noise performance, the peak-to-peak noise of the input signal and reference must be < 50μV. Averaging The noise of the A/D converter can be compensated by averaging the digital codes. By averaging conversion results, transition noise is reduced by a factor of 1/√n , where n is the number of averages. For example, averaging four conversion results reduces the transition noise from ±0.5LSB to ±0.25LSB. Averaging should only be used for input signals with frequencies near DC. For AC signals, a digital filter can be used to low-pass filter and decimate the output codes. This works in a similar manner to averaging; for every decimation by 2, the signal-to-noise ratio improves by 3dB. 22 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 DIGITAL INTERFACE Signal Levels The ADS8326 has a wide range of power-supply voltage. The A/D converter, as well as the digital interface circuit, is designed to accept and operate from 2.7V up to 5.5V. This voltage range will accommodate different logic levels. When the ADS8326 power-supply voltage is in the range of 4.5V to 5.5V (5V logic level), the ADS8326 can be connected directly to another 5V, CMOS-integrated circuit. When the ADS8326 power-supply voltage is in the range of 2.7V to 3.6V (3V logic level), the ADS8326 can be connected directly to another 3.3V LVCMOS integrated circuit. A falling CS signal initiates the conversion and data transfer. The first 4.5 to 5.0 clock periods of the conversion cycle are used to sample the input signal. After the fifth falling DCLOCK edge, DOUT is enabled and will output a low value for one clock period. For the next 16 DCLOCK periods, DOUT will output the conversion result, most significant bit first. After the least significant bit (B0) has been output, subsequent clocks will repeat the output data, but in a least significant bit first format. After the most significant bit (B15) has been repeated, DOUT will tri-state. Subsequent clocks will have no effect on the converter. A new conversion is initiated only when CS has been taken high and returned low. Serial Interface Data Format The ADS8326 communicates with microprocessors and other digital systems via a synchronous 3-wire serial interface, as illustrated in the Timing Information section. The DCLOCK signal synchronizes the data transfer, with each bit being transmitted on the falling edge of DCLOCK. Most receiving systems will capture the bitstream on the rising edge of DCLOCK. However, if the minimum hold time for DOUT is acceptable, the system can use the falling edge of DCLOCK to capture each bit. The output data from the ADS8326 is in Straight Binary format, as shown in Figure 43. This figure represents the ideal output code for a given input voltage and does not include the effects of offset, gain error, or noise. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 23 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com 65535 1111 1111 1111 1111 65534 1111 1111 1111 1111 65533 1000 0000 0000 0001 32769 1000 0000 0000 0000 32768 0111 1111 1111 1111 32767 0000 0000 0000 0010 2 0000 0000 0000 0001 1 0000 0000 0000 0000 Step Digital Output Code Straight Binary 1111 1111 1111 1111 0 2.499962V VZ = VCM = 0V 2.500038V VFS = VCM + VREF = 5V 38.15mV VFS - 1LSB = 4.999924V VMS = VCM + VREF/2 = 2.5V 76.29mV 4.999847V Unipolar Analog Input Voltage 1LSB = 76.29mV 152.58mV VCM = 0V VREF = 5V 16-BIT Zero Code Midscale Code Full- Scale Code Straight Binary Output VZ = 0000h VMS = 8000h VFS = FFFFh Unipolar Analog Input VCODE = VCM VCODE = VCM + VREF/2 VCODE = (VCM + VREF) - 1LSB Figure 43. Ideal Conversion Characteristics (Conditions: VCM = 0V, VREF = 5V) 24 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 POWER DISSIPATION Short Cycling The architecture of the converter, the semiconductor fabrication process, and a careful design allow the ADS8326 to convert at up to a 250kHz rate while requiring very little power. However, for the absolute lowest power dissipation, there are several things to keep in mind. Another way to save power is to use the CS signal to short-cycle the conversion. The ADS8326 places the latest data bit on the DOUT line as it is generated; therefore, the converter can easily be short-cycled. This term means that the conversion can be terminated at any time. For example, if only 14 bits of the conversion result are needed, then the conversion can be terminated (by pulling CS high) after the 14th bit has been clocked out. The power dissipation of the ADS8326 scales directly with conversion rate. Therefore, the first step to achieving the lowest power dissipation is to find the lowest conversion rate that will satisfy the requirements of the system. In addition, the ADS8326 goes into Power-Down mode under two conditions: when the conversion is complete and whenever CS is high (see the Timing Information section). Ideally, each conversion should occur as quickly as possible, preferably at a 6.0MHz clock rate. This way, the converter spends the longest possible time in Power-Down mode. This is very important because the converter not only uses power on each DCLOCK transition (as is typical for digital CMOS components), but also uses some current for the analog circuitry, such as the comparator. The analog section dissipates power continuously until Power-Down mode is entered. Figure 17 and Figure 18 (+5V), and Figure 35 and Figure 36 illustrate the current consumption of the ADS8326 versus sample rate. For these graphs, the converter is clocked at maximum speed regardless of the sample rate. CS is held high during the remaining sample period. This technique can also be used to lower the power dissipation (or to increase the conversion rate) in those applications where an analog signal is being monitored until some condition becomes true. For example, if the signal is outside a predetermined range, the full 16-bit conversion result may not be needed. If so, the conversion can be terminated after the first n bits, where n might be as low as 3 or 4. This results in lower power dissipation in both the converter and the rest of the system because they spend more time in Power-Down mode. POWER-ON RESET The ADS8326 bias circuit is self-starting. There may be a static current (approximately 1.5mA with VDD = 5V) after power-on, unless the circuit is powered down. It is recommended to run a single test conversion (configured the same as any regular conversion) after the power supply reaches at least 2.4V to ensure the device is put into power-down mode. There is an important distinction between the power-down mode that is entered after a conversion is complete and the full power-down mode that is enabled when CS is high. CS low will only shut down the analog section. The digital section is completely shut down only when CS is high. Thus, if CS is left low at the end of a conversion, and the converter is continually clocked, the power consumption will not be as low as when CS is high. Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 25 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com LAYOUT For optimum performance, care should be taken with the physical layout of the ADS8326 circuitry. This is particularly true if the reference voltage is low and/or the conversion rate is high. At a 250kHz conversion rate, the ADS8326 makes a bit decision every 167ns. That is, for each subsequent bit decision, the digital output must be updated with the results of the last bit decision, the capacitor array appropriately switched and charged, and the input to the comparator settled to a 16-bit level, all within one clock cycle. The basic SAR architecture is sensitive to spikes on the power supply, reference, and ground connections that occur just prior to latching the comparator output. Thus, during any single conversion for an n-bit SAR converter, there are n windows in which large external transient voltages can easily affect the conversion result. Such spikes might originate from switching power supplies, digital logic, and high-power devices, to name a few potential sources. This particular source of error can be very difficult to track down if the glitch is almost synchronous to the converter DCLOCK signal because the phase difference between the two changes with time and temperature, causing sporadic misoperation. With this in mind, power to the ADS8326 should be clean and well-bypassed. A 0.1μF ceramic bypass capacitor should be placed as close as possible to the ADS8326 package. In addition, a 1μF to 10μF capacitor and a 5Ω or 10Ω series resistor may be used to low-pass filter a noisy supply. resistor can help in this case). Keep in mind that while the ADS8326 draws very little current from the reference on average, there are still instantaneous current demands placed on the external input and reference circuitry. Texas Instruments' OPA365 op amp provides optimum performance for buffering the signal inputs; the OPA350 can be used to effectively buffer the reference input. Also, keep in mind that the ADS8326 offers no inherent rejection of noise or voltage variation in regards to the reference input. This is of particular concern when the reference input is tied to the power supply. Any noise and ripple from the supply will appear directly in the digital results. While high-frequency noise can be filtered out, as described in the previous paragraph, voltage variation resulting from the line frequency (50Hz or 60Hz) can be difficult to remove. The GND pin on the ADS8326 should be placed on a clean ground point. In many cases, this will be the analog ground. Avoid connecting the GND pin too close to the grounding point for a microprocessor, microcontroller, or digital signal processor. If needed, run a ground trace directly from the converter to the power-supply connection point. The ideal layout will include an analog ground plane for the converter and associated analog circuitry. The reference should be similarly bypassed with a 47μF capacitor. Again, a series resistor and large capacitor can be used to low-pass filter the reference voltage. If the reference voltage originates from an op amp, make sure that the op amp can drive the bypass capacitor without oscillation (the series 26 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 ADS8326 www.ti.com.................................................................................................................................................. SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009 APPLICATION CIRCUITS high-frequency noise from the supply itself. The exact values should be picked such that the filter provides adequate rejection of noise. Operational amplifiers and voltage reference are connected to analog power supply, AVDD. Figure 44 and Figure 45 show two examples of a basic data acquisition system. The ADS8326 input range is connected to 2.5V or 4.096V. The 5Ω resistor and 1μF to 10μF capacitor filters the microcontroller noise on the supply, as well as any DVDD 2.7V to 3.6V 0.1mF AVDD 2.7V to 5V + 10mF 5W REF3225 REF OPA350 10W IN OUT 2.2mF 0.1mF GND 0.47mF VDD 47mF + 10mF ADS8326 DSP 10W TMS320C6xx or TMS320C5xx or TMS320C2xx +IN OPA365 VCM + (0V to 2.5V) 1000pF CS 1nF DOUT DCLOCK 10W GND -IN OPA365 VCM GND 1000pF Figure 44. Basic Data Acquisition System: Example 1 DVDD 4.5V to 5.5V 0.1mF 10mF 5W AVDD 4.3V to 5.5V REF3240 REF OPA350 10W IN OUT VDD 0.1mF 47mF 2.2mF 0.47mF + GND + 10mF ADS8326 10W Microcontroller or DSP +IN OPA365 0V to 4.096V 1000pF CS DOUT DCLOCK -IN GND GND Figure 45. Basic Data Acquisition System: Example 2 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 27 ADS8326 SBAS343C – MAY 2007 – REVISED SEPTEMBER 2009.................................................................................................................................................. www.ti.com REVISION HISTORY NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision B (May, 2008) to Revision C ..................................................................................................... Page • Released SON-8 package; changed statements regarding SON-8 package availability ..................................................... 1 • Deleted footnote about SON-8 package availability ............................................................................................................. 2 • Deleted footnote about SON-8 package availability ............................................................................................................. 3 • Deleted footnote about SON-8 package availability ............................................................................................................. 7 Changes from Revision A (August, 2007) to Revision B ............................................................................................... Page • Changed SON-8 package availability to Q3, 2008 ............................................................................................................... 1 • Changed y-axis unit in Figure 35 from μA to mA ............................................................................................................... 18 • Added Power-On Reset section ......................................................................................................................................... 25 28 Submit Documentation Feedback Copyright © 2007–2009, Texas Instruments Incorporated Product Folder Link(s): ADS8326 PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) ADS8326IBDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IBDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IBDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IBDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IBDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IBDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IDGKR ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IDGKRG4 ACTIVE VSSOP DGK 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IDGKT ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU | CU NIPDAUAG Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IDGKTG4 ACTIVE VSSOP DGK 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IDRBR ACTIVE SON DRB 8 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 ADS8326IDRBT ACTIVE SON DRB 8 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 D26 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing ADS8326IBDGKR VSSOP DGK 8 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8326IBDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8326IBDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8326IBDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8326IDGKR VSSOP DGK 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8326IDGKT VSSOP DGK 8 250 180.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 ADS8326IDRBR SON DRB 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 ADS8326IDRBT SON DRB 8 250 180.0 12.4 3.3 3.3 1.1 8.0 12.0 Q2 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) ADS8326IBDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8326IBDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8326IBDRBR SON DRB 8 3000 338.1 338.1 20.6 ADS8326IBDRBT SON DRB 8 250 210.0 185.0 35.0 ADS8326IDGKR VSSOP DGK 8 2500 367.0 367.0 35.0 ADS8326IDGKT VSSOP DGK 8 250 210.0 185.0 35.0 ADS8326IDRBR SON DRB 8 3000 338.1 338.1 20.6 ADS8326IDRBT SON DRB 8 250 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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