GS2986 GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Features Description • • • • The GS2986 is a multi-rate serial digital reclocker designed to automatically recover the embedded clock from a digital video signal and retime the incoming video data. It will recover the embedded clock signal and retime the data from a SMPTE 424M, SMPTE 292M, or SMPTE 259M-C compliant digital video signal. • • • • • • • • • • • • • • • • SMPTE 424M, SMPTE 292M and SMPTE 259M-C compliant Supports DVB-ASI at 270Mb/s Single supply operation at 3.3V or 2.5V 180mW typical power consumption (213mW with RCO enabled) at 2.5V Input signal equalization and output-signal de-emphasis settings to compensate for board-trace dielectric losses 4:1 input multiplexer patented technology Choice of dual reclocked data outputs or one reclocked data output and one clock output Uses standard 27MHz crystal Cascadable crystal buffer supports multiple reclockers using a single crystal Differential inputs and outputs support DC coupling to industry-standard differential logic on-chip 100Ω differential data input/output termination selectable 400mVppd or 800mVppd output swing on each output seamless interface to other Gennum products 4 wire SPI host interface for device configuration and monitoring Standard logic control and status signal levels Auto and Manual modes for rate selection Standards indication in Auto mode Lock Detect Output Mute, Bypass and Autobypass functions SD/HD indication output to control GS2978 or GS2988 dual slew-rate cable drivers Operating temperature range: -40°C to +85°C Small footprint QFN package (6mm x 6mm) Pb-free and RoHS compliant A serial host interface provides the ability to configure and monitor multiple GS2986 devices in a daisy-chain configuration. Adjustable input trace equalization (EQ) for up to 40” of FR4 trace losses, and adjustable output de-emphasis (DE) for up to 20” of FR4 trace losses, can be configured via the host interface. The GS2986 can operate in either auto or manual rate selection mode. In Auto mode, the device will automatically detect and lock onto incoming SMPTE SDI data signals at any supported rate. For single rate data systems, the GS2986 can be configured to operate in Manual mode. In both modes, the device requires only one external crystal to set the VCO frequency when not locked and provides adjustment free operation. The GS2986 accepts industry-standard differential input levels including LVPECL and CML. The differential data and clock outputs feature selectable output swing via the host interface, ensuring compatibility with most industry-standard, terminated differential receivers. The GS2986 features dual differential outputs. The second output can be configured to emit either the recovered clock signal or the re-timed video data. This output can also be disabled to save power. In systems which require passing of non-SMPTE data rates, the GS2986 can be configured to either automatically or manually enter a bypass mode in order to pass the signal without reclocking. The GS2986 is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous sub-components are RoHS compliant. Applications • SMPTE 424M, SMPTE 292M and SMPTE 259M-C coaxial cable serial digital interfaces GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 www.semtech.com 1 of 41 XTAL- CP_CAP XTAL_BUF_OUT XTAL+ XTAL OSC LF+ Buffer LDO DDO0 Retimer Data Buffer DDO0 Phase Frequency Detector DDI0 DDI0 Charge Pump VCO DDI1 DDO1/RCO Clock/ Data Buffer DDO1/RCO DDI1 Equalizer/ Data Mux Phase Detector DDI2 DDI2 Selectable Divide DDI3 DDI3 Selectable Divide LOS Detect HIF SDI/EQ0_EN LOS LDO Control SDO/EQ1_EN SCK/EQ2_EN CS/EQ3_EN DDI_SEL[1:0] 1.8V SPI LOCKED DDO1_DISABLE SD/HD VDD_1p8 GS2986 Functional Block Diagram Revision History Version ECR PCN Date Changes and/or Modifications 3 158335 – July 2012 Removed jumper from Figure 5-1: GS2986 Typical Application Circuit 2 158129 – May 2012 Corrected 4.15.3 section to make it easier to follow and changed to Semtech template. 1 153705 – March 2010 Converted to Data Sheet. Updated Power numbers in Table 2-1: DC Electrical Characteristics. Added Table 4-5: Suggested LOS Threshold Settings. 0 152591 – September 2009 Converted to Preliminary Data Sheet. Updates to Electrical Characteristics. Updates to Section 4.15 Host Interface. B 151972 – July 2009 Added Section 4.15 Host Interface. Updated Power numbers in Table 2-1: DC Electrical Characteristics and Loop Bandwidth numbers in Table 2-2: AC Electrical Characteristics. Added Table 1-2: GS2986 Default Start-up Settings and Figure 4-2: De-emphasis Waveform. A 151668 – April 2009 New document. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 2 of 41 Contents Features.................................................................................................................................................................1 Applications.........................................................................................................................................................1 Description...........................................................................................................................................................1 Revision History .................................................................................................................................................2 1. Pin Out...............................................................................................................................................................5 1.1 Pin Assignment ..................................................................................................................................5 1.2 Pin Descriptions ................................................................................................................................6 1.3 Default Start-up Settings ................................................................................................................8 2. Electrical Characteristics ............................................................................................................................9 2.1 Absolute Maximum Ratings ..........................................................................................................9 2.2 DC Electrical Characteristics ........................................................................................................9 2.3 AC Electrical Characteristics ..................................................................................................... 10 3. Input/Output Circuits ............................................................................................................................... 13 4. Detailed Description.................................................................................................................................. 17 4.1 Serial Data Input ............................................................................................................................ 17 4.2 Modes of Operation ...................................................................................................................... 17 4.3 Input Trace Equalization ............................................................................................................. 17 4.4 4:1 Input Mux .................................................................................................................................. 18 4.5 Crystal Buffer .................................................................................................................................. 19 4.6 LOS (Loss Of Signal) Detection .................................................................................................. 19 4.7 Serial Digital Reclocker ............................................................................................................... 20 4.8 Lock Detection ................................................................................................................................ 20 4.8.1 Lock Detect and Asynchronous Lock ......................................................................... 21 4.9 Serial Data Output ......................................................................................................................... 21 4.9.1 Output Signal Interface Levels...................................................................................... 21 4.9.2 Adjustable Output Swing................................................................................................ 21 4.9.3 Output De-emphasis ........................................................................................................ 21 4.10 Automatic and Manual Data Rate Selection ...................................................................... 22 4.11 SD/HD Indication ........................................................................................................................ 23 4.12 Bypass Mode ................................................................................................................................. 23 4.13 DVB-ASI ......................................................................................................................................... 24 4.14 Output Mute and Data/Clock Output Selection ............................................................... 24 4.15 Host Interface ............................................................................................................................... 24 4.15.1 Introduction ...................................................................................................................... 24 4.15.2 Legacy Mode & Start-up................................................................................................ 25 4.15.3 Host Interface Mode & Start-up.................................................................................. 25 4.15.4 Clock & Data Timing....................................................................................................... 25 4.15.5 Single Device Operation ............................................................................................... 25 4.15.6 Write Operation - Single Device ................................................................................ 26 4.15.7 Read Operation - Single Device ................................................................................. 27 4.15.8 Daisy Chain Operation.................................................................................................. 29 4.15.9 Read & Write Operation - Daisy Chained Devices .............................................. 30 4.15.10 Writing to all Devices .................................................................................................. 30 4.15.11 Writing to a Single Device in the Chain ................................................................ 31 GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 3 of 41 4.15.12 Reading from all Devices ........................................................................................... 31 4.15.13 Reading from a Single Device in the Chain.......................................................... 32 4.15.14 Host Register Map......................................................................................................... 33 4.16 Device Power-up ......................................................................................................................... 36 4.17 Standby ........................................................................................................................................... 36 5. Typical Application Circuit ..................................................................................................................... 37 6. Package and Ordering Information...................................................................................................... 38 6.1 Package Dimensions ..................................................................................................................... 38 6.2 Recommended PCB Footprint ................................................................................................... 39 6.3 Packaging Data ............................................................................................................................... 39 6.4 Marking Diagram ........................................................................................................................... 40 6.5 Solder Reflow Profile .................................................................................................................... 40 6.6 Ordering Information ................................................................................................................... 41 GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 4 of 41 1. Pin Out XTAL_BUF_OUT 36 XTAL+ 37 XTAL- SDI/EQ0_EN 38 CS/EQ3_EN VEE_CP 39 SCK/EQ2_EN VCC_CP 40 SDO/EQ1_EN LF+ 1.1 Pin Assignment 35 34 33 32 31 CP_CAP 1 30 VEE_DDO0 DDI0 2 29 VCC_DDO0 HIF 3 28 DDO0 DDI0 4 27 DDO0 DDI1 5 26 VEE_DDO1 DDI1 6 25 VCC_DDO1 DDI2 7 24 DDO1/RCO DDI2 8 23 DDO1/RCO DDI3 9 22 DDO1_DISABLE 10 21 SD/HD 17 18 19 20 VDD_DIG VSS_DIG VCC_VCO 16 LOS DDI_SEL1 15 LOCKED 14 VDD_1P8 13 VEE_VCO 12 DDI_SEL0 Ground Pad (bottom of package) 11 RSVD DDI3 GS2986 40-pin QFN (top view) Figure 1-1: GS2986 Pin Out GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 5 of 41 1.2 Pin Descriptions Table 1-1: GS2986 Pin Descriptions Pin Number Name Type Description 1 CP_CAP Power External capacitor for internal LDO regulator supplying the charge pump circuit. 2, 4 DDI0, DDI0 Input Serial Digital Differential Input 0. 3 HIF Logic Input 5, 6 DDI1, DDI1 Input Serial Digital Differential Input 1. 7, 8 DDI2, DDI2 Input Serial Digital Differential Input 2. 9, 10 DDI3, DDI3 Input Serial Digital Differential Input 3. 11 RSVD Reserved 12, 13 DDI_SEL[0:1] Logic Input 14 VCC_VCO Power Most positive power supply connection for the internal VCO section. Connect to a 3.3V supply with a 422Ω resistor, or to a 2.5V supply with a 267Ω resistor. 15 VEE_VCO Power Most negative power supply connection for the internal VCO section. Connect to GND. 16 VDD_1P8 Power External capacitor for internal 1.8V digital supply. 17 LOCKED Output Lock Detect status signal. HIGH when the PLL is locked. 18 LOS Output Loss Of Signal status. HIGH when the input signal is invalid. 19 VDD_DIG Power Most positive power supply connection for the digital core. Connect to 3.3V or 2.5V. 20 VSS_DIG Power Most negative power supply for the digital core. Connect to GND. 21 SD/HD Output This signal will be LOW for all rates other than 270Mb/s. This signal is HIGH for 270Mb/s. 22 DDO1_DISABLE Logic Input 23, 24 DDO1/RCO, DDO1/RCO Output Differential serial clock or data outputs. 25 VCC_DDO1 Power Most positive power supply connection for the DDO1/DDO1 output driver. Connect to 3.3V or 2.5V. 26 VEE_DDO1 Power Most negative power supply connection for the DDO1/DDO1 output driver. Connect to GND. 27, 28 DDO0, DDO0 Output Differential Serial Digital Outputs. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 Host interface selection pin. Active-low input. See Section 4.15.1. Reserved pin. Do not connect to this pin. Selects one of four serial digital input signals for processing. See Section 4.4. Disables the DDO1/RCO and DDO1/RCO outputs when LOW. See Section 4.14. 6 of 41 Table 1-1: GS2986 Pin Descriptions (Continued) Pin Number Name Type Description 29 VCC_DDO0 Power Most positive power supply connection for the DDO0/DDO0 output driver. Connect to 3.3V or 2.5V. 30 VEE_DDO0 Power Most negative power supply connection for the DDO0/DDO0 output driver. Connect to GND. 31 XTAL_BUF_OUT Output Buffered output of the reference oscillator. 32 XTAL+ Output Reference crystal output. 33 XTAL- Input 34 CS/EQ3_EN Input/Logic Input Reference crystal input. In host mode (HIF set LOW): Chip select input for SPI serial host interface. Active-low input. In non-host mode (HIF set HIGH): Trace equalization on/off pin for Serial Digital Differential Input 3. Active-high input. 35 SCK/EQ2_EN Input/Logic Input In host mode (HIF set LOW): Burst-mode clock input for SPI serial host interface. In non-host mode (HIF set HIGH): Trace equalization on/off pin for Serial Digital Differential Input 2. Active-high input. 36 SDO/EQ1_EN Input/Logic Input In host mode (HIF set LOW): Serial digital data output for SPI serial host interface. Active-high output. In non-host mode (HIF set HIGH): Trace equalization on/off pin for Serial Digital Differential Input 1. Active-high input. 37 SDI/EQ0_EN Input/Logic Input In host mode (HIF set LOW): Serial digital data input for SPI serial host interface. Active-high input. In non-host mode (HIF set HIGH): Trace equalization on/off pin for Serial Digital Differential Input 0. Active-high input. 38 VEE_CP Power Most negative power supply connection for the internal charge pump. Connect to GND. 39 VCC_CP Power Most positive power supply connection for the internal charge pump. Connect to 3.3V or 2.5V 40 LF+ Passive − Center Pad − GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 Loop Filter capacitor connection. (CLF = 47nF). Connect as shown in Typical Application Circuit on page 37. Ground pad on bottom of package. Connect to GND. 7 of 41 1.3 Default Start-up Settings The GS2986 has some functions that are not accessible via direct pin control, and are only accessible through the host interface registers. These functions have an internal pull-up or pull-down resistor that sets the default logic level or start-up state, if it is not already set by a pin. If the user wishes to override these logic levels, the associated bit should be programmed within the PIN_OR_1 register (pin override register) at address 0x0C. The logic values within the PIN_OR_1 register become active when the user sets the Pin Override Enable bit to HIGH within that same register. Table 1-2 shows: 1. The default logic state set by the internal pull-up or pull-down resistors. 2. The default values within the Pin Override register upon reset. More details are given in Section 4.15. Table 1-2: GS2986 Default Start-up Settings Default State set by Internal Resistors Default State within the Pin Override Register Bypasses the reclocker stage when set HIGH. 0 0 When set HIGH, this bit automatically bypasses the reclocker stage when the PLL is not locked to a supported rate. 0 0 When set HIGH, the standard is automatically detected from the input data rate. 1 0 None 0:0 Floating Ground Name BYPASS AUTOBYPASS AUTO/MAN SS0, SS1 KBB Description When AUTO/MAN is set HIGH, SS[1:0] are outputs displaying the data rate to which the PLL has locked. Therefore, the bits will not have a default start-up value. Controls the loop bandwidth of the PLL. DATA_MUTE Mutes the DDO0/DDO0 and DDO1/DDO1 (if data is selected) outputs when LOW. 1 0 DATA/CLOCK HIGH = DATA LOW = CLOCK 0 0 De-emphasis on/off pin for serial digital output. 0 0 DE_EN HIGH = de-emphasis on LOW = de-emphasis off GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 8 of 41 2. Electrical Characteristics 2.1 Absolute Maximum Ratings Parameter Value Supply Voltage -0.5 to +3.6VDC Input ESD Voltage 4kV Storage Temperature Range -50ºC < TA < 125ºC Operating Temperature Range -40ºC to 85ºC Input Voltage Range -0.3 to (VCC + 0.3) VDC Solder Reflow Temperature 260ºC 2.2 DC Electrical Characteristics Table 2-1: DC Electrical Characteristics Parameter Supply Voltage Power (DDO1/RCO disabled, minimum output swing) Symbol VDD P Power (DDO1/RCO enabled, minimum output swing) Power in Power-down mode Conditions Min Typ Max Units 3.3V 3.135 3.3 3.465 V 2.5V 2.375 2.5 2.625 V VDD = 3.3V − 250 325 mW VDD = 2.5V − 180 235 mW VDD = 3.3V − 290 390 mW VDD = 2.5V − 210 275 mW VDD = 3.3V − 48 60 mW VDD = 2.5V − 30 40 mW Serial Input Termination − Differential 80 100 120 Ω Serial Output Termination − Differential 80 100 120 Ω Serial Input Common Mode Voltage − − 1.6 − VDD V Serial Output Common Mode Voltage − − − VCC(ΔVOD /2) − V VIL (2.5V operation) − VOUT≤VOL, max -0.3 − 0.7 V VOUT≤VOL, max -0.3 − 0.8 V VOUT≥VOH, min 1.7 − VDD +0.3 V VOUT≥VOH, min 2 − VDD +0.3 V VIN = 0V or VIN = VDD − +/-10 +/-20 μA VIL (3.3V operation) VIH (2.5V operation) − VIH (3.3V operation) IIN − GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 9 of 41 Table 2-1: DC Electrical Characteristics (Continued) Parameter Symbol Conditions − VOL (2.5V operation) VOL (3.3V operation) − VOH (2.5V operation) VOH (3.3V operation) − Hysteresis Voltage (SPI inputs) NOTE: guaranteed by simulation. Min Typ Max Units VDD = min, IOL = 100μA − − 0.2 V VDD = min, IOL = 100μA − − 0.2 V VDD = min, IOH = -100μA 2.1 − − V VDD = min, IOH = -100μA VDD -0.4 − − V 2.5V operation − 350 − mV 3.3V operation − 350 − mV 2.3 AC Electrical Characteristics Table 2-2: AC Electrical Characteristics Parameter Serial Input Data Rate (for reclocking) Symbol DRSDO Serial Input Data Rate (bypass) Conditions Min Typ Max Units Notes − 0.27 − 2.97 Gb/s − − DC − 2.97 Gb/s − − − − 10 MHz − SPI Operating Speed − Input Voltage Swing ΔVSDI Set ATTEN_EN = 1 for ΔVSDI>1Vpp 100 − 2000 mVp-pd − Output Voltage Swing ΔVOD default 300 400 500 mVp-pd − see DRIVER_1 register (0x01) addresses 8 & 9 in 4.15.14 Host Register Map. 600 800 1000 mVp-pd − LOW Recommended setting for 0 to 10 inches of FR4 − MED Recommended setting for 10 to 20 inches of FR4 − HIGH Recommended setting for >20 inches of FR4 − Input Trace Equalization − GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 10 of 41 Table 2-2: AC Electrical Characteristics (Continued) Parameter Output De-Emphasis Input Jitter Tolerance Loop Bandwidth Symbol − − BWLOOP Conditions Min Typ Max Units Notes OFF - 0 − 0 − dB − ON - 0 − 0 − dB − ON - 1 − 0.7 − dB − ON - 2 − 1.3 − dB − ON - 3 − 2 − dB − ON - 4 − 2.6 − dB − ON - 5 − 3.3 − dB − ON - 6 − 4 − dB − ON - 7 − 4.7 − dB − 0.8 − − UI − KBB = VCC − 170 − kHz − KBB = FLOAT − 340 − kHz − KBB = GND − 680 − kHz − KBB = VCC − 0.875 − MHz − KBB = FLOAT − 1.75 − MHz − KBB = GND − 3.5 − MHz − KBB = VCC − 1.75 − MHz − KBB = FLOAT − 3.5 − MHz − KBB = GND − 7.0 − MHz − square-wave modulated jitter (270Mb/s) BWLOOP (1485Mb/s) BWLOOP (2970Mb/s) PLL Lock Time (asynchronous) talock − − 0.5 1 ms − PLL Lock Time (synchronous) tslock CLF = 47nF, SD/HD = 0 − 0.5 4 μs − CLF = 47nF, SD/HD = 1 − 5 10 μs − KBB = FLOAT − 0.01 − UI − − 0.03 − UI − − 0.05 − UI − 20% to 80% (400mV swing) − 65 − ps − 20% to 80% (800mV swing) − 80 − ps − − − − 15 ps − Serial Data output Jitter Intrinsic (DDO0) tOJ(270MB/s) PRN 2^23-1 test pattern tOJ(1485MB/s) KBB = FLOAT PRN 2^23-1 test pattern tOJ(2970MB/s) KBB = FLOAT PRN 2^23-1 test pattern Output Rise/Fall Time Output Rise/Fall Time Mismatch tr/f − GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 11 of 41 Table 2-2: AC Electrical Characteristics (Continued) Parameter Symbol Conditions Min Typ Max Units Notes Eye Cross Shift − percentage of signal amplitude − − 5 % − Power Supply Noise Rejection − 50 - 100Hz − 100 − mVp-p − 100Hz - 10MHz − 40 − mVp-p − 10MHz - 1.485GHz − 10 − mVp-p − GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 12 of 41 3. Input/Output Circuits VCC 5.55kΩ 12.96kΩ 25Ω VCC VCC 25Ω 25Ω 25Ω DDI DDI Figure 3-1: High-speed Inputs (DDI0, DDI0, DDI1, DDI1, DDI2, DDI2, DDI3, DDI3) VCC 2.5µA VCC 1.4kΩ IN VREF Figure 3-2: Low-speed Input with weak internal pull-up (HIF, DDO1_DISABLE) GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 13 of 41 VCC VCC 1.4kΩ IN VREF 2.5µA Figure 3-3: Low-speed Input with weak internal pull-down (DDI_SEL0, DDI_SEL1) VCC VCC 972Ω OUT Figure 3-4: Low-speed Outputs (LOCKED, LOS, SD/HD) VCC VCC VCC 50Ω DDO 50Ω DDO Figure 3-5: High-speed Outputs (DDO1/RCO, DDO1/RCO, DDO0, DDO0) GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 14 of 41 VCC VCC XTAL_BUFF_OUT Figure 3-6: Crystal Buffered Output (XTAL_BUF_OUT) VCC VCC EN VCC VCC XTAL+ 246Ω XTALEN Figure 3-7: High-speed Crystal Oscillator I/O (XTAL-, XTAL+) VCC VCC 1kΩ IN 2.5µA Figure 3-8: SPI Inputs/EQ Ctrl (CS/EQ3_EN, SCK/EQ2_EN, SDI/EQ0_EN) GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 15 of 41 VCC VCC 1.4kΩ VREF 2.5µA VCC Tgate SDO SPI SDO tri-state Logic Figure 3-9: SPI Output/EQ Control (SDO/EQ1_EN) GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 16 of 41 4. Detailed Description The GS2986 is a multi-standard reclocker for serial digital SDTV signals operating at 270Mb/s, and HDTV signals operating at 1.485Gb/s, 1.485/1.001Gb/s, 2.97Gb/s and 2.97/1.001Gb/s. 4.1 Serial Data Input The GS2986 features four differential input buffers. The serial data input signal is connected to the DDI0/DDI0, DDI1/DDI1, DDI2/DDI2 and DDI3/DDI3 input pins of the device. Input signals can be single-ended or differential, DC or AC-coupled. The input circuit is self-biasing, to allow for simple AC or DC-coupling of input signals to the device. 4.2 Modes of Operation The GS2986 has two modes of operation: Legacy Mode (HIF = HIGH) and SPI Mode (HIF = LOW). In Legacy Mode, chip functions are controlled via pins only, and offers limited control of input Equalization. In SPI mode, access is gained to extended digital controls like: Bypass, Autobypass, Auto/Manual selection, Control status inputs or outputs, changes to KBB settings, additional EQ and DE settings as well as access to additional features such as LOS adjustment, polarity invert, auto-mute, etc. 4.3 Input Trace Equalization The GS2986 features adjustable trace equalization to compensate for PCB trace dielectric losses at 1.5GHz. The trace equalization has three peak-gain settings. The maximum peak gain value is optimized for compensating the high-frequency losses associated with 25 inches of 5-mil stripline in FR4 material. For boards with different striplines or materials, users can experiment to find the EQ setting which optimizes their system performance. These settings are accessible via the serial host interface. Each serial digital input; DDI, DDI includes a pin EQn_EN to turn its trace equalizer on or off. When a pin EQn_EN is tied LOW or left unconnected, the trace equalization for input n is set to LOW. When an EQn_EN pin is tied HIGH, and input n is selected, the trace equalization for input n is set to Medium. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 17 of 41 Table 4-1: Input Trace Equalization Operation EQn_EN Setting Trace Equalization LOW Low HIGH Medium The default peak-gain setting upon power-up is optimized for compensating the high-frequency losses associated with approximately 10 inches of 5-mil stripline in FR4 material. The EQn_EN pins are multiplexed with the serial host interface pins when pin HIF is tied high, as shown in Table 4-2: Table 4-2: EQn_EN Pins Multiplexed Pin Function SDI/EQ0_EN Active-high logic input to enable trace-equalization for high-speed input channel 0. SDO/EQ1_EN Active-high logic input to enable trace-equalization for high-speed input channel 1. SCK/EQ2_EN Active-high logic input to enable trace-equalization for high-speed input channel 2. CS/EQ3_EN Active-high logic input to enable trace-equalization for high-speed input channel 3. 4.4 4:1 Input Mux The GS2986 incorporates a 4:1 input mux, which allows the connection of four independent streams of video/data. There are four differential inputs (DDI[3:0] / DDI[3:0]). The active channel can be selected via the DDI_SEL[1:0] pins as shown in Table 4-3. Table 4-3: Input Selection Table DDI_SEL[1:0] Selected Input 00 DDI0 01 DDI1 10 DDI2 11 DDI3 The DDI_SEL pins include internal pulldowns which pull the input voltage LOW if either pin is unconnected. Active circuitry associated with the input buffers and trace EQ can only be turned on for the selected input. Inputs which are not selected have their input buffers and trace EQs turned OFF to save power. Unused inputs can be either left floating, or tied to VCC. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 18 of 41 4.5 Crystal Buffer The GS2986 features a crystal buffer supporting a Gennum recommended external 27MHz crystal. The GS2986 requires an external 27MHz reference clock for correct operation. This reference clock is generated by connecting a crystal to the XTAL- and XTAL+ pins of the device. Alternately, a 27MHz external clock source can be connected to the XTAL- pin of the device, while the XTAL+ pin should be left floating. 4.6 LOS (Loss Of Signal) Detection The LOS (Loss Of Signal) status pin is an active-high output that indicates when the serial digital input signal selected at the 4:1 input mux is invalid. In order for this output to be asserted, transitions must not be present for a period of tLA = 5 - 10μs. After this output has been asserted, LOS will de-assert within tLD = 0 - 5μs after the appearance of a transition at the DDIx input. See Figure 4-1. This signal is HIGH (signal lost), when the number of data edges within a window is below a defined threshold. The output is automatically muted when LOS is detected. This signal is LOW (signal valid), when the number of data edges within a window is above a defined threshold. See Table 4-4. Table 4-4: LOS Operation LOS Signal HIGH Invalid LOW Valid The LOS function is operational for all operating modes of the device. t LA t LD DATA LOS Figure 4-1: LOS Signal Timing The LOS detector has two major modes. In legacy mode, a simple edge-based detector is used to monitor the received signal at the output of the data slicer. Since the incoming signal has undergone considerable gain by this point, the legacy detector can be more susceptible to false de-assertion of LOS for unused channels which experience significant cross-talk from adjacent active channels. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 19 of 41 The new LOS detector uses a measure of both signal amplitude and duration to minimize false detection of the impulse like signals that are characteristic of cross-talk. In this mode, the signal is tapped off at the output of the equalizer stage, prior to the high gain buffers. The threshold setting within the detector can be adjusted to increase or decrease its sensitivity. Gennum recommends using the least sensitive threshold level. This provides the most margin against false de-assertion of LOS. Table 4-5: Suggested LOS Threshold Settings Input Signal Amplitude LOS Detection Method Select LOS Threshold Adjust >250mV 0x1 0x0 200mV to 250mV 0x1 0x1 150mV to 200mV 0x1 0x2 <150mV 0x1 or 0x0 0x3 The LOS mode can be selected by using the host interface, in register TOP_1 (address 0x02). 4.7 Serial Digital Reclocker The output of the Equalizer is fed to the reclocker. The function of the reclocker is to re-time the input signal and to generate system clocks. The reclocker operates at three frequencies; 2.97Gb/s, 1.485Gb/s and 270Mb/s, and provides a minimum input jitter tolerance of 0.8UI to square-wave-modulated jitter at these rates. When there is no serial input signal, the internal clock maintains a frequency close to the expected incoming data rate by locking to the external reference crystal. 4.8 Lock Detection The lock detect block indicates, via the active-high LOCKED signal, when the device has achieved lock to the incoming data stream. The lock logic within the GS2986 includes a system that monitors the frequency and the phase of the incoming data, as well as a monitor to detect harmonic lock. Table 4-6: Lock Operation LOCKED Status HIGH Locked LOW Not locked The LOCKED output signal is also available via the host interface. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 20 of 41 4.8.1 Lock Detect and Asynchronous Lock The reference crystal is used to assist the PLL in achieving short lock time. The lock detection algorithm is a continuous process, which begins at device power up or after a system reset, and continues until the device is powered down. The asynchronous lock time is defined as the time it takes the device to lock when a video signal is first applied to the serial digital inputs, or when the digital video signal rate changes. The synchronous lock time is defined as the time it takes the device to lock to a signal which has been momentarily interrupted. 4.9 Serial Data Output The GS2986 features two current-mode differential output drivers, each capable of driving a maximum of 800mVpp, differential, into an external 100Ω differential load. Each of the GS2986's output buffers include two on-chip, 50Ω termination resistors. 4.9.1 Output Signal Interface Levels The serial digital outputs of the GS2986 are compatible when DC-coupled with all Gennum serial digital interface products that feature a differential LVPECL or CML receiver designed for SDI applications and operate from 3.3V or 2.5V supplies. This includes but is not limited to: GS2978, GS2988, and GS2989. The serial digital data inputs are also compatible when DC-coupled with LVPECL or CML differential outputs from crosspoint switches which operate from 3.3V or 2.5V supplies. This includes but is not limited to: GS2974A, GS2974B, and GS2984 equalizers. 4.9.2 Adjustable Output Swing It is possible, via the host interface, to force the output swing to 400mVpp or 800mVpp differential, when the outputs are terminated with 50Ω loads. The default output swing upon power-up is 400mVpp differential. 4.9.3 Output De-emphasis The GS2986 features adjustable output de-emphasis to compensate for PCB trace dielectric losses. The output de-emphasis has eight settings, evenly distributed from a minimum of 0dB (output de-emphasis OFF) to a peak de-emphasis setting that is optimized for compensating the high-frequency losses associated with approximately 20 inches of 5-mil stripline in FR4 material. These settings are accessible via the serial host interface. The action of the de-emphasis settings is to attenuate the trailing edge of the output data waveform relative to the output swings set through the host interface. De-emphasis is turned OFF when in Bypass mode. The default de-emphasis setting upon power-up is 0dB (OFF). NOTE: Changing the de-emphasis setting will vary both V1 & V2 (see Figure 4-2). GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 21 of 41 Tx signal after de-emphasis 0.6 V1 0.4 V2 Volts 0.2 0 De-emphasis (dB) =20 log (V1/V2) -V2 -0.2 -0.4 -0.6 -V1 11110000 pattern 268 269 270 271 272 273 274 275 UI Figure 4-2: De-emphasis Waveform 4.10 Automatic and Manual Data Rate Selection The GS2986 can be configured to manually lock to a specific data rate or automatically search for and lock to the incoming data rate. The default configuration is AUTO mode. This can be changed via the host interface. In AUTO mode, the SS[1:0] registers become read only, and the bit pattern indicates the data rate at which the PLL is currently locked to (or previously locked to). The search algorithm cycles through the data rates and starts over if that data rate is not found (see Figure 4-3). A “search algorithm” cycles through the supported data rates until lock is achieved, as shown in Figure 4-3 below. Power up 270Mb/s 1485Mb/s 2970Mb/s *Note: the search algorithm does not necessarily begin with 270Mb/s. Figure 4-3: GS2986 Automatic Mode Search Algorithm In MANUAL mode, the SS[1:0] registers become read or write pins become inputs and the data rate can be programmed. In this mode, the search algorithm is disabled and the GS2986's PLL GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 22 of 41 will only lock to the data rate selected in accordance with Table 4-7. Table 4-7: Data Rate Indication/Selection Bit Pattern SS[1:0] Data Rate (Mb/s) 0 Reserved 1 270 2 1485 or 1485/1.001 3 2970 or 2970/1.001 4.11 SD/HD Indication The SD/HD signal indicates the output data rate of the device and can be connected to the SD/HD input pin of dual slew rate cable drivers such as the GS2988. When this signal is HIGH, the data rate is 270Mb/s. This signal is LOW for all other data rates. This signal is also LOW when the device is operating in bypass mode (Auto-bypass and User-bypass). The SD/HD signal is LOW when the device is not locked. 4.12 Bypass Mode In bypass mode, the GS2986 passes the data at the inputs, directly to the output. There are two register bits that control the bypass function: BYPASS and AUTOBYPASS. The BYPASS bit is an active-high signal which forces the GS2986 into bypass mode for as long as the bit is asserted HIGH. The AUTOBYPASS bit is an active-high signal that places the GS2986 into bypass mode only when the PLL has not locked to a data rate. Table 4-8: Bypass Modes Bypass Autobypass Device Operation HIGH X Bypass Mode LOW HIGH Bypass Mode if the PLL has not locked to a data rate LOW LOW Power-up default. Normal Operation, part always tries to lock to the incoming data stream. Note that if BYPASS is HIGH, this will override the AUTOBYPASS functionality. When the GS2986's PLL is not locked and BYPASS = LOW and AUTOBYPASS = LOW, the serial digital output DDO/DDO will produce invalid data. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 23 of 41 The AUTOBYPASS function will bypass unsupported (non-reclocked) SMPTE SDI signal rates without producing bit errors: 143Mb/s, 177Mb/s, 360Mb/s, 540Mb/s. 4.13 DVB-ASI The GS2986 also reclocks DVB-ASI signals at 270Mb/s. In auto mode, the device will automatically lock to the incoming 270Mb/s signal. In manual mode, the SS[1:0] pins must be set to 01 (270Mb/s) to ensure proper operation. 4.14 Output Mute and Data/Clock Output Selection The DATA_MUTE register is provided to allow muting of the serial digital data output. Setting DATA_MUTE = LOW will force the serial digital outputs DDO/DDO to mute (statically latch HIGH) under all conditions and operating modes. The DDO1_DISABLE pin is provided to allow the second data/clock output to be powered down. When DDO1_DISABLE is set LOW, the serial digital clock outputs DDO1/RCO and DDO1/RCO are muted and the driver is powered-down. The DATA/CLOCK register is provided to allow the second output to emit a copy of the reclocked serial data or the recovered clock. In Legacy mode, the default is DATA output. Table 4-9: Configuration of GS2986 Output Drivers and Mute/Disable Pins DATA_MUTE DDO1_DISABLE DATA/CLOCK DDO0 DDO1/RCO 1 1 0 DATA CLOCK 1 1 1 DATA DATA 0 1 0 MUTE CLOCK 0 1 1 MUTE MUTE 1 0 X DATA Power down 0 0 X MUTE Power down 4.15 Host Interface 4.15.1 Introduction The GS2986 offers a Serial Peripheral Interface (SPI) to access advanced features and programmability. The polarity of the HIF pin tells the GS2986 whether or not the host interface is active (HIF = 0) or in legacy mode (HIF = 1). Using the host interface, it is possible to override the control pin settings, and such settings will persist until the device has been powered-down and/or reset. The host interface is capable of GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 24 of 41 reading hard-wired pin configuration, pin override settings and the values of all status monitoring pins. There is an optional 3-state feature available in the Control Status Registers (CSR) that puts the SPI SDO to high-impedance when it’s not being used (Register: TOP_1, bit: 2). The maximum operating speed of the SPI is 10MHz. 4.15.2 Legacy Mode & Start-up In legacy mode, basic configuration of the device including a subset of equalizer settings are available at the pin level. In this mode, register settings are automatically set to default so that the IC is live at power-up. 4.15.3 Host Interface Mode & Start-up In host interface mode, the user gains access to Control and Status Registers (CSRs) that manage advanced features. In this mode, equalizer and de-emphasis settings are set through the CSR. The SPI control port is functional at start-up without the need for a separate, external reset signal. However, all internal registers must be set to their default state by issuing a required Reset Command via the SPI. This is done by setting the R bit (reset) LOW in the command word. This will guarantee the CSR will not start up in a random state. A simple way to issue the required reset of the CSR is to hold the slave device’s SDI input LOW for an entire 64 cycle WRITE communication. Details of the WRITE operation are found in section 4.15.6 below. 4.15.4 Clock & Data Timing The SPI signals are Serial Data Input (SDI), Serial Data Output (SDO), active-low Chip Select (CS), and Serial Clock Input (SCK). The host interface operates in SPI Mode 0, i.e. the SDI input will latch data in on the rising edge of SCK. The SDO data output will transition on falling edges of SCK. Data is transmitted or received on the SPI port MSB first LSB last. SCK CS Cycle # SDI SDO 1 2 3 4 5 6 7 8 z 1 2 3 4 5 6 7 8 z z 1 2 3 4 5 6 7 8 z Figure 4-4: Data Clock Alignment GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 25 of 41 4.15.5 Single Device Operation For applications with a single device or applications with multiple devices where daisy chaining is not desired, the chain position bits C[6:0] should always be set to 0. As a by-product of the daisy chaining feature, Read and Write operations experience a 32 SCK cycle latency from SDI to SDO. For more details on daisy-chaining, refer to Section 4.15.8 on page 29. rw 0 R A[4:0] C N[6:0] = `0000000’ Reset Address Chain Position 0 Read/ Write Figure 4-5: 16-bit Command Format 4.15.6 Write Operation - Single Device A Write operation consists of a 16-bit command word and a 16-bit data word, followed by 32 cycles with the slave SDI held HIGH. When writing to a single non-daisy chained device, the following format should be used: 16 bit command rw R/W 0 R A[4:0] C[6:0] = 0 Reset Address Chain Position 0 CS MOSI Command Command [15:0] Data [15:0] [15:0] MISO Data High 32 cycles Command’ [15:0] Data [15:0] Figure 4-6: Single Device Write 1. At power-up, the device should be reset by setting the R bit LOW. A simple way to accomplish a reset is to hold the slave SDI line low for an entire 64 cycle communication. 2. For a Write operation, the r/w bit should be set to 0. 3. The 2nd and 3rd bits are reserved and should be set to 0. 4. The R bit should always be set HIGH for a normal Write operation. 5. Refer to the Register Map for information on Address and Data bits. 6. The slave SDI line should be held HIGH for 32 cycles before de-asserting CS. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 26 of 41 4.15.7 Read Operation - Single Device For Reading from a device the following format should be used: 16 bit command rw R/W 0 R A[4:0] C[6:0] = 0 Reset Address Chain Position 0 CS MOSI Command [15:0] Data High 16 cycles MISO Data High 16 cycles Data High 16 cycles Command’ [15:0] Data [15:0] Figure 4-7: Single Device Read 1. For a Read operation, the r/w bit should be set to 1. 2. The 2nd and 3rd bits are reserved and should be set to 0. 3. The R bit should always be set HIGH for a normal Read Operation. 4. Data Out at the slave SDO will appear after holding the slave SDI line HIGH for 32 cycles. 5. The 16-bit data is now available on the slave SDO line. Detailed timing diagrams for Write and Read can be seen in Figure 4-8 and Figure 4-9. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 27 of 41 R/W 0 0 t3 R t1 A4 A3 t2 A2 A1 A0 t8 C6 C5 C4 R/W 0 t3 0 R t1 A4 A3 t2 A2 A1 A0 t8 C6 C5 t6 t7 t8 Output hold time (15pF load) CS_n HIGH after last HOST_CLK rising edge Input data hold time GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 t3 Input data setup time D8 t2 D9 HOST_CLK duty cycle C0 D10 t1 C1 D15 D14 D13 D12 D11 HOST_CLK period C0 t0 C2 C1 CS_n LOW before HOST_CLK rising edge C3 C2 Symbol C4 C3 Parameter Table 4-10: GSPI Time Delay Figure 4-9: SPI Read Timing 32 cycles delayed SDO SDI CS SCK t0 Figure 4-8: SPI Write Timing 32 cycles delayed SDO SDI CS SCK t0 D7 D6 D5 D4 D2 D1 D0 R/W 0 50% levels Conditions D3 0 t6 R/W R 0 A4 R A4 A1 A0 − − − − − − − − 1.5 1.5 1.5 C1 60 C2 1.5 C0 D9 D8 D7 ns ns ns ns % ns ns Units D15 D14 D13 D12 D13 D12 D11 D10 50 C3 D15 D14 40 C4 C0 − C5 C1 − C6 C2 100 A0 C3 − A1 C4 − A2 C5 Max A3 C6 Typ Min A2 75% of HOST_CLK period 0 A3 D11 D6 D10 D5 D9 D4 D8 D3 D7 D2 D6 D1 D5 D0 t7 D4 D3 D2 D1 28 of 41 D0 4.15.8 Daisy Chain Operation For applications with multiple GS2986 devices, it is possible to daisy-chain up to 127 parts in serial. In this configuration, the first device SDI should be connected to the SPI Master SDO. The serial data output of each device is then connected to the serial data input of the following device, and so on. The last device's SDO connects to the Master's SDI. Connecting devices in serial reduces the number of I/O ports required by the master by removing the need for additional chip select lines. SPI Master SCK SDO SDI CS SCK SDI SDO CS SPI Slave Chain Position 0 SCK SDI SDO CS SPI Slave Chain Position 1 SCK SDI SDO CS SPI Slave Chain Position 2 Figure 4-10: Daisy Chained SPI Bus The position of each GS2986 device in the serial chain is referred to as its Chain Position, with 0 corresponding to the first device. The Chain Position in the SPI command word is decoded by each slave to know which device the master is talking to. Each GS2986 slave is designed to output a replica of what it receives at its input after a delay of 32 cycles. The Chain Position part of the command is decremented by one in the duplicated command word at the output. Each device in the chain will only execute the issued command if it verifies that the current chain position is set to 0. A[4:0] C[6:0]=N Chain Position A[4:0] C[6:0]=N-1 Chain Position -1 32 cycles A[4:0] 32 cycles SDI SDO GS2986 SDI SDO C[6:0]=N-2 Chain Position -2 GS2986 Figure 4-11: Chain Position Decoding GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 29 of 41 4.15.9 Read & Write Operation - Daisy Chained Devices In a serial daisy chain configuration, Read and/or Write operations can be performed to multiple devices in the chain via consecutive operations. Figure 4-12 below shows a simple 3 device configuration. MISO MOSI µC SDI SDO GS2986 SDI SDO GS2986 SDI SDO GS2986 Figure 4-12: Three Devices in Daisy Chain Configuration 4.15.10 Writing to all Devices When writing to all devices in the chain, a Write Command and corresponding Data is required for each device. When the devices are being configured in the same way, all of them will have the same command and data with the exception of the Chain Position bits. This example assumes a 3-device daisy chain. A command is issued to the last device in the chain first, although it is possible to talk to the devices in any order. CS MOSI Command2 [15:0] Data [15:0] Command1 [15:0] Data [15:0] Command0 [15:0] Data [15:0] Data High 32 cycles Chain Position = 2 Chain Position = 1 Chain Position = 0 MISO Command0' [15:0] Data [15:0] Figure 4-13: Daisy Chain Write 1. The first command issued in time is the command for the last device in the chain (chain position = 2). When the first device receives this command it will recognize that the Chain Position is 2 and will not execute the command. It will duplicate the command and data word at its output and decrement the Chain Position by one. 2. Consecutive commands are issued for each device in the chain as shown. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 30 of 41 4.15.11 Writing to a Single Device in the Chain The following example shows how to write to a single device in a chain: CS MOSI CommandN [15:0] DataN [15:0] Data High 32xN cycles Data High 32 cycles Chain Position = N MISO CommandN’ [15:0] DataN [15:0] Chain Position = N (N = 0 for first device in chain) Figure 4-14: Daisy Chain Write to a Single Device 1. The command is issued to Chain Position N. 2. 32xN cycles are required to shift the command through N devices. The device at chain position N executes the command. 3. 32 additional cycles are needed to complete the communication. 4.15.12 Reading from all Devices To read from all devices in the chain, a Read command is issued for each device consecutively. After each command, the data is held HIGH for 16 cycles. Once a device recognizes it is being talked to, it will output data from the register requested. Clock needs to be applied to cycle the output data through all devices in the chain. CS SDI Command 2 Data HIGH for 16 cycles (Chain Position = 2) Command 1 Data HIGH for 16 cycles Command 0 Data HIGH for 16 cycles (Chain Position = 0) (Chain Position = 1) SDO CS SDI Data held HIGH for 32x3 cycles SDO Command2’ Data2 Command1’ Data1 Command0’ Data0 Figure 4-15: Daisy Chain Read 1. Read command is issued to the last device in the chain, followed by Read commands to the lower chain positions. 2. Clock is applied to cycle the output data through the chain. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 31 of 41 3. Command2’ refers to the altered or decremented Command2. 4.15.13 Reading from a Single Device in the Chain The following example shows how to read from a single device in a chain: CS MOSI CommandN [15:0] Data High 16 cycles Data High 32xN cycles Data High 32x(K-N-1) cycles Data High 16 cycles Data High 16 cycles CommandN’ [15:0] DataN [15:0] Chain Position = N MISO Chain Position = N (N = 0 for first device in chain) Chain Length = K (K ≥ 1) Figure 4-16: Daisy Chain Read from a Single Device 1. Read command and 16 cycles of data held HIGH are issued to chain position N. 2. 32xN cycles are applied with data HIGH to cycle the command through N devices in the chain (NOTE: N is 0 for first device in chain). Device N executes the command. 3. With K representing the total number of devices in the chain, 32x(K-N-1) cycles are applied to bring the return data through the rest of the chain. 4. 16 additional cycles are applied until the Data from device N is available on the Master SDI. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 32 of 41 4.15.14 Host Register Map Table 4-11: Host Register Map Register Name Register Address Bit Position Access Function Default Value Valid Range Comments EQ_1 0x00 15:10 RW Reserved. 9 RW Input Attenuation Enable (ATTEN_EN) 0x0 0 or 1 Enable for input signals above 1Vpp differential 8 RW Equalizer Offset Correction Enable 0x1 0 or 1 Recommend always on 7 RW Equalizer Gain Setting for DDI3 0x0 0 or 1 See supplementary table below 6 RW Equalizer Gain Setting for DDI2 0x0 0 or 1 See supplementary table below 5 RW Equalizer Gain Setting for DDI1 0x00 0 or 1 See supplementary table below 4 RW Equalizer Gain Setting for DDI0 0x00 0 or 1 See supplementary table below 3 RW Equalizer Enable for DDI3 0x00 0 or 1 See supplementary table below 2 RW Equalizer Enable for DDI2 0x00 0 or 1 See supplementary table below 1 RW Equalizer Enable for DDI1 0x00 0 or 1 See supplementary table below 0 RW Equalizer Enable for DDI0 0x00 0 or 1 See supplementary table below Equalizer Decode Logic EQ_EN EQ_GAIN EQ Setting Recommended Trace Lengths 0 0 LOW 0 to 10 inches of FR4 0 1 LOW 0 to 10 inches of FR4 1 0 MED 10 to 20 inches of FR4 1 1 HIGH 20 or more inches of FR4 GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 33 of 41 Table 4-11: Host Register Map (Continued) Register Name Register Address Bit Position Access DRIVER_1 0x01 15:10 RW 9 Function Default Value Valid Range Comments Unused 0x0 0 or 1 − RW Amplitude Control for DDO1 0x1 0 or 1 0 = 800mV swing 1 = 400mV swing 8 RW Amplitude Control for DDO0 0x1 0 or 1 0 = 800mV swing 1 = 400mV swing 7:5 RW De-Emphasis Boost Amplitude Control for DDO1 0x2 0x0 to 0x7 0x0 = Lowest Setting 0x7 = Highest Setting 4:2 RW De-Emphasis Boost Amplitude Control for DDO0 0x2 0x0 to 0x7 0x0 = Lowest Setting 0x7 = Highest Setting 1 RW De-Emphasis Enable for DDO1 0x0 0 or 1 1 = Enabled 0 = Disabled 0 RW De-Emphasis Enable for DDO0 0x0 0 or 1 1 = Enabled 0 = Disabled TOP_1 0x02 15:9 RW Reserved. 8:7 RW LOS Threshold Adjust 0x0 0x0 to 0x3 0x0 = least sensitive 0x3 = most sensitive 6:5 RW LOS Detection Method Select 0x0 0x0 to 0x2 0x0 = legacy edge detectionmethod 0x1 = new signal strength detectionmethod 0x2 = dual detection method: both must say signal present for LOS to be LOW 4 RW LOS Mute Enable 0x0 0 or 1 When enabled the output will automatically mute if Loss of Signal is HIGH 3 RW Power Down 0x0 0 or 1 Chip powers down when asserted 2 RW Tri-State Enable for SPI Output 0x0 0 or 1 When enabled the SPI SDO will be high Z when CS is not selected GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 34 of 41 Table 4-11: Host Register Map (Continued) Register Name Register Address Bit Position Access TOP_1 0x02 1 RW 0 0X03 to 0X0B PIN_OR_1 STATUS_1 0x0C 0X0D 0X0E to 0X11 Function Default Value Valid Range Comments Crystal Buffer Disable 0x0 0 or 1 0 = Enabled 1 = Disabled RW Data Polarity Invert 0x0 0 or 1 0 = Not Inverted 1 = Inverted 15:13 RW Unused 0x0 0 or 1 − 12 RW DATA/CLOCK 0x0 0 or 1 − 11 RW DDO1_DIASBLE 0x0 0 or 1 − 10 RW DATA_MUTE 0x0 0 or 1 − 9:8 RW KBB 0x0 0x0, 0x2 or 0x3 Equivalent settings: 0x0 = KBB to ground 0x2 = KBB floating 0x3 = KBB to VCC 7 RW SS1 0x0 0 or 1 − 6 RW SS0 0x0 0 or 1 − 5 RW AUTO/MAN 0x0 0 or 1 − 4 RW AUTOBYPASS 0x0 0 or 1 − 3 RW BYPASS 0x0 0 or 1 − 2 RW DDI_SEL1 0x0 0 or 1 − 1 RW DDI_SEL0 0x0 0 or 1 − 0 RW Pin Override Enable 0x0 0 or 1 When enabled input values will be taken from this register instead of package pins 15:4 RO Reserved. − − − 3 RO SD/HD − − − 2 RO LOCKED − − − 1 RO SS1 − − − 0 RO SS0 − − − Reserved. Reserved. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 35 of 41 4.16 Device Power-up In host mode (HIF pin tied LOW), control & status registers (CSRs) may start up in a random state. There is a bit in the command word R which will reset the CSR when set LOW. In non-host mode (HIF pin tied HIGH), the HIF pin is used to trigger an internal reset signal to place all registers in a deterministic, default state upon power-up. In either host mode or non-host mode, other internal state machines (e.g. offset correction and PLL) automatically recover from any state at start-up with no reset required. It takes ~10μs for the device to lock after start-up. 4.17 Standby The purpose of Standby mode is to allow operating power to be reduced when the device's functionality is not required, and to have a rapid and simple transition to full operation when the device is required. In order to achieve this, the device can be powered-down by writing a ‘1’ to the ‘Power Down’ bit located in register address 0x02. GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 36 of 41 18p CS/EQ3_EN GND XTAL_BUF_OUT 27MHz 1M HIF 3 31 32 XTAL- XTAL+ 33 CS/EQ3_EN 34 SCK/EQ2_EN 35 SDO/EQ1_EN 36 SDI/EQ0_EN 37 39 38 VEE_CP VEE_DDO0 VCC_DDO0 HIF DDO0 4 DDI0 DDO0 5 DDI1 6 VEE_DDO1 GS2986 VCC_DDO1 DDI1 30 29 28 25 24 DDO1/RCO DDI2 DDO1/RCO 23 9 DDI3 10 DDI3 VSS_DIG 10n GND Data Output 0 VCC GND 10n Data Output 1/ Serial Clock 22 21 GND SD/HD 20 LOS LOCKED 220n DDI_SEL1 DDI_SEL0 10u VCC VDD_DIG VCC 10n 1u 19 LOS LOCKED 17 18 VDD_1P8 16 VEE_VCO 15 11 VCC_VCO DDI2 SD/HD GND 10n 26 8 DDO1_DISABLE VCC 27 7 RSVD Data Input 3 DDI0 14 Data Input 2 2 DDI_SEL1 Data Input 1 CP_CAP 13 Data Input 0 1 DDI_SEL0 GND 12 220n VCC_CP LF+ 40 10n DDO1_DISABLE VCC 18p SCK/EQ2_EN SDI/EQ0_EN 47n GND SDO/EQ1_EN 5. Typical Application Circuit R* GND Note: R* value is set to 267Ω for 2.5v supply or 422Ω for 3.3v supply. Figure 5-1: GS2986 Typical Application Circuit GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 37 of 41 6. Package and Ordering Information 6.1 Package Dimensions GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 38 of 41 6.2 Recommended PCB Footprint 0.28 0.5 0.85 4.5 5.1 5.95 6.8 4.5 0.25 5.1 6.8 NOTE: All dimensions are in millimeters. 6.3 Packaging Data Parameter Value Package Type 6mm x 6mm 40-pin QFN Moisture Sensitivity Level 3 Junction to Case Thermal Resistance, θj-c 19.9°C/W Junction to Air Thermal Resistance, θj-a (at zero airflow) 34.9°C/W Junction to Board Thermal Resistance, θj-b 12.5°C/W Psi, ψ 0.5°C/W Pb-free and RoHS Compliant Yes GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 39 of 41 6.4 Marking Diagram Pin 1 ID GS2986 XXXXE3 YYWW XXXX - Last 4 digits (excluding decimal) of SAP Batch Assembly (FIN) as listed on Packing Slip. E3 - Pb-free & Green indicator YYWW - Date Code 6.5 Solder Reflow Profile Temperature 60-150 sec. 20-40 sec. 260°C 250°C 3°C/sec max 217°C 6°C/sec max 200°C 150°C 25°C Time 60-180 sec. max 8 min. max Figure 6-1: Maximum Pb-free Solder Reflow Profile 6.6 Ordering Information Part Number Package Temperature Range GS2986 GS2986-INE3 Pb-free 40-pin QFN -40°C to 85°C GS2986 GS2986-INTE3 Pb-free 40-pin QFN (250pc. tape and reel) -40°C to 85°C GS2986 GS2986-INTE3Z Pb-free 40-pin QFN (2.5k tape and reel) -40°C to 85°C GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 40 of 41 DOCUMENT IDENTIFICATION CAUTION DATA SHEET ELECTROSTATIC SENSITIVE DEVICES Information relating to this product and the application or design described herein is believed to be reliable, however such information is provided as a guide only and Semtech assumes no liability for any errors in this document, or for the application or design described herein. Semtech reserves the right to make changes to the product or this document at any time without notice. DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION © Semtech 2012 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. Semtech assumes no responsibility or liability whatsoever for any failure or unexpected operation resulting from misuse, neglect improper installation, repair or improper handling or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified range. SEMTECH PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF SEMTECH PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK. Should a customer purchase or use Semtech products for any such unauthorized application, the customer shall indemnify and hold Semtech and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Contact Information Semtech Corporation Gennum Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805) 498-2111, Fax: (805) 498-3804 www.semtech.com GS2986 Multi-Rate SDI Reclocker with Equalization & De-emphasis Data Sheet 52134 - 3 July 2012 41 of 41 41