NSC LMP8350MANOPB Lmp8350 ultra low distortion fully differential precision adc driver with selectable power mode Datasheet

LMP8350
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SNOSB80B – FEBRUARY 2011 – REVISED MARCH 2013
LMP8350 Ultra Low Distortion Fully Differential Precision ADC Driver with Selectable
Power Modes
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FEATURES
DESCRIPTION
•
•
•
•
•
•
The LMP8350 is an ultra low distortion fully
differential amplifier designed for driving highperformance precision analog-to-digital converters
(ADC). As part of the PowerWise™ family, a unique
mode enable pin allows the user to choose from three
different
operating
modes,
trading
power
consumption for dynamic performance.
1
234
Differential Input and Output
Tri-Level Power Settings with Shutdown
Ultra Low HD2/HD3 and THD+N Distortion
Adjustable Output Common Mode Level
Fully Balanced Differential Architecture
Single or Dual Supply Operation
APPLICATIONS
•
•
•
High Resolution Differential ADC Driver
Portable instrumentation
Precision Line Driver
KEY SPECIFICATIONS
(TA = 25°C, VS = +10V, RL = 2kΩ//20pF, typical
values unless otherwise specified)
•
•
•
•
•
•
•
•
•
•
Operating Voltage Range 4.5V to 12V
Supply Current 3 to 13mA
Total THD+N @ 1KHz 0.000097%
HD2 / HD3 Distortion @ 1KHz < –124 dBc
Bandwidth 118 mHz
Settling to 0.1% 20 ns
Low Offset Drift 0.4 µV/°C
Offset Voltage 80µV
Voltage Noise 4.6nV/Hz
Operating temperature range −40°C to +85°C
The high power mode is optimized for highest AC
performance. The low noise, wide bandwidth and fast
slew rate makes the LMP8350 ideal for driving 24bit
ADCs with input sampling rates of 10MHz or less.
The medium power mode is optimized for precision
DC performance, and can be used to drive 24-bit
ADCs with input sampling rates of 6MHz or less. The
low power mode is a trade-off between AC
performance and quiescent current for power
sensitive applications. The disable mode fully shutsdown the amplifier for further standby power savings.
The fully differential architecture of this device allows
for easy implementation of a single-ended to fullydifferential output conversion. Driving a 3Vpp, 1kHz
output sine wave with the amplifier powered by ±3.3V
rails in high power mode yields 0.000098% THD+N.
The LMP8350 is part of the LMP™ precision amplifier
family. It is offered in the 8-Pin SOIC package and
has an operating temperature range of −40°C to
+85°C.
1
2
3
4
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
LMP is a trademark of Texas Instruments.
PowerWise is a trademark of National Semiconductor Corporation.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011–2013, Texas Instruments Incorporated
LMP8350
SNOSB80B – FEBRUARY 2011 – REVISED MARCH 2013
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Typical Application
+VREF
+V
+V
VREFP
VA
VIO
+V
RF1
RO1
RG1
VINN
CS
- +
VOCM
+ VINP
CS
LMP8350
SCLK
24 Bit A/D
RO2
VINP
- VINN
+ RG2
SDI
SDO
MicroController
VREFN AGND DGND
RF2
Typical Application Circuit
Connection Diagram
-IN
VOCM
V+
+OUT
1
2
8
-
+
7
3
6
4
5
+IN
EN
V-
-OUT
Figure 1. 8-Pin SOIC
Top View
PIN DESCRIPTIONS
2
Pin
Name
1
-IN
2
VOCM
Description
Inverting Input
Output Common Mode voltage set input. Sets output common mode voltage equal to the applied VOCM pin
voltage.
3
V+
4
+OUT
Positive Power Supply Voltage
Non-Inverting Output
5
-OUT
Inverting Output
6
V-
Negative Power Supply Voltage
7
EN
Enable and Power Select input. Applied voltage sets power level or shutdown mode.
8
+IN
Non-Inverting Input
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings (1) (2)
ESD Tolerance (3)
Human Body Model
2500 V
Machine Model
200V
Charge-Device Model
1250V
See (4)
Output Short Circuit Duration
V+ relative to V-
-0.3 to +12.9V
IN+, IN-, OUT, EN and VOCM Pins
V+ + 0.3V, V- – 0.3V
Input Current
1 mA
−65°C to +150°C
Storage Temperature Range
Junction Temperature (5)
+150°C
For soldering specifications: http://www.ti.com/lit/SNOA549
(1)
(2)
(3)
(4)
(5)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit
operation at elevated ambient temperature can exceed the maximum allowable junction temperature of 150°C. Positive number (+) is
sourcing, negative number (-) is sinking.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
Operating Ratings (1)
−40°C to +85°C
Temperature Range (TA)
+
–
Supply Voltage (VS = V – V )
4.5V to 12V
Package Thermal Resistance (θJA) (2)
(1)
(2)
8-Pin SOIC
150°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA. The maximum allowable power dissipation at any ambient temperature is
PD = (TJ(MAX) – TA)/ θJA. All numbers apply for packages soldered directly onto a PC Board.
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+10V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +10V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply
at the temperature extremes.
Symbol
Conditions (2)
Typ (4)
Max (3)
High Power
±0.6
±4
±4.05
Mid Power
±0.08
±2
±2.03
Low Power
±0.1
±2.5
±2.52
High Power
±0.8
Mid Power
±0.5
Low Power
±0.4
Parameter
Min (3)
Units
10V DC Characteristics
VOS
Input Offset Voltage
(RTI)
TCVOS
IB
Input Offset Voltage vs.Temperature (5)
Input Bias Current
AVOL
CMVR
CMRR
Open Loop Gain
Common Mode Voltage Range (6)
Common Mode Rejection Ratio
mV
μV/°C
High Power
2
2.1
Mid Power
2.7
3.2
Low Power
3.5
3.7
High Power
65
90
Mid Power
72
130
Low Power
74
114
HP @ CMRR ≥73dB
1.2
8.8
MP @ CMRR ≥83dB
1.2
8.8
LP @ CMRR ≥77dB
1.2
8.8
DC, VOCM=0,VID=0,
ΔVcm=±0.2V
High Power
75
90
Medium Power
84
130
Low Power
79
114
μA
dB
V
dB
ZIND
Differential Input Resistance
VCM = mid supply
0.48
MΩ
CIND
Differential Input Capacitance
VCM = mid supply
1
pF
VO
Output Swing
(Single Ended)
(1)
(2)
(3)
(4)
(5)
(6)
4
High Power
0.86
0.75 to
9.25
Mid Power
0.85
0.74 to
9.26
9.15
Low Power
0.86
0.81 to
9.19
9.14
9.14
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA
For annotation brevity, “HP”=High Power, “MP”=Medium Power, “LP” =Low Power, “DIS”=Disabled or shut down, “SE”=Single Ended
Mode, “DM”=Differential Mode. See Table 1 in Applications section for power setting details. It is also assumed RG = RG1 = RG2
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Drift Determined by dividing the change in parameter at temperature extremes by the total temperature change. Value is the worst case
of TaMIN to 25°C and 25°C to TaMAX.
At amplifier inputs.
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+10V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +10V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply
at the temperature extremes.
Symbol
ISHORT
PSRR
IS
Short-Circuit Current
Power Supply Rejection Ratio
VS ±10%
Supply Current
PD
Power Down Mode
ten
Conditions (2)
Min (3)
Typ (4)
+75 / -36
+108 / -65
Medium Power
+60 / -26
+85 / -48
Low Power
+15 / -6
+36 / -20
Parameter
Enable Time
Output Shorted to mid supply
High Power
Max (3)
High Power
107
Mid Power
118
Low Power
124
mA
dB
15
18
20
VEN=6.25 (8)
8
10
11
VEN=3.75 (8)
3
4
5
VEN=8.75
Units
(7)
(8)
Disable Voltage Threshold (8)
mA
<1.65
Shutdown Current
0.75
Enable Pin Current
100
High Power
15
Mid Power
20
Low Power
40
High Power
118
Mid Power
87
V
0.9
0.95
mA
μA
ns
10V AC Characteristics
SSBW
SR
trise
tfall
ts
en
(7)
(8)
(9)
Small Signal Bandwidth
200mVp-p Differential
Slew Rate
2Vp-p Differential (9)
Rise Time
2Vp-p Differential
Fall Time
2Vp-p Differential
0.1% Settling Time
2Vp-p
Input Referred Voltage Noise
@ 10KHz
Low Power
31
High Power
507
Mid Power
393
Low Power
178
High Power
3.0
Mid Power
3.9
Low Power
9.7
High Power
2.8
Mid Power
3.8
Low Power
9.6
2V Step, CL = 20pF
High Power
20
Mid Power
25
Low Power
38
High Power
4.6
Mid Power
4.8
Low Power
8
MHz
V/μs
ns
ns
ns
nV/√Hz
The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit
operation at elevated ambient temperature can exceed the maximum allowable junction temperature of 150°C. Positive number (+) is
sourcing, negative number (-) is sinking.
Enable voltage is referred to V- (negative supply voltage).
Slew Rate is the average of the rising and falling edges.
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+10V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +10V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply
at the temperature extremes.
Symbol
In
THD+N
HD2
Input Referred Current Noise
@ 10KHz
Total Harmonic Distortion + Noise
3Vp-p @ 1KHz
2nd Harmonic Distortion
3Vp-p, 1KHz
2nd Harmonic Distortion
6Vp-p, 1KHz
HD3
Conditions (2)
Parameter
3rd Harmonic Distortion
3Vp-p, 1KHz
3rd Harmonic Distortion
6Vp-p, 1KHz
Min (3)
Typ (4)
f = 10 kHz
High Power
1.7
Mid Power
1.1
Low Power
0.6
High Power
0.000097
Mid Power
0.000109
Low Power
0.000185
High Power
–124.7
Mid Power
–122.8
Low Power
–117.2
High Power
–118.9
Mid Power
–117.6
Low Power
–114.7
High Power
–139.9
Mid Power
–141.9
Low Power
–133.3
High Power
–129.5
Mid Power
–132.4
Low Power
–129.4
High Power
4.8
Mid Power
2.4
Low Power
0.64
High Power
±1.62
Mid Power
±0.23
Max (3)
Units
pA/√Hz
%
–116
dBc
dBc
–126
dBc
dBc
10V VOCM Input Characteristics
VOCM Small Signal Bandwidth
200mVp-p
VOCM Gain
VOCM Offset Voltage
1
Low Power
VOCM Voltage Range
VOCM Input Resistance
6
MHz
V/V
mV
±0.43
All Power Levels
1.8 to 8.2
V
All power levels
30 to mid
supply
KΩ
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+6.6V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +6.6V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply
at the temperature extremes..
Symbol
Conditions (2)
Typ (4)
Max (3)
High Power
±0.3
±3.5
±3.54
Mid Power
±0.1
±2.8
±2.83
Low Power
±0.1
±2.5
±2.52
High Power
±0.7
Mid Power
±0.5
Low Power
±0.4
Parameter
Min (3)
Units
6.6V DC Characteristics
VOS
Input Offset Voltage
(RTI)
TCVOS
IB
Input Offset Voltage vs.Temperature (5)
Input Bias Current
AVOL
CMVR
CMRR
Open Loop Gain
Common Mode Voltage Range (6)
Common Mode Rejection Ratio
mV
μV/°C
High Power
1.4
2.4
Mid Power
2.5
3.0
Low Power
3.5
3.7
High Power
65
70
Mid Power
73
76
Low Power
72
75
HP @ CMRR ≥68dB
1.2
5.4
MP @ CMRR ≥63dB
1.2
5.4
LP @ CMRR ≥ 79dB
1.2
5.4
DC, VOCM=0,VID=0,
ΔVcm=±0.2V
High Power
70
85
Mid Power
86
117
Low Power
81
113
μA
dB
V
dB
ZIND
Differential Input Resistance
VCM = mid supply
0.48
MΩ
CIND
Differential Input Capacitance
VCM = mid supply
1
pF
VO
Output Swing
(Single Ended)
(1)
(2)
(3)
(4)
(5)
(6)
High Power
0.84
0.77 to
5.83
Mid Power
0.82
0.75 to
5.83
5.78
Low Power
0.83
0.77 to
5.83
5.77
5.76
V
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA
For annotation brevity, “HP”=High Power, “MP”=Medium Power, “LP” =Low Power, “DIS”=Disabled or shut down, “SE”=Single Ended
Mode, “DM”=Differential Mode. See Table 1 in Applications section for power setting details. It is also assumed RG = RG1 = RG2
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Drift Determined by dividing the change in parameter at temperature extremes by the total temperature change. Value is the worst case
of TaMIN to 25°C and 25°C to TaMAX.
At amplifier inputs.
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+6.6V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +6.6V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply
at the temperature extremes..
Symbol
ISHORT
PSRR
Conditions (2)
Min (3)
Typ (4)
+54 / –30
+83 / –49
Mid Power
+40 / –19
+64 / –35
Low Power
+15 / –6
+27 / –15
Parameter
Short-Circuit Current
Power Supply Rejection Ratio
VS ±10%
Output Shorted to mid supply
High Power
High Power
111
Mid Power
117
Low Power
IS
Supply Current
PD
Power Down Mode
ten
Enable Time
Max (3)
mA
dB
127
14
16
18
VEN=4.125 (8)
7
9
10
VEN=2.475 (8)
2
3
4
VEN=5.775
Units
(7)
(8)
Disable Voltage Threshold (8)
<1.225
Shutdown Current
0.55
Enable Pin Current
40
High Power
18
Mid Power
22
Low Power
43
High Power
116
Mid Power
85
mA
V
0.65
0.7
mA
μA
ns
6.6V AC Characteristics
SSBW
SR
trise
tfall
ts
en
In
(7)
(8)
(9)
8
Small Signal Bandwidth
200mVp-p Differential
Slew Rate
2Vp-p Differential (9)
Rise Time
2Vp-p Differential
Fall Time
2Vp-p Differential
0.1% Settling Time
2Vp-p
Input Referred Voltage Noise
@ 10KHz
Input Referred Current Noise
@ 10KHz
Low Power
29
High Power
488
Mid Power
376
Low Power
166
High Power
3.1
Mid Power
4.2
Low Power
10.4
High Power
3.0
Mid Power
4.0
Low Power
10.3
2V Step, CL = 20pF
High Power
19
Mid Power
25
Low Power
43
High Power
4.5
Mid Power
4.8
Low Power
8
High Power
1.7
Mid Power
1.2
Low Power
0.6
MHz
V/μs
ns
ns
ns
nV/√Hz
pA/√Hz
The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit
operation at elevated ambient temperature can exceed the maximum allowable junction temperature of 150°C. Positive number (+) is
sourcing, negative number (-) is sinking.
Enable voltage is referred to V- (negative supply voltage).
Slew Rate is the average of the rising and falling edges.
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+6.6V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF = RG = 1kΩ, Fully differential input, VS = +6.6V,
RL = 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply
at the temperature extremes..
Symbol
THD+N
HD2
Total Harmonic Distortion + Noise
3Vp-p @ 1KHz
2nd Harmonic Distortion
3Vp-p, 1KHz
2nd Harmonic Distortion
6Vp-p, 1KHz
HD3
Conditions (2)
Parameter
3rd Harmonic Distortion
3Vp-p, 1KHz
3rd Harmonic Distortion
6Vp-p, 1KHz
Min (3)
Typ (4)
High Power
0.000098
Mid Power
0.00011
Low Power
0.000089
High Power
–124.7
Mid Power
–122.8
Low Power
–117.2
High Power
–118.9
Mid Power
–117.6
Low Power
–114.7
High Power
–139.9
Mid Power
-141.9
Low Power
–133.3
High Power
–121.4
Mid Power
–125.3
Low Power
–124.5
High Power
4.5
Mid Power
2.2
Low Power
0.6
High Power
±0.97
Mid Power
±0.43
Max (3)
Units
%
dBc
dBc
dBc
dBc
6.6V VOCM Input Characteristics
VOCM Small Signal Bandwidth
200mVp-p
VOCM Gain
VOCM Offset Voltage
1
Low Power
VOCM Voltage Range
VOCM Input Resistance
MHz
V/V
mV
±0.89
All Power Levels
1.2 to 5.4
V
All power levels
30 to mid
supply
KΩ
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+5V Electrical Characteristics (1)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF=RG = 1kΩ, Fully differential input, VS = +5V, RL
= 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply at
the temperature extremes.
Symbol
Typ (3)
Max (2)
High Power
±0.2
±3.2
±3.6
Mid Power
±0.1
±2.0
±2.3
Low Power
±0.1
±2.0
±2.3
High Power
±0.7
Mid Power
±0.5
Low Power
±0.4
Parameter
Min (2)
Conditions
Units
5V DC Characteristics
VOS
Input Offset Voltage
(RTI)
TCVOS
IB
Input Offset Voltage vs.Temperature (4)
Input Bias Current
AVOL
CMVR
CMRR
Open Loop Gain
Common Mode Voltage Range (5)
Common Mode Rejection Ratio
μV/°C
High Power
1.5
1.6
Mid Power
2.5
3.0
Low Power
3.5
3.7
High Power
63
68
Mid Power
71
75
Low Power
68
75
mV
μA
dB
HP @ CMRR ≥60dB
1.15
3.85
MP @ CMRR ≥86dB
1.15
3.85
LP @ CMRR ≥80dB
1.15
3.85
DC, VOCM=0,VID=0,
ΔVcm=±0.2V
High Power
63
79
Mid Power
87
114
Low Power
82
114
V
dB
ZIND
Differential Input Resistance
VCM = mid supply
0.48
MΩ
CIND
Differential Input Capacitance
VCM = mid supply
1
pF
VO
Output Swing
(Single Ended)
ISHORT
(1)
(2)
(3)
(4)
(5)
(6)
10
Short-Circuit Current
High Power
0.82
0.77 to
4.23
Mid Power
0.82
0.75 to
4.25
4.18
Low Power
0.83
0.77 to
4.23
4.17
+44 / –25
+72 / –42
Mid Power
+34 / –16
+57 / –31
Low Power
+12 / –5
+23 / –13
Output Shorted to mid supply
High Power
4.18
V
(6)
mA
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No ensured specification of parametric performance is indicated in the electrical
tables under conditions of internal self-heating where TJ > TA
Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlations using the
Statistical Quality Control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped
production material.
Drift Determined by dividing the change in parameter at temperature extremes by the total temperature change. Value is the worst case
of TaMIN to 25°C and 25°C to TaMAX.
At amplifier inputs.
The short circuit test is a momentary test which applies to both single-supply and split-supply operation. Continuous short circuit
operation at elevated ambient temperature can exceed the maximum allowable junction temperature of 150°C. Positive number (+) is
sourcing, negative number (-) is sinking.
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+5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF=RG = 1kΩ, Fully differential input, VS = +5V, RL
= 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply at
the temperature extremes.
Symbol
PSRR
Parameter
Power Supply Rejection Ratio
VS ±10%
Conditions
Supply Current
PD
Power Down Mode
ten
Enable Time
Typ (3)
High Power
117
Mid Power
120
Low Power
IS
Min (2)
Max (2)
dB
111
13
15
17
VEN=3.125 (7)
7
9
10
VEN=1.875 (7)
2
3
4
VEN=4.375
(7)
Disable Voltage Threshold (7)
Units
mA
<1.025
Shutdown Current
0.50
Enable Pin Current
15
High Power
20
Mid Power
22
Low Power
50
High Power
114.5
Mid Power
84
V
0.85
0.90
mA
μA
ns
5V AC Characteristics
SSBW
SR
Slew Rate
2Vp-p Differential (8)
trIse
Rise Time
2Vp-p Differential
tfall
Fall Time
2Vp-p Differential
ts
0.1% Settling Time
2Vp-p
en
Input Referred Voltage Noise
In
Input Referred Current Noise
THD+N
(7)
(8)
Small Signal Bandwidth
200mVp-p Differential
Total Harmonic Distortion + Noise
3Vp-p @ 1KHz
Low Power
28
High Power
476
Mid Power
366
Low Power
160
High Power
3.2
Mid Power
4.3
Low Power
10.8
High Power
3.1
Mid Power
4.1
Low Power
10.7
2V Step, CL = 20pF
High Power
19
Mid Power
24
Low Power
48
f = 10 kHz
High Power
4.5
Mid Power
4.8
Low Power
8
f = 10 kHz
High Power
1.8
Mid Power
1.2
Low Power
0.6
High Power
0.000107
Mid Power
0.000114
Low Power
0.000192
MHz
V/μs
ns
ns
ns
nV/√Hz
pA/√Hz
%
Enable voltage is referred to V- (negative supply voltage).
Slew Rate is the average of the rising and falling edges.
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+5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are ensured for TA = 25°C, Avcl = +1, RF=RG = 1kΩ, Fully differential input, VS = +5V, RL
= 2 kΩ//20pF differentially, Input CMR and VOCM=mid supply and HP mode unless otherwise noted. Boldface limits apply at
the temperature extremes.
Symbol
HD2
HD3
Parameter
nd
2 Harmonic Distortion
3Vp-p, 1KHz
Conditions
Min (2)
Typ (3)
Max (2)
Units
High Power
–125.3
Mid Power
–122.6
Low Power
–117.0
High Power
–125.5
Mid Power
–130.0
Low Power
–128.7
High Power
4.4
Mid Power
2.2
Low Power
0.56
High Power
±0.46
Mid Power
±0.53
Low Power
±0.11
VOCM Voltage Range
All Power Levels
1.15 to
3.85
V
VOCM Input Resistance
All power levels
30 to mid
supply
KΩ
3rd Harmonic Distortion
3Vp-p, 1KHz
dBc
dBc
5V VOCM Input Characteristics
VOCM Small Signal Bandwidth
200mVp-p
VOCM Gain
VOCM Offset Voltage
12
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V/V
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Typical Performance Characteristics
Unless otherwise specified, TA = 25°C, Avcl = +1, RF=RG = 1kΩ, fully differential input, VS = +10V, RL = 2 kΩ//20pF
differentially, Input CMR and VOCM = mid supply and HP mode unless otherwise noted.
VOCM Frequency Response at 10V
3
0
0
HP
VOCMGAIN (dB)
DIFFERENTIAL GAIN (dB)
Frequency Response at 10V
3
-3
-6
HP
-9
Avcl = +1
Vout = 200mVp-p
Differential
-12
-15
1M
MP
-3
-6
-9
MP
-12
ûVocm = 200mVp-p
LP
10M
100M
FREQUENCY (Hz)
1G
10k
Figure 2.
100M
VOCM Frequency Response at 6.6V
3
3
0
0
HP
VOCMGAIN (dB)
DIFFERENTIAL GAIN (dB)
100k
1M
10M
FREQUENCY (Hz)
Figure 3.
Frequency Response at 6.6V
-3
-6
HP
-9
-3
-6
-9
MP
-12
Avcl = +1
Vout = 200mVp-p
Differential
-15
1M
MP
-12
ûVocm = 200mVp-p
LP
LP
-15
10M
100M
FREQUENCY (Hz)
1G
10k
Figure 4.
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 5.
Frequency Response at 5V
VOCM Frequency Response at 5V
3
3
0
0
HP
VOCMGAIN (dB)
DIFFERENTIAL GAIN (dB)
LP
-15
-3
-6
HP
-9
-12
Avcl = +1
Vout = 200mVp-p
Differential
-15
1M
MP
-6
MP
-9
-12
ûVocm = 200mVpp
LP
10M
100M
FREQUENCY (Hz)
-3
LP
-15
1G
Figure 6.
10k
100k
1M
10M
FREQUENCY (Hz)
100M
Figure 7.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, Avcl = +1, RF=RG = 1kΩ, fully differential input, VS = +10V, RL = 2 kΩ//20pF
differentially, Input CMR and VOCM = mid supply and HP mode unless otherwise noted.
Distortion at 10V, High Power
Distortion at 6.6V, High Power
-40
-40
f = 1KHz
f = 1KHz
-60
DISTORTION (dBc)
DISTORTION (dBc)
-60
-80
-100
HD2
-120
HD3
-140
-80
-100
HD2
-120
-140
HD3
-160
-160
0
2 4 6 8 10 12 14 16 18
DIFFERENTIAL OUTPUT (Vpp)
0
2
4
6
8
10
DIFFERENTIAL OUTPUT (Vpp)
Figure 8.
Figure 9.
Distortion at 10V, Mid Power
Distortion at 6.6V, Mid Power
-40
-40
f = 1KHz
f = 1KHz
-60
DISTORTION (dBc)
-60
DISTORTION (dBc)
12
-80
-100
HD2
-120
-140
-80
-100
HD2
-120
-140
HD3
HD3
-160
-160
0
2 4 6 8 10 12 14 16 18
DIFFERENTIAL OUTPUT (Vpp)
0
2
4
6
8
10
DIFFERENTIAL OUTPUT (Vpp)
Figure 10.
Figure 11.
Distortion at 10V, Low Power
Distortion at 6.6V, Low Power
-40
-40
f = 1KHz
f = 1KHz
-60
DISTORTION (dBc)
DISTORTION (dBc)
-60
-80
-100
HD2
-120
-140
-80
-100
HD2
-120
-140
HD3
-160
HD3
-160
0
2 4 6 8 10 12 14 16 18
DIFFERENTIAL OUTPUT (Vpp)
Figure 12.
14
12
0
2
4
6
8
10
DIFFERENTIAL OUTPUT (Vpp)
12
Figure 13.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, Avcl = +1, RF=RG = 1kΩ, fully differential input, VS = +10V, RL = 2 kΩ//20pF
differentially, Input CMR and VOCM = mid supply and HP mode unless otherwise noted.
Distortion at 5V, High Power
THD+N at 10V
1
-40
f = 1 kHz
BW = 22 kHz
f = 1KHz
0.1
-80
THD+N (%)
DISTORTION (dBc)
-60
HD3
-100
LP
0.01
HP
0.001
-120
-140
0.00001
HD2
-160
0
1
2
3
4
5
6
7
DIFFERENTIAL OUTPUT (Vpp)
MP
0.000001
0
8
2
4
6
Figure 15.
Distortion at 5V, Mid Power
THD+N at 6.6V
1
-40
f = 1 kHz
BW = 22 kHz
f = 1KHz
-60
0.1
-80
THD+N (%)
DISTORTION (dBc)
10 12 14 16 18 20
DIFFERENTIAL OUTPUT (Vp-p)
Figure 14.
-100
HD2
LP
0.01
HP
0.001
-120
0.0001
-140
MP
HD3
-160
0
1
2
3
4
5
6
7
DIFFERENTIAL OUTPUT (Vpp)
0.00001
0
8
2
4
6
8
10
12
DIFFERENTIAL OUTPUT (Vp-p)
Figure 16.
Figure 17.
Distortion at 5V, Low Power
THD+N at 5V
-40
1
f = 1 kHz
BW = 22 kHz
f = 1KHz
-60
0.1
-80
THD+N (%)
DISTORTION (dBc)
8
-100
HD2
-120
-140
0.01
HP
LP
0.001
MP
0.0001
HD3
-160
0
1
2
3
4
5
6
7
DIFFERENTIAL OUTPUT (Vpp)
8
0.00001
0
1
2
3
4
5
6
7
8
9
10
DIFFERENTIAL OUTPUT (Vp-p)
Figure 18.
Figure 19.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, Avcl = +1, RF=RG = 1kΩ, fully differential input, VS = +10V, RL = 2 kΩ//20pF
differentially, Input CMR and VOCM = mid supply and HP mode unless otherwise noted.
Voltage Noise at 10V
Current Noise at 10V
100
100
HP
CURRENT NOISE (S$¥+])
VOLTAGE NOISE (Q9¥+])
HP
MP
10
LP
Differential Out
Referred to Input
1
MP
10
LP
1
Differential Out
Referred to Input
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 20.
Figure 21.
Voltage Noise at 6.6V
Current Noise at 6.6V
100
100
HP
CURRENT NOISE (S$¥+])
VOLTAGE NOISE (Q9¥+])
HP
LP
10
MP
Differential Out
Referred to Input
1
MP
10
LP
1
Differential Out
Referred to Input
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
1
10
100
1k
10k
FREQUENCY (Hz)
Figure 22.
Voltage Noise at 5V
Current Noise at 5V
100
HP
HP
CURRENT NOISE (S$¥+])
VOLTAGE NOISE (Q9¥+])
100k
Figure 23.
100
MP
10
LP
Differential Out
Referred to Input
1
MP
10
LP
1
Differential Out
Referred to Input
0.1
1
10
100
1k
10k
FREQUENCY (Hz)
100k
Figure 24.
16
100k
1
10
100
1k
10k
FREQUENCY (Hz)
100k
Figure 25.
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Typical Performance Characteristics (continued)
Unless otherwise specified, TA = 25°C, Avcl = +1, RF=RG = 1kΩ, fully differential input, VS = +10V, RL = 2 kΩ//20pF
differentially, Input CMR and VOCM = mid supply and HP mode unless otherwise noted.
Pulse Response at 10V
Pulse Response at 6.6V
1.5
MP
HP
DIFFERENTIAL OUTPUT (Vpp)
DIFFERENTIAL OUTPUT (Vpp)
1.5
1.0
0.5
0.0
-0.5
LP
-1.0
MP
-1.5
0
40
0.5
0.0
-0.5
LP
-1.0
MP
-1.5
80
120
TIME (ns)
160
MP
HP
1.0
200
0
Figure 26.
40
80
120
TIME (ns)
160
200
Figure 27.
Pulse Response at 5V
DIFFERENTIAL OUTPUT (Vpp)
1.5
HP
MP
1.0
0.5
0.0
-0.5
LP
-1.0
-1.5
MP
0 20 40 60 80 100 120 140 160 180 200
TIME (ns)
Figure 28.
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APPLICATION SECTION
The LMP8350 is a fully differential voltage feedback amplifier designed to drive precision differential ADC
converters. The LMP8350, though fully integrated for ultimate balance and distortion performance, functionally
provides three channels. Two of these channels are the V+ and V− signal path channels, which function similarly
to inverting mode operational amplifiers and are the primary signal paths.
The third “channel” is the common mode (VOCM) feedback circuit. This is the circuit that sets the output common
mode as well as driving the V+ and V− outputs to be equal magnitude and opposite phase, even when only one
of the two input channels is driven. The common mode feedback circuit allows for single ended to differential
operation. The output common mode voltage is set by applying the appropriate voltage to the VOCM pin.
ENABLE PIN AND POWER MODE SELECTION
The LMP8350 is equipped with a four level enable (EN) pin to select one of three power modes or shutdown.
These modes are selected by applying the appropriate voltage to the EN pin.
Each power level has a corresponding performance level. The high power mode will have the best overall BW
and distortion performance, but at the cost of higher supply current and some DC accuracy. The Low power
mode has the lowest supply current, but with a noticeable loss of AC performance and output drive capabilities.
The mid-power mode provides the best balance of AC and precision DC specifications. In disable mode, the
amplifier is shutdown and the output stage goes into a high impedance state. Table 1 summarizes these
performance trade-offs.
Table 1. Performance vs. Power Mode Summary
Mode
High
Med
Low
VS
–3dB BW
(MHz)
HD2
(dBc)
Noise
(nV/Hz)
SR
(V/µS)
Typ Vos
(mV)
10
118
–124.7
4.6
507
0.6
6.6
116
–124.7
4.5
488
0.3
5
114
–125.5
4.5
476
0.2
10
87
–122.8
4.8
393
0.08
6.6
85
–122.8
4.8
376
0.1
5
84
–122.6
4.8
366
0.1
10
31
–117.2
8.0
178
0.1
6.6
29
–117.2
8.0
166
0.1
5
28
–117.0
8.0
160
0.1
To set the mode, internally the voltage at the EN pin is compared against the total supply voltage (VS) and sets
the current consumption as shown in the table below. The EN pin voltage is referenced to the V- pin.
Table 2. Enable Pin Mode Selection
VEN
(VS = V+ - V-)
Power
Mode
VEN @ 10V
VEN @ 6.6V
VEN @ 5V
IS
mA
7/8 * VS
High
8.75
5.775
4.375
13 to 15
5/8 * VS
Med
6.25
4.125
3.125
7 to 9
3/8 * VS
Low
3.75
2.475
1.875
2 to 3
1/8 * VS
Dis
1.25
0.825
0.625
<1
The enable pin should not be allowed to float. If the enable pin is not used it can be tied to V+ to select the high
power mode or set with two resistors.
Each power setting has a +/-400mV tolerance at each level, though it is recommended to keep the set voltage
within the center of the range as performance may vary near the transition zones.
During shutdown, both outputs are in a high impedance state, so the feedback and gain set resistors will then set
the input and output impedance of the circuit. For this reason input to output isolation will be poor in the disabled
state.
18
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The voltage at the EN pin can be generated with a resistive voltage divider or a buffer connected to a voltage
source or a DAC. The schematic diagram below shows how to generate EN voltage with a resistive voltage
divider.
Values of RA and RB can be calculated to achieve the voltages in Table 2, however their sum should be below
50kΩ to keep the voltage at the enable pin stable. Recommended values for Ra and Rb are given in Table 3.
Table 3. Recommended Ra and Rb for Mode Selection
Mode
10V
6.6V
5V
VEN
High Power
RA=0
RB=inf
RA=0
RB=inf
RA=0
RB=inf
>7/8 VS
Med Power
RA=18K
RB=30K
RA=18K
RB=30K
RA=18K
RB=30K
5/8 VS
Low Power
RA=33K
RB=18K
RA=33K
RB=18K
RA=33K
RB=18K
3/8 VS
Shutdown
RA=Inf
RB=0
RA=Inf
RB=0
RA=Inf
RB=0
<1/8 VS
VOCM PIN AND OUTPUT COMMON MODE SETTING
Output common mode voltage is set by the VOCM pin. Both outputs will be offset in the same direction (phase) by
an amount equal to the applied VOCM voltage.
The VOCM pin, if left unconnected, will self-bias to mid-supply . Two internal 60KΩ resistors set this midpoint.
These resistors are shown in Figure 29.
+
V
60 k:
Internal
Circuitry
VOCM
Input
60 k:
V
-
Figure 29. VOCM Internal Bias Circuit
The equivalent resistance looking into the VOCM pin will look like 30KΩ to mid supply, plus about ±700nA for
internal base currents (which scales with power mode and supply current). If left floating, the VOCM input should
be bypassed to ground with a 0.1 µF ceramic capacitor.
If a different output common mode voltage is desired, the VOCM pin should be driven by a clean, low impedance
source to override the internal divider resistors. The VOCM pin should be bypassed to ground with a 0.1 µF
ceramic capacitor. It should be noted that any signal or noise coupling into the VOCM will be passed as common
mode noise and may result in the loss of dynamic range, degraded CMRR, degraded balance and higher
distortion. The VOCM pin is primarily intended as a DC bias path and is not intended for use as a signal path.
For applications that can tolerate slight shifts in the VOCMvoltage over temperature, it is also possible to use a
single resistor to program the VOCM voltage by paralleling one of the internal resistors to change the ratio.
FULL BANDWIDTH LIMITATIONS
Although the LMP8350 has a unity gain bandwidth of over 200MHz, it is primarily intended for lower sample rate,
high-precision ADC’s with baseband analog input signal bandwidths in the DC to <1MHz range (not to be
confused with sampling rate). The LMP8350's high open loop bandwidth is used to provide ultra low-distortion
and fast settling times. Maximum power bandwidth is limited by the internal output common mode feedback path,
which is limited to 1MHz to 5MHz. Operation with input signals above 1MHz with near full output swings can
cause random shifts in the output common mode and possible AC instabilities. For this reason, the LMP8350 is
not intended to be used wide bandwidth (>1MHz) signal paths. Single ended inputs rely on the common mode
signal path and will have a bandwidth limited to that of the internal common mode buffer.
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FULLY DIFFERENTIAL OPERATION
The LMP8350 will perform best when used with split supplies and in a fully differential configuration. See
Figure 30 for recommend circuits.
RF1
RO
RG1
+
VI
a
CL
VOCM
RL
VO
RG2
RO
RF2
EN
Figure 30. Typical Fully Differential Application
The circuit shown in Figure 30 is a typical fully differential application as might be used to drive a Sigma Delta
ADC. In this circuit, closed loop gain, is (AV) = VOUT/ VIN = RF/RG, where RF=RF1=RF2 and RG=RG1=RG2. For all
the applications in this data sheet , VIN is presumed to be the voltage presented to the circuit by the signal
source. For differential signals this will be the difference of the signals on each input (which will be double the
magnitude of each individual signal), while in single ended inputs it will just be the driven input signal.
When fed with a differential signal, the LMP8350 provides excellent distortion, balance and common mode
rejection, provided the resistors RF, RG and any input termination resistors (RT) are well matched and strict
symmetry is observed in board layout. With a DC CMRR of over 80 dB, the DC and low frequency CMRR of
most circuits will be dominated by the external resistor matching and board trace resistance. At low distortion
levels, board layout symmetry and supply bypassing become a factor as well. It is assumed throughout this
document that RF1 = RF2 and RG1 = RG2 for maximum channel symmetry
Precision resistors of at least 0.1% accuracy or better are recommended and careful board layout will also be
required for optimum performance.
Operation with RF feedback resistors as low as 300 ohms is possible in the High and Medium power modes. This
will slightly improve the noise and bandwidth results. However, feedback resistors with RF values of less than
1KΩ should be avoided in the low power mode due to the reduced output drive current capabilities. If low value
resistors (<300Ω) must be used in the low power mode, the maximum output swing will need to be limited.
The resistors RO help keep the amplifier stable when presented with a load CL, as is common when driving an
analog to digital converter (ADC).
1000
50:
100:
TWISTED PAIR
500
+
2 VPP
a
VOCM
500
2 VPP
50:
1000
GAIN = 2
EN
Figure 31. Fully Differential Cable Driver
20
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With up to 15 VPP differential output voltage swing and 80 mA of linear drive current, the LMP8350 makes an
excellent precision cable driver as shown in Figure 31. The LMP8350 is also suitable for driving differential
cables from a single ended source.
RF
RO
RG
RS
VI
+
a
RT
RL
CL
VOCM
VO
RG
RM
RO
RF
EN
SET RM = RT||RS
1
-
1
RIN
§
¨¨
©
§ 1
¨R
© S
RIN =
RG
RF
§
1- ¨
2
*
(R
F + RG)
©
§
¨¨
©
SET RT =
Figure 32. Single Ended in Differential Out
SINGLE ENDED INPUT TO DIFFERENTIAL OUTPUT
Figure 32 shows a typical application where an LMP8350 is used to produce a differential signal from a single
ended source. It should be noted that compared to differential input, using a single ended input will reduce gain
by 1/2, so that the closed loop gain will be; Gain = AV = 0.5 * RF/RG.
In single ended input operation the output common mode voltage is set by the VOCM pin. Also, In this mode the
common mode feedback circuit must recreate the signal that is not present on the unused differential input pin.
The common mode feedback circuit is responsible for ensuring balanced output with a single ended input.
Balance error is defined as the amount of input signal that couples into the output common mode. It is measured
as the undesired output common mode swing divided by the signal on the input. Balance error can be caused by
either a channel to channel gain error, or phase error. Either condition will produce a common mode shift. As
mentioned in the previous FULL BANDWIDTH LIMITATIONS section, the overall bandwidth is limited due to the
VOCM buffer bandwidth limitations in this configuration.
Supply and VOCM pin bypassing are also critical in this mode of operation.
SINGLE SUPPLY OPERATION
As shown in Figure 33, the input common mode voltage is less than the output common voltage. It is set by
current flowing through the feedback network from the device output. The input common mode voltage range
places constraints on gain settings. Possible solutions to this limitation include AC coupling the input signal,
using split power supplies and limiting stage gain. AC coupling with single supply is shown in Figure 34.
VICM= Input common mode voltage = (V+IN+V−IN)/2.
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RF
RO
VO1
RG
RS
VI1
+
VI
a
RL
CL
VOCM
RT
VO
RG
VI2
VO2
RM
RO
RF
EN
*VCM =
VO1 + VO2
VICM = VOCM *
2
*BY DESIGN
(RG + RM)
(RG + RM + RF)
=a
VOCM
1 + AV
WHERE RM << RG
Figure 33. Relating AV to Input/Output Common Mode Voltages
In Figure 33 the differential closed loop gain is = AV= RF/RG. Please note that in single ended to differential
operation VIN is measured single ended while VOUT is measured differentially. This means that gain is really onehalf, or 6 dB, less when measured on either of the output pins separately.
RF
RO
RG
RS
VO1
VI1
+
VI
a
RT
RL
CL
VOCM
VO
RG
RM
VI2
VO2
RO
RF
EN
*VCM =
VO1 + VO2
2
*BY DESIGN
VICM = VOCM
VICM =
VI1 + VI2
2
Figure 34. AC Coupled for Single Supply Operation
POWER SUPPLY AND VOCM BYPASSING
The LMP8350 requires supply bypassing capacitors as shown in Figure 35 and Figure 36 for fastest settling time
and overall stability.
22
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+
V
0.01 PF
10 PF
+
VOCM
0.1 PF
0.1 PF
0.01 PF
10 PF
V
-
Figure 35. Split Supply Bypassing Capacitors
The 0.01 µF and 0.1 µF capacitors should be leadless surface mount (SMT) ceramic capacitors and should be
no more than 3 mm from the supply pins. The SMT capacitors should be connected directly to a ground plane.
Thin traces or small vias will reduce the effectiveness of bypass capacitors.
V
+
0.01 PF
0.1 PF
10 PF
+
VOCM
0.1 PF
Figure 36. Single Supply Bypassing Capacitors
Also shown in both figures is a capacitor from the VOCM pin to ground. The VOCM pin sets the output common
mode voltage. Any noise on this input is transferred directly to the output. The VOCM pin should be bypassed
even if the pin in not used. There is an internal resistive divider on chip to set the output common mode voltage
to the mid point of the supply pins. The impedance looking into this pin is approximately 30 kΩ. If a different
output common mode voltage is desired drive this pin with a clean, accurate voltage reference.
DRIVING ANALOG TO DIGITAL CONVERTERS
Analog to digital converters (ADC) present challenging load conditions. They typically have high impedance
inputs with large and often variable capacitive components. As well, there are usually current spikes associated
with switched capacitor or sample and hold circuits. Figure 37 shows a typical circuit for driving an ADC. The two
resistors serve to isolate the capacitive loading of the ADC from the amplifier and ensure stability. In addition, the
resistors form part of a low pass filter which helps to provide anti alias and noise reduction functions. The CS
capacitor helps to smooth the current spikes associated with the internal switching circuits of the ADC and also
are a key component in the low pass filtering of the ADC input. The capacitor should be a low distortion
capacitor, such as an NPO, to avoid causing significant distortion terms. In the circuit of Figure 37, the cutoff
frequency of the filter is 1/ (2*π*(RISO1+RISO2) *(CS + CCONVERTER)), which should be slightly less than the
sampling frequency. Note that the ADC input capacitance must be factored into the frequency response of the
input filter. Also as shown in Figure 37, the input capacitance to many ADCs is variable based on the clock cycle.
For lower speed, precision ADC's, the external cap is generally sized to ten times the internal sampling capacitor
value. See the data sheet for your particular ADC for details.
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RF1
RISO1
RG1
+
VI
a
VOCM
CS
-
A/D
8-18 pF
RG2
RISO2
RF2
VREF
EN
LOW IMPEDANCE
VOLTAGE REFERENCE
Figure 37. Driving an ADC
The amplifier and ADC should be located as close together as possible. Both devices require that the filter
components be in close proximity to them. The amplifier needs to have minimal parasitic loading on the output
traces, and the ADC is sensitive to high frequency noise that may couple in on its input lines. Some high
performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling
process results in all input signals presented to the input stage mixing down into the Nyquist range (DC to Fs/2).
See AN-236 (SNAA079) for more details on the subsampling process and the requirements this imposes on the
filtering necessary in your system.
CAPACITIVE DRIVE
As noted in the Driving ADC section, capacitive loads should be isolated from the amplifier output with small
valued resistors. This is particularly the case when the load has a resistive component that is 500Ω or higher. A
typical ADC has capacitive components of around 8 to 18pF, and the resistive component could be 1000Ω or
higher. If driving a transmission line, such as a twisted pair, using matching resistors will be sufficient to isolate
any subsequent capacitance.
POWER DISSIPATION
The LMP8350 is optimized for maximum performance in the small form factor of the standard SOIC package,
and is essentially a dual channel amplifier. To ensure maximum output drive and highest performance, thermal
shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX of 150°C is never
exceeded due to the overall power dissipation.
Follow these steps to determine the Maximum power dissipation for the LMP8350:
1. Calculate the quiescent (no-load) power: PAMP = ICC* (VS), where VS = V+ - V−. (Be sure to include any
current through the feedback network if VOCM is not mid rail.)
2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS - V+OUT) * I+OUT) + rms
((VS − V−OUT) * I−OUT) , where VOUT and IOUT are the voltage and the current measured at the output pins of
the differential amplifier as if they were single ended amplifiers and VS is the total supply voltage.
3. Calculate the total RMS power: PT = PAMP + PD.
The maximum power that the LMP8350 package can dissipate at a given temperature can be derived with the
following equation:
PMAX = (150° – TAMB)/ θJA, where TAMB = Ambient temperature (°C) and θJA = Thermal resistance, from junction
to ambient, for a given package (°C/W). For the SOIC package θJA is 150°C/W.
NOTE: If VOCM is not 0V then there will be quiescent current flowing in the feedback network. This current should
be included in the thermal calculations and added into the quiescent power dissipation of the amplifier.
24
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SNOSB80B – FEBRUARY 2011 – REVISED MARCH 2013
ESD PROTECTION
The LMP8350 is protected against electrostatic discharge (ESD) on all pins. The LMP8350 will survive 2000V
Human Body model and 200V Machine model events. Under normal operation the ESD diodes have no effect on
circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMP8350 is
driven by a large signal while the device is powered down the ESD diodes will conduct . The current that flows
through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is
possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to
conserve power and still prevent unexpected operation.
BOARD LAYOUT
While the main signal path frequencies may be fairly low, the ultra-low distortion and settling time specifications
rely on wide internal bandwidths. Precautions usually taken for high speed amplifiers should be followed to
maintain the best settling times and lowest distortion specifications. In order to get maximum benefit from the
differential circuit architecture, board layout and component selection is very critical. The circuit board should
have low a inductance ground plane and well bypassed broad supply lines. External components should be
leadless surface mount types. The feedback network and output matching resistors should be composed of short
traces and precision resistors (0.1%). The output matching resistors should be placed within 3-4 mm of the
amplifier as should the supply bypass capacitors.
The LMP8350 is sensitive to parasitic capacitances on the outputs. Ground and power plane metal should be
removed from beneath the amplifier and from beneath RF and RG.
With any differential signal path symmetry is very important. Even small amounts of asymmetry will contribute to
distortion and balance errors. Special attention should be paid to where the bypass capacitors are grounded, as
this also affects settling and distortion performance.
The LMH730154 evaluation board is an example of good layout techniques. Evaluation boards are available for
purchase through the product folder on TI’s web site.
EVALUATION BOARD
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15 for more information). Texas Instruments suggests the
following evaluation boards as a guide for high frequency layout and as an aid in device testing and
characterization:
Device
Package
Evaluation Board Part Number
LMP8350MA
SOIC
LMH730154
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LMP8350
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
26
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
LMP8350MA/NOPB
ACTIVE
SOIC
D
8
95
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMP83
50MA
LMP8350MAX/NOPB
ACTIVE
SOIC
D
8
2500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 85
LMP83
50MA
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LMP8350MAX/NOPB
Package Package Pins
Type Drawing
SOIC
D
8
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
2500
330.0
12.4
Pack Materials-Page 1
6.5
B0
(mm)
K0
(mm)
P1
(mm)
5.4
2.0
8.0
W
Pin1
(mm) Quadrant
12.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-Apr-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMP8350MAX/NOPB
SOIC
D
8
2500
367.0
367.0
35.0
Pack Materials-Page 2
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