HCPL-3150 (Single Channel), HCPL-315J (Dual Channel) 0.5 Amp Output Current IGBT Gate Drive Optocoupler Data Sheet Lead (Pb) Free RoHS 6 fully compliant RoHS 6 fully compliant options available; -xxxE denotes a lead-free product Description Features The HCPL-315X consists of an LED optically coupled to an integrated circuit with a power output stage. This optocoupler is ideally suited for driving power IGBTs and MOSFETs used in motor control inverter applications. The high operating voltage range of the output stage provides the drive voltages required by gate controlled devices. The voltage and current supplied by this optocoupler makes it ideally suited for directly driving IGBTs with ratings up to 1200 V/50 A. For IGBTs with higher ratings, the HCPL-3150/315J can be used to drive a discrete power stage which drives the IGBT gate. x 0.6A maximum peak output current x 0.5 A minimum peak output current x 15 kV/μs minimum Common Mode Rejection (CMR) at VCM = 1500 V x 1.0V maximum low level output voltage (VOL) eliminates need for negative gate drive x ICC = 5 mA maximum supply current x Under Voltage Lock-Out protection (UVLO) with hysteresis x Wide operating VCC range: 15 to 30 volts Applications x 0.5 μs maximum propagation delay x Isolated IGBT/MOSFET gate drive x AC and brushless dc motor drives x +/– 0.35 μs maximum delay between devices/ channels x Industrial inverters x Industrial temperature range: -40°C to 100°C x Switch Mode Power Supplies (SMPS) x HCPL-315J: channel one to channel two output isolation = 1500 Vrms/1 min. x Uninterruptable Power Supplies (UPS) x Safety and regulatory approval: UL recognized (UL1577), 3750 Vrms/1 min (HCPL-3150) 5000 Vrms/1 min (HCPL-315J) IEC/EN/DIN EN 60747-5-2 approved VIORM = 630 Vpeak (HCPL-3150 option 060 only) VIORM = 1230 Vpeak (HCPL-315J) CSA certified Functional Diagram N/C ANODE 1 8 2 CATHODE 3 N/C 4 7 SHIELD HCPL-3150 VCC VO 6 VO 5 VEE N/C 1 16 VCC ANODE 2 15 VO CATHODE 3 SHIELD LED VCC - VEE “Positive Going” (i.e., Turn-On) VCC - VEE “Negative-Going” (i.e., Turn-Off) VO OFF ON ON ON 0 - 30 V 0 - 11 V 11 - 13.5 V 13.5 - 30 V 0 - 30 V 0 - 9.5 V 9.5 - 12 V 12 - 30 V LOW LOW TRANSITION HIGH 14 VEE ANODE 6 11 VCC CATHODE 7 10 VO N/C 8 SHIELD TRUTH TABLE 9 VEE HCPL-315J A 0.1 μF bypass capacitor must be connected between the VCC and VEE pins for each channel. CAUTION: It is advised that normal static precautions be taken in handling and assembly of this component to prevent damage and/or degradation which may be induced by ESD. Selection Guide: Invertor Gate Drive Optoisolators Package Type Part Number Number of Channels Widebody (400 mil) 8-Pin DIP (300 mil) Small Outline SO-16 HCPL3150 HCPL-3120 HCPLJ312 HCPL-J314 HCNW-3120 HCPL-315J HCPL-316J HCPL-314J 1 1 1 1 1 2 1 2 IEC/EN/DIN EN 60747-5-2 Approvals VIORM 630 Vpeak Option 060 VIORM 1230Vpeak VIORM 1414 Vpeak VIORM 1230 Vpeak UL Approval 5000 Vrms/1 min. 5000 Vrms/1 min. 5000 Vrms/1min. 5000 Vrms/1 min. Output Peak Current 0.5A 2A CMR (minimum) UVLO 2A 0.4A 2A 0.5A 2A 0.4A 15 kV/μs 10 kV/μs 15 kV/μs 10 kV/μs Yes No Yes No Fault Status No Yes No Ordering Information HCPL-3150 is UL Recognized with 3750 Vrms for 1 minute per UL1577. HCPL-315J is UL Recognized with 5000 Vrms for 1 minute per UL1577. Option Part Number HCPL-3150 HCPL-315J RoHS Compliant Non RoHS Compliant -000E No option -300E #300 x x -500E #500 x x -060E #060 -360E #360 x x -560E #560 x x -000E No option x -500E #500 Package Surface Mount Gull Wing Tape & Reel IEC/EN/DIN EN 60747-5-2 Quantity 50 per tube 300 mil DIP-8 SO-16 x 50 per tube x x x 1000 per reel x 50 per tube x 50 per tube x 1000 per reel x 45 per tube x 850 per reel To order, choose a part number from the part number column and combine with the desired option from the option column to form an order entry. Example 1: HCPL-3150-560E to order product of 300 mil DIP Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/DIN EN 60747-5-2 Safety Approval in RoHS compliant. Example 2: HCPL-3150 to order product of 300 mil DIP package in tube packaging and non RoHS compliant. Option datasheets are available. Contact your Avago sales representative or authorized distributor for information. Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and RoHS compliant option will use ‘-XXXE’. 2 Package Outline Drawings Standard DIP Package 9.40 (0.370) 9.90 (0.390) 8 7 6 5 OPTION CODE* A 3150 Z YYWW PIN ONE 1 2 3 0.20 (0.008) 0.33 (0.013) 6.10 (0.240) 6.60 (0.260) DATE CODE 7.36 (0.290) 7.88 (0.310) 5° TYP. 4 1.78 (0.070) MAX. 1.19 (0.047) MAX. 3.56 ± 0.13 (0.140 ± 0.005) 4.70 (0.185) MAX. DIMENSIONS PIN IN MILLIMETERS AND (INCHES). DIAGRAM PIN ONE 0.51 (0.020) MIN. 2.92 (0.115) MIN. 0.76 (0.030) 1.40 (0.055) 0.65 (0.025) MAX. * MARKING1 CODE 8 OPTION NUMBERS. VDD1LETTER VDD2FOR "V" = OPTION 060. OPTION NUMBERS AND 500 7 NOT MARKED. 2 VIN+ 300 VOUT+ NOTE: FLOATING IS 0.25 mm (10 mils) MAX. 6 3 V LEAD V PROTRUSION IN– 2.28 (0.090) 2.80 (0.110) 4 OUT– GND1 GND2 5 Package Outline Drawings Gull-Wing Surface-Mount Option 300 LAND PATTERN RECOMMENDATION 9.65 ± 0.25 (0.380 ± 0.010) 8 7 6 OPTION CODE* 5 A 3150 Z 6.350 ± 0.25 (0.250 ± 0.010) YYWW MOLDED 1 2 3 1.016 (0.040) 10.9 (0.430) 4 1.27 (0.050) 9.65 ± 0.25 (0.380 ± 0.010) 1.780 (0.070) MAX. 1.19 (0.047) MAX. 7.62 ± 0.25 (0.300 ± 0.010) 0.20 (0.008) 0.33 (0.013) 3.56 ± 0.13 (0.140 ± 0.005) 1.080 ± 0.320 (0.043 ± 0.013) 2.540 (0.100) BSC 0.635 ± 0.130 (0.025 ± 0.005) DIMENSIONS IN MILLIMETERS (INCHES). TOLERANCES (UNLESS OTHERWISE SPECIFIED): xx.xx = 0.01 xx.xxx = 0.005 LEAD COPLANARITY MAXIMUM: 0.102 (0.004) NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. 3 2.0 (0.080) 0.635 ± 0.25 (0.025 ± 0.010) 12° NOM. *MARKING CODE LETTER FOR OPTION NUMBERS. "V" = OPTION 060. OPTION NUMBERS 300 AND 500 NOT MARKED. 16 - Lead Surface Mount 9 VO2 11 10 GND2 VO1 10.36 ± 0.20 (0.408 ± 0.008) GND1 VCC1 16 15 14 VCC2 LAND PATTERN RECOMMENDATION (0.295 ± 0.004) 7.49 ± 0.10 NC VIN1 V1 VIN2 V2 NC HCPL-315J 1 2 3 6 7 8 (0.458) 11.63 (0.085) 2.16 (0.025) 0.64 (0.004 – 0.011) 0.10 – 0.30 STANDOFF (0.345 ± 0.008) 8.76 ± 0.20 VIEW FROM PIN 16 0 - 8° 9° (0.025 MIN.) 0.64 VIEW FROM PIN 1 (0.138 ± 0.005) 3.51 ± 0.13 (0.0091 – 0.0125) 0.23 – 0.32 (0.408 ± 0.008) 10.36 ± 0.20 ALL LEADS TO BE COPLANAR ± (0.002 INCHES) 0.05 mm. (0.018) (0.050) 0.457 1.27 (0.406 ± 0.007) 10.31 ± 0.18 4 DIMENSIONS IN (INCHES) AND MILLIMETERS. NOTE: FLOATING LEAD PROTRUSION IS 0.25 mm (10 mils) MAX. Recommended Pb-Free IR Profile Recommended reflow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used. Regulatory Information The HCPL-3150 and HCPL-315J have been approved by the following organizations: UL IEC/EN/DIN EN 60747-5-2 Recognized under UL 1577, Component Recognition Program, File E55361. Approved under: IEC 60747-5-5:1997 + A1:2002 EN 60747-5-2:2001 + A1:2002 DIN EN 60747-5-2 (VDE 0884 Teil 2):2003-01. (Option 060 and HCPL-315J only) CSA Approved under CSA Component Acceptance Notice #5, File CA 88324. IEC/EN/DIN EN 60747-5-2 Insulation Characteristics Description Symbol Installation classification per DIN VDE 0110/1.89, Table 1 for rated mains voltage ≤ 150 Vrms for rated mains voltage ≤ 300 Vrms for rated mains voltage ≤ 600 Vrms for rated mains voltage ≤ 1000Vrms Climatic Classification 55/100/21 Pollution Degree (DIN VDE 0110/1.89) Maximum Working Insulation Voltage Input to Output Test Voltage, Method b* VIORM x 1.875 = VPR, 100% Production Test with tm = 1 sec, Partial discharge < 5 pC Input to Output Test Voltage, Method a* VIORM x 1.6 = VPR, Type and Sample Test, tm = 10 sec, Partial discharge < 5 pC Highest Allowable Overvoltage* (Transient Overvoltage tini = 60 sec) Safety-Limiting Values – Maximum Values Allowed in the Event of a Failure, Also See Figure 37, Thermal Derating Curve. Case TemperatureTS Input Current Output Power Insulation Resistance at TS, VIO = 500 V HCPL-3150#060 HCPL-315J I - IV I - III I - II I - IV I - IV I - IV I-III Unit 55/100/21 2 2 VIORM 630 1230 Vpeak VPR 1181 2306 Vpeak VPR 945 1968 Vpeak VIOTM 6000 8000 Vpeak 175 IS, INPUT PS, OUTPUT 175 230 600 °C 400 1200 mA mW RS ≥ 109 ≥ 109 Ω *Refer to the front of the optocoupler section of the current Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description of Method a and Method b partial discharge test profiles. Note: Isolation characteristics are guaranteed only within the safety maximum ratings which must be ensured by protective circuits in application. 5 Insulation and Safety Related Specifications Parameter Symbol HCPL-3150 HCPL-315J Units Conditions Minimum External Air Gap (External Clearance) L(101) 7.1 8.3 mm Measured from input terminals to output terminals, shortest distance through air. Minimum External Tracking (External Creepage) L(102) 7.4 8.3 mm Measured from input terminals to output erminals, shortest distance path along body. 0.08 ≥0.5 mm Through insulation distance conductor to conductor. ≥175 ≥175 Volts DIN IEC 112/VDE 0303 Part 1 IIIa IIIa Minimum Internal Plastic Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) CTI Isolation Group Material Group (DIN VDE 0110, 1/89, Table 1) Option 300 - surface mount classification is Class A in accordance wtih CECC 00802. Absolute Maximum Ratings Parameter Symbol Min. Max. Units Storage Temperature TS -55 125 °C Operating Temperature TA -40 100 °C Average Input Current IF(AVG) 25 mA Peak Transient Input Current (<1 μs pulse width, 300 pps) IF(TRAN) 1.0 A VR 5 Volts IOH(PEAK) 0.6 A 2, 16 2, 16 Reverse Input Voltage “High” Peak Output Current 1, 16 0.6 A Supply Voltage (VCC - VEE) 0 35 Volts Output Voltage VO(PEAK) 0 VCC Volts PO 250 mW 3, 16 PT 295 mW 4, 16 “Low” Peak Output Current IOL(PEAK) Output Power Dissipation Total Power Dissipation Lead Solder Temperature 260°C for 10 sec., 1.6 mm below seating plane Solder Reflow Temperature Profile See Package Outline Drawings Section Recommended Operating Conditions Parameter Power Supply Voltage Symbol Min. Max. Units (VCC - VEE) 15 30 Volts Input Current (ON) IF(ON) 7 16 mA Input Voltage (OFF) VF(OFF) -3.6 0.8 V TA -40 100 °C Operating Temperature 6 Note Electrical Specifications (DC) Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground, each channel) unless otherwise specified. Parameter Symbol Min. Typ.* High Level Output Current IOH 0.1 0.4 Low Level Output Current IOL Max. Units A 0.5 0.1 0.6 A 0.5 High Level Output VOH (VCC - 4) (VCC - 3) V Test Conditions Fig. VO = (VCC - 4 V) 2, 3, 17 2 VO = (VEE + 2.5 V) 5, 6, 5 VO = (VEE + 15 V) 18 2 IO = -100 mA 1, 3, 19 0.4 VOL 1.0 V IO = 100 mA 4, 6, Voltage High Level 20 2.5 ICCH 5.0 mA ICCL 2.7 5.0 mA IFLH Current Low to High Threshold Input 16 Output Open, VF = -3.0 to +0.8 V Supply Current Threshold Input Output Open, 7, 8 IF = 7 to 16 mA Supply Current Low Level 5 VO = (VCC - 15 V) Voltage Low Level Output VFHL 0.8 VF 1.2 2.2 5.0 2.6 6.4 mA HCPL-3150 IO = 0 mA, 9, 15, HCPL-315J VO > 5 V 21 HCPL-3150 IF = 10 mA 16 V Voltage High to Low Input Forward Voltage Temperature ΔVF/ΔTA 1.5 1.8 1.6 1.95 -1.6 V HCPL-315J mV/°C IF = 10 mA Coefficient of Forward Voltage Input Reverse BVR Breakdown Voltage Input Capacitance UVLO Threshold UVLO Hysteresis 5 V 3 CIN 70 VUVLO+ 11.0 12.3 13.5 VUVLO- 9.5 10.7 12.0 UVLOHYS 1.6 *All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted. 7 HCPL-3150 IR = 10 μA HCPL-315J IR = 10 μA pF f = 1 MHz, VF = 0 V V VO > 5 V, 22, IF = 10 mA 36 V Note 6, 7 Switching Specifications (AC) Over recommended operating conditions (TA = -40 to 100°C, IF(ON) = 7 to 16 mA, VF(OFF) = -3.6 to 0.8 V, VCC = 15 to 30 V, VEE = Ground, each channel) unless otherwise specified. Parameter Fig. Note Rg = 47 Ω, 10, 11, 14 Time to High Cg = 3 nF, 12, 13, Output Level f = 10 kHz, 14, 23 Propagation Delay Symbol Min. Typ.* Max. Units tPLH 0.10 0.30 0.50 μs Test Conditions Duty Cycle = 50% Propagation Delay tPHL 0.10 0.3 0.50 μs 0.3 μs 0.35 μs 34, 36 23 Time to Low Output Level Pulse Width PWD 15 Distortion Propagation Delay PDD Difference Between (tPHL - tPLH) -0.35 10 Any Two Parts or Channels Rise Time tr 0.1 μs Fall Time tf 0.1 μs tUVLO ON 0.8 μs UVLO Turn On Delay UVLO Turn Off tUVLO OFF 0.6 μs |CMH| 15 30 kV/μs TA = 25°C, 24 11, 12 IF = 10 to 16 mA, Transient VCM = 1500 V, Immunity VCC = 30 V Output Low Level 8 VO < 5 V, IF = 10 mA Common Mode Common Mode 22 IF = 10 mA Delay Output High Level VO > 5 V, |CML| 15 30 kV/μs TA = 25°C, VCM = 1500 V, Transient VF = 0 V, Immunity VCC = 30 V 11, 13 Package Characteristics (each channel, unless otherwise specified) Parameter Symbol Device Min. Input-Output Momentary Withstand Voltage** VISO HCPL-3150 3750 HCPL-315J 5000 Output-Output Momentary Withstand Voltage** VO-O HCPL-315J 1500 Resistance (Input - Output) RI-O Typ.* Max. Units Test Conditions Vrms RH < 50%, t = 1 min., TA = 25°C 8, 9 Vrms RH < 50% t = 1 min., TA = 25°C 17 9 1012 Ω VI-O = 500 VDC f = 1 MHz CapacitanceCI-O (Input - Output) HCPL-3150 HCPL-315J 0.6 1.3 pF LED-to-CaseTLC Thermal Resistance HCPL-3150 391 °C/W LED-to-Detector Thermal Resistance TLD HCPL-3150 439 °C/W Detector-to-Case Thermal Resistance TDC HCPL-3150 119 °C/W Thermocouple located at center underside of package Fig. 28 Note 18 *All typical values at TA = 25°C and VCC - VEE = 30 V, unless otherwise noted. **The Input-Output/Output-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output/output-output continuous voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled “Optocoupler Input-Output Endurance Voltage.” Notes: 1. Derate linearly above 70°C free-air temperature at a rate of 0.3 mA/°C. 2. Maximum pulse width = 10 μs, maximum duty cycle = 0.2%. This value is intended to allow for component tolerances for designs with IO peak minimum = 0.5 A. See Applications section for additional details on limiting IOH peak. 3. Derate linearly above 70°C free-air temperature at a rate of 4.8 mW/°C. 4. Derate linearly above 70°C free-air temperature at a rate of 5.4 mW/°C. The maximum LED junction temperature should not exceed 125°C. 5. Maximum pulse width = 50 μs, maximum duty cycle = 0.5%. 6. In this test VOH is measured with a dc load current. When driving capacitive loads VOH will approach VCC as IOH approaches zero amps. 7. Maximum pulse width = 1 ms, maximum duty cycle = 20%. 8. In accordance with UL1577, each HCPL-3150 optocoupler is proof tested by applying an insulation test voltage ≥4500 Vrms (≥ 6000 Vrms for the HCPL-315J) for 1 second. This test is performed before the 100% production test for partial discharge (method b) shown in the IEC/EN/ DIN EN 60747-5-2 Insulation Characteristics Table, if applicable. 9. Device considered a two-terminal device: pins on input side shorted together and pins on output side shorted together. 10. The difference between tPHL and tPLH between any two parts or channels under the same test condition. 11. Pins 1 and 4 (HCPL-3150) and pins 3 and 4 (HCPL-315J) need to be connected to LED common. 12. Common mode transient immunity in the high state is the maximum tolerable |dVCM /dt| of the common mode pulse, VCM, to assure that the output will remain in the high state (i.e., VO > 15.0 V). 13. Common mode transient immunity in a low state is the maximum tolerable |dVCM/dt| of the common mode pulse, VCM, to assure that the output will remain in a low state (i.e., VO < 1.0 V). 14. This load condition approximates the gate load of a 1200 V/25 A IGBT. 15. Pulse Width Distortion (PWD) is defined as |tPHL-tPLH| for any given device. 16. Each channel. 17. Device considered a two terminal device: Channel one output side pins shorted together, and channel two output side pins shorted together. 18. See the thermal model for the HCPL-315J in the application section of this data sheet. 9 -3 -4 -40 -20 0 20 40 60 80 100 0.40 0.35 0.30 0.25 -40 -20 TA – TEMPERATURE – °C 100 0.2 0 -40 -20 0 20 40 60 80 100 0.8 0.6 0.4 VF(OFF) = -3.0 to 0.8 V VOUT = 2.5 V VCC = 15 to 30 V VEE = 0 V 0.2 0 -40 -20 0 20 40 60 80 100 ICC – SUPPLY CURRENT – mA 3.0 2.5 VCC = 30 V VEE = 0 V IF = 10 mA for ICCH IF = 0 mA for ICCL ICCH ICCL 3.0 2.5 40 60 80 TA – TEMPERATURE – °C Figure 7. ICC vs. Temperature. 100 IF = 10 mA for ICCH IF = 0 mA for ICCL TA = 25 °C VEE = 0 V 2.0 1.5 20 IF = 7 to 16 mA VCC = 15 to 30 V VEE = 0 V -5 -6 0 0.2 0.4 1.0 0.8 0.6 IOH – OUTPUT HIGH CURRENT – A VF(OFF) = -3.0 to 0.8 V VCC = 15 to 30 V 4 VEE = 0 V 3 2 1 0 15 20 25 VCC – SUPPLY VOLTAGE – V Figure 8. ICC vs. VCC. 100 °C 25 °C -40 °C 0 0.2 0.4 1.0 0.8 0.6 Figure 6. VOL vs. IOL. 3.5 0 -4 IOL – OUTPUT LOW CURRENT – A Figure 5. IOL vs. Temperature. ICCH ICCL 1.5 -40 -20 -3 TA – TEMPERATURE – °C 3.5 100 °C 25 °C -40 °C -2 Figure 3. VOH vs. IOH. VOL – OUTPUT LOW VOLTAGE – V IOL – OUTPUT LOW CURRENT – A 0.4 Figure 4. VOL vs. Temperature. ICC – SUPPLY CURRENT – mA 80 -1 5 TA – TEMPERATURE – °C 10 60 40 1.0 VF(OFF) = -3.0 to 0.8 V IOUT = 100 mA VCC = 15 to 30 V VEE = 0 V 0.6 2.0 20 Figure 2. IOH vs. Temperature. 1.0 0.8 0 TA – TEMPERATURE – °C Figure 1. VOH vs. Temperature. VOL – OUTPUT LOW VOLTAGE – V 0.45 (VOH - VCC ) – OUTPUT HIGH VOLTAGE DROP – V -2 IF = 7 to 16 mA VOUT = VCC - 4 V VCC = 15 to 30 V VEE = 0 V 30 IFLH – LOW TO HIGH CURRENT THRESHOLD – mA -1 0.50 IF = 7 to 16 mA IOUT = -100 mA VCC = 15 to 30 V VEE = 0 V IOH – OUTPUT HIGH CURRENT – A (VOH - VCC ) – HIGH OUTPUT VOLTAGE DROP – V 0 5 VCC = 15 TO 30 V VEE = 0 V OUTPUT = OPEN 4 3 2 1 0 -40 -20 0 20 40 60 80 TA – TEMPERATURE – °C Figure 9. IFLH vs. Temperature. 100 TPLH TPHL 300 200 15 400 300 200 TPLH TPHL 100 30 25 20 VCC – SUPPLY VOLTAGE – V 12 14 300 200 TPLH TPHL 0 50 150 100 200 Figure 13. Propagation Delay vs. Rg. 1000 10 IF + VF – 1.0 0.1 0.01 0.001 1.10 1.20 1.30 1.40 1.50 300 200 TPLH TPHL 1.60 VF – FORWARD VOLTAGE – V Figure 16. Input Current vs. Forward Voltage. 20 40 60 80 100 30 400 300 200 TPLH TPHL 100 0 TA – TEMPERATURE – °C Figure 12. Propagation Delay vs. Temperature. VCC = 30 V, VEE = 0 V TA = 25 °C IF = 10 mA Rg = 47 Ω DUTY CYCLE = 50% f = 10 kHz 0 20 40 60 80 Cg – LOAD CAPACITANCE – nF Figure 14. Propagation Delay vs. Cg. TA = 25°C 100 400 100 -40 -20 16 VO – OUTPUT VOLTAGE – V 400 Tp – PROPAGATION DELAY – ns Tp – PROPAGATION DELAY – ns 10 500 VCC = 30 V, VEE = 0 V TA = 25 °C IF = 10 mA Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz Rg – SERIES LOAD RESISTANCE – Ω IF – FORWARD CURRENT – mA 8 Figure 11. Propagation Delay vs. IF. 500 11 6 IF(ON) = 10 mA IF(OFF) = 0 mA VCC = 30 V, VEE = 0 V Rg = 47 Ω, Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz IF – FORWARD LED CURRENT – mA Figure 10. Propagation Delay vs. VCC. 100 VCC = 30 V, VEE = 0 V Rg = 47 Ω, Cg = 3 nF TA = 25 °C DUTY CYCLE = 50% f = 10 kHz Tp – PROPAGATION DELAY – ns 400 100 500 500 IF = 10 mA TA = 25 °C Rg = 47 Ω Cg = 3 nF DUTY CYCLE = 50% f = 10 kHz Tp – PROPAGATION DELAY – ns Tp – PROPAGATION DELAY – ns 500 100 25 20 15 10 5 0 0 1 2 3 4 5 IF – FORWARD LED CURRENT – mA Figure 15. Transfer Characteristics. 1 1 8 8 0.1 μF 0.1 μF 2 + – 7 4V IF = 7 to 16 mA 2 7 3 6 4 5 + VCC = 15 – to 30 V + VCC = 15 – to 30 V 3 6 IOL 2.5 V + – IOH 4 5 Figure 17. IOH Test Circuit. Figure 18. IOL Test Circuit. 1 1 8 8 0.1 μF 0.1 μF 2 7 VOH IF = 7 to 16 mA 2 100 mA 7 + VCC = 15 – to 30 V + VCC = 15 – to 30 V 3 6 3 6 4 5 VOL 100 mA 4 5 Figure 19. VOH Test Circuit. 1 Figure 20. VOL Test Circuit. 8 1 8 2 7 3 6 4 5 0.1 μF 0.1 μF 2 7 IF VO > 5 V 3 6 4 5 Figure 21. IFLH Test Circuit. 12 + VCC = 15 – to 30 V IF = 10 mA VO > 5 V Figure 22. UVLO Test Circuit. + – VCC 1 8 0.1 μF IF = 7 to 16 mA + 10 KHz – 500 Ω 2 + – 7 IF VCC = 15 to 30 V tr tf VO 50% DUTY CYCLE 3 90% 47 Ω 6 50% VOUT 3 nF 4 10% 5 tPLH tPHL Figure 23. tPLH, tPHL, tr, and tf Test Circuit and Waveforms. VCM 1 5V δt 0.1 μF A B δV 8 IF 2 VO 6 4 5 VCM Δt 0V 7 + – 3 = Δt + – VCC = 30 V VOH VO SWITCH AT A: IF = 10 mA VO VOL + – SWITCH AT B: IF = 0 mA VCM = 1500 V Figure 24. CMR Test Circuit and Waveforms. Applications Information Eliminating Negative IGBT Gate Drive in many applications as shown in Figure 25. Care should be taken with such a PC board design to avoid routing the IGBT collector or emitter traces close to the HCPL3150/315J input as this can result in unwanted coupling of transient signals into the HCPL-3150/315J and degrade performance. (If the IGBT drain must be routed near the HCPL-3150/315J input, then the LED should be reverse-biased when in the off state, to prevent the transient signals coupled from the IGBT drain from turning on the HCPL-3150/315J.) To keep the IGBT firmly off, the HCPL-3150/315J has a very low maximum VOL specification of 1.0 V. The HCPL3150/315J realizes this very low VOL by using a DMOS transistor with 4 Ω (typical) on resistance in its pull down circuit. When the HCPL-3150/315J is in the low state, the IGBT gate is shorted to the emitter by Rg + 4 Ω. Minimizing Rg and the lead inductance from the HCPL-3150/315J to the IGBT gate and emitter (possibly by mounting the HCPL-3150/315J on a small PC board directly above the IGBT) can eliminate the need for negative IGBT gate drive HCPL-3150 +5 V 1 270 Ω 8 0.1 μF 2 + – VCC = 18 V + HVDC 7 Rg CONTROL INPUT 74XXX OPEN COLLECTOR 3 6 4 5 Figure 25a. Recommended LED Drive and Application Circuit. 13 Q1 3-PHASE AC Q2 - HVDC HCPL-315J +5 V 270 Ω CONTROL INPUT 1 16 2 15 0.1 μF + – FLOATING SUPPLY VCC = 18 V + HVDC Rg 74XX OPEN COLLECTOR 3 14 GND 1 +5 V 3-PHASE AC 6 270 Ω CONTROL INPUT 11 0.1 μF 7 VCC = 18 V + – 10 Rg 74XX OPEN COLLECTOR 8 9 GND 1 - HVDC Figure 25b. Recommended LED Drive and Application Circuit (HCPL-315J) Selecting the Gate Resistor (Rg) to Minimize IGBT Switching Losses. Step 1: Calculate Rg Minimum From the IOL Peak Specification. The IGBT and Rg in Figure 26 can be analyzed as a simple RC circuit with a voltage supplied by the HCPL-3150/315J. (V – V - V ) Rg ≥ CC EE OL IOLPEAK = = Step 2: Check the HCPL-3150/315J Power Dissipation and Increase Rg if Necessary. The HCPL-3150/315J total power dissipation (PT ) is equal to the sum of the emitter power (PE) and the output power (PO): PT = PE + PO PE = IF x VF x Duty Cycle (VCC – VEE - 1.7 V) IOLPEAK PO = PO(BIAS) + PO (SWITCHING) (15 V + 5 V - 1.7 V) 0.6 A For the circuit in Figure 26 with IF (worst case) = 16 mA, Rg = 30.5 Ω, Max Duty Cycle = 80%, Qg = 500 nC, f = 20 kHz and TAmax = 90°C: = 30.5 Ω The VOL value of 2 V in the previous equation is a conservative value of VOL at the peak current of 0.6 A (see Figure 6). At lower Rg values the voltage supplied by the HCPL-3150/315J is not an ideal voltage step. This results in lower peak currents (more margin) than predicted by this analysis. When negative gate drive is not used VEE in the previous equation is equal to zero volts. = ICCx(VCC - VEE) + ESW(RG, QG) xf PE = 16 mA x 1.8 V x 0.8 = 23 mW PO = 4.25 mA x 20 V + 4.0 μJx20 kHz = 85 mW + 80 mW = 165 mW > 154 mW (PO(MAX) @ 90°C = 250 mW20Cx 4.8 mW/C) 14 HCPL-3150 +5 V 1 8 270 Ω 0.1 μF 2 + – VCC = 15 V + HVDC 7 Rg Q1 CONTROL INPUT 3 6 – + 74XXX OPEN COLLECTOR 4 3-PHASE AC VEE = -5 V 5 Q2 - HVDC Figure 26a. HCPL-3150 Typical Application Circuit with Negative IGBT Gate Drive. HCPL-315J +5 V 1 270 Ω CONTROL INPUT 16 0.1 μF 2 + – + HVDC FLOATING SUPPLY VCC = 15 V 15 Rg 74XX OPEN COLLECTOR 3 14 – + VEE = -5 V GND 1 +5 V 6 270 Ω CONTROL INPUT 11 0.1 μF 7 3-PHASE AC VCC = 15 V + – 10 Rg 74XX OPEN COLLECTOR 8 9 – + VCC = -5 V GND 1 - HVDC Figure 26b. HCPL-315J Typical Application Circuit with Negative IGBT Gate Drive. PE Parameter Description IF LED Current VF LED On Voltage VCC VEE Duty Cycle Maximum LED Duty Cycle ESW(Rg,Qg) PO Parameter ICC f 15 Description Supply Current Positive Supply Voltage Negative Supply Voltage Energy Dissipated in the HCPL-3150/315J for each IGBT Switching Cycle (See Figure 27) Switching Frequency The value of 4.25 mA for ICC in the previous equation was obtained by derating the ICC max of 5 mA (which occurs at -40°C) to ICC max at 90°C (see Figure 7). Since PO for this case is greater than PO(MAX), Rg must be increased to reduce the HCPL-3150 power dissipation. PO(SWITCHING MAX) = PO(MAX) - PO(BIAS) = 69 mW 20 kHz LD θLD = 439°C/W TJD θDC = 119°C/W TC θCA = 83°C/W* For example, given PE = 45 mW, PO = 250 mW, TA = 70°C and TCA = 83°C/W: TJE = PEx 313°C/W + PDx 132°C/W + TA The steady state thermal model for the HCPL-3150 is shown in Figure 28a. The thermal resistance values given in this model can be used to calculate the temperatures at each node for a given operating condition. As shown by the model, all heat generated flows through TCA which raises the case temperature TC accordingly. The value of TCA depends on the conditions of the board design and is, therefore, determined by the designer. The value of TCA = 83°C/W was obtained from thermal measurements using a 2.5 x 2.5 inch PC board, with small traces (no ground plane), a single HCPL-3150 soldered into the center of the board and still air. The absolute maximum power dissipation derating specifications assume a TCAvalue of 83°C/W. 16 + TCA DC DC TJD = PE x (49°C/W + TCA) + PDx (104°C/W + TCA) + TA Thermal Model (HCPL-3150) Figure 28a. Thermal Model. ) x LC TJE = PE x (230°C/W + TCA) + PDx (49°C/W + TCA) + TA = 3.45 μJ For Qg = 500 nC, from Figure 27, a value of ESW = 3.45 μJ gives a Rg = 41 Ω. TA ( T T+ T T + T Inserting the values for TLC and TDC shown in Figure 28 gives: f θLC = 391°C/W ) + PDx (TDC||(TLD + TLC) + TCA) + TA PO(SWITCHINGMAX) TJE ( LC = 69 mW = TJE = PE x (TLC||(TLD + TDC) + TCA) TLC x TDC + PD x + TCA + TA TLC + TDC + TLD TJD = PE = 154 mW - 85 mW ESW(MAX) From the thermal mode in Figure 28a the LED and detector IC junction temperatures can be expressed as: = 45 mWx 313°C/W + 250 mW x 132°C/W + 70°C = 117°C TJD = PEx 132°C/W + PDx 187°C/W + TA = 45 mWx 132C/W + 250 mW x 187°C/W + 70°C = 123°C TJE and TJD should be limited to 125°C based on the board layout and part placement (TCA) specific to the application. TJE = LED junction temperature TJD = detector IC junction temperature TC = case temperature measured at the center of the package bottom TLC = LED-to-case thermal resistance TLD = LED-to-detector thermal resistance TDC = detector-to-case thermal resistance TCA = case-to-ambient thermal resistance TCA will depend on the board design and the placement of the part. Thermal Model Dual-Channel (SOIC-16) HCPL-315J Optoisolator LED 2 θ3 θ2 Definitions T1, T2, T3, T4, T5, T6, T7, T8, T9, T10: Thermal impedances between nodes as shown in Figure 28b. Ambient Temperature: Measured approximately 1.25 cm above the optocoupler with no forced air. θ4 θ5 DETECTOR 1 θ7 Description This thermal model assumes that a 16-pin dual-channel (SOIC-16) optocoupler is soldered into an 8.5 cm x 8.1 cm printed circuit board (PCB). These optocouplers are hybrid devices with four die: two LEDs and two detectors. The temperature at the LED and the detector of the optocoupler can be calculated by using the equations below. 'TE1A = A11PE1 + A12PE2+A13PD1+A14PD2 θ1 LED 1 DETECTOR 2 θ10 θ8 θ6 θ9 AMBIENT Figure 28b. Thermal Impedance Model for HCPL-315J. 'TE2A = A21PE1 + A22PE2+A23PD1+A24PD2 'TD1A = A31PE1 + A32PE2+A33PD1+A34PD2 'TD2A = A41PE1 + A42PE2+A43PD1+A44PD2 where: 'TE1A = Temperature difference between ambient and LED 1 'TE2A = Temperature difference between ambient and LED 2 'TD1A = Temperature difference between ambient and detector 1 'TD2A = Temperature difference between ambient and detector 2 PE1 = Power dissipation from LED 1; PE2 = Power dissipation from LED 2; PD1 = Power dissipation from detector 1; PD2 = Power dissipation from detector 2 Axy thermal coefficient (units in °C/W) is a function of thermal impedances T1 through T10. PE1 PD1 PE2 PD2 Thermal Coefficient Data (units in °C/W) Part Number A11, A22 A12, A21 A13, A31 A24, A42 A14, A41 A23, A32 A33, A44 A34, A43 HCPL-315J 198 64 62 64 83 90 137 69 Note: Maximum junction temperature for above part: 125°C. 17 LED Drive Circuit Considerations for Ultra High CMR Performance Without a detector shield, the dominant cause of optocoupler CMR failure is capacitive coupling from the input side of the optocoupler, through the package, to the detector IC as shown in Figure 29. The HCPL-3150/315J improves CMR performance by using a detector IC with an optically transparent Faraday shield, which diverts the capacitively coupled current away from the sensitive IC circuitry. How ever, this shield does not eliminate the capacitive coupling between the LED and optocoupler pins 5-8 as shown in Figure 30. This capacitive coupling causes perturbations in the LED current during common mode transients and becomes the major source of CMR failures for a shielded optocoupler. The main design objective of a high CMR LED drive circuit becomes keeping the LED in the proper state (on or off ) during common mode transients. For example, the recommended application circuit (Figure 25), can achieve 15 kV/μs CMR while minimizing component complexity. Techniques to keep the LED in the proper state are discussed in the next two sections. CMR with the LED On (CMRH) Esw – ENERGY PER SWITCHING CYCLE – μJ A high CMR LED drive circuit must keep the LED on during common mode transients. This is achieved by overdriving the LED current beyond the input threshold so that it is not pulled below the threshold during a transient. A minimum LED current of 10 mA provides adequate margin over the maximum IFLH of 5 mA to achieve 15 kV/μs CMR. 7 Qg = 100 nC Qg = 250 nC Qg = 500 nC 6 5 VCC = 19 V VEE = -9 V 4 3 2 1 0 0 20 40 60 80 100 Rg – GATE RESISTANCE – Ω Figure 27. Energy Dissipated in the HCPL-3150 for Each IGBT Switching Cycle. 18 CMR with the LED Off (CMRL) A high CMR LED drive circuit must keep the LED off (VF ≤ VF(OFF)) during common mode transients. For example, during a -dVCM/dt transient in Figure 31, the current flowing through CLEDP also flows through the RSAT and VSAT of the logic gate. As long as the low state voltage developed across the logic gate is less than VF(OFF), the LED will remain off and no common mode failure will occur. The open collector drive circuit, shown in Figure 32, cannot keep the LED off during a +dVCM/dt transient, since all the current flowing through CLEDN must be supplied by the LED, and it is not recommended for applications requiring ultra high CMRL performance. Figure 33 is an alternative drive circuit which, like the recommended application circuit (Figure 25), does achieve ultra high CMR performance by shunting the LED in the off state. Under Voltage Lockout Feature The HCPL-3150/315J contains an under voltage lockout (UVLO) feature that is designed to protect the IGBT under fault conditions which cause the HCPL-3150/315J supply voltage (equivalent to the fully-charged IGBT gate voltage) to drop below a level necessary to keep the IGBT in a low resistance state. When the HCPL-3150/315J output is in the high state and the supply voltage drops below the HCPL-3150/315J VUVLO- threshold (9.5 <VUVLO- <12.0), the optocoupler output will go into the low state with a typical delay, UVLO Turn Off Delay, of 0.6 μs. When the HCPL-3150/315J output is in the low state and the supply voltage rises above the HCPL-3150/315J VUVLO+ threshold (11.0 < VUVLO+ < 13.5), the optocoupler will go into the high state (assuming LED is “ON”) with a typical delay, UVLO TURN On Delay, of 0.8 μs. IPM Dead Time and Propagation Delay Specifications The HCPL-3150/315J includes a Propagation Delay Difference (PDD) specification intended to help designers minimize “dead time” in their power inverter designs. Dead time is the time period during which both the high and low side power transistors (Q1 and Q2 in Figure 25) are off. Any overlap in Q1 and Q2 conduction will result in large currents flowing through the power devices from the high- to the low-voltage motor rails. To minimize dead time in a given design, the turn on of LED2 should be delayed (relative to the turn off of LED1) so that under worst-case conditions, transistor Q1 has just turned off when transistor Q2 turns on, as shown in Figure 34. The amount of delay necessary to achieve this conditions is equal to the maximum value of the propagation delay difference specification, PDDMAX, which is specified to be 350 ns over the operating temperature range of -40°C to 100°C. 1 Delaying the LED signal by the maximum propagation delay difference ensures that the minimum dead time is zero, but it does not tell a designer what the maximum dead time will be. The maximum dead time is equivalent to the difference between the maximum and minimum propagation delay difference specifications as shown in Figure 35. The maximum dead time for the HCPL-3150/315J is 700 ns (= 350 ns - (-350 ns)) over an operating temperature range of -40°C to 100°C. Note that the propagation delays used to calculate PDD and dead time are taken at equal temperatures and test conditions since the optocouplers under consideration are typically mounted in close proximity to each other and are switching identical IGBTs. 8 1 2 7 2 3 6 3 5 4 CLEDO1 CLEDP 8 CLEDP 7 CLEDO2 CLEDN 4 Figure 29. Optocoupler Input to Output Capacitance Model for Unshielded Optocouplers. +5 V 1 7 + – VCC = 18 V ILEDP 4 ••• 6 CLEDN Rg SHIELD 6 5 Figure 30. Optocoupler Input to Output Capacitance Model for Shielded Optocouplers. 0.1 μF 2 3 5 * THE ARROWS INDICATE THE DIRECTION OF CURRENT FLOW DURING –dVCM/dt. + – VCM Figure 31. Equivalent Circuit for Figure 25 During Common Mode Transient. 19 SHIELD 8 CLEDP + VSAT – CLEDN ••• 1 1 8 8 +5 V +5 V CLEDP CLEDP 2 3 Q1 CLEDN 7 2 6 3 5 4 7 6 CLEDN ILEDN 4 SHIELD Figure 32. Not Recommended Open Collector Drive Circuit. ILED1 VOUT1 5 SHIELD Figure 33. Recommended LED Drive Circuit for Ultra-High CMR. ILED1 VOUT1 Q1 ON Q1 ON Q1 OFF Q1 OFF Q2 ON Q2 ON VOUT2 ILED2 Q2 OFF VOUT2 Q2 OFF ILED2 tPHL MAX tPHL MIN tPLH MIN tPHL MAX tPLH PDD* MAX = (tPHL- tPLH)MAX = tPHL MAX - tPLH MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR PDD CALCULATIONS THE PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 34. Minimum LED Skew for Zero Dead Time. MIN tPLH MAX (tPHL-tPLH) MAX = PDD* MAX MAXIMUM DEAD TIME (DUE TO OPTOCOUPLER) = (tPHL MAX - tPHL MIN) + (tPLH MAX - tPLH MIN) = (tPHL MAX - tPLH MIN) – (tPHL MIN - tPLH MAX) = PDD* MAX – PDD* MIN *PDD = PROPAGATION DELAY DIFFERENCE NOTE: FOR DEAD TIME AND PDD CALCULATIONS ALL PROPAGATION DELAYS ARE TAKEN AT THE SAME TEMPERATURE AND TEST CONDITIONS. Figure 35. Waveforms for Dead Time. 20 12 (12.3, 10.8) 10 (10.7, 9.2) 8 6 4 2 0 (10.7, 0.1) 5 0 10 (12.3, 0.1) 15 20 (VCC - VEE ) – SUPPLY VOLTAGE – V Figure 36. Under Voltage Lock Out. OUTPUT POWER – PS, INPUT CURRENT – IS VO – OUTPUT VOLTAGE – V 14 800 PS (mW) IS (mA) 700 600 500 400 300 200 100 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C Figure 37a. HCPL-3150: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN 60747-5-2. 1400 PSI OUTPUT PSI – POWER – mW 1200 PSI INPUT 1000 800 600 400 200 0 0 25 50 75 100 125 150 175 200 TS – CASE TEMPERATURE – °C Figure 37b. HCPL-315J: Thermal Derating Curve, Dependence of Safety Limiting Value with Case Temperature per IEC/EN/DIN EN 60747-5-2. For product information and a complete list of distributors, please go to our website: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2011 Avago Technologies. All rights reserved. Obsoletes 5989-2944EN AV02-0164EN - March 28, 2011