LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 LMH6554 2.8 GHz Ultra Linear Fully Differential Amplifier Check for Samples: LMH6554 FEATURES DESCRIPTION • • • • • • • • • • • The LMH6554 is a high performance fully differential amplifier designed to provide the exceptional signal fidelity and wide large-signal bandwidth necessary for driving 8 to 16 bit high speed data acquisition systems. Using TI’s proprietary differential current mode input stage architecture, the LMH6554 has unity gain, small-signal bandwidth of 2.8 GHz and allows operation at gains greater than unity without sacrificing response flatness, bandwidth, harmonic distortion, or output noise performance. 1 2 Small Signal Bandwidth 2.8 GHz 2 VPP Large Signal Bandwidth 1.8 GHz 0.1 dB Gain Flatness 830 MHz OIP3 @ 150 MHz 46.5 dBm HD2/HD3 @ 75 MHz -96 / -97 dBc Input Noise Voltage 0.9 nV/√Hz Input Noise Current 11 pA/√Hz Slew Rate 6200 V/μs Power 260mW Typical Supply Current 52 mA Package 14 Lead UQFN The device's low impedance differential output is designed to drive ADC inputs and any intermediate filter stage. The LMH6554 delivers 16-bit linearity up to 75 MHz when driving 2V peak-to-peak into loads as low as 200Ω. APPLICATIONS • • • • • • • • • The LMH6554 is fabricated in Texas Instruments' advanced complementary BiCMOS process and is available in a space saving 14 lead UQFN package for higher performance. Differential ADC Driver Single-Ended to Differential Converter High Speed Differential Signaling IF/RF and Baseband Gain Blocks SAW Filter Buffer/Driver Oscilloscope Probes Automotive Safety Applications Video Over Twisted Pair Differential Line Driver Typical Application 200: 91: RS = 50: VS C a V 76.8: AC-Coupled Source 0.1 PF + 50: VCM + - 91: 30: 0.1 PF Up To 16-Bit Data Converter LMH6554 - + ADC 50: - VCMO V 0.1 PF 200: VEN Figure 1. Single to Differential ADC Driver 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (1) (2) (3) Human Body Model 2000V Machine Model 250V Charge Device Model 750V − Supply Voltage (VS = V - V ) 5.5V Common Mode Input Voltage From V-to V+ + Maximum Input Current 30mA (4) Maximum Output Current (pins 12, 13) Soldering Information Infrared or Convection (30 sec) 260°C For soldering specifications see SNOA549 (1) (2) (3) (4) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 30157. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC). Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). The maximum output current (IOUT) is determined by device power dissipation limitations. See the Power Dissipation section of Application Information for more details. Operating Ratings (1) Operating Temperature Range −40°C to +125°C Storage Temperature Range −65°C to +150°C Total Supply Voltage Temperature Range (1) 4.7V to 5.25V Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications, see the Electrical Characteristics tables. Thermal Properties Junction-to-Ambient Thermal Resistance (θJA) 60°C/W Maximum Operating Junction Temperature 2 150°C Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 +5V Electrical Characteristics (1) Unless otherwise specified, all limits are ensured for TA = +25°C, AV = +2, V+ = +2.5V, V− = −2.5V, RL = 200Ω, VCM = (V++V)/2, RF = 200Ω, for single-ended in, differential out. Boldface Limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units AC Performance (Differential) SSBW LSBW Small Signal −3 dB Bandwidth (2) Large Signal Bandwidth AV = 1, VOUT = 0.2 VPP 2800 AV = 2, VOUT = 0.2 VPP 2500 AV = 4, VOUT = 0.2 VPP 1600 AV = 1, VOUT = 2 VPP 1800 AV = 2, VOUT = 2 VPP 1500 AV = 2, VOUT = 1.5 VPP 1900 MHz MHz 0.1 dBBW 0.1 dB Bandwidth AV = 2, VOUT = 0.2 VPP, RF = 250Ω 830 MHz SR Slew Rate 4V Step 6200 V/μs 2V Step, 10–90% 290 0.4V Step, 10–90% 150 tr/tf Rise/Fall Time ps Ts_0.1 0.1% Settling Time 2V Step, RL = 200Ω 4 ns Overdrive Recovery Time VIN = 2V, AV = 5 V/V 6 ns Distortion and Noise Response HD2 HD3 2nd Harmonic Distortion rd 3 Harmonic Distortion VOUT = 2 VPP, f = 20 MHz -102 VOUT = 2 VPP, f = 75 MHz -96 VOUT = 2 VPP, f = 125 MHz -87 VOUT = 2 VPP, f = 250 MHz −79 VOUT = 1.5 VPP, f = 250 MHz −81 VOUT = 2 VPP, f = 20 MHz −110 VOUT = 2 VPP, f = 75 MHz −97 VOUT = 2 VPP, f = 125 MHz −87 VOUT = 2 VPP, f = 250 MHz −70 dBc dBc VOUT = 1.5 VPP, f = 250 MHz −75 OIP3 Output 3rd-Order Intercept f = 150 MHz, VOUT = 2VPP Composite 46.5 IMD3 Two-Tone Intermodulation f = 150 MHz, VOUT = 2VPP Composite −97 dBc en Input Voltage Noise Density f = 10 MHz 0.9 nV/√Hz in+ Input Noise Current f = 10 MHz 11 pA/√Hz in- Input Noise Current f = 10 MHz 11 pA/√Hz NF Noise Figure 50Ω System, AV = 7.3, 100 MHz 7.7 dB (4) dBm Input Characteristics −75 IBI+ / IBITCIbi Input Bias Current Temperature Drift IBID Input Bias Current TCIbo Input Bias Current Diff Offset Temperature Drift (3) CMRR Common Mode Rejection Ratio (1) (2) (3) (4) (5) (5) −29 20 8 VCM = 0V, VID = 0V, IBOFFSET = (IB-- IB+)/2 DC, VCM = 0V, VID = 0V −10 1 µA µA/°C μA 10 0.006 µA/°C 83 dB Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No specification of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. See Application Information for information on temperature de-rating of this device." Min/Max ratings are based on product characterization and simulation. Individual parameters are tested as noted. Limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. For test schematic, refer to Figure 35. IBI is referred to a differential output offset voltage by the following relationship: VOD(OFFSET) = IBI*2RF. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 3 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com +5V Electrical Characteristics (1) (continued) Unless otherwise specified, all limits are ensured for TA = +25°C, AV = +2, V+ = +2.5V, V− = −2.5V, RL = 200Ω, VCM = (V++V)/2, RF = 200Ω, for single-ended in, differential out. Boldface Limits apply at the temperature extremes. Symbol Parameter Conditions Min (2) Typ (3) Max (2) Units 19 Ω 1 pF ±1.3 V RIN Differential Input Resistance Differential CIN Differential Input Capacitance Differential CMVR Input Common Mode Voltage Range CMRR > 32 dB ±1.25 Single-Ended Output ±1.35 ±1.42 V VOUT = 0V ±120 Output Performance Output Voltage Swing IOUT Output Current ISC (3) (3) ±150 mA Short Circuit Current One Output Shorted to Ground VIN = 2V Single-Ended (6) 150 mA Output Balance Error ΔVOUT Common Mode /ΔVOUT Differential, ΔVOD = 1V, f < 1 Mhz −64 dB Common Mode Small Signal Bandwidth VIN+ = VIN− = 0V 500 MHz Slew Rate VIN = VIN = 0V Input Offset Voltage Common Mode, VID = 0, VCM = 0V Output Common Mode Control Circuit VOSCM IOSCM Input Offset Current 200 − + CMRR −6.5 4 mV 6 18 μA ±1.18 ±1.25 V 82 dB (7) Voltage Range Measure VOD, VID = 0V Input Resistance 180 ΔVOCM/ΔVCM Gain V/μs −16 0.99 0.995 kΩ 1.0 V/V Miscellaneous Performance ZT Open Loop Transimpedance Gain PSRR IS Power Supply Rejection Ratio Supply Current (8) Enable Voltage Threshold Disable Voltage Threshold Differential + 180 − DC, ΔV = ΔV = 1V RL = ∞ 74 46 (6) (7) (8) (9) 4 Supply Current, Disabled 95 52 dB 57 60 mA Single 5V Supply (9) 2.5 Single 5V Supply (9) 2.5 V 15 ns Enable/Disable Time ISD kΩ Enable=0, Single 5V supply 450 510 V 570 600 μA Short circuit current should be limited in duration to no more than 10 seconds. See the Power Dissipation section of Application Information for more details. Negative input current implies current flowing out of the device. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. VEN threshold is typically +/-0.3V centered around (V+ + V-) / 2 relative to ground. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 Connection Diagram V - 3 + VCM V 2 1 14 NC +FB 4 RF -IN 5 13 +OUT +IN 6 12 -OUT -FB 7 11 NC RG RG RF 8 V - 9 10 VEN V + Figure 2. 14 Lead UQFN - Top View See Package Number NHJ0014A Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 5 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VS = ±2.5V (TA = 25°C, RF = 200Ω, RG = 90Ω, RT = 76.8Ω, RL = 200Ω, AV = +2, for single ended in, differential out, unless specified). Frequency Response vs. RF 2 Frequency Response vs. Gain 2 RF = 200: 1 0 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) 0 -1 RF = 250: -2 -3 RF = 300: -4 -5 -6 -7 -1 -10 1 AV = 2 V/V -2 -3 AV = 4 V/V -4 -5 AV = 8 V/V -6 -7 -8 -9 AV = 1 V/V 1 -8 -9 VOD = 0.2 VPP 10 100 1000 -10 1 10000 VOD = 0.2 VPP 10 FREQUENCY (MHz) Frequency Response vs. RL Frequency Response vs. Output Voltage (VOD) 2 0 RL = 500: NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) VOD = 0.2 VPP 1 4 2 0 -2 RL = 200: -4 -6 -1 VOD = 1.6 VPP -2 -3 -4 VOD = 2 VPP -5 -6 -7 -8 -8 -9 VOD = 0.2 VPP 10 100 1000 -10 1 10000 10 FREQUENCY (MHz) 1000 Figure 5. Figure 6. Frequency Response vs. Capacitive Load Suggested ROUT vs. Capacitive Load 10000 70 LOAD = 1k: || CAP LOAD 2 CL=2.2 pF, RO=38: 1 60 0 -1 -2 CL=6.8 pF, RO=22: -3 -4 CL=18 pF, RO=14: SUGGESTED RO (:) NORMALIZED GAIN (dB) 100 FREQUENCY (MHz) 3 -5 CL=68 pF, RO=5: 50 40 30 20 -7 -8 10 -9 V = 200 mV OD PP -10 1 10 100 1000 10000 FREQUENCY (MHz) 0 5 10 15 20 25 30 35 40 CAPACITIVE LOAD (pF) Figure 7. 6 10000 Figure 4. RL = 1k: -6 1000 Figure 3. 6 -10 1 1100 FREQUENCY (MHz) Figure 8. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics VS = ±2.5V (continued) (TA = 25°C, RF = 200Ω, RG = 90Ω, RT = 76.8Ω, RL = 200Ω, AV = +2, for single ended in, differential out, unless specified). 2 VPP Pulse Response Single Ended Input 0.3 1.5 0.2 1.0 0.1 0.5 VOD (V) VOD (V) 0.5 VPP Pulse Response Single Ended Input 0 0 -0.1 -0.5 -0.2 -1.0 -0.3 0 1 2 3 4 5 6 7 8 9 -1.5 0 10 1 2 3 4 TIME (ns) 7 8 9 10 Figure 10. 4 VPP Pulse Response Single Ended Input Distortion vs. Frequency Single Ended Input 2.5 -60 2.0 -65 1.5 -70 DISTORTION (dBc) VOD (V) 6 Figure 9. 1.0 0.5 0 -0.5 -1.0 -80 -90 -105 3 4 5 6 7 8 9 -110 25 10 HD3 -95 -100 2 HD2 -85 -2.0 1 RL = 200: VOD = 2 VPP VOCM = 0V -75 -1.5 -2.5 0 75 TIME (ns) 175 225 275 300 Figure 11. Figure 12. Distortion vs. Output Common Mode Voltage Distortion vs. Output Common Mode Voltage -40 RL = 200: VOD = 2 VPP fc = 25 MHz RL = 200: VOD = 2 VPP fc = 75 MHz -50 DISTORTION (dBc) -60 -70 HD3 -80 -90 HD2 -100 -110 -1.0 125 FREQUENCY (MHz) -50 DISTORTION (dBc) 5 TIME (ns) -60 -70 HD3 -80 HD2 -90 -0.5 0 0.5 1.0 -100 -1.0 VOCM (V) -0.5 0 0.5 1.0 VOCM (V) Figure 13. Figure 14. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 7 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VS = ±2.5V (continued) (TA = 25°C, RF = 200Ω, RG = 90Ω, RT = 76.8Ω, RL = 200Ω, AV = +2, for single ended in, differential out, unless specified). Distortion vs. Output Common Mode Voltage 3rd Order Intermodulation Products vs VOUT -20 -80 RL = 200: VOD = 2 VPP fc = 150 MHz -30 -85 DISTORTION (dBc) -40 150 MHz IMD 3 (dBc) -50 -60 HD3 -70 -90 -95 75 MHz -80 -100 HD2 -90 -100 -1.0 -0.5 0 0.5 -105 0.8 1.0 1.0 1.2 1.4 1.6 1.8 2 DIFFERENTIAL VOUT (VPP_EACH_TONE) VOCM (V) Figure 15. Figure 16. OIP3 vs Output Power POUT OIP3 vs Center Frequency 55 55 150 MHz 75 MHz 50 50 45 45 OIP3 (dBm) OIP3 (dBm) 40 40 250 MHz 35 35 30 25 30 450 MHz 20 25 20 -4 15 -3 -2 -1 0 1 2 3 10 50 100 150 200 250 300 350 400 450 500 4 DIFFERENTIAL OUTPUT POWER POD (dBm/tone) CENTER FREQUENCY (MHz) Figure 17. Figure 18. Noise Figure vs Frequency Maximum VOUT vs. IOUT 1.6 8.0 1.4 MAXIMUM VOUT (V) NOISE FIGURE (dB) 7.8 7.6 7.4 Av= 7.3 V/V Rs= 50 Single Ended Input 7.2 1.2 1.0 0.8 0.6 0.4 0.2 VIN = 1.7V SINGLE-ENDED INPUT 7.0 0 100 200 300 400 FREQUENCY (MHz) 500 -20 -40 -60 -80 -100 OUTPUT CURRENT (mA) Figure 19. 8 0 0 Figure 20. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 Typical Performance Characteristics VS = ±2.5V (continued) (TA = 25°C, RF = 200Ω, RG = 90Ω, RT = 76.8Ω, RL = 200Ω, AV = +2, for single ended in, differential out, unless specified). Minimum VOUT vs. IOUT Overdrive Recovery 0 1.2 3 INPUT VIN = 1.7V SINGLE-ENDED INPUT -0.6 -0.8 -1.0 -1.2 OUTPUT 40 60 80 0 0 -1.4 20 0.4 1 -1 -0.4 -2 -0.8 -3 0 100 200 400 OUTPUT CURRENT (mA) -1.2 1000 Figure 22. PSRR CMRR 90 90 85 85 +PSRR 80 80 75 75 CMRR (dB) PSRR (dBc DIFFERENTIAL) 800 TIME (ns) Figure 21. 70 -PSRR 65 60 70 65 60 55 55 50 50 45 600 INPUT VOLTAGE (V) -0.4 -1.6 0 0.8 2 OUTPUT VOLTAGE (VOD) MINIMUM VOUT (V) -0.2 45 VIN = 0V 40 1 10 100 VIN = 0V VOD = 1VPP 40 1 1000 FREQUENCY (MHz) 10 100 1000 FREQUENCY (MHz) Figure 23. Figure 24. Balance Error Open Loop Transimpedance -30 120 0 100 -30 80 -60 60 -90 40 -120 AV = 1 V/V -45 -50 PHASE (°) -40 |Z| (dB. ) BALANCE ERROR (dBc) -35 -55 20 -60 -65 1 0 10 100 1000 FREQUENCY (MHz) Figure 25. 100k -150 Gain Phase -180 1M 10M 100M 1G FREQUECNY (Hz) 10G Figure 26. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 9 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics VS = ±2.5V (continued) (TA = 25°C, RF = 200Ω, RG = 90Ω, RT = 76.8Ω, RL = 200Ω, AV = +2, for single ended in, differential out, unless specified). Differential S-Parameter Magnitude vs. Frequency Closed Loop Output Impedance 10 1k 0 -10 MAGNITUDE (dB) |Z| ( ) 100 10 1 -20 S11 S22 S21 -30 -40 -50 S11 -60 (SINGLE-ENDED INPUT) -70 S12 -80 -90 100m 1 10 100 FREQUENCY (MHz) 1k -100 1 100 1000 3000 FREQUENCY (MHz) Figure 27. 10 AV = 1 V/V 10 Figure 28. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 APPLICATION INFORMATION The LMH6554 is a fully differential, current feedback amplifier with integrated output common mode control, designed to provide low distortion amplification to wide bandwidth differential signals. The common mode feedback circuit sets the output common mode voltage independent of the input common mode, as well as forcing the V+ and V− outputs to be equal in magnitude and opposite in phase, even when only one of the inputs is driven as in single to differential conversion. The proprietary current feedback architecture of the LMH6554 offers gain and bandwidth independence with exceptional gain flatness and noise performance, even at high values of gain, simply with the appropriate choice of RF1 and RF2. Generally RF1 is set equal to RF2, and RG1 equal to RG2, so that the gain is set by the ratio RF/RG. Matching of these resistors greatly affects CMRR, DC offset error, and output balance. A maximum of 0.1% tolerance resistors are recommended for optimal performance, and the amplifier is internally compensated to operate with optimum gain flatness with RF value of 200Ω depending on PCB layout, and load resistance. The output common mode voltage is set by the VCM pin with a fixed gain of 1 V/V. This pin should be driven by a low impedance reference and should be bypassed to ground with a 0.1 µF ceramic capacitor. Any unwanted signal coupling into the VCM pin will be passed along to the outputs, reducing the performance of the amplifier. The LMH6554 can be configured to operate on a single 5V supply connected to V+ with V- grounded or configured for a split supply operation with V+ = +2.5V and V− = −2.5V. Operation on a single 5V supply, depending on gain, is limited by the input common mode range; therefore, AC coupling may be required. Split supplies will allow much less restricted AC and DC coupled operation with optimum distortion performance. Enable / Disable Operation The LMH6554 is equipped with an enable pin (VEN) to reduce power consumption when not in use. The VEN pin, when not driven, floats high (on). When the VEN pin is pulled low, the amplifier is disabled and the amplifier output stage goes into a high impedance state so the feedback and gain set resistors determine the output impedance of the circuit. For this reason input to output isolation will be poor in the disabled state and the part is not recommended in multiplexed applications where outputs are all tied together. With a 5V difference between V+ and V-, the VEN threshold is ½ way between the supplies (e.g. 2.5V with 5V single supply) as shown in Figure 29. R2 ensures active (enable) mode with VEN floating, and R1 provides input current limiting. VEN also has ESD diodes to either supply. LMH6554 Bias Circuitry R Supply Mid-Point Q2 R2 20k R1 10k Q1 ESD Proteciont V+ VEN R I Tail V- Figure 29. Enable Block Diagram Fully Differential Operation The LMH6554 will perform best in a fully differential configuration. The circuit shown in Figure 30 is a typical fully differential application circuit as might be used to drive an analog to digital converter (ADC). In this circuit the closed loop gain is AV= VOUT / VIN = RF / RG, where the feedback is symmetric. The series output resistors, RO, are optional and help keep the amplifier stable when presented with a capacitive load. Refer to the Driving Capacitive Loads section for details. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 11 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com Here is the expression for the input impedance, RIN, as defined in Figure 30: RIN = 2RG When driven from a differential source, the LMH6554 provides low distortion, excellent balance, and common mode rejection. This is true provided the resistors RF, RG and RO are well matched and strict symmetry is observed in board layout. With an intrinsic device CMRR of greater than 70 dB, using 0.1% resistors will give a worst case CMRR of around 50 dB for most circuits. The circuit configuration shown in Figure 30 was used to measure differential S-parameters in a 100Ω environment at a gain of 1 V/V. Refer to Figure 28 in Typical Performance Characteristics VS = ±2.5V for measurement results. 200: RF RS 50: VS 200: RS 50: + RG + VIN - a 50: 67: VCM RIN VOUT + LMH6554 RG RL=100: - 200: 67: VEN 50: RF 200: Figure 30. Differential S-Parameter Test Circuit Single Ended Input To Differential Output Operation In many applications, it is required to drive a differential input ADC from a single ended source. Traditionally, transformers have been used to provide single to differential conversion, but these are inherently bandpass by nature and cannot be used for DC coupled applications. The LMH6554 provides excellent performance as a single-ended input to differential output converter down to DC. Figure 31 shows a typical application circuit where an LMH6554 is used to produce a balanced differential output signal from a single ended source. RF AV, RIN V RS VS a + RO RG + VCM RT - IN+ RO RG +- ADC + RM IN- VO LMH6554 V - RF § ¨ ¨ © §2RG + RM (1-E2) RIN = ¨¨ 1 + E2 © § ¨ ¨ © § ¨ ¨ © § RG E1 = ¨R + R ¨ G F © § ¨ ¨ © § 2(1 - E1) AV = ¨¨ © E1 + E2 § RG + RM E2 = ¨¨R + R + R F M © G RS = RT || RIN RM = RT || RS Figure 31. Single Ended Input with Differential Output 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 When using the LMH6554 in single-to-differential mode, the complimentary output is forced to a phase inverted replica of the driven output by the common mode feedback circuit as opposed to being driven by its own complimentary input. Consequently, as the driven input changes, the common mode feedback action results in a varying common mode voltage at the amplifier's inputs, proportional to the driving signal. Due to the non-ideal common mode rejection of the amplifier's input stage, a small common mode signal appears at the outputs which is superimposed on the differential output signal. The ratio of the change in output common mode voltage to output differential voltage is commonly referred to as output balance error. The output balance error response of the LMH6554 over frequency is shown in the Typical Performance Characteristics VS = ±2.5V. To match the input impedance of the circuit in Figure 31 to a specified source resistance, RS, requries that RT || RIN = RS. The equations governing RIN and AV for single-to-differential operation are also provide in Figure 31. These equations, along with the source matching condition, must be solved iteratively to achieve the desired gain with the proper input termination. Component values for several common gain configuration in a 50Ω environment are given in Table 1. Table 1. Gain Component Values for 50Ω System Gain RF RG RT RM 0dB 200Ω 191Ω 62Ω 27.7Ω 6dB 200Ω 91Ω 76.8Ω 30.3Ω 12dB 200Ω 35.7Ω 147Ω 37.3Ω Single Supply Operation Single 5V supply operation is possible: however, as discussed earlier, AC input coupling is recommended due to input common mode limitations. An example of an AC coupled, single supply, single-to-differential circuit is shown in Figure 32. Note that when AC coupling, both inputs need to be AC coupled irrespective of single-todifferential or differential-differential configuration. For higher supply voltages DC coupling of the inputs may be possible provided that the output common mode DC level is set high enough so that the amplifier's inputs and outputs are within their specified operation ranges. RF RO 0.1 PF RG RS + VS a RT VCM LMH6554 CL RL VO RG RM 0.1 PF RO RF VEN Figure 32. AC Coupled for Single Supply Operation Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 13 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com Split Supply Operation For optimum performance, split supply operation is recommended using +2.5V and −2.5V supplies; however, operation is possible on split supplies as low as +2.35V and −2.35V and as high as +2.65V and −2.65V. Provided the total supply voltage does not exceed the 4.7V to 5.3V operating specification, non-symmetric supply operation is also possible and in some cases advantageous. For example, if a 5V DC coupled operation is required for low power dissipation but the amplifier input common mode range prevents this operation, it is still possible with split supplies of (V+) and (V-). Where (V+)-(V-) = 5V and V+ and V- are selected to center the amplifier input common mode range to suit the application. Driving Analog To Digital Converters Analog-to-digital converters present challenging load conditions. They typically have high impedance inputs with large and often variable capacitive components. Figure 34 shows the LMH6554 driving an ultra-high-speed Gigasample ADC the ADC10D1500. The LMH6554 common mode voltage is set by the ADC10D1500. The circuit in Figure 34 has a 2nd order bandpass LC filter across the differential inputs of the ADC10D1500. The ADC10D1500 is a dual channel 10–bit ADC with maximum sampling rate of 3 GSPS when operating in a single channel mode and 1.5 GSPS in dual channel mode. Figure 33 shows the SFDR and SNR performance vs. frequency for the LMH6554 and ADC10D1500 combination circuit with the ADC input signal level at −1dBFS. In order to properly match the input impedance seen at the LMH6554 amplifier inputs, RM is chosen to match ZS || RT for proper input balance. The amplifier is configured to provide a gain of 2 V/V in single to differential mode. An external bandpass filter is inserted in series between the input signal source and the amplifier to reduce harmonics and noise from the signal generator. 90 85 80 75 SFDR (dBm) (dB) 70 65 60 55 50 SNR (dBFs) 45 40 0 100 200 300 400 500 600 700 750 INPUT FREQUENCY (MHz) Figure 33. LMH6554 / ADC10D1500 SFDR and SNR Performance vs. Frequency The amplifier and ADC should be located as close together as possible. Both devices require that the filter components be in close proximity to them. The amplifier needs to have minimal parasitic loading on it's outputs and the ADC is sensitive to high frequency noise that may couple in on its inputs. Some high performance ADCs have an input stage that has a bandwidth of several times its sample rate. The sampling process results in all input signals presented to the input stage mixing down into the first Nyquist zone (DC to Fs/2). 14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 200: 91: RS = 50: VS C a V 76.8: AC-Coupled Source + 50: 0.1 PF VCM ADC + - Up To 16-Bit Data Converter LMH6554 - + 91: 50: - 30: VCMO V 0.1 PF 0.1 PF VEN 200: Figure 34. Driving a 10-bit Gigasample ADC Output Noise Performance and Measurement Unlike differential amplifiers based on voltage feedback architectures, noise sources internal to the LMH6554 refer to the inputs largely as current sources, hence the low input referred voltage noise and relatively higher input referred current noise. The output noise is therefore more strongly coupled to the value of the feedback resistor and not to the closed loop gain, as would be the case with a voltage feedback differential amplifier. This allows operation of the LMH6554 at much higher gain without incurring a substantial noise performance penalty, simply by choosing a suitable feedback resistor. Figure 35 shows a circuit configuration used to measure noise figure for the LMH6554 in a 50Ω system. A feedback resistor value of 200Ω is chosen for the UQFN package to minimize output noise while simultaneously allowing both high gain (7 V/V) and proper 50Ω input termination. Refer to Single Ended Input To Differential Output Operation for the calculation of resistor and gain values. 200: V RS = 50: VS + 1 PF 2:1 (TURNS) 8: VCM a + VO LMH6554 + 50: 50: 8: 1 PF V - 200: AV = 7 V/V Figure 35. Noise Figure Circuit Configuration Driving Capacitive Loads As noted previously, capacitive loads should be isolated from the amplifier output with small valued resistors. This is particularly the case when the load has a resistive component that is 500Ω or higher. A typical ADC has capacitive components of around 10 pF and the resistive component could be 1000Ω or higher. If driving a transmission line, such as 50Ω coaxial or 100Ω twisted pair, using matching resistors will be sufficient to isolate any subsequent capacitance. For other applications see Figure 8 in Typical Performance Characteristics VS = ±2.5V. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 15 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com Balanced Cable Driver With up to 5.68 VPP differential output voltage swing the LMH6554 can be configured as a cable driver. The LMH6554 is also suitable for driving differential cables from a single ended source as shown in Figure 36. 200: 50: 91: RS = 50: + VS a 76.8: Input Source VCM 2 VPP LMH6554 91: VEN 50: 30.3: 100: TWISTED PAIR 200: Figure 36. Fully Differential Cable Driver Power Supply Bypassing The LMH6554 requires supply bypassing capacitors as shown in Figure 37 and Figure 38. The 0.01 μF and 0.1 μF capacitors should be leadless SMT ceramic capacitors and should be no more than 3 mm from the supply pins. These capacitors should be star routed with a dedicated ground return plane or trace for best harmonic distortion performance. Thin traces or small vias will reduce the effectiveness of bypass capacitors. Also shown in both figures is a capacitor from the VCM and VEN pins to ground. These inputs are high impedance and can provide a coupling path into the amplifier for external noise sources, possibly resulting in loss of dynamic range, degraded CMRR, degraded balance and higher distortion. + V 0.1 PF 10 PF 0.01 PF +IN VCM -OUT + LMH6554 -IN 0.1 PF - +OUT VEN 0.1 PF - V 0.1 PF 0.01 PF 10 PF Figure 37. Split Supply Bypassing Capacitors 16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 V + 0.01 PF 0.1 PF 10 PF +IN VCM + -OUT LMH6554 -IN +OUT - 0.1 PF VEN 0.01 PF Figure 38. Single Supply Bypassing Capacitors Power Dissipation The LMH6554 is optimized for maximum speed and performance in a small form factor 14 lead UQFN package. To ensure maximum output drive and highest performance, thermal shutdown is not provided. Therefore, it is of utmost importance to make sure that the TJMAX is never exceeded due to the overall power dissipation. Follow these steps to determine the maximum power dissipation for the LMH6554: 1. Calculate the quiescent (no-load) power: PAMP = ICC * (VS) where • VS = V+ − V-. (Be sure to include any current through the feedback network if VCM is not mid-rail) (1) 2. Calculate the RMS power dissipated in each of the output stages: PD (rms) = rms ((VS − V+OUT) * I+OUT) + rms ((VS − V-OUT) * I-OUT) where • • • VOUT and IOUT are the voltage the current measured at the output pins of the differential amplifier as if they were single ended amplifiers VS is the total supply voltage (2) 3. Calculate the total RMS power: PT = PAMP + PD (3) The maximum power that the LMH6554 package can dissipate at a given temperature can be derived with the following equation: PMAX = (150° − TAMB)/ θJA where • • • TAMB = Ambient temperature (°C) θJA = Thermal resistance, from junction to ambient, for a given package (°C/W) For the 14 lead UQFN package, θJA is 60°C/W (4) NOTE If VCM is not 0V then there will be quiescent current flowing in the feedback network. This current should be included in the thermal calculations and added into the quiescent power dissipation of the amplifier. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 17 LMH6554 SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 www.ti.com ESD Protection The LMH6554 is protected against electrostatic discharge (ESD) on all pins. The LMH6554 will survive 2000V Human Body model and 250V Machine model events. Under normal operation the ESD diodes have no affect on circuit performance. There are occasions, however, when the ESD diodes will be evident. If the LMH6554 is driven by a large signal while the device is powered down the ESD diodes will conduct. The current that flows through the ESD diodes will either exit the chip through the supply pins or will flow through the device, hence it is possible to power up a chip with a large signal applied to the input pins. Using the shutdown mode is one way to conserve power and still prevent unexpected operation. Board Layout The LMH6554 is a high speed, high performance amplifier. In order to get maximum benefit from the differential circuit architecture board layout and component selection is very critical. The circuit board should have a low inductance ground plane and well bypassed broad supply lines. External components should be leadless surface mount types. The feedback network and output matching resistors should be composed of short traces and precision resistors (0.1%). The output matching resistors should be placed within 3 or 4 mm of the amplifier as should the supply bypass capacitors. Refer to Power Supply Bypassing for recommendations on bypass circuit layout. Evaluation boards are available through the product folder on ti.com. By design, the LMH6554 is relatively insensitive to parasitic capacitance at its inputs. Nonetheless, ground and power plane metal should be removed from beneath the amplifier and from beneath RF and RG for best performance at high frequency. With any differential signal path, symmetry is very important. Even small amounts of asymmetry can contribute to distortion and balance errors. Evaluation Board See LMH6554 Product Folder for evaluation board availability and ordering information. 18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 LMH6554 www.ti.com SNOSB30O – OCTOBER 2008 – REVISED MARCH 2013 REVISION HISTORY Changes from Revision N (March 2013) to Revision O • Page Changed layout of National Data Sheet to TI format .......................................................................................................... 18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH6554 19 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMH6554LE/NOPB ACTIVE UQFN NHJ 14 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 AJA LMH6554LEE/NOPB ACTIVE UQFN NHJ 14 250 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 AJA LMH6554LEX/NOPB ACTIVE UQFN NHJ 14 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 125 AJA (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH6554LE/NOPB UQFN NHJ 14 LMH6554LEE/NOPB UQFN NHJ LMH6554LEX/NOPB UQFN NHJ SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 2.8 2.8 1.0 8.0 12.0 Q1 14 250 178.0 12.4 2.8 2.8 1.0 8.0 12.0 Q1 14 4500 330.0 12.4 2.8 2.8 1.0 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH6554LE/NOPB UQFN NHJ 14 1000 213.0 191.0 55.0 LMH6554LEE/NOPB UQFN NHJ 14 250 213.0 191.0 55.0 LMH6554LEX/NOPB UQFN NHJ 14 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA NHJ0014A LEE14A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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