Renesas HD6417720BL133C Renesas 32-bit risc microcomputer superhtm risc engine family / sh7700 sery Datasheet

REJ09B0033-0300
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
32
SH7720 Group, SH7721 Group
Hardware Manual
SuperH
TM
Renesas 32-Bit RISC Microcomputer
RISC engine Family / SH7700 Series
SH7720 Group
HD6417720
HD6417320
SH7721 Group
R8A77210
R8A77211
Rev.3.00
Revision Date: Jan. 18, 2008
Rev. 3.00 Jan. 18, 2008 Page ii of lxii
Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate
Renesas products for their use. Renesas neither makes warranties or representations with respect to the
accuracy or completeness of the information contained in this document nor grants any license to any
intellectual property rights or any other rights of Renesas or any third party with respect to the information in
this document.
2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising
out of the use of any information in this document, including, but not limited to, product data, diagrams, charts,
programs, algorithms, and application circuit examples.
3. You should not use the products or the technology described in this document for the purpose of military
applications such as the development of weapons of mass destruction or for the purpose of any other military
use. When exporting the products or technology described herein, you should follow the applicable export
control laws and regulations, and procedures required by such laws and regulations.
4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and
application circuit examples, is current as of the date this document is issued. Such information, however, is
subject to change without any prior notice. Before purchasing or using any Renesas products listed in this
document, please confirm the latest product information with a Renesas sales office. Also, please pay regular
and careful attention to additional and different information to be disclosed by Renesas such as that disclosed
through our website. (http://www.renesas.com )
5. Renesas has used reasonable care in compiling the information included in this document, but Renesas
assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information
included in this document.
6. When using or otherwise relying on the information in this document, you should evaluate the information in
light of the total system before deciding about the applicability of such information to the intended application.
Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any
particular application and specifically disclaims any liability arising out of the application and use of the
information in this document or Renesas products.
7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas
products are not designed, manufactured or tested for applications or otherwise in systems the failure or
malfunction of which may cause a direct threat to human life or create a risk of human injury or which require
especially high quality and reliability such as safety systems, or equipment or systems for transportation and
traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication
transmission. If you are considering the use of our products for such purposes, please contact a Renesas
sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above.
8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below:
(1) artificial life support devices or systems
(2) surgical implantations
(3) healthcare intervention (e.g., excision, administration of medication, etc.)
(4) any other purposes that pose a direct threat to human life
Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who
elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas
Technology Corp., its affiliated companies and their officers, directors, and employees against any and all
damages arising out of such applications.
9. You should use the products described herein within the range specified by Renesas, especially with respect
to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation
characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or
damages arising out of the use of Renesas products beyond such specified ranges.
10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific
characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use
conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and
injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for
hardware and software including but not limited to redundancy, fire control and malfunction prevention,
appropriate treatment for aging degradation or any other applicable measures. Among others, since the
evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or
system manufactured by you.
11. In case Renesas products listed in this document are detached from the products to which the Renesas
products are attached or affixed, the risk of accident such as swallowing by infants and small children is very
high. You should implement safety measures so that Renesas products may not be easily detached from your
products. Renesas shall have no liability for damages arising out of such detachment.
12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written
approval from Renesas.
13. Please contact a Renesas sales office if you have any questions regarding the information contained in this
document, Renesas semiconductor products, or if you have any other inquiries.
Rev. 3.00 Jan. 18, 2008 Page iii of lxii
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product's state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system's
operation is not guaranteed if they are accessed.
Rev. 3.00 Jan. 18, 2008 Page iv of lxii
Configuration of This Manual
This manual comprises the following items:
1.
2.
3.
4.
5.
6.
General Precautions on Handling of Product
Configuration of This Manual
Preface
Contents
Overview
Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each
section includes notes in relation to the descriptions given, and usage notes are given, as required,
as the final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev. 3.00 Jan. 18, 2008 Page v of lxii
Preface
The SH7720 or SH7721 Group RISC (Reduced Instruction Set Computer) microcomputer
includes a Renesas Technology original RISC CPU as its core, and the peripheral functions
required to configure a system.
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Users of this manual are expected to understand the
fundamentals of electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the above users.
Refer to the SH-3/SH-3E/SH3-DSP Software Manual for a detailed description of
the instruction set.
Notes on reading this manual:
• Product names
The following products are covered in this manual.
Product Classifications and Abbreviations
Basic Classification
Product Code
SH7720 Group
HD6417720, HD6417320
SH7721 Group
R8A77210, R8A77211
• In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions, and electrical characteristics.
• In order to understand the details of the CPU's functions
Read the SH-3/SH-3E/SH3-DSP Software Manual.
Rev. 3.00 Jan. 18, 2008 Page vi of lxii
Rules:
Register name:
The following notation is used for cases when the same or a
similar function, e.g. serial communication, is implemented
on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB (most significant bit) is on the left and the LSB
(least significant bit) is on the right.
Number notation: Binary is B'xx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation: An overbar is added to a low-active signal: xxxx
Related Manuals:
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com/
SH7720 or SH7721 Group manuals:
Document Title
Document No.
SH7720/SH7721 Group Hardware Manual
This manual
SH-3/SH-3E/SH3-DSP Software Manual
REJ09B0317
Users manuals for development tools:
Document Title
Document No.
TM
Super RISC engine C/C++ Compiler, Assembler, Optimizing Linkage Editor REJ10B0152
Compiler Package V.9.00 User's Manual
SuperHTM RISC engine High-performance Embedded Workshop 3 User's
Manual
REJ10B0025
SuperHTM RISC engine High-performance Embedded Workshop 3 Tutorial
REJ10B0023
Application note:
Document Title
TM
SuperH
Document No.
RISC engine C/C++ Compiler Package Application Note
REJ05B0463
Rev. 3.00 Jan. 18, 2008 Page vii of lxii
Abbreviations
ADC
ALU
ASE
ASID
AUD
BCD
bps
BSC
CCN
CMT
CPG
CPU
DES
DMAC
etu
FIFO
Hi-Z
H-UDI
INTC
IrDA
JTAG
LQFP
LRU
LSB
MMU
MPX
MSB
PC
PFC
PLL
PWM
RAM
RISC
Analog to Digital Converter
Arithmetic Logic Unit
Adaptive System Evaluator
Address Space Identifier
Advanced User Debugger
Binary Coded Decimal
bit per second
Bus State Controller
Cache memory Controller
Compare Match Timer
Clock Pulse Generator
Central Processing Unit
Data Encryption Standard
Direct Memory Access Controller
Elementary Time Unit
First-In First-Out
High Impedance
User Debugging Interface
Interrupt Controller
Infrared Data Association
Joint Test Action Group
Low Profile QFP
Least Recently Used
Least Significant Bit
Memory Management Unit
Multiplex
Most Significant Bit
Program Counter
Pin Function Controller
Phase Locked Loop
Pulse Width Modulation
Random Access Memory
Reduced Instruction Set Computer
Rev. 3.00 Jan. 18, 2008 Page viii of lxii
ROM
RSA
RTC
SCIF
SDHI
SDRAM
SSL
TAP
T.B.D
TLB
TMU
TPU
UART
UBC
USB
WDT
Read Only Memory
Rivest Shamir Adleman
Real Time Clock
Serial Communication Interface with FIFO
SD Host Interface
Synchronous DRAM
Secure Socket Layer
Test Access Port
To Be Determined
Translation Lookaside Buffer
Timer Unit
Timer Pulse Unit
Universal Asynchronous Receiver/Transmitter
User Break Controller
Universal Serial Bus
Watchdog Timer
All trademarks and registered trademarks are the property of their respective owners.
Rev. 3.00 Jan. 18, 2008 Page ix of lxii
Rev. 3.00 Jan. 18, 2008 Page x of lxii
Contents
Section 1 Overview..................................................................................................1
1.1
1.2
1.3
Features.................................................................................................................................. 1
Block Diagram ..................................................................................................................... 10
Pin Assignments................................................................................................................... 10
1.3.1 Pin Assignments ..................................................................................................... 10
1.3.2 Pin Functions .......................................................................................................... 25
Section 2 CPU........................................................................................................37
2.1
2.2
2.3
2.4
2.5
2.6
Processing States and Processing Modes ............................................................................. 37
2.1.1 Processing States..................................................................................................... 37
2.1.2 Processing Modes ................................................................................................... 38
Memory Map ....................................................................................................................... 39
2.2.1 Virtual Address Space............................................................................................. 39
2.2.2 External Memory Space.......................................................................................... 40
Register Descriptions ........................................................................................................... 42
2.3.1 General Registers.................................................................................................... 45
2.3.2 System Registers..................................................................................................... 46
2.3.3 Program Counter..................................................................................................... 47
2.3.4 Control Registers .................................................................................................... 48
Data Formats........................................................................................................................ 51
2.4.1 Register Data Format .............................................................................................. 51
2.4.2 Memory Data Formats ............................................................................................ 52
Features of CPU Core Instructions ...................................................................................... 54
2.5.1 Instruction Execution Method................................................................................. 54
2.5.2 CPU Instruction Addressing Modes ....................................................................... 56
2.5.3 Instruction Formats ................................................................................................. 60
Instruction Set ...................................................................................................................... 63
2.6.1 Instruction Set Based on Functions......................................................................... 63
2.6.2 Operation Code Map............................................................................................... 77
Section 3 DSP Operating Unit ...............................................................................81
3.1
3.2
DSP Extended Functions ..................................................................................................... 81
DSP Mode Resources .......................................................................................................... 83
3.2.1 Processing Modes ................................................................................................... 83
3.2.2 DSP Mode Memory Map........................................................................................ 83
3.2.3 CPU Register Sets................................................................................................... 84
Rev. 3.00 Jan. 18, 2008 Page xi of lxii
3.3
3.4
3.5
3.6
3.2.4 DSP Registers ......................................................................................................... 88
CPU Extended Instructions.................................................................................................. 89
3.3.1 DSP Repeat Control................................................................................................ 89
DSP Data Transfer Instructions ......................................................................................... 100
3.4.1 General Registers.................................................................................................. 104
3.4.2 DSP Data Addressing ........................................................................................... 106
3.4.3 Modulo Addressing .............................................................................................. 108
3.4.4 Memory Data Formats .......................................................................................... 110
3.4.5 Instruction Formats of Double and Single Transfer Instructions .......................... 111
DSP Data Operation Instructions....................................................................................... 113
3.5.1 DSP Registers ....................................................................................................... 113
3.5.2 DSP Operation Instruction Set.............................................................................. 118
3.5.3 DSP-Type Data Formats....................................................................................... 123
3.5.4 ALU Fixed-Point Arithmetic Operations.............................................................. 125
3.5.5 ALU Integer Operations ....................................................................................... 131
3.5.6 ALU Logical Operations ...................................................................................... 133
3.5.7 Fixed-Point Multiply Operation............................................................................ 135
3.5.8 Shift Operations .................................................................................................... 137
3.5.9 Most Significant Bit Detection Operation ............................................................ 141
3.5.10 Rounding Operation.............................................................................................. 144
3.5.11 Overflow Protection.............................................................................................. 146
3.5.12 Local Data Move Instruction ................................................................................ 147
3.5.13 Operand Conflict .................................................................................................. 148
DSP Extended Function Instruction Set............................................................................. 149
3.6.1 CPU Extended Instructions................................................................................... 149
3.6.2 Double-Data Transfer Instructions ....................................................................... 151
3.6.3 Single-Data Transfer Instructions ......................................................................... 152
3.6.4 DSP Operation Instructions .................................................................................. 154
3.6.5 Operation Code Map in DSP Mode ...................................................................... 160
Section 4 Memory Management Unit (MMU).................................................... 165
4.1
4.2
4.3
Role of MMU .................................................................................................................... 165
4.1.1 MMU of This LSI................................................................................................. 168
Register Descriptions......................................................................................................... 174
4.2.1 Page Table Entry Register High (PTEH).............................................................. 174
4.2.2 Page Table Entry Register Low (PTEL) ............................................................... 175
4.2.3 Translation Table Base Register (TTB) ................................................................ 175
4.2.4 MMU Control Register (MMUCR) ...................................................................... 175
TLB Functions ................................................................................................................... 177
4.3.1 Configuration of the TLB ..................................................................................... 177
Rev. 3.00 Jan. 18, 2008 Page xii of lxii
4.4
4.5
4.6
4.7
4.3.2 TLB Indexing........................................................................................................ 179
4.3.3 TLB Address Comparison .................................................................................... 180
4.3.4 Page Management Information............................................................................. 182
MMU Functions................................................................................................................. 183
4.4.1 MMU Hardware Management .............................................................................. 183
4.4.2 MMU Software Management ............................................................................... 184
4.4.3 MMU Instruction (LDTLB).................................................................................. 184
4.4.4 Avoiding Synonym Problems ............................................................................... 186
MMU Exceptions............................................................................................................... 188
4.5.1 TLB Miss Exception............................................................................................. 188
4.5.2 TLB Protection Violation Exception .................................................................... 189
4.5.3 TLB Invalid Exception ......................................................................................... 190
4.5.4 Initial Page Write Exception................................................................................. 191
4.5.5 MMU Exception in Repeat Loop.......................................................................... 192
Memory-Mapped TLB....................................................................................................... 194
4.6.1 Address Array ....................................................................................................... 194
4.6.2 Data Array ............................................................................................................ 194
4.6.3 Usage Examples.................................................................................................... 196
Usage Note......................................................................................................................... 196
Section 5 Cache ...................................................................................................197
5.1
5.2
5.3
5.4
Features.............................................................................................................................. 197
5.1.1 Cache Structure..................................................................................................... 197
Register Descriptions ......................................................................................................... 199
5.2.1 Cache Control Register 1 (CCR1) ........................................................................ 200
5.2.2 Cache Control Register 2 (CCR2) ........................................................................ 201
5.2.3 Cache Control Register 3 (CCR3) ........................................................................ 204
Operation ........................................................................................................................... 205
5.3.1 Searching the Cache.............................................................................................. 205
5.3.2 Read Access.......................................................................................................... 207
5.3.3 Prefetch Operation ................................................................................................ 207
5.3.4 Write Access ......................................................................................................... 207
5.3.5 Write-Back Buffer ................................................................................................ 208
5.3.6 Coherency of Cache and External Memory .......................................................... 208
Memory-Mapped Cache .................................................................................................... 209
5.4.1 Address Array ....................................................................................................... 209
5.4.2 Data Array ............................................................................................................ 210
5.4.3 Usage Examples.................................................................................................... 212
Rev. 3.00 Jan. 18, 2008 Page xiii of lxii
Section 6 X/Y Memory ....................................................................................... 213
6.1
6.2
6.3
Features.............................................................................................................................. 213
Operation ........................................................................................................................... 214
6.2.1 Access from CPU ................................................................................................. 214
6.2.2 Access from DSP.................................................................................................. 214
6.2.3 Access from Bus Master Module.......................................................................... 215
Usage Notes ....................................................................................................................... 215
6.3.1 Page Conflict ........................................................................................................ 215
6.3.2 Bus Conflict .......................................................................................................... 215
6.3.3 MMU and Cache Settings..................................................................................... 216
6.3.4 Sleep Mode ........................................................................................................... 216
Section 7 Exception Handling ............................................................................. 217
7.1
7.2
7.3
7.4
7.5
Register Descriptions......................................................................................................... 217
7.1.1 TRAPA Exception Register (TRA) ...................................................................... 218
7.1.2 Exception Event Register (EXPEVT)................................................................... 219
7.1.3 Interrupt Event Register (INTEVT)...................................................................... 219
7.1.4 Interrupt Event Register 2 (INTEVT2)................................................................. 220
7.1.5 Exception Address Register (TEA) ...................................................................... 220
Exception Handling Function ............................................................................................ 221
7.2.1 Exception Handling Flow ..................................................................................... 221
7.2.2 Exception Vector Addresses................................................................................. 222
7.2.3 Exception Codes ................................................................................................... 222
7.2.4 Exception Request and BL Bit (Multiple Exception Prevention) ......................... 222
7.2.5 Exception Source Acceptance Timing and Priority .............................................. 223
Individual Exception Operations ....................................................................................... 227
7.3.1 Resets.................................................................................................................... 227
7.3.2 General Exceptions............................................................................................... 227
7.3.3 General Exceptions (MMU Exceptions)............................................................... 231
Exception Processing While DSP Extension Function is Valid......................................... 234
7.4.1 Illegal Instruction Exception and Illegal Slot Instruction Exception .................... 234
7.4.2 CPU Address Error ............................................................................................... 234
7.4.3 Exception in Repeat Control Period ..................................................................... 234
Usage Notes ....................................................................................................................... 241
Section 8 Interrupt Controller (INTC)................................................................. 243
8.1
8.2
8.3
Features.............................................................................................................................. 243
Input/Output Pins............................................................................................................... 245
Register Descriptions......................................................................................................... 246
Rev. 3.00 Jan. 18, 2008 Page xiv of lxii
8.4
8.5
8.3.1 Interrupt Priority Registers A to J (IPRA to IPRJ)................................................ 247
8.3.2 Interrupt Control Register 0 (ICR0)...................................................................... 249
8.3.3 Interrupt Control Register 1 (ICR1)...................................................................... 250
8.3.4 Interrupt Request Register 0 (IRR0) ..................................................................... 252
8.3.5 Interrupt Request Register 1 (IRR1) ..................................................................... 253
8.3.6 Interrupt Request Register 2 (IRR2) ..................................................................... 254
8.3.7 Interrupt Request Register 3 (IRR3) ..................................................................... 255
8.3.8 Interrupt Request Register 4 (IRR4) ..................................................................... 256
8.3.9 Interrupt Request Register 5 (IRR5) ..................................................................... 257
8.3.10 Interrupt Request Register 6 (IRR6) ..................................................................... 259
8.3.11 Interrupt Request Register 7 (IRR7) ..................................................................... 260
8.3.12 Interrupt Request Register 8 (IRR8) ..................................................................... 261
8.3.13 Interrupt Request Register 9 (IRR9) ..................................................................... 262
8.3.14 PINT Interrupt Enable Register (PINTER)........................................................... 264
8.3.15 Interrupt Control Register 2 (ICR2)...................................................................... 265
Interrupt Sources................................................................................................................ 266
8.4.1 NMI Interrupt........................................................................................................ 266
8.4.2 IRQ Interrupts ....................................................................................................... 266
8.4.3 IRL interrupts........................................................................................................ 267
8.4.4 PINT Interrupts ..................................................................................................... 268
8.4.5 On-Chip Peripheral Module Interrupts ................................................................. 268
8.4.6 Interrupt Exception Handling and Priority............................................................ 269
Operation ........................................................................................................................... 276
8.5.1 Interrupt Sequence ................................................................................................ 276
8.5.2 Multiple Interrupts ................................................................................................ 278
Section 9 Bus State Controller (BSC)..................................................................279
9.1
9.2
9.3
9.4
Features.............................................................................................................................. 279
Input/Output Pins ............................................................................................................... 283
Area Overview ................................................................................................................... 285
9.3.1 Area Division........................................................................................................ 285
9.3.2 Shadow Area......................................................................................................... 285
9.3.3 Address Map ......................................................................................................... 287
9.3.4 Area 0 Memory Type and Memory Bus Width .................................................... 289
9.3.5 Data Alignment..................................................................................................... 289
Register Descriptions ......................................................................................................... 290
9.4.1 Common Control Register (CMNCR) .................................................................. 291
9.4.2 CSn Space Bus Control Register (CSnBCR) ........................................................ 294
9.4.3 CSn Space Wait Control Register (CSnWCR) ..................................................... 299
9.4.4 SDRAM Control Register (SDCR)....................................................................... 325
Rev. 3.00 Jan. 18, 2008 Page xv of lxii
9.5
9.6
9.4.5 Refresh Timer Control/Status Register (RTCSR)................................................. 328
9.4.6 Refresh Timer Counter (RTCNT)......................................................................... 329
9.4.7 Refresh Time Constant Register (RTCOR) .......................................................... 330
9.4.8 SDRAM Mode Registers 2, 3 (SDMR2 and SRMR3) ......................................... 330
Operation ........................................................................................................................... 331
9.5.1 Endian/Access Size and Data Alignment.............................................................. 331
9.5.2 Normal Space Interface ........................................................................................ 337
9.5.3 Access Wait Control ............................................................................................. 343
9.5.4 CSn Assert Period Expansion ............................................................................... 345
9.5.5 SDRAM Interface ................................................................................................. 346
9.5.6 Burst ROM (Clock Asynchronous) Interface ....................................................... 385
9.5.7 Byte-Selection SRAM Interface ........................................................................... 387
9.5.8 PCMCIA Interface................................................................................................ 392
9.5.9 Burst ROM (Clock Synchronous) Interface.......................................................... 400
9.5.10 Wait between Access Cycles ................................................................................ 401
9.5.11 Bus Arbitration ..................................................................................................... 401
Usage Notes ....................................................................................................................... 404
Section 10 Direct Memory Access Controller (DMAC)..................................... 407
10.1 Features.............................................................................................................................. 407
10.2 Input/Output Pins............................................................................................................... 409
10.3 Register Descriptions......................................................................................................... 410
10.3.1 DMA Source Address Registers (SAR_0 to SAR_5) ........................................... 411
10.3.2 DMA Destination Address Registers (DAR_0 to DAR_5) .................................. 412
10.3.3 DMA Transfer Count Registers (DMATCR_0 to DMATCR_5) ......................... 412
10.3.4 DMA Channel Control Registers (CHCR_0 to CHCR_5) ................................... 413
10.3.5 DMA Operation Register (DMAOR) ................................................................... 418
10.3.6 DMA Extended Resource Selectors 0 to 2 (DMARS0 to DMARS2)................... 420
10.4 Operation ........................................................................................................................... 424
10.4.1 DMA Transfer Flow ............................................................................................. 424
10.4.2 DMA Transfer Requests ....................................................................................... 426
10.4.3 Channel Priority.................................................................................................... 431
10.4.4 DMA Transfer Types............................................................................................ 434
10.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing ........................... 444
10.5 Usage Notes ....................................................................................................................... 448
10.5.1 Notes on DACK Pin Output ................................................................................. 448
10.5.2 Notes on the Cases When DACK is Divided........................................................ 448
10.5.3 Other Notes........................................................................................................... 452
Rev. 3.00 Jan. 18, 2008 Page xvi of lxii
Section 11 Clock Pulse Generator (CPG)............................................................453
11.1
11.2
11.3
11.4
Features.............................................................................................................................. 453
Input/Output Pins ............................................................................................................... 457
Clock Operating Modes ..................................................................................................... 458
Register Descriptions ......................................................................................................... 461
11.4.1 Frequency Control Register (FRQCR) ................................................................. 461
11.4.2 USBH/USBF Clock Control Register (UCLKCR) ............................................... 464
11.5 Changing Frequency .......................................................................................................... 465
11.5.1 Changing Multiplication Rate............................................................................... 465
11.5.2 Changing Division Ratio....................................................................................... 465
11.6 Usage Notes ....................................................................................................................... 466
11.7 Notes on Board Design ...................................................................................................... 466
Section 12 Watchdog Timer (WDT)....................................................................469
12.1 Features.............................................................................................................................. 469
12.2 Register Descriptions for WDT ......................................................................................... 471
12.2.1 Watchdog Timer Counter (WTCNT).................................................................... 471
12.2.2 Watchdog Timer Control/Status Register (WTCSR)............................................ 471
12.2.3 Notes on Register Access...................................................................................... 473
12.3 WDT Operation ................................................................................................................. 474
12.3.1 Canceling Software Standbys ............................................................................... 474
12.3.2 Changing Frequency ............................................................................................. 475
12.3.3 Using Watchdog Timer Mode .............................................................................. 475
12.3.4 Using Interval Timer Mode .................................................................................. 476
Section 13 Power-Down Modes ..........................................................................477
13.1 Features.............................................................................................................................. 477
13.1.1 Power-Down Modes ............................................................................................. 477
13.1.2 Reset ..................................................................................................................... 478
13.2 Input/Output Pins ............................................................................................................... 479
13.3 Register Descriptions ......................................................................................................... 480
13.3.1 Standby Control Register (STBCR)...................................................................... 480
13.3.2 Standby Control Register 2 (STBCR2)................................................................. 481
13.3.3 Standby Control Register 3 (STBCR3)................................................................. 483
13.3.4 Standby Control Register 4 (STBCR4)................................................................. 484
13.3.5 Standby Control Register 5 (STBCR5)................................................................. 486
13.4 Sleep Mode ........................................................................................................................ 488
13.4.1 Transition to Sleep Mode...................................................................................... 488
13.4.2 Canceling Sleep Mode .......................................................................................... 488
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13.5 Software Standby Mode..................................................................................................... 489
13.5.1 Transition to Software Standby Mode .................................................................. 489
13.5.2 Canceling Software Standby Mode ...................................................................... 489
13.6 Module Standby Function.................................................................................................. 491
13.6.1 Transition to Module Standby Function ............................................................... 491
13.6.2 Canceling Module Standby Function.................................................................... 491
13.7 STATUS Pin Change Timing ............................................................................................ 492
13.7.1 Reset ..................................................................................................................... 492
13.7.2 Software Standby Mode........................................................................................ 493
13.7.3 Sleep Mode ........................................................................................................... 494
13.8 Hardware Standby Mode ................................................................................................... 496
13.8.1 Transition to Hardware Standby Mode................................................................. 496
13.8.2 Canceling the Hardware Standby Mode ............................................................... 496
13.8.3 Hardware Standby Mode Timing.......................................................................... 497
Section 14 Timer Unit (TMU)............................................................................. 499
14.1 Features.............................................................................................................................. 499
14.2 Register Descriptions......................................................................................................... 501
14.2.1 Timer Start Register (TSTR) ................................................................................ 502
14.2.2 Timer Control Registers (TCR) ............................................................................ 503
14.2.3 Timer Constant Registers (TCOR) ....................................................................... 504
14.2.4 Timer Counters (TCNT) ....................................................................................... 504
14.3 Operation ........................................................................................................................... 505
14.3.1 Counter Operation ................................................................................................ 505
14.4 Interrupts............................................................................................................................ 508
14.4.1 Status Flag Set Timing.......................................................................................... 508
14.4.2 Status Flag Clear Timing ...................................................................................... 508
14.4.3 Interrupt Sources and Priorities ............................................................................ 509
14.5 Usage Notes ....................................................................................................................... 510
14.5.1 Writing to Registers .............................................................................................. 510
14.5.2 Reading Registers ................................................................................................. 510
Section 15 16-Bit Timer Pulse Unit (TPU) ......................................................... 511
15.1 Features.............................................................................................................................. 511
15.2 Input/Output Pins............................................................................................................... 514
15.3 Register Descriptions......................................................................................................... 515
15.3.1 Timer Control Registers (TCR) ............................................................................ 516
15.3.2 Timer Mode Registers (TMDR) ........................................................................... 520
15.3.3 Timer I/O Control Registers (TIOR) .................................................................... 521
15.3.4 Timer Interrupt Enable Registers (TIER) ............................................................. 523
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15.3.5 Timer Status Registers (TSR) ............................................................................... 524
15.3.6 Timer Counters (TCNT) ....................................................................................... 526
15.3.7 Timer General Registers (TGR)............................................................................ 526
15.3.8 Timer Start Register (TSTR) ................................................................................ 527
15.4 Operation ........................................................................................................................... 528
15.4.1 Overview............................................................................................................... 528
15.4.2 Basic Functions..................................................................................................... 529
15.4.3 Buffer Operation ................................................................................................... 534
15.4.4 PWM Modes ......................................................................................................... 536
15.4.5 Phase Counting Mode........................................................................................... 539
15.5 Usage Notes ....................................................................................................................... 545
Section 16 Compare Match Timer (CMT) ..........................................................547
16.1 Features.............................................................................................................................. 547
16.2 Register Descriptions ......................................................................................................... 549
16.2.1 Compare Match Timer Start Register (CMSTR) .................................................. 550
16.2.2 Compare Match Timer Control/Status Register (CMCSR) .................................. 551
16.2.3 Compare Match Timer Counter (CMCNT) .......................................................... 553
16.2.4 Compare Match Timer Constant Register (CMCOR)........................................... 553
16.3 Operation ........................................................................................................................... 554
16.3.1 Counter Operation................................................................................................. 554
16.3.2 Counter Size.......................................................................................................... 555
16.3.3 Timing for Counting by CMCNT ......................................................................... 556
16.3.4 DMA Transfer Requests and Internal Interrupt Requests to CPU ........................ 556
16.3.5 Compare Match Flag Set Timing (All Channels) ................................................. 557
Section 17 Realtime Clock (RTC) .......................................................................559
17.1 Features.............................................................................................................................. 559
17.2 Input/Output Pin................................................................................................................. 561
17.3 Register Descriptions ......................................................................................................... 562
17.3.1 64-Hz Counter (R64CNT) .................................................................................... 563
17.3.2 Second Counter (RSECCNT) ............................................................................... 564
17.3.3 Minute Counter (RMINCNT) ............................................................................... 565
17.3.4 Hour Counter (RHRCNT)..................................................................................... 566
17.3.5 Day of Week Counter (RWKCNT) ...................................................................... 567
17.3.6 Date Counter (RDAYCNT) .................................................................................. 568
17.3.7 Month Counter (RMONCNT) .............................................................................. 569
17.3.8 Year Counter (RYRCNT) ..................................................................................... 569
17.3.9 Second Alarm Register (RSECAR) ...................................................................... 570
17.3.10 Minute Alarm Register (RMINAR)...................................................................... 570
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17.3.11 Hour Alarm Register (RHRAR) ........................................................................... 571
17.3.12 Day of Week Alarm Register (RWKAR) ............................................................. 572
17.3.13 Date Alarm Register (RDAYAR)......................................................................... 573
17.3.14 Month Alarm Register (RMONAR) ..................................................................... 574
17.3.15 Year Alarm Register (RYRAR)............................................................................ 574
17.3.16 RTC Control Register 1 (RCR1)........................................................................... 575
17.3.17 RTC Control Register 2 (RCR2)........................................................................... 577
17.3.18 RTC Control Register 3 (RCR3)........................................................................... 579
17.4 Operation ........................................................................................................................... 580
17.4.1 Initial Settings of Registers after Power-On ......................................................... 580
17.4.2 Setting Time ......................................................................................................... 580
17.4.3 Reading Time........................................................................................................ 581
17.4.4 Alarm Function..................................................................................................... 582
17.5 Usage Notes ....................................................................................................................... 583
17.5.1 Register Writing during RTC Count..................................................................... 583
17.5.2 Use of Realtime Clock (RTC) Periodic Interrupts................................................ 583
17.5.3 Transition to Standby Mode after Setting Register............................................... 583
17.5.4 Crystal Oscillator Circuit ...................................................................................... 584
Section 18 Serial Communication Interface with FIFO (SCIF).......................... 585
18.1 Features.............................................................................................................................. 585
18.2 Input/Output Pins............................................................................................................... 588
18.3 Register Descriptions......................................................................................................... 589
18.3.1 Receive Shift Register (SCRSR) .......................................................................... 590
18.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 590
18.3.3 Transmit Shift Register (SCTSR) ......................................................................... 590
18.3.4 Transmit FIFO Data Register (SCFTDR)............................................................. 590
18.3.5 Serial Mode Register (SCSMR)............................................................................ 591
18.3.6 Serial Control Register (SCSCR).......................................................................... 595
18.3.7 FIFO Error Count Register (SCFER) ................................................................... 599
18.3.8 Serial Status Register (SCSSR) ............................................................................ 600
18.3.9 Bit Rate Register (SCBRR) .................................................................................. 607
18.3.10 FIFO Control Register (SCFCR) .......................................................................... 609
18.3.11 FIFO Data Count Register (SCFDR).................................................................... 612
18.3.12 Transmit Data Stop Register (SCTDSR) .............................................................. 613
18.4 Operation ........................................................................................................................... 613
18.4.1 Asynchronous Mode ............................................................................................. 613
18.4.2 Serial Operation .................................................................................................... 614
18.4.3 Synchronous Mode ............................................................................................... 624
18.4.4 Serial Operation in Synchronous Mode ................................................................ 625
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18.5 Interrupt Sources and DMAC ............................................................................................ 635
18.6 Usage Notes ....................................................................................................................... 637
Section 19 Infrared Data Association Module (IrDA).........................................639
19.1 Features.............................................................................................................................. 639
19.2 Input/Output Pins ............................................................................................................... 640
19.3 Register Description........................................................................................................... 640
19.3.1 IrDA Mode Register (SCIMR) ............................................................................. 640
19.4 Operation ........................................................................................................................... 642
19.4.1 Transmitting.......................................................................................................... 642
19.4.2 Receiving .............................................................................................................. 642
19.4.3 Data Format Specification .................................................................................... 643
Section 20 I2C Bus Interface (IIC) .......................................................................645
20.1 Features.............................................................................................................................. 645
20.2 Input/Output Pins ............................................................................................................... 648
20.3 Register Descriptions ......................................................................................................... 648
20.3.1 I2C Bus Control Register 1 (ICCR1)..................................................................... 649
20.3.2 I2C Bus Control Register 2 (ICCR2)..................................................................... 650
20.3.3 I2C Bus Mode Register (ICMR)............................................................................ 651
20.3.4 I2C Bus Interrupt Enable Register (ICIER) ........................................................... 653
20.3.5 I2C Bus Status Register (ICSR)............................................................................. 655
20.3.6 Slave Address Register (SAR).............................................................................. 657
20.3.7 I2C Bus Transmit Data Register (ICDRT)............................................................. 658
20.3.8 I2C Bus Receive Data Register (ICDRR).............................................................. 658
20.3.9 I2C Bus Shift Register (ICDRS)............................................................................ 658
20.3.10 I2C Bus Master Transfer Clock Select Register (ICCKS)..................................... 658
20.4 Operation ........................................................................................................................... 660
20.4.1 I2C Bus Format...................................................................................................... 660
20.4.2 Master Transmit Operation ................................................................................... 661
20.4.3 Master Receive Operation..................................................................................... 663
20.4.4 Slave Transmit Operation ..................................................................................... 665
20.4.5 Slave Receive Operation....................................................................................... 667
20.4.6 Noise Canceller..................................................................................................... 670
20.4.7 Example of Use..................................................................................................... 670
20.5 Interrupt Request................................................................................................................ 675
20.6 Bit Synchronous Circuit..................................................................................................... 676
20.7 Usage Notes ....................................................................................................................... 677
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Section 21 Serial I/O with FIFO (SIOF) ............................................................. 679
21.1 Features.............................................................................................................................. 679
21.2 Input/Output Pins............................................................................................................... 681
21.3 Register Descriptions......................................................................................................... 682
21.3.1 Mode Register (SIMDR) ...................................................................................... 683
21.3.2 Control Register (SICTR)..................................................................................... 686
21.3.3 Transmit Data Register (SITDR) .......................................................................... 689
21.3.4 Receive Data Register (SIRDR) ........................................................................... 690
21.3.5 Transmit Control Data Register (SITCR) ............................................................. 691
21.3.6 Receive Control Data Register (SIRCR) .............................................................. 692
21.3.7 Status Register (SISTR)........................................................................................ 693
21.3.8 Interrupt Enable Register (SIIER) ........................................................................ 699
21.3.9 FIFO Control Register (SIFCTR) ......................................................................... 701
21.3.10 Clock Select Register (SISCR) ............................................................................. 703
21.3.11 Transmit Data Assign Register (SITDAR) ........................................................... 704
21.3.12 Receive Data Assign Register (SIRDAR) ............................................................ 706
21.3.13 Control Data Assign Register (SICDAR) ............................................................. 707
21.4 Operation ........................................................................................................................... 709
21.4.1 Serial Clocks......................................................................................................... 709
21.4.2 Serial Timing ........................................................................................................ 711
21.4.3 Transfer Data Format............................................................................................ 713
21.4.4 Register Allocation of Transfer Data .................................................................... 715
21.4.5 Control Data Interface .......................................................................................... 717
21.4.6 FIFO...................................................................................................................... 719
21.4.7 Transmit and Receive Procedures......................................................................... 721
21.4.8 Interrupts............................................................................................................... 727
21.4.9 Transmit and Receive Timing............................................................................... 729
21.5 Usage Notes ....................................................................................................................... 734
21.5.1 Regarding SYNC Signal High Width when Restarting Transmission
in Master Mode 2.................................................................................................. 734
Section 22 Analog Front End Interface (AFEIF) ................................................ 735
22.1 Features.............................................................................................................................. 735
22.2 Input/Output Pins............................................................................................................... 736
22.3 Register Configuration....................................................................................................... 736
22.3.1 AFEIF Control Register 1 and 2 (ACTR1, ACTR2) ............................................ 737
22.3.2 Make Ratio Count Register (MRCR) ................................................................... 740
22.3.3 Minimum Pause Count Register (MPCR) ............................................................ 740
22.3.4 AFEIF Status Register 1 and 2 (ASTR1, ASTR2)................................................ 740
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22.3.5 Dial Pulse Number Queue (DPNQ) ...................................................................... 745
22.3.6 Ringing Pulse Counter (RCNT)............................................................................ 746
22.3.7 AFE Control Data Register (ACDR) .................................................................... 746
22.3.8 AFE Status Data Register (ASDR) ....................................................................... 746
22.3.9 Transmit Data FIFO Port (TDFP)......................................................................... 747
22.3.10 Receive Data FIFO Port (RDFP) .......................................................................... 747
22.4 Operation ........................................................................................................................... 748
22.4.1 Interrupt Timing.................................................................................................... 748
22.4.2 AFE Interface........................................................................................................ 750
22.4.3 DAA Interface....................................................................................................... 752
22.4.4 Wake up Ringing Interrupt ................................................................................... 754
Section 23 USB Pin Multiplex Controller ...........................................................755
23.1 Features.............................................................................................................................. 755
23.2 Input/Output Pins ............................................................................................................... 756
23.3 Register Descriptions ......................................................................................................... 758
23.3.1 USB Transceiver Control Register (UTRCTL) .................................................... 758
23.4 Examples of External Circuit............................................................................................. 759
23.4.1 Example of the Connection between USB Function Controller and Transceiver. 759
23.4.2 Example of the Connection between USB Host Controller and Transceiver........ 761
23.5 Usage Notes ....................................................................................................................... 763
23.5.1 About the USB Transceiver .................................................................................. 763
23.5.2 About the Examples of External Circuit ............................................................... 763
Section 24 USB Host Controller (USBH) ...........................................................765
24.1 Features.............................................................................................................................. 765
24.2 Input/Output Pins ............................................................................................................... 766
24.3 Register Descriptions ......................................................................................................... 767
24.3.1 Hc Revision Register (USBHR) ........................................................................... 768
24.3.2 Hc Control Register (USBHC) ............................................................................. 768
24.3.3 Hc Command Status Register (USBHCS) ............................................................ 771
24.3.4 Hc Interrupt Status Register (USBHIS) ................................................................ 774
24.3.5 Hc Interrupt Enable Register (USBHIE) .............................................................. 776
24.3.6 Hc Interrupt Disable Register (USBHID) ............................................................. 777
24.3.7 HCCA Register (USBHHCCA)............................................................................ 779
24.3.8 Hc Period Current ED Register (USBHPCED) .................................................... 779
24.3.9 Hc Control Head ED Register (USBHCHED)...................................................... 780
24.3.10 Hc Control Current ED Register (USBHCCED) .................................................. 780
24.3.11 Hc Bulk Head ED Register (USBHBHED) .......................................................... 780
24.3.12 Hc Bulk Current ED Register (USBHBCED) ...................................................... 781
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24.4
24.5
24.6
24.7
24.3.13 Hc Done Head ED Register (USBHDHED)......................................................... 781
24.3.14 Hc Fm Interval Register (USBHFI)...................................................................... 781
24.3.15 Hc Frame Remaining Register (USBHFR)........................................................... 783
24.3.16 Hc Fm Number b Register (USBHFN)................................................................. 784
24.3.17 Hc Periodic Start Register (USBHPS) .................................................................. 785
24.3.18 Hc LS Threshold Register (USBHLST) ............................................................... 786
24.3.19 Hc Rh Descriptor A Register (USBHRDA) ......................................................... 787
24.3.20 Hc Rh Descriptor B Register (USBHRDB).......................................................... 789
24.3.21 Hc Rh Status Register (USBHRS)........................................................................ 790
24.3.22 Hc Rh Port Status 1 and Hc Rh Port Status 2 Registers
(USBHRPS1, USBHRPS2) .................................................................................. 792
Data Storage Format which Required by USB Host Controller ........................................ 798
24.4.1 Storage Format of the Transferred Data ............................................................... 798
24.4.2 Storage Format of the Descriptor.......................................................................... 799
Data Alignment Restriction of USB Host Controller......................................................... 799
24.5.1 Restriction on the Line Boundary of the Synchronous DRAM ............................ 799
24.5.2 Restriction on the Memory Access Address ......................................................... 800
Accessing External Address from the USB Host............................................................... 800
Usage Notes ....................................................................................................................... 801
Section 25 USB Function Controller (USBF) ..................................................... 803
25.1 Features.............................................................................................................................. 803
25.2 Input/Output Pins............................................................................................................... 805
25.3 Register Descriptions......................................................................................................... 806
25.3.1 Interrupt Flag Register 0 (IFR0) ........................................................................... 808
25.3.2 Interrupt Flag Register 1 (IFR1) ........................................................................... 810
25.3.3 Interrupt Flag Register 2 (IFR2) ........................................................................... 811
25.3.4 Interrupt Flag Register 3 (IFR3) ........................................................................... 813
25.3.5 Interrupt Flag Register 4 (IFR4) ........................................................................... 815
25.3.6 Interrupt Select Register 0 (ISR0)......................................................................... 816
25.3.7 Interrupt Select Register 1 (ISR1)......................................................................... 816
25.3.8 Interrupt Select Register 2 (ISR2)......................................................................... 817
25.3.9 Interrupt Select Register 3 (ISR3)......................................................................... 817
25.3.10 Interrupt Select Register 4 (ISR4)......................................................................... 818
25.3.11 Interrupt Enable Register 0 (IER0) ....................................................................... 818
25.3.12 Interrupt Enable Register 1 (IER1) ....................................................................... 819
25.3.13 Interrupt Enable Register 2 (IER2) ....................................................................... 819
25.3.14 Interrupt Enable Register 3 (IER3) ....................................................................... 820
25.3.15 Interrupt Enable Register 4 (IER4) ....................................................................... 820
25.3.16 EP0i Data Register (EPDR0i)............................................................................... 821
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25.4
25.5
25.6
25.7
25.8
25.3.17 EP0o Data Register (EPDR0o) ............................................................................. 821
25.3.18 EP0s Data Register (EPDR0s) .............................................................................. 821
25.3.19 EP1 Data Register (EPDR1) ................................................................................. 822
25.3.20 EP2 Data Register (EPDR2) ................................................................................. 822
25.3.21 EP3 Data Register (EPDR3) ................................................................................. 822
25.3.22 EP4 Data Register (EPDR4) ................................................................................. 823
25.3.23 EP5 Data Register (EPDR5) ................................................................................. 823
25.3.24 EP0o Receive Data Size Register (EPSZ0o) ........................................................ 823
25.3.25 EP1 Receive Data Size Register (EPSZ1) ............................................................ 824
25.3.26 EP4 Receive Data Size Register (EPSZ4) ............................................................ 824
25.3.27 Trigger Register (TRG)......................................................................................... 824
25.3.28 Data Status Register (DASTS).............................................................................. 825
25.3.29 FIFO Clear Register 0 (FCLR0) ........................................................................... 825
25.3.30 FIFO Clear Register 1 (FCLR1) ........................................................................... 826
25.3.31 DMA Transfer Setting Register (DMA) ............................................................... 826
25.3.32 Endpoint Stall Register 0 (EPSTL0)..................................................................... 827
25.3.33 Endpoint Stall Register 1 (EPSTL1)..................................................................... 828
25.3.34 Configuration Value Register (CVR) ................................................................... 828
25.3.35 Time Stamp Register (TSRH/TSRL).................................................................... 829
25.3.36 Control Register 0 (CTLR0) ................................................................................. 830
25.3.37 Control Register 1 (CTLR1) ................................................................................. 831
25.3.38 Endpoint Information Register (EPIR) ................................................................. 831
25.3.39 Timer Register (TMRH/TMRL) ........................................................................... 836
25.3.40 Set Time Out Register (STOH/STOL).................................................................. 836
Operation ........................................................................................................................... 837
25.4.1 Cable Connection.................................................................................................. 837
25.4.2 Cable Disconnection ............................................................................................. 838
25.4.3 Control Transfer.................................................................................................... 839
25.4.4 EP1 Bulk-Out Transfer (Dual FIFOs)................................................................... 845
25.4.5 EP2 Bulk-In Transfer (Dual FIFOs) ..................................................................... 846
25.4.6 EP3 Interrupt-In Transfer...................................................................................... 848
EP4 Isochronous-Out Transfer........................................................................................... 849
EP5 Isochronous-In Transfer ............................................................................................. 852
Processing of USB Standard Commands and Class/Vendor Commands........................... 855
25.7.1 Processing of Commands Transmitted by Control Transfer ................................. 855
Stall Operations.................................................................................................................. 856
25.8.1 Overview............................................................................................................... 856
25.8.2 Forcible Stall by Application ................................................................................ 856
25.8.3 Automatic Stall by USB Function Controller ....................................................... 858
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25.9 Usage Notes ....................................................................................................................... 859
25.9.1 Setup Data Reception ........................................................................................... 859
25.9.2 FIFO Clear............................................................................................................ 859
25.9.3 Overreading/Overwriting of Data Register........................................................... 859
25.9.4 Assigning EP0 Interrupt Sources .......................................................................... 860
25.9.5 FIFO Clear when DMA Transfer is Set ................................................................ 860
25.9.6 Note on Using TR Interrupt .................................................................................. 860
25.9.7 Note on Clock Frequency ..................................................................................... 861
Section 26 LCD Controller (LCDC) ................................................................... 863
26.1 Features.............................................................................................................................. 863
26.2 Input/Output Pins............................................................................................................... 865
26.3 Register Configuration....................................................................................................... 866
26.3.1 LCDC Input Clock Register (LDICKR) ............................................................... 867
26.3.2 LCDC Module Type Register (LDMTR) ............................................................. 868
26.3.3 LCDC Data Format Register (LDDFR)................................................................ 871
26.3.4 LCDC Scan Mode Register (LDSMR) ................................................................. 873
26.3.5 LCDC Start Address Register for Upper Display Data Fetch (LDSARU) ........... 875
26.3.6 LCDC Start Address Register for Lower Display Data Fetch (LDSARL) ........... 876
26.3.7 LCDC Line Address Offset Register for Display Data Fetch (LDLAOR) ........... 877
26.3.8 LCDC Palette Control Register (LDPALCR)....................................................... 878
26.3.9 Palette Data Registers 00 to FF (LDPR00 to LDPRFF) ....................................... 879
26.3.10 LCDC Horizontal Character Number Register (LDHCNR) ................................. 880
26.3.11 LCDC Horizontal Sync Signal Register (LDHSYNR)......................................... 881
26.3.12 LCDC Vertical Display Line Number Register (LDVDLNR) ............................. 882
26.3.13 LCDC Vertical Total Line Number Register (LDVTLNR).................................. 883
26.3.14 LCDC Vertical Sync Signal Register (LDVSYNR) ............................................. 884
26.3.15 LCDC AC Modulation Signal Toggle Line Number Register (LDACLNR) ....... 885
26.3.16 LCDC Interrupt Control Register (LDINTR) ....................................................... 886
26.3.17 LCDC Power Management Mode Register (LDPMMR) ..................................... 889
26.3.18 LCDC Power-Supply Sequence Period Register (LDPSPR)................................ 891
26.3.19 LCDC Control Register (LDCNTR)..................................................................... 892
26.3.20 LCDC User Specified Interrupt Control Register (LDUINTR)............................ 893
26.3.21 LCDC User Specified Interrupt Line Number Register (LDUINTLNR) ............. 895
26.3.22 LCDC Memory Access Interval Number Register (LDLIRNR) .......................... 896
26.4 Operation ........................................................................................................................... 897
26.4.1 LCD Module Sizes which can be Displayed in this LCDC .................................. 897
26.4.2 Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (SDRAM) ...................................................................... 898
26.4.3 Color Palette Specification ................................................................................... 905
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26.4.4 Data Format .......................................................................................................... 907
26.4.5 Setting the Display Resolution.............................................................................. 910
26.4.6 Power Management Registers............................................................................... 910
26.4.7 Operation for Hardware Rotation ......................................................................... 915
26.5 Clock and LCD Data Signal Examples.............................................................................. 918
26.6 Usage Notes ....................................................................................................................... 928
26.6.1 Procedure for Halting Access to Display Data Storage VRAM
(Synchronous DRAM in Area 3) .......................................................................... 928
Section 27 A/D Converter....................................................................................929
27.1 Features.............................................................................................................................. 929
27.2 Input Pins ........................................................................................................................... 931
27.3 Register Descriptions ......................................................................................................... 932
27.3.1 A/D Data Registers A to D (ADDRA to ADDRD) .............................................. 932
27.3.2 A/D Control/Status Registers (ADCSR)............................................................... 933
27.4 Operation ........................................................................................................................... 936
27.4.1 Single Mode.......................................................................................................... 936
27.4.2 Multi Mode ........................................................................................................... 938
27.4.3 Scan Mode ............................................................................................................ 940
27.4.4 Input Sampling and A/D Conversion Time .......................................................... 942
27.4.5 External Trigger Input Timing.............................................................................. 943
27.5 Interrupts............................................................................................................................ 944
27.6 Definitions of A/D Conversion Accuracy.......................................................................... 944
27.7 Usage Notes ....................................................................................................................... 946
27.7.1 Notes on A/D Conversion..................................................................................... 946
27.7.2 Notes on A/D Conversion-End Interrupt and DMA Transfer............................... 948
27.7.3 Allowable Signal-Source Impedance.................................................................... 948
27.7.4 Influence to Absolute Accuracy............................................................................ 949
27.7.5 Setting Analog Input Voltage ............................................................................... 949
27.7.6 Notes on Board Design ......................................................................................... 949
27.7.7 Notes on Countermeasures to Noise ..................................................................... 950
Section 28 D/A Converter (DAC)........................................................................953
28.1 Features.............................................................................................................................. 953
28.2 Input/Output Pins ............................................................................................................... 954
28.3 Register Descriptions ......................................................................................................... 954
28.3.1 D/A Data Registers 0 and 1 (DADR0, DADR1) .................................................. 954
28.3.2 D/A Control Register (DACR) ............................................................................. 955
28.4 Operation ........................................................................................................................... 956
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Section 29 PC Card Controller (PCC)................................................................. 957
29.1 Features.............................................................................................................................. 957
29.1.1 PCMCIA Support ................................................................................................. 959
29.2 Input/Output Pins............................................................................................................... 962
29.3 Register Descriptions......................................................................................................... 963
29.3.1 Area 6 Interface Status Register (PCC0ISR) ........................................................ 963
29.3.2 Area 6 General Control Register (PCC0GCR) ..................................................... 966
29.3.3 Area 6 Card Status Change Register (PCC0CSCR) ............................................. 969
29.3.4 Area 6 Card Status Change Interrupt Enable Register (PCC0CSCIER)............... 972
29.4 Operation ........................................................................................................................... 976
29.4.1 PC card Connection Specification (Interface Diagram, Pin Correspondence)...... 976
29.4.2 PC Card Interface Timing..................................................................................... 980
29.5 Usage Notes ....................................................................................................................... 985
Section 30 SIM Card Module (SIM) ................................................................... 987
30.1 Features.............................................................................................................................. 987
30.2 Input/Output Pins............................................................................................................... 989
30.3 Register Descriptions......................................................................................................... 989
30.3.1 Serial Mode Register (SCSMR)............................................................................ 990
30.3.2 Bit Rate Register (SCBRR) .................................................................................. 991
30.3.3 Serial Control Register (SCSCR).......................................................................... 992
30.3.4 Transmit Shift Register (SCTSR) ......................................................................... 994
30.3.5 Transmit Data Register (SCTDR)......................................................................... 994
30.3.6 Serial Status Register (SCSSR) ............................................................................ 995
30.3.7 Receive Shift Register (SCRSR) ........................................................................ 1001
30.3.8 Receive Data Register (SCRDR) ........................................................................ 1001
30.3.9 Smart Card Mode Register (SCSCMR) .............................................................. 1002
30.3.10 Serial Control 2 Register (SCSC2R)................................................................... 1003
30.3.11 Guard Extension Register (SCGRD) .................................................................. 1004
30.3.12 Wait Time Register (SCWAIT) .......................................................................... 1004
30.3.13 Sampling Register (SCSMPL)............................................................................ 1005
30.4 Operation ......................................................................................................................... 1006
30.4.1 Overview ............................................................................................................ 1006
30.4.2 Data Format ........................................................................................................ 1007
30.4.3 Register Settings ................................................................................................. 1008
30.4.4 Clocks ................................................................................................................. 1011
30.4.5 Data Transmit/Receive Operation....................................................................... 1012
30.5 Usage Notes ..................................................................................................................... 1020
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Section 31 MultiMediaCard Interface (MMCIF) ..............................................1027
31.1 Features............................................................................................................................ 1027
31.2 Input/Output Pins ............................................................................................................. 1029
31.3 Register Descriptions ....................................................................................................... 1030
31.3.1 Mode Register (MODER)................................................................................... 1031
31.3.2 Command Type Register (CMDTYR)................................................................ 1031
31.3.3 Response Type Register (RSPTYR) ................................................................... 1033
31.3.4 Transfer Byte Number Count Register (TBCR) ................................................. 1036
31.3.5 Transfer Block Number Counter (TBNCR)........................................................ 1037
31.3.6 Command Registers 0 to 5 (CMDR0 to CMDR5).............................................. 1037
31.3.7 Response Registers 0 to 16 and D (RSPR0 to RSPR16 and RSPRD) ................ 1038
31.3.8 Command Start Register (CMDSTRT)............................................................... 1040
31.3.9 Operation Control Register (OPCR) ................................................................... 1041
31.3.10 Command Timeout Control Register (CTOCR) ................................................. 1043
31.3.11 Data Timeout Register (DTOUTR) .................................................................... 1044
31.3.12 Card Status Register (CSTR) .............................................................................. 1045
31.3.13 Interrupt Control Registers 0 and 1 (INTCR0 and INTCR1).............................. 1047
31.3.14 Interrupt Status Registers 0 and 1 (INTSTR0 and INTSTR1) ............................ 1049
31.3.15 Transfer Clock Control Register (CLKON)........................................................ 1053
31.3.16 VDD/Open-Drain Control Register (VDCNT)................................................... 1054
31.3.17 Data Register (DR) ............................................................................................. 1054
31.3.18 FIFO Pointer Clear Register (FIFOCLR) ........................................................... 1055
31.3.19 DMA Control Register (DMACR) ..................................................................... 1055
31.3.20 Interrupt Control Register 2 (INTCR2)............................................................... 1056
31.3.21 Interrupt Status Register 2 (INTSTR2)............................................................... 1057
31.4 Operation ......................................................................................................................... 1058
31.4.1 Operations in MMC Mode.................................................................................. 1058
31.5 Operations Using DMAC................................................................................................. 1088
31.5.1 Operation of Read Sequence............................................................................... 1088
31.5.2 Operation of Write Sequence.............................................................................. 1098
31.6 MMCIF Interrupt Sources................................................................................................ 1108
Section 32 SSL Accelerator (SSL) ....................................................................1109
Section 33 User Break Controller (UBC) ..........................................................1111
33.1 Features............................................................................................................................ 1111
33.2 Register Descriptions ....................................................................................................... 1113
33.2.1 Break Address Register A (BARA) .................................................................... 1113
33.2.2 Break Address Mask Register A (BAMRA)....................................................... 1114
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33.2.3 Break Bus Cycle Register A (BBRA)................................................................. 1114
33.2.4 Break Address Register B (BARB) .................................................................... 1116
33.2.5 Break Address Mask Register B (BAMRB) ....................................................... 1117
33.2.6 Break Data Register B (BDRB).......................................................................... 1117
33.2.7 Break Data Mask Register B (BDMRB)............................................................. 1118
33.2.8 Break Bus Cycle Register B (BBRB) ................................................................. 1119
33.2.9 Break Control Register (BRCR) ......................................................................... 1120
33.2.10 Execution Times Break Register (BETR)........................................................... 1124
33.2.11 Branch Source Register (BRSR)......................................................................... 1124
33.2.12 Branch Destination Register (BRDR)................................................................. 1125
33.2.13 Break ASID Register A (BASRA) ..................................................................... 1125
33.2.14 Break ASID Register B (BASRB)...................................................................... 1126
33.3 Operation ......................................................................................................................... 1127
33.3.1 Flow of the User Break Operation ...................................................................... 1127
33.3.2 Break on Instruction Fetch Cycle ....................................................................... 1128
33.3.3 Break on Data Access Cycle............................................................................... 1129
33.3.4 Break on X/Y-Memory Bus Cycle ..................................................................... 1130
33.3.5 Sequential Break................................................................................................. 1131
33.3.6 Value of Saved Program Counter ....................................................................... 1131
33.3.7 PC Trace ............................................................................................................. 1132
33.3.8 Usage Examples.................................................................................................. 1133
33.4 Usage Notes ..................................................................................................................... 1138
Section 34 Pin Function Controller (PFC) ........................................................ 1141
34.1 Register Descriptions....................................................................................................... 1146
34.1.1 Port A Control Register (PACR) ........................................................................ 1147
34.1.2 Port B Control Register (PBCR)......................................................................... 1148
34.1.3 Port C Control Register (PCCR)......................................................................... 1150
34.1.4 Port D Control Register (PDCR) ........................................................................ 1151
34.1.5 Port E Control Register (PECR) ......................................................................... 1153
34.1.6 Port F Control Register (PFCR).......................................................................... 1154
34.1.7 Port G Control Register (PGCR) ........................................................................ 1156
34.1.8 Port H Control Register (PHCR) ........................................................................ 1157
34.1.9 Port J Control Register (PJCR) ........................................................................... 1159
34.1.10 Port K Control Register (PKCR) ........................................................................ 1160
34.1.11 Port L Control Register (PLCR) ......................................................................... 1161
34.1.12 Port M Control Register (PMCR) ....................................................................... 1162
34.1.13 Port P Control Register (PPCR).......................................................................... 1164
34.1.14 Port R Control Register (PRCR)......................................................................... 1165
34.1.15 Port S Control Register (PSCR).......................................................................... 1167
Rev. 3.00 Jan. 18, 2008 Page xxx of lxii
34.1.16 Port T Control Register (PTCR) ......................................................................... 1168
34.1.17 Port U Control Register (PUCR) ........................................................................ 1169
34.1.18 Port V Control Register (PVCR) ........................................................................ 1170
34.1.19 Pin Select Register A (PSELA) .......................................................................... 1171
34.1.20 Pin Select Register B (PSELB)........................................................................... 1173
34.1.21 Pin Select Register C (PSELC)........................................................................... 1174
34.1.22 Pin Select Register D (PSELD) .......................................................................... 1176
34.1.23 USB Transceiver Control Register (UTRCTL) .................................................. 1178
Section 35 I/O Ports ...........................................................................................1179
35.1 Port A............................................................................................................................... 1179
35.1.1 Register Description ........................................................................................... 1179
35.1.2 Port A Data Register (PADR)............................................................................. 1180
35.2 Port B ............................................................................................................................... 1181
35.2.1 Register Description ........................................................................................... 1181
35.2.2 Port B Data Register (PBDR) ............................................................................. 1182
35.3 Port C ............................................................................................................................... 1183
35.3.1 Register Description ........................................................................................... 1183
35.3.2 Port C Data Register (PCDR) ............................................................................. 1184
35.4 Port D............................................................................................................................... 1185
35.4.1 Register Description ........................................................................................... 1185
35.4.2 Port D Data Register (PDDR)............................................................................. 1186
35.5 Port E ............................................................................................................................... 1187
35.5.1 Register Description ........................................................................................... 1187
35.5.2 Port E Data Register (PEDR).............................................................................. 1188
35.6 Port F ............................................................................................................................... 1190
35.6.1 Register Description ........................................................................................... 1190
35.6.2 Port F Data Register (PFDR) .............................................................................. 1191
35.7 Port G............................................................................................................................... 1193
35.7.1 Register Description ........................................................................................... 1193
35.7.2 Port G Data Register (PGDR)............................................................................. 1194
35.8 Port H............................................................................................................................... 1195
35.8.1 Register Description ........................................................................................... 1195
35.8.2 Port H Data Register (PHDR)............................................................................. 1196
35.9 Port J ................................................................................................................................ 1197
35.9.1 Register Description ........................................................................................... 1197
35.9.2 Port J Data Register (PJDR) ............................................................................... 1198
35.10 Port K............................................................................................................................... 1199
35.10.1 Register Description ........................................................................................... 1199
35.10.2 Port K Data Register (PKDR)............................................................................. 1200
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35.11 Port L ............................................................................................................................... 1201
35.11.1 Register Description ........................................................................................... 1201
35.11.2 Port L Data Register (PLDR).............................................................................. 1202
35.12 Port M .............................................................................................................................. 1203
35.12.1 Register Description ........................................................................................... 1203
35.12.2 Port M Data Register (PMDR) ........................................................................... 1204
35.13 Port P ............................................................................................................................... 1205
35.13.1 Register Description ........................................................................................... 1205
35.13.2 Port P Data Register (PPDR) .............................................................................. 1206
35.14 Port R ............................................................................................................................... 1207
35.14.1 Register Description ........................................................................................... 1207
35.14.2 Port R Data Register (PRDR) ............................................................................. 1208
35.15 Port S ............................................................................................................................... 1209
35.15.1 Register Description ........................................................................................... 1209
35.15.2 Port S Data Register (PSDR) .............................................................................. 1210
35.16 Port T ............................................................................................................................... 1211
35.16.1 Register Description ........................................................................................... 1211
35.16.2 Port T Data Register (PTDR).............................................................................. 1212
35.17 Port U............................................................................................................................... 1213
35.17.1 Register Description ........................................................................................... 1213
35.17.2 Port U Data Register (PUDR)............................................................................. 1214
35.18 Port V............................................................................................................................... 1215
35.18.1 Register Description ........................................................................................... 1215
35.18.2 Port V Data Register (PVDR)............................................................................. 1216
Section 36 User Debugging Interface (H-UDI)................................................. 1217
36.1 Features............................................................................................................................ 1217
36.2 Input/Output Pins............................................................................................................. 1218
36.3 Register Descriptions....................................................................................................... 1220
36.3.1 Bypass Register (SDBPR) .................................................................................. 1220
36.3.2 Instruction Register (SDIR) ................................................................................ 1220
36.3.3 Shift Register ...................................................................................................... 1221
36.3.4 Boundary Scan Register (SDBSR) ..................................................................... 1221
36.3.5 ID Register (SDID)............................................................................................. 1230
36.4 Operation ......................................................................................................................... 1231
36.4.1 TAP Controller ................................................................................................... 1231
36.4.2 Reset Configuration ............................................................................................ 1232
36.4.3 TDO Output Timing ........................................................................................... 1232
36.4.4 H-UDI Reset ....................................................................................................... 1233
36.4.5 H-UDI Interrupt .................................................................................................. 1233
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36.5 Boundary Scan ................................................................................................................. 1234
36.5.1 Supported Instructions ........................................................................................ 1234
36.5.2 Points for Attention............................................................................................. 1235
36.6 Usage Notes ..................................................................................................................... 1236
36.7 Advanced User Debugger (AUD).................................................................................... 1236
Section 37 List of Registers ...............................................................................1237
37.1 Register Addresses........................................................................................................... 1238
37.2 Register Bits..................................................................................................................... 1255
37.3 Register States in Each Operating Mode ......................................................................... 1289
Section 38 Electrical Characteristics .................................................................1305
38.1
38.2
38.3
38.4
Absolute Maximum Ratings ............................................................................................ 1305
Power-On and Power-Off Order ...................................................................................... 1306
DC Characteristics ........................................................................................................... 1309
AC Characteristics ........................................................................................................... 1314
38.4.1 Clock Timing ...................................................................................................... 1315
38.4.2 Control Signal Timing ........................................................................................ 1319
38.4.3 AC Bus Timing................................................................................................... 1322
38.4.4 Basic Timing....................................................................................................... 1324
38.4.5 Burst ROM Timing............................................................................................. 1331
38.4.6 SDRAM Timing ................................................................................................. 1332
38.4.7 PCMCIA Timing ................................................................................................ 1351
38.4.8 Peripheral Module Signal Timing....................................................................... 1355
38.4.9 16-Bit Timer Pulse Unit (TPU)........................................................................... 1356
38.4.10 RTC Signal Timing............................................................................................. 1357
38.4.11 SCIF Module Signal Timing............................................................................... 1358
38.4.12 I2C Bus Interface Timing .................................................................................... 1360
38.4.13 SIOF Module Signal Timing .............................................................................. 1362
38.4.14 AFEIF Module Signal Timing ............................................................................ 1365
38.4.15 USB Module Signal Timing ............................................................................... 1366
38.4.16 LCDC Module Signal Timing ............................................................................ 1368
38.4.17 SIM Module Signal Timing ................................................................................ 1369
38.4.18 MMCIF Module Signal Timing.......................................................................... 1370
38.4.19 H-UDI Related Pin Timing................................................................................. 1372
38.5 A/D Converter Characteristics ......................................................................................... 1374
38.6 D/A Converter Characteristics ......................................................................................... 1374
38.7 AC Characteristic Test Conditions................................................................................... 1375
Rev. 3.00 Jan. 18, 2008 Page xxxiii of lxii
Appendix
A.
B.
C.
....................................................................................................... 1377
Pin States ......................................................................................................................... 1377
Product Lineup................................................................................................................. 1390
Package Dimensions ........................................................................................................ 1392
Main Revisions and Additions in this Edition................................................... 1395
Index
....................................................................................................... 1451
Rev. 3.00 Jan. 18, 2008 Page xxxiv of lxii
Figures
Section 1 Overview
Figure 1.1 Block Diagram ............................................................................................................ 10
Figure 1.2 Pin Assignments (PLBG0256GA-A (BP-256H/HV))................................................. 11
Figure 1.3 Pin Assignments (PLBG0256KA-A (BP-256C/CV)) ................................................. 12
Section 2 CPU
Figure 2.1
Figure 2.2
Figure 2.3
Figure 2.4
Figure 2.5
Figure 2.6
Figure 2.7
Figure 2.8
Processing State Transitions........................................................................................ 38
Virtual Address to External Memory Space Mapping................................................. 41
Register Configuration in Each Processing Mode....................................................... 44
General Registers ........................................................................................................ 46
System Registers and Program Counter ...................................................................... 47
Control Register Configuration ................................................................................... 51
Data Format on Memory (Big Endian Mode) ............................................................. 52
Data Format on Memory (Little Endian Mode) .......................................................... 53
Section 3 DSP Operating Unit
Figure 3.1 DSP Instruction Format............................................................................................... 82
Figure 3.2 CPU Registers in DSP Mode....................................................................................... 84
Figure 3.3 DSP Register Configuration ........................................................................................ 88
Figure 3.4 DSP Registers and Bus Connections ......................................................................... 101
Figure 3.5 General Registers (DSP Mode) ................................................................................. 104
Figure 3.6 Sample Parallel Instruction Program......................................................................... 119
Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions ....................... 121
Figure 3.8 Data Formats ............................................................................................................. 124
Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow........................................................... 125
Figure 3.10 Operation Sequence Example.................................................................................. 127
Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode ........................................ 128
Figure 3.12 DC Bit Generation Examples in Negative Value Mode .......................................... 129
Figure 3.13 DC Bit Generation Examples in Overflow Mode.................................................... 129
Figure 3.14 ALU Integer Arithmetic Operation Flow ................................................................ 131
Figure 3.15 ALU Logical Operation Flow ................................................................................. 133
Figure 3.16 Fixed-Point Multiply Operation Flow ..................................................................... 135
Figure 3.17 Arithmetic Shift Operation Flow............................................................................. 137
Figure 3.18 Logical Shift Operation Flow.................................................................................. 139
Figure 3.19 PDMSB Operation Flow ......................................................................................... 141
Figure 3.20 Rounding Operation Flow ....................................................................................... 145
Figure 3.21 Definition of Rounding Operation........................................................................... 145
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Figure 3.22 Local Data Move Instruction Flow.......................................................................... 147
Section 4 Memory Management Unit (MMU)
Figure 4.1 MMU Functions ........................................................................................................ 167
Figure 4.2 Virtual Address Space (MMUCR.AT = 1)................................................................ 169
Figure 4.3 Virtual Address Space (MMUCR.AT = 0)................................................................ 170
Figure 4.4 P4 Area...................................................................................................................... 171
Figure 4.5 Physical Address Space............................................................................................. 172
Figure 4.6 Overall Configuration of the TLB............................................................................. 177
Figure 4.7 Virtual address and TLB Structure............................................................................ 178
Figure 4.8 TLB Indexing (IX = 1) .............................................................................................. 179
Figure 4.9 TLB Indexing (IX = 0) .............................................................................................. 180
Figure 4.10 Objects of Address Comparison.............................................................................. 181
Figure 4.11 Operation of LDTLB Instruction............................................................................. 185
Figure 4.12 Synonym Problem (32-kbyte Cache) ...................................................................... 187
Figure 4.13 MMU Exception Generation Flowchart .................................................................. 193
Figure 4.14 Specifying Address and Data for Memory-Mapped TLB Access ........................... 195
Section 5 Cache
Figure 5.1
Figure 5.2
Figure 5.3
Figure 5.4
Cache Structure ......................................................................................................... 198
Cache Search Scheme ............................................................................................... 206
Write-Back Buffer Configuration.............................................................................. 208
Specifying Address and Data for Memory-Mapped Cache Access
(16-kbyte mode) ........................................................................................................ 211
Section 7 Exception Handling
Figure 7.1 Register Bit Configuration ........................................................................................ 218
Section 8 Interrupt Controller (INTC)
Figure 8.1 Block Diagram of INTC............................................................................................ 244
Figure 8.2 Example of IRL Interrupt Connection....................................................................... 267
Figure 8.3 Interrupt Operation Flowchart................................................................................... 277
Section 9 Bus State Controller (BSC)
Figure 9.1
Figure 9.2
Figure 9.3
Figure 9.4
Block Diagram of BSC ............................................................................................. 282
Address Space ........................................................................................................... 286
Normal Space Basic Access Timing (Access Wait 0)............................................... 337
Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0) ...................................... 339
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Figure 9.5 Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0) ...................................... 340
Figure 9.6 Example of 32-Bit Data-Width SRAM Connection .................................................. 341
Figure 9.7 Example of 16-Bit Data-Width SRAM Connection .................................................. 342
Figure 9.8 Example of 8-Bit Data-Width SRAM Connection.................................................... 342
Figure 9.9 Wait Timing for Normal Space Access (Software Wait Only) ................................. 343
Figure 9.10 Wait State Timing for Normal Space Access
(Wait State Insertion using WAIT Signal) .............................................................. 344
Figure 9.11 CSn Assert Period Expansion.................................................................................. 345
Figure 9.12 Example of 32-Bit Data-Width SDRAM Connection ............................................. 347
Figure 9.13 Example of 16-Bit Data-Width SDRAM Connection ............................................. 348
Figure 9.14 Burst Read Basic Timing (Auto-Precharge)............................................................ 361
Figure 9.15 Burst Read Wait Specification Timing (Auto-Precharge)....................................... 362
Figure 9.16 Basic Timing for Single Read (Auto-Precharge)..................................................... 363
Figure 9.17 Basic Timing for Burst Write (Auto-Precharge) ..................................................... 365
Figure 9.18 Basic Timing for Single Write (Auto-Precharge).................................................... 366
Figure 9.19 Burst Read Timing (No Auto-Precharge)................................................................ 368
Figure 9.20 Burst Read Timing (Bank Active, Same Row Address) ......................................... 369
Figure 9.21 Burst Read Timing (Bank Active, Different Row Addresses) ................................ 370
Figure 9.22 Single Write Timing (No Auto-Precharge) ............................................................. 371
Figure 9.23 Single Write Timing (Bank Active, Same Row Address) ....................................... 372
Figure 9.24 Single Write Timing (Bank Active, Different Row Addresses) .............................. 373
Figure 9.25 Auto-Refresh Timing .............................................................................................. 375
Figure 9.26 Self-Refresh Timing ................................................................................................ 376
Figure 9.27 Access Timing in Power-Down Mode .................................................................... 378
Figure 9.28 Write Timing for SDRAM Mode Register (Based on JEDEC)............................... 381
Figure 9.29 EMRS Command Issue Timing............................................................................... 384
Figure 9.30 Transition Timing in Deep Power-Down Mode...................................................... 385
Figure 9.31 Burst ROM (Clock Asynchronous) Access
(Bus Width = 32 Bits, 16-byte Transfer (Number of Bursts = 4),
Access Wait for First Time = 2, Access Wait for 2nd Time and after = 1) ............. 387
Figure 9.32 Basic Access Timing for Byte-Selection SRAM (BAS = 0) ................................... 388
Figure 9.33 Basic Access Timing for Byte-Selection SRAM (BAS = 1) ................................... 389
Figure 9.34 Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)............. 390
Figure 9.35 Example of Connection with 32-Bit Data-Width Byte-Selection SRAM ............... 391
Figure 9.36 Example of Connection with 16-Bit Data-Width Byte-Selection SRAM ............... 391
Figure 9.37 Example of PCMCIA Interface Connection............................................................ 393
Figure 9.38 Basic Access Timing for PCMCIA Memory Card Interface................................... 394
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Figure 9.39 Wait Timing for PCMCIA Memory Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1,
Hardware Wait = 1)................................................................................................. 395
Figure 9.40 Example of PCMCIA Space Assignment
(CS5BWCR.SA[1:0] = B'10, CS6BWCR.SA[1:0] = B'10) .................................... 396
Figure 9.41 Basic Timing for PCMCIA I/O Card Interface ....................................................... 398
Figure 9.42 Wait Timing for PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1,
Hardware Wait = 1)................................................................................................. 399
Figure 9.43 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3) ............................. 399
Figure 9.44 Burst ROM (Clock Synchronous) Access Timing
(Burst Length = 8, Wait Cycles inserted in First Access = 2,
Wait Cycles inserted in Second and Subsequent Accesses = 1).............................. 400
Figure 9.45 Bus Arbitration Timing ........................................................................................... 403
Section 10 Direct Memory Access Controller (DMAC)
Figure 10.1
Figure 10.2
Figure 10.3
Figure 10.4
Figure 10.5
Figure 10.6
Block Diagram of DMAC ....................................................................................... 408
DMA Transfer Flowchart........................................................................................ 425
Round-Robin Mode................................................................................................. 432
Changes in Channel Priority in Round-Robin Mode............................................... 433
Data Flow of Dual Address Mode........................................................................... 435
Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)................................. 436
Figure 10.7 Data Flow in Single Address Mode......................................................................... 437
Figure 10.8 Example of DMA Transfer Timing in Single Address Mode ................................. 438
Figure 10.9 DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)......................................................... 439
Figure 10.10 Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)....................................................... 440
Figure 10.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)....................................................... 440
Figure 10.12 Bus State when Multiple Channels are Operating................................................. 443
Figure 10.13 Example of DREQ Input Detection in Cycle Steal Mode Edge Detection............ 444
Figure 10.14 Example of DREQ Input Detection in Cycle Steal Mode Level Detection........... 445
Figure 10.15 Example of DREQ Input Detection in Burst Mode Edge Detection ..................... 445
Figure 10.16 Example of DREQ Input Detection in Burst Mode Level Detection .................... 446
Figure 10.17 Example of DMA Transfer End in Cycle Steal Mode Level Detection ................ 446
Figure 10.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device) ............................... 447
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Figure 10.19 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted One Extra Time) ........................................ 450
Figure 10.20 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted Normally)................................................... 450
Figure 10.21 Timing of DREQ Input Detection by Level Detection in Cycle Stealing Mode
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted One Extra Time) ........................................ 451
Figure 10.22 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles
and So DREQ Sampling is Accepted Normally)................................................... 452
Section 11 Clock Pulse Generator (CPG)
Figure 11.1 Block Diagram of CPG ........................................................................................... 454
Figure 11.2 Points for Attention when Using Crystal Resonator................................................ 467
Figure 11.3 Points for Attention when Using PLL Oscillator Circuit ........................................ 468
Section 12 Watchdog Timer (WDT)
Figure 12.1 Block Diagram of WDT .......................................................................................... 470
Figure 12.2 Writing to WTCNT and WTCSR............................................................................ 474
Section 13 Power-Down Modes
Figure 13.1
Figure 13.2
Figure 13.3
Figure 13.4
Figure 13.5
Canceling Standby Mode with STBY Bit in STBCR.............................................. 490
STATUS Output at Power-on Reset........................................................................ 492
STATUS Output at Manual Reset ........................................................................... 492
STATUS Output when Software Standby Mode is Canceled by an Interrupt......... 493
STATUS Output When Software Standby Mode is Canceled
by a Power-on Reset................................................................................................ 493
Figure 13.6 STATUS Output When Software Standby Mode is Canceled
by a Manual Reset ................................................................................................... 494
Figure 13.7 STATUS Output when Sleep Mode is Canceled by an Interrupt ............................ 494
Figure 13.8 STATUS Output When Sleep Mode is Canceled by a Power-on Reset.................. 495
Figure 13.9 STATUS Output When Sleep Mode is Canceled by a Manual Reset ..................... 495
Figure 13.10 Hardware Standby Mode Timing (CA is pulled low in normal operation) ........... 497
Figure 13.11 Hardware Standby Mode Timing
(CA is pulled low while WDT operates after the standby mode is canceled) ....... 498
Figure 13.12 Timing When Power of Pins other than VCC_RTC and VCCQ_RTC is Off........... 498
Rev. 3.00 Jan. 18, 2008 Page xxxix of lxii
Section 14 Timer Unit (TMU)
Figure 14.1
Figure 14.2
Figure 14.3
Figure 14.4
Figure 14.5
Figure 14.6
Figure 14.7
Block Diagram of TMU .......................................................................................... 500
Setting Count Operation.......................................................................................... 505
Auto-Reload Count Operation................................................................................. 506
Count Timing when Internal Clock is Operating .................................................... 507
Count Timing when RTC Clock is Operating ......................................................... 507
UNF Set Timing ...................................................................................................... 508
Status Flag Clear Timing......................................................................................... 508
Section 15 16-Bit Timer Pulse Unit (TPU)
Figure 15.1 Block Diagram of TPU............................................................................................ 513
Figure 15.2 Example of Counter Operation Setting Procedure .................................................. 529
Figure 15.3 Free-Running Counter Operation ............................................................................ 530
Figure 15.4 Periodic Counter Operation..................................................................................... 531
Figure 15.5 Example of Setting Procedure for Waveform Output by Compare Match.............. 532
Figure 15.6 Example of 0 Output/1 Output Operation ............................................................... 533
Figure 15.7 Example of Toggle Output Operation ..................................................................... 533
Figure 15.8 Compare Match Buffer Operation........................................................................... 534
Figure 15.9 Example of Buffer Operation Setting Procedure..................................................... 535
Figure 15.10 Example of Buffer Operation ................................................................................ 536
Figure 15.11 Example of PWM Mode Setting Procedure .......................................................... 537
Figure 15.12 Example of PWM Mode Operation (1) ................................................................. 538
Figure 15.13 Examples of PWM Mode Operation (2)................................................................ 538
Figure 15.14 Example of Phase Counting Mode Setting Procedure........................................... 540
Figure 15.15 Example of Phase Counting Mode 1 Operation .................................................... 541
Figure 15.16 Example of Phase Counting Mode 2 Operation .................................................... 542
Figure 15.17 Example of Phase Counting Mode 3 Operation .................................................... 543
Figure 15.18 Example of Phase Counting Mode 4 Operation .................................................... 544
Figure 15.19 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 545
Section 16 Compare Match Timer (CMT)
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Block Diagram of CMT .......................................................................................... 548
Counter Operation (One-Shot Operation) ............................................................... 554
Counter Operation (Free-Running Operation) ........................................................ 555
CMF Set Timing...................................................................................................... 557
Section 17 Realtime Clock (RTC)
Figure 17.1 RTC Block Diagram................................................................................................ 560
Figure 17.2 Setting Time ............................................................................................................ 580
Figure 17.3 Reading Time .......................................................................................................... 581
Rev. 3.00 Jan. 18, 2008 Page xl of lxii
Figure 17.4 Using Alarm Function ............................................................................................. 582
Figure 17.5 Using Periodic Interrupt Function ........................................................................... 583
Figure 17.6 Example of Crystal Oscillator Circuit Connection .................................................. 584
Section 18 Serial Communication Interface with FIFO (SCIF)
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Block Diagram of SCIF........................................................................................... 587
Sample SCIF Initialization Flowchart ..................................................................... 616
Sample Serial Transmission Flowchart ................................................................... 617
Example of Transmit Operation
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 619
Figure 18.5 Example of Transmit Data Stop Function ............................................................... 619
Figure 18.6 Transmit Data Stop Function Flowchart ................................................................. 620
Figure 18.7 Sample Serial Reception Flowchart (1)................................................................... 621
Figure 18.8 Sample Serial Reception Flowchart (2)................................................................... 622
Figure 18.9 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit) .................................................... 623
Figure 18.10 Example of CTS Control Operation ...................................................................... 624
Figure 18.11 Example of RTS Control Operation ...................................................................... 624
Figure 18.12 Data Format in Synchronous Communication ...................................................... 625
Figure 18.13 Sample SCIF Initialization Flowchart (1) (Transmission) .................................... 626
Figure 18.13 Sample SCIF Initialization Flowchart (2) (Reception).......................................... 627
Figure 18.13 Sample SCIF Initialization Flowchart (3)
(Simultaneous Transmission and Reception) ........................................................ 628
Figure 18.14 Sample Serial Transmission Flowchart (1)
(First Transmission after Initialization) ................................................................. 629
Figure 18.14 Sample Serial Transmission Flowchart (2)
(Second and Subsequent Transmission) ................................................................ 630
Figure 18.15 Sample Serial Reception Flowchart (1) (First Reception after Initialization) ....... 631
Figure 18.15 Sample Serial Reception Flowchart (2) (Second and Subsequent Reception) ...... 632
Figure 18.16 Sample Simultaneous Serial Transmission and Reception Flowchart (1)
(First Transfer after Initialization) ......................................................................... 633
Figure 18.16 Sample Simultaneous Serial Transmission and Reception Flowchart (2)
(Second and Subsequent Transfer) ........................................................................ 634
Figure 18.17 Receive Data Sampling Timing in Asynchronous Mode ...................................... 638
Section 19 Infrared Data Association Module (IrDA)
Figure 19.1 Block Diagram of IrDA........................................................................................... 639
Figure 19.2 Transmit/Receive Operation.................................................................................... 643
Rev. 3.00 Jan. 18, 2008 Page xli of lxii
Section 20 I2C Bus Interface (IIC)
Figure 20.1 Block Diagram of I2C Bus Interface ....................................................................... 646
Figure 20.2 External Circuit Connections of I/O Pins ................................................................ 647
Figure 20.3 I2C Bus Formats ...................................................................................................... 660
Figure 20.4 I2C Bus Timing........................................................................................................ 661
Figure 20.5 Master Transmit Mode Operation Timing (1)......................................................... 662
Figure 20.6 Master Transmit Mode Operation Timing (2)......................................................... 663
Figure 20.7 Master Receive Mode Operation Timing (1) .......................................................... 664
Figure 20.8 Master Receive Mode Operation Timing (2) .......................................................... 665
Figure 20.9 Slave Transmit Mode Operation Timing (1) ........................................................... 666
Figure 20.10 Slave Transmit Mode Operation Timing (2) ......................................................... 667
Figure 20.11 Slave Receive Mode Operation Timing (1)........................................................... 668
Figure 20.12 Slave Receive Mode Operation Timing (2)........................................................... 669
Figure 20.13 Block Diagram of Noise Conceller ....................................................................... 670
Figure 20.14 Sample Flowchart for Master Transmit Mode ...................................................... 671
Figure 20.15 Sample Flowchart for Master Receive Mode ........................................................ 672
Figure 20.16 Sample Flowchart for Slave Transmit Mode......................................................... 673
Figure 20.17 Sample Flowchart for Slave Receive Mode .......................................................... 674
Figure 20.18 The Timing of the Bit Synchronous Circuit .......................................................... 676
Section 21 Serial I/O with FIFO (SIOF)
Figure 21.1 Block Diagram of SIOF .......................................................................................... 680
Figure 21.2 Serial Clock Supply................................................................................................. 709
Figure 21.3 Serial Data Synchronization Timing ....................................................................... 711
Figure 21.4 SIOF Transmit/Receive Timing .............................................................................. 712
Figure 21.5 Transmit/Receive Data Bit Alignment .................................................................... 715
Figure 21.6 Control Data Bit Alignment .................................................................................... 716
Figure 21.7 Control Data Interface (Slot Position)..................................................................... 717
Figure 21.8 Control Data Interface (Secondary FS) ................................................................... 718
Figure 21.9 Example of Transmit Operation in Master Mode.................................................... 721
Figure 21.10 Example of Receive Operation in Master Mode ................................................... 722
Figure 21.11 Example of Transmit Operation in Slave Mode .................................................... 723
Figure 21.12 Example of Receive Operation in Slave Mode ..................................................... 724
Figure 21.13 Transmit and Receive Timing (8-Bit Monaural Data (1))..................................... 729
Figure 21.14 Transmit and Receive Timing (8-Bit Monaural Data (2))..................................... 730
Figure 21.15 Transmit and Receive Timing (16-Bit Monaural Data (1))................................... 730
Figure 21.16 Transmit and Receive Timing (16-Bit Stereo Data (1)) ........................................ 731
Figure 21.17 Transmit and Receive Timing (16-Bit Stereo Data (2)) ........................................ 731
Figure 21.18 Transmit and Receive Timing (16-Bit Stereo Data (3)) ........................................ 732
Figure 21.19 Transmit and Receive Timing (16-Bit Stereo Data (4)) ........................................ 732
Rev. 3.00 Jan. 18, 2008 Page xlii of lxii
Figure 21.20 Transmit and Receive Timing (16-Bit Stereo Data).............................................. 733
Figure 21.21 Frame Length (32-Bit)........................................................................................... 734
Section 22 Analog Front End Interface (AFEIF)
Figure 22.1
Figure 22.2
Figure 22.3
Figure 22.4
Figure 22.5
Figure 22.6
Figure 22.7
Figure 22.8
Block Diagram of AFE Interface............................................................................. 735
FIFO Interrupt Timing............................................................................................. 748
Ringing Interrupt Occurrence Timing ..................................................................... 749
Interrupt Generator .................................................................................................. 749
AFE Serial Interface................................................................................................ 750
AFE Control Sequence............................................................................................ 751
DAA Block Diagram............................................................................................... 752
Ringing Detect Sequence ........................................................................................ 753
Section 23 USB Pin Multiplex Controller
Figure 23.1 Block Diagram of USB PIN Multiplexer ................................................................ 755
Figure 23.2 Example 1 of Transceiver Connection for USB Function Controller
(On-Chip Transceiver is Used)................................................................................ 759
Figure 23.3 Example 2 of Transceiver Connection for USB function Controller
(On-Chip Transceiver is not Used).......................................................................... 760
Figure 23.4 Example 1 of Transceiver Connection for USB Host Controller
(On-Chip Transceiver is Used)................................................................................ 762
Figure 23.5 Example 2 of Transceiver Connection for USB Host Controller
(On-Chip Transceiver is not Used).......................................................................... 763
Section 25 USB Function Controller (USBF)
Figure 25.1 Block Diagram of USBF ......................................................................................... 804
Figure 25.2 Example of Endpoint Configuration........................................................................ 835
Figure 25.3 Cable Connection Operation ................................................................................... 837
Figure 25.4 Cable Disconnection Operation............................................................................... 838
Figure 25.5 Transfer Stages in Control Transfer ........................................................................ 839
Figure 25.6 Setup Stage Operation ............................................................................................. 840
Figure 25.7 Data Stage (Control-In) Operation .......................................................................... 841
Figure 25.8 Data Stage (Control-Out) Operation........................................................................ 842
Figure 25.9 Status Stage (Control-In) Operation ........................................................................ 843
Figure 25.10 Status Stage (Control-Out) Operation ................................................................... 844
Figure 25.11 EP1 Bulk-Out Transfer Operation......................................................................... 845
Figure 25.12 EP2 Bulk-In Transfer Operation............................................................................ 846
Figure 25.13 EP3 Interrupt-In Transfer Operation ..................................................................... 848
Figure 25.14 EP4 Isochronous-Out Transfer Operation (SOF is Normal).................................. 849
Figure 25.15 EP4 Isochronous-Out Transfer Operation (SOF is Broken) .................................. 850
Rev. 3.00 Jan. 18, 2008 Page xliii of lxii
Figure 25.16
Figure 25.17
Figure 25.18
Figure 25.19
Figure 25.20
EP5 Isochronous-In Transfer Operation (SOF is Normal) .................................... 852
EP5 Isochronous-In Transfer Operation (SOF in Broken) .................................... 853
Forcible Stall by Application ................................................................................ 857
Automatic Stall by USB Function Controller........................................................ 858
Set Timing of TR Interrupt Flag............................................................................ 861
Section 26 LCD Controller (LCDC)
Figure 26.1 LCDC Block Diagram............................................................................................. 864
Figure 26.2 Valid Display and the Retrace Period ..................................................................... 898
Figure 26.3 Color-Palette Data Format....................................................................................... 905
Figure 26.4 Power-Supply Control Sequence and States of the LCD Module ........................... 911
Figure 26.5 Power-Supply Control Sequence and States of the LCD Module ........................... 911
Figure 26.6 Power-Supply Control Sequence and States of the LCD Module ........................... 912
Figure 26.7 Power-Supply Control Sequence and States of the LCD Module ........................... 912
Figure 26.8 Operation for Hardware Rotation (Normal Mode).................................................. 916
Figure 26.9 Operation for Hardware Rotation (Rotation Mode) ................................................ 917
Figure 26.10 Clock and LCD Data Signal Example................................................................... 918
Figure 26.11 Clock and LCD Data Signal Example
(STN Monochrome 8-Bit Data Bus Module) ........................................................ 918
Figure 26.12 Clock and LCD Data Signal Example (STN Color 4-Bit Data Bus Module)........ 919
Figure 26.13 Clock and LCD Data Signal Example (STN Color 8-Bit Data Bus Module)........ 919
Figure 26.14 Clock and LCD Data Signal Example (STN Color 12-Bit Data Bus Module)...... 920
Figure 26.15 Clock and LCD Data Signal Example (STN Color 16-Bit Data Bus Module)...... 921
Figure 26.16 Clock and LCD Data Signal Example
(DSTN Monochrome 8-Bit Data Bus Module) ..................................................... 922
Figure 26.17 Clock and LCD Data Signal Example
(DSTN Monochrome 16-Bit Data Bus Module) ................................................... 922
Figure 26.18 Clock and LCD Data Signal Example (DSTN Color 8-Bit Data Bus Module)..... 923
Figure 26.19 Clock and LCD Data Signal Example (DSTN Color 12-Bit Data Bus Module)... 923
Figure 26.20 Clock and LCD Data Signal Example (DSTN Color 16-Bit Data Bus Module)... 924
Figure 26.21 Clock and LCD Data Signal Example (TFT Color 16-Bit Data Bus Module) ...... 925
Figure 26.22 Clock and LCD Data Signal Example (8-Bit Interface Color 640 × 480)............. 926
Figure 26.23 Clock and LCD Data Signal Example (16-Bit Interface Color 640 × 480)........... 927
Section 27 A/D Converter
Figure 27.1 Block Diagram of A/D Converter ........................................................................... 930
Figure 27.2 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 937
Figure 27.3 Example of A/D Converter Operation
(Multi Mode, Channels AN0 to AN2 Selected) ...................................................... 939
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Figure 27.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)........................................................ 941
Figure 27.5 A/D Conversion Timing .......................................................................................... 942
Figure 27.6 External Trigger Input Timing ................................................................................ 943
Figure 27.7 Definitions of A/D Conversion Accuracy ............................................................... 945
Figure 27.8 Analog Input Circuit Example................................................................................. 949
Figure 27.9 Example of Analog Input Protection Circuit ........................................................... 950
Figure 27.10 Analog Input Pin Equivalent Circuit ..................................................................... 951
Section 28 D/A Converter (DAC)
Figure 28.1 Block Diagram of D/A Converter ........................................................................... 953
Figure 28.2 D/A Converter Operation Example ......................................................................... 956
Section 29 PC Card Controller (PCC)
Figure 29.1
Figure 29.2
Figure 29.3
Figure 29.4
Figure 29.5
Figure 29.6
Figure 29.7
Figure 29.8
Figure 29.9
PC Card Controller Block Diagram......................................................................... 958
Continuous 32-Mbyte Area Mode........................................................................... 960
Continuous 16-Mbyte Area Mode (Area 6)............................................................. 961
Interface................................................................................................................... 976
PCMCIA Memory Card Interface Basic Timing..................................................... 980
PCMCIA Memory Card Interface Wait Timing...................................................... 981
PCMCIA I/O Card Interface Basic Timing ............................................................. 982
PCMCIA I/O Card Interface Wait Timing .............................................................. 983
Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ............................... 984
Section 30 SIM Card Module (SIM)
Figure 30.1
Figure 30.2
Figure 30.3
Figure 30.4
Figure 30.5
Figure 30.6
Figure 30.7
Figure 30.8
Figure 30.9
Smart Card Interface ............................................................................................... 988
Data Format Used by Smart Card Interface .......................................................... 1007
Examples of Start Character Waveforms .............................................................. 1010
Example of Initialization Flow .............................................................................. 1013
Example of Transmit Processing........................................................................... 1015
Example of Receive Processing ............................................................................ 1017
Receive Data Sampling Timing in Smart Card Mode ........................................... 1020
Retransmission when Smart Card Interface is in Receive Mode........................... 1022
Retransmit Standby Mode (Clock Stopped)
when Smart Card Interface is in Transmit Mode................................................... 1023
Figure 30.10 Procedure for Stopping Clock and Restarting ..................................................... 1024
Figure 30.11 Example of Pin Connections in Smart Card Interface......................................... 1025
Figure 30.12 TEIE Set Timing ................................................................................................. 1026
Rev. 3.00 Jan. 18, 2008 Page xlv of lxii
Section 31 MultiMediaCard Interface (MMCIF)
Figure 31.1 Block Diagram of MMCIF.................................................................................... 1028
Figure 31.2 Example of Command Sequence for Commands
that do not Require Command Response............................................................... 1060
Figure 31.3 Operational Flow for Commands that do not Require Command Response......... 1061
Figure 31.4 Example of Command Sequence for Commands without Data Transfer
(No Data Busy State)............................................................................................. 1063
Figure 31.5 Example of Command Sequence for Commands without Data Transfer
(with Data Busy State)........................................................................................... 1064
Figure 31.6 Operational Flowchart for Commands without Data Transfer .............................. 1065
Figure 31.7 Example of Command Sequence for Commands with Read Data
(Block Size ≤ FIFO Size) ...................................................................................... 1067
Figure 31.8 Example of Command Sequence for Commands with Read Data
(Block Size > FIFO Size) ...................................................................................... 1068
Figure 31.9 Example of Command Sequence for Commands with Read Data
(Multiblock Transfer) ............................................................................................ 1069
Figure 31.10 Example of Command Sequence for Commands with Read Data
(Stream Transfer) ................................................................................................ 1070
Figure 31.11 Operational Flowchart for Commands with Read Data
(Single Block Transfer) ....................................................................................... 1071
Figure 31.12 Operational Flowchart for Commands with Read Data
(Open-ended Multiblock Transfer) (1) ................................................................ 1072
Figure 31.12 Operational Flowchart for Commands with Read Data
(Open-ended Multiblock Transfer) (2) ................................................................ 1073
Figure 31.13 Operational Flowchart for Commands with Read Data
(Pre-defined Multiblock Transfer) (1) ................................................................. 1074
Figure 31.13 Operational Flowchart for Commands with Read Data
(Pre-defined Multiblock Transfer) (2) ................................................................. 1075
Figure 31.14 Operational Flowchart for Commands with Read Data (Stream Transfer) ......... 1076
Figure 31.15 Example of Command Sequence for Commands with Write Data
(Block Size ≤ FIFO Size) .................................................................................... 1078
Figure 31.16 Example of Command Sequence for Commands with Write Data
(Block Size > FIFO Size) .................................................................................... 1079
Figure 31.17 Example of Command Sequence for Commands with Write Data
(Multiblock Transfer) .......................................................................................... 1080
Figure 31.18 Example of Command Sequence for Commands with Write Data
(Stream Transfer) ................................................................................................ 1081
Figure 31.19 Operational Flowchart for Commands with Write Data
(Single Block Transfer) ....................................................................................... 1082
Rev. 3.00 Jan. 18, 2008 Page xlvi of lxii
Figure 31.20 Operational Flowchart for Commands with Write Data
(Open-ended Multiblock Transfer) (1) ................................................................ 1083
Figure 31.20 Operational Flowchart for Commands with Write Data
(Open-ended Multiblock Transfer) (2) ................................................................ 1084
Figure 31.21 Operational Flowchart for Commands with Write Data
(Pre-defined Multiblock Transfer) (1) ................................................................. 1085
Figure 31.21 Operational Flowchart for Commands with Write Data
(Pre-defined Multiblock Transfer) (2) ................................................................. 1086
Figure 31.22 Operational Flowchart for Commands with Write Data (Stream Transfer) ....... 1087
Figure 31.23 Operational Flowchart for Read Sequence (Single Block Transfer) ................... 1090
Figure 31.24 Operational Flowchart for Read Sequence
(Open-ended Multiblock Transfer) (1) ................................................................ 1091
Figure 31.24 Operational Flowchart for Read Sequence
(Open-ended Multiblock Transfer) (2) ................................................................ 1092
Figure 31.25 Operational Flowchart for Read Sequence
(Pre-defined Multiblock Transfer) (1) ................................................................. 1093
Figure 31.25 Operational Flowchart for Read Sequence
(Pre-defined Multiblock Transfer) (2) ................................................................. 1094
Figure 31.26 Operational Flowchart for Rear Sequence (Stream Read Transfer) .................... 1095
Figure 31.27 Operational Flowchart for Pre-defined Multiblock Read Transfer
in Auto Mode (1) ................................................................................................. 1096
Figure 31.27 Operational Flowchart for Pre-defined Multiblock Read Transfer
in Auto Mode (2) ................................................................................................. 1097
Figure 31.28 Operational Flowchart for Write Sequence (Single Block Transfer) .................. 1100
Figure 31.29 Operational Flowchart for Write Sequence
(Open-ended Multiblock Transfer) (1) ................................................................ 1101
Figure 31.29 Operational Flowchart for Write Sequence
(Open-ended Multiblock Transfer) (2) ................................................................ 1102
Figure 31.30 Operational Flowchart for Write Sequence
(Pre-defined Multiblock Transfer) (1) ................................................................. 1103
Figure 31.30 Operational Flowchart for Write Sequence
(Pre-defined Multiblock Transfer) (2) ................................................................. 1104
Figure 31.31 Operational Flowchart for Write Sequence (Stream Write Transfer).................. 1105
Figure 31.32 Operational Flowchart for Pre-defied Multiblock Write Transfer
in Auto Mode (1) ................................................................................................. 1106
Figure 31.32 Operational Flowchart for Pre-defied Multiblock Write Transfer
in Auto Mode (2) ................................................................................................. 1107
Section 33 User Break Controller (UBC)
Figure 33.1 Block Diagram of UBC......................................................................................... 1112
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Section 35 I/O Ports
Figure 35.1 Port A .................................................................................................................... 1179
Figure 35.2 Port B .................................................................................................................... 1181
Figure 35.3 Port C .................................................................................................................... 1183
Figure 35.4 Port D .................................................................................................................... 1185
Figure 35.5 Port E..................................................................................................................... 1187
Figure 35.6 Port F..................................................................................................................... 1190
Figure 35.7 Port G .................................................................................................................... 1193
Figure 35.8 Port H .................................................................................................................... 1195
Figure 35.9 Port J ..................................................................................................................... 1197
Figure 35.10 Port K .................................................................................................................. 1199
Figure 35.11 Port L................................................................................................................... 1201
Figure 35.12 Port M.................................................................................................................. 1203
Figure 35.13 Port P................................................................................................................... 1205
Figure 35.14 Port R .................................................................................................................. 1207
Figure 35.15 Port S................................................................................................................... 1209
Figure 35.16 Port T................................................................................................................... 1211
Figure 35.17 Port U .................................................................................................................. 1213
Figure 35.18 Port V .................................................................................................................. 1215
Section 36 User Debugging Interface (H-UDI)
Figure 36.1
Figure 36.2
Figure 36.3
Figure 36.4
Block Diagram of H-UDI...................................................................................... 1218
TAP Controller State Transitions .......................................................................... 1231
H-UDI Data Transfer Timing................................................................................ 1233
H-UDI Reset.......................................................................................................... 1233
Section 38 Electrical Characteristics
Figure 38.1 EXTAL Clock Input Timing ................................................................................. 1316
Figure 38.2 CKIO Clock Output Timing.................................................................................. 1316
Figure 38.3 CKIO Clock Input Timing .................................................................................... 1316
Figure 38.4 Power-On Oscillation Settling Time ..................................................................... 1317
Figure 38.5 Oscillation Settling Time on Return from Standby (Return by Reset).................. 1317
Figure 38.6 Oscillation Settling Time on Return from Standby (Return by NMI or IRQ)....... 1317
Figure 38.7 PLL Synchronization Settling Time by Reset, NMI or IRQ Interrupts................. 1318
Figure 38.8 Reset Input Timing................................................................................................ 1320
Figure 38.9 Interrupt Signal Input Timing................................................................................ 1320
Figure 38.10 Bus Release Timing ............................................................................................ 1321
Figure 38.11 Pin Drive Timing at Standby............................................................................... 1321
Figure 38.12 Basic Bus Cycle in Normal Space (No Wait)...................................................... 1324
Figure 38.13 Basic Bus Cycle in Normal Space (Software Wait 1) ......................................... 1325
Rev. 3.00 Jan. 18, 2008 Page xlviii of lxii
Figure 38.14 Basic Bus Cycle in Normal Space (External Wait 1 Input)................................. 1326
Figure 38.15 Basic Bus Cycle in Normal Space
(Software Wait 1, External Wait Valid (WM Bit = 0), No Idle Cycle) ............... 1327
Figure 38.16 CS Extended Bus Cycle in Normal Space
(SW = 1 Cycle, HW = 1 Cycle, External Wait 1 Input) ...................................... 1328
Figure 38.17 Bus Cycle of SRAM with Byte Selection
(SW = 1 Cycle, HW = 1 Cycle, External Wait 1 Input,
BAS = 0 (UB and LB in Write Cycle Controlled)) ............................................. 1329
Figure 38.18 Bus Cycle of SRAM with Byte Selection
(SW = 1 Cycle, HW = 1 Cycle, External Wait 1 Input,
BAS = 1 (WE in Write Cycle Controlled)) ......................................................... 1330
Figure 38.19 Read Bus Cycle of Burst ROM
(Software Wait 1, External Wait 1 Input, Burst Wait 1, Number of Burst 2)...... 1331
Figure 38.20 Single Read Bus Cycle of SDRAM
(Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 1 Cycle) ...... 1332
Figure 38.21 Single Read Bus Cycle of SDRAM
(Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycles, TRP = 2 Cycles)... 1333
Figure 38.22 Burst Read Bus Cycle of SDRAM (Single Read × 8)
(Auto Precharge Mode, CAS Latency 2, TRCD = 1 Cycle, TRP = 2 Cycles) .... 1334
Figure 38.23 Burst Read Bus Cycle of SDRAM (Single Read × 8)
(Auto Precharge Mode, CAS Latency 2, TRCD = 2 Cycles, TRP = 1 Cycle) .... 1335
Figure 38.24 Single Write Bus Cycle of SDRAM
(Auto Precharge Mode, TRWL = 1 Cycle).......................................................... 1336
Figure 38.25 Single Write Bus Cycle of SDRAM
(Auto Precharge Mode, TRCD = 3 Cycles, TRWL = 1 Cycle) ........................... 1337
Figure 38.26 Burst Write Bus Cycle of SDRAM (Single Write × 8) (Auto Precharge Mode,
TRCD = 1 Cycle, TRWL = 1 Cycle)................................................................... 1338
Figure 38.27 Burst Write Bus Cycle of SDRAM (Single Write × 8)
(Auto Precharge Mode, TRCD = 2 Cycles, TRWL = 1 Cycle) ........................... 1339
Figure 38.28 Burst Read Bus Cycle of SDRAM (Single Read × 8)
(Bank Active Mode: ACTV + READ Command, CAS Latency 2,
TRCD = 1 Cycle)................................................................................................. 1340
Figure 38.29 Burst Read Bus Cycle of SDRAM (Single Read × 8)
(Bank Active Mode: READ Command, Same Row Address,
CAS Latency 2, TRCD = 1 Cycle) ...................................................................... 1341
Figure 38.30 Burst Read Bus Cycle of SDRAM (Single Read × 8)
(Bank Active Mode: PRE + ACTV + READ Command,
Different Row Address, CAS Latency 2, TRCD = 1 Cycle) ............................... 1342
Figure 38.31 Burst Write Bus Cycle of SDRAM (Single Write × 8)
(Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................. 1343
Rev. 3.00 Jan. 18, 2008 Page xlix of lxii
Figure 38.32 Burst Write Bus Cycle of SDRAM (Single Write × 8)
(Bank Active Mode: ACTV + WRIT Command, TRCD = 1 Cycle) .................. 1344
Figure 38.33 Burst Write Bus Cycle of SDRAM (Single Write × 8)
(Bank Active Mode: PRE + ACTV + WRIT Command, TRCD = 1 Cycle)....... 1345
Figure 38.34 Auto Refresh Timing of SDRAM (TRP = 2 Cycles) .......................................... 1346
Figure 38.35 Self Refresh Timing of SDRAM (TRP = 2 Cycles) ............................................ 1347
Figure 38.36 Power-On Sequence of SDRAM (Mode Write Timing, TRP = 2 Cycles).......... 1348
Figure 38.37 Write to Read Bus Cycle in Power-Down Mode of SDRAM
(Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)... 1349
Figure 38.38 Read to Write Bus Cycle in Power-Down Mode of SDRAM
(Auto Precharge Mode, TRCD = 1 Cycle, TRP = 1 Cycle, TRWL = 1 Cycle)... 1350
Figure 38.39 PCMCIA Memory Card Interface Bus Timing ................................................... 1351
Figure 38.40 PCMCIA Memory Card Interface Bus Timing
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait 1,
Hardware Wait 1) ................................................................................................ 1352
Figure 38.41 PCMCIA I/O Card Interface Bus Timing............................................................ 1353
Figure 38.42 PCMCIA I/O Card Interface Bus Timing
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait 1,
Hardware Wait 1) ................................................................................................ 1354
Figure 38.43 REFOUT, IRQOUT Delay Time ........................................................................ 1354
Figure 38.44 I/O Port Timing ................................................................................................... 1355
Figure 38.45 DREQ Input Timing (DREQ Low Level is Detected) ........................................ 1355
Figure 38.46 DACK Output Timing......................................................................................... 1355
Figure 38.47 TPU Output Timing ............................................................................................. 1356
Figure 38.48 TPU Clock Input Timing..................................................................................... 1356
Figure 38.49 Oscillation Settling Time when RTC Crystal Oscillator is Turned On ............... 1357
Figure 38.50 SCK Input Clock Timing .................................................................................... 1358
Figure 38.51 SCIF Input/Output Timing in Synchronous Mode .............................................. 1359
Figure 38.52 I2C Bus Interface Input/Output Timing ............................................................... 1361
Figure 38.53 SIOF_MCLK Input Timing................................................................................. 1362
Figure 38.54 SIOF Transmission/Reception Timing (Master Mode 1, Fall Sampling)............ 1363
Figure 38.55 SIOF Transmission/Reception Timing (Master Mode 1, Rise Sampling)........... 1363
Figure 38.56 SIOF Transmission/Reception Timing (Master Mode 2, Fall Sampling)............ 1364
Figure 38.57 SIOF Transmission/Reception Timing (Master Mode 2, Rise Sampling)........... 1364
Figure 38.58 SIOF Transmission/Reception Timing (Slave Mode 1, Slave Mode 2) .............. 1365
Figure 38.59 AFEIF Module AC Timing ................................................................................. 1366
Figure 38.60 USB Clock Timing.............................................................................................. 1367
Figure 38.61 LCDC Module Signal Timing ............................................................................. 1369
Figure 38.62 SIM Module Signal Timing ................................................................................ 1370
Figure 38.63 MMCIF Transmit Timing ................................................................................... 1371
Rev. 3.00 Jan. 18, 2008 Page l of lxii
Figure 38.64
Figure 38.65
Figure 38.66
Figure 38.67
Figure 38.68
Figure 38.69
MMCIF Receive Timing (Rise Sampling) .......................................................... 1371
TCK Input Timing............................................................................................... 1372
TRST Input Timing (Reset Hold)........................................................................ 1373
H-UDI Data Transfer Timing .............................................................................. 1373
ASEMD0 Input Timing....................................................................................... 1373
Output Load Circuit............................................................................................. 1375
Appendix
Figure C.1 Package Dimensions (PLBG0256GA-A (BP-256H/HV))...................................... 1392
Figure C.2 Package Dimensions (PLBG0256KA-A (BP-256C/CV)) ...................................... 1393
Rev. 3.00 Jan. 18, 2008 Page li of lxii
Rev. 3.00 Jan. 18, 2008 Page lii of lxii
Tables
Section 1 Overview
Table 1.1
SH7720/SH7721 Features......................................................................................... 2
Table 1.2
Product Lineup (SH7720 Group).............................................................................. 8
Table 1.3
Product Lineup (SH7721 Group).............................................................................. 9
Table 1.4
List of Pin Assignments .......................................................................................... 13
Table 1.5
SH7720/SH7721 Pin Functions .............................................................................. 25
Section 2 CPU
Table 2.1
Table 2.2
Table 2.3
Table 2.4
Table 2.5
Table 2.6
Table 2.7
Table 2.8
Table 2.9
Table 2.10
Table 2.11
Table 2.12
Virtual Address Space............................................................................................. 40
Register Initial Values............................................................................................. 43
Addressing Modes and Effective Addresses for CPU Instructions......................... 56
CPU Instruction Formats ........................................................................................ 60
CPU Instruction Types............................................................................................ 63
Data Transfer Instructions....................................................................................... 67
Arithmetic Operation Instructions .......................................................................... 69
Logic Operation Instructions .................................................................................. 71
Shift Instructions..................................................................................................... 72
Branch Instructions ................................................................................................. 73
System Control Instructions.................................................................................... 74
Operation Code Map............................................................................................... 77
Section 3 DSP Operating Unit
Table 3.1
Table 3.2
Table 3.3
Table 3.4
Table 3.5
Table 3.6
Table 3.7
Table 3.8
Table 3.9
Table 3.10
Table 3.11
Table 3.12
Table 3.13
Table 3.14
Table 3.15
CPU Processing Modes .......................................................................................... 83
Virtual Address Space............................................................................................. 84
Operation of SR Bits in Each Processing Mode ..................................................... 87
RS and RE Setting Rule.......................................................................................... 93
Repeat Control Instructions .................................................................................... 93
Repeat Control Macros ........................................................................................... 94
DSP Mode Extended System Control Instructions ................................................. 96
PC Value during Repeat Control (When RC[11:0] ≥ 2) ......................................... 99
Extended System Control Instructions in DSP Mode ........................................... 103
Overview of Data Transfer Instructions................................................................ 106
Modulo Addressing Control Instructions.............................................................. 108
Double Data Transfer Instruction Formats ........................................................... 111
Single Data Transfer Instruction Formats ............................................................. 112
Destination Register in DSP Instructions.............................................................. 114
Source Register in DSP Operations ...................................................................... 115
Rev. 3.00 Jan. 18, 2008 Page liii of lxii
Table 3.16
Table 3.17
Table 3.18
Table 3.19
Table 3.20
Table 3.21
Table 3.22
Table 3.23
Table 3.24
Table 3.25
Table 3.26
Table 3.27
Table 3.28
Table 3.29
Table 3.30
Table 3.31
Table 3.32
Table 3.33
Table 3.34
Table 3.35
Table 3.36
Table 3.37
Table 3.38
Table 3.39
Table 3.40
DSR Register Bits................................................................................................. 116
DSP Operation Instruction Formats...................................................................... 118
Correspondence between DSP Instruction Operands and Registers ..................... 119
DC Bit Update Definitions ................................................................................... 120
Examples of NOPX and NOPY Instruction Codes............................................... 122
Variation of ALU Fixed-Point Operations............................................................ 126
Correspondence between Operands and Registers ............................................... 126
Variation of ALU Integer Operations ................................................................... 131
Variation of ALU Logical Operations .................................................................. 133
Variation of Fixed-Point Multiply Operation ....................................................... 135
Correspondence between Operands and Registers ............................................... 136
Variation of Shift Operations................................................................................ 137
Operation Definition of PDMSB .......................................................................... 143
Variation of PDMSB Operation............................................................................ 144
Variation of Rounding Operation ......................................................................... 145
Definition of Overflow Protection for Fixed-Point Arithmetic Operations .......... 146
Definition of Overflow Protection for Integer Arithmetic Operations.................. 146
Variation of Local Data Move Operations............................................................ 147
Correspondence between Operands and Registers ............................................... 148
DSP Mode Extended System Control Instructions ............................................... 149
Double Data Transfer Instruction ......................................................................... 151
Single Data Transfer Instructions ......................................................................... 152
Correspondence between DSP Data Transfer Operands and Registers ................ 153
DSP Operation Instructions .................................................................................. 154
Operation Code Map............................................................................................. 160
Section 4 Memory Management Unit (MMU)
Table 4.1
Access States Designated by D, C, and PR Bits ................................................... 183
Section 5 Cache
Table 5.1
Table 5.2
Table 5.3
Table 5.4
Table 5.5
Table 5.6
Table 5.7
Table 5.8
Number of Entries and Size/Way in Each Cache Size.......................................... 197
LRU and Way Replacement (when Cache Locking Mechanism is Disabled)...... 199
Way Replacement when a PREF Instruction Misses the Cache ........................... 203
Way Replacement when Instructions other than the PREF Instruction
Miss the Cache...................................................................................................... 203
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)................ 203
LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)................ 204
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)................ 204
Address Format Based on the Size of Cache to be Assigned to Memory............. 211
Rev. 3.00 Jan. 18, 2008 Page liv of lxii
Section 6 X/Y Memory
Table 6.1
Table 6.2
X/Y Memory Virtual Addresses ........................................................................... 213
MMU and Cache Settings..................................................................................... 216
Section 7 Exception Handling
Table 7.1
Table 7.2
Table 7.3
Table 7.4
Table 7.5
Exception Event Vectors....................................................................................... 225
Instruction Positions and Restriction Types.......................................................... 235
SPC Value When a Re-Execution Type Exception Occurs in Repeat Control
(SR.RC[11:0]≥2)................................................................................................... 237
Exception Acceptance in the Repeat Loop ........................................................... 239
Instruction Where a Specific Exception Occurs
When a Memory Access Exception Occurs in Repeat Control
(SR.RC[11:0]≥1)................................................................................................... 240
Section 8 Interrupt Controller (INTC)
Table 8.1
Table 8.2
Table 8.3
Table 8.4
Table 8.5
Pin Configuration.................................................................................................. 245
Interrupt Sources and IPRA to IPRJ ..................................................................... 248
Interrupt Exception Handling Sources and Priority (IRQ Mode) ......................... 270
Interrupt Exception Handling Sources and Priority (IRL Mode).......................... 272
Interrupt Level and INTEVT Code....................................................................... 275
Section 9 Bus State Controller (BSC)
Table 9.1
Table 9.2
Table 9.3
Table 9.4
Table 9.5
Table 9.6
Table 9.7
Table 9.8
Table 9.9
Table 9.10
Table 9.11
Table 9.12
Table 9.12
Table 9.13
Pin Configuration.................................................................................................. 283
Address Space Map 1 (CMNCR.MAP = 0).......................................................... 287
Address Space Map 2 (CMNCR.MAP = 1).......................................................... 288
Correspondence between External Pins (MD3 and MD4),
Memory Type of CS0, and Memory Bus Width................................................... 289
Correspondence between External Pin (MD5) and Endians ................................. 289
32-Bit External Device/Big Endian Access and Data Alignment ......................... 331
16-Bit External Device/Big Endian Access and Data Alignment ......................... 332
8-Bit External Device/Big Endian Access and Data Alignment........................... 333
32-Bit External Device/Little Endian Access and Data Alignment ...................... 334
16-Bit External Device/Little Endian Access and Data Alignment ...................... 335
8-Bit External Device/Little Endian Access and Data Alignment ........................ 336
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (1)-1..................................................................... 349
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (1)-2..................................................................... 350
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (2)-1..................................................................... 351
Rev. 3.00 Jan. 18, 2008 Page lv of lxii
Table 9.13
Table 9.14
Table 9.15
Table 9.15
Table 9.16
Table 9.16
Table 9.17
Table 9.17
Table 9.18
Table 9.19
Table 9.20
Table 9.21
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (2)-2..................................................................... 352
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (3) ........................................................................ 353
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (4)-1..................................................................... 354
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (4)-2..................................................................... 355
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (5)-1..................................................................... 356
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (5)-2..................................................................... 357
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (6)-1..................................................................... 358
Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0],
and Address Multiplex Output (6)-2..................................................................... 359
Relationship between Access Size and Number of Bursts.................................... 360
Access Address in SDRAM Mode Register Write ............................................... 380
Output Addresses when EMRS Command is Issued ............................................ 383
Relationship between Bus Width, Access Size, and Number of Bursts................ 386
Section 10 Direct Memory Access Controller (DMAC)
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.7
Table 10.8
Pin Configuration.................................................................................................. 409
Transfer Request Sources ..................................................................................... 423
Selecting External Request Modes with RS Bits .................................................. 426
Selecting External Request Detection with DL, DS Bits ...................................... 427
Selecting External Request Detection with DO Bit .............................................. 427
Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits ..... 429
Supported DMA Transfers.................................................................................... 434
Relationship between Request Modes and Bus Modes
by DMA Transfer Category.................................................................................. 441
Section 11 Clock Pulse Generator (CPG)
Table 11.1
Table 11.2
Table 11.3
Pin Configuration.................................................................................................. 457
Clock Operating Modes ........................................................................................ 458
Possible Combination of Clock Mode and FRQCR Values ................................. 459
Section 13 Power-Down Modes
Table 13.1
Table 13.2
States of Power-Down Modes .............................................................................. 478
Pin Configuration.................................................................................................. 479
Rev. 3.00 Jan. 18, 2008 Page lvi of lxii
Section 14 Timer Unit (TMU)
Table 14.1
TMU Interrupt Sources ......................................................................................... 509
Section 15 16-Bit Timer Pulse Unit (TPU)
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.4
Table 15.4
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Table 15.9
Table 15.10
Table 15.11
TPU Functions ...................................................................................................... 512
TPU Pin Configurations........................................................................................ 514
TPU Clock Sources............................................................................................... 518
TPSC2 to TPSC0 (1)............................................................................................. 518
TPSC2 to TPSC0 (2)............................................................................................. 518
TPSC2 to TPSC0 (3)............................................................................................. 519
TPSC2 to TPSC0 (4)............................................................................................. 519
IOA2 to IOA0 ....................................................................................................... 522
Register Combinations in Buffer Operation ......................................................... 534
Phase Counting Mode Clock Input Pins ............................................................... 539
Up/Down-Count Conditions in Phase Counting Mode 1...................................... 541
Up/Down-Count Conditions in Phase Counting Mode 2...................................... 542
Up/Down-Count Conditions in Phase Counting Mode 3...................................... 543
Up/Down-Count Conditions in Phase Counting Mode 4...................................... 544
Section 17 Realtime Clock (RTC)
Table 17.1
Table 17.2
Pin Configuration.................................................................................................. 561
Recommended Oscillator Circuit Constants (Recommended Values).................. 584
Section 18 Serial Communication Interface with FIFO (SCIF)
Table 18.1
Table 18.2
Table 18.3
Table 18.4
Pin configuration................................................................................................... 588
SCSMR Settings and SCIF Transmit/Receive ...................................................... 614
Serial Transmit/Receive Formats.......................................................................... 615
SCIF Interrupt Sources ......................................................................................... 636
Section 19 Infrared Data Association Module (IrDA)
Table 19.1
Pin Configuration.................................................................................................. 640
Section 20 I2C Bus Interface (IIC)
Table 20.1
Table 20.2
Table 20.3
Table 20.4
I2C Bus Interface Pins........................................................................................... 648
Transfer Rate ........................................................................................................ 659
Interrupt Requests ................................................................................................. 675
Time for Monitoring SCL..................................................................................... 676
Section 21 Serial I/O with FIFO (SIOF)
Table 21.1
Pin Configuration.................................................................................................. 681
Rev. 3.00 Jan. 18, 2008 Page lvii of lxii
Table 21.2
Table 21.3
Table 21.4
Table 21.5
Table 21.6
Table 21.7
Table 21.8
Table 21.9
Table 21.10
Table 21.11
Table 21.12
Operation in Each Transfer Mode......................................................................... 685
SIOF Serial Clock Frequency ............................................................................... 710
Serial Transfer Modes........................................................................................... 713
Frame Length........................................................................................................ 714
Audio Mode Specification for Transmit Data....................................................... 716
Audio Mode Specification for Receive Data ........................................................ 716
Setting Number of Channels in Control Data ....................................................... 717
Conditions to Issue Transmit Request .................................................................. 719
Conditions to Issue Receive Request .................................................................... 720
Transmit and Receive Reset.................................................................................. 725
SIOF Interrupt Sources ......................................................................................... 727
Section 22 Analog Front End Interface (AFEIF)
Table 22.1
Table 22.2
Table 22.3
Pin Configuration.................................................................................................. 736
FIFO Interrupt Size............................................................................................... 738
Telephone Number and Data ................................................................................ 745
Section 23 USB Pin Multiplex Controller
Table 23.1
Table 23.2
Table 23.3
Table 23.4
Pin Configuration (Digital Transceiver Signal) .................................................... 756
Pin Configuration (Analog Transceiver Signal) ................................................... 756
Pin Configuration (Power Control Signal)............................................................ 757
Pin Configuration (Clock Signal) ......................................................................... 757
Section 24 USB Host Controller (USBH)
Table 24.1
Pin Configuration.................................................................................................. 766
Section 25 USB Function Controller (USBF)
Table 25.1
Table 25.2
Table 25.3
Table 25.4
Table 25.5
Pin Configuration and Functions .......................................................................... 805
Restrictions of Settable Values ............................................................................. 834
Example of Endpoint Configuration..................................................................... 834
Example of Setting of Endpoint Configuration Information ................................ 835
Command Decoding on Application Side ............................................................ 855
Section 26 LCD Controller (LCDC)
Table 26.1
Table 26.2
Table 26.3
Table 26.4
Pin Configuration.................................................................................................. 865
I/O Clock Frequency and Clock Division Ratio ................................................... 868
Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (32-bit SDRAM)............................................................ 899
Limits on the Resolution of Rotated Displays, Burst Length,
and Connected Memory (16-bit SDRAM)............................................................ 902
Rev. 3.00 Jan. 18, 2008 Page lviii of lxii
Table 26.5
Table 26.6
Table 26.7
Available Power-Supply Control-Sequence Periods at Typical Frame Rates....... 913
LCDC Operating Modes ....................................................................................... 914
LCD Module Power-Supply States....................................................................... 914
Section 27 A/D Converter
Table 27.1
Table 27.2
Table 27.3
Table 27.4
Table 27.5
Pin Configuration.................................................................................................. 931
Analog Input Channels and A/D Data Registers................................................... 932
A/D Conversion Time (Single Mode)................................................................... 943
Conditions for the Method of Transferring Results of A/D Conversion
and Inclusion of Superfluous DMA ...................................................................... 947
Analog Input Pin Ratings...................................................................................... 950
Section 28 D/A Converter (DAC)
Table 28.1
Pin Configuration.................................................................................................. 954
Section 29 PC Card Controller (PCC)
Table 29.1
Table 29.2
Table 29.3
Features of the PCMCIA Interface ....................................................................... 959
PCC Pin Configuration ......................................................................................... 962
PCMCIA Support Interface .................................................................................. 977
Section 30 SIM Card Module (SIM)
Table 30.1
Table 30.2
Table 30.3
Table 30.4
Pin Configuration.................................................................................................. 989
Register Settings for Smart Card Interface ......................................................... 1009
Example of Bit Rates (bits/s) for SCBRR Settings
(Pφ = 19.8 MHz, SCSMPL = 371)...................................................................... 1011
Interrupt Sources of Smart Card Interface .......................................................... 1018
Section 31 MultiMediaCard Interface (MMCIF)
Table 31.1
Table 31.2
Table 31.3
Table 31.4
Table 31.5
Pin Configuration................................................................................................ 1029
Correspondence between Commands and Settings of CMDTYR
and RSPTYR ...................................................................................................... 1034
CMDR Configuration ......................................................................................... 1037
Correspondence between Command Response Byte Number and RSPR........... 1039
MMCIF Interrupt Sources................................................................................... 1108
Section 33 User Break Controller (UBC)
Table 33.1
Table 33.2
Table 33.3
Specifying Break Address Register .................................................................... 1116
Specifying Break Data Register.......................................................................... 1118
Data Access Cycle Addresses and Operand Size Comparison Conditions ......... 1129
Rev. 3.00 Jan. 18, 2008 Page lix of lxii
Section 34 Pin Function Controller (PFC)
Table 34.1
Multiplexed Pins................................................................................................. 1141
Section 35 I/O Ports
Table 35.1
Table 35.2
Table 35.3
Table 35.4
Table 35.5
Table 35.6
Table 35.7
Table 35.8
Table 35.9
Table 35.10
Table 35.11
Table 35.12
Table 35.13
Table 35.14
Table 35.15
Table 35.16
Table 35.17
Table 35.18
Port A Data Register (PADR) Read/Write Operations ....................................... 1180
Port B Data Register (PBDR) Read/Write Operations ....................................... 1182
Port C Data Register (PCDR) Read/Write Operations ....................................... 1184
Port D Data Register (PDDR) Read/Write Operations ....................................... 1186
Port E Data Register (PEDR) Read/Write Operations........................................ 1188
Port F Data Register (PFDR) Read/Write Operations ........................................ 1191
Port G Data Register (PGDR) Read/Write Operations ....................................... 1194
Port H Data Register (PHDR) Read/Write Operations ....................................... 1196
Port J Data Register (PJDR) Read/Write Operations.......................................... 1198
Port K Data Register (PKDR) Read/Write Operations ....................................... 1200
Port L Data Register (PLDR) Read/Write Operations ........................................ 1202
Port M Data Register (PMDR) Read/Write Operations...................................... 1204
Port P Data Register (PPDR) Read/Write Operations ........................................ 1206
Port R Data Register (PRDR) Read/Write Operations........................................ 1208
Port S Data Register (PSDR) Read/Write Operations ........................................ 1210
Port T Data Register (PTDR) Read/Write Operations ........................................ 1212
Port U Data Register (PUDR) Read/Write Operations ....................................... 1214
Port V Data Register (PVDR) Read/Write Operations ....................................... 1216
Section 36 User Debugging Interface (H-UDI)
Table 36.1
Table 36.2
Table 36.3
Table 36.4
Pin Configuration................................................................................................ 1219
H-UDI Commands.............................................................................................. 1221
Pins and Boundary Scan Register Bits................................................................ 1222
Reset Configuration ............................................................................................ 1232
Section 38 Electrical Characteristics
Table 38.1
Table 38.2
Table 38.3
Table 38.4
Table 38.4
Table 38.4
Table 38.4
Table 38.5
Table 38.6
Absolute Maximum Ratings ............................................................................... 1305
Recommended Timing in Power-On .................................................................. 1307
Recommended Timing in Power-Off.................................................................. 1308
DC Characteristics (1) [Common] ...................................................................... 1309
DC Characteristics (2-a) [Except USB Transceiver, I2C, ADC,
DAC Analog Related Pins]................................................................................. 1311
DC Characteristics (2-b) [I2C Related Pins] ....................................................... 1312
DC Characteristics (2-c) [USB Transceiver Related Pins] ................................. 1313
Permissible Output Current Values .................................................................... 1313
Maximum Operating Frequencies....................................................................... 1314
Rev. 3.00 Jan. 18, 2008 Page lx of lxii
Table 38.7
Table 38.8
Table 38.9
Table 38.10
Table 38.11
Table 38.12
Table 38.13
Table 38.14
Table 38.15
Table 38.16
Table 38.17
Table 38.18
Table 38.19
Table 38.20
Table 38.21
Table 38.22
Table 38.23
Table 38.24
Table 38.25
Clock Timing ...................................................................................................... 1315
Control Signal Timing ........................................................................................ 1319
Bus Timing ......................................................................................................... 1322
Peripheral Module Signal Timing....................................................................... 1355
16-Bit Timer Pulse Unit...................................................................................... 1356
RTC Signal Timing............................................................................................. 1357
SCIF Module Signal Timing............................................................................... 1358
I2C Bus Interface Timing .................................................................................... 1360
SIOF Module Signal Timing............................................................................... 1362
AFEIF Module Signal Timing ............................................................................ 1365
USB Module Clock Timing ................................................................................ 1366
USB Electrical Characteristics (Full-Speed)....................................................... 1367
USB Electrical Characteristics (Low-Speed)...................................................... 1367
LCDC Module Signal Timing............................................................................. 1368
SIM Module Signal Timing ................................................................................ 1369
MMCIF Module Signal Timing.......................................................................... 1370
H-UDI Related Pin Timing ................................................................................. 1372
A/D Converter Characteristics ............................................................................ 1374
D/A Converter Characteristics ............................................................................ 1374
Appendix
Table A.1
Pin States ............................................................................................................ 1377
Rev. 3.00 Jan. 18, 2008 Page lxi of lxii
Rev. 3.00 Jan. 18, 2008 Page lxii of lxii
Section 1
Section 1
1.1
Overview
Overview
Features
This LSI is a single-chip RISC microprocessor that integrates a 32-bit RISC-type Super H
architecture CPU with a digital signal processing (DSP) extension as its core, together with a
large-capacity 32-kbyte cache memory, a 16-kbyte X/Y memory, and an interrupt controller.
High-speed data transfers can be performed by an on-chip direct memory access controller
(DMAC), and an external memory access support function enables direct connection to different
kinds of memory. This LSI also supports a stereo audio recording and playback function, a USB
host controller, a function controller, an LCD controller, a PCMCIA interface, an A/D converter,
and a D/A converter.
The USB host controller and LCD controller have bus master functions, so that data supplied from
an external memory (area 3) can be freely processed. Since the USB host controller, in particular,
conforms to Open HCI standards, it is extremely easy to transfer data from the PC of a device
driver or other devices. Also, low-power operation suitable for battery operation is possible
because the LCD controller continues to display even in sleep mode.
A powerful built-in power management function keeps power consumption low, even during highspeed operation. This LSI is ideal for electronics devices, which require both high speed and low
power consumption.
The SH7720 group integrates an SSL (Secure Socket Layer) accelerator that performs RSA
(Rivest-Shamir-Adleman) operations and DES (Data Encryption Standard) and Triple-DES
encryption/decryption, while the SH7721 group does not have the SSL accelerator. Each group
consists of several models which includes or does not include an SD host interface (SDHI) to be
suited to a variety of applications. See table 1.2 and 1.3, Product Lineup, for the models including
(or not including) the SDHI.
Note: For the detailed specifications of the SDHI and SSL, contact the Renesas representatives
in your region.
Table 1.1 shows the features of this LSI.
Rev. 3.00
Jan. 18, 2008
Page 1 of 1458
REJ09B0033-0300
Section 1
Table 1.1
Overview
SH7720/SH7721 Features
Item
Features
CPU
•
Renesas Technology Original SuperH architecture
•
Upper compatibility with SH-1, SH-2, and SH3-DSP at object code level
•
32-bit internal data bus
•
General-register
 Sixteen 32-bit general registers (eight 32-bit shadow registers)
 Five 32-bit control registers
 Four 32-bit system registers
•
RISC type instruction set
 Instruction length: 16-bit fixed length for improved code efficiency
 Load/store architecture
 Delayed branch instruction
 Instruction set based on C language
DSP operating
unit
•
Instruction execution time: One instruction/cycle for basic instructions
•
Logical address space: 4 Gbytes
•
Space identifier ASID: 8 bits, 256 logical address spaces
•
Five-stage pipeline
•
•
•
•
•
Mixture of 16-bit and 32-bit instructions
32-/40-bit internal data bus
Multiplier, ALU, barrel shifter, and DSP register
16-bit x 16-bit → 32-bit one cycle multiplier
Large-capacity DSP data register file
 Six 32-bit data registers
 Two 40-bit data registers
Extended Harvard architecture for DSP data buses
 Two data buses
 One instruction bus
Up to four parallel operations: ALU, multiply, two loads, and store
Two address units to generating addresses for two memory access
DSP data addressing modes: Increment, index register addition (with or
without modulo addressing)
Zero-overhead repeat loop control
Conditional execution instructions
User DSP mode and privileged DSP mode
•
•
•
•
•
•
•
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 2 of 1458
Section 1
Item
Features
•
Memory
management unit •
(MMU)
•
Cache memory
X/Y memory
Overview
4-Gbyte address space, 256 address spaces (8-bit ASID)
Page unit sharing
Supports multiple page sizes: 1 kbyte or 4 kbytes
•
128-entry, 4-way set associative TLB
•
Specifies replacement way by software and supports random replacement
algorithm
•
Address assignment allows direct access to TLB contents
•
32-kbyte cache mixing instructions and data
•
512-entry, 4-way set associative, 16-byte block length
•
Write-back, write-through, least recent used (LRU) replacement algorithm
•
Single-stage write-back buffer
•
User-selectable mapping mechanism
 Fixed mapping for mission-critical realtime applications
 Automatic mapping through TLB for easy to use
•
Three independent read/write ports
 8-/16-/32-bit access from CPU
 Up to two 16-bit accesses from DSP
 8-/16-/32-bit access from DMAC
•
•
Interrupt
controller (INTC)
8-kbyte RAM for X and Y memory individual (4 kbytes × 4)
Seven external interrupt pins (NMI, IRQ5 to IRQ0)
 NMI: Fall/rise selectable
 IRQ: Fall/rise/high level/low level selectable
Bus state
controller (BSC)
•
On-chip peripheral interrupt: Sets priority for each module
•
Physical address space is provided to support areas of up to 64 Mbytes and
32 Mbytes.
•
Each area allows independent setting of the following functions:
 Bus size (8, 16, or 32 bits). An access wait cycle count with a different
size to be supported is provided for each area.
 Number of access wait cycles. Some areas can be inserted wait cycles
independently in read access and write access.
 Sets of idle wait cycle (for the same or different area)
 Supports SRAM, page mode ROM, SDRAM, and pseudo SRAM (ready
for page mode) by specifying memory to be connected to each area.
 Outputs chip select signals to corresponding areas, such as CS0, CS2 to
CS4, CS5A/CS5B, and CS6A/CS6B
Rev. 3.00
Jan. 18, 2008
Page 3 of 1458
REJ09B0033-0300
Section 1
Overview
Item
Features
Direct memory
•
access controller
•
(DMAC)
•
Number of channels: Six channels (two channels support external requests)
Address space: 4 Gbytes on architecture
Data transfer length: Bytes, words (2 bytes), longwords (4 bytes), 16 bytes
(longword × 4)
•
Maximum number of transfer times: 16,777,216 times
•
Address mode: Single address mode or dual address mode selectable
•
Transfer request: Selectable from external request, on-chip peripheral
module request, and auto request
•
Bus mode: Selectable from cycle steal mode (normal mode and intermittent
mode) and burst mode
•
Priority: Selectable from channel priority fixed mode and round robin mode
•
Interrupt request: Supports interrupt request to CPU at the end of data
transfer
•
External request detection: Selectable from DREQ input low/high level
detection and rising/falling detection
•
Transfer request acceptance signal: DACK and TEND can be set an active
level
Clock pulse
•
generator (CPG)
•
Clock mode: Input clock selectable from external clock (EXTAL or CKIO)
and crystal resonator
Generates three types of clocks
 CPU clock: Maximum 133.34 MHz
 Bus clock: Maximum 66.67 MHz
 Peripheral clock: Maximum 33.34 MHz
•
Supports power-down mode
 Sleep mode
 Standby mode
 Module standby mode (X/Y memory standby enabled)
Watchdog timer
(WDT)
•
One-channel watchdog timer
•
One-channel watchdog timer (WDT)
•
Interrupt request: WDT only
Timer unit (TMU) •
Rev. 3.00
Internal three-channel 32-bit timer
•
Auto-reload type 32-bit down counter
•
Internal prescaler for Pφ
•
Interrupt request
Jan. 18, 2008
REJ09B0033-0300
Page 4 of 1458
Section 1
Item
Overview
Features
16-bit timer pulse •
unit (TPU)
•
Four-channel 16-bit timer
PWM mode
•
Four types of counter input clocks
•
Phase counting mode (two channels)
•
Internal six-channel 32-bit counter (16-/32-bit switchable)
•
Selectable prescaling for Pφ
•
Internal full-channel compare match function
•
With interrupt request and DMAC request
Realtime clock
(RTC)
•
Built-in clock, calendar functions, and alarm functions
•
On-chip 32-kHz crystal oscillator circuit with a maximum resolution (cycle
interrupt) of 1/256 second
Serial
communication
interface with
FIFO
(SCIF0, SCIF1)
•
Includes a 64-byte FIFO for transmission and another for reception
•
Supports high-speed UART for Bluetooth
•
Internal prescaler for Pφ
•
With interrupt request and DMAC request
Infrared data
association
module (IrDA)
•
Conforms to the IrDA 1.0 system
•
Asynchronous serial communication
•
On-chip 64-stage FIFO buffers for transmission and reception
Compare match
timer (CMT)
I C bus interface •
(IIC)
2
Serial I/O with
FIFO
(SIOF0, SIOF1)
Supports multi master transmission/reception
•
Includes a 64-byte FIFO for transmission and another for reception
•
Supports 8-/16-/16-bit stereo sound input/output
•
Sampling rate clock input selectable from Pφ and external pin
•
Includes a prescaler for Pφ
•
Interrupt requests and DMAC requests
Analog front end •
interface (AFEIF)
•
STLC7550 can directly be connected
Data access arrangement function
•
128-word transmit FIFO
•
128-word receive FIFO
Rev. 3.00
Jan. 18, 2008
Page 5 of 1458
REJ09B0033-0300
Section 1
Overview
Item
Features
USB host
•
controller (USBH)
•
Conforms to OHCI Rev. 1.0
USB Rev. 1.1 compatible
•
127 endpoints
•
Support interrupt/bulk/control/isochronous mode
•
Bus master controller (can access area 3 and synchronous DRAM)
•
Two ports with analog transceiver (one is common with USB function
controller)
•
External clock input function
USB function
•
controller (USBF)
•
Conforms to OHCI Rev. 1.0
LCD controller
(LCDC)
A/D converter
(ADC)
D/A converter
(DAC)
PC card
controller (PCC)
Rev. 3.00
Six endpoints
•
Support interrupt/bulk/control/isochronous mode
•
One port with analog transceiver (common with USB function controller),
12 Mbps only
•
External clock input function
•
From 16 × 1 to 1024 × 1024 pixels can be supported
•
4/8/15/16 bpp (bit per pixel) color pallet
•
1/2/4/6 bpp (bit per pixel) gray scale
•
8-bit frame rate controller
•
TFT/DSTN/STN panels
•
Signal polarity setting function
•
Hardware panel rotation
•
Power control function
•
Selectable clock source (LCLK, Bclk, or Pclk)
•
10 bits ± 4 LSB, four channels
•
Conversion time: 15 µs
•
Input range: 0 to AVCC (max. 3.6 V)
•
8 bits ± 4 LSB, two channels
•
Conversion time: 10 µs
•
Output range: 0 to AVCC (max. 3.6 V)
•
Complies with the PCMCIA Rev.2.1/JEIDA Version 4.2
•
Supports the IC memory card interface and I/O card interface
Jan. 18, 2008
REJ09B0033-0300
Page 6 of 1458
Section 1
Item
Features
SIM card
interface (SIM)
•
Single channel ready for ISO7816-3 data protocol (T = 0, T = 1)
•
Asynchronous half-duplex character transmission protocol
•
Data length of 8 bits
•
Generates and checks a parity bit
•
Number of output clocks per 1 etu selectable
•
Direct convention/inverse convention selectable
•
Internal prescaler for Pφ
•
Clock polarity changeable at idle time (low or high)
•
With interrupt request and DMAC request
MultiMedia Card •
interface
•
(MMCIF)
•
Complies with The MultiMedia Card System Specification Version 3.1
Supports MMC mode
16.5-Mbps bit rate (max) for the card interface (Pφ = 33 MHz)
•
Incorporates sixty-four 16-bit data-transfer FIFOs
•
Interrupt and DMA request
•
Module standby function
SD host interface •
(SDHI)
Note: Only for
models with the
SDHI
Overview
Supports SDHC (SD High Capacity) and SDIO
 Supports Part 1 Physical Layer Ver.1.01 to 2.0 of SD Specification, but
not supported for High-Speed
 Supports Part E1 SDIO Ver. 1.00 to 2.00 of SD Specification
•
SD memory/IO card interface (1 bit/4 bits SD bus)
•
SD clock frequency ≤ 1/2 peripheral clock frequency
•
Error check function: CRC7 (command/response), CRC16 (data)
•
MMC (MultiMedia Card) access
•
Interrupt request and DAMC transfer request (SD_BUF read/write)
•
Card detection function
•
Write protect
SSL accelerator
(SSL)
•
RSA encryption
•
Supported operations: addition, subtraction, multiplication, power operation
Note: SH7720
group only
•
DES and Triple-DES encryption/decryption
Rev. 3.00
Jan. 18, 2008
Page 7 of 1458
REJ09B0033-0300
Section 1
Overview
Item
Features
User break
controller (UBC)
•
Two break channels
•
All of address, data value, access type, and data size can be set as break
conditions.
•
Supports sequential break function
User debugging •
interface (H-UDI)
•
•
Table 1.2
Supports E10A emulator
Realtime branch trace
1-kbyte on-chip memory for executing high-speed emulation program
Product Lineup (SH7720 Group)
Power Supply
Voltage
Operating
Model
I/O
Internal
Frequency
Product Code
Package
SSL
SDHI
SH7720
3.3 V
1.5 V
133.34
HD6417720BP133C
256-pin 17mm x 17mm CSP
O

±0.3V
±0.1V
MHz
O

O

O

O
O
O
O
O
O
O
O
(PLBG0256GA-A)
HD6417720BP133CV
256-pin 17mm x 17mm CSP
(PLBG0256GA-A)
HD6417720BL133C
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
HD6417720BL133CV
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
SH7320
HD6417320BP133C
256-pin 17mm x 17mm CSP
(PLBG0256GA-A)
HD6417320BP133CV
256-pin 17mm x 17mm CSP
(PLBG0256GA-A)
HD6417320BL133C
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
HD6417320BL133CV
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
[Legend] O: Provided; : Not provided
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 8 of 1458
Section 1
Table 1.3
Overview
Product Lineup (SH7721 Group)
Power Supply
Voltage
Model
SH7721
Operating
I/O
Internal
Frequency
Product Code
Package
SSL
SDHI
3.3 V
1.5 V
133.34
R8A77210C133BG
256-pin 17mm x 17mm CSP


±0.3V
±0.1V
MHz







O

O

O

O
(PLBG0256GA-A)
R8A77210C133BGV
256-pin 17mm x 17mm CSP
(PLBG0256GA-A)
R8A77210C133BA
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
R8A77210C133BAV
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
R8A77211C133BG
256-pin 17mm x 17mm CSP
(PLBG0256GA-A)
R8A77211C133BGV
256-pin 17mm x 17mm CSP
(PLBG0256GA-A)
R8A77211C133BA
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
R8A77211C133BAV
256-pin 11mm x 11mm CSP
(PLBG0256KA-A)
[Legend] O: Provided; : Not provided
Rev. 3.00
Jan. 18, 2008
Page 9 of 1458
REJ09B0033-0300
Section 1
Overview
1.2
Block Diagram
Super H
CPU core
User break
controller (UBC)
DSP core
CPU bus
X bus
Y bus
Cache access
X/Y memory
controller (CCN)
Instruction/data for
CPU/DSP (16 kbytes)
Internal bus
External bus
Cache
memory
(32 kbytes)
Internal bus
Direct memory
access controller
(DMAC)
Bus state
Peripheral
controller
bus controller
(BSC)
Peripheral bus
Interrupt
controller
(INTC)
User debugging
interface (H-UDI)
Realtime
clock
(RTC)
Memory
management
unit (MMU)
Clock pulse
generator
(CPG)
SSL
accelerator
(SSL)
USB host
controller
(USBH)
512-byte
RAM
LDC
controller
(LCDC)
2.56-kbyte
line buffer
Compare
match
timer (CMT)
16-bit
timer pulse
unit (TPU)
Timer unit
(TMU)
Peripheral bus
Serial communication
interface 0 with FIFO
128-byte FIFO
(SCIF0/IrDA)
Serial communication
interface 1 with FIFO
128-byte FIFO (SCIF1)
SD host
interface
(SDHI)
I2C
576-byte
SRAM
128-byte
RAM
Analog front end
interface (AFEIF)
MultiMediaCard
interface (MMCIF)
Figure 1.1
1.3
Pin Assignments
1.3.1
Pin Assignments
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 10 of 1458
USB function controller
1-kbyte FIFO (USBF)
256-byte
SRAM
Serial I/O
with FIFO
(SIOF0)
Block Diagram
256-byte
SRAM
Serial I/O
with FIFO
(SIOF1)
A/D
converter
(ADC)
SIM card
interface
(SIM)
D/A
converter
(DAC)
PC card
controller
(PCC)
Figure 1.2
RD/WR
WE3/
DQMUU/
ICIOWR
D17/PTA1
WE2/
DQMUL/
ICIORD
VccQ1
CKIO
K
Rev. 3.00
Jan. 18, 2008
A9
A3
VssQ1
VccQ1
Y
W
V
U
VccQ1
A6
A16
VssQ1
A11
VccQ1
R
A2
A14
VssQ1
P
A8
CS3
T
D21/PTA5
D13
A1
A7
A4
A5
A13
A17
CS2
WE1/
WE0/DQMLL
DQMLU/WE
RAS/PTH6
N
M
L
CAS/PTH5
D16/PTA0
D18/PTA2
D20/PTA4
VssQ1
A0/PTR0
D12
A10
A12
A15
Vss
Vcc
CKE/PTH4
D19/PTA3
Vss
VssQ1
D22/PTA6
J
H
D23/PTA7
Vcc
D27/PTB3
VccQ1
D25/PTB1
D28/PTB4
D30/PTB6
STATUS0/
PTH2
D26/PTB2
D29/PTB5
Vss_PLL1
D31/PTB7
MD5
7
8
9
D9
D14
VccQ1
D5
D10
D8
D11
INDEX
D15
VccQ
11
LCD_CLK
12
VssQ
13
VssQ1
VccQ1
D3
D2
D6
D7
D1
D4
BREQ
CS5B/CE1A/
PTM1
CS6A/CE2B
VssQ1
VssQ1
CS4
BACK
Vss
CS6B/
CS5A/CE2A
CE1B/PTM0
D0
Vcc
Vss
SH7330
PLBG0256GA-A
(BP-256H/HV)
(Top view)
LCD_CL1/
PTE3
CS0
A18
WAIT/
PCC_WAIT
BS
Vcc
RD
A21/PTR3
A20/PTR2
A19/PTR1
SIOF0_RxD/
PTS1
AN1/PTF2
USB2_P
VssQ1
A25/PTR7
VccQ1
VssQ1
TEND0/
VccQ_RTC
PINT2/PTM2
AVcc_USB
AVss_USB
19
XTAL_USB
SIM_D/
SIM_RST/
SCIF1_TxD/
SD_WP/
SCIF1_RxD/PTV1 SD_CD/PTV2
MMC_DAT/
SIOF1_TxD/
SD_DAT0/
TPU_TI3A/PTU2
TCK/PTL3
TMS/PTL6
VccQ1
TEND1/
PINT3/PTM3
XTAL_RTC
DACK1/PTM5
Vss_RTC
RESETP
TDI/PTL4
ASEMD0
AUDSYNC/
PTJ0
VccQ
VssQ
AUDATA3/
PTJ4
IRQ2/IRL2/
PTP2
VccQ
CA
Vcc_RTC
VccQ
VssQ
PINT5/
PCC_VS2/
PTK1
PINT4/
PCC_VS1/
PTK0
TDO/PTL5
PINT6/
PCC_RDY/
PTK2
PINT7/
ASEBRKAK/
PCC_RESET/
PTJ5
PTK3
TRST/PTL7
AUDCK/PTJ6
AUDATA0/
PTJ1
Vcc
IRQ0/IRL0/
PTP0
SCIF0_SCK/
PTT0
AUDATA1/
PTJ2
NMI
IRQ3/IRL3/
PTP3
AUDATA2/
PTJ3
Vss
IRQ1/IRL1/
PTP1
SCIF0_RxD/
IrRx/PTT1
MMC_CMD/
SIOF1_MCLK/ SIOF1_SYNC/ SCIF0_RTS/
SIOF1_RxD/
SD_DAT1/
SD_DAT2/
TPU_TO0/
SD_CMD/
TPU_TI2B/PTU1 TPU_TI3B/PTU3 PTU4
PTT3
SCIF0_CTS/ MMC_CLK/
SIOF1_SCK/
SCIF0_TxD/ TPU_TO1/
VssQ
SD_CLK/
IrTX/PTT2
PTT4
TPU_TI2A/PTU0
Vcc
VccQ
VssQ
USB1d_TXENL/
PINT8/
PCC_CD1/PTG0
MMC_ODMOD/ AFE_RXIN/ SIM_CLK/
SCIF1_RTS/
SCIF1_SCK/
LCD_VCPWC/ IIC_SCL/
SD_DAT3/PTV0
TPU_TO2/PTV3 PTE6
USB1d_RCV/ USB1d_TXSE0/
USB1d_SPEED/
IRQ5/AFE_FS/ IRQ4/
AFE_TXOUT/
PINT9/PCC_CD2/
PCC_REG/
PCC_DRV/
PTG1
PTG6
PTG5
MMC_VDDON/ AFE_RDET/ USB1d_DPLS/
SCIF1_CTS/
PINT10/
LCD_VEPWC/ IIC_SDA/
AFE_HC1/
TPU_TO3/PTV4 PTE5
PCC_BVD1/PTG2
Vss
VccQ
VssQ
20
USB1d_TXDPLS/
AFE_SCLK/IOIS16/ USB1_ovr_current/ EXTAL_USB
PCC_IOIS16/
USBF_VBUS
PTG4
USB1_M
AVcc_USB
18
USB1d_DMNS/ USB1d_SUSPEND/
PINT11/
REFOUT/
AFE_RLYCNT/
PCC_BVD2/PTG3 IRQOUT/PTP4
AVcc
USB1_P
AN0/PTF1
17
A24/PTR6 DACK0/
DREQ1/PTM7
PINT1/PTM4
DA0/PTF5
AN3/PTF4
USB2_M
AVss
AN2/PTF3
16
15
USB1_pwr_en/
USBF_UPLUP/
PTH0
A23/PTR5 DREQ0/
EXTAL_RTC
PINT0/PTM6
A22/PTR4
USB2_ovr_current
DA1/PTF6
VccQ
14
SIOF0_SYNC/ SIOF0_TxD/ SIOF0_SCK/
ADTRG/PTF0
PTS4
PTS0
PTS2
VssQ
10
LCD_DATA12/ LCD_DATA9/ LCD_DATA6/ LCD_DATA2/ LCD_DON/
PTE1
PTC6
PTC2
PINT12/PTD4 PTD1
LCD_CL2/
PTE2
LCD_M_DISP/ SIOF0_MCLK/ USB2_pwr_en/
PTE4
PTS3
PTH1
LCD_DATA5/ LCD_DATA1/
PTC5
PTC1
LCD_DATA15/ LCD_DATA11/ LCD_DATA7/ LCD_DATA3/ LCD_FLM/
PTC7
PINT15/PTD7 PTD3
PTE0
PTC3
VccQ
6
LCD_DATA14/ LCD_DATA10/ LCD_DATA8/ LCD_DATA4/ LCD_DATA0/
PTC0
PTD0
PTC4
PINT14/PTD6 PTD2
MD3
MD4
RESETM
EXTAL
VssQ
XTAL
5
4
LCD_DATA13/
PINT13/PTD5
3
STATUS1/
PTH3
VssQ1
G
D24/PTB0
VccQ1
E
F
MD0
VssQ1
D
Vss_PLL2
MD1
MD2
Vcc_PLL2
B
Vcc_PLL1
VccQ
VssQ
A
C
2
1
Section 1
Overview
Pin Assignments (PLBG0256GA-A (BP-256H/HV))
Page 11 of 1458
REJ09B0033-0300
Rev. 3.00
REJ09B0033-0300
Jan. 18, 2008
Figure 1.3
D23/PTA7
VssQ1
D27/PTB3
VssQ1
VccQ1
G
Page 12 of 1458
Pin Assignments (PLBG0256KA-A (BP-256C/CV))
VccQ1
A13
A11
A8
A5
A14
A3
A15
A12
VccQ1
A6
A4
VssQ1
R
T
U
V
W
Y
AA
A10
A7
A17
CS3
P
A2
A9
VssQ1
WE0/
DQMLL
N
A1
VssQ1
RAS/PTH6
M
WE2/
DQMUL/
ICIORD
A0/PTR0
D14
VccQ1
Vcc
WE3/
DQMUU/
ICIOWR
D16/PTA0
CAS/PTH5
VccQ1
L
Vcc
Vss_PLL1
D21/PTA5
VssQ1
K
D20/PTA4
D26/PTB2
D17/PTA1
VccQ1
J
H
D30/PTB6
D24/PTB0
VssQ1
F
Vcc_PLL2
Vss_PLL2
E
D29/PTB5
Vcc_PLL1
MD0
D28/PTB4
MD3
D
XTAL
MD4
EXTAL
4
LCD_DATA11/
PTD3
3
C
MD2
B
VssQ
2
LCD_DATA15/
D31/PTB7
PINT15/PTD7
MD1
A
1
D15
D11
VccQ1
D15
A16
Vss
CS2
WE1/
DQMLU/
WE
CKE/PTH4
RD/WR
CKIO
D18/PTA2
D19/PTA3
Vss
D22/PTA6
D25/PTB1
VccQ
MD5
RESETM
5
6
7
8
9
10
VssQ
11
D12
D8
D13
VssQ1
D9
D6
D10
VccQ1
D4
D2
D7
D1
D0
D3
CS6A/CE2B CS5A/CE2A
VssQ1
CS0
Vss
CS6B/CE1B/
PTM0
CS5B/CE1A/
PTM1
BACK
VccQ1
Vcc
12
13
14
VccQ
VssQ
Vss
CS4
RD
BREQ
BS
A18
VssQ1
A19/PTR1
WAIT/
PCC_WAIT
LCD_CLK
A21/PTR3
VccQ1
A23/PTR5
A20/PTR2
SIOF0_MCLK/
PTS3
USB1_pwr_en/
USBF_UPLUP DA0/PTF5
PTH0
Vcc
AVss
15
AN0/PTF1
16
VssQ1
VccQ1
TEND0/PINT2/
PTM2
TEND1/PINT3/
PTM3
A25/PTR7
A24/PTR6
DACK0/
PINT1/
PTM4
USB1d_TXDPLS/
AFE_SCLK/IOIS16/
PCC_IOIS16/PTG4
ADTRG/
PTF0
USB2_pwr_en/
PTH1
19
20
EXTAL_USB
IRQ0/IRL0/
PTP0
VccQ
TCK/PTL3
VssQ
EXTAL_RTC
VccQ_RTC
CA
ASEBRKAK/
PTJ5
DACK1/
PTM5
RESETP
VccQ
TRST/PTL7
AUDATA3/
PTJ4
VccQ
AUDCK/
PTJ6
IRQ2/IRL2/
PTP2
SCIF0_SCK/ AUDATA1/
PTJ2
PTT0
VssQ
SCIF0_RTS/
TPU_TO0/
PTT3
XTAL_RTC
TDI/PTL4
Vcc_RTC
Vss_RTC
TDO/PTL5
VssQ
PINT5/
PCC_VS2/
PTK1
PINT4/
PCC_VS1/
PTK0
DREQ1/
PTM7
PINT6/
PCC_RDY/
PTK2
PINT7/
TMS/PTL6 PCC_RESET/
PTK3
ASEMD0
AUDSYNC/
PTJ0
Vcc
Vss
IRQ1/IRL1/
PTP1
AUDATA0/
PTJ1
PTJ3
AUDATA2/
NMI
IRQ3/IRL3/
PTP3
SCIF0_TxD/ SCIF0_RxD/
IrTX/PTT2 IrRX/PTT1
Vcc
SIOF1_MCLK/
SD_DAT1/
TPU_TI3B/PTU3
MMC_CMD/
SCIF0_CTS/
SIOF1_RxD/
TPU_TO1/
SD_CMD/
TPU_TI2B/PTU1 PTT4
SIOF1_SYNC/
SD_DAT2/
PTU4
MMC_CLK/
SIOF1_SCK/
SD_CLK/
TPU_TI2A/PTU0
VccQ
SIM_CLK/
SCIF1_SCK/
SD_DAT3/
PTV0
MMC_DAT/
SIOF1_TxD/
SD_DAT0/
TPU_TI3A/PTU2
MMC_ODMOD/
SCIF1_RTS/
LCD_VCPWC/
TPU_TO2/PTV3
SIM_RST/
SD_WP/
SCIF1_RxD/PTV1
VssQ
SIM_D/
SCIF1_TxD/
SD_CD/PTV2
AFE_RXIN/
IIC_SCL/
PTE6
USB1d_TXENL/
USB1d_DPLS/
PINT10/AFE_HC1/ PINT8/
PCC_BVD1/PTG2 PCC_CD1/
/PTG0
VccQ
USB1d_RCV/ USB1d_TXSE0/
IRQ5/AFE_FS/ IRQ4/AFE_TXOUT/
PCC_REG/
PCC_DRV/PTG5
PTG6
AFE_RDET/ USB1d_SUSPEND/
REFOUT/IRQOUT/
IIC_SDA/
PTP4
PTE5
VssQ
USB1_M
21
USB1d_SPEED/
PINT9/
PCC_CD2/PTG1
DREQ0/
PINT0/
PTM6
AVcc
USB1_ovr_current/
USBF_VBUS
USB1d_DMNS/
PINT11/
AVcc_USB
AFE_RLYCNT/
PCC_BVD2/PTG3
Vss
MMC_VDDON/
SCIF1_CTS/
LCD_VEPWC/ XTAL_USB
TPU_TO3/PTV4
AN3/PTF4
AVcc_USB
USB1_P
18
AVss_USB
AN2/PTF3
USB2_M
17
USB2_P
A22/PTR4
VccQ
AN1/PTF2
SIOF0_RxD/ USB2_ovr_current DA1/PTF6
PTS1
SIOF0_SYNC/ SIOF0_TxD/ SIOF0_SCK/
PTS4
PTS2
PTS0
SH7330
PLBG0256KA-A
(BP-256C/CV)
(Top view)
LCD_CL1/
PTE3
LCD_DATA7/ LCD_DATA5/ LCD_DATA1/ LCD_FLM/
PTC5
PTC7
PTC1
PTE0
INDEX
VssQ
LCD_DATA3/
PTC3
LCD_M_DISP/
PTE4
VccQ
LCD_CL2/
PTE2
STATUS1/ LCD_DATA13/
PTH3
PINT13/PTD5
STATUS0/ LCD_DATA12/ LCD_DATA9/ LCD_DATA6/ LCD_DATA2/ LCD_DON/
PTH2
PINT12/PTD4 PTD1
PTC6
PTC2
PTE1
LCD_DATA14/ LCD_DATA10/ LCD_DATA8/ LCD_DATA4/ LCD_DATA0/
PINT14/PTD6 PTD2
PTD0
PTC4
PTC0
Section 1
Overview
Section 1
Table 1.4
Overview
List of Pin Assignments
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
I/O
Buffer
Power
Supply
Function
A1
A2
VssQ
I/O power supply (0V)

A2
D5
VccQ
I/O power supply (3.3 V)

A3
D6
STATUS1/PTH3
Status output/general-purpose
port
O/IO
VccQ
A4
D7
LCD_DATA13/PINT13/
PTD5
LCD data/port interrupt/
general-purpose port
O/I/IO
VccQ
A5
E6
VssQ
I/O power supply (0V)

A6
D8
VccQ
I/O power supply (3.3 V)

A7
E8
LCD_DATA5/PTC5
LCD data/general-purpose port
O/IO
VccQ
A8
E9
LCD_DATA1/PTC1
LCD data/general-purpose port
O/IO
VccQ
A9
D10
LCD_CL2/PTE2
LCD shift clock 2/general-purpose O/IO
port
VccQ
A10
A11
VssQ
I/O power supply (0V)

A11
E12
VccQ
I/O power supply (3.3 V)

A12
E13
LCD_CLK
LCD clock source
A13
D12
VssQ
I/O power supply (0V)

A14
E15
VccQ
I/O power supply (3.3 V)

A15
D13
USB1_pwr_en/
USBF_UPLUP/PTH0
USB1 power-enable/pull-up
control/general-purpose port
A16
A15
AVss
Analog power supply (0V)

A17
A16
AN0/PTF1
ADC analog input/general-purpose I/I
port
AVcc
A18
B18
AVcc_USB
USB power supply (3.3 V)

A19
D17
AVss_USB
USB power supply (0 V)

A20
B21
VssQ
I/O power supply (0V)

B1
E4
Vcc_PLL2
PLL2 power supply (1.5 V)

B2
B1
MD2
Clock mode setting
I
VccQ
B3
B2
XTAL
Crystal
O
VccQ
B4
A5
RESETM
Manual reset
I
VccQ
B5
A4
MD4
Bus width setting
I
VccQ
I/O
Rev. 3.00
I
VccQ
O/O/IO
Jan. 18, 2008
VccQ
Page 13 of 1458
REJ09B0033-0300
Section 1
Overview
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply
B6
C1
LCD_DATA15/PINT15/
PTD7
LCD data/port interrupt/
general-purpose port
O/I/IO
VccQ
B7
B3
LCD_DATA11/PTD3
LCD data/general-purpose port
O/IO
VccQ
B8
E7
LCD_DATA7/PTC7
LCD data/general-purpose port
O/IO
VccQ
B9
D9
LCD_DATA3/PTC3
LCD data/general-purpose port
O/IO
VccQ
B10
E10
LCD_FLM/PTE0
LCD line marker/general-purpose
port
O/IO
VccQ
B11
D11
LCD_M_DISP/PTE4
LCD current-alternating signal/
general-purpose port
O/IO
VccQ
B12
E14
SIOF0_MCLK/PTS3
SIOF master clock/generalpurpose port
I/IO
VccQ
B13
E16
USB2_pwr_en/PTH1
USB2 power-enable/
general-purpose port
O/IO
VccQ
B14
B16
DA1/PTF6
DAC analog output/generalpurpose port
O/I
VccQ
B15
B17
AN2/PTF3
ADC analog input/general-purpose I/I
port
AVcc
B16
A17
USB2_M
USB D− port 2
IO
AVcc_
USB
B17
A18
USB1_P
USB D+ port 1
IO
AVcc_
USB
B18
A21
USB1_M
USB D− port 1
IO
AVcc_
USB
B19
A20
AVcc_USB
USB power supply (3.3 V)

B20
E20
VccQ
I/O power supply (3.3 V)

C1
D2
Vcc_PLL1
PLL1 power supply (1.5 V)

C2
A1
MD1
Clock mode setting
I
VccQ
C3
B5
MD5
Endian setting
I
VccQ
C4
A3
EXTAL
External clock
I
VccQ
C5
B4
MD3
Bus width setting
I
VccQ
C6
B7
LCD_DATA12/PINT12/
PTD4
LCD data/port interrupt/
general-purpose port
O/I/IO
VccQ
C7
B8
LCD_DATA9/PTD1
LCD data/general-purpose port
O/IO
VccQ
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 14 of 1458
Section 1
Pin No.
(PLBG
0256
GA-A)
Overview
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply
C8
B9
LCD_DATA6/PTC6
LCD data/general-purpose port
O/IO
VccQ
C9
B10
LCD_DATA2/PTC2
LCD data/general-purpose port
O/IO
VccQ
C10
B11
LCD_DON/PTE1
LCD display on signal/
general-purpose port
O/IO
VccQ
C11
A12
SIOF0_SYNC/PTS4
SIOF frame sync/general-purpose IO/IO
port
VccQ
C12
A13
SIOF0_TxD/PTS2
SIOF transmit data/generalpurpose port
O/IO
VccQ
C13
A14
SIOF0_SCK/PTS0
SIOF serial clock/general-purpose IO/IO
port
VccQ
C14
E17
ADTRG/PTF0
ADC external trigger/generalpurpose port
I/I
VccQ
C15
D18
AN3/PTF4
ADC analog input/general-purpose I/I
port
AVcc
C16
D16
USB2_P
USB D+ port 2
AVcc_
USB
C17
B19
AVcc
Analog power supply (3.3 V)
C18
E18
USB1d_TXDPLS/
AFE_SCLK/IOIS16/
PCC_IOIS16/PTG4
D+ transmit output/AFE shift
clock/16-bit IO/PCCI 6-bit
IO/general-purpose port
O/I/I/I/
IO
VccQ
C19
B20
USB1_ovr_current/
USBF_VBUS
USB1 overcurrent/monitor
I/I
VccQ
I
IO

C20
E21
EXTAL_USB
USB external clock
D1
F1
VssQ1
I/O power supply (0 V)
D2
D1
MD0
Clock mode setting
I
VccQ
D3
C2
D31/PTB7
Data bus/general-purpose port
IO/IO
VccQ1
D4
B6
STATUS0/PTH2
Status output/general-purpose
port
O/IO
VccQ
D5
A6
LCD_DATA14/PINT14/
PTD6
LCD data/port interrupt/
general-purpose port
O/I/IO
VccQ
D6
A7
LCD_DATA10/PTD2
LCD data/general-purpose port
O/IO
VccQ
D7
A8
LCD_DATA8/PTD0
LCD data/general-purpose port
O/IO
VccQ
D8
A9
LCD_DATA4/PTC4
LCD data/general-purpose port
O/IO
VccQ
Rev. 3.00
VccQ

Jan. 18, 2008
Page 15 of 1458
REJ09B0033-0300
Section 1
Overview
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply
D9
A10
LCD_DATA0/PTC0
LCD data/general-purpose port
O/IO
VccQ
D10
E11
LCD_CL1/PTE3
LCD shift clock 1/general-purpose O/IO
port
VccQ
D11
B12
Vss
Internal power supply (0 V)

D12
B13
Vcc
Internal power supply (1.5 V)

D13
B14
SIOF0_RxD/PTS1
SIOF receive data/generalpurpose port
I/IO
VccQ
D14
B15
USB2_ovr_current
USB2 port overcurrent
I
VccQ
D15
D14
DA0/PTF5
DAC analog output/generalpurpose port
O/I
VccQ
D16
D15
AN1/PTF2
ADC analog input/general-purpose I/I
port
AVcc
D17
A19
USB1d_DMNS/PINT11/
AFE_RLYCNT/
PCC_BVD2/PTG3
D- signal input/port interrupt/
AFE on-hook control/PCC buttery
detection 2/general-purpose port
I/I/O/I/
IO
VccQ
D18
C21
USB1d_SUSPEND/
REFOUT/IRQOUT/
PTP4
Suspend state/bus request
(refresh)/ bus request (interrupt)/
general-purpose port
O/O/O/
IO
VccQ
D19
F18
XTAL_USB
USB crystal
O
VccQ
D20
F21
USB1d_TXENL/PINT8/
PCC_CD1/PTG0
Driver output enable/port interrupt/ O/I/I/IO
PCC card detection 1/
general-purpose port
VccQ
E1
G1
VccQ1
I/O power supply (1.8/3.3 V)

E2
E1
Vss_PLL2
PLL2 power supply (0 V)

E3
F4
Vss_PLL1
PLL1 power supply (0 V)

E4
G4
D30/PTB6
Data bus/general-purpose port
IO/IO
VccQ1
E17
G18
USB1d_SPEED/PINT9/
PCC_CD2/PTG1
Speed control/port interrupt/
PCC card detection 2/
general-purpose port
O/I/I/IO
VccQ
E18
D20
USB1d_RCV/IRQ5/
AFE_FS/PCC_REG/
PTG6
Receive data/interrupt/
area indicate signal/
AFE frame synchronization/
PCC space indication/
general-purpose port
I/I/I/O/
IO
VccQ
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 16 of 1458
Section 1
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
E19
D21
E20
Overview
I/O
Buffer
Power
Supply
Function
I/O
USB1d_TXSE0/IRQ4/
AFE_TXOUT/
PCC_DRV/PTG5
SE0 state/interrupt/
AFE serial transmission/
PCC buffer control/
general-purpose port
O/I/O/
O/IO
G21
VssQ
I/O power supply (0V)
F1
G2
D24/PTB0
Data bus/general-purpose port
IO/IO
VccQ1
F2
E2
D29/PTB5
Data bus/general-purpose port
IO/IO
VccQ1
F3
D4
D28/PTB4
Data bus/general-purpose port
IO/IO
VccQ1
F4
H4
D27/PTB3
Data bus/general-purpose port
IO/IO
VccQ1
F17
F17
MMC_VDDON/
SCIF1_CTS/
LCD_VEPWC/
TPU_TO3/PTV4
MMC card power supply control/
O/I/O/
SCIF transmit enable/LCD power O/IO
supply control/ TPU comparematch output/general-purpose port
VccQ
F18
C20
AFE_RDET/IIC_SDA/
PTE5
AFE ringing/IIC data I/O
/general-purpose port
I/IO/I
VccQ
F19
F20
USB1d_DPLS/PINT10/
AFE_HC1/PCC_BVD1/
PTG2
D+ transmit input/port interrupt/
AFE hardware control/
PCC battery detection 1/
general-purpose port
I/I/O/I/
IO
VccQ
F20
H20
VccQ
I/O power supply (3.3 V)

G1
H2
VssQ1
I/O power supply (0V)

G2
F2
D26/PTB2
Data bus/general-purpose port
IO/IO
VccQ1
IO/IO
VccQ1
VccQ

G3
E5
D25/PTB1
Data bus/general-purpose port
G4
J4
Vcc
Internal power supply (1.5 V)

G17
G17
Vss
Internal power supply (0 V)

G18
H18
MMC_ODMOD/
SCIF1_RTS/
LCD_VCPWC/TPU_TO2/
PTV3
MMC open drain control/
O/O/O/
SCIF transmit request/LCD power O/IO
supply control/TPU comparematch output/general-purpose port
VccQ
G19
G20
AFE_RXIN/IIC_SCL/
PTE6
AFE serial receive/
IIC clock/general-purpose port
I/IO/I
VccQ
G20
J20
SIM_CLK/ SCIF1_SCK/
SD_DAT3/PTV0
SIM clock/SCIF serial clock/
SD data/general-purpose port
O/IO/
IO/IO
VccQ
Rev. 3.00
Jan. 18, 2008
Page 17 of 1458
REJ09B0033-0300
Section 1
Pin No.
(PLBG
0256
GA-A)
Overview
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply

H1
J1
VccQ1
I/O power supply (1.8/3.3 V)
H2
H1
D23/PTA7
Data bus/general-purpose port
IO/IO
VccQ1
H3
F5
D22/PTA6
Data bus/general-purpose port
IO/IO
VccQ1
H4
G5
Vss
Power-supply (0 V)

H17
J18
Vcc
Power-supply (1.5 V)

H18
H17
SIM_RST/SCIF1_RxD/
SD_WP/PTV1
SIM reset/SCIF receive data/
SD write protect/
general-purpose port
O/I/I/IO
VccQ
H19
H21
SIM_D/SCIF1_TxD/
SD_CD/PTV2
SIM data/SCIF transmit data/
SD card detection/
general-purpose port
IO/O/I/
IO
VccQ
H20
K20
MMC_DAT/SIOF1_TxD/
SD_DAT0/TPU_TI3A/
PTU2
MMC data/SIOF transmit data/
SD data/TPU clock input/
general-purpose port
IO/O/
IO/I/IO
VccQ
J1
K1
VssQ1
I/O power supply (0V)
J2
J2
D20/PTA4
Data bus/general-purpose port
IO/IO
VccQ1
J3
K4
D21/PTA5
Data bus/general-purpose port
IO/IO
VccQ1
J4
H5
D19/PTA3
Data bus/general-purpose port
IO/IO
VccQ1
J17
K17
MMC_CMD/
SIOF1_RxD/SD_CMD/
TPU_TI2B/PTU1
MMC command/SIOF receive
data/SD command/TPU clock
input/general-purpose port
IO/I/IO/
I/IO
VccQ
J18
J17
SIOF1_MCLK/SD_DAT1/ SIOF master clock/SD data/
TPU_TI3B/PTU3
TPU clock input/general-purpose
port
I/IO/I/IO VccQ
J19
J21
SIOF1_SYNC/SD_DAT2/ SIOF frame sync/
PTU4
SD data/general-purpose port
IO/IO/IO VccQ
J20
L17
SCIF0_RTS/TPU_TO0/
PTT3
SCIF transmit request/TPU
compare-match output/
general-purpose port
O/O/IO
K1
L1
VccQ1
I/O power supply (1.8/3.3 V)
K2
K2
D17/PTA1
Data bus/general-purpose port
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 18 of 1458

VccQ

IO/IO
VccQ1
Section 1
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
Overview
I/O
Buffer
Power
Supply
I/O
K3
J5
D18/PTA2
Data bus/general-purpose port
IO/IO
VccQ1
K4
L4
D16/PTA0
Data bus/general-purpose port
IO/IO
VccQ1
K17
L20
SCIF0_TxD/IrTx/PTT2
SCIF transmit data/ IrDA transmit
data/general-purpose port
O/O/IO
VccQ
K18
K18
SCIF0_CTS/TPU_TO1/
PTT4
SCIF transmit enable/TPU
compare-match output/
general-purpose port
I/O/IO
VccQ
K19
K21
MMC_CLK/SIOF1_SCK/ MMC clock/SIOF serial clock/
O/IO/O/ VccQ
SD_CLK/TPU_TI2A/
SD clock/TPU clock input/general- I/IO
PTU0
purpose port
K20
M17
VssQ

I/O power supply (0V)
L1
K5
CKIO
System clock
IO
VccQ1
L2
M1
WE2/DQMUL/ICIORD
Second-highest-byte write/
DQ mask UL/IO read
O/O/O
VccQ1
L3
M4
WE3/DQMUU/ICIOWR
Highest-byte write/
DQ mask UU/IO write
O/O/O
VccQ1
L4
L5
RD/WR
Read/write signal
O
VccQ1
L17
L21
SCIF0_RxD/IrRx/PTT1
SCIF receive data/IrDA receive
data/general-purpose port
I/I/IO
VccQ
L18
M20
IRQ3/IRL3/PTP3
Interrupt/interrupt/general-purpose I/I/IO
port
VccQ
L19
N17
SCIF0_SCK/PTT0
SCIF serial clock/general-purpose IO/IO
port
VccQ
L20
L18
VccQ
I/O power supply (3.3 V)

M1
L2
CAS/PTH5
Column address/general-purpose
port
O/IO
VccQ1
M2
N1
WE0/DQMLL
Lowest-byte write/DQ mask LL
O/O
VccQ1
M3
N5
WE1/DQMLU/WE
Second-lowest-byte write/
DQ mask LU/write enable
O/O/O
VccQ1
M4
M5
CKE/PTH4
Clock enable/general-purpose port O/IO
VccQ1
M17
M21
IRQ1/IRL1/PTP1
Interrupt/interrupt/
general-purpose port
I/I/IO
VccQ
M18
N20
NMI
NMI interrupt
I
VccQ
Rev. 3.00
Jan. 18, 2008
Page 19 of 1458
REJ09B0033-0300
Section 1
Overview
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply
M19
M18
IRQ0/IRL0/PTP0
Interrupt/interrupt/
general-purpose port
I/I/IO
VccQ
M20
P17
IRQ2/IRL2/PTP2
Interrupt/interrupt/
general-purpose port
I/I/IO
VccQ
N1
M2
RAS/PTH6
Row address/general-purpose port O/IO
VccQ1
N2
P1
CS3
Chip select
O
VccQ1
N3
P5
CS2
Chip select
O
N4
N4
Vcc
Power-supply (1.5 V)

N17
N21
Vss
Power-supply (0 V)

N18
P20
AUDATA2/PTJ3
AUD data/general-purpose port
O/IO
VccQ
N19
N18
AUDATA1/PTJ2
AUD data/general-purpose port
O/IO
VccQ
N20
R17
AUDATA3/PTJ4
AUD data/general-purpose port
O/IO
VccQ
P1
N2
VssQ1
I/O power supply (0V)
P2
W2
A14
Address bus
O
P3
P2
A17
Address bus
O
P4
R5
Vss
Internal power supply (0 V)
P17
P21
Vcc
Internal power supply (1.5 V)


P18
R20
AUDATA0/PTJ1
AUD data/general-purpose port
O/IO
VccQ
P19
P18
AUDCK/PTJ6
AUD clock/general-purpose port
O/IO
VccQ
P20
T17
VssQ
I/O power supply (0V)

R1
P4
VccQ1
I/O power supply (1.8/3.3 V)

R2
T2
A11
Address bus
O
VccQ1
R3
R2
A13
Address bus
O
VccQ1
R4
R1
A15
Address bus
O
VccQ1
R17
T20
AUDSYNC/PTJ0
AUD synchronous signal/
general-purpose port
O/IO
VccQ
R18
R21
ASEMD0
ASE mode
I
VccQ
R19
R18
TRST/PTL7
Test reset/general-purpose port
I/IO
VccQ
R20
U17
VccQ
I/O power supply (3.3 V)
T1
T5
A16
Address bus
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 20 of 1458
VccQ1

VccQ1
VccQ1


O
VccQ1
Section 1
Overview
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply
T2
V1
A6
Address bus
O
VccQ1
T3
V2
A5
Address bus
O
VccQ1
T4
T1
A12
Address bus
O
VccQ1
T17
U20
TMS/PTL6
Test mode select/general-purpose I/IO
port
VccQ
T18
T18
TCK/PTL3
Test clock/general-purpose port
I/IO
VccQ
T19
U21
PINT7/PCC_RESET/
PTK3
Port interrupt/PCC reset/generalpurpose port
I/O/IO
VccQ
T20
V18
ASEBRKAK/PTJ5
ASE break mode acknowledge/
general-purpose port
O/IO
VccQ
U1
R4
VssQ1
I/O power supply (0 V)
U2
T4
A9
Address bus
O
VccQ1
U3
W1
A4
Address bus
O
VccQ1

U4
AA3
A10
Address bus
O
VccQ1
U5
Y5
D11
Data bus
IO
VccQ1
U6
Y6
D8
Data bus
IO
VccQ1
U7
AA8
D4
Data bus
IO
VccQ1
U8
AA9
D1
Data bus
IO
VccQ1
U9
AA10
Vcc
Internal power supply (1.5 V)

U10
V11
Vss
Internal power supply (0 V)

U11
U11
BACK
Bus request acknowledge
O
U12
U12
BS
Bus start
O
U13
V13
A19/PTR1
Address bus/general-purpose port O/IO
VccQ1
U14
U15
A22/PTR4
Address bus/general-purpose port O/IO
VccQ1
U15
U16
A24/PTR6
Address bus/general-purpose port O/IO
VccQ1
U16
V15
DACK0/PINT1/PTM4
DMA transfer request reception/
port interrupt/
general-purpose port
O/I/IO
VccQ1
U17
W21
DREQ1/PTM7
DMA transfer request/
general-purpose port
I/IO
VccQ1
U18
T21
TDI/PTL4
Test data input/general-purpose
port
I/IO
VccQ
Rev. 3.00
Jan. 18, 2008
VccQ1
VccQ1
Page 21 of 1458
REJ09B0033-0300
Section 1
Overview
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply
U19
V21
PINT6/PCC_RDY/PTK2
Port interrupt/PCC ready/generalpurpose port
I/I/IO
VccQ
U20
W20
TDO/PTL5
Test data output/general-purpose
port
O/IO
VccQ
V1
U1
VccQ1
I/O power supply (1.8/3.3 V)
V2
Y2
A3
Address bus
O

VccQ1
V3
U4
A7
Address bus
O
VccQ1
V4
AA6
D12
Data bus
IO
VccQ1
V5
Y4
D14
Data bus
IO
VccQ1
V6
AA7
D9
Data bus
IO
VccQ1
V7
Y7
D6
Data bus
IO
VccQ1
V8
Y8
D2
Data bus
IO
VccQ1
V9
Y9
D0
Data bus
IO
VccQ1
V10
Y10
CS5B/CE1A/PTM1
Chip select/chip select/
general-purpose port
O/O/IO
VccQ1
V11
V12
BREQ
Bus request
I
VccQ1
V12
U13
WAIT/PCC_WAIT
Wait/PCC wait
I/I
VccQ1
V13
U14
A20/PTR2
Address bus/general-purpose port O/IO
VccQ1
V14
V14
A23/PTR5
Address bus/general-purpose port O/IO
VccQ1
V15
Y19
DREQ0/PINT0/PTM6
DMA transfer request/
I/I/IO
port interrupt/general-purpose port
VccQ1
V16
Y18
EXTAL_RTC
RTC external clock
I
VccQ_
RTC
V17
AA19
XTAL_RTC
RTC crystal
O
VccQ_
RTC
V18
V17
RESETP
Power-on reset
I
VccQ_
RTC
V19
AA21
PINT5/PCC_VS2/PTK1
Port interrupt/
PCC voltage detection 2/
general-purpose port
I/I/IO
VccQ
V20
V20
VssQ
I/O power supply (0 V)
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 22 of 1458

Section 1
Pin No.
(PLBG
0256
GA-A)
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
Overview
I/O
Buffer
Power
Supply
I/O
W1
U2
A8
Address bus
O
VccQ1
W2
AA2
A2
Address bus
O
VccQ1
W3
AA1
A1
Address bus
O
VccQ1
W4
AA4
A0/PTR0
Address bus/general-purpose port O/IO
VccQ1
W5
AA5
D15
Data bus
IO
VccQ1
W6
V7
D10
Data bus
IO
VccQ1
W7
V8
D7
Data bus
IO
VccQ1
W8
V9
D3
Data bus
IO
VccQ1
W9
V10
CS6B/CE1B/PTM0
Chip select/chip select/generalpurpose port
O/O/IO
VccQ1
W10
U9
CS5A/CE2A
Chip select/chip select
O/O
VccQ1
W11
AA12
CS4
Chip select
O
VccQ1
W12
AA13
A18
Address bus
O
VccQ1
W13
AA14
A21/PTR3
Address bus/general-purpose port O/IO
VccQ1
W14
Y15
A25/PTR7
Address bus/general-purpose port O/IO
VccQ1
W15
Y16
TEND0/PINT2/PTM2
DMA transfer end/port interrupt/
general-purpose port
VccQ1
W16
AA18
VccQ_RTC
RTC power supply (3.3 V)
W17
V16
TEND1/PINT3/PTM3
DMA transfer end/port interrupt/
general-purpose port
W18
Y20
Vss_RTC
RTC power supply (0 V)
W19
Y21
PINT4/PCC_VS1/PTK0
Port interrupt/PCC voltage
detection 1/general-purpose port
W20
U18
VccQ
I/O power supply (3.3 V)

Y1
Y1
VssQ1
I/O power supply (0 V)

Y2
V5
VccQ1
I/O power supply (1.8/3.3 V)

Y3
V6
D13
Data bus
Y4
Y3
VssQ1
I/O power supply (0 V)
O/I/IO

O/I/IO

I/I/IO
IO
VccQ
VccQ1

Y5
V4
VccQ1
I/O power supply (1.8/3.3 V)
Y6
U5
D5
Data bus

IO
Rev. 3.00
VccQ1
Jan. 18, 2008
VccQ1
Page 23 of 1458
REJ09B0033-0300
Section 1
Pin No.
(PLBG
0256
GA-A)
Overview
Pin No.
(PLBG
0256
KA-A) Pin Name
Function
I/O
I/O
Buffer
Power
Supply
Y7
U6
VssQ1
I/O power supply (0 V)

Y8
U7
VccQ1
I/O power supply (1.8/3.3 V)

Y9
U8
CS6A/CE2B
Chip select/chip select
Y10
AA11
VssQ1
I/O power supply (0 V)

Y11
U10
VccQ1
I/O power supply (1.8/3.3 V)

Y12
Y11
CS0
Chip select
O
VccQ1
Y13
Y12
RD
Read strobe
O
VccQ1
Y14
Y13
VssQ1
I/O power supply (0 V)
VccQ1
Y15
Y14
VccQ1
I/O power supply (1.8/3.3 V)

Y16
AA15
VssQ1
I/O power supply (0 V)

Y17
AA16
VccQ1
I/O power supply (1.8/3.3 V)

Y18
AA17
DACK1/PTM5
DMA transfer request reception/
general-purpose port
O/IO
VccQ1
Y19
Y17
CA
Chip active
I
VccQ_
RTC
Y20
AA20
Vcc_RTC
RTC power supply (1.5 V)
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 24 of 1458
O/O
VccQ1

Section 1
1.3.2
Overview
Pin Functions
Table 1.5 lists the pin functions.
Table 1.5
SH7720/SH7721 Pin Functions
Classification
Symbol
I/O
Name
Function
Power supply
Vcc

Power supply
Power supply for the internal
modules and ports for the system.
Connect all Vcc pins to the system
power supply. There will be no
operation if any pins are open.
Vss

Ground
Ground pin. Connect all Vss pins
to the system power supply (0 V).
There will be no operation if any
pins are open.
VccQ

Power supply
Power supply for I/O pins. Connect
all VccQ pins to the system power
supply. There will be no operation
if any pins are open.
VssQ

Ground
Ground pin. Connect all VssQ pins
to the system power supply (0 V).
There will be no operation if any
pins are open.
VccQ1

Power supply
Input/output power supply
(1.8/3.3 V) pin.
VssQ1

Ground
Input/output power supply (0 V)
pin.
Vcc_PLL1

PLL1 power
supply
Power supply for the on-chip PLL1
oscillator. (1.5 V)
Vss_PLL1

PLL1 ground
Ground pin for the on-chip PLL1
oscillator.
Vcc_PLL2

PLL2 power
supply
Power supply for the on-chip PLL2
oscillator. (1.5 V)
Vss_PLL2

PLL2 ground
Ground pin for the on-chip PLL2
oscillator.
EXTAL
I
External clock
For connection to a crystal
resonator. An external clock signal
may also be input.
Clock
Rev. 3.00
Jan. 18, 2008
Page 25 of 1458
REJ09B0033-0300
Section 1
Overview
Classification
Symbol
I/O
Name
Function
Clock
XTAL
O
Crystal
For connection to a crystal
resonator.
CKIO
I/O
System clock
Used as a pin to input external
clock or output clock.
I
Mode set
Sets the operating mode. Do not
change values on these pins
during operation.
Operating mode MD5 to MD0
control
MD2 to MD0 set the clock mode,
MD3 and MD4 set the bus width of
area 0 and MD5 sets the endian.
System control
Interrupts
RESETP
I
Power-on reset
When low, the system enters the
power-on reset state.
RESETM
I
Manual reset
When low, the system enters the
manual reset state.
STATUS1,
STATUS0
O
Status output
Indicates the operating state.
BREQ
I
Bus request
Low when an external device
requests the release of the bus
mastership.
BACK
O
Bus request
acknowledge
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which
has output the BREQ signal that it
has acquired the bus.
CA
I
Chip active
High in normal operation, and low
in hardware standby mode.
NMI
I
Non-maskable
interrupt
Non-maskable interrupt request
pin. Fix to high level when not in
use.
IRQ5 to IRQ0
I
Interrupt
requests 5 to 0
Maskable interrupt request pins.
Interrupt
requests 3 to 0
Maskable interrupt request pin.
IRL3 to IRL0
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
I
Page 26 of 1458
Selectable as level input or edge
input. The rising edge or falling
edge is selectable as the detection
edge. The low level or high level is
selectable as the detection level.
Input a coded interrupt level.
Section 1
Classification
Symbol
I/O
Name
Interrupts
PINT15 to
PINT0
I
Port interrupt
Port interrupt request pins
requests 15 to 0
Overview
Function
REFOUT
O
Bus request
Bus request signal for refreshing
IRQOUT
O
Bus request
Bus request signal for interrupt
Address bus
A25 to A0
O
Address bus
Outputs addresses.
Data bus
D31 to D0
I/O
Data bus
32-bit bidirectional data bus
Bus control
CS4 to CS2,
CS0
CS6A, CS6B,
CS5A, CS5B,
CE2A, CE2B,
CE1A, CE1B
O
Chip select
Chip-select signal for external
memory or devices.
RD
O
Read strobe
Indicates reading of data from
external devices.
RD/WR
O
Read/write
signal
Read/write signal
BS
O
Bus start
Bus-cycle start signal pin
BACK
O
Bus request
acknowledge
Indicates that the bus mastership
has been released to an external
device.
BREQ
I
Bus request
Low when an external device
requests the release of the bus
mastership.
WE
O
Write enable
Write enable pin for PCMCIA
WE3 (BE3)
O
Highest-byte
write
Indicates that bits 31 to 24 of the
data in the external memory or
device are being written.
WE2 (BE2)
O
Second-highest- Indicates that bits 23 to 16 of the
byte write
data in the external memory or
device are being written.
WE1 (BE1)
O
Second-lowest- Indicates that bits 15 to 8 of the
byte write
data in the external memory or
device are being written.
WE0 (BE0)
O
Lowest-byte
write
Indicates that bits 7 to 0 of the data
in the external memory or device
are being written.
CKE
O
Clock enable
Clock enable (SDRAM)
Rev. 3.00
Jan. 18, 2008
Page 27 of 1458
REJ09B0033-0300
Section 1
Overview
Classification
Symbol
I/O
Name
Bus control
CAS
O
Column address Connect to the CAS pin when the
SDRAM is connected.
DQMUU
O
DQ mask UU
Selects D31 to D24. (SDRAM)
DQMUL
O
DQ mask UL
Selects D23 to D16. (SDRAM)
DQMLU
O
DQ mask LU
Selects D15 to D8. (SDRAM)
DQMLL
O
DQ mask LL
Selects D7 to D0. (SDRAM)
RAS
O
Row address
Connect to the RAS pin when the
SDRAM is connected.
WAIT
I
Wait input
Inserts a wait cycle into the bus
cycles during access to the
external space.
IOIS16
I
16-bit IO
Indicates 16-bit I/O when PCMCIA
is in use.
ICIORD
O
IO read
Indicates I/O read when PCMCIA
is in use.
ICIOWR
O
IO write
Indicates I/O write when PCMCIA
is in use.
I
DMA-transfer
request
Input pins for external requests for
DMA transfer
O
DMA transfer
request
reception
Indicates the acceptance of DMA
transfer requests to external
devices.
O
DMA-transfer
end
Transfer end output pins for DMAC
O
TPU comparematch output
TPU compare-match output pins
TPU_TI3A to
TPU_TI2A
I
TPU clock input TPU clock input pins
TPU_TI2B to
TPU_TI3B
I
TPU clock input TPU clock input pins
O
AFE on-hook
control
AFE_FS
I
AFE frame
AFE frame synchronization signal
synchronization pin
AFE_SCLK
I
AFE shift clock
Direct memory
DREQ0,
access controller DREQ1
(DMAC)
DACK0,
DACK1
TEND0,
TEND1
16-bit timer pulse TPU_TO3 to
unit (TPU)
TPU_TO0
Analog front end AFE_RLYCNT
interface (AFEIF)
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Function
Page 28 of 1458
On-hook control pin
AFE shift clock input pin
Section 1
Classification
Symbol
I/O
Name
Function
O
AFE serial
transmission
AFE serial transmit data output pin
AFE_RDET
I
AFE ringing
signal
AFE ringing signal input pin
AFE_HC1
O
AFE hardware
control
AFE hardware control signal
AFE_RXIN
I
AFE serial
reception
AFE serial receive data
SCIF0_TxD,
SCIF1_TxD
O
SCIF transmit
data
Transmit data pins
SCIF0_RxD,
SCIF1_RxD
I
SCIF receive
data
Receive data pins
SCIF0_SCK,
SCIF1_SCK
I/O
SCIF serial
clock
Clock input/output pins
SCIF0_RTS,
SCIF1_RTS
O
SCIF transmit
request
Transmit request output pins
SCIF0_CTS,
SCIF1_CTS
I
SCIF transmit
enable
Modem control pins
IrTX
O
IrDA transmit
data
IrDA transmit data output pin
IrRX
I
IrDA receive
data
IrDA receive data input pin
SIOF0_SYNC,
SIOF1_SYNC
I/O
SIOF frame
sync
SIOF frame synchronization
signals
SIOF0_TxD,
SIOF1_TxD
O
SIOF transmit
data
SIOF transmit data pin
SIOF0_RxD,
SIOF1_RxD
I
SIOF receive
data
SIOF receive data pin
SIOF0_SCK,
SIOF1_SCK
I/O
SIOF serial
clock
SIOF serial clock pins
SIOF0_MCLK,
SIOF1_MCLK
I
SIOF master
clock
SIOF master clock input pins
I/O
IIC clock
I2C serial clock pin
I/O
IIC data
I C data input/output pin

RTC power
supply
Power supply pin for the RTC
(3.3 V)
Analog front end AFE_TXOUT
interface (AFEIF)
Serial
communication
interface with
FIFO
(SCIF)
IrDA
Serial I/O with
FIFO (SIOF)
I2C bus interface IIC_SCL
(IIC)
IIC_SDA
Realtime clock
(RTC)
Overview
VccQ_RTC
2
Rev. 3.00
Jan. 18, 2008
Page 29 of 1458
REJ09B0033-0300
Section 1
Overview
Classification
Symbol
I/O
Name
Function
Realtime clock
(RTC)
Vcc_RTC

RTC power
supply
Power supply pin for the RTC
(1.5 V)
Vss_RTC

RTC ground
Ground pin for the RTC.
EXTAL_RTC
I
RTC external
clock
Connects crystal resonator for the
RTC. Also used to input external
clock for the RTC.
XTAL_RTC
O
RTC crystal
Connects crystal resonator for the
RTC.
LCD_DATA15 O
to LCD_DATA0
LCD data
Data output pin for LCD panel
LCD_CL1
O
LCD shift clock
1
LCD shift clock 1/ horizontal sync
signal pin
LCD_CL2
O
LCD shift clock
2
LCD shift clock 2/dot clock pin
LCD_CLK
I
LCD clock
source
LCD clock source input pin
LCD_FLM
O
LCD line marker First line marker/vertical sync
signal pin
LCD_DON
O
LCD display on
LCD display on signal pin
LCD_VCPWC
O
LCD power
control (VCC)
LCD module power control (VCC)
pin
LCD_VEPWC
O
LCD power
control (VEE)
LCD module power control (VEE)
pin
LCD_M_DISP
O
LCD current
alternating
signal
LCD current alternating signal pin
PC card
PCC_BVD1
controller (PCC)
I
PCC battery
detection 1
Pin for buttery voltage detect 1/
card status change signal from PC
card
PCC_BVD2
I
PCC battery
detection 2
Pin for buttery voltage detect 2/
digital sound signal pin from PC
card
PCC_RDY
I
PCC ready
Pin for ready signal/interrupt
request signal form PC card
PCC_REG
O
PCC space
indication
Area indicate signal pin for PC
card
PCC_RESET
O
PCC reset
Reset signal pin for PC card
PCC_CD1
I
PCC card
detection 1
Pin for card detect 1 signal from
PC card
LCD controller
(LCDC)
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 30 of 1458
Section 1
Classification
Symbol
Overview
I/O
Name
Function
I
PCC card
detection 2
Pin for card detect 2 signal from
PC card
PCC_WAIT
I
PCC wait
request
PCC hardware wait request signal
pin
PCC_DRV
O
PCC buffer
control
PCC buffer control signal pin
PCC_VS1
I
PCC voltage
detection 1
Pin for voltage sense 1 signal from
PC card
PCC_VS2
I
PCC voltage
detection 2
Pin for voltage sense 2 signal from
PC card
PCC_IOIS16
I
PCC16-bit IO
Pin for write protection signal/16bit I/O signal from PC card
O
MMC open
drain control
Open drain mode control pin
O
MMC card
power control
MMC power control pin
MMC_CLK
O
MMC clock
Clock output pin
MMC_DAT
I/O
MMC data
Data input/output pin in MMC
mode
PC card
PCC_CD2
controller (PCC)
MultiMedia Card MMC_ODMOD
interface
(MMCIF)
MMC_VDDON
Response/data input pin in SPI
mode
This pin is connected to the Data
out pin on the MMC side.
MMC_CMD
I/O
MMC command Command output/response input
pin in MMC mode
Command/data output pin in SPI
mode
This pin is connected to the Data
in pin on the MMC side.
SD host interface SD_CLK
(SDHI)
SD_CMD
O
SD clock
Clock output pin
I/O
SD command
Command output/response input
pin
SD_DAT0
I/O
SD data 0
Data input/output pin
SD_DAT1
I/O
SD data 1
Data input/output pin
SD_DAT2
I/O
SD data 2
Data input/output pin
SD_DAT3
I/O
SD data 3
Data input/output pin
Rev. 3.00
Jan. 18, 2008
Page 31 of 1458
REJ09B0033-0300
Section 1
Overview
Classification
Symbol
I/O
Name
Function
SD host interface SD_CD
(SDHI)
I
SD card
detection
Card detection pin
SD_WP
I
SD write protect Write protect pin
O
SIM reset
Smart card reset output pin
O
SIM clock
Smart card clock output pin
SIM_D
I/O
SIM data
Transmit/receive data input/output
pin
AN3 to AN0
I
ADC analog
input
Analog input pin
AVcc

Analog power
supply
Power supply pin for the A/D or
D/A converter. When the A/D or
D/A converter is not in use,
connect this pin to input/output
power supply (VccQ).
AVss

Analog ground
Ground pin for the A/D or D/A
converter. Connect this pin to
input/output power supply (VssQ).
ADTRG
I
ADC external
trigger
External trigger signal for starting
A/D conversion
DA0
O
DAC analog
output
Channel 0 analog output pin
DA1
O
DAC analog
output
Channel 1 analog output pin
AVcc_USB

USB power
supply
Power supply pin for USB
AVss_USB

USB ground
Ground pin for USB
EXTAL_USB
I
USB external
clock
Connects crystal resonator for
USB. Also used to input external
clock for USB (48 MHz)
XTAL_USB
O
USB crystal
Connects a crystal resonator for
USB
USB1_ovr_
current/
USBF_VBUS
I
USB1 overcurrent/
monitor
USB port 1 over-current detection/
USB cable connection monitor pin
USB2_ovr_
current
I
USB2 overcurrent
USB port 2 over-current detection
pin
SIM card module SIM_RST
(SIM)
SIM_CLK
A/D converter
(ADC)
D/A converter
(DAC)
USB
Rev. 3.00
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REJ09B0033-0300
Page 32 of 1458
Section 1
Overview
Classification
Symbol
I/O
Name
Function
USB
USB1_pwr_en/
USBF_UPLUP
O
USB1 power
enable/pull-up
control
USB port 1 power enable control/
pull- up control output pin
SUB2_pwer_en O
USB2 power
enable
USB port 2 power enable control
pin
USB1_P
I/O
USB D+ port 1
D+ port 1 transceiver pin for USB
USB1_M
I/O
USB D− port 1
D− port 1 transceiver pin for USB
USB2_P
I/O
USB D+ port 2
D+ port 2 transceiver pin for USB
USB2_M
I/O
USB D− port 2
D− port 2 transceiver pin for USB
USB1d_DMNS
I
D− signal input
Input pin to driver for D− signal
from receiver
USB1d_
SUSPEND
O
Suspend state
Transceiver suspend state output
pin
USB1d_RCV
I
Receive data
Input pin for receive data from
differential receiver
USB1d_TXENL O
Driver output
enable
Driver output enable pin
USB1d_SPEED O
Speed control
Transceiver speed control pin
USB1d_TXSE0 O
SE0 state
SE0 state output pin
USB1d_
TXDPLS
O
D+ transmit
output
D+ transmit output pin to driver
USB1d_DPLS
I
D+ transmit
input
D+ transmit input pin to driver
PTA7 to PTA0
I/O
General
purpose port
8-bit general-purpose port pins
PTB7 to PTB0
I/O
General
purpose port
8-bit general-purpose port pins
PTC7 to PTC0
I/O
General
purpose port
8-bit general-purpose port pins
PTD7 to PTD0
I/O
General
purpose port
8-bit general-purpose port pins
PTE6, PTE5
I
General
purpose port
7-bit general-purpose port pins
PTE4 to PTE0
I/O
General
purpose port
PTF6 to PTF0
I
General
purpose port
I/O port
7-bit general-purpose port pins
Rev. 3.00
Jan. 18, 2008
Page 33 of 1458
REJ09B0033-0300
Section 1
Overview
Classification
Symbol
I/O
Name
Function
I/O port
PTG6 to PTG0
I/O
General
purpose port
7-bit general-purpose port pins
PTH6 to PTH0
I/O
General
purpose port
7-bit general-purpose port pins
PTJ6 to PTJ0
I/O
General
purpose port
7-bit general-purpose port pins
PTK3 to PTK0
I/O
General
purpose port
4-bit general-purpose port pins
PTL7 to PTL3
I/O
General
purpose port
5-bit general-purpose port pins
PTM7 to PTM0
I/O
General
purpose port
8-bit general-purpose port pins
PTP4 to PTP0
I/O
General
purpose port
5-bit general-purpose port pins
PTR7 to PTR0
I/O
General
purpose port
8-bit general-purpose port pins
PTS4 to PTS0
I/O
General
purpose port
5-bit general-purpose port pins
PTT4 to PTT0
I/O
General
purpose port
5-bit general-purpose port pins
PTU4 to PTU0
I/O
General
purpose port
5-bit general-purpose port pins
PTV4 to PTV0
I/O
General
purpose port
5-bit general-purpose port pins
TCK
I
Test clock
Test-clock input pin
TMS
I
Test mode
select
Test-mode select signal input pin
TDI
I
Test data input
Serial input pin for instructions and
data
TDO
O
Test data
output
Serial output pin for instructions
and data
TRST
I
Test reset
Initial-signal input pin
User debugging
interface
(H-UDI)
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
Page 34 of 1458
Section 1
Overview
Classification
Symbol
I/O
Name
Function
Advanced user
debugger
(AUD)
AUDATA3 to
AUDATA0
O
AUD data
Destination-address output pin in
branch-trace mode
AUDCK
O
AUD clock
Synchronous clock output pin in
branch-trace mode
AUDSYNC
O
AUD
synchronous
signal
Data start-position acknowledgesignal output pin in branch-trace
mode
ASEBRKAK
O
ASE break
mode
acknowledge
Indicates that the E10A emulator
has entered its break mode.
ASEMD0
I
ASE mode
Sets ASE mode.
E10A interface
Notes: 1. All Vcc/Vss/VccQ/VssQ/VccQ1/VssQ1/AVcc/AVss/AVcc_USB/AVss_USB/VccQ_RTC/
Vcc_RTC/Vss_RTC/Vcc_PLL1/Vss_PLL1/Vcc_PLL2/Vss_PLL2 should be connected to
the system power supply (so that power is supplied at all times.) In hardware standby
mode, the power supply to other than Vcc_RTC and VccQ_RTC can be turned off
(section 13.8).
2. Always supply power to the Vcc_RTC and VccQ_RTC, even if the RTC is not being
used.
3. Always supply power to the Vcc_PLL1 and Vcc_PLL2, even if the PLL is not being
used.
4. Drive ASEMD0 high when using the user system alone, and not using an emulator or
the H-UDI. When this pin is low or open, RESETP may be masked.
5. Drivability can be switched by the register settings of the pin function controller (PFC).
When 3.3 V is applied to VccQ1, set the drivability low. When 1.8 V is applied to
VccQ1, set the drivability high.
6. SDHI associated pins support only for the models including the SDHI.
Rev. 3.00
Jan. 18, 2008
Page 35 of 1458
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Section 1
Rev. 3.00
Overview
Jan. 18, 2008
REJ09B0033-0300
Page 36 of 1458
Section 2
Section 2
CPU
CPU
2.1
Processing States and Processing Modes
2.1.1
Processing States
This LSI supports four types of processing states: a reset state, an exception handling state, a
program execution state, and a low-power consumption state, according to the CPU processing
states.
(1)
Reset State
In the reset state, the CPU is reset. The LSI supports two types of resets: power-on reset and
manual reset. For details on resets, refer to section 7, Exception Handling.
In power-on reset, the registers and internal statuses of all LSI on-chip modules are initialized. In
manual reset, the register contents of a part of the LSI on-chip modules are retained. For details,
refer to section 37, List of Registers. The CPU internal statuses and registers are initialized both in
power-on reset and manual reset. After initialization, the program branches to address
H'A0000000 to pass control to the reset processing program to be executed.
(2)
Exception Handling State
In the exception handling state, the CPU processing flow is changed temporarily by a general
exception or interrupt exception processing. The program counter (PC) and status register (SR) are
saved in the save program counter (SPC) and save status register (SSR), respectively. The program
branches to an address obtained by adding a vector offset to the vector base register (VBR) and
passes control to the exception processing program defined by the user to be executed. For details
on reset, refer to section 7, Exception Handling.
(3)
Program Execution State
The CPU executes programs sequentially.
(4)
Low-Power Consumption State
The CPU stops operation to reduce power consumption. The power-down mode can be entered by
executing the SLEEP instruction. For details on the power-down mode, refer to section 13, PowerDown Modes.
Figure 2.1 shows a status transition diagram.
CPUS3D0S_000020020300
Rev. 3.00 Jan. 18, 2008 Page 37 of 1458
REJ09B0033-0300
Section 2
2.1.2
CPU
Processing Modes
This LSI supports two processing modes: user mode and privileged mode. These processing
modes can be determined by the processing mode bit (MD) in the status register (SR). If the MD
bit is cleared to 0, the user mode is selected. If the MD bit is set to 1, the privileged mode is
selected. The CPU enters the privileged mode by a transition to reset state or exception handling
state. In the privileged mode, any registers and resources in address spaces can be accessed.
Clearing the MD bit in the SR to 0 puts the CPU in the user mode. In the user mode, some of the
registers, including SR, and some of the address spaces cannot be accessed by the user program
and system control instructions cannot be executed. This function effectively protects the system
resources from the user program. To change the processing mode from user to privileged mode, a
transition to exception handling state is required.
Note: To call a service routine used in privileged mode from user mode, the LSI supports an
unconditional trap instruction (TRAPA). When a transition from user mode to privileged
mode occurs, the contents of the SR and PC are saved. A program execution in user mode
can be resumed by restoring the contents of the SR and PC. To return from an exception
processing program, the LSI supports an RTE instruction.
(From any states)
Power-on reset
Manual reset
Reset processing
routine starts
Reset state
Multiple
exceptions
Exception
handling
routine starts
SLEEP instruction
An exception
is accepted
Exception handling state
An exception
is accepted
Figure 2.1
Rev. 3.00 Jan. 18, 2008 Page 38 of 1458
REJ09B0033-0300
Program execution state
Low-power
consumption state
Processing State Transitions
Section 2
2.2
Memory Map
2.2.1
Virtual Address Space
CPU
The LSI supports 32-bit virtual addresses and accesses system resources using the 4-Gbytes of
virtual address space. User programs and data are accessed from the virtual address space. The
virtual address space is divided into several areas as shown in table 2.1.
(1)
P0/U0 Area
This area is called the P0 area when the CPU is in privileged mode and the U0 area when in user
mode. For the P0 and U0 areas, access using the cache is enabled. The P0 and U0 areas are
handled as address translatable areas.
If the cache is enabled, access to the P0 or U0 area is cached. If a P0 or U0 address is specified
while the address translation unit is enabled, the P0 or U0 address is translated into a physical
address based on translation information defined by the user.
If the CPU is in user mode, only the U0 area can be accessed. If P1, P2, P3, or P4 is accessed in
user mode, a transition to an address error exception occurs.
(2)
P1 Area
The P1 area is defined as a cacheable but non-address translatable area. Normally, programs
executed at high speed in privileged mode, such as exception processing handlers, which are at the
core of the operating system (OS), are assigned to the P1 area.
(3)
P2 Area
The P2 area is defined as a non-cacheable but non-address translatable area. A reset processing
program to be called from the reset state is described at the start address (H'A0000000) of the P2
area. Normally, programs such as system initialization routines and OS initiation programs are
assigned to the P2 area. To access a part of an on-chip I/O, its corresponding program should be
assigned to the P2 area.
(4)
P3 Area
The P3 area is defined as a cacheable and address translatable area. This area is used if an address
translation is required for a privileged program.
Rev. 3.00 Jan. 18, 2008 Page 39 of 1458
REJ09B0033-0300
Section 2
(5)
CPU
P4 Area
The P4 area is defined as a control area which is non-cacheable and non-address translatable. This
area can be accessed only in privileged mode. A part of the LSI’s on-chip I/O is assigned to this
area.
Table 2.1
Virtual Address Space
Address Range Name
Mode
Description
H'00000000 to
H'7FFFFFFF
Privileged/user mode
2-Gbyte physical space, cacheable, address
translatable
P0/U0
In user mode, only this address space can be
accessed.
H'80000000 to
H'9FFFFFFF
P1
Privileged mode
0.5-Gbyte physical space, cacheable
H'A0000000 to
H'BFFFFFFF
P2
Privileged mode
0.5-Gbyte physical space, non-cacheable
H'C0000000 to
H'DFFFFFFF
P3
Privileged mode
0.5-Gbyte physical space, cacheable,
address translatable
H'E0000000 to
H'FFFFFFFF
P4
Privileged mode
0.5-Gbyte control space, non-cacheable
2.2.2
External Memory Space
This LSI uses 29 bits of the 32-bit virtual address to access external memory. In this case, 0.5Gbyte of external memory space can be accessed. The external memory space is managed in area
units. Different types of memory can be connected to each area, as shown in figure 2.2. For
details, please refer to section 9, Bus State Controller (BSC).
In addition, area 1 in the external memory space is used as an on-chip I/O space where most of this
LSI’s on-chip I/Os are mapped.
Normally, the upper three bits of the 32-bit virtual address are masked and the lower 29 bits are
used for external memory addresses.*2 For example, address H'00000100 in the P0 area, address
H'80000100 in the P1 area, address H'A0000100 in the P2 area, and address H'C0000100 in the P3
area of the virtual address space are mapped into address H'00000100 of area 0 in the external
memory space. The P4 area in the virtual address space is not mapped into the external memory
address. If an address in the P4 area is accessed, an external memory cannot be accessed.
Rev. 3.00 Jan. 18, 2008 Page 40 of 1458
REJ09B0033-0300
Section 2
CPU
Notes: 1. To access an on-chip I/O mapped into area 1 in the external memory space, access the
address from the P2 area which is not cached in the virtual address space.
2. If the address translation unit is enabled, arbitrary mapping in page units can be
specified. For details, refer to section 4, Memory Management Unit (MMU).
External memory space
H'0000 0000
P0 area
Area 0
Area 1
Area 2
Area 3
Area 4
Area 5
Area 6
Area 7
H'0000 0000
U0 area
H'8000 0000
H'8000 0000
P1 area
H'A000 0000
P2 area
Address error
H'C000 0000
P3 area
H'E000 0000
P4 area
H'FFFF FFFF
H'FFFF FFFF
Privileged mode
Figure 2.2
User mode
Virtual Address to External Memory Space Mapping
Rev. 3.00 Jan. 18, 2008 Page 41 of 1458
REJ09B0033-0300
Section 2
2.3
CPU
Register Descriptions
This LSI provides thirty-three 32-bit registers: 24 general registers, five control registers, three
system registers, and one program counter.
(1) General Registers
This LSI incorporates 24 general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to
R7_BANK1 and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB)
bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1) are accessed as general registers.
(2) System Registers
This LSI incorporates the multiply and accumulate registers (MACH/MACL) and procedure
register (PR) as system registers. These registers can be accessed regardless of the processing
mode.
(3) Program Counter
The program counter stores the value obtained by adding 4 to the current instruction address.
(4) Control Registers
This LSI incorporates the status register (SR), global base register (GBR), save status register
(SSR), save program counter (SPC), and vector base register as control register. Only the GBR can
be accessed in user mode. Control registers other than the GBR can be accessed only in privileged
mode.
Rev. 3.00 Jan. 18, 2008 Page 42 of 1458
REJ09B0033-0300
Section 2
CPU
Table 2.2 shows the register values after reset. Figure 2.3 shows the register configurations in each
process mode.
Table 2.2
Register Initial Values
Register Type
General registers
Registers
Initial Values*
R0_BANK0 to R7_BANK0,
Undefined
R0_BANK1 to R7_BANK1,
R8 to R15
System registers
MACH, MACL, PR
Undefined
Program counter
PC
H'A0000000
Control registers
SR
MD bit = 1, RB bit = 1, BL bit = 1, I3 to I0 bits
= H'F (1111), reserved bits = all 0, other bits =
undefined
GBR, SSR, SPC
Undefined
VBR
H'00000000
Note:
*
Initialized by a power-on or manual reset.
Rev. 3.00 Jan. 18, 2008 Page 43 of 1458
REJ09B0033-0300
Section 2
CPU
31
0
31
0
31
0
R0_BANK0*1,*2
R1_BANK0*2
R2_BANK0*2
R3_BANK0*2
R4_BANK0*2
R5_BANK0*2
R6_BANK0*2
R7_BANK0*2
R8
R9
R10
R11
R12
R13
R14
R15
R0_BANK1*1,*3
R1_BANK1*3
R2_BANK1*3
R3_BANK1*3
R4_BANK1*3
R5_BANK1*3
R6_BANK1*3
R7_BANK1*3
R8
R9
R10
R11
R12
R13
R14
R15
R0_BANK0*1,*4
R1_BANK0*4
R2_BANK0*4
R3_BANK0*4
R4_BANK0*4
R5_BANK0*4
R6_BANK0*4
R7_BANK0*4
R8
R9
R10
R11
R12
R13
R14
R15
SR
SR
SSR
SR
SSR
GBR
MACH
MACL
PR
GBR
MACH
MACL
PR
VBR
GBR
MACH
MACL
PR
PC
SPC
PC
SPC
R0_BANK0*1,*4
R1_BANK0*4
R2_BANK0*4
R3_BANK0*4
R4_BANK0*4
R5_BANK0*4
R6_BANK0*4
R7_BANK0*4
R0_BANK1*1,*3
R1_BANK1*3
R2_BANK1*3
R3_BANK1*3
R4_BANK1*3
R5_BANK1*3
R6_BANK1*3
R7_BANK1*3
(b) Privileged mode register
configuration (RB = 1)
(c) Privileged mode register
configuration (RB = 0)
PC
(a) User mode register
configuration
VBR
Notes: 1. The R0 register is used as an index register in indexed register indirect addressing mode
and indexed GBR indirect addressing mode.
2. Bank register
3. Bank register
Accessed as a general register when the RB bit is set to 1 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is cleared to 0.
4. Bank register
Accessed as a general register when the RB bit is cleared to 0 in the SR register.
Accessed only by LDC/STC instructions when the RB bit is set to 1.
Figure 2.3
Register Configuration in Each Processing Mode
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REJ09B0033-0300
Section 2
2.3.1
CPU
General Registers
There are twenty-four 32-bit general registers: R0_BANK0 to R7_BANK0, R0_BANK1 to
R7_BANK1, and R8 to R15. R0 to R7 are banked. The process mode and the register bank (RB)
bit in the status register (SR) define which set of banked registers (R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1) are accessed as general registers. R0 to R7 registers in the selected
bank are accessed as R0 to R7. R0 to R7 in the non-selected bank is accessed as R0_BANK to
R7_BANK by the control register load instruction (LDC) and control register store instruction
(STC).
In user mode, bank 0 is selected regardless of the RB bit value. Sixteen registers: R0_BANK0 to
R7_BANK0 and R8 to R15 are accessed as general registers R0 to R15. The R0_BANK1 to
R7_BANK1 registers in bank 1 cannot be accessed.
In privileged mode that is entered by a transition to exception handling state, the RB bit is set to 1
to select bank 1. In privileged mode, sixteen registers: R0_BANK1 to R7_BANK1 and R8 to R15
are accessed as general registers R0 to R15. A bank is switched automatically when an exception
handling state is entered, registers R0 to R7 need not be saved by the exception handling routine.
The R0_BANK0 to R7_BANK0 registers in bank 0 can be accessed as R0_BANK to R7_BANK
by the LDC and STC instructions.
In privileged mode, bank 0 can also be used as general registers by clearing the RB bit to 0. In this
case, sixteen registers: R0_BANK0 to R7_BANK0 and R8 to R15 are accessed as general
registers R0 to R15. The R0_BANK1 to R7_BANK1 registers in bank 1 can be accessed as
R0_BANK to R7_BANK by the LDC and STC instructions.
The general registers R0 to R15 are used as equivalent registers for almost all instructions. In
some instructions, the R0 register is automatically used or only the R0 register can be used as
source or destination registers.
Rev. 3.00 Jan. 18, 2008 Page 45 of 1458
REJ09B0033-0300
Section 2
CPU
31
0
R0*1,*2
General Registers: Undefined after reset
R1*2
Notes: 1. R0 functions as an index register in the indexed
register-indirect addressing mode and indexed
GBR-indirect addressing mode. In some
instructions, only R0 can be used as the source
or destination register.
2. R0 to R7 are banked registers. In privileged
mode, either R0_BANK0 to R7_BANK0 or
R0_BANK1 to R7_BANK1 is selected by the
RB bit in the SR register.
R2*2
R3*2
R4*2
R5*2
R6*2
R7*2
R8
R9
R10
R11
R12
R13
R14
R15
Figure 2.4
2.3.2
General Registers
System Registers
The system registers: multiply and accumulate registers (MACH/MACL) and procedure register
(PR) as system registers can be accessed by the LDS and STS instructions.
(1)
Multiply and Accumulate Registers (MACH/MACL)
The multiply and accumulate registers (MACH/MACL) store the results of multiplication and
accumulation instructions or multiplication instructions. The MACH/MACL registers also store
addition values for the multiplication and accumulations. After reset, these registers are undefined.
The MACH and MACL registers store upper 32 bits and lower 32 bits, respectively.
(2)
Procedure Register (PR)
The procedure register (PR) stores the return address for a subroutine call using the BSR, BSRF,
or JSR instruction. The return address stored in the PR register is restored to the program counter
(PC) by the RTS (return from the subroutine) instruction. After reset, this register is undefined.
Rev. 3.00 Jan. 18, 2008 Page 46 of 1458
REJ09B0033-0300
Section 2
2.3.3
CPU
Program Counter
The program counter (PC) stores the value obtained by adding 4 to the current instruction address.
There is no instruction to read the PC directly. Before an exception handling state is entered, the
PC is saved in the save program counter (SPC). Before a subroutine call is executed, the PC is
saved in the procedure register (PR). In addition, the PC can be used for PC relative addressing
mode.
Figure 2.5 shows the system register and program counter configurations.
Multiply and accumulate high and low registers (MACH/MACL)
31
0
MACH
MACL
Procedure register (PR)
31
0
PR
Program counter (PC)
31
0
PC
Figure 2.5
System Registers and Program Counter
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REJ09B0033-0300
Section 2
2.3.4
CPU
Control Registers
The control registers (SR, SSR, SPC, GBR, and VBR) can be accessed by the LDC or STC
instruction in privileged mode. The GBR register can be accessed in the user mode.
The control registers are described below.
(1)
Status Register (SR)
The status register (SR) indicates the system status as shown below. The SR register can be
accessed only in privileged mode.
Bit
Bit Name
Initial
Value
R/W
Description
31

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
30
MD
1
R/W
Processing Mode
Indicates the CPU processing mode.
0: User mode
1: Privileged mode
The MD bit is set to 1 in reset or exception handling
state.
29
RB
1
R/W
Register Bank
The general registers R0 to R7 are banked registers.
0: In this case, R0_BANK0 to R7_BANK0 and R8 to
R15 are used as general registers.
R0_BANK1 to R7_BANK1 can be accessed by the
LDC or STR instruction.
1: In this case, R0_BANK1 to R7_BANK1 and R8 to
R15 are used as general registers.
R0_BANK0 to R7_BANK0 can be accessed by the
LDC or STR instruction.
The RB bit is set to 1 in reset or exception handling
state.
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REJ09B0033-0300
Section 2
Bit
Bit Name
Initial
Value
R/W
Description
28
BL
1
R/W
Block
CPU
Specifies whether an exception, interrupt, or user
break is enabled or not.
0: Enables an exception, interrupt, or user break.
1: Disables an exception, interrupt, or user break.
The BL bit is set to 1 in reset or exception handling
state.
27 to 10

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
M

R/W
M Bit
8
Q

R/W
Q Bit
These bits are used by the DIV0S, DIV0U, and DIV1
instructions. These bits can be changed even in user
mode by using the DIV0S, DIV0U, and DIV1
instructions. These bits are undefined at reset. These
bits do not change in an exception handling state.
7 to 4
I3 to I0
All 1
R/W
Interrupt Mask
Indicates the interrupt mask level. These bits do not
change even if an interrupt occurs. At reset, these bits
are initialized to B'1111. These bits are not affected in
an exception handling state.
3, 2

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
S

R/W
Saturation Mode
Specifies the saturation mode for multiply instructions
or multiply and accumulate instructions. This bit can be
specified by the SETS and CLRS instructions in user
mode.
At reset, this bit is undefined. This bit is not affected in
an exception handling state.
Rev. 3.00 Jan. 18, 2008 Page 49 of 1458
REJ09B0033-0300
Section 2
CPU
Bit
Bit Name
Initial
Value
R/W
Description
0
T

R/W
T Bit
Indicates true or false for compare instructions or carry
or borrow occurrence for an operation instruction with
carry or borrow. This bit can be specified by the SETT
and CLRT instructions in user mode.
At reset, this bit is undefined. This bit is not affected in
an exception handling state.
Note: The M, Q, S, and T bits can be set/cleared by the user mode specific instructions. Other bits
can be read or written in privileged mode.
(2)
Save Status Register (SSR)
The save status register (SSR) can be accessed only in privileged mode. Before entering the
exception, the contents of the SR register is stored in the SSR register. At reset, the SSR initial
value is undefined.
(3)
Save Program Counter (SPC)
The save program counter (SPC) can be accessed only in privileged mode. Before entering the
exception, the contents of the PC is stored in the SPC. At reset, the SPC initial value is undefined.
(4)
Global Base Register (GBR)
The global base register (GBR) is referenced as a base register in GBR indirect addressing mode.
At reset, the GBR initial value is undefined.
(5)
Vector Base Register (VBR)
The vector base register (VBR) can be accessed only in privileged mode. If a transition from reset
state to exception handling state occurs, this register is referenced as a base address. For details,
refer to section 7, Exception Handling. At reset, the VBR is initialized as H'00000000.
Rev. 3.00 Jan. 18, 2008 Page 50 of 1458
REJ09B0033-0300
Section 2
CPU
Figure 2.6 shows the control register configuration.
Save status register (SSR)
31
SSR
0
Save program counter (SPC)
31
SPC
0
Global base register (GBR)
31
GBR
0
Vector base register (VBR)
31
VBR
0
Status register (SR)
31
0 MD RB BL 0
Figure 2.6
2.4
Data Formats
2.4.1
Register Data Format
0
0 M Q I3 I2 I1 I0 0 0 S T
Control Register Configuration
Register operands are always longwords (32 bits). When the memory operand is only a byte (8
bits) or a word (16 bits), it is sign-extended into a longword when loaded into a register.
31
0
Longword
Rev. 3.00 Jan. 18, 2008 Page 51 of 1458
REJ09B0033-0300
Section 2
2.4.2
CPU
Memory Data Formats
Memory data formats are classified into byte, word, and longword. Memory can be accessed in
byte, word, and longword. When the memory operand is only a byte (8 bits) or a word (16 bits), it
is sign-extended into a longword when loaded into a register.
An address error will occur if word data starting from an address other than 2n or longword data
starting from an address other than 4n is accessed. In such cases, the data accessed cannot be
guaranteed.
When a word or longword operand is accessed, the byte positions on the memory corresponding to
the word or longword data on the register is determined to the specified endian mode (big endian
or little endian).
Figure 2.7 shows a byte correspondence in big endian mode. In big endian mode, the MSB byte in
the register corresponds to the lowest address in the memory, and the LSB the in the register
corresponds to the highest address. For example, if the contents of the general register R0 is stored
at an address indicated by the general register R1 in longword, the MSB byte of the R0 is stored at
the address indicated by the R1 and the LSB byte of the R1 register is stored at the address
indicated by the (R1 +3).
The on-chip device registers assigned to memory are accessed in big endian mode. Note that the
available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In big endian mode,
the instruction code must be stored from upper byte to lower byte in this order from the
word boundary of the memory.
31
23
15
Byte position
in R0
Byte position
in memory
7
0
[15:8]
[7:0]
[7:0]
[15:8]
@(R1+0) @(R1+1) @(R1+2) @(R1+3)
(a) Byte access
Example: MOV.W R0, @R1
(R1 = Address 4n)
[31:24]
[23:16]
[15:8]
[7:0]
[31:24]
[23:16]
[15:8]
[7:0]
@(R1+0) @(R1+1) @(R1+2) @(R1+3)
(c) Longword access
Example: MOV.L R0, @R1
(R1 = Address 4n)
Data Format on Memory (Big Endian Mode)
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REJ09B0033-0300
[7:0]
@(R1+0) @(R1+1) @(R1+2) @(R1+3)
(b) Word access
Example: MOV.B R0, @R1
(R1 = Address 4n)
Figure 2.7
[7:0]
Section 2
CPU
The little endian mode can also be specified as data format. Either big-endian or little-endian mode
can be selected according to the MD5 pin at reset. When MD5 is low at reset, the processor
operates in big-endian mode. When MD5 is high at reset, the processor operates in little-endian
mode. The endian mode cannot be modified dynamically.
In little endian mode, the MSB byte in the register corresponds to the highest address in the
memory, and the LSB the in the register corresponds to the lowest address (figure 2.8). For
example, if the contents of the general register R0 is stored at an address indicated by the general
register R1 in longword, the MSB byte of the R0 is stored at the address indicated by the (R1+3)
and the LSB byte of the R1 register is stored at the address indicated by the R1.
If the little endian mode is selected, the on-chip memory are accessed in little endian mode.
However, the on-chip device registers assigned to memory are accessed in big endian mode. Note
that the available access size (byte, word, or long word) differs in each register.
Note: The CPU instruction codes of this LSI must be stored in word units. In little endian mode,
the instruction code must be stored from lower byte to upper byte in this order from the
word boundary of the memory.
31
23
15
Byte position
in R0
7
0
[7:0]
Byte position
in memory
[7:0]
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
(a) Byte access
[7:0]
[15:8]
[7:0]
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
(b) Word access
Example: MOV.B R0, @R1
(R1 = Address 4n)
Figure 2.8
[15:8]
[31:24]
[23:16]
[15:8]
[7:0]
[31:24]
[23:16]
[15:8]
[7:0]
@(R1+3) @(R1+2) @(R1+1) @(R1+0)
(c) Longword access
Example: MOV.W R0, @R1
(R1 = Address 4n)
Example: MOV.L R0, @R1
(R1 = Address 4n)
Data Format on Memory (Little Endian Mode)
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REJ09B0033-0300
Section 2
CPU
2.5
Features of CPU Core Instructions
2.5.1
Instruction Execution Method
(1)
Instruction Length
All instructions have a fixed length of 16 bits and are executed in the sequential pipeline. In the
sequential pipeline, almost all instructions can be executed in one cycle. All data items are handles
in longword (32 bits). Memory can be accessed in byte, word, or longword. In this case, Memory
byte or word data is sign-extended and operated on as longword data. Immediate data is signextended to longword size for arithmetic operations (MOV, ADD, and CMP/EQ instructions) or
zero-extended to longword size for logical operations (TST, AND, OR, and XOR instructions).
(2)
Load/Store Architecture
Basic operations are executed between registers. In operations involving memory, data is first
loaded into a register (load/store architecture). However, bit manipulation instructions such as
AND are executed directly on memory.
(3)
Delayed Branching
Unconditional branch instructions are executed as delayed branches. With a delayed branch
instruction, the branch is made after execution of the instruction (called the slot instruction)
immediately following the delayed branch instruction. This minimizes disruption of the pipeline
when a branch is made.
This LSI supports two types of conditional branch instructions: delayed branch instruction or
normal branch instruction.
Example:
BRA
TARGET
ADD
R1, R0
the
Rev. 3.00 Jan. 18, 2008 Page 54 of 1458
REJ09B0033-0300
; ADD is executed before branching to
TARGET
Section 2
(4)
CPU
T Bit
The result of a comparison is indicated by the T bit in the status register (SR), and a conditional
branch is performed according to whether the result is True or False. Processing speed has been
improved by keeping the number of instructions that modify the T bit to a minimum.
Example:
ADD
ADD
#1, R0
; The T bit cannot be modified by the
instruction
CMP/EQ
#0, R0
; The T bit is set to 1 if R0 is 0.
BT
TARGET
; Branch to TARGET if the T bit is set
1 (R0=0).
to
(5)
Literal Constant
Byte literal constant is placed inside the instruction code as immediate data. Since the instruction
length is fixed to 16 bits, word and longword literal constant is not placed inside the instruction
code, but in a table in memory. The table in memory is referenced with a MOV instruction using
PC-relative addressing mode with displacement.
Example:
(6)
MOV.W
@(disp, PC), R0
Absolute Addresses
When data is referenced by absolute address, the absolute address value is placed in a table in
memory beforehand as well as word or longword literal constant. Using the method whereby
immediate data is loaded when an instruction is executed, this value is transferred to a register and
the data is referenced using register indirect addressing mode.
(7)
16-Bit/32-Bit Displacement
When data is referenced with a 16- or 32-bit displacement, the displacement value is placed in a
table in memory beforehand. Using the method whereby word or longword immediate data is
loaded when an instruction is executed, this value is transferred to a register and the data is
referenced using indexed register indirect addressing mode.
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REJ09B0033-0300
Section 2
2.5.2
CPU
CPU Instruction Addressing Modes
The following table shows addressing modes and effective address calculation methods for
instructions executed by the CPU core.
Table 2.3
Addressing Modes and Effective Addresses for CPU Instructions
Addressing
Mode
Instruction
Format
Effective Address Calculation Method
Calculation Formula
Register
direct
Rn
Effective address is register Rn.

Register
indirect
@Rn
Register
indirect with
post-increment
@Rn+
(Operand is register Rn contents.)
Effective address is register Rn contents.
Rn
Rn
Rn
Effective address is register Rn contents. A
constant is added to Rn after instruction
execution: 1 for a byte operand, 2 for a word
operand, 4 for a longword operand.
Rn
Rn
Rn
After instruction execution
Byte: Rn + 1 → Rn
Word: Rn + 2 → Rn
Longword: Rn + 4 → Rn
Rn + 1/2/4
+
1/2/4
Register
indirect with
pre-decrement
@–Rn
Effective address is register Rn contents,
decremented by a constant beforehand: 1 for a
byte operand, 2 for a word operand, 4 for a
longword operand.
Rn - 1/2/4
-
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REJ09B0033-0300
Word: Rn – 2 → Rn
Longword: Rn – 4 → Rn
(Instruction executed with
Rn after calculation)
Rn
1/2/4
Byte: Rn – 1 → Rn
Rn - 1/2/4
Section 2
Addressing
Mode
Instruction
Format
Register
indirect with
displacement
@(disp:4,
Rn)
Effective Address Calculation Method
CPU
Calculation Formula
Effective address is register Rn contents with 4-bit Byte: Rn + disp
displacement disp added. After disp is zeroWord: Rn + disp × 2
extended, it is multiplied by 1 (byte), 2 (word), or 4
Longword: Rn + disp × 4
(longword), according to the operand size.
Rn
+
disp
(zero-extended)
Rn
+ disp × 1/2/4
×
1/2/4
Indexed
register indirect
@(R0, Rn)
Effective address is sum of register Rn
and R0 contents.
Rn + R0
Rn
+
Rn + R0
R0
GBR indirect with @(disp:8,
displacement
GBR)
Effective address is register GBR contents with 8bit displacement disp added. After disp is zeroextended, it is multiplied by 1 (byte), 2 (word), or 4
(longword), according to the
operand size.
Byte: GBR + disp
Word: GBR + disp × 2
Longword:
GBR + disp × 4
GBR
disp
+
(Zero-extended)
GBR
+ disp × 1/2/4
×
1/2/4
Indexed GBR
indirect
@(R0, GBR) Effective address is sum of register GBR and R0
contents.
GBR + R0
GBR
+
GBR + R0
R0
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REJ09B0033-0300
Section 2
CPU
Addressing
Mode
Instruction
Format
PC-relative with
displacement
@(disp:8,
PC)
Effective Address Calculation Method
Calculation Formula
Effective address is PC with 8-bit displacement disp
added. After disp is zero-extended, it is multiplied
by 2 (word) or 4 (longword), according to the
operand size. With a longword operand, the lower 2
bits of PC are masked.
Word: PC + disp × 2
Longword:
PC&H'FFFFFFFC
+ disp × 4
PC
&
H'FFFFFFFC
*
+
disp
PC + disp × 2
or
PC &
H'FFFFFFFC
+ disp × 4
(zero-extended)
×
*: With longword operand
2/4
PC-relative
disp:8
Effective address is PC with 8-bit displacement disp PC + disp × 2
added after being sign-extended and multiplied by
2.
PC
disp
+
PC + disp × 2
(sign-extended)
×
2
disp:12
PC + disp × 2
Effective address is PC with 12-bit displacement
disp added after being sign-extended and multiplied
by 2
PC
disp
+
PC + disp × 2
(sign-extended)
×
2
Rn
Effective address is sum of PC and Rn.
PC
+
Rn
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REJ09B0033-0300
PC + Rn
PC + Rn
Section 2
Addressing
Mode
Instruction
Format
Immediate
CPU
Effective Address Calculation Method
Calculation Formula
#imm:8
8-bit immediate data imm of TST, AND, OR, or
XOR instruction is zero-extended.

#imm:8
8-bit immediate data imm of MOV, ADD, or
CMP/EQ instruction is sign-extended.

#imm:8
8-bit immediate data imm of TRAPA instruction is
zero-extended and multiplied by 4.

Note: For addressing modes with displacement (disp) as shown below, the assembler description
in this manual indicates the value before it is scaled (x1, x2, or x4) according to the operand
size to clarify the LSI operation. For details on assembler description, refer to the
description rules in each assembler.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR)
; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp:12 ; PC relative
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REJ09B0033-0300
Section 2
2.5.3
CPU
Instruction Formats
Table 2.4 shows the instruction formats, and the meaning of the source and destination operands,
for instructions executed by the CPU core. The meaning of the operands depends on the
instruction code. The following symbols are used in the table.
Table 2.4
xxxx:
Instruction code
mmmm:
Source register
nnnn:
Destination register
iiii:
Immediate data
dddd:
Displacement
CPU Instruction Formats
Instruction Format
Source Operand
Destination
Operand
Sample Instruction
0 type


NOP

nnnn: register
direct
MOVT Rn
15
0
xxxx xxxx xxxx xxxx
n type
15
0
xxxx nnnn xxxx xxxx
Control register or nnnn: register
system register
direct
m type
15
0
xxxx mmmm xxxx xxxx
STS
Control register or nnnn: preSTC.L
system register
decrement register
indirect
SR,@-Rn
mmmm: register
direct
Rm,SR
Control register or LDC
system register
mmmm: postControl register or LDC.L
increment register system register
indirect
@Rm+,SR
mmmm: register
indirect

JMP
@Rm
PC-relative using
Rm

BRAF
Rm
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REJ09B0033-0300
MACH,Rn
Section 2
Instruction Format
Source Operand
Destination
Operand
nm type
mmmm: register
direct
nnnn: register
direct
ADD
mmmm: register
indirect
nnnn: register
indirect
MOV.L Rm,@Rn
15
0
xxxx nnnn mmmm xxxx
mmmm: postMACH, MACL
increment register
indirect (multiplyand-accumulate
operation)
CPU
Sample Instruction
Rm,Rn
MAC.W @Rm+,@Rn+
nnnn: * postincrement register
indirect (multiplyand-accumulate
operation)
mmmm: postnnnn: register
increment register direct
indirect
md type
15
0
xxxx xxxx mmmm dddd
nd4 type
15
0
xxxx xxxx nnnn dddd
nmd type
15
0
xxxx nnnn mmmm dddd
MOV.L @Rm+,Rn
mmmm: register
direct
nnnn: preMOV.L Rm,@-Rn
decrement register
indirect
mmmm: register
direct
nnnn: indexed
register indirect
mmmmdddd:
register indirect
with displacement
R0 (register direct) MOV.B @(disp,Rm),R0
MOV.L Rm,@(R0,Rn)
R0 (register direct) nnnndddd:
register indirect
with displacement
MOV.B R0,@(disp,Rn)
mmmm: register
direct
nnnndddd:
register indirect
with displacement
MOV.L Rm,@(disp,Rn)
mmmmdddd:
register indirect
with displacement
nnnn: register
direct
MOV.L @(disp,Rm),Rn
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REJ09B0033-0300
Section 2
CPU
Instruction Format
Source Operand
d type
dddddddd: GBR
indirect with
displacement
15
0
xxxx xxxx dddd dddd
Destination
Operand
Sample Instruction
R0 (register direct) MOV.L @(disp,GBR),R0
R0 (register direct) dddddddd: GBR
indirect with
displacement
MOV.L R0,@(disp,GBR)
dddddddd:
PC-relative with
displacement
R0 (register direct) MOVA @(disp,PC),R0
dddddddd:
PC-relative

BF
label
dddddddddddd:
PC-relative

BRA
label
(label=disp+PC)
dddddddd: PCrelative with
displacement
nnnn: register
direct
MOV.L @(disp,PC),Rn
15
0
xxxx nnnn dddd dddd
i type
iiiiiiii: immediate
Indexed GBR
indirect
AND.B #imm,@(R0,GBR)
iiiiiiii: immediate
R0 (register direct) AND
iiiiiiii: immediate

TRAPA #imm
iiiiiiii: immediate
nnnn: register
direct
ADD
d12 type
15
0
xxxx dddd dddd dddd
nd8 type
15
xxxx xxxx
0
iiii
iiii
ni type
15
xxxx nnnn i i i i
Note:
*
0
iiii
In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 3.00 Jan. 18, 2008 Page 62 of 1458
REJ09B0033-0300
#imm,R0
#imm,Rn
Section 2
2.6
Instruction Set
2.6.1
Instruction Set Based on Functions
CPU
Table 2.5 shows the instructions classified by function.
Table 2.5
Type
Data transfer
instructions
Arithmetic
operation
instructions
CPU Instruction Types
Kinds of
Instruction
Op Code
Function
Number of
Instructions
5
MOV
Data transfer
39
MOVA
Effective address transfer
MOVT
T bit transfer
SWAP
Upper/lower swap
XTRCT
Extraction of middle of linked registers
ADD
Binary addition
ADDC
Binary addition with carry
ADDV
Binary addition with overflow check
CMP/cond
Comparison
DIV1
Division
DIV0S
Signed division initialization
DIV0U
Unsigned division initialization
DMULS
Signed double-precision multiplication
DMULU
Unsigned double-precision multiplication
DT
Decrement and test
EXTS
Sign extension
21
33
EXTU
Zero extension
MAC
Multiply-and-accumulate, doubleprecision multiply-and-accumulate
MUL
Double-precision multiplication
(32 × 32 bits)
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REJ09B0033-0300
Section 2
CPU
Type
Arithmetic
operation
instructions
Logic
operation
instructions
Shift
instructions
Kinds of
Instruction
Op Code
Function
Number of
Instructions
21
MULS
Signed multiplication (16 × 16 bits)
33
MULU
Unsigned multiplication (16 × 16 bits)
NEG
Sign inversion
NEGC
Sign inversion with borrow
SUB
Binary subtraction
SUBC
Binary subtraction with borrow
SUBV
Binary subtraction with underflow
AND
Logical AND
NOT
Bit inversion
OR
Logical OR
TAS
Memory test and bit setting
TST
Logical AND and T bit setting
XOR
Exclusive logical OR
ROTCL
1-bit left shift with T bit
ROTCR
1-bit right shift with T bit
ROTL
1-bit left shift
ROTR
1-bit right shift
SHAD
Arithmetic dynamic shift
SHAL
Arithmetic 1-bit left shift
SHAR
Arithmetic 1-bit right shift
6
12
SHLD
Logical dynamic shift
SHLL
Logical 1-bit left shift
SHLLn
Logical n-bit left shift
SHLR
Logical 1-bit right shift
SHLRn
Logical n-bit right shift
Rev. 3.00 Jan. 18, 2008 Page 64 of 1458
REJ09B0033-0300
14
16
Section 2
Type
Branch
instructions
System
control
instructions
Total:
Kinds of
Instruction
Op Code
Function
9
BF
Conditional branch, delayed conditional 11
branch (T = 0)
BT
Conditional branch, delayed conditional
branch (T = 1)
BRA
Unconditional branch
BRAF
Unconditional branch
BSR
Branch to subroutine procedure
BSRF
Branch to subroutine procedure
JMP
Unconditional branch
JSR
Branch to subroutine procedure
RTS
Return from subroutine procedure
CLRMAC
MAC register clear
CLRS
S bit clear
CLRT
T bit clear
LDC
Load into control register
LDS
Load into system register
LDTLB
PTEH/PTEL load into TLB
NOP
No operation
15
68
CPU
Number of
Instructions
PREF
Data prefetch to cache
RTE
Return from exception handling
SETS
S bit setting
SETT
T bit setting
SLEEP
Transition to power-down mode
STC
Store from control register
STS
Store from system register
TRAPA
Trap exception handling
75
188
The instruction code, operation, and number of execution states of the CPU instructions are shown
in the following tables, classified by instruction type, using the format shown below.
Rev. 3.00 Jan. 18, 2008 Page 65 of 1458
REJ09B0033-0300
Section 2
CPU
Instruction
Instruction Code
Operation
Privilege
Indicated by mnemonic.
Indicated in MSB ↔
LSB order.
Indicates summary of
operation.
Indicates a
privileged
instruction.
Explanation of Symbols
Explanation of Symbols
Explanation of Symbols
OP.Sz SRC, DEST
OP:
Operation code
Sz:
Size
SRC: Source
DEST: Destination
mmmm: Source register
→, ←:
Transfer direction
nnnn: Destination register
0000: R0
0001: R1
.........
(xx):
Memory operand
Rm:
Source register
Rn:
Destination register
imm: Immediate data
1111: R15
iiii:
Immediate data
dddd:
Displacement*2
disp: Displacement
Execution
States
Value
when no
wait states
are
inserted*1
T Bit
Value of T
bit after
instruction
is executed
Explanation
of Symbols
: No
change
M/Q/T: Flag bits in SR
&:
Logical AND of each bit
|:
Logical OR of each bit
^:
Exclusive logical OR of
each bit
~:
Logical NOT of each bit
<<n: n-bit left shift
>>n: n-bit right shift
Notes: 1. The table shows the minimum number of execution states. In practice, the number of
instruction execution states will be increased in cases such as the following:
a.
When there is a conflict between an instruction fetch and a data access
b.
When the destination register of a load instruction (memory → register) is also
used by the following instruction
2. Scaled (x1, x2, or x4) according to the instruction operand size, etc.
Rev. 3.00 Jan. 18, 2008 Page 66 of 1458
REJ09B0033-0300
Section 2
Table 2.6
CPU
Data Transfer Instructions
Privileged
Mode
Cycles T Bit
imm → Sign extension → Rn
–
1
–
1001nnnndddddddd
(disp x 2+PC)→Sign
extension → Rn
–
1
–
@(disp,PC),Rn
1101nnnndddddddd
(disp x 4+PC)→Rn
–
1
–
Rm,Rn
0110nnnnmmmm0011
Rm→Rn
–
1
–
MOV.B Rm,@Rn
0010nnnnmmmm0000
Rm→(Rn)
–
1
–
MOV.W Rm,@Rn
0010nnnnmmmm0001
Rm→(Rn)
–
1
–
MOV.L
Rm,@Rn
0010nnnnmmmm0010
Rm→(Rn)
–
1
–
MOV.B @Rm,Rn
0110nnnnmmmm0000
(Rm)→Sign extension→Rn
–
1
–
MOV.W @Rm,Rn
0110nnnnmmmm0001
(Rm)→Sign extension→Rn
–
1
–
MOV.L
0110nnnnmmmm0010
(Rm)→Rn
–
1
–
MOV.B Rm,@–Rn
0010nnnnmmmm0100
Rn–1→Rn, Rm→(Rn)
–
1
–
MOV.W Rm,@–Rn
0010nnnnmmmm0101
Rn–2→Rn, Rm→(Rn)
–
1
–
MOV.L
Instruction
Instruction Code Operation
MOV
1110nnnniiiiiiii
MOV.W @(disp,PC),Rn
MOV.L
MOV
#imm,Rn
@Rm,Rn
Rm,@–Rn
0010nnnnmmmm0110
Rn–4→Rn, Rm→(Rn)
–
1
–
MOV.B @Rm+,Rn
0110nnnnmmmm0100
(Rm)→Sign extension→Rn,
Rm+1→Rm
–
1
–
MOV.W @Rm+,Rn
0110nnnnmmmm0101
(Rm)→Sign extension→Rn,
Rm+2→Rm
–
1
–
MOV.L
0110nnnnmmmm0110
(Rm)→Rn, Rm+4→Rm
–
1
–
MOV.B R0,@(disp,Rn)
10000000nnnndddd
R0→(disp+Rn)
–
1
–
MOV.W R0,@(disp,Rn)
10000001nnnndddd
R0→(disp x 2+Rn)
–
1
–
MOV.L
Rm,@(disp,Rn)
0001nnnnmmmmdddd
Rm→(disp x 4+Rn)
–
1
–
MOV.B @(disp,Rm),R0
10000100mmmmdddd
(disp+Rm)→Sign
extension→R0
–
1
–
MOV.W @(disp,Rm),R0
10000101mmmmdddd
(disp x 2+Rm)→Sign
extension→R0
–
1
–
MOV.L
0101nnnnmmmmdddd
(disp x 4+Rm)→Rn
–
1
–
MOV.B Rm,@(R0,Rn)
0000nnnnmmmm0100
Rm→(R0+Rn)
–
1
–
MOV.W Rm,@(R0,Rn)
0000nnnnmmmm0101
Rm→(R0+Rn)
–
1
–
MOV.L
0000nnnnmmmm0110
Rm→(R0+Rn)
–
1
–
@Rm+,Rn
@(disp,Rm),Rn
Rm,@(R0,Rn)
Rev. 3.00 Jan. 18, 2008 Page 67 of 1458
REJ09B0033-0300
Section 2
CPU
Privileged
Mode
Cycles
T Bit
(R0+Rm)→Sign
extension→Rn
–
1
–
0000nnnnmmmm1101
(R0+Rm)→Sign
extension→Rn
–
1
–
@(R0,Rm),Rn
0000nnnnmmmm1110
(R0+Rm)→Rn
–
1
–
MOV.B
R0,@(disp,GBR)
11000000dddddddd
R0→(disp+GBR)
–
1
–
MOV.W
R0,@(disp,GBR)
11000001dddddddd
R0→(disp x 2+GBR)
–
1
–
MOV.L
R0,@(disp,GBR)
11000010dddddddd
R0→(disp x 4+GBR)
–
1
–
MOV.B
@(disp,GBR),R0
11000100dddddddd
(disp+GBR)→Sign
extension→R0
–
1
–
MOV.W
@(disp,GBR),R0
11000101dddddddd
(disp x 2+GBR)→Sign
extension→R0
–
1
–
MOV.L
@(disp,GBR),R0
11000110dddddddd
(disp x 4+GBR)→R0
–
1
–
MOVA
@(disp,PC),R0
11000111dddddddd
disp x 4+PC→R0
–
1
–
MOVT
Rn
0000nnnn00101001
T→Rn
–
1
–
SWAP.B
Rm,Rn
0110nnnnmmmm1000
Rm→Swap lowest two
bytes→Rn
–
1
–
SWAP.W Rm,Rn
0110nnnnmmmm1001
Rm→Swap two
consecutive words→Rn
–
1
–
XTRCT
0010nnnnmmmm1101
Rm: Middle 32 bits of Rn
→Rn
–
1
–
Instruction
Instruction Code Operation
MOV.B
@(R0,Rm),Rn
0000nnnnmmmm1100
MOV.W
@(R0,Rm),Rn
MOV.L
Rm,Rn
Rev. 3.00 Jan. 18, 2008 Page 68 of 1458
REJ09B0033-0300
Section 2
Table 2.7
CPU
Arithmetic Operation Instructions
Privileged
Mode
Cycles T Bit
Instruction
Instruction Code Operation
ADD
Rm,Rn
0011nnnnmmmm1100
Rn+Rm→Rn
–
1
–
ADD
#imm,Rn
0111nnnniiiiiiii
Rn+imm→Rn
–
1
–
ADDC
Rm,Rn
0011nnnnmmmm1110
Rn+Rm+T→Rn, Carry→T
–
1
Carry
ADDV
Rm,Rn
0011nnnnmmmm1111
Rn+Rm→Rn, Overflow→T
–
1
Overflow
CMP/EQ
#imm,R0
10001000iiiiiiii
If R0 = imm, 1 → T
–
1
Comparison
CMP/EQ
Rm,Rn
0011nnnnmmmm0000
If Rn = Rm, 1 → T
–
1
result
Comparison
result
CMP/HS
CMP/GE
CMP/HI
CMP/GT
CMP/PL
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rn
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010101
If Rn ≥ Rm with unsigned data, –
1→T
1
If Rn ≥ Rm with signed data,
1→T
1
–
Comparison
result
Comparison
result
If Rn > Rm with unsigned data, –
1→T
1
If Rn > Rm with signed data,
1→T
–
1
If Rn ≥ 0, 1 → T
–
Comparison
result
Comparison
result
1
Comparison
result
CMP/PZ
Rn
0100nnnn00010001
If Rn > 0, 1 → T
–
1
Comparison
result
CMP/STR Rm,Rn
0010nnnnmmmm1100
If Rn and Rm have an
equivalent byte, 1 → T
–
1
DIV1
Rm,Rn
0011nnnnmmmm0100
Single-step division (Rn/Rm)
–
1
Calculatio
n result
DIV0S
Rm,Rn
0010nnnnmmmm0111
MSB of Rn → Q,
MSB of Rm → M, M ^ Q → T
–
1
Calculatio
n result
DIV0U
0000000000011001
0 → M/Q/T
–
1
0
DMULS.L Rm,Rn
0011nnnnmmmm1101
Signed operation of Rn × Rm
→ MACH,
MACL 32 × 32 → 64 bits
–
2 (to
5)*
–
DMULU.L Rm,Rn
0011nnnnmmmm0101
Unsigned operation of Rn ×
Rm → MACH,
MACL 32 × 32 → 64 bits
–
2 (to
5)*
–
DT
0100nnnn00010000
Rn – 1 → Rn,
if Rn = 0, 1 → T, else 0 → T
–
1
Comparison
Rn
Comparison
result
result
Rev. 3.00 Jan. 18, 2008 Page 69 of 1458
REJ09B0033-0300
Section 2
CPU
Privileged
Mode
Cycles
Instruction
Instruction Code Operation
EXTS.B
Rm,Rn
0110nnnnmmmm1110
A byte in Rm is sign-extended –
→ Rn
1
–
EXTS.W
Rm,Rn
0110nnnnmmmm1111
A word in Rm is sign-extended –
→ Rn
1
–
EXTU.B
Rm,Rn
0110nnnnmmmm1100
A byte in Rm is zero-extended –
→ Rn
1
–
EXTU.W
Rm,Rn
0110nnnnmmmm1101
A word in Rm is zeroextended → Rn
–
1
–
MAC.L
@Rm+,
@Rn+
0000nnnnmmmm1111
Signed operation of (Rn) ×
(Rm) + MAC → MAC,
Rn + 4 → Rn, Rm + 4 → Rm
32 × 32 + 64 → 64 bits
–
2 (to 5)* –
MAC.W
@Rm+,
@Rn+
0100nnnnmmmm1111
Signed operation of (Rn) ×
(Rm) + MAC → MAC,
Rn + 2 → Rn, Rm + 2 → Rm
16 × 16 + 64 → 64 bits
–
2 (to 5)* –
MUL.L
Rm,Rn
0000nnnnmmmm0111
Rn × Rm → MACL
32 × 32 → 32 bits
–
2 (to 5) * –
MULS.W
Rm,Rn
0010nnnnmmmm1111
Signed operation of Rn × Rm
→ MACL
16 × 16 → 32 bits
–
1( to 3)* –
MULU.W
Rm,Rn
0010nnnnmmmm1110
Unsigned operation of
Rn × Rm → MACL
16 × 16 → 32 bits
–
1(to 3)*
–
NEG
Rm,Rn
0110nnnnmmmm1011
0–Rm→Rn
–
1
–
NEGC
Rm,Rn
0110nnnnmmmm1010
0–Rm–T→Rn, Borrow→T
–
1
Borrow
SUB
Rm,Rn
0011nnnnmmmm1000
Rn–Rm→Rn
–
1
–
SUBC
Rm,Rn
0011nnnnmmmm1010
Rn–Rm–T→Rn, Borrow →T
–
1
Borrow
Rm,Rn
0011nnnnmmmm1011
Rn–Rm→Rn, Underflow→T
–
1
Underflow
SUBV
Note:
*
T Bit
The number of execution cycles indicated within the parentheses ( ) are required when
the operation result is read from the MACH/MACL register immediately after the
instruction.
Rev. 3.00 Jan. 18, 2008 Page 70 of 1458
REJ09B0033-0300
Section 2
Table 2.8
CPU
Logic Operation Instructions
Instruction
Instruction Code
AND
Rm,Rn
0010nnnnmmmm1001 Rn & Rm → Rn
AND
#imm,R0
11001001iiiiiiii
AND.B
#imm,@(R0, 11001101iiiiiiii
GBR)
NOT
Rm,Rn
OR
OR
OR.B
Privileged
Mode
Cycles T Bit
Operation
–
1
–
R0 & imm → R0
–
1
–
(R0+GBR) & imm → (R0+GBR)
–
3
–
0110nnnnmmmm0111 ∼ Rm → Rn
–
1
–
Rm,Rn
0010nnnnmmmm1011 Rn | Rm → Rn
#imm,R0
11001011iiiiiiii
–
1
–
R0 | imm → R0
–
1
–
#imm,@(R0, 11001111iiiiiiii
GBR)
(R0+GBR) | imm → (R0+GBR)
–
3
–
TAS.B
@Rn
0100nnnn00011011
If (Rn) is 0, 1 → T; 1 → MSB of
(Rn)
–
4
Test
result
TST
Rm,Rn
0010nnnnmmmm1000 Rn & Rm; if the result is 0, 1 → T –
1
Test
result
TST
#imm,R0
11001000iiiiiiii
R0 & imm; if the result is 0, 1 →
T
–
1
Test
result
TST.B
#imm,@(R0, 11001100iiiiiiii
GBR)
(R0 + GBR) & imm; if the result
is 0, 1 → T
–
3
Test
result
XOR
Rm,Rn
0010nnnnmmmm1010 Rn ^ Rm → Rn
–
1
–
XOR
#imm,R0
11001010iiiiiiii
R0 ^ imm → R0
–
1
–
XOR.B
#imm,@(R0, 11001110iiiiiiii
GBR)
(R0+GBR) ^ imm → (R0+GBR)
–
3
–
Rev. 3.00 Jan. 18, 2008 Page 71 of 1458
REJ09B0033-0300
Section 2
CPU
Table 2.9
Shift Instructions
Instruction
Instruction Code
Operation
Privileged
Mode
Cycles
T Bit
ROTL
Rn
0100nnnn00000100
T←Rn←MSB
–
1
MSB
ROTR
Rn
0100nnnn00000101
LSB→Rn→T
–
1
LSB
ROTCL
Rn
0100nnnn00100100
T←Rn←T
–
1
MSB
ROTCR
Rn
0100nnnn00100101
T→Rn→T
–
1
LSB
SHAD
Rm, Rn 0100nnnnmmmm1100 Rn ≥ 0: Rn << Rm → Rn
–
Rn < 0: Rn >> Rm → [MSB → Rn]
1
–
SHAL
Rn
0100nnnn00100000
T←Rn←0
–
1
MSB
SHAR
Rn
0100nnnn00100001
MSB→Rn→T
–
1
LSB
SHLD
Rm, Rn 0100nnnnmmmm1101 Rm ≥ 0: Rn << Rm → Rn
Rm < 0: Rn >> Rm → [0 → Rn]
–
1
–
SHLL
Rn
0100nnnn00000000
T←Rn←0
–
1
MSB
SHLR
Rn
0100nnnn00000001
0→Rn→T
–
1
LSB
SHLL2
Rn
0100nnnn00001000
Rn<<2 → Rn
–
1
–
SHLR2
Rn
0100nnnn00001001
Rn>>2 → Rn
–
1
–
SHLL8
Rn
0100nnnn00011000
Rn<<8 → Rn
–
1
–
SHLR8
Rn
0100nnnn00011001
Rn>>8 → Rn
–
1
–
SHLL16
Rn
0100nnnn00101000
Rn<<16 → Rn
–
1
–
SHLR16
Rn
0100nnnn00101001
Rn>>16 → Rn
–
1
–
Rev. 3.00 Jan. 18, 2008 Page 72 of 1458
REJ09B0033-0300
Section 2
CPU
Table 2.10 Branch Instructions
Privilege Cycle
d Mode s
T Bit
Instruction
Instruction Code
Operation
BF
disp
10001011dddddddd
If T = 0, disp × 2 + PC → PC;
if T = 1, nop
–
3/1*
–
BF/S
disp
10001111dddddddd
Delayed branch,
if T = 0, disp × 2 + PC → PC;
if T = 1, nop
–
2/1*
–
BT
disp
10001001dddddddd
If T = 1, disp × 2 + PC → PC;
if T = 0, nop
–
3/1*
–
BT/S
disp
10001101dddddddd
Delayed branch,
if T = 1, disp × 2 + PC → PC;
if T = 0, nop
–
2/1*
–
BRA
disp
1010dddddddddddd
Delayed branch, disp × 2 + PC
→ PC
–
2
–
BRAF
Rm
0000mmmm00100011
Delayed branch,Rm + PC → PC –
2
–
BSR
disp
1011dddddddddddd
Delayed branch, PC → PR, disp –
× 2 + PC → PC
2
–
BSRF
Rm
0000mmmm00000011
Delayed branch, PC → PR, Rm
+ PC → PC
–
2
–
JMP
@Rm
0100mmmm00101011
Delayed branch, Rm → PC
–
2
–
JSR
@Rm
0100mmmm00001011
Delayed branch, PC → PR, Rm
→ PC
–
2
–
0000000000001011
Delayed branch, PR → PC
–
2
–
RTS
Note:
*
One state when the branch is not executed.
Rev. 3.00 Jan. 18, 2008 Page 73 of 1458
REJ09B0033-0300
Section 2
CPU
Table 2.11 System Control Instructions
Privileged
Mode
Cycles T Bit
Instruction
Instruction Code Operation
CLRMAC
0000000000101000
0→MACH,MACL
–
1
–
CLRS
0000000001001000
0→S
–
1
–
CLRT
0000000000001000
0→T
–
1
0
LDC
Rm,SR
0100mmmm00001110
Rm→SR
√
6
LSB
LDC
Rm,GBR
0100mmmm00011110
Rm→GBR
–
4
–
LDC
Rm,VBR
0100mmmm00101110
Rm→VBR
√
4
–
LDC
Rm,SSR
0100mmmm00111110
Rm→SSR
√
4
–
LDC
Rm,SPC
0100mmmm01001110
Rm→SPC
√
4
–
LDC
Rm,R0_BANK 0100mmmm10001110 Rm→R0_BANK
√
4
–
LDC
Rm,R1_BANK 0100mmmm10011110 Rm→R1_BANK
√
4
–
LDC
Rm,R2_BANK 0100mmmm10101110 Rm→R2_BANK
√
4
–
LDC
Rm,R3_BANK 0100mmmm10111110 Rm→R3_BANK
√
4
–
LDC
Rm,R4_BANK 0100mmmm11001110 Rm→R4_BANK
√
4
–
LDC
Rm,R5_BANK 0100mmmm11011110 Rm→R5_BANK
√
4
–
LDC
Rm,R6_BANK 0100mmmm11101110 Rm→R6_BANK
√
4
–
LDC
Rm,R7_BANK 0100mmmm11111110 Rm→R7_BANK
√
4
–
LDC.L
@Rm+,SR
0100mmmm00000111
(Rm)→SR, Rm+4→Rm
√
8
LSB
LDC.L
@Rm+,GBR
0100mmmm00010111
(Rm)→GBR, Rm+4→Rm
–
4
–
LDC.L
@Rm+,VBR
0100mmmm00100111
(Rm)→VBR, Rm+4→Rm
√
4
–
LDC.L
@Rm+,SSR
0100mmmm00110111
(Rm)→SSR,Rm+4→Rm
√
4
–
LDC.L
@Rm+,SPC
0100mmmm01000111
(Rm)→SPC,Rm+4→Rm
√
4
–
LDC.L
@Rm+,
R0_BANK
0100mmmm10000111
(Rm)→R0_BANK,Rm+4→Rm
√
4
–
LDC.L
@Rm+,
R1_BANK
0100mmmm10010111
(Rm)→R1_BANK,Rm+4→Rm
√
4
–
LDC.L
@Rm+,
R2_BANK
0100mmmm10100111
(Rm)→R2_BANK,Rm+4→Rm
√
4
–
LDC.L
@Rm+,
R3_BANK
0100mmmm10110111
(Rm)→R3_BANK, Rm+4→Rm
√
4
–
LDC.L
@Rm+,
R4_BANK
0100mmmm11000111
(Rm)→R4_BANK, Rm+4→Rm
√
4
–
Rev. 3.00 Jan. 18, 2008 Page 74 of 1458
REJ09B0033-0300
Section 2
Privileged
Mode
Cycles T Bit
Instruction
Instruction Code Operation
LDC.L
@Rm+,
R5_BANK
0100mmmm11010111
(Rm)→R5_BANK, Rm+4→Rm
√
4
–
LDC.L
@Rm+,
R6_BANK
0100mmmm11100111
(Rm)→R6_BANK, Rm+4→Rm
√
4
–
LDC.L
@Rm+,
R7_BANK
0100mmmm11110111
(Rm)→R7_BANK, Rm+4→Rm
√
4
–
LDS
Rm,MACH
0100mmmm00001010
Rm→MACH
–
1
–
LDS
Rm,MACL
0100mmmm00011010
Rm→MACL
–
1
–
LDS
Rm,PR
0100mmmm00101010
Rm→PR
–
1
–
LDS.L
@Rm+,MACH 0100mmmm00000110
(Rm)→MACH, Rm+4→Rm
–
1
–
LDS.L
@Rm+,MACL 0100mmmm00010110
(Rm)→MACL, Rm+4→Rm
–
1
–
LDS.L
@Rm+,PR
0100mmmm00100110
(Rm)→PR, Rm+4→Rm
–
1
–
LDTLB
0000000000111000
PTEH/PTEL→TLB
√
1
–
NOP
0000000000001001
No operation
–
1
–
0000mmmm10000011
(Rm) → cache
–
1
–
RTE
0000000000101011
Delayed branch, SSR → SR,
SPC → PC
√
5
–
SETS
0000000001011000
1→S
–
1
–
SETT
0000000000011000
1→T
–
1
0000000000011011
Sleep
√
4*
–
PREF
@Rm
SLEEP
CPU
1
1
STC
SR,Rn
0000nnnn00000010
SR→Rn
√
1
–
STC
GBR,Rn
0000nnnn00010010
GBR→Rn
–
1
–
STC
VBR,Rn
0000nnnn00100010
VBR→Rn
√
1
–
STC
SSR, Rn
0000nnnn00110010
SSR→Rn
√
1
–
STC
SPC,Rn
0000nnnn01000010
SPC→Rn
√
1
–
STC
R0_BANK,Rn
0000nnnn10000010
R0_BANK→Rn
√
1
–
STC
R1_BANK,Rn
0000nnnn10010010
R1_BANK→Rn
√
1
–
STC
R2_BANK,Rn
0000nnnn10100010
R2_BANK→Rn
√
1
–
STC
R3_BANK,Rn
0000nnnn10110010
R3_BANK→Rn
√
1
–
STC
R4_BANK,Rn
0000nnnn11000010
R4_BANK→Rn
√
1
–
STC
R5_BANK,Rn
0000nnnn11010010
R5_BANK→Rn
√
1
–
STC
R6_BANK,Rn
0000nnnn11100010
R6_BANK→Rn
√
1
–
Rev. 3.00 Jan. 18, 2008 Page 75 of 1458
REJ09B0033-0300
Section 2
CPU
Instruction
Instruction
Code
Operation
Privileged
Mode
Cycles T Bit
STC
R7_BANK,Rn
0000nnnn11110010
R7_BANK→Rn
√
1
–
STC.L
SR,@–Rn
0100nnnn00000011
Rn–4→Rn, SR→(Rn)
√
1
–
STC.L
GBR,@–Rn
0100nnnn00010011
Rn–4→Rn, GBR→(Rn)
–
1
–
STC.L
VBR,@–Rn
0100nnnn00100011
Rn–4→Rn, VBR→(Rn)
√
1
–
STC.L
SSR,@–Rn
0100nnnn00110011
Rn–4→Rn, SSR→(Rn)
√
1
–
STC.L
SPC,@–Rn
0100nnnn01000011
Rn–4→Rn, SPC→(Rn)
√
1
–
STC.L
R0_BANK,@–Rn 0100nnnn10000011
Rn–4→Rn, R0_BANK→(Rn)
√
1
–
STC.L
R1_BANK,@–Rn 0100nnnn10010011
Rn–4→Rn, R1_BANK→(Rn)
√
1
–
STC.L
R2_BANK,@–Rn 0100nnnn10100011
Rn–4→Rn, R2_BANK→(Rn)
√
1
–
STC.L
R3_BANK,@–Rn 0100nnnn10110011
Rn–4→Rn, R3_BANK→(Rn)
√
1
–
STC.L
R4_BANK,@–Rn 0100nnnn11000011
Rn–4→Rn, R4_BANK→(Rn)
√
1
–
STC.L
R5_BANK,@–Rn 0100nnnn11010011
Rn–4→Rn, R5_BANK→(Rn)
√
1
–
STC.L
R6_BANK,@–Rn 0100nnnn11100011
Rn–4→Rn, R6_BANK→(Rn)
√
1
–
STC.L
R7_BANK,@–Rn 0100nnnn11110011
Rn–4→Rn, R7_BANK→(Rn)
√
1
–
STS
MACH,Rn
0000nnnn00001010
MACH→Rn
–
1
–
STS
MACL,Rn
0000nnnn00011010
MACL→Rn
–
1
–
STS
PR,Rn
0000nnnn00101010
PR→Rn
–
1
–
STS.L
MACH,@–Rn
0100nnnn00000010
Rn–4→Rn, MACH→(Rn)
–
1
–
STS.L
MACL,@–Rn
0100nnnn00010010
Rn–4→Rn, MACL→(Rn)
–
1
–
STS.L
PR,@–Rn
0100nnnn00100010
Rn–4→Rn, PR→(Rn)
–
1
–
11000011iiiiiiii
Unconditional trap exception
2
occurs*
–
8
–
TRAPA #imm
Notes:
The table shows the minimum number of clocks required for execution. In practice, the
number of execution cycles will be increased in the following conditions.
a. If there is a conflict between an instruction fetch and a data access
b. If the destination register of a load instruction (memory → register) is also used by
the following instruction.
For addressing modes with displacement (disp) as shown below, the assembler
description in this manual indicates the value before it is scaled (x 1, x 2, or x 4)
according to the operand size to clarify the LSI operation. For details on assembler
description, refer to the description rules in each assembler.
@ (disp:4, Rn) ; Register indirect with displacement
@ (disp:8, GBR) ; GBR indirect with displacement
@ (disp:8, PC) ; PC relative with displacement
disp:8, disp:12 ; PC relative
Rev. 3.00 Jan. 18, 2008 Page 76 of 1458
REJ09B0033-0300
Section 2
CPU
1. Number of states before the chip enters the sleep state.
2. For details, refer to section 7, Exception Handling.
2.6.2
Operation Code Map
Table 2.12 shows the operation code map.
Table 2.12 Operation Code Map
Instruction Code
MSB
LSB
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MD: 00
MD: 01
MD: 10
MD: 11
0000
Rn
Fx
0000
0000
Rn
Fx
0001
0000
Rn
00MD
0010
STC
SR, Rn
0000
Rn
01MD
0010
STC
SPC, Rn
0000
Rn
10MD
0010
STC
0000
Rn
11MD
0010
0000
Rm
00MD
0000
Rm
10MD
0000
Rn
0000
STC
GBR, Rn
STC
VBR, Rn
STC
SSR, Rn
R0_BANK, Rn
STC
R1_BANK, Rn
STC
R2_BANK, Rn
STC
R3_BANK, Rn
STC
R4_BANK, Rn
STC
R5_BANK, Rn
STC
R6_BANK, Rn
STC
R7_BANK, Rn
0011
BSRF
Rm
BRA
Rm
0011
PREF
@Rm
Rm
01MD
MOV.B
Rm, @(R0, Rn)
MOV.L
Rm,@(R0, Rn)
MUL.L
Rm, Rn
0000
00MD
1000
CLRT
SETT
0000
0000
01MD
1000
CLRS
SETS
0000
0000
Fx
1001
NOP
DIV0U
0000
0000
Fx
1010
0000
0000
Fx
1011
RTS
SLEEP
0000
Rn
Fx
1000
0000
Rn
Fx
1001
0000
Rn
Fx
1010
0000
Rn
Fx
1011
0000
Rn
Rm
0001
Rn
0010
MOV.W
Rm, @(R0, Rn)
CLRMAC
LDTLB
RTE
MOVT
Rn
STS
MACH, Rn
STS
MACL, Rn
STS
PR, Rn
11MD
MOV. B
@(R0, Rm), Rn
MOV.W
@(R0, Rm), Rn
MOV.L
@(R0, Rm), Rn
Rm
disp
MOV.L
Rm, @(disp:4, Rn)
Rn
Rm
00MD
MOV.B
Rm, @Rn
MOV.W
Rm, @Rn
MOV.L
Rm, @Rn
0010
Rn
Rm
01MD
MOV.B
Rm, @–Rn
MOV.W
Rm, @–Rn
MOV.L
0010
Rn
Rm
10MD
TST
Rm, Rn
AND
Rm, Rn
XOR
MAC.L
@Rm+,@Rn+
Rm, @–Rn
DIV0S
Rm, Rn
Rm, Rn
OR
Rm, Rn
Rev. 3.00 Jan. 18, 2008 Page 77 of 1458
REJ09B0033-0300
Section 2
CPU
Instruction Code
MSB
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
LSB
MD: 00
MD: 01
MD: 10
MD: 11
XTRCT
MULU.W Rm, Rn
MULSW
Rm, Rn
CMP/HS
Rm, Rn
CMP/GE
Rm, Rn
CMP/HI
Rm, Rn
CMP/GT
Rm, Rn
SUBC
Rm, Rn
SUBV
Rm, Rn
ADDV
Rm, Rn
STC.L
SSR, @–Rn
0010
Rn
Rm
11MD
CMP/STR Rm, Rn
Rm, Rn
0011
Rn
Rm
00MD
CMP/EQ Rm, Rn
0011
Rn
Rm
01MD
DIV1
Rm, Rn
0011
Rn
Rm
10MD
SUB
Rm, Rn
0011
Rn
Rm
11MD
ADD
Rm, Rn
DMULS.L Rm,Rn
ADDC
Rm, Rn
0100
Rn
Fx
0000
SHLL
Rn
DT
Rn
SHAL
Rn
DMULU.L Rm,Rn
0100
Rn
Fx
0001
SHLR
Rn
CMP/PZ
Rn
SHAR
Rn
0100
Rn
Fx
0010
STS.L
MACH, @–Rn
STS.L
MACL, @–Rn
STS.L
PR, @–Rn
0100
Rn
00MD
0011
STC.L
SR, @–Rn
STC.L
GBR, @–Rn
STC.L
VBR, @–Rn
0100
Rn
01MD
0011
STC.L
SPC, @–Rn
0100
Rn
10MD
0011
STC.L
STC.L
STC.L
STC.L
R0_BANK, @–Rn
R1_BANK, @–Rn
R2_BANK, @–Rn
R3_BANK, @–Rn
STC.L
STC.L
STC.L
STC.L
R4_BANK, @–Rn
R5_BANK, @–Rn
R6_BANK, @–Rn
R7_BANK, @–Rn
0100
Rn
11MD
0011
0100
Rn
Fx
0100
ROTL
Rn
0100
Rn
Fx
0101
ROTR
Rn
0100
Rm
Fx
0110
LDS.L
ROTCL
Rn
CMP/PL
Rn
ROTCR
Rn
LDS.L
@Rm+, MACL
LDS.L
@Rm+, PR
LDC.L
@Rm+, GBR
LDC.L
@Rm+, VBR
@Rm+, MACH
0100
Rm
00MD
0111
LDC.L
@Rm+, SR
0100
Rm
01MD
0111
LDC.L
@Rm+, SPC
0100
Rm
10MD
0111
LDC.L
LDC.L
LDC.L
LDC.L
@Rm+, R0_BANK
@Rm+, R1_BANK
@Rm+, R2_BANK
@Rm+, R3_BANK
LDC.L
LDC.L
LDC.L
LDC.L
@Rm+, R4_BANK
@Rm+, R5_BANK
@Rm+, R6_BANK
@Rm+, R7_BANK
SHLL2
SHLL8
SHLL16
0100
0100
Rm
Rn
11MD
Fx
0111
1000
Rn
Rn
Rn
0100
Rn
Fx
1001
SHLR2
Rn
SHLR8
Rn
SHLR16
Rn
0100
Rm
Fx
1010
LDS
Rm, MACH
LDS
Rm, MACL
LDS
Rm, PR
0100
Rm/
Fx
1011
JSR
@Rm
TAS.B
@Rn
JMP
@Rm
Rn
0100
Rn
Rm
1100
SHAD
Rm, Rn
0100
Rn
Rm
1101
SHLD
Rm, Rn
Rev. 3.00 Jan. 18, 2008 Page 78 of 1458
REJ09B0033-0300
LDC.L
@Rm+, SSR
Section 2
Instruction Code
MSB
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
LSB
MD: 00
MD: 01
MD: 10
MD: 11
0100
Rm
00MD
1110
LDC
Rm, SR
0100
Rm
01MD
1110
LDC
Rm, SPC
0100
Rm
10MD
1110
LDC
0100
Rm
11MD
1110
LDC
0100
Rn
Rm
1111
MAC.W
@Rm+, @Rn+
0101
Rn
Rm
disp
MOV.L
@(disp:4, Rm), Rn
LDC
LDC
Rm, GBR
LDC
Rm, VBR
Rm, SSR
Rm, R0_BANK
LDC
Rm, R1_BANK
LDC
Rm, R2_BANK LDC
Rm, R3_BANK
Rm, R4_BANK
LDC
Rm, R5_BANK
LDC
Rm, R6_BANK LDC
Rm, R7_BANK
0110
Rn
Rm
00MD
MOV.B
@Rm, Rn
MOV.W
@Rm, Rn
MOV.L
@Rm, Rn
MOV
Rm, Rn
0110
Rn
Rm
01MD
MOV.B
@Rm+, Rn
MOV.W
@Rm+, Rn
MOV.L
@Rm+, Rn
NOT
Rm, Rn
0110
Rn
Rm
10MD
SWAP.B
Rm, Rn
SWAP.W
Rm, Rn
NEGC
Rm, Rn
NEG
Rm, Rn
0110
Rn
Rm
11MD
EXTU.B
Rm, Rn
EXTU.W
Rm, Rn
EXTS.B
Rm, Rn
EXTS.W
Rm, Rn
0111
Rn
imm
ADD
# imm : 8, Rn
1000
00MD
Rn
1000
01MD
Rm
disp
disp
1000
10MD
imm/disp
1000
11MD
imm/disp
1001
Rn
disp
1010
MOV. B
MOV. W
R0, @(disp: 4, Rn)
R0, @(disp: 4, Rn)
MOV.B
MOV.W
@(disp:4, Rm), R0
@(disp: 4, Rm), R0
CMP/EQ
BT
disp: 8
BF
disp: 8
BT/S
disp: 8
BF/S
disp: 8
TRAPA
#imm: 8
#imm:8, R0
MOV.W
@(disp : 8, PC), Rn
disp
BRA
disp: 12
1011
disp
BSR
disp: 12
1100
00MD
1100
01MD
imm/disp
disp
CPU
MOV.B
MOV.W
MOV.L
R0, @(disp: 8, GBR)
R0, @(disp: 8, GBR)
R0, @(disp: 8, GBR)
MOV.B
MOV.W
MOV.L
MOVA
@(disp: 8, GBR), R0
@(disp: 8, GBR), R0
@(disp: 8, GBR), R0
@(disp: 8, PC), R0
AND
XOR
OR
1100
10MD
imm
TST
#imm: 8, R0
1100
11MD
imm
TST.B
AND.B
XOR.B
OR.B
#imm: 8, @(R0, GBR)
#imm: 8, @(R0, GBR)
#imm: 8, @(R0, GBR)
#imm: 8, @(R0, GBR)
1101
Rn
disp
MOV.L
@(disp: 8, PC), Rn
1110
Rn
imm
MOV
#imm:8, Rn
1111
************
#imm: 8, R0
#imm: 8, R0
#imm: 8, R0
Note: For details, refer to the SH-3/SH-3H/SH3-DSP Software Manual.
Rev. 3.00 Jan. 18, 2008 Page 79 of 1458
REJ09B0033-0300
Section 2
CPU
Rev. 3.00 Jan. 18, 2008 Page 80 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Section 3 DSP Operating Unit
3.1
DSP Extended Functions
This LSI incorporates a DSP unit and X/Y memory directly connected to the DSP unit. This LSI
supports the DSP extended function instruction sets needed to control the DSP unit and X/Y
memory. The DSP extended function instructions are classified into four groups.
(1)
Extended System Control Instructions for the CPU
If the DSP extended function is enabled, the following extended system control instructions can be
used for the CPU.
• Repeat loop control instructions and repeat loop control register access instructions are added.
Looped programs can be executed efficiently by using the zero-overhead repeat control unit.
For details, refer to section 3.3, CPU Extended Instructions.
• Modulo addressing control instructions and control register access instructions are added.
Function allows access to data with a circular structure. For details, refer to section 3.4, DSP
Data Transfer Instructions.
• DSP unit register access instructions are added. Some of the DSP unit registers can be used in
the same way as the CPU system registers. For details, refer to section 3.4, DSP Data Transfer
Instructions.
(2)
Data Transfer Instructions for Data Transfers between DSP Unit and On-Chip X/Y
Memory
Data transfer instructions for data transfers between the DSP unit and on-chip X/Y memory are
called double-data transfer instructions. Instruction codes for these double-transfer instructions are
16 bit codes as well as CPU instruction codes. These data transfer instructions perform data
transfers between the DSP unit and on-chip X/Y memory that is directly connected to the DSP
unit. These data transfer instructions can be described in combination with other DSP unit
operation instructions. For details, refer to section 3.4, DSP Data Transfer Instructions.
(3)
Data Transfer Instructions for Data Transfers between DSP Unit Registers and All
Virtual Address Spaces
Data transfer instructions for data transfers between DSP unit registers and all virtual address
spaces are called single-data transfer instructions. Instruction codes for the double-transfer
instructions are 16 bit codes as well as CPU instruction codes. These data transfer instructions
DSPS301S_010020030200
Rev. 3.00 Jan. 18, 2008 Page 81 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
performs data transfers between the DSP unit registers and all virtual address spaces. For details,
refer to section 3.4, DSP Data Transfer Instructions.
(4)
DSP Unit Operation Instructions
DSP unit operation instructions are called DSP data operation instructions. These instructions are
provided to execute digital signal processing operations at high speed using the DSP. Instruction
codes for these instructions are 32 bits. The DSP data operation instruction fields consist of two
fields: field A and field B. In field A, a function for double data transfer instructions can be
described. In field B, ALU operation instructions and multiply instructions can be described. The
instructions described in fields A and B can be executed in parallel. A maximum of four
instructions (ALU operation, multiply, and two data transfers) can be executed in parallel. For
details, refer to section 3.5, DSP Data Operation Instructions.
Notes: 1. 32-bit instruction codes are handled as two consecutive 16-bit instruction codes.
Accordingly, 32-bit instruction codes can be assigned to a word boundary. 32-bit
instruction codes must be stored in memory, upper word and lower word, in this order,
in word units.
2. In little endian, the upper and lower words must be stored in memory as data to be
accessed in word units.
15
0
12 11
0000
*
-
CPU core instruction
1110
15
10 9
111100
Double-data transfer instruction
15
10 9
31
DSP data operation instruction
A Field
111101
Single-data transfer instruction
0
0
A Field
26 25
111110
16 15
A Field
Figure 3.1 DSP Instruction Format
Rev. 3.00 Jan. 18, 2008 Page 82 of 1458
REJ09B0033-0300
0
B Field
Section 3 DSP Operating Unit
3.2
DSP Mode Resources
3.2.1
Processing Modes
The CPU processing modes can be extended using the mode bit (MD) and DSP bit (DSP) in the
status register (SR), as shown below.
Table 3.1
CPU Processing Modes
Description
MD
DSP
Processing Mode
Access of Resources
Protected in Privileged Mode
or Privileged Instruction
Execution
0
0
User mode
Prohibited
Invalid
0
1
User DSP mode
Prohibited
Valid
1
0
Privileged mode
Allowed
Invalid
1
1
Privileged DSP mode Allowed
DSP Extended
Functions
Valid
As shown above, the extension of the DSP function by the DSP bit can be specified independently
of the control by the MD bit. Note, however, that the DSP bit can be modified only in privileged
mode. Before the DSP bit is modified, a transition to privileged mode or privileged DSP mode is
necessary.
3.2.2
DSP Mode Memory Map
In DSP mode, a part of the P2 area in the virtual address space can be accessed in user DSP mode.
When this area is accessed in user DSP mode, this area is referred to as a Uxy area. X/Y memory
is then assigned to this Uxy area. Accordingly, X/Y memory can also be accessed in user DSP
mode.
Rev. 3.00 Jan. 18, 2008 Page 83 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Table 3.2
Virtual Address Space
Address Range
Name
Protection
Description
H'A5000000 to H'A5FFFFFF
P2/Uxy
Privileged or
DSP
16-Mbyte physical address space,
non-cacheable, non-address
translatable
Can be accessed in privileged mode,
privileged DSP mode, and user DSP
mode
3.2.3
CPU Register Sets
In DSP mode, the status register (SR) in the CPU unit is extended to add control bits and three
control registers: a repeat start register (SR), repeat end register (RE), and modulo register (MOD)
are added as control registers.
31
0
30
29
28 27
MD RB BL
RC[11:0]
16 15
14
0
0
13
9
8
7
6
5
4
0 DSP DMY DMX M
Q
I3
I2
I1
I0
31
12
11
10
0
RS
Repeat start register (RS)
31
0
RE
31
Repeat end register (RE)
16 15
ME
0
MS
MODulo register (MOD)
Figure 3.2 CPU Registers in DSP Mode
Rev. 3.00 Jan. 18, 2008 Page 84 of 1458
REJ09B0033-0300
1
0
RF1 RF0 S
3
2
T
Status Register
(SR)
Section 3 DSP Operating Unit
(1)
Extension of Status Register (SR)
In DSP mode, the following control bits are added to the status register (SR). These added bits are
called DSP extension bits. These DSP extension bits are valid only in DSP mode.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 28



For details, refer to section 2, CPU.
27 to 16
RC11 to
RC0
All 0
R/W
Repeat Counter
15 to 13



For details, refer to section 2, CPU.
12
DSP
0
R/W
DSP Bit
Holds the number of repeat times in order to perform
loop control, and can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the
exception handling state.
Enables or disables the DSP extended functions. If
this bit is set to 1, the DSP extended functions are
enabled. This bit can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset, this
bit is initialized to 0. This bit is not affected in the
exception handling state.
11
MDY
0
R/W
Modulo Control Bits
10
MDX
0
R/W
Enable or disable modulo addressing for X/Y memory
access. These bits can be modified in privileged mode,
privileged DSP mode, or user DSP mode. At reset,
these bits are initialized to 0. These bits are affected in
the exception handling state.
9 to 4



For details, refer to section 2, CPU.
3
FR1
0
R/W
Repeat Flag Bits
2
FR0
0
R/W
Used by repeat control instructions. These bits can be
modified in privileged mode, privileged DSP mode, or
user DSP mode. At reset, these bits are initialized to 0.
These bits are affected in the exception handling state.
1, 0



For details, refer to section 2, CPU.
Note: When data is written to the SR register, 0 should be written to bits that are specified as 0.
Rev. 3.00 Jan. 18, 2008 Page 85 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
(2)
Repeat Start Register (RS)
The repeat start register (RS) holds the start address of a loop repeat module that is controlled by
the repeat function. This register can be accessed in DSP mode. At reset, the initial value of this
register is undefined. This register is not affected in the exception handling state.
(3)
Repeat End Register (RE)
The repeat end register (RE) holds the end address of a loop repeat module that is controlled by
the repeat function. This register can be accessed in DSP mode. At reset, this register is initialized
to 0. This register is not affected in the exception handling state.
(4)
Modulo Register (MOD)
The modulo register stores the modulo end address and modulo start address for modulo
addressing in upper and lower 16 bits. The upper and lower 16 bits of the modulo register are
referred to as the ME register and MS register, respectively. This register can be accessed in DSP
mode. At reset, the initial value of this register is undefined. This register is not affected in the
exception handling state.
The above registers can be accessed by the control register load instruction (LDC) and store
instruction (STC). Note that the LDC and STC instructions for the RS, RE, and MOD registers can
be used only in privileged DSP mode and user DSP mode. The LDC and STC instruction for the
SR register can be executed only when the MD bit is set to 1 or in user DSP mode. Note, however,
that the LDC and STC instructions can modify only the RC11 to RC0, RF1 to RF0, DMX, and
DMY bits in the SR, as described below.
• In user mode, if the LCD and STC instructions are used for the RS, an illegal instruction
exception occurs.
• In privileged and privileged DSP modes, all SR bits can be modified.
• In user DSP mode, the SR can be read by the STC instruction.
• In user DSP mode, the LDC instruction can be issued to the SR but only the DSP extension
bits can be modified.
Rev. 3.00 Jan. 18, 2008 Page 86 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Table 3.3
Operation of SR Bits in Each Processing Mode
Privileged
Mode
Field
MD = 1 &
DSP = 0
MD
Access to
DSP-Related
Bit with
Dedicated
Instruction
User Mode
Privileged
DSP Mode
User DSP
Mode
MD = 0 &
DSP = 0
MD = 1 &
DSP = 1
MD = 0 &
DSP = 1
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
RB
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
BL
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1
RC [11:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
DSP
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
0
DMY
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
0
DMX
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
0
Q
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
M
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
I[3:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
1111
RF[1:0]
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
R: OK, L: OK
S
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
T
S: OK, L: OK
S, L: Invalid
instruction
S: OK, L: OK
S: OK, L: NG
x
SETRC
instruction
SETRC
instruction
Initial Value
after Reset
000000000000
x
[Legend]
S:
STC instruction
L:
LDC instruction
OK:
STC/LDC operation is enabled.
Invalid instruction:
Exception occurs when an invalid instruction is executed.
NG:
Previous value is retained. No change.
x:
Undefined
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Before entering the exception handling state, all bits including the DSP extension bits of the SR
registers are saved in the SSR. Before returning from the exception handling, all bits including the
DSP extension bits of the SR must be restored. If the repeat control must be recovered before
entering the exception handling state, the RS and RE registers must be recovered to the value that
existed before exception handling. In addition, if it is necessary to recover modulo control before
entering the exception handling state, the MOD register must be recovered to the value that
existed before exception handling.
3.2.4
DSP Registers
The DSP unit incorporates eight data registers (A0, A1, X0, X1, Y0, Y1, M0, and M1) and a status
register (DSR). Figure 3.3 shows the DSP register configuration. These are 32-bit width registers
with the exception of registers A0 and A1. Registers A0 and A1 include 8 guard bits (fields A0G
and A1G), giving them a total width of 40 bits. The DSR register stores the DSP data operation
result (zero, negative, others). The DSP register has a DC bit whose function is similar to the T bit
in the CPU register. For details on DSR bits, refer to section 3.5, DSP Data Operation Instructions.
39
32 31
A0G
A0
0
A1G
A1
M0
M1
Initial value
DSR : All 0
Others: Undefined
X0
X1
Y0
Y1
(a) DSP data registers
31
8
................
7
6
5
4
GT
Z
N
V
3
(b) DSP status register (DSR)
Figure 3.3 DSP Register Configuration
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1
CS[2:0]
0
DC
Section 3 DSP Operating Unit
3.3
CPU Extended Instructions
3.3.1
DSP Repeat Control
In DSP mode, a specific function is provided to execute repeat loops efficiently. By using this
function, loop programs can be executed without overhead caused by the compare and branch
instructions.
(1)
Examples of Repeat Loop Programs
Examples of repeat loop programs are shown below.
• Example 1: Repeat loop consisting of 4 or more instructions
LDRS RptStart
; Sets repeat start instruction address
to the RS register
LDRE RptDtct +4
; Sets (repeat detection instruction
address + 4) to the RE register
SETRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
Instr0
; At least one instruction is required
from SETRC instruction to [Repeat start
instruction]
RptStart: instr1
... ...
... ...
; [Repeat start instruction]
;
;
RptDtct:
instr(N-3)
;Three instruction prior to the repeat
end instruction is regarded as repeat
detection instruction
RptEnd2:
instr(N-2)
;
RptEnd1:
instr(N-1)
;
RptEnd:
instrN
; [Repeat end instruction]
In the above program example, instructions from the RptStart address (instr1 instruction) to the
RptEnd address (instrN instruction) are repeated four times. These repeated instructions in the
program are called repeat loop. The start and end instructions of the repeat loop are called the
repeat start instruction and repeat end instruction, respectively. The CPU sequentially executes
instructions and starts repeat loop control if the CPU detects the completion of a specific
instruction. This specific instruction is called the repeat detection instruction. In a repeat loop
consisting of four or more instructions, an instruction three instructions prior to the repeat end
instruction is regarded as the repeat detection instruction. In a repeat loop consisting of four or
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Section 3 DSP Operating Unit
more instructions, the same instruction is regarded as the RptStart instruction and RptDtct
instruction.
To control the repeat loop, the DSP extended control registers, such as the RE register and RS
register and the RC[11:0] and RF[1:0] bits of the SR register, are used. These registers can be
specified by the LDRE, LDRS, and SETRC instructions.
• Repeat end register (RE)
The RE register is specified by the LDRE instruction. The RE register specifies (repeat
detection instruction address +4). In a repeat loop consisting of four or more instructions, an
instruction three instructions prior to the repeat end instruction is regarded as the repeat
detection instruction. A repeat loop consisting of three or less instructions is described later.
• Repeat start register (RS)
The RE register is specified by the LDRS instruction. In a repeat loop consisting of 4 or more
instructions, the RS register specifies the repeat start instruction address. In a repeat loop
consisting of three or less instructions, a specific address is specified in the RS. This is
described later.
• Repeat counter (RC[11:0] bits of the SR)
The repeat counter is specifies the number of repetitions by the SETRC instruction. During
repeat loop execution, the RC holds the remaining number of repetitions.
• Repeat flags (RF[1:0] bits of the SR)
The repeat flags are automatically specified according to the RS and RE register values during
SETRC instruction execution. The repeat flags store information on the number of instructions
included in the repeat loop. Normally, the user cannot modify the repeat flag values.
The CPU always executes instructions by comparing the RE register to program counter values.
Because the PC stores (the current instruction address +4), if the RE matches the PC during repeat
instruction detection execution, a repeat detection instruction can be detected. If a repeat detection
instruction is executed without branching and if RC[11:0] > 0, then repeat control is performed. If
RC[11:0] ≥ 2 when the repeat end instruction is completed, the RC[11:0] is decremented by 1 and
then control is passed to the address specified by the RS register.
Examples 2 to 4 show program examples of the repeat loop consisting of three instructions, two
instructions, and one instruction, respectively. In these examples, an instruction immediately prior
to the repeat start instruction is regarded as a repeat detection instruction. The RS register specifies
the specific value that indicates the number of repeat instructions.
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Section 3 DSP Operating Unit
• Example 2: Repeat loop consisting of three instructions
LDRS RptDtct +4
; Sets (repeat detection instruction
address + 4) to the RS register
LDRE RptDtct +4
; Sets (repeat detection instruction
address + 4) to the RE register
SETRC #4
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; If RE-RS==0 during SETRC instruction
execution, the repeat loop is regarded
as three-instruction repeat.
RptDtct:
instr0
; An instruction prior to the Repeat
start instruction is regarded as a
repeat detection instruction.
RptStart: instr1
RptEnd:
; [Repeat start instruction]
Instr2
;
instr3
; [Repeat end instruction]
• Example 3: Repeat loop consisting of two instructions
LDRS RptDtct +6; Sets (repeat detection instruction
address + 6) to the RS register
LDRE RptDtct +4
SETRC #4
; Sets (repeat detection instruction
address + 4) to the RE register
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; If RE-RS==-2 during SETRC instruction
execution, the repeat loop is regarded
as two-instruction repeat.
RptDtct:
instr0
; An instruction prior to the Repeat
start instruction is regarded as a
repeat detection instruction.
RptStart: instr1
; [Repeat start instruction]
RptEnd:
; [Repeat end instruction]
instr2
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Section 3 DSP Operating Unit
• Example 4: Repeat loop consisting of one instruction
LDRS RptDtct +8; Sets (repeat detection instruction
address + 8) to the RS register
LDRE RptDtct +4
SETRC #4
; Sets (repeat detection instruction
address + 4) to the RE register
; Sets the number of repetitions (4) to
the RC[11:0] bits of the SR register
; If RE-RS==-4 during SETRC instruction
execution, the repeat loop is regarded
as one-instruction repeat.
RptDtct:
instr0
; An instruction prior to the Repeat
start instruction is regarded as a
repeat detection instruction.
instr1
; [Repeat start instruction]==[Repeat end
instruction]
RptStart:
RptEnd:
In repeat loops consisting of three instructions, two instructions and one instruction, specific
addresses are specified in the RS register. RE – RS is calculated during SETRC instruction
execution, and the number of instructions included in the repeat loop is determined according to
the result. A value of 0, –2,and –4 in the result correspond to three instructions, two instructions,
and one instruction, respectively.
If repeat instruction execution is completed without branching and if RC[11:0] > 0, an instruction
following the repeat detection instruction is regarded as a repeat start instruction and instruction
execution is repeated for the number of times corresponding to the recognized number of
instructions. If RC[11:0] ≥ 2 when the repeat end instruction is completed, the RC[11:0] is
decremented by 1 and then control is passed to the address specified by the RS register. If
RC[11:0] ==1 (or 0) when the repeat end instruction is completed, the RC[11:0] is cleared to 0 and
then the control is passed to the next instruction following the repeat end instruction.
Note: If RE – RS is a positive value, the CPU regards the repeat loop as a four-instruction repeat
loop. (In a repeat loop consisting of four or more instructions, RE – RS is always a
positive value. For details, refer to example 1 above.) If RE – RS is positive, or a value
other than 0, –2,and –4, correct operation cannot be guaranteed.
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Section 3 DSP Operating Unit
Table 3.4 shows the addresses to be specified in the repeat start register (RS) and repeat end
register (RE).
Table 3.4
RS and RE Setting Rule
Number of Instructions in Repeat Loop
1
2
≥4
3
RS
RptStart0 + 8
RptStart0 + 6
RptStart0 + 4
RptStart
RE
RptStart0 + 4
RptStart0 + 4
RptStart0 + 4
RptEnd3 + 4
Note: The terms used above in table 3.2, are defined as follows.
RptStart: Address of the repeat start instruction
RptStart0: Address of the instruction one instruction prior to the repeat start instruction
RptEnd3: Address of the instruction three instructions prior to the repeat end instruction
(2)
Repeat Control Instructions and Repeat Control Macros
To describe a repeat loop, the RS and RE registers must be specified appropriately by the LDRS
and LDRS instructions and then the number of repetitions must be specified by the SERTC
instruction. An 8-bit immediate data or a general register can be used as an operand of the SETRC
instruction. To specify the RC as a value greater than 256, use SETRC Rm type instructions.
Table 3.5
Repeat Control Instructions
Number of
Execution States
Instruction
Operation
LDRS @(disp,PC)
Calculates (disp x 2 + PC) and stores the result to the
RS register
1
LDRE @(disp,PC)
Calculates (disp x 2 + PC) and stores the result to the
RE register
1
SETRC #imm
Sets 8-bit immediate data imm to the RC[11:0] bits of
the SR register and sets the information related to the
number of repetitions to the RF[1:0] bits of the SR.
1
RC[11:0] can be specified as 0 to 255.
SETRC Rm
Sets the[11:0] bits of the Rm register to the RC[11:0]
bits of the SR register and sets the information related
to the number of repetitions to the RF[1:0] bits of the
SR.
1
RC[11:0] can be specified as 0 to 4095.
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Section 3 DSP Operating Unit
The RS and RE registers must be specified appropriately according to the rules shown in table 3.4.
The SH assembler supports control macros (REPEAT) as shown in table 3.6 to solve problems.
Table 3.6
Repeat Control Macros
Number of
Execution States
Instruction
Operation
REPEAT RptStart,
RptEnd, #imm
Specifies RptStart as repeat start instruction, RptEnd as 3
repeat end instruction, and 8-bit immediate data #imm
as number of repetitions. This macro is extended to
three instructions: LDRS, LDRE, and SETRC which are
converted correctly.
REPEAT RptStart,
RptEnd, Rm
Specifies RptStart as repeat start instruction, RptEnd as 3
repeat end instruction, and the [11:0] bits of Rm as
number of repetitions. This macro is extended to three
instructions: LDRS, LDRE, and SETRC which are
converted correctly.
Using the repeat macros shown in table 3.4, examples 1 to 4 shown above can be simplified to
examples 5 to 8 as shown below.
• Example 5: Repeat loop consisting of 4 or more instructions (extended to the instruction
stream shown in example 1, above)
REPEAT RptStart, RptEnd, #4
Instr0
;
RptStart: instr1
Rptend:
; [Repeat start instruction]
... ...
;
... ...
;
instr(N-3)
;
instr(N-2)
;
instr(N-1)
;
instrN
; [Repeat end instruction]
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Section 3 DSP Operating Unit
• Example 6: Repeat loop consisting of three instructions (extended to the instruction stream
shown in example 2, above)
REPEAT RptStart, RptEnd, #4
instr0
RptStart: instr1
RptEnd:
;
; [Repeat start instruction]
instr2
;
instr3
; [Repeat end instruction]
• Example 7: Repeat loop consisting of two instructions (extended to the instruction stream
shown in example 3, above)
REPEAT RptStart, RptEnd, #4
instr0
;
RptStart: instr1
; [Repeat start instruction]
RptEnd:
; [Repeat end instruction]
instr2
• Example 8: Repeat loop consisting of one instruction instructions (extended to the instruction
stream shown in example 4, above)
REPEAT RptStart, RptEnd, #4
instr0
;
instr1
; [Repeat start instruction]==[Repeat end
instruction]
RptStart:
RptEnd:
In the DSP mode, the system control instructions (LDC and STC) that handle the RS and RE
registers are extended. The RC[11:0] bits and RF[1:0] bits of the SR can be controlled by the LDC
and STC instructions for the SR register. These instructions should be used if an exception is
enabled during repeat loop execution. The repeat loop can be resumed correctly by storing the RS
and RE register values and RC[11:0] bits and RF[1:0] bits of the SR register before exception
handling and by restoring the stored values after exception handling. However, note that there are
some restrictions on exception acceptance during repeat loop execution. For details refer to
Restrictions on Repeat Loop Control in section 3.3.1, DSP Repeat Control and section 7,
Exception Handling.
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Section 3 DSP Operating Unit
Table 3.7
DSP Mode Extended System Control Instructions
Instruction
Operation
Number of
Execution States
STC RS, Rn
RS→Rn
1
STC RE, Rn
RE→Rn
1
STC.L RS, @-Rn
Rn-4→Rn, RS→(Rn)
1
STC.L RE, @-Rn
Rn-4→Rn, RE→(Rn)
1
LDC.L @Rn+, RS
(Rn)→RS, Rn+4→Rn
4
LDC.L @Rn+, RE
(Rn)→RE, Rn+4→Rn
4
LDC Rn,RS
Rn →RS
4
LDC Rn, RE
Rn→RE
4
(3)
Restrictions on Repeat Loop Control
(a)
Repeat control instruction assignment
The SETRC instruction must be executed after executing the LDRS and LDRE instructions. In
addition, note that at least one instruction is required between the SETRC instruction and a repeat
start instruction.
(b)
Illegal instruction one or more instructions following the repeat detection instruction
If one of the following instructions is executed between an instruction following a repeat detection
instruction to a repeat end instruction, an illegal instruction exception occurs.
• Branch instructions
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE registers
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Note: This restriction applies to all instructions for a repeat loop consisting of one to three
instructions and to three instructions including a repeat end instruction.
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Section 3 DSP Operating Unit
(c)
Instructions prohibited during repeat loop (In a repeat loop consisting of four or more
instructions)
The following instructions must not be placed between the repeat start instruction and repeat
detection instruction in a repeat loop consisting of four or more instructions. Otherwise, the
correct operation cannot be guaranteed.
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE registers
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+,RS
Note: Multiple repeat loops cannot be guaranteed. Describe the inner loop by repeat control
instructions, and the external loop by other instructions such as DT or BF/S.
(d)
Branching to an instruction following the repeat detection instruction and restriction
on an exception acceptance
Execution of a repeat detection instruction must be completed without any branch so that the CPU
can recognize the repeat loop. Therefore, when the execution branches to an instruction following
the repeat detection instruction, the control will not be passed to a repeat start instruction after
executing a repeat end instruction because the repeat loop is not recognized by the CPU. In this
case, the RC[11:0] bits of the SR register will not be changed.
• If a conditional branch instruction is used in the repeat loop, an instruction before a repeat
detection instruction must be specified as a branch destination.
• If a subroutine call is used in the repeat loop, a delayed slot instruction of the subroutine call
instruction must be placed before a repeat detection instruction.
Here, a branch includes a return from an exception processing routine. If an exception whose
return address is placed in an instruction following the repeat detection instruction occurs, the
repeat control cannot be returned correctly. Accordingly, an exception acceptance is restricted
from the repeat detection instruction to the repeat end instruction. Exceptions such as interrupts
that can be retained by the CPU are retained. For exceptions that cannot be retained by the CPU, a
transition to an exception occurs but a program cannot be returned to the previous execution state
correctly. For details, refer to section 7, Exception Handling.
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Notes: 1. If a TRAPA instruction is used as a repeat detection instruction, an instruction
following the repeat detection instruction is regarded as a return address. In this case, a
control cannot be returned to the repeat control correctly. In a TRAPA instruction, an
address of an instruction following the repeat detection address is regarded as return
address. Accordingly, to return to the repeat control correctly, place a return address
prior to the repeat detection instruction.
2. If a SLEEP instruction is placed following a repeat detection instruction, a transition to
the low-power consumption state or an exception acceptance such as interrupts can be
performed correctly. In this case, however, the repeat control cannot be returned
correctly. To return to the repeat control correctly, the SLEEP instruction must be
placed prior to the repeat detection instruction.
(e)
Branch from a repeat detection instruction
If a repeat detection instruction is a delayed slot instruction of a delayed branch instruction or a
branch instruction, a repeat loop can be acknowledged when a branch does not occur in a
branch instruction. If a branch occurs in a branch instruction, a repeat control is not performed
and a branch destination instruction is executed.
(f) Program counter during repeat control
If RC[11:0] ≥ 2, the program counter (PC) value is not correct for instructions two instructions
following a repeat detection instruction. In a repeat loop consisting of one to three instructions,
the PC indicates the correct value (instruction address + 4) for an instruction (repeat start
instruction) following a repeat detect ion instruction but the PC continues to indicate the same
address (repeat start instruction address) from the subsequent instruction to a repeat end
instruction. In a repeat loop consisting of four or more instructions, the PC indicates the correct
value (instruction address + 4) for an instruction following a repeat detect ion instruction, but
PC indicates the RS and (RS +2) for instructions two and three instructions following the
repeat detection instruction. Here, RS indicates the value stored in the repeat start register
(RS). The correct operation cannot be guaranteed for the incorrect PC values.
Accordingly, PC relative addressing instructions placed two or more instructions following the
repeat detection instruction cannot be executed correctly and the correct results cannot be
obtained.
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Section 3 DSP Operating Unit
• PC relative addressing instructions
MOV.A @(disp, PC), Rn
MOV.W @(disp, PC), Rn
MOV.L @(disp, PC), Rn
(Including the case when the MOV #imm,Rn is extended to MOV.W @(disp, PC), Rn or
MOV.L @(disp, PC), Rn)
Table 3.8
PC Value during Repeat Control (When RC[11:0] ≥ 2)
Number of Instructions in Repeat Loop
3
≥4
RptDtct + 4
RptDtct + 4
RptDtct +4
RptDtct1+ 4
RptDtct1 + 4
RptDtct1 + 4
―
RptDtct1+ 4
RptDtct1 + 4
RS
―
―
RptDtct1 + 4
RS + 2
1
2
RptDtct
RptDtct + 4
RptDtct1
RptDtct1 + 4
RptDtct2
RptDtct3
Note: In table 3.8, the following labels are used.
RptDtct: An address of the repeat detection instruction
RptDtct1:
An address of the instruction one instruction following the repeat start
instruction (In a repeat loop consisting of one to three instructions, RptStart is
a repeat start instruction)
RptDtct2:
An address of the instruction two instruction following the repeat start
instruction
RptDtct3:
An address of the instruction three instruction following the repeat start
instruction
(g)
Repeat counter and repeat control
The CPU always executes a program with comparing the repeat end register (RE) and the program
counter (PC). If the PC matches the RE while the RC[11:0] bits of the SR register are other than 0,
the repeat control function is initiated.
• If RC ≥ 2, a control is passed to a repeat start instruction after a repeat end instruction has been
executed. The RC is decremented by 1 at the completion of the repeat end instruction.
In this case, restrictions (1) to (6) are also applied.
• If RC == 1, the RC is decremented to 0 at the completion of the repeat end instruction and a
control is passed to the subsequent instruction. In this case, restrictions (1) to (6) are also
applied.
• If RC == 0, the repeat control function is not initiated even if a repeat detection instruction is
executed. The repeat loop is executed once as normal instructions and a control is not be
passed to a repeat start instruction even if a repeat end instruction is executed.
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Section 3 DSP Operating Unit
3.4
DSP Data Transfer Instructions
In DSP mode, data transfer instructions are added for the DSP unit registers. The newly added
instructions are classified into the following three groups.
1. Double data transfer instructions
The DSP unit is connected to the X memory and Y memory via the specific buses called X bus
and Y bus. By using the data transfer instructions using the X and Y buses, two data items can
be transferred between the DSP unit and X/Y memories simultaneously. These instructions are
called double data transfer instructions. These double data transfer instructions can be
described in combination with the DSP operation instructions to execute data transfer and data
operation in parallel,
2. Single data transfer instructions
The DSP unit is also connected to the L bus that is used by the CPU. The DSP registers other
than the DSR can access any virtual addresses generated by the CPU. In this case, the single
data transfer instructions are used. The single data transfer instructions cannot be used in
combination with the DSP operation instructions and can access only one data item at a time.
3. System control instructions
Some of the DSP unit registers are handled as the CPU system registers. To control these
system registers, the system control registers are supported. The DSP registers are connected to
the CPU general registers via the data transfer bus (C bus).
In any DSP data transfer instructions, an address to be accessed is generated and output by the
CPU. For DSP data transfer instructions, some of the CPU general registers are used for address
generation and specific addressing modes are used.
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Section 3 DSP Operating Unit
LAB
[31:0]
CPU
XAB
[15:0]
YAB
[15:0]
LDB
[31:0]
CDB
[31:0]
DSP unit
DSR
A0G
X memory
Y memory
XDB
[15:0]
A0
A1G
A1
YDB
[15:0]
M0
M1
X0
X1
Y0
Y1
Legend
XAB : X bus (address)
XDB : X bus (data)
YAB : Y bus (address)
YDB : Y bus (data)
LAB : L bus (address)
LDB : L bus (data)
CDB : C bus (data)
Figure 3.4 DSP Registers and Bus Connections
(1) Double data transfer instructions (MOVX.W, MOVY.W)
With double data transfer instructions, X memory and Y memory can be accessed in parallel.
In this case, the specific buses called X bus and Y bus are used to access X memory and Y
memory, respectively. To fetch the CPU instructions, the L bus is used. Accordingly, no conflict
occurs among X, Y, and L buses.
Load instructions for X memory specify the X0 or X1 register as the destination operand. Load
instructions for Y memory specify the Y0 or Y1 register as the destination operand. Store registers
for X or Y memory specify the A0 or A1 register as the source operand. These instructions use
only word data (16 bits). When a word data transfer instruction is executed, the upper word of
register operand is used. To load word data, data is loaded to the upper word of the destination
register and the lower word of the destination register is automatically cleared to 0.
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Section 3 DSP Operating Unit
Double data transfer instructions can be described in parallel to the DSP operation instructions.
Even if a conditional operation instruction is specified in parallel to a double data transfer
instruction, the specified condition does not affect the data transfer operations. For details, refer to
section 3.5, DSP Data Operation Instructions.
Double data transfer instructions can access only the X memory or Y memory and cannot access
other memory space. The X bus and Y bus are 16 bits and support 64-byte address spaces
corresponding to address areas H'A5000000 to H'A500FFFF and H'A5010000 to H'A501FFFF,
respectively. Because these areas are included in the P2/Uxy area, they are not affected by the
cache and address translation unit.
(2) Single data transfer instructions
The single data transfer instructions access any memory location. All DSP registers other than the
DSR can be specified as source and destination operands.* Guard bit registers A0G and A1G can
also be specified as two independent registers. Because these instructions use the L bus (LAB and
LDB), these instructions can access any virtual space handled by the CPU. If these instructions
access the cacheable area while the cache is enabled, the area accessed by these instructions are
cached. The X memory and Y memory are mapped to the virtual address space and can also be
accessed by the single data transfer instructions. In this case, bus conflict may occur between data
transfer and instruction fetch because the CPU also uses the L bus for instruction fetches.
The single data transfer instructions can handle both word and longword data. In word data
transfer, only the upper word of the operand register is valid. In word data load, word data is
loaded into the upper word of the destination registers and the lower word of the destination is
automatically cleared to 0. If the guard bits are supported, the sign bit is extended before storage.
In longword data load, longword data is loaded into the upper and lower word of the destination
register. If the guard bits are supported, the sign bit is extended before storage. When the guard
register is stored, the sign bit is extended to the upper 24 bits of the LDB and are loaded onto the
LDB bus.
Notes: * Since the DSR register is defined as the system register, it can be accessed by the LDS
or STS instruction.
1. Any data transfer instruction is executed at the MA stage of the pipeline.
2. Any data transfer instruction does not modify the condition code bits of the DSR
register.
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Section 3 DSP Operating Unit
(3) System control instructions
The DSR, A0, X0, X1, Y0, and Y1 registers in the DSP unit can also be used as the CPU system
registers. Accordingly, data transfer operations between these DSP system registers and general
registers or memory can be executed by the STS and LDS instructions. These DSP system
registers can be treated as the CPU system register such as PR, MACH and MACL and can use the
same addressing modes.
Table 3.9
Extended System Control Instructions in DSP Mode
Instruction
Operation
Execution States
STS
DSR,Rn
DSR → Rn
1
STS
A0,Rn
A0 → Rn
1
STS
X0,Rn
X0 → Rn
1
STS
X1,Rn
X1 → Rn
1
STS
Y0,Rn
Y0 → Rn
1
STS
Y1,Rn
Y1 → Rn
1
STS.L
DSR,@-Rn
Rn – 4 → Rn, DSR → (Rn)
1
STS.L
A0,@-Rn
Rn – 4 → Rn, A0 → (Rn)
1
STS.L
X0,@-Rn
Rn – 4 → Rn, X0 → (Rn)
1
STS.L
X1,@-Rn
Rn – 4 → Rn, X1 → (Rn)
1
STS.L
Y0,@-Rn
Rn – 4 → Rn, Y0 → (Rn)
1
STS.L
Y1,@-Rn
Rn – 4 → Rn, Y1 → (Rn)
1
LDS.L
@Rn+,DSR
(Rn) → DSR, Rn + 4 → Rn
1
LDS.L
@Rn+,A0
(Rn) → A0, Rn + 4 → Rn
1
LDS.L
@Rn+,X0
(Rn) → X0, Rn + 4 → Rn
1
LDS.L
@Rn+,X1
(Rn) → X1, Rn + 4 → Rn
1
LDS.L
@Rn+,Y0
(Rn) → Y0, Rn + 4 → Rn
1
LDS.L
@Rn+,Y1
(Rn) → Y1, Rn + 4 → Rn
1
LDS
Rn,DSR
Rn → DSR
1
LDS
Rn,A0
Rn → A0
1
LDS
Rn,X0
Rn → X0
1
LDS
Rn,X1
Rn → X1
1
LDS
Rn,Y0
Rn → Y0
1
LDS
Rn,Y1
Rn → Y1
1
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Section 3 DSP Operating Unit
3.4.1
General Registers
The DSP instructions 10 general registers in the 16 general registers are used as address pointers
or index registers for double data transfers and single data transfers. In the following descriptions,
another register function in the DSP instructions is also indicated within parentheses [ ].
• Double data transfer instructions (X memory and Y memory are accessed simultaneously)
In double data transfers, X memory Y memory can be accessed simultaneously. To specify X
and Y memory addresses, two address pointers are supported.
Address Pointer
Index Register
X memory (MOVX.W)
R4,R5[Ax]
R8 [Ix]
Y memory (MOVY.W)
R6,R7[Ay]
R9 [Iy]
• Single data transfer instructions
In single data transfer, any virtual address space can be accessed via the L bus. The following
address pointers and index registers are used.
Any virtual space (MOVS.W/L)
31
Address Pointer
Index Register
R4,R5, R2, R3[As]
R8 [Is]
0
R0
R1
R2
R3
R4
R5
R6
R7
R8
R9
R10
R11
R12
R13
R14
R15
General registers (DSP mode)
[As2]
[As3]
[As0]
[As1, Ax1]
[Ay0]
[Ay1]
[Ix, Is]
[Iy]
X and Y double data transfers:
R4, 5
R8
[Ax] : Address register set for the X data memory
[Ix] : Index register for X address register set Ax
R6, 7
R9
[Ay] : Address register set for the Y data memory
[Iy] : Index register for Y address register set Ay
Single data transfers:
R4, 5, 2, 3 [As] : Address register set for all data memories
R8
[Is] : Index register used for single data transfers
Figure 3.5 General Registers (DSP Mode)
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Section 3 DSP Operating Unit
In assembler, R0 to R9 are used as symbols. In the DSP data transfer instructions, the following
register names (alias) can also be used. In assembler, described as shown below.
Ix: .REG
(R8)
Ix indicates the alias of register 8. Other aliases are shown below.
Ax0: .REG (R4)
Ax1: .REG (R5)
Ix: .REG (R8)
Ay0: .REG (R6)
Ay1: .REG(R7)
Iy: .REG (R9)
As0: .REG (R4); This definition is used for if the alias is required in the single data transfer
As1: .REG (R5); This definition is used for if the alias is required in the single data transfer
As2: .REG (R2)
As3: .REG (R3)
Is: .REG (R8); This definition is used for if the alias is required in the single data transfer
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Section 3 DSP Operating Unit
3.4.2
DSP Data Addressing
Table 3.10 shows the relationship between the double data transfer instructions and single data
transfer instructions.
Table 3.10 Overview of Data Transfer Instructions
Double Data Transfer
Instructions
Single Data Transfer Instructions
MOVX.W
MOVY.W
MOVS.W, MOVS.L
Address register
Ax: R4, R5
Ay: R6, R7
As: R2, R3, R4, R5
Index register
Ix: R8, Iy: R9
Is: R8
Addressing
Nop/Inc (+2)/index addition:
post-increment
Nop/Inc (+2, +4)/index addition: postincrement

Dec (–2, –4): pre-decrement
Modulo addressing
Possible
Not possible
Data bus
XDB, YDB
LDB
Data length
16 bits (word)
16/32 bits (word/longword)
Bus conflict
No
Yes
Memory
X/Y data memory
Entire memory space
Source register
Da: A0, A1
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
Destination register
Dx: X0/X1
Dy: Y0/Y1
Ds: A0/A1, M0/M1, X0/X1, Y0/Y1,
A0G, A1G
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Section 3 DSP Operating Unit
(1)
Addressing Mode for Double Data Transfer Instructions
The double data transfer instructions supports the following three addressing modes.
• Non-update address register addressing
The Ax and Ay registers are address pointers. They are not updated.
• Increment address register addressing
The Ax and Ay registers are address pointers. After a data transfer, they are each incremented
by 2 (post-increment).
• Addition index register addressing
The Ax and Ay registers are address pointers. After a data transfer, the value of the Ix or Iy
register is added to each (post-increment). The double data transfer instructions do not
supports decrement addressing mode. To perform decrement, –2 or –4 is set in the index
register and addition index register addressing is specified.
When using X/Y data addressing, bit 0 of the address pointer is invalid; bits 0 and 1 of the address
pointer are invalid in word access. Accordingly, bit 0 of the address pointer and index register
must be cleared to 0 in X/Y data addressing.
When accessing X and Y memory using the X and Y buses, the upper word of Ax and Ay is
ignored. The result of Ay+ or Ay+Iy is stored in the lower word of Ay, while the upper word
retains its original value. The Ax and Ax +Ix operations are executed in longword (32 bits) and the
upper word may be changed according to the result.
(2)
Single Data Addressing
The following four kinds of addressing can be used with single data transfer instructions.
• Non-update address register addressing
The As register is an address pointer. An access to @As is performed but As is not updated.
• Increment address register addressing:
The As register is an address pointer. After an access to @As, the As register is incremented
by 2 or 4 (post-increment).
• Addition index register addressing:
The As register is an address pointer. After an access to @As, the value of the Is register is
added to the As register (post-increment).
• Decrement address register addressing:
The As register is an address pointer. Before a data transfer, –2 or –4 is added to the As
register (i.e. 2 or 4 is subtracted) (pre-decrement).
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Section 3 DSP Operating Unit
In single data transfer instructions, all bits in 32-bit address are valid.
3.4.3
Modulo Addressing
In double data transfer instructions, a module addressing can be used. If the address pointer value
reaches the preset modulo end address while a modulo addressing mode is specified,, the address
pointer value becomes the modulo start address.
To control modulo addressing, the modulo register (MOD) extended in the DSP mode and the
DMX and DMY bits of the SR register are used.
The MOD register is provided to set the start and end addresses of the modulo address area. The
upper and lower words of the MOD register store modulo start address (MS) and modulo end
address (ME), respectively. The LDC and STC instructions are extended for MOD register
handling.
If the DMX bit in the SR register is set, the modulo addressing is specified for the X address
register. If the DMY bit in the SR register is set, the modulo addressing is specified for the Y
address register. Modulo addressing is valid for either the X or the Y address register, only; it
cannot be set for both at the same time. Therefore, DMX and DMY cannot both be set
simultaneously (if they are, the DMY setting will be valid). ( In the future, this specification may
be changed.) The MDX and MDY bits of the SR can be specified by the STC or LDC instruction
for the SR register.
If an exception is accepted during modulo addressing, the MDX and MDY bits of the SR and
MOD register must be saved. By restoring these register values, a control is returned to the
modulo addressing after an exception handling.
Table 3.11 Modulo Addressing Control Instructions
Instruction
Operation
Execution States
STC MOD,Rn
MOD → Rn
1
STC.L MOD,Rn
Rn – 4 → Rn, MOD → (Rn)
1
LDC.L @Rn+,MOD
(Rn) → Rn, Rn + 4 → Rn
4
LDC Rn,MOD
Rn → MOD
4
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Section 3 DSP Operating Unit
An example of the use of modulo addressing is shown below.
MOV.L #H’70047000, R10
;Specify MS=H’7000 ME = H’7004
LDC R10,MOD
;Specify ME:MS to MOD register
STC SR, R10
;
MOV.L #H’FFFFF3FF, R11;
MOV.L #H’00000400, R12;
AND R11, R10
;
OR R12, R10
;
LDC R10, SR
; Specify SR.MDX=1,
SR.MDY=0, and X modulo addressing mode
MOV.L #H’A5007000, R4
MOVX.W @R4+,X0
; R4: H’A5007000→ H’A5007002
MOVX.W @R4+,X0
; R4: H’A5007002→ H’A5007004
MOVX.W @R4+,X0
; R4: H’A5007004→ H’A5007000
(Matches to ME and MS is set)
MOVX.W @R4+,X0
; R4: H’A5007000→ H’A5007002
The start and end addresses are specified in MS and ME, then the DMX or DMY bit is set to 1.
When the X or Y data transfer instruction specified by the DMX or DMY is executed, the address
register contents before updating are compared with ME*, and if they match, start address MS is
stored in the address register as the value after updating.
When the addressing type of the X/Y data transfer instruction is no-update, the X/Y data transfer
instruction is not returned to MS even if they match ME. When the addressing type of the X/Y
data transfer instruction is addition index register addressing, the address pointed may not match
the address pointer ME, and exceed it. In this case, the address pointer value does not become the
modulo start address.
The maximum modulo size is 64 kbytes. This is sufficient to access the X and Y data memory.
Note: Not only with modulo addressing, but when X and Y data addressing is used, bit 0 is
ignored. 0 must always be written to bit 0 of the address pointer, index register, MS, and
ME.
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Section 3 DSP Operating Unit
3.4.4
Memory Data Formats
Memory data formats that can be used in the DSP instructions are classified into byte and
longword. An address error will occur if word data starting from an address other than 2n or
longword data starting from an address other than 4n is accessed by MOVS.L, LDS.L, or STS.L
instruction. In such cases, the data accessed cannot be guaranteed
An address error will not occur if word data starting from an address other than 2n is accessed by
the MOVX.W or MOVY.W instruction. When using the MOVX.W or MOVY.W instruction, an
address must be specified on the boundary 2n. If an address is specified other than 2n, the data
accessed cannot be guaranteed.
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Section 3 DSP Operating Unit
3.4.5
Instruction Formats of Double and Single Transfer Instructions
The format of double data transfer instructions is shown in tables 3.12 and that of single data
transfer instructions in table 3.13.
Table 3.12 Double Data Transfer Instruction Formats
Type
Mnemonic
X memory NOPX
data
MOVX.W @Ax,Dx
transfer
MOVX.W @Ax+,Dx
15 14 13 12 11 10 9
1
1
1
1
0
0
8
7
6
5
4
0
0
0
0
Ax
Dx
0
0
1
1
0
1
1
0
1
1
0
1
1
MOVX.W Da,@Ax
Da
1
MOVX.W Da,@Ax+
MOVX.W Da,@Ax+Ix
1
1
1
1
0
0
2
0
MOVX.W @Ax+Ix,Dx
Y memory NOPY
data
MOVY.W @Ay,Dy
transfer
MOVY.W @Ay+,Dy
3
1
0
0
0
0
0
0
Ay
Dy
0
0
1
1
0
1
1
0
1
MOVY.W Da,@Ay+
1
0
MOVY.W Da,@Ay+Iy
1
1
MOVY.W @Ay+Iy,Dy
MOVY.W Da,@Ay
Da
1
Note: Ax: 0 = R4, 1 = R5
Ay: 0 = R6, 1 = R7
Dx: 0 = X0, 1 = X1
Dy: 0 = Y0, 1 = Y1
Da: 0 = A0, 1 = A1
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Section 3 DSP Operating Unit
Table 3.13 Single Data Transfer Instruction Formats
Type
Mnemonic
3
2
1
0
0:(*)
0
0
0
0
0:R4
1:(*)
0
1
MOVS.W @As+,Ds
1:R5
2:(*)
1
0
MOVS.W @As+Is,Ds
2:R2
3:(*)
1
1
MOVS.W Ds,@-As
3:R3
4:(*)
0
0
0
1
MOVS.W Ds,@As
5:A1
0
1
MOVS.W Ds,@As+
6:(*)
1
0
MOVS.W Ds,@As+Is
7:A0
1
1
1
0
1
1
Single data MOVS.W @-As,Ds
transfer
MOVS.W @As,Ds
Note:
*
15 14 13 12 11 10 9
1
1
1
1
0
1
8
As
7
Ds
6
5
4
MOVS.L @-As,Ds
8:X0
0
0
MOVS.L @As,Ds
9:X1
0
1
MOVS.L @As+,Ds
A:Y0
1
0
MOVS.L @As+Is,Ds
B:Y1
1
1
MOVS.L Ds,@-As
C:M0
0
0
MOVS.L Ds,@As
D:A1G
0
1
MOVS.L Ds,@As+
E:M1
1
0
MOVS.L Ds,@As+Is
F:A0G
1
1
Codes reserved for system use.
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Section 3 DSP Operating Unit
3.5
DSP Data Operation Instructions
3.5.1
DSP Registers
This LSI has eight data registers (A0, A1, X0, X1, Y0, Y1, M0 and M1) and one control register
(DSR) as DSP registers (figure 3.3).
Four kinds of operation access the DSP data registers. The first is DSP data processing. When a
DSP fixed-point data operation uses A0 or A1 as the source register, it uses the guard bits (bits 39
to 32). When it uses A0 or A1 as the destination register, guard bits 39 to 32 are valid. When a
DSP fixed-point data operation uses a DSP register other than A0 or A1 as the source register, it
sign-extends the source value to bits 39 to 32. When it uses one of these registers as the
destination register, bits 39 to 32 of the result are discarded.
The second kind of operation is an X or Y data transfer operation, MOVX.W, MOVY.W. This
operation accesses the X and Y memories through the 16-bit X and Y data buses (figure 3.4). The
register to be loaded or stored by this operation always comprises the upper 16 bits (bits 31 to 16).
X0 or X1 can be the destination of an X memory load and Y0 or Y1 can be the destination of a Y
memory load, but no other register can be the destination register in this operation. When data is
read into the upper 16 bits of a register (bits 31 to 16), the lower 16 bits of the register (bits 15 to
0) are automatically cleared. A0 and A1 can be stored in the X or Y memory by this operation, but
no other registers can be stored.
The third kind of operation is a single-data transfer instruction, MOVS.W or MOVS.L. These
instructions access any memory location through the LDB (figure 3.4). All DSP registers connect
to the LDB and can be the source or destination register of the data transfer. These instructions
have word and longword access modes. In word mode, registers to be loaded or stored by this
instruction comprise the upper 16 bits (bits 31 to 16) for DSP registers except A0G and A1G.
When data is loaded into a register other than A0G and A1G in word mode, the lower half of the
register is cleared. When A0 or A1 is used, the data is sign-extended to bits 39 to 32 and the lower
half is cleared. When A0G or A1G is the destination register in word mode, data is loaded into an
8-bit register, but A0 or A1 is not cleared. In longword mode, when the destination register is A0
or A1, it is sign-extended to bits 39 to 32.
The fourth kind of operation is system control instructions such as LDS, STS, LDS.L, or STS.L.
The DSR, A0, X0, X1, Y0, and Y1 registers of the DSP register can be treated as system registers.
For these registers, data transfer instructions between the CPU general registers and system
registers or memory access instructions are supported.
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Section 3 DSP Operating Unit
Tables 3.14 and 3.15 show the data type of registers used in DSP instructions. Some instructions
cannot use some registers shown in the tables because of instruction code limitations. For
example, PMULS can use A1 as the source register, but cannot use A0. These tables ignore details
of register selectability.
Table 3.14 Destination Register in DSP Instructions
Guard Bits
Registers
Instructions
A0, A1
DSP
operation
A0G, A1G
X0, X1
Y0, Y1
M0, M1
39
32
Fixed-point, PSHA,
PMULS
Sign-extended
Register Bits
31
16
15
40-bit result
Integer, PDMSB
Sign-extended 24-bit result
Cleared
Logical, PSHL
Cleared
Cleared
Data
transfer
MOVS.W
Sign-extended 16-bit data
MOVS.L
Sign-extended
Data
transfer
MOVS.W
Data
No update
MOVS.L
Data
No update
DSP
operation
Fixed-point, PSHA,
PMULS
Data
transfer
Cleared
32-bit data
32-bit result
Integer, logical,
PDMSB, PSHL
16-bit result
Cleared
MOVX/Y.W, MOVS.W
16-bit result
Cleared
MOVS.L
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REJ09B0033-0300
16-bit result
32-bit data
0
Section 3 DSP Operating Unit
Table 3.15 Source Register in DSP Operations
Guard Bits
Registers
Instructions
A0, A1
DSP
operation
39
Fixed-point, PDMSB,
PSHA
X0, X1
Y0, Y1
M0, M1
*
16
15
0
24-bit data
Logical, PSHL, PMULS
16-bit data
Data
transfer
MOVX/Y.W, MOVS.W
16-bit data
Data
transfer
MOVS.W
Data
MOVS.L
Data
DSP
Fixed-point, PDMSB,
PSHA
Sign*
Integer
Sign*
Data
transfer
Note:
31
40-bit data
Integer
A0G, A1G
32
Register Bits
32-bit data
MOVS.L
32-bit data
16-bit data
Logical, PSHL, PMULS
16-bit data
MOVS.W
16-bit data
MOVS.L
32-bit data
The data is sign-extended and input to the ALU.
The DSP unit incorporates one control register and DSP status register (DSR). The DSR register
stores the DSP data operation result (zero, negative, others). The DSP register also has the DC bit
whose function is similar to the T bit in the CPU register. The DC bit functions as status flag.
Conditional DSP data operations are controlled based on the DC bit. These operation control
affects only the DSP unit instructions. In other words, these operations control affects only the
DSP registers and does not affect address register update and CPU instructions such as load and
store instructions. A condition to be reflected on the DC bit should be specified to the DC status
selection bits (CS[2:0]).
The unconditional DSP type data instructions other than PMULS, MOVX, MOVY, and MOVS
change the condition flag and DC bit. However, the CPU instructions including the MAC
instruction do not modify the DC bit. In addition, conditional DSP instructions do not modify the
DSR.
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Section 3 DSP Operating Unit
Table 3.16 DSR Register Bits
Bits
Bit Name
Initial
Value
R/W
Function
31 to 8

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7
GT
0
R/W
Signed Greater Bit
Indicates that the operation result is positive (except 0),
or that operand 1 is greater than operand 2
1: Operation result is positive, or operand 1 is greater
than operand 2
6
Z
0
R/W
Zero Bit
Indicates that the operation result is zero (0), or that
operand 1 is equal to operand 2
1: Operation result is zero (0), or operands are equal
5
N
0
R/W
Negative Bit
Indicates that the operation result is negative, or that
operand 1 is smaller than operand 2
1: Operation result is negative, or operand 1 is smaller
than operand 2
4
V
0
R/W
Overflow Bit
Indicates that the operation result has overflowed
1: Operation result has overflowed
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Section 3 DSP Operating Unit
Bits
Bit Name
Initial
Value
R/W
Function
3 to 1
CS
All 0
R/W
DC Bit Status Selection
Designate the mode for selecting the operation result
status to be set in the DC bit
000: Carry/borrow mode
001: Negative value mode
010: Zero mode
011: Overflow mode
100: Signed greater mode
101: Signed greater than or equal to mode
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
0
DC
0
R/W
DSP Status Bit
Sets the status of the operation result in the mode
designated by the CS bits
0: Designated mode status has not occurred
1: Designated mode status has occurred
Indicates the operation result by carry or borrow
regardless of the CS bit status after the PADDC or
PSUBC instruction has been executed.
The DSR is assigned to the system registers. For the DSR, the following load and store
instructions are supported.
STS DSR,Rn;
STS.L DSR,@-Rn;
LDS Rn,DSR;
LDS.L @Rn+,DSR;
If the DSR is read by the STS instruction, upper bits (bits 31 to 16) are all 0.
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Section 3 DSP Operating Unit
3.5.2
DSP Operation Instruction Set
DSP operation instructions are instructions for digital signal processing performed by the DSP
unit. These instructions have a 32-bit instruction code, and multiple instructions can be executed
in parallel. The instruction code is divided into a field A and field B; a parallel data transfer
instruction is specified in the field A, and a single or double data operation instruction in the field
B. Instructions can be specified independently, and are also executed independently.
B-field data operation instructions are of three kinds: double data operation instructions,
conditional single data operation instructions, and unconditional single data operation instructions.
The formats of the DSP operation instructions are shown in table 3.17. The respective operands
are selected independently from the DSP registers. The correspondence between DSP operation
instruction operands and registers is shown in table 3.18.
Table 3.17 DSP Operation Instruction Formats
Type
Instruction Formats
Double data operation instructions
ALUop. Sx, Sy, Du
MLTop. Se, Df, Dg
Conditional single data operation
instructions
Unconditional single data operation
instructions
DCT
ALUop. Sx, Sy, Dz
DCF
ALUop. Sx, Sy, Dz
DCT
ALUop. Sx, Dz
DCF
ALUop. Sx, Dz
DCT
ALUop. Sy, Dz
DCF
ALUop. Sy, Dz
ALUop. Sx, Sy, Dz
ALUop. Sx, Dz
ALUop. Sy, Dz
MLTop. Se, Sf, Dg
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Section 3 DSP Operating Unit
Table 3.18 Correspondence between DSP Instruction Operands and Registers
ALU Operations
Register
Sx
A0
A1
Sy
Multiply Operations
Dz
Du
Yes
Yes
Yes
Yes
Yes
Yes
Se
Sf
Yes
Yes
Dg
Yes
Yes
M0
Yes
Yes
Yes
M1
Yes
Yes
Yes
X0
Yes
Yes
X1
Yes
Yes
Y0
Yes
Yes
Y1
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
When writing parallel instructions, the field-B instruction is written first, followed by the field-A
instruction. A sample parallel processing program is shown in figure 3.6.
DCF
PADD
A0, M0, A0
PINC
M1, A1
PCMP M1, M0
PMULS X0, Y0, M0
MOVX.W @R4+,
X0
MOVY.W @R6+, Y0
MOVX.W @R5+R8, X0
MOVY.W @R7+, Y1
MOVX.W @R4,
[NOPY]
X1
Figure 3.6 Sample Parallel Instruction Program
Square brackets mean that the contents can be omitted.
The no operation instructions NOPX and NOPY can be omitted. For details on the field B in DSP
data operation instructions, refer to section 3.6.4, DSP Operation Instructions.
The DSR register condition code bit (DC) is always updated on the basis of the result of an
unconditional ALU or shift operation instruction. Conditional instructions do not update the DC
bit. Multiply instructions, also, do not update the DC bit. DC bit updating is performed by means
of the CS[2:0] bits in the DSR register. The DC bit update rules are shown in table 3.19.
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Section 3 DSP Operating Unit
Table 3.19 DC Bit Update Definitions
CS [2:0]
Condition Mode
Description
0
Carry or borrow
mode
The DC bit is set if an ALU arithmetic operation generates a carry
or borrow, and is cleared otherwise.
0
0
When a PSHA or PSHL shift instruction is executed, the last bit
data shifted out is copied into the DC bit.
When an ALU logical operation is executed, the DC bit is always
cleared.
0
0
1
Negative value
mode
When an ALU or shift (PSHA) arithmetic operation is executed,
the MSB of the result, including the guard bits, is copied into the
DC bit.
When an ALU or shift (PSHL) logical operation is executed, the
MSB of the result, excluding the guard bits, is copied into the DC
bit.
0
1
0
Zero value mode
The DC bit is set if the result of an ALU or shift operation is allzeros, and is cleared otherwise.
0
1
1
Overflow mode
The DC bit is set if the result of an ALU or shift (PSHA) arithmetic
operation exceeds the destination register range, excluding the
guard bits, and is cleared otherwise.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
1
0
0
Signed greater-than This mode is similar to signed greater-or-equal mode, but DC is
mode
cleared if the result is all-zeros.
DC = ~{(negative value ^ over-range) | zero value};
In case of arithmetic operation
DC = 0; In case of logical operation
1
0
1
Signed greater-orequal mode
If the result of an ALU or shift (PSHA) arithmetic operation
exceeds the destination register range, including the guard bits
(over-range), the definition is the same as in negative value mode.
If the result is not over-range, the definition is the opposite of that
in negative value mode.
When an ALU or shift (PSHL) logical operation is executed, the
DC bit is always cleared.
DC = ~(negative value ^ over-range);
In case of arithmetic operation
DC = 0 ; In case of logical operation
1
1
0
Reserved (setting prohibited)
1
1
1
Reserved (setting prohibited)
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Section 3 DSP Operating Unit
• Conditional Operations and Data Transfer
Some instructions belonging to this class can be executed conditionally, as described earlier.
The specified condition is valid only for the B field of the instruction, and is not valid for data
transfer instructions for which a parallel specification is made. Examples are shown in figure
3.7.
DCT PADD X0,Y0,A0
MOVX.W @R4+,X0
MOVY.W A0,@R6+R9
When condition is True
Before execution: X0=H'33333333, Y0=H'55555555,
R4=H'00008000, R6=H'00005000,
(R4)=H'1111, (R6)=H'2222
After execution: X0=H'11110000, Y0=H'55555555,
R4=H'00008002, R6=H'00005004,
(R4)=H'1111, (R6)=H'3456
A0=H'123456789A,
R9=H'00000004
A0=H'0088888888,
R9=H'00000004
When condition is False
Before execution: X0=H'33333333, Y0=H'55555555,
R4=H'00008000, R6=H'00005000,
(R4)=H'1111, (R6)=H'2222
After execution: X0=H'11110000, Y0=H'55555555,
R4=H'00008002, R6=H'00005004,
(R4)=H'1111, (R6)=H'3456
A0=H'123456789A,
R9=H'00000004
A0=H'123456789A,
R9=H'00000004
Figure 3.7 Examples of Conditional Operations and Data Transfer Instructions
• Assignment of NOPX and NOPY Instruction Codes
When there is no data transfer instruction to be parallel-processed simultaneously with a DSP
operation instruction, an NOPX or NOPY instruction can be written as the data transfer
instruction, or the instruction can be omitted. The instruction code is the same whether an
NOPX or NOPY instruction is written or the instruction is omitted. Examples of NOPX and
NOPY instruction codes are shown in table 3.20.
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Section 3 DSP Operating Unit
Table 3.20 Examples of NOPX and NOPY Instruction Codes
Instruction
PADD X0,Y0,A0
Code
MOVX.W @R4+,X0
MOVY.W @R6+R9,Y0
1111100000001011
1011000100000111
PADD X0,Y0,A0
NOPX
MOVY.W @R6+R9,Y0
1111100000000011
1011000100000111
PADD X0,Y0,A0
NOPX
PADD X0,Y0,A0
NOPX
NOPY
1111100000000000
1011000100000111
1111100000000000
1011000100000111
PADD X0,Y0,A0
1111100000000000
1011000100000111
MOVX.W @R4+,X0
MOVY.W @R6+R9,Y0
1111000000001011
MOVX.W @R4+,X0
NOPY
1111000000001000
MOVS.W @R4+,X0
NOPX
NOPX
NOP
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1111010010001000
MOVY.W @R6+R9,Y0
1111000000000011
MOVY.W @R6+R9,Y0
1111000000000011
NOPY
1111000000000000
0000000000001001
Section 3 DSP Operating Unit
3.5.3
DSP-Type Data Formats
This LSI has several different data formats that depend on the instruction. This section explains
the data formats for DSP type instructions.
Figure 3.8 shows three DSP-type data formats with different binary point positions. A CPU-type
data format with the binary point to the right of bit 0 is also shown for reference.
The DSP-type fixed point data format has the binary point between bit 31 and bit 30. The DSPtype integer format has the binary point between bit 16 and bit 15. The DSP-type logical format
does not have a binary point. The valid data lengths of the data formats depend on the instruction
and the DSP register.
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Section 3 DSP Operating Unit
DSP type fixed point
39
With guard bits
31 30
0
–28 to +28 – 2–31
S
31 30
Without guard bits
0
–1 to +1 – 2–31
S
39
31 30
16 15
0
–1 to +1 – 2–15
S
Multiplier input
DSP type integer
39
With guard bits
32 31
16 15
0
–223 to +223 – 1
S
16 15
31
Without guard bits
S
Shift amount for
arithmetic shift (PSHA)
31
–215 to +215 – 1
16 15
22
0
–32 to +32
S
31
Shift amount for
logical shift (PSHL)
0
21 16 15
0
–16 to +16
S
39
31
16 15
0
DSP type logical
CPU type integer
31
Longword
S: Sign bit
0
–231 to +231 – 1
S
: Binary point
: Does not affect the operations
Figure 3.8 Data Formats
The shift amount for the arithmetic shift (PSHA) instruction has a 7-bit field that can represent
values from –64 to +63, but –32 to +32 are valid numbers for the instruction. Also the shift
amount for a logical shift operation has a 6-bit field, but –16 to +16 are valid numbers for the
instruction.
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Section 3 DSP Operating Unit
3.5.4
ALU Fixed-Point Arithmetic Operations
Figure 3.9 shows the ALU arithmetic operation flow. Table 3.21 shows the variation of this type
of operation and table 3.22 shows the correspondence between each operand and registers.
39
Guard
31
0
39
Source 1
Guard
31
0
Source 2
ALU
GT
Z
N
V DC
DSR
Guard
39
Destination
31
0
Figure 3.9 ALU Fixed-Point Arithmetic Operation Flow
Note: The ALU fixed-point arithmetic operations are basically 40-bit operation; 32 bits of the
base precision and 8 bits of the guard-bit parts. So the signed bit is copied to the guard-bit
parts when a register not providing the guard-bit parts is specified as the source operand.
When a register not providing the guard-bit parts is specified as a destination operand, the
lower 32 bits of the operation result are input into the destination register.
ALU fixed-point operations are executed between registers. Each source and destination operand
are selected independently from one of the DSP registers. When a register providing guard bits is
specified as an operand, the guard bits are activated for this type of operation. These operations
are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the
MA stage in which memory access is performed.
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Section 3 DSP Operating Unit
Table 3.21 Variation of ALU Fixed-Point Operations
Mnemonic
Function
Source 1
Source 2
Destination
PADD
Addition
Sx
Sy
Dz (Du)
PSUB
Subtraction
Sx
Sy
Dz (Du)
PADDC
Addition with carry
Sx
Sy
Dz
PSUBC
Subtraction with borrow
Sx
Sy
Dz
PCMP
Comparison
Sx
Sy

PCOPY
Data copy
Sx
All 0
Dz
All 0
Sy
Dz
All 0
Dz
PABS
Absolute
Sx
All 0
Sy
Dz
PNEG
Negation
Sx
All 0
Dz
All 0
Sy
Dz
All 0
All 0
Dz
PCLR
Clear
Table 3.22 Correspondence between Operands and Registers
Register
Sx
A0
A1
Sy
Dz
Du
Yes
Yes
Yes
Yes
Yes
Yes
M0
Yes
Yes
M1
Yes
Yes
X0
Yes
X1
Yes
Yes
Yes
Yes
Y0
Yes
Yes
Y1
Yes
Yes
Yes
As shown in figure 3.10, data loaded from the memory at the MA stage, which is programmed at
the same line as the ALU operation, is not used as a source operand for this operation, even
though the destination operand of the data load operation is identical to the source operand of the
ALU operation. In this case, previous operation results are used as the source operands for the
ALU operation, and then updated as the destination operand of the data load operation.
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Section 3 DSP Operating Unit
Operation Sequence Example
PADD X0, Y0, A0
Slot
Stage
IF
ID
EX
MA/DSP
MOVX.W @R4 + X0
MOVX.W @R4 + X0
3
1
2
MOVX
MOVX & PADD
MOVX
4
5
6
MOVX & PADD
Addressing
Addressing
MOVX
MOVX & PADD
Previous cycle result is used.
Figure 3.10 Operation Sequence Example
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. However, in case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of a DC bit is selected by CS[2:0] (condition selection) bits in
DSR. The DC bit result is as follows:
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Section 3 DSP Operating Unit
(1)
Carry or Borrow Mode: CS[2:0] = B'000
The DC bit indicates that carry or borrow is generated from the most significant bit of the
operation result, except the guard-bit parts. Some examples are shown in figure 3.11. This mode is
the default condition. When the input data is negative in a PABS or PNEG instruction, carry is
generated.
Example 1
Guard bits
Example 2
Guard bits
0000 0000 1111111111111111
+) 0000 0000 0000 0000 0000 0001
0000 0001 0000 0000 0000 0000
111111110111 0000 0000 0000
+) 0011 11110001 0000 0000 0000
(1) 0011 11101000 0000 0000 0000
Carry detecting point
Carry detecting point
Carry is detected
Carry is not detected
Example 3
Example 4
Guard bits
Guard bits
0000 0000 0000 0000 0000 0001
–) 0000 0000 0000 0000 0000 0001
0000 0000 0000 0000 0000 0000
Borrow detecting point
Borrow is not detected
0000 0000 0001 0000 0000 0001
–) 0000 0000 0001 0000 0000 0010
111111111111111111111111
Borrow detecting point
Borrow is detected
Figure 3.11 DC Bit Generation Examples in Carry or Borrow Mode
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Section 3 DSP Operating Unit
(2)
Negative Value Mode: CS[2:0] = B'001
The DC flag indicates the same value as the MSB of the operation result. When the result is a
negative number, the DC bit shows 1. When it is 0 or a positive number, the DC bit shows 0. The
ALU always executes 40-bit arithmetic operation, so the sign bit to detect whether positive or
negative is always got from the MSB of the operation result regardless of the destination operand.
Some examples are shown in figure 3.12.
Example 1
Guard bits
Example 2
Guard bits
1100 0000 0000 0000 0000 0000
+) 0000 0000 0000 0000 0000 0001
1100 0000 0000 0000 0000 0001
Sign bit
Negative value
0011 0000 0000 0000 0000 0000
+) 0000 0000 1000 0000 0000 0001
0011 0000 1000 0000 0000 0001
Sign bit
Positive value
Figure 3.12 DC Bit Generation Examples in Negative Value Mode
(3)
Zero Value Mode: CS[2:0] = B'010
The DC flag indicates whether the operation result is 0 or not. When the result is 0, the DC bit
shows 1. When it is not 0, the DC bit shows 0.
(4)
Overflow Mode: CS[2:0] = B'011
The DC bit indicates whether or not overflow occurs in the result. When an operation yields a
result beyond the range of the destination register, except the guard-bit parts, the DC bit is set.
Even though guard bits are provided in the destination register, the DC bit always indicates the
result of when no guard bits are provided. So, the DC bit is always set to 1 if the guard-bit parts
are used for large number representation. Some DC bit generation examples in overflow mode are
shown in figure 3.13.
Example 1
Guard bits
Example 2
Guard bits
111111111111111111111111
+) 111111111000 0000 0000 0000
111111110111111111111111
Overflow detecting field
Overflow case
111111111111111111111111
+) 111111111000 0000 0000 0001
111111111000 0000 0000 0000
Overflow detecting field
Non overflow case
Figure 3.13 DC Bit Generation Examples in Overflow Mode
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Section 3 DSP Operating Unit
(5)
Signed Greater Than Mode: CS[2:0] = B'100
The DC bit indicates whether or not the source 1 data (signed) is greater than the source 2 data
(signed) as the result of compare operation PCMP. The PCMP operation should be executed
before executing the conditional operation under this condition mode. This mode is similar to the
Negative Value Mode described before, because the result of a compare operation is a positive
value if the source 1 data is greater than the source 2 data. However, the signed bit of the result
shows a negative value if the compare operation yields a result beyond the range of the destination
operand, including the guard-bit parts (called “Over-range”), even though the source 1 data is
greater than the source 2 data. The DC bit is updated concerning this type of special case in this
condition mode. The equation below shows the definition of getting this condition:
DC = ~ {(Negative ^ Over-range) | Zero}
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of the CMP/GT operation of the CPU instruction.
(6)
Signed Greater Than or Equal Mode: CS[2:0] = B'101
The DC bit indicates whether the source 1 data (signed) is greater than or equal to the source 2
data (signed) as the result of compare operation PCMP. This mode is similar to the Signed Greater
Than Mode described before but the equal case is also included in this mode. The equation below
shows the definition of getting this condition:
DC = ~ (Negative ^ Over-range)
When the PCMP operation is executed under this condition mode, the result of the DC bit is the
same as the T bit’s result of a CMP/GE operation of the CPU instruction.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
Note: The DC bit is always updated as the carry flag for ‘PADDC’ and is always updated as the
carry/borrow flag for ‘PSUBC’ regardless of the CS[2:0] state.
• Overflow Protection
The S bit in SR is effective for any ALU fixed-point arithmetic operations in the DSP unit. See
section 3.5.11, Overflow Protection, for details.
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Section 3 DSP Operating Unit
3.5.5
ALU Integer Operations
Figure 3.14 shows the ALU integer arithmetic operation flow. Table 3.23 shows the variation of
this type of operation. The correspondence between each operand and registers is the same as
ALU fixed-point operations as shown in table 3.22.
39
Guard
0
31
39
Guard
Source 1
31
0
Source 2
ALU
GT
Z
N
V DC
DSR
Ignored
Destination
Guard
39
Cleared to 0
0
31
Figure 3.14 ALU Integer Arithmetic Operation Flow
Table 3.23 Variation of ALU Integer Operations
Mnemonic
Function
Source 1
Source 2
Destination
PINC
Increment by 1
Sx
+1
Dz
+1
Sy
Dz
Sx
–1
Dz
–1
Sy
Dz
PDEC
Decrement by 1
Note: The ALU integer operations are basically 24-bit operation, the upper 16 bits of the base
precision and 8 bits of the guard-bits parts. So the signed bit is copied to the guard-bit parts
when a register not providing the guard-bit parts is specified as the source operand. When
a register not providing the guard-bit parts is specified as a destination operand, the upper
word excluding the guard bits of the operation result are input into the destination register.
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Section 3 DSP Operating Unit
In ALU integer arithmetic operations, the lower word of the source operand is ignored and the
lower word of the destination operand is automatically cleared. The guard-bit parts are effective in
ALU integer arithmetic operations if they are supported. Others are basically the same operation
as ALU fixed-point arithmetic operations. As shown in table 3.23, however, this type of operation
provides two kinds of instructions only, so that the second operand is actually either +1 or –1.
When a word data is loaded into one of the DSP unit’s registers, it is input as an upper word data.
When a register providing guard bits is specified as an operand, the guard bits are also activated.
These operations, as well as fixed-point operations, are executed in the DSP stage, as shown in
figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is
performed.
Every time an ALU arithmetic operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. This is the same as fixed-point
operations but the lower word of each source and destination operand is not used in order to
generate them. See section 3.5.4, ALU Fixed-Point Arithmetic Operations, for details.
In case of a conditional operation, they are not updated even though the specified condition is true
and the operation is executed. In case of an unconditional operation, they are always updated in
accordance with the operation result. See section 3.5.4, ALU Fixed-Point Arithmetic Operations,
for details.
• Overflow Protection
The S bit in SR is effective for any ALU integer arithmetic operations in DSP unit. See section
3.5.11, Overflow Protection, for details.
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Section 3 DSP Operating Unit
3.5.6
ALU Logical Operations
Figure 3.15 shows the ALU logical operation flow. Table 3.24 shows the variation of this type of
operation. The correspondence between each operand and registers is the same as the ALU fixedpoint operations as shown in table 3.21.
As shown in figure 3.15, this type of operation uses only the upper word of each operand. The
lower word and guard-bit parts are ignored for the source operand and those of the destination
operand are automatically cleared. These operations are also executed in the DSP stage, as shown
in figure 3.10. The DSP stage is the same stage as the MA stage in which memory access is
performed.
39
0
31
39
31
0
Source 2
Source 1
ALU
GT
Z
N
V DC
DSR
Ignored
Destination
39
31
Cleared to 0
0
Figure 3.15 ALU Logical Operation Flow
Table 3.24 Variation of ALU Logical Operations
Mnemonic
Function
Source 1
Source 2
Destination
PAND
Logical AND
Sx
Sy
Dz
POR
Logical OR
Sx
Sy
Dz
PXOR
Logical exclusive OR
Sx
Sy
Dz
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Section 3 DSP Operating Unit
Every time an ALU logical operation is executed, the DC, N, Z, V, and GT bits in the DSR
register are basically updated in accordance with the operation result. In case of a conditional
operation, they are not updated even though the specified condition is true and the operation is
executed. In case of an unconditional operation, they are always updated in accordance with the
operation result. The definition of the DC bit is selected by the CS[2:0] (condition selection) bits
in DSR. The DC bit result is:
(1)
Carry or Borrow Mode: CS[2:0] = 000
The DC bit is always cleared.
(2)
Negative Value Mode: CS[2:0] = 001
Bit 31 of the operation result is loaded into the DC bit.
(3)
Zero Value Mode: CS[2:0] = 010
The DC bit is set when the operation result is zero; otherwise it is cleared.
(4)
Overflow Mode: CS[2:0] = 011
The DC bit is always cleared.
(5)
Signed Greater Than Mode: CS[2:0] = 100
The DC bit is always cleared.
(6)
Signed Greater Than or Equal Mode: CS[2:0] = 101
The DC bit is always cleared.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
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Section 3 DSP Operating Unit
3.5.7
Fixed-Point Multiply Operation
Figure 3.16 shows the multiply operation flow. Table 3.25 shows the variation of this type of
operation and table 3.26 shows the correspondence between each operand and registers. The
multiply operation of the DSP unit is single-word signed single-precision multiplication. These
operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same
stage as the MA stage in which memory access is performed.
If a double-precision multiply operation is needed, the CPU standard double-word multiply
instructions can be made of use.
39
31
0
39
31
S Source 1
0
S Source 2
0
MAC
S
39
Destination
31
0
Ignored
1 0
Figure 3.16 Fixed-Point Multiply Operation Flow
Table 3.25 Variation of Fixed-Point Multiply Operation
Mnemonic
Function
Source 1
Source 2
Destination
PMULS
Signed multiplication
Se
Sf
Dg
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Section 3 DSP Operating Unit
Table 3.26 Correspondence between Operands and Registers
Register
Se
Sf
Dg
A0


Yes
A1
Yes
Yes
Yes
M0


Yes
M1


Yes
X0
Yes
Yes

X1
Yes


Y0
Yes
Yes

Y1

Yes

Note: The multiply operations basically generate 32-bit operation results. So when a register
providing the guard-bit parts are specified as a destination operand, the guard-bit parts will
copy bit 31 of the operation result.
The multiply operation of the DSP unit side is not integer but fixed-point arithmetic operation. So,
the upper words of each multiplier and multiplicand are input into a MAC unit as shown in figure
3.16. In the SH’s standard multiply operations, the lower words of both source operands are input
into a MAC unit. The operation result is also different from the SH’s case. The SH’s multiply
operation result is aligned to the LSB of the destination, but the fixed-point multiply operation
result is aligned to the MSB, so that the LSB of the fixed-point multiply operation result is always
0.
The fixed-point multiply operation is executed in one cycle. Multiply is always unconditional, but
does not affect any condition code bits, DC, N, Z, V, and GT , in DSR.
• Overflow Protection
The S bit in SR is effective for this multiply operation in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
If the S bit is 0, overflow occurs only when H'8000*H'8000 ((-1.0)*(-1.0)) operation is
executed as signed fixed-point multiply. The result is H'00 8000 0000 but it does not mean
(+1.0). If the S bit is 1, overflow is prevented and the result is H'00 7FFF FFFF.
Rev. 3.00 Jan. 18, 2008 Page 136 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.5.8
Shift Operations
Shift operations can use either register or immediate value as the shift amount operand. Other
source and destination operands are specified by the register. There are two kinds of shift
operations of arithmetic and logical shifts. Table 3.27 shows the variation of this type of operation.
The correspondence between each operand and registers, except for immediate operands, is the
same as the ALU fixed-point operations as shown in table 3.21.
Table 3.27 Variation of Shift Operations
Mnemonic
Function
Source 1
Source 2
Destination
PSHA Sx, Sy, Dz
Arithmetic shift
Sx
Sy
Dz
PSHL Sx, Sy, Dz
Logical shift
Sx
Sy
Dz
PSHA #Imm1, Dz Arithmetic shift with
immediate.
Dz
Imm1
Dz
PSHL #Imm2, Dz Logical shift with
immediate.
Dz
Imm2
Dz
–32 <= Imm1 <= +32, –16 <= Imm2 <= +16
(1)
Arithmetic Shift
Figure 3.17 shows the arithmetic shift operation flow.
Left shift
39
32 31
Right shift
16 15
0
39
32 31
16 15
0
0
(MSB copy)
Shift out
>=0
39
Shift amount data
(source 2)
32 31
Shift out
<0
+32 to -32
23 22 16 15
GT
Updated
0
Z
N
V DC
DSR
Sy
6
0
Imm1
Ignored
Figure 3.17 Arithmetic Shift Operation Flow
Rev. 3.00 Jan. 18, 2008 Page 137 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Note: The arithmetic shift operations are basically 40-bit operation, that is, the 32 bits of the
base precision and eight bits of the guard-bit parts. So the signed bit is copied to the guardbit parts when a register not providing the guard-bit parts is specified as the source
operand. When a register not providing the guard-bit parts is specified as a destination
operand, the lower 32 bits of the operation result are input into the destination register.
In this arithmetic shift operation, all bits of the source 1 and destination operands are activated.
The shift amount is specified by the source 2 operand as an integer data. The source 2 operand can
be specified by either a register or immediate operand. The available shift range is from –32 to
+32. Here, a negative value means the right shift, and a positive value means the left shift. It is
possible for any source 2 operand to specify from –64 to +63 but the result is unknown if an
invalid shift value is specified. In case of a shift with an immediate operand instruction, the source
1 operand must be the same register as the destination’s. This operation is executed in the DSP
stage, as shown in figure 3.10 as well as in fixed-point operations. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time an arithmetic shift operation is executed, the DC, N, Z, V, and GT bits in DSR are
basically updated in accordance with the operation result. In case of a conditional operation, they
are not updated even though the specified condition is true and the operation is executed. In case
of an unconditional operation, they are always updated in accordance with the operation result.
The definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC
bit result is:
1. Carry or Borrow Mode: CS[2:0] = B'000
The DC bit indicates the last shifted out data as the operation result.
2. Negative Value Mode: CS[2:0] = B'001
The DC bit is set to 1 when the operation result is a negative value, and cleared to 0 when the
operation result is zero or a positive value.
3. Zero Value Mode: CS[2:0] = B'010
The DC bit is set when the operation result is zero; otherwise it is cleared.
4. Overflow Mode: CS[2:0] = B'011
The DC bit is set to 1 when an overflow occurs.
5. Signed Greater Than Mode: CS[2:0] = B'100
The DC bit is always cleared to 0.
6. Signed Greater Than or Equal Mode: CS[2:0] = B'101
The DC bit is always cleared to 0.
Rev. 3.00 Jan. 18, 2008 Page 138 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits. See the
overflow mode part above. The GT bit always indicates the same state as the DC bit set in signed
greater than mode by the CS[2:0] bits. See the signed greater than mode part above.
• Overflow Protection
The S bit in SR is also effective for arithmetic shift operation in the DSP unit. See section
3.5.11, Overflow Protection, for details.
(2)
Logical Shift
Figure 3.18 shows the logical shift operation flow.
Cleared to 0
39
Left shift
32 31
Right shift
16 15
0
39
0
Shift out
0
>=0
39
32 31
32 31
<0
+16 to -16
22 21 16 15
Shift amount data
(source 2)
16 15
0
Shift out
GT
Updated
Z
N
V DC
DSR
0
Sy
5
Ignored
0
Imm2
Figure 3.18 Logical Shift Operation Flow
As shown in figure 3.18, the logical shift operation uses the upper word of the source 1 operand
and the destination operand. The lower word and guard-bit parts are ignored for the source
operand and those of the destination operand are automatically cleared as in the ALU logical
operations. The shift amount is specified by the source 2 operand as an integer data. The source 2
operand can be specified by either the register or immediate operand. The available shift range is
from –16 to +16. Here, a negative value means the right shift, and a positive value means the left
shift. It is possible for any source 2 operand to specify from –32 to +31, but the result is unknown
if an invalid shift value is specified. In case of a shift with an immediate operand instruction, the
source 1 operand must be the same register as the destination’s. These operations are executed in
the DSP stage, as shown in figure 3.10. The DSP stage is the same stage as the MA stage in which
memory access is performed.
Rev. 3.00 Jan. 18, 2008 Page 139 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Every time a logical shift operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated even though the specified condition is true and the operation is executed. In case of an
unconditional operation, they are always updated in accordance with the operation result. The
definition of the DC bit is selected by the CS[2:0] (condition selection) bits in DSR. The DC bit
result is:
1. Carry or Borrow Mode: CS[2:0] = B'000
The DC bit indicates the last shifted out data as the operation result.
2. Negative Value Mode: CS[2:0] = B'001
Bit 31 of the operation result is loaded into the DC bit.
3. Zero Value Mode: CS[2:0] = B'010
The DC bit is set to 1 when the operation result is zero; otherwise it is cleared to 0.
4. Overflow Mode: CS[2:0] = B'011
The DC bit is always cleared to 0.
5. Signed Greater Than Mode: CS[2:0] = B'100
The DC bit is always cleared to 0.
6. Signed Greater Than or Equal Mode: CS[2:0] = B'101
The DC bit is always cleared.
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit
always indicates the same state as the DC bit set in overflow mode by the CS[2:0] bits, but it is
always cleared in this operation. So is the GT bit.
Rev. 3.00 Jan. 18, 2008 Page 140 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.5.9
Most Significant Bit Detection Operation
The PDMSB, most significant bit detection operation, is used to calculate the shift amount for
normalization. Figure 3.19 shows the PDMSB operation flow and table 3.28 shows the operation
definition. Table 3.29 shows the possible variations of this type of operation. The correspondence
between each operand and registers is the same as for ALU fixed-point operations, as shown in
table 3.21.
Note: The result of the MSB detection operation is basically 24 bits as well as ALU integer
operation, the upper 16 bits of the base precision and eight bits of the guard-bit parts.
When a register not providing the guard-bit parts is specified as a destination operand, the
upper word of the operation result is input into the destination register.
As shown in figure 3.19, the PDMSB operation uses all bits as a source operand, but the
destination operand is treated as an integer operation result because shift amount data for
normalization should be integer data as described in section 3.5.8, Shift Operations. These
operations are executed in the DSP stage, as shown in figure 3.10. The DSP stage is the same
stage as the MA stage in which memory access is performed.
Every time a PDMSB operation is executed, the DC, N, Z, V, and GT bits in DSR are basically
updated in accordance with the operation result. In case of a conditional operation, they are not
updated, even though the specified condition is true, and the operation is executed. In case of an
unconditional operation, they are always updated with the operation result.
39
31
0
Source 1 or 2
Guard
GT
Priority encoder
Guard
39
Z
N
V DC
DSR
Cleared to 0
31
0
Figure 3.19 PDMSB Operation Flow
Rev. 3.00 Jan. 18, 2008 Page 141 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
The definition of the DC bit is selected by the CS0 to CS2 (condition selection) bits in DSR. The
DC bit result is
(1)
Carry or Borrow Mode: CS[2:0] = B'000
The DC bit is always cleared to 0.
(2)
Negative Value Mode: CS[2:0] = B'001
The DC bit is set when the operation result is a negative value, and cleared to 0 when the
operation result is zero or a positive value.
(3)
Zero Value Mode: CS[2:0] = B'010
The DC bit is set when the operation result is zero; otherwise it is cleared to 0.
(4)
Overflow Mode: CS[2:0] = B'011
The DC bit is always cleared to 0.
(5)
Signed Greater Than Mode: CS[2:0] = B'100
The DC bit is set to 1 when the operation result is a positive value; otherwise it is cleared to 0.
(6)
Signed Greater Than or Equal Mode: CS[2:0] = B'101
The DC bit is set to 1 when the operation result is zero or a positive value; otherwise it is cleared
to 0.
Rev. 3.00 Jan. 18, 2008 Page 142 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Table 3.28 Operation Definition of PDMSB
Source Data
Guard Bit
Result for DST
Upper Word
Guard
Bit
Upper Word
Lower Word
39 38 … 33 32 31 30 29 28 …
3
2
1
0
39 to
32
31 to 21 20 19 18 17 16 Decimal
22
0
0
… 0
0
0
0
0
0
…
0
0
0
0
All 0
All 0
0
1
0
0
… 0
0
0
0
0
0
…
0
0
0
1
All 0
All 0
0
1
1
1
1
0
+30
0
0
… 0
0
0
0
0
0
…
0
0
1
*
All 0
All 0
0
1
1
1
0
1
+29
0
0
… 0
0
0
0
0
0
…
0
1
*
*
All 0
All 0
0
1
1
1
0
0
+28
:
:
1
1
1
1
+31
:
0
0
… 0
0
0
0
0
1
…
*
*
*
*
All 0
All 0
0
0
0
0
1
0
+2
0
0
… 0
0
0
0
1
*
…
*
*
*
*
All 0
All 0
0
0
0
0
0
1
+1
0
0
… 0
0
0
1
*
*
…
*
*
*
*
All 0
All 0
0
0
0
0
0
0
0
0
0
… 0
0
1
*
*
*
…
*
*
*
*
All 1
All 1
1
1
1
1
1
1
–1
0
0
… 0
1
*
*
*
*
…
*
*
*
*
All 1
All 1
1
1
1
1
1
0
–2
0
1
… *
*
*
*
*
*
…
*
*
*
*
All 1
All 1
1
1
1
0
0
0
–8
1
0
… *
*
*
*
*
*
…
*
*
*
*
All 1
All 1
1
1
1
0
0
0
–8
:
:
:
:
1
1
… 1
0
*
*
*
*
…
*
*
*
*
All 1
All 1
1
1
1
1
1
0
–2
1
1
… 1
1
0
*
*
*
…
*
*
*
*
All 1
All 1
1
1
1
1
1
1
–1
1
1
… 1
1
1
0
*
*
…
*
*
*
*
All 0
All 0
0
0
0
0
0
0
0
1
1
… 1
1
1
1
0
*
…
*
*
*
*
All 0
All 0
0
0
0
0
0
1
+1
1
1
… 1
1
1
1
1
0
…
*
*
*
*
All 0
All 0
0
0
0
0
1
0
+2
:
:
:
1
1
… 1
1
1
1
1
1
…
1
0
*
*
All 0
All 0
0
1
1
1
0
0
+28
1
1
… 1
1
1
1
1
1
…
1
1
0
*
All 0
All 0
0
1
1
1
0
1
+29
1
1
… 1
1
1
1
1
1
…
1
1
1
0
All 0
All 0
0
1
1
1
1
0
+30
1
1
… 1
1
1
1
1
1
…
1
1
1
1
All 0
All 0
0
1
1
1
1
1
+31
Note:
*
means don’t care.
Rev. 3.00 Jan. 18, 2008 Page 143 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Table 3.29 Variation of PDMSB Operation
Mnemonic
Function
PDMSB
MSB detection
Source
Source 2
Destination
Sx

Dz

Sy
Dz
The N bit always indicates the same state as the DC bit set in negative value mode by the CS[2:0]
bits. See the negative value mode part above. The Z bit always indicates the same state as the DC
bit set in zero value mode by the CS[2:0] bits. See the zero value mode part above. The V bit is
always cleared. The GT bit always indicates the same state as the DC bit set in signed greater than
mode by the CS[2:0] bits. See the signed greater than mode part above.
3.5.10
Rounding Operation
The DSP unit provides the function that rounds from 32 bits to 16 bits. In case of providing guardbit parts, it rounds from 40 bits to 24 bits. When a round instruction is executed, H'00008000 is
added to the source operand data and then, the lower word is cleared. Figure 3.20 shows the
rounding operation flow and figure 3.21 shows the operation definition. Table 3.30 shows the
variation of this type of operation. The correspondence between each operand and registers is the
same as ALU fixed-point operations as shown in table 3.21.
As shown in figure 3.21, the rounding operation uses full-size data for both source and destination
operands. These operations are executed in the DSP stage as shown in figure 3.10. The DSP stage
is the same stage as the MA stage in which memory access is performed.
The rounding operation is always executed unconditionally, so that the DC, N, Z, V, and GT bits
in DSR are always updated in accordance with the operation result. The definition of the DC bit is
selected by the CS0 to CS2 (condition selection) bits in DSR. The result of these condition code
bits is the same as the ALU-fixed point arithmetic operations.
Rev. 3.00 Jan. 18, 2008 Page 144 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
39
Guard
31
0
Source 1 or 2
H'00008000
ALU
GT
Z
N
V DC
DSR
Guard
39
Cleared to 0
31
0
Figure 3.20 Rounding Operation Flow
Rounded result
H'00 0002
H'00 0001
Analog value
True value
H'00 0001 8000
H'00 0002 0000
H'00 0002 8000
0
Figure 3.21 Definition of Rounding Operation
Table 3.30 Variation of Rounding Operation
Mnemonic
Function
Source 1
Source 2
Destination
PRND
Rounding
Sx

Dz

Sy
Dz
• Overflow Protection
The S bit in SR is effective for any rounding operations in the DSP unit. See section 3.5.11,
Overflow Protection, for details.
Rev. 3.00 Jan. 18, 2008 Page 145 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.5.11
Overflow Protection
The S bit in SR is effective for any arithmetic operations executed in the DSP unit, including the
SH’s standard multiply and MAC operations. The S bit in SR is used as the overflow protection
enable bit. The arithmetic operation overflows when the operation result exceeds the range of
two’s complement representation without guard-bit parts. Table 3.31 shows the definition of
overflow protection for fixed-point arithmetic operations, including fixed-point signed by signed
multiplication described in section 3.5.7, Fixed-Point Multiply Operation. Table 3.32 shows the
definition of overflow protection for integer arithmetic operations. The lower word of the
saturation value of the integer arithmetic operation is don’t care. Lower word value cannot be
guaranteed.
When the overflow protection is effective, overflow never occurs. So, the V bit is cleared, and the
DC bit is also cleared when the overflow mode is selected by the CS[2:0] bits.
Table 3.31 Definition of Overflow Protection for Fixed-Point Arithmetic Operations
Sign
Overflow Condition
–31
Fixed Value
–31
Hex Representation
Positive
Result > 1 – 2
1–2
H'00 7FFF FFFF
Negative
Result < –1
–1
H'FF 8000 0000
Table 3.32 Definition of Overflow Protection for Integer Arithmetic Operations
Sign
Overflow Condition
15
Positive
Result > 2 – 1
15
Negative
Note:
*
Result < –2
means don’t care.
Rev. 3.00 Jan. 18, 2008 Page 146 of 1458
REJ09B0033-0300
Fixed Value
15
Hex Representation
2 –1
00 7FFF ****
15
FF 8000 ****
–2
Section 3 DSP Operating Unit
3.5.12
Local Data Move Instruction
The DSP unit of this LSI provides additional two independent registers, MACL and MACH, in
order to support CPU standard multiply/MAC operations. They can be also used as temporary
storage registers by local data move instructions between MACH/L and other DSP registers.
Figure 3.22 shows the flow of seven local data move instructions. Table 3.33 shows the variation
of this type of instruction.
MACH
MACL
PSTS
X0
Y0
M0
A0
PLDS
X1
Y1
M1
A1
A0G A1G
DSR
Cannot be used
Figure 3.22 Local Data Move Instruction Flow
Table 3.33 Variation of Local Data Move Operations
Mnemonic
Function
Operand
PLDS
Data move from DSP register to MACL/MACH
Dz
PSTS
Data move from MACL/MACH to DSP register
Dz
This instruction is very similar to other transfer instructions. If either the A0 or A1 register is
specified as the destination operand of PSTS, the signed bit is sign-extended and copied into the
corresponding guard-bit parts, A0G or A1G. The DC bit in DSR and other condition code bits are
not updated regardless of the instruction result. This instruction can operate as a conditional. This
instruction can operate with MOVX and MOVY in parallel.
Rev. 3.00 Jan. 18, 2008 Page 147 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.5.13
Operand Conflict
When an identical destination operand is specified with multiple parallel instructions, data conflict
occurs. Table 3.34 shows the correspondence between each operand and registers.
Table 3.34 Correspondence between Operands and Registers
X-Memory
Load
Ax
Ix
Dx
Y-Memory
Load
Ay
Iy
Dy
6-Instruction
ALU
Sx
Sy
1
DSP
A0
Registers A1
Du
3-Instruction
Multiply
Se
Sf
2
*
*
*1
*2
*1
*1
*1
M0
2
1
X0
*
*
X1
*2
*1
2
*
1
*
1
*
*1
1
*
*
Y1
*2
*1
Sx
*
2
*
1
*1
*2
*1
*1
*1
2
Y0
Dg
*1
*1
M1
3-Instruction
ALU
2
*
1
*
1
Sy
Dz
*1
*1
*1
*1
1
*
*2
*1
*2
1
2
*
*
*
*1
*1
*2
Notes: 1. Registers available for operands
2. Registers available for operands (when there is operand conflict)
There are three cases of operand conflict problems.
• When ALU operation and multiply instructions specify the same destination operand (Du and
Dg)
• When X-memory load and ALU operation specify the same destination operand (Dx and Du,
or Dz)
• When Y-memory load and ALU operation specify the same destination operand (Dy and Du,
or Dz)
In these cases above, the result is not guaranteed.
Rev. 3.00 Jan. 18, 2008 Page 148 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.6
DSP Extended Function Instruction Set
3.6.1
CPU Extended Instructions
Table 3.35 DSP Mode Extended System Control Instructions
Instruction
Instruction Code
Operation
Execution States
T Bit
SETRC #imm
10000010iiiiiiii
imm → RC (of SR)
1
–
SETRC Rn
0100nnnn00010100
Rn[11:0] → RC(of SR)
1
–
LDRS @(disp,PC)
10001100dddddddd
(disp x 2 + PC) → RS
1
–
LDRE @(disp,PC)
10001110dddddddd
(disp x 2 + PC) → RE
1
–
STC MOD,Rn
0000nnnn01010010
MOD →Rn
1
–
STC RS,Rn
0000nnnn01100010
RS → Rn
1
–
STC RE,Rn
0000nnnn01110010
RE → Rn
1
–
STS DSR,Rn
0000nnnn01101010
DSR → Rn
1
–
STS A0,Rn
0000nnnn01111010
A0 → Rn
1
–
STS X0,Rn
0000nnnn10001010
X0 → Rn
1
–
STS X1,Rn
0000nnnn10011010
X1 → Rn
1
–
STS Y0,Rn
0000nnnn10101010
Y0 → Rn
1
–
STS Y1,Rn
0000nnnn10111010
Y1 → Rn
1
–
STS.L DSR,@-Rn
0100nnnn01100010
Rn-4 → Rn, DSR → (Rn)
1
–
STS.L A0,@-Rn
0100nnnn01110010
Rn-4 → Rn, A0 → (Rn)
1
–
STS.L X0,@-Rn
0100nnnn10000010
Rn-4 → Rn, X0 → (Rn)
1
–
STS.L X1,@-Rn
0100nnnn10010010
Rn-4 → Rn, X1 → (Rn)
1
–
STS.L Y0,@-Rn
0100nnnn10100010
Rn-4 → Rn, Y0 → (Rn)
1
–
STS.L Y1,@-Rn
0100nnnn10110010
Rn-4 → Rn, Y1 →(Rn)
1
–
STC.L MOD,@-Rn
0100nnnn01010011
Rn-4 → Rn, MOD → (Rn)
1
–
STC.L RS,@-Rn
0100nnnn01100011
Rn-4 → Rn, RS → (Rn)
1
–
STC.L RE,@-Rn
0100nnnn01110011
Rn-4 → Rn, RE → (Rn)
1
–
LDS.L @Rn + ,DSR
0100nnnn01100110
(Rn) → DSR, Rn + 4→Rn
1
–
LDS.L @Rn + ,A0
0100nnnn01110110
(Rn) → A0, Rn + 4 → Rn
1
–
LDS.L @Rn + ,X0
0100nnnn10000110
(Rn) → X0, Rn + 4 → Rn
1
–
LDS.L @Rn + ,X1
0100nnnn10010110
(Rn) → X1, Rn + 4 → Rn
1
–
LDS.L @Rn + ,Y0
0100nnnn10100110
(Rn) → Y0, Rn + 4 → Rn
1
–
Rev. 3.00 Jan. 18, 2008 Page 149 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Instruction
Instruction Code
Operation
Execution States T Bit
LDS.L @Rn + ,Y1
0100nnnn10110110
(Rn) → Y1, Rn + 4 → Rn
1
–
LDC.L @Rn + ,MOD
0100nnnn01010111
(Rn) → MOD, Rn + 4 → Rn 4
–
LDC.L @Rn + ,RS
0100nnnn01100111
(Rn) → RS, Rn + 4 → Rn
4
–
LDC.L @Rn + ,RE
0100nnnn01110111
(Rn) → RE, Rn + 4 → Rn
4
–
LDS Rn,DSR
0100nnnn01101010
Rn → DSR
1
–
LDS Rn,A0
0100nnnn01111010
Rn → A0
1
–
LDS Rn,X0
0100nnnn10001010
Rn → X0
1
–
LDS Rn,X1
0100nnnn10011010
Rn → X1
1
–
LDS Rn,Y0
0100nnnn10101010
Rn → Y0
1
–
LDS Rn,Y1
0100nnnn10111010
Rn → Y1
1
–
LDC Rn,MOD
0100nnnn01011110
Rn → MOD
4
–
LDC Rn,RS
0100nnnn01101110
Rn → RS
4
–
LDC Rn,RE
0100nnnn01111110
Rn → RE
4
–
Rev. 3.00 Jan. 18, 2008 Page 150 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.6.2
Double-Data Transfer Instructions
Table 3.36 Double Data Transfer Instruction
Instruction Code
X
memory
NOPX
1111000*0*0*00** X memory no access
1
–
MOVX.W @Ax,Dx
111100A*D*0*01** (Ax) → MSW of Dx, 0 →
1
–
111100A*D*0*10** (Ax) → MSW of Dx, 0 →
1
–
111100A*D*0*11** (Ax) → MSW of Dx, 0 →
1
–
MOVX.W Da,@Ax
111100A*D*1*01** MSW of Da → (Ax)
1
–
MOVX.W Da,@Ax+
111100A*D*1*10** MSW of Da → (Ax), Ax + 2
1
–
111100A*D*1*11** MSW of Da → (Ax), Ax + Ix
1
–
NOPY
111100*0*0*0**00 Y memory no access
1
–
MOVY.W @Ay,Dy
111100*A*D*0**01 (Ay) → MSW of Dy, 0 →
1
–
111100*A*D*0**10 (Ay) → MSW of Dy, 0 →
1
–
111100*A*D*0**11 (Ay) → MSW of Dy, 0 →
1
–
MOVY.W Da,@Ay
111100*A*D*1**01 MSW of Da → (Ay)
1
–
MOVY.W Da,@Ay+
111100*A*D*1**10 MSW of Da → (Ay), Ay + 2
1
–
111100*A*D*1**11 MSW of Da → (Ay), Ay + Iy
1
–
data
transfer
Operation
Execution
States
DC
Instruction
LSW of Dx
MOVX.W @Ax+,Dx
LSW of Dx, Ax + 2 → Ax
MOVX.W @Ax+Ix,Dx
LSW of Dx, Ax + Ix → Ax
→ Ax
MOVX.W Da,@Ax+Ix
→ Ax
Y
memory
data
transfer
LSW of Dy
MOVY.W @Ay+,Dy
LSW of Dy, Ay + 2 → Ay
MOVY.W @Ay+Iy,Dy
LSW of Dy, Ay + Iy → Ay
→ Ay
MOVY.W Da,@Ay+Iy
→ Ay
Rev. 3.00 Jan. 18, 2008 Page 151 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.6.3
Single-Data Transfer Instructions
Table 3.37 Single Data Transfer Instructions
Execution
States
DC
Instruction
Instruction Code
Operation
MOVS.W @-As,Ds
111101AADDDD0000
As-2 → As, (As) → MSW of
Ds, 0 → LSW of Ds
1
–
MOVS.W @As,Ds
111101AADDDD0100
(As) → MSW of Ds, 0
→ LSW of Ds
1
–
MOVS.W @As+,Ds
111101AADDDD1000
(As) → MSW of Ds, 0
→ LSW of Ds, As + 2 → As
1
–
MOVS.W @As+Ix,Ds
111101AADDDD1100
(Asc) → MSW of Ds, 0
1
→ LSW of Ds, As + Ix → As
–
MOVS.W Ds,@-As
111101AADDDD0001
As-2 → As, MSW of Ds
→ (As)
1
–
*
MOVS.W Ds,@As
111101AADDDD0101
MSW of Ds → (As)
1
–
*
MOVS.W Ds,@As+
111101AADDDD1001
MSW of Ds → (As), As + 2
→ As
1
–
*
MOVS.W Ds,@As+Ix
111101AADDDD1101
MSW of Ds → (As), As + Ix
→ As
1
–
*
MOVS.L @-As,Ds
111101AADDDD0010
As-4 → As, (As) → Ds
1
–
MOVS.L @As,Ds
111101AADDDD0110
(As) → Ds
1
–
MOVS.L @As+,Ds
111101AADDDD1010
(As) → Ds, As + 4 → As
1
–
MOVS.L @As+Ix,Ds
111101AADDDD1110
(As) → Ds, As + Ix → As
1
–
MOVS.L Ds,@-As
111101AADDDD0011
As-4 → As, Ds → (As)
1
–
MOVS.L Ds,@As
111101AADDDD0111
Ds → (As)
1
–
MOVS.L Ds,@As+
111101AADDDD1011
Ds → (As), As + 4 → As
1
–
MOVS.L Ds,@As+Ix
111101AADDDD1111
Ds → (As), As + Ix → As
1
–
Note:
*
Category
If guard bit registers A0G and A1G are specified in source operand Ds, the data is
output to the LDB[7:0] bus and the sign bit is copied into the upper bits, [31:8].
Rev. 3.00 Jan. 18, 2008 Page 152 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
The correspondence between DSP data transfer operands and registers is shown in table 3.38.
Table 3.38 Correspondence between DSP Data Transfer Operands and Registers
Register
SH
register
Ax
Ix
Dx
Iy
Dy
Da
As
Ds
R0
R1
R2 (As2)
Yes
R3 (As3)
Yes
R4 (Ax0)
Yes
Yes
R5 (Ax1)
Yes
Yes
R6 (Ay0)
Yes
R7 (Ay1)
Yes
R8 (Ix)
Yes
R9 (Iy)
DSP
register
Ay
Yes
A0
Yes
Yes
A1
Yes
Yes
M0
Yes
M1
Yes
X0
Yes
Yes
X1
Yes
Yes
Y0
Yes
Yes
Y1
Yes
Yes
A0G
Yes
A1G
Yes
Rev. 3.00 Jan. 18, 2008 Page 153 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.6.4
DSP Operation Instructions
Table 3.39 DSP Operation Instructions
Instruction
Instruction Code Operation
Execution
States
DC
Se*Sf → Dg (Signed)
1
–
Sx + Sy → Du Se*Sf → Dg (Signed)
1
*
Sy-Sy → Du Se*Sf → Dg (Signed)
1
*
Sx + Sy → Dz
1
*
111110**********
If DC = 1, Sx + Sy → Dz
1
–
10110010xxyyzzzz
If DC = 0, nop
1
–
PMULS Se,Sf, Dg 111110**********
0100eeff0000gg00
PADD Sx,Sy,Du
111110**********
PMULS Se,Sf,Dg 0111eeffxxyygguu
PSUB Sx,Sy,Du
111110**********
PMULS Se,Sf,Dg 0110eeffxxyygguu
PADD Sx,Sy,Dz
111110**********
10110001xxyyzzzz
DCT PADD Sx,Sy,Dz
DCF PADD Sx,Sy,Dz
PSUB Sx,Sy,Dz
111110**********
If DC = 0, Sx + Sy → Dz
10110011xxyyzzzz
If DC = 1, nop
111110**********
Sx-Sy → Dz
1
*
1
–
1
–
1
*
1
–
1
–
1
*
10100001xxyyzzzz
DCT PSUB Sx,Sy,Dz
DCF PSUB Sx,Sy,Dz
PSHA Sx,Sy,Dz
DCT PSHA Sx,Sy,Dz
111110**********
If DC = 1, Sx-Sy → Dz
10100010xxyyzzzz
If DC = 0, nop
111110**********
If DC = 0, Sx-Sy → Dz
10100011xxyyzzzz
If DC = 1, nop
111110**********
If Sy >= 0, Sx<<Sy → Dz (arithmetic shift)
10010001xxyyzzzz
If Sy < 0, Sx>>Sy → Dz
111110**********
If DC = 1 & Sy >= 0, Sx<<Sy → Dz
(arithmetic shift)
10010010xxyyzzzz
If DC=1 & Sy<0, Sx>>Sy → Dz If DC=0, nop
DCF PSHA Sx,Sy,Dz
111110**********
10010011xxyyzzzz
If DC = 0 & Sy >= 0, Sx<<Sy → Dz
(arithmetic shift)
If DC = 0 & Sy < 0, Sx>>Sy → Dz
If DC = 1, nop
PSHL Sx,Sy,Dz
111110**********
If Sy >= 0, Sx<<Sy → Dz (logical shift)
10000001xxyyzzzz
If Sy < 0, Sx>>Sy → Dz
Rev. 3.00 Jan. 18, 2008 Page 154 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Instruction
Instruction Code Operation
DCT PSHL Sx,Sy,Dz
111110**********
10000010xxyyzzzz
Execution
States
DC
If DC = 1 & Sy >= 0, Sx<<Sy → Dz
(logical shift)
1
–
1
–
Sx →Dz
1
*
Sy →Dz
1
*
If DC = 1, Sx → Dz If DC = 0, nop
1
–
If DC = 1, Sy → Dz If DC = 0, nop
1
–
If DC = 0, Sx → Dz If DC = 1, nop
1
–
If DC = 0, Sy → Dz If DC = 1, nop
1
–
Sx → Dz normalization count shift value
1
*
Sy → Dz normalization count shift value
1
*
If DC = 1, normalization count shift value Sx
→ Dz
1
–
1
–
1
–
If DC = 1 & Sy < 0, Sx>>Sy → Dz
If DC = 0, nop
DCF PSHL Sx,Sy,Dz
111110**********
10000011xxyyzzzz
If DC = 0 & Sy >= 0, Sx<<Sy → Dz (logical
shift)
If DC = 0 & Sy < 0, Sx>>Sy → Dz
If DC = 1, nop
PCOPY Sx,Dz
111110**********
11011001xx00zzzz
PCOPY Sy,Dz
111110**********
1111100100yyzzzz
DCT PCOPY Sx,Dz
111110**********
11011010xx00zzzz
DCT PCOPY Sy,Dz
111110**********
1111101000yyzzzz
DCF PCOPY Sx,Dz
111110**********
11011011xx00zzzz
DCF PCOPY Sy,Dz
111110**********
1111101100yyzzzz
PDMSB Sx,Dz
111110**********
10011101xx00zzzz
PDMSB Sy,Dz
111110**********
1011110100yyzzzz
DCT PDMSB Sx,Dz
111110**********
10011110xx00zzzz
If DC = 0, nop
DCT PDMSB Sy,Dz
111110**********
1011111000yyzzzz
If DC = 1, normalization count shift value Sy
→ Dz
If DC = 0, nop
DCF PDMSB Sx,Dz
111110**********
10011111xx00zzzz
If DC = 0, normalization count shift value Sx
→ Dz
If DC = 1, nop
Rev. 3.00 Jan. 18, 2008 Page 155 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Instruction
Instruction Code Operation
DCF PDMSB Sy,Dz
111110**********
1011111100yyzzzz
Execution
States
DC
If DC = 0, normalization count shift value 1
Sy → Dz
–
If DC=1, nop
PINC Sx,Dz
111110**********
MSW of Sx + 1 → Dz
1
*
MSW of Sy + 1 → Dz
1
*
If DC = 1, MSW of Sx + 1 → Dz
1
–
1
–
1
–
1
–
0-Sx → Dz
1
*
0-Sy → Dz
1
*
If DC = 1, 0-Sx → Dz
1
–
1
–
1
–
1
–
Sx | Sy → Dz
1
*
1
–
1
–
10011001xx00zzzz
PINC Sy,Dz
111110**********
1011100100yyzzzz
DCT PINC Sx,Dz
111110**********
10011010xx00zzzz If DC = 0, nop
DCT PINC Sy,Dz
111110**********
If DC = 1, MSW of Sy + 1 → Dz
1011101000yyzzzz If DC = 0, nop
DCF PINC Sx,Dz
111110**********
If DC = 0, MSW of Sx + 1 → Dz
10011011xx00zzzz If DC = 1, nop
DCF PINC Sy,Dz
111110**********
If DC = 0, MSW of Sy + 1 → Dz
1011101100yyzzzz If DC = 1, nop
PNEG Sx,Dz
111110**********
11001001xx00zzzz
PNEG Sy,Dz
111110**********
1110100100yyzzzz
DCT PNEG Sx,Dz
111110**********
11001010xx00zzzz If DC = 0, nop
DCT PNEG Sy,Dz
111110**********
If DC = 1, 0-Sy → Dz
1110101000yyzzzz If DC = 0, nop
DCF PNEG Sx,Dz
111110**********
If DC = 0, 0-Sx → Dz
11001011xx00zzzz If DC = 1, nop
DCF PNEG Sy,Dz
111110**********
If DC = 0, 0-Sy → Dz
1110101100yyzzzz If DC = 1, nop
POR Sx,Sy,Dz
111110**********
10110101xxyyzzzz
DCT POR Sx,Sy,Dz
DCF POR Sx,Sy,Dz
111110**********
If DC = 1, Sx | Sy → Dz
10110110xxyyzzzz
If DC = 0, nop
111110**********
If DC = 0, Sx | Sy → Dz
10110111xxyyzzzz
If DC = 1, nop
Rev. 3.00 Jan. 18, 2008 Page 156 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Instruction
PAND Sx,Sy,Dz
Execution
States
DC
Instruction Code Operation
111110**********
Sx & Sy → Dz
1
*
1
–
1
–
10010101xxyyzzzz
DCT PAND Sx,Sy,Dz
DCF PAND Sx,Sy,Dz
PXOR Sx,Sy,Dz
111110**********
If DC = 1, Sx & Sy → Dz
10010110xxyyzzzz
If DC = 0, nop
111110**********
If DC = 0, Sx & Sy → Dz
10010111xxyyzzzz
If DC = 1, nop
111110**********
Sx ^ Sy → Dz
1
*
111110**********
If DC = 1, Sx ^ Sy → Dz
1
–
10100110xxyyzzzz
If DC = 0, nop
111110**********
If DC = 0, Sx ^ Sy → Dz
1
–
10100101xxyyzzzz
DCT PXOR Sx,Sy,Dz
DCF PXOR Sx,Sy,Dz
PDEC Sx,Dz
10100111xxyyzzzz
If DC = 1, nop
111110**********
Sx [39:16]-1 → Dz
1
*
If DC = 1, Sx [39:16]-1 → Dz
1
–
1
–
Sy [31:16]-1 → Dz
1
*
If DC = 1, Sy [31:16]-1 → Dz
1
–
1
–
h'00000000 → Dz
1
*
If DC = 1, h'00000000 → Dz
1
–
1
–
1
*
10001001xx00zzzz
DCT PDEC Sx,Dz
111110**********
10001010xx00zzzz If DC = 0, nop
DCF PDEC Sx,Dz
111110**********
If DC = 0, Sx [39:16]-1 → Dz
10001011xx00zzzz If DC = 1, nop
PDEC Sy,Dz
111110**********
1010100100yyzzzz
DCT PDEC Sy,Dz
111110**********
1010101000yyzzzz If DC = 0, nop
DCF PDEC Sy,Dz
111110**********
If DC = 0, Sy [31:16]-1 → Dz
1010101100yyzzzz If DC = 1, nop
PCLR Dz
111110**********
100011010000zzzz
DCT PCLR Dz
111110**********
100011100000zzzz If DC = 0, nop
DCF PCLR Dz
111110**********
If DC = 0, h'00000000 → Dz
100011110000zzzz If DC = 1, nop
PSHA #imm,Dz
111110**********
00010iiiiiiizzzz
If imm>=0, Dz<<imm → Dz (arithmetic
shift)
If imm<0, Dz>>imm → Dz
Rev. 3.00 Jan. 18, 2008 Page 157 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Instruction
PSHL #imm,Dz
PSTS MACH,Dz
Instruction Code Operation
111110**********
If imm>=0, Dz<<imm → Dz (logical shift)
00000iiiiiiizzzz
If imm<0, Dz>>imm → Dz
111110**********
Execution
States
DC
1
*
MACH → Dz
1
–
If DC = 1, MACH → Dz
1
–
If DC = 0, MACH → Dz
1
–
MACL → Dz
1
–
If DC = 1, MACL → Dz
1
–
If DC = 0, MACL → Dz
1
–
Dz → MACH
1
–
If DC = 1, Dz → MACH
1
–
If DC = 0, Dz → MACH
1
–
Dz → MACL
1
–
If DC = 1, Dz → MACL
1
–
If DC = 0, Dz → MACL
1
–
Sx + Sy + DC →Dz Carry → DC
1
Carry
Sx-Sy-DC → Dz Borrow → DC
1
Borrow
Sx-Sy → DC update
1
*
110011010000zzzz
DCT PSTS MACH,Dz
111110**********
110011100000zzzz
DCF PSTS MACH,Dz
111110**********
110011110000zzzz
PSTS MACL,Dz
111110**********
110111010000zzzz
DCT PSTS MACL,Dz
111110**********
110111100000zzzz
DCF PSTS MACL,Dz
111110**********
PLDS Dz,MACH
111110**********
110111110000zzzz
111011010000zzzz
DCT PLDS Dz,MACH
111110**********
111011100000zzzz
DCF PLDS Dz,MACH
111110**********
111011110000zzzz
PLDS Dz,MACL
111110**********
111111010000zzzz
DCT PLDS Dz,MACL
111110**********
111111100000zzzz
DCF PLDS Dz,MACL
111110**********
111111110000zzzz
PADDC Sx,Sy,Dz 111110**********
10110000xxyyzzzz
PSUBC Sx,Sy,
Dz
PCMP Sx,Sy
111110**********
10100000xxyyzzzz
111110**********
10000100xxyy0000
Rev. 3.00 Jan. 18, 2008 Page 158 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Instruction
PABS Sx,Dz
Execution
States
DC
Instruction Code Operation
111110**********
If Sx<0, 0-Sx → Dz If Sx>=0, Sx→ Dz
1
*
If Sy<0, 0-Sy → Dz If Sy>=0, Sy → Dz
1
*
Sx + h'00008000 → Dz
LSW of Dz → h'0000
1
*
Sy + h'00008000 → Dz
LSW of Dz → h'0000
1
*
10001000xx00zzzz
PABS Sy,Dz
111110**********
1010100000yyzzzz
PRND Sx,Dz
111110**********
10011000xx00zzzz
PRND Sy,Dz
111110**********
1011100000yyzzzz
Note:
*
See table 3.19.
Rev. 3.00 Jan. 18, 2008 Page 159 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
3.6.5
Operation Code Map in DSP Mode
Table 3.40 shows the operation code map including an instruction codes extended in the DSP
mode.
Table 3.40 Operation Code Map
Instruction Code
MSB
Fx: 0000
LSB MD: 00
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MD: 01
MD: 10
MD: 11
0000 Rn
Fx
0000
0000 Rn
Fx
0001
0000 Rn
00MD 0010 STC
SR, Rn
STC
GBR, Rn
STC
VBR, Rn
STC
SSR, Rn
0000 Rn
01MD 0010 STC
SPC, Rn
STC
MOD, Rn
STC
RS, Rn
STC
RE, Rn
0000 Rn
10MD 0010 STC
R0_BANK, Rn
STC
R1_BANK, Rn STC
R2_BANK, Rn STC
R3_BANK, Rn
0000 Rn
11MD 0010 STC
R4_BANK, Rn
STC
R5_BANK, Rn STC
R6_BANK, Rn STC
R7_BANK, Rn
0000 Rm
00MD 0011 BSRF Rm
0000 Rm
10MD 0011 PREF @Rm
0000 Rn
Rm
BRAF
01MD MOV.B Rm, @(R0, Rn) MOV.W
0000 0000 00MD 1000 CLRT
SETT
0000 0000 01MD 1000 CLRS
SETS
Rm
Rm, @(R0, Rn) MOV.L Rm,@(R0, Rn) MUL.L Rm, Rn
CLRMAC
LDTLB
0000 0000 10MD 1000
0000 0000 11MD 1000
0000 0000 Fx
1001 NOP
0000 0000 Fx
1010
0000 0000 Fx
1011 RTS
0000 Rn
Fx
1000
0000 Rn
Fx
1001
0000 Rn
00MD 1010 STS
0000 Rn
01MD 1010
0000 Rn
10MD 1010 STS
0000 Rn
Fx
DIV0U
SLEEP
MACH, Rn
X0, Rn
1011
Rev. 3.00 Jan. 18, 2008 Page 160 of 1458
REJ09B0033-0300
STS
STS
RTE
MACL, Rn
X1, Rn
MOVT
Rn
STS
PR, Rn
STS
DSR, Rn
STS
A0, Rn
STS
Y0, Rn
STS
Y1, Rn
Section 3 DSP Operating Unit
Instruction Code
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MSB
MD: 00
MD: 01
MD: 10
MD: 11
MOV.W
MOV.L
MAC.L
@(R0, Rm), Rn
@(R0, Rm), Rn
@Rm+,@Rn+
0000
LSB
Rn
Rm
11MD MOV. B
@(R0, Rm), Rn
0001
Rn
Rm
disp
MOV.L
Rm, @(disp:4, Rn)
0010
Rn
Rm
00MD MOV.B
Rm, @Rn
MOV.W
Rm, @Rn
MOV.L
Rm, @Rn
0010
Rn
Rm
01MD MOV.B
Rm, @−Rn
MOV.W
Rm, @−Rn
MOV.L
Rm, @−Rn DIV0S
Rm, Rn
0010
Rn
Rm
10MD TST
Rm, Rn
AND
Rm, Rn
XOR
Rm, Rn
OR
Rm, Rn
0010
Rn
Rm
11MD CMP/STR Rm, Rn
XTRCT
Rm, Rn
MULU.W
Rm, Rn
MULSW Rm, Rn
0011
Rn
Rm
00MD CMP/EQ Rm, Rn
CMP/HS
Rm, Rn
CMP/GE Rm, Rn
0011
Rn
Rm
01MD DIV1
Rm, Rn
CMP/HI
Rm, Rn
CMP/GT Rm, Rn
0011
Rn
Rm
10MD SUB
Rm, Rn
SUBC
Rm, Rn
SUBV
Rm, Rn
0011
Rn
Rm
11MD ADD
Rm, Rn
DMULS.L Rm,Rn
ADDC
Rm, Rn
ADDV
Rm, Rn
0100
Rn
Fx
0000
SHLL
Rn
DT
Rn
SHAL
Rn
0100
Rn
Fx
0001
SHLR
Rn
CMP/PZ Rn
SHAR
Rn
0100
Rn
Fx
0010
DMULU.L Rm,Rn
STS.L
STS.L
STS.L
MACH, @−Rn
MACL, @−Rn
PR, @−Rn
0100
Rn
00MD 0011
STC.L
SR, @−Rn
STC.L
GBR, @−Rn
STC.L VBR,
@−Rn
STC.L
SSR, @−Rn
0100
Rn
01MD 0011
STC.L
SPC, @−Rn
STC.L
MOD, @−Rn
STC.L RS,
@−Rn
STC.L
RE, @−Rn
0100
Rn
10MD 0011
STC.L
STC.L
STC.L
STC.L
R0_BANK, @−Rn
R1_BANK, @−Rn
R2_BANK, @−Rn
R3_BANK, @−Rn
STC.L
STC.L
STC.L
STC.L
R4_BANK, @−Rn
R5_BANK, @−Rn
R6_BANK, @−Rn
R7_BANK, @−Rn
0100
Rn
11MD 0011
0100
Rn
Fx
0100
ROTL
Rn
SETRC
Rn
ROTCL
Rn
0100
Rn
Fx
0101
ROTR
Rn
CMP/PL
Rn
ROTCR
Rn
0100
Rm
00MD 0110
0100
0100
Rm
Rm
LDS.L
LDS.L
LDS.L
@Rm+, MACH
@Rm+, MACL
@Rm+, PR
01MD 0110
10MD 0110
LDS.L
@Rm+, X0
LDS.L
@Rm+, X1
LDS.L
LDS.L
@Rm+, DSR
@Rm+, A0
LDS.L
@Rm+, Y0 LDS.L
@Rm+, Y1
Rev. 3.00 Jan. 18, 2008 Page 161 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Instruction Code
MSB
LSB
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MD: 00
MD: 01
MD: 10
MD: 11
0100 Rm
00MD 0111
LDC.L
@Rm+, SR
LDC.L
@Rm+, GBR
LDC.L
@Rm+, VBR
LDC.L
@Rm+, SSR
0100 Rm
01MD 0111
LDC.L
@Rm+, SPC
LDC.L
@Rm+, MOD
LDC.L
@Rm+, RS
LDC.L
@Rm+, RE
0100 Rm
10MD 0111
0100 Rm
11MD 0111
LDC.L
LDC.L
LDC.L
LDC.L
@Rm+, R0_BANK
@Rm+, R1_BANK
@Rm+, R2_BANK
@Rm+, R3_BANK
LDC.L
LDC.L
LDC.L
LDC.L
@Rm+, R4_BANK
@Rm+, R5_BANK
@Rm+, R6_BANK
@Rm+, R7_BANK
0100 Rn
Fx
1000
SHLL2
Rn
SHLL8
Rn
SHLL16
0100 Rn
Fx
1001
SHLR2 Rn
SHLR8
Rn
SHLR16 Rn
0100 Rm
00MD 1010
LDS
LDS
Rm, MACL
LDS
Rm, PR
0100 Rm
01MD 1010
LDS
Rm, DSR
LDS
Rm, A0
0100 Rm
10MD 1010
LDS
Rm, Y1
Rm, MACH
Rn
LDS
Rm, X0
LDS
Rm, X1
LDS
Rm, Y0
@Rm
TAS.B
@Rn
JMP
@Rm
0100 Rm/Rn Fx
1011
JSR
0100 Rn
Rm
1100
SHAD
Rm, Rn
0100 Rn
Rm
1101
SHLD
Rm, Rn
0100 Rm
00MD 1110
LDC
Rm, SR
LDC
Rm, GBR
LDC
Rm, VBR
LDC
Rm, SSR
0100 Rm
01MD 1110
LDC
Rm, SPC
LDC
Rm, MOD
LDC
Rm, RS
LDC
Rm, RE
0100 Rm
10MD 1110
0100 Rm
11MD 1110
LDC
LDC
LDC
LDC
Rm, R0_BANK
Rm, R1_BANK
Rm, R2_BANK
Rm, R3_BANK
LDC
LDC
LDC
LDC
Rm, R4_BANK
Rm, R5_BANK
Rm, R6_BANK
Rm, R7_BANK
MOV.L
@Rm, Rn
MOV
Rm, Rn
@Rm+, Rn
NOT
Rm, Rn
Rm, Rn
0100 Rn
Rm
1111
MAC.W @Rm+, @Rn+
0101 Rn
Rm
disp
MOV.L
0110 Rn
Rm
00MD MOV.B @Rm, Rn
MOV.W
@Rm, Rn
0110 Rn
Rm
01MD MOV.B @Rm+, Rn
MOV.W
@Rm+, Rn MOV.L
0110 Rn
Rm
10MD SWAP.B Rm, Rn
SWAP.W Rm, Rn
NEGC
Rm, Rn
NEG
0110 Rn
Rm
11MD EXTU.B Rm, Rn
EXTU.W
EXTS.B
Rm, Rn
EXTS.W Rm, Rn
0111 Rn
imm
1000 00MD
Rn
imm
ADD
disp
@ (disp:4, Rm), Rn
#imm : 8, Rn
MOV.B
MOV.W
R0, @(disp: 4, Rn)
R0, @(disp: 4, Rn)
Rev. 3.00 Jan. 18, 2008 Page 162 of 1458
REJ09B0033-0300
Rm, Rn
SETRC #imm
Section 3 DSP Operating Unit
Instruction Code
Fx: 0000
Fx: 0001
Fx: 0010
Fx: 0011 to 1111
MD: 10
MD: 11
MSB
LSB MD: 00
MD: 01
1000 01MD Rm
disp
MOV.B
MOV.W
@(disp:4, Rm), R0
@(disp: 4, Rm), R0
1000 10MD imm/disp
CMP/EQ
#imm:8, R0
BT
disp: 8
1000 11MD imm/disp
LDRS
@(disp:8,PC)
BT/S
disp: 8
1001 Rn
MOV.W @ (disp : 8, PC), Rn
disp
1010 disp
BRA
disp : 12
1011 disp
BSR
disp: 12
1100 00MD imm/disp
1100 01MD disp
LDRE
@(disp:8,PC)
BF
disp: 8
BF/S
disp: 8
TRAPA
#imm: 8
MOV.B
MOV.W
MOV.L
R0, @(disp: 8, GBR)
R0, @(disp: 8, GBR)
R0, @(disp: 8, GBR)
MOV.B
MOV.W
MOV.L
MOVA
@(disp: 8, GBR), R0
@(disp: 8, GBR), R0
@(disp: 8, GBR), R0
@(disp: 8, PC), R0
AND
XOR
OR
1100 10MD imm
TST
1100 11MD imm
TST.B
AND.B
XOR.B
OR.B
#imm: 8, @(R0, GBR)
#imm: 8, @(R0, GBR)
#imm: 8, @(R0, GBR)
#imm: 8, @(R0, GBR)
#imm: 8, R0
#imm: 8, R0
#imm: 8, R0
#imm: 8, R0
1101 Rn
disp
MOV.L
@(disp: 8, PC), Rn
1110 Rn
imm
MOV
#imm:8, Rn
1111 00**
********
MOVX.W, MOVY.W
Double data transfer instruction
1111 01**
********
MOVS.W, MOVS.L
Single data transfer instruction
1111 10**
********
MOVX.W, MOVY.W
Double data transfer instruction, with DSP parallel operation instruction (32-
bit instruction )
1111 11**
********
Notes: 1. For details, refer to the SH-3/SH-3E/SH3-DSP Software Manual.
2. Instructions in the hatched areas are DSP extended instructions. These instructions
can be executed only when the DSP bit in the SR register is set to 1.
Rev. 3.00 Jan. 18, 2008 Page 163 of 1458
REJ09B0033-0300
Section 3 DSP Operating Unit
Rev. 3.00 Jan. 18, 2008 Page 164 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
Section 4 Memory Management Unit (MMU)
This LSI has an on-chip memory management unit (MMU) that supports a virtual memory system.
The on-chip translation look-aside buffer (TLB) caches information for user-created address
translation tables located in external memory. It enables high-speed translation of virtual addresses
into physical addresses. Address translation uses the paging system and supports two page sizes (1
kbyte or 4 kbytes). The access rights to virtual address space can be set for each of the privileged
and user modes to provide memory protection.
4.1
Role of MMU
The MMU is a feature designed to make efficient use of physical memory. As shown in figure 4.1,
if a process is smaller in size than the physical memory, the entire process can be mapped onto
physical memory. However, if the process increases in size to the extent that it no longer fits into
physical memory, it becomes necessary to partition the process and to map those parts requiring
execution onto memory as occasion demands (figure 4.1 (1)). Having the process itself consider
this mapping onto physical memory would impose a large burden on the process. To lighten this
burden, the idea of virtual memory was born as a means of performing en bloc mapping onto
physical memory (figure 4.1 (2)). In a virtual memory system, substantially more virtual memory
than physical memory is provided, and the process is mapped onto this virtual memory. Thus a
process only has to consider operation in virtual memory. Mapping from virtual memory to
physical memory is handled by the MMU. The MMU is normally controlled by the operating
system, switching physical memory to allow the virtual memory required by a process to be
mapped onto physical memory in a smooth fashion. Switching of physical memory is performed
via secondary storage, etc.
The virtual memory system that came into being in this way is particularly effective in a timesharing system (TSS) in which a number of processes are running simultaneously (figure 4.1 (3)).
If processes running in a TSS had to take mapping onto virtual memory into consideration while
running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this
load on the individual processes and so improve efficiency (figure 4.1 (4)). In the virtual memory
system, virtual memory is allocated to each process. The task of the MMU is to perform efficient
mapping of these virtual memory areas onto physical memory. It also has a memory protection
feature that prevents one process from inadvertently accessing another process’s physical memory.
When address translation from virtual memory to physical memory is performed using the MMU,
it may occur that the relevant translation information is not recorded in the MMU, with the result
that one process may inadvertently access the virtual memory allocated to another process. In this
case, the MMU will generate an exception, change the physical memory mapping, and record the
new address translation information.
MMUS300S_000020020300
Rev. 3.00 Jan. 18, 2008 Page 165 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
Although the functions of the MMU could also be implemented by software alone, the need for
translation to be performed by software each time a process accesses physical memory would
result in poor efficiency. For this reason, a buffer for address translation (translation look-aside
buffer: TLB) is provided in hardware to hold frequently used address translation information. The
TLB can be described as a cache for storing address translation information. Unlike cache
memory, however, if address translation fails, that is, if an exception is generated, switching of
address translation information is normally performed by software. This makes it possible for
memory management to be performed flexibly by software.
The MMU has two methods of mapping from virtual memory to physical memory: a paging
method using fixed-length address translation, and a segment method using variable-length
address translation. With the paging method, the unit of translation is a fixed-size address space
(usually of 1 to 64 kbytes) called a page.
In the following text, the address space in virtual memory is referred to as virtual address space,
and address space in physical memory as physical memory space.
Rev. 3.00 Jan. 18, 2008 Page 166 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
Virtual
memory
Process 1
Physical
memory
Process 1
MMU
Physical
memory
Physical
memory
Process 1
(2)
(1)
Process 1
Process 1
Virtual
memory
MMU
Physical
memory
Physical
memory
Process 2
Process 2
Process 3
Process 3
(3)
(4)
Figure 4.1 MMU Functions
Rev. 3.00 Jan. 18, 2008 Page 167 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
4.1.1
(1)
MMU of This LSI
Virtual Address Space
This LSI supports a 32-bit virtual address space that enables access to a 4-Gbyte address space. As
shown in figures 4.2 and 4.3, the virtual address space is divided into several areas. In privileged
mode, a 4-Gbyte space comprising areas P0 to P4 are accessible. In user mode, a 2-Gbyte space of
U0 area is accessible, and a 16-Mbyte space of Uxy area is also accessible if the DSP bit in the SR
register is set to 1. Access to any area (excluding the U0 area and Uxy area) in user mode will
result in an address error.
If the MMU is enabled by setting the AT bit in the MMUCR register to 1, P0, P3, and U0 areas
can be used as any physical address area in 1- or 4-kbyte page units. By using an 8-bit address
space identifier, P0, P2, and U0 areas can be increased to up to 256 areas. Mapping from virtual
address to 29-bit physical address can be achieved by the TLB.
(a)
P0, P3, and U0 Areas
The P0, P3, and U0 areas can be address translated by the TLB and can be accessed through the
cache. If the MMU is enabled, these areas can be mapped to any physical address space in 1- or 4kbyte page units via the TLB. If the CE bit in the cache control register (CCR1) is set to 1 and if
the corresponding cache enable bit (C bit) of the TLB entry is set to 1, access via the cache is
enabled. If the MMU is disabled, replacing the upper three bits of an address in these areas with 0s
creates the address in the corresponding physical address space. If the CE bit in the CCR1 register
is set to 1, access via the cache is enabled. When the cache is used, either the copy-back or writethrough mode is selected for write access via the WT bit in CCR1.
If these areas are mapped to the on-chip module control register area or on-chip memory area in
area 1 in the physical address space via the TLB, the C bit of the corresponding page must be
cleared to 0.
(b)
P1 Area
The P1 area can be accessed via the cache and cannot be address-translated by the TLB. Whether
the MMU is enabled or not, replacing the upper three bits of an address in these areas with 0s
creates the address in the corresponding physical address space. Use of the cache is determined by
the CE bit in the cache control register (CCR1). When the cache is used, either the copy-back or
write-through mode is selected for write access by the CB bit in the CCR1 register.
Rev. 3.00 Jan. 18, 2008 Page 168 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
(c)
P2 Area
The P2 area cannot be accessed via the cache and cannot be address-translated by the TLB.
Whether the MMU is enabled or not, replacing the upper three bits of an address in this area with
0s creates the address in the corresponding physical address space.
(d)
P4 Area
The P4 area is mapped to the on-chip I/O of this LSI. This area cannot be accessed via the cache
and cannot be address-translated by the TLB. Figure 4.4 shows the configuration of the P4 area.
H'0000 0000
256
256
External Address
Space
H'0000 0000
Area 0
Area 1
Area 2
P0 area
Cacheable
Address translation possible
Area 3
Area 4
Area 5
U0 area
Cacheable
Address translation possible
Area 6
Area 7
H'8000 0000
H'8000 0000
P1 area
Cacheable
Address translation not possible
Address error
H'A000 0000
P2 area
Non-Cacheable
Address translation not possible
H'C000 0000
P3 area
Cacheable
Address translation possible
H'A500 0000
Uxy area*
H'A5FF FFFF
Address error
H'E000 0000
P4 area
Non-Cacheable
Address translation not possible
H'FFFF FFFF
H'FFFF FFFF
Privileged mode
User mode
Note: Only exists when SR.DSP = 1
Figure 4.2 Virtual Address Space (MMUCR.AT = 1)
Rev. 3.00 Jan. 18, 2008 Page 169 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
External address space
H'0000 0000
H'0000 0000
Area 0
Area 1
Area 2
Area 3
P0 area
Cacheable
Area 4
U0 area
Cacheable
Area 5
Area 6
Area 7
H'8000 0000
H'8000 0000
P1 area
Cacheable
Address error
P2 area
Uxy area*
H'A000 0000
Non-cacheable
H'A500 0000
H'A5FF FFFF
H'C000 0000
P3 area
Cacheable
Address error
H'E000 0000
P4 area
Non-cacheable
H'FFFF FFFF
H'FFFF FFFF
Privileged mode
User mode
Note: Only exists when SR.DSP = 1
Figure 4.3 Virtual Address Space (MMUCR.AT = 0)
Rev. 3.00 Jan. 18, 2008 Page 170 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
H'E000 0000
Reserved
H'F000 0000
H'F100 0000
H'F200 0000
H'F300 0000
H'F400 0000
Cache address array
Cache data array
TLB address array
TLB data array
Reserved
H'FC00 0000
Control register area
H'FFFF FFFF
Figure 4.4 P4 Area
The area from H'F000 0000 to H'F0FF FFFF is for direct access to the cache address array. For
more information, see section 5.4, Memory-Mapped Cache.
The area from H'F100 0000 to H'F1FF FFFF is for direct access to the cache data array. For more
information, see section 5.4, Memory-Mapped Cache.
The area from H'F200 0000 to H'F2FF FFFF is for direct access to the TLB address array. For
more information, see section 4.6, Memory-Mapped TLB.
The area from H'F300 0000 to H'F3FF FFFF is for direct access to the TLB data array. For more
information, see section 4.6, Memory-Mapped TLB.
The area from H'FC00 0000 to H'FFFF FFFF is reserved for registers of the on-chip peripheral
modules. For more information, see section 37, List of Registers.
(e)
Uxy Area
The Uxy area is mapped to the on-chip memory of this LSI. This area is made usable in user mode
when the DSP bit in the SR register is set to 1. In user mode, accessing this area when the DSP bit
is 0 will result in an address error. This area cannot be accessed via the cache and cannot be
address-translated by the TLB. For more information on the Uxy area, see section 6, X/Y
Memory.
Rev. 3.00 Jan. 18, 2008 Page 171 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
(2)
Physical Address Space
This LSI supports a 29-bit physical address space. As shown in figure 4.5, the physical address
space is divided into eight areas. Area 1 is mapped to the on-chip module control register area and
on-chip memory area. Area 7 is reserved.
For details on physical address space, refer to section 9, Bus State Controller (BSC).
H'0000 0000
Area 0
H'0400 0000
H'0800 0000
Area 1
(On-chip registers and
On-chip memories)
Area 2
H'0C00 0000
Area 3
H'1000 0000
Area 4
H'1400 0000
Area 5
H'1800 0000
Area 6
H'1C00 0000
Area 7
(Reserved)
H'1FFF FFFF
Figure 4.5 Physical Address Space
(3)
Address Transition
When the MMU is enabled, the virtual address space is divided into units called pages. Physical
addresses are translated in page units. Address translation tables in external memory hold
information such as the physical address that corresponds to the virtual address and memory
protection codes. When an access to area P1 or P2 occurs, there is no TLB access and the physical
address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB is searched
by virtual address and, if that virtual address is registered in the TLB, the access hits the TLB. The
corresponding physical address and the page control information are read from the TLB and the
physical address is determined.
If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing
will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in
external memory is searched and the corresponding physical address and the page control
Rev. 3.00 Jan. 18, 2008 Page 172 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
information are registered in the TLB. After returning from the handler, the instruction that caused
the TLB miss is re-executed. When the MMU is enabled, address translation information that
results in a physical address space of H'2000 0000 to H'FFFF FFFF should not be registered in the
TLB.
When the MMU is disabled, masking the upper three bits of the virtual address to 0s creates the
address in the corresponding physical address space. Since this LSI supports 29-bit address space
as physical address space, the upper three bits of the virtual address are ignored as shadow areas.
For details, refer to section 9, Bus State Controller (BSC). For example, address H'0000 1000 in
the P0 area, address H'8000 1000 in the P1 area, address H'A000 1000 in the P2 area, and address
H'C000 1000 in the P3 area are all mapped to the same physical memory. If these addresses are
accessed while the cache is enabled, the upper three bits are always cleared to 0 to guarantee the
continuity of addresses stored in the address array of the cache.
(4)
Single Virtual Memory Mode and Multiple Virtual Memory Mode
There are two virtual memory modes: single virtual memory mode and multiple virtual memory
mode. In single virtual memory mode, multiple processes run in parallel using the virtual address
space exclusively and the physical address corresponding to a given virtual address is specified
uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the virtual
address space, so a given virtual address may be translated into different physical addresses
depending on the process. By the value set to the MMU control register (MMUCR), either single
or multiple virtual mode is selected.
In terms of operation, the only difference between single virtual memory mode and multiple
virtual memory mode is in the TLB address comparison method (see section 4.3.3, TLB Address
Comparison).
(5)
Address Space Identifier (ASID)
In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate
between processes running in parallel and sharing virtual address space. The ASID is eight bits in
length and can be set by software setting of the ASID of the currently running process in page
table entry register high (PTEH) within the MMU. When the process is switched using the ASID,
the TLB does not have to be purged.
In single virtual memory mode, the ASID is used to provide memory protection for processes
running simultaneously and using the virtual address space exclusively (see section 4.3.3, TLB
Address Comparison).
Rev. 3.00 Jan. 18, 2008 Page 173 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
4.2
Register Descriptions
There are four registers for MMU processing. These are all peripheral module registers, so they
are located in address space area P4 and can only be accessed from privileged mode by specifying
the address.
The MMU has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and access size of these registers.
•
•
•
•
Page table entry register high (PTEH)
Page table entry register low (PTEL)
Translation table base register (TTB)
MMU control register (MMUCR)
4.2.1
Page Table Entry Register High (PTEH)
The page table entry register high (PTEH) register residing at address H'FFFF FFF0, which
consists of a virtual page number (VPN) and ASID. The VPN set is the VPN of the virtual address
at which the exception is generated in case of an MMU exception or address error exception.
When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case
the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the
ASID, software sets the number of the currently executing process. The VPN and ASID are
recorded in the TLB by the LDTLB instruction.
A program that modifies the ASID in PTEH should be allocated in the P1 or P2 areas.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 10
VPN

R/W
The Number of the Logical Page
9, 8

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
7 to 0
ASID

R/W
Rev. 3.00 Jan. 18, 2008 Page 174 of 1458
REJ09B0033-0300
Address Space Identifier
Section 4 Memory Management Unit (MMU)
4.2.2
Page Table Entry Register Low (PTEL)
The page table entry register low (PTEL) register residing at address H'FFFF FFF4, and used to
store the physical page number and page management information to be recorded in the TLB by
the LDTLB instruction. The contents of this register are only modified in response to a software
command.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 29

All 0
R/W
Reserved
These bits are always read as 0. The write value
should always be 0.
28 to 10
PPN

9

8
V
7
R/W
The Number of the Physical Page
0
R
Page Management Information

R/W
For more details, see section 4.3, TLB Functions.

0
R
6, 5
PR

R/W
4
SZ

R/W
3
C

R/W
2
D

R/W
1
SH

R/W
0

0
R
4.2.3
Translation Table Base Register (TTB)
The translation table base register (TTB) residing at address H'FFFF FFF8, which points to the
base address of the current page table. The hardware does not set any value in TTB automatically.
TTB is available to software for general purposes. The initial value is undefined.
4.2.4
MMU Control Register (MMUCR)
The MMU control register (MMUCR) residing at address H'FFFF FFE0. Any program that
modifies MMUCR should reside in the P1 or P2 area.
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Bit
Bit Name
Initial
Value
R/W
Description
31 to 9

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
SV
0
R/W
Single Virtual Memory Mode
0: Multiple virtual memory mode
1: Single virtual memory mode
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5, 4
RC
All 0
R/W
Random Counter
A 2-bit random counter that is automatically updated by
hardware according to the following rules in the event of
an MMU exception.
When a TLB miss exception occurs, all of TLB entry
way corresponding to the virtual address at which the
exception occurred are checked. If all ways are valid, 1
is added to RC; if there is one or more invalid way, they
are set by priority from way 0, in the order way 0, way 1,
way 2, way 3. In the event of an MMU exception other
than a TLB miss exception, the way which caused the
exception is set in RC.
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
TF
0
R/W
TLB Flush
Write 1 to flush the TLB (clear all valid bits of the TLB to
0). When they are read, 0 is always returned.
1
IX
0
R/W
Index Mode
0: VPN bits 16 to 12 are used as the TLB index number.
1: The value obtained by EX-ORing ASID bits 4 to 0 in
PTEH and VPN bits 16 to 12 is used as the TLB
index number.
0
AT
0
R/W
Address Translation
Enables/disables the MMU.
0: MMU disabled
1: MMU enabled
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4.3
TLB Functions
4.3.1
Configuration of the TLB
The TLB caches address translation table information located in the external memory. The address
translation table stores the virtual page number and the corresponding physical number, the
address space identifier, and the control information for the page, which is the unit of address
translation. Figure 4.6 shows the overall TLB configuration. The TLB is 4-way set associative
with 128 entries. There are 32 entries for each way. Figure 4.7 shows the configuration of virtual
addresses and TLB entries.
Way 0 to 3
Entry 0
VPN(31 to 17)
VPN(11 to 10) ASID(7 to 0)
Way 0 to 3
V
Entry 0
Entry 1
Entry 1
Entry 31
Entry 31
PPN(28 to 10)PR(1 to 0) SZ
Address array
C
D SH
Data array
Figure 4.6 Overall Configuration of the TLB
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10 9
31
VPN
0
Offset
Virtual address (1-kbyte page)
31
12
11
VPN
0
Offset
Virtual address (4-kbyte page)
(15)
(2)
(8)
(1)
VPN (31 to 17) VPN (11 to 10) ASID V
(19)
(2) (1) (1) (1) (1)
PPN
PR SZ C D SH
TLB entry
[Legend]
VPN:
Virtual page number
Upper 19 bits of virtual address for a 1-kbyte page, or upper 20 bits of logical address for a 4-kbyte page. Since VPN
bits 16 to 12 are used as the index number, they are not stored in the TLB entry. Attention must be paid to the
synonym problem (see section 4.4.4, Avoiding Synonym Problems).
ASID: Address space identifier
Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple
virtual memory mode, if the SH bit is 0, the address is compared with the ASID in PTEH when address comparison is
performed.
SH:
Share status bit
0: Page not shared between processes
1: Page shared between processes
SZ:
Page-size bit
0: 1-kbyte page
1: 4-kbyte page
V:
Valid bit
Indicates whether entry is valid.
0: Invalid
1: Valid
Cleared to 0 by a power-on reset. Not affected by a manual reset.
PPN:
Physical page number
Upper 22 bits of physical address. PPN bits 11 to10 are not used in case of a 4-kbyte page.
PR:
Protection key field
2-bit field encoded to define the access rights to the page.
00: Reading only is possible in privileged mode.
01: Reading/writing is possible in privileged mode.
10: Reading only is possible in privileged/user mode.
11: Reading/writing is possible in privileged/user mode.
C:
Cacheable bit
Indicates whether the page is cacheable.
0: Non-cacheable
1: Cacheable
D:
Dirty bit
Indicates whether the page has been written to.
0: Not written to
1: Written to
Figure 4.7 Virtual address and TLB Structure
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4.3.2
TLB Indexing
The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16
to 12 and ASID bits 4 to 0 in PTEH are used as the index number regardless of the page size. The
index number can be generated in two different ways depending on the setting of the IX bit in
MMUCR.
1. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index
number
2. When IX = 0, VPN bits 16 to 12 alone are used as the index number
The first method is used to prevent lowered TLB efficiency that results when multiple processes
run simultaneously in the same virtual address space (multiple virtual memory) and a specific
entry is selected by indexing of each process. In single virtual memory mode (MMUCR.SV = 1),
IX bit should be set to 0. Figures 4.8 and 4.9 show the indexing schemes.
Virtual address
31
PTEH register
17 16 12 11
0
10
31
VPN
7
0
0
ASID
ASID(4 to 0)
Exclusive-OR
Index
Way 0 to 3
0
VPN(31 to 17)
VPN(11 to 10)
ASID(7 to 0)
V
PPN(28 to 10) PR(1 to 0) SZ
C
D
SH
31
Address Array
Data Array
Figure 4.8 TLB Indexing (IX = 1)
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Section 4 Memory Management Unit (MMU)
Virtual address
31
17 16 12 11
0
Index
Way 0 to 3
0
VPN(31 to 17)
VPN(11 to 10)
ASID(7 to 0)
V
PPN(28 to 10) PR(1 to 0) SZ
C
D
SH
31
Address array
Data array
Figure 4.9 TLB Indexing (IX = 0)
4.3.3
TLB Address Comparison
The results of address comparison determine whether a specific virtual page number is registered
in the TLB. The virtual page number of the virtual address that accesses external memory is
compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is
compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If
the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered.
It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one
way, as hardware operation is not guaranteed if this occurs. An example of setting which causes
TLB hits to occur simultaneously in more than one way is described below. It is necessary to
ensure that this kind of setting is not made by software.
1. If there are two identical TLB entries with the same VPN and a setting is made such that a
TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1)
and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there
is a possibility of simultaneous TLB hits in both these ways.
2. If several entries which have different ASID with the same VPN are registered in single virtual
memory mode, there is the possibility of simultaneous TLB hits in more than one way when
accessing the corresponding page in privileged mode. Several entries with the same VPN must
not be registered in single virtual memory mode.
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Section 4 Memory Management Unit (MMU)
3. There is the possibility of simultaneous TLB hits in more than one way. These hits may occur
depending on the contents of ASID in PTEH when a page to which SH is set 1 is registered in
the TLB in index mode (MMUCR.IX = 1). Therefore a page to which SH is set 1 must not be
registered in index mode. When memory is shared by several processings, different pages must
be registered in each ASID.
The object compared varies depending on the page management information (SZ, SH) in the TLB
entry. It also varies depending on whether the system supports multiple virtual memory or single
virtual memory.
The page-size information determines whether VPN (11 to 10) is compared. VPN (11 to 10) is
compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1).
The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry
are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not
when there is sharing (SH = 1).
When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged
(SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared
when single virtual memory is supported and privileged mode is engaged. The objects of address
comparison are shown in figure 4.10.
SH = 1 or
(SR.MD = 1 and
MMUCR.SV = 1)?
No
Yes
SZ = 0?
No (4-kbyte)
Yes (1-kbyte)
Bits compared:
VPN 31 to 17
VPN 11 to 10
SZ = 0?
No (4-kbyte)
Yes (1-kbyte)
Bits compared:
VPN 31 to 17
Bits compared:
VPN 31 to 17
VPN 11 to 10
ASID 7 to 0
Bits compared:
VPN 31 to 17
ASID 7 to 0
Figure 4.10 Objects of Address Comparison
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Section 4 Memory Management Unit (MMU)
4.3.4
Page Management Information
In addition to the SH and SZ bits, the page management information of TLB entries also includes
D, C, and PR bits.
The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit
is 0, an attempt to write to the page results in an initial page write exception. For physical page
swapping between secondary memory and main memory, for example, pages are controlled so that
a dirty page is paged out of main memory only after that page is written back to secondary
memory. To record that there has been a write to a given page in the address translation table in
memory, an initial page write exception is used.
The C bit in the entry indicates whether the referenced page resides in a cacheable or noncacheable area of memory. When the control registers and on-chip memory in area 1 are mapped,
set the C bit to 0. The PR field specifies the access rights for the page in privileged and user modes
and is used to protect memory. Attempts at non-permitted accesses result in TLB protection
violation exceptions.
Access states designated by the D, C, and PR bits are shown in table 4.1.
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Table 4.1
Access States Designated by D, C, and PR Bits
Privileged Mode
D bit
C bit
PR bit
User Mode
Reading
Writing
Reading
Writing
0
Permitted
Initial page write
exception
Permitted
Initial page write
exception
1
Permitted
Permitted
Permitted
Permitted
0
Permitted
(no caching)
Permitted
(no caching)
Permitted
(no caching)
Permitted
(no caching)
1
Permitted
(with caching)
Permitted
(with caching)
Permitted
(with caching)
Permitted
(with caching)
00
Permitted
TLB protection
violation
exception
TLB protection
violation
exception
TLB protection
violation exception
01
Permitted
Permitted
TLB protection
violation
exception
TLB protection
violation exception
10
Permitted
TLB protection
violation
exception
Permitted
TLB protection
violation exception
11
Permitted
Permitted
Permitted
Permitted
4.4
MMU Functions
4.4.1
MMU Hardware Management
There are two kinds of MMU hardware management as follows.
1. The MMU decodes the virtual address accessed by a process and performs address translation
by controlling the TLB in accordance with the MMUCR settings.
2. In address translation, the MMU receives page management information from the TLB, and
determines the MMU exception and whether the cache is to be accessed (using the C bit). For
details of the determination method and the hardware processing, see section 4.5, MMU
Exceptions.
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4.4.2
MMU Software Management
There are three kinds of MMU software management, as follows.
1. MMU register setting
MMUCR setting, in particular, should be performed in areas P1 and P2 for which address
translation is not performed. Also, since SV and IX bit changes constitute address translation
system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to
the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the
AT bit cleared to 0, use in the disabled state must be avoided with software that does not use
the MMU.
2. TLB entry recording, deletion, and reading
TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing
directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory
allocation TLB can be accessed. See section 4.4.3, MMU Instruction (LDTLB), for details of
the LDTLB instruction, and section 4.6, Memory-Mapped TLB, for details of the memorymapped TLB.
3. MMU exception processing
When an MMU exception is generated, it is handled on the basis of information set from the
hardware side. See section 4.5, MMU Exceptions, for details.
When single virtual memory mode is used, it is possible to create a state in which physical
memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to
specify recording of all TLB entries. This strengthens inter-process memory protection, and
enables special access levels to be created in the privileged mode only.
Recording a 1- or 4- kbyte page TLB entry may result in a synonym problem. See section 4.4.4,
Avoiding Synonym Problems.
4.4.3
MMU Instruction (LDTLB)
The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is
0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR
to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the
index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in
PTEH and ASID bits 4 to 0 in PTEH are used as the index number.
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Figure 4.11 shows the case where the IX bit in MMUCR is 0.
When an MMU exception occurs, the virtual page number of the virtual address that caused the
exception is set in PTEH by hardware. The way is set in the RC bit in MMUCR for each exception
according to the rules (see section 4.2.4, MMU Control Register (MMUCR)). Consequently, if the
LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine,
TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH
and the RC bits in MMUCR.
As the LDTLB instruction changes address translation information, there is a risk of destroying
address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure,
therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an
access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two
instructions after the LDTLB instruction.
MMUCR
31
9
0
0
SV 0 0 RC 0 TF IX AT
Way selection
Index
PTEH register
31
17
VPN
12
10
VPN
8
0
PTEL register
31 29 28
10
0
000
ASID
PPN
0
0 V 0 PR SZ C D SH 0
Write
Write
Way 0 to 3
0
VPN(31 to 17)
VPN(11 to 10)
ASID(7 to 0)
V
PPN(28 to 10) PR(1 to 0) SZ
C
D SH
31
Address array
Data array
Figure 4.11 Operation of LDTLB Instruction
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Section 4 Memory Management Unit (MMU)
4.4.4
Avoiding Synonym Problems
When a 1- or 4-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number
of virtual addresses are mapped onto a single physical address, the same physical address data will
be recorded in a number of cache entries, and it will not be possible to guarantee data congruity.
The reason that this problem occurs is explained below with reference to figure 4.12.
The relationship between bit n of the virtual address and cache size is shown in the following
table. Note that no synonym problems occur in 4-kbyte page when the cache size is 16 kbytes.
Cache Size
Bit n in Virtual Address
16 kbytes
11
32 kbytes
12
To achieve high-speed operation of this LSI’s cache, an index number is created using virtual
address bits 12 to 4. When a 1-kbyte page is used, virtual address bits 12 to 10 is subject to
address translation and when a 4-kbyte page is used, a virtual address bit 12 is subject to address
translation. Therefore, the physical address bits 12 to 10 may not be the same as the virtual address
bits 12 to 10.
For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following
translation has been performed are recorded in two TLBs:
Virtual address 1 H'0000 0000 → physical address H'0000 0C00
Virtual address 2 H'000 00C00 → physical address H'0000 0C00
Virtual address 1 is recorded in cache entry H'000, and virtual address 2 in cache entry H'0C0.
Since two virtual addresses are recorded in different cache entries despite the fact that the physical
addresses are the same, memory inconsistency will occur as soon as a write is performed to either
virtual address.
Consequently, the following restrictions apply to the recording of address translation information
in TLB entries.
1. When address translation information whereby a number of 1-kbyte page TLB entries are
translated into the same physical address is recorded in the TLB, ensure that the VPN bits 12 is
the same.
2. When address translation information whereby a number of 4-kbyte page TLB entries are
translated into the same physical address is recorded in the TLB, ensure that the VPN bit 12 is
the same.
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3. Do not use the same physical addresses for address translation information of different page
sizes.
The above restrictions apply only when performing accesses using the cache.
Note: When multiple items of address translation information use the same physical memory to
provide for future SuperH RISC engine family expansion, ensure that the VPN bits 20 to
10 are the same.
• When using a 4-kbyte page
Virtual address
31
13 12 11 10
0
Offset
VPN
Virtual address 12 to 4
Physical address
13 12 11 10
28
0
Cache
Offset
PPN
Physical address 28 to 10
• When using a 1-kbyte page
Virtual address
31
13 12 11 10
VPN
Virtual address 12 to 4
Physical address
28
0
Offset
13 12 11 10
PPN
0
Cache
Offset
Physical address 28 to 10
Figure 4.12 Synonym Problem (32-kbyte Cache)
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4.5
MMU Exceptions
When the address translation unit of the MMU is enabled, occurrence of the MMU exception is
checked following the CPU address error check. There are four MMU exceptions: TLB miss, TLB
invalid, TLB protection violation, and initial page write, and these MMU exceptions are checked
in this order.
4.5.1
TLB Miss Exception
A TLB miss results when the virtual address and the address array of the selected TLB entry are
compared and no match is found. TLB miss exception processing includes both hardware and
software operations.
• Hardware Operations
In a TLB miss, this hardware executes a set of prescribed operations, as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written to the save program counter (SPC). If the exception occurred in a delay slot, the PC
value indicating the address of the related delayed branch instruction is written to the SPC.
E The contents of the status register (SR) at the time of the exception are written to the save
status register (SSR).
F. The mode (MD) bit in SR is set to 1 to place the privileged mode.
G. The block (BL) bit in SR is set to 1 to mask any further exception requests.
H. The register bank (RB) bit in SR is set to 1.
I. The RC field in the MMU control register (MMUCR) is incremented by 1 when all entries
indexed are valid. When some entries indexed are invalid, the smallest way number of
them is set in RC. The setting priority is way0, way1, way2, and way3.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0400 to invoke the user-written TLB miss exception handler.
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• Software (TLB Miss Handler) Operations
The software searches the page tables in external memory and allocates the required page table
entry. Upon retrieving the required page table entry, software must execute the following
operations:
A. Write the value of the physical page number (PPN) field and the protection key (PR), page
size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table
entry recorded in the address translation table in the external memory into the PTEL
register.
B. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
C. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
D. Issue the return from exception handler (RTE) instruction to terminate the handler routine
and return to the instruction stream. Issue the RTE instruction after issuing two instructions
from the LDTLB instruction.
4.5.2
TLB Protection Violation Exception
A TLB protection violation exception results when the virtual address and the address array of the
selected TLB entry are compared and a valid entry is found to match, but the type of access is not
permitted by the access rights specified in the PR field. TLB protection violation exception
processing includes both hardware and software operations.
• Hardware Operations
In a TLB protection violation exception, this hardware executes a set of prescribed operations,
as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the
EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written into SPC (if the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written into SPC).
E. The contents of SR at the time of the exception are written to SSR.
F. The MD bit in SR is set to 1 to place the privileged mode.
G. The BL bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way that generated the exception is set in the RC field in MMUCR.
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Section 4 Memory Management Unit (MMU)
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100 to invoke the TLB protection violation exception handler.
• Software (TLB Protection Violation Handler) Operations
Software resolves the TLB protection violation and issues the RTE (return from exception
handler) instruction to terminate the handler and return to the instruction stream. Issue the RTE
instruction after issuing two instructions from the LDTLB instruction.
4.5.3
TLB Invalid Exception
A TLB invalid exception results when the virtual address is compared to a selected TLB entry
address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception
processing includes both hardware and software operations.
• Hardware Operations
In a TLB invalid exception, this hardware executes a set of prescribed operations, as follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Either exception code H'040 for a load access, or H'060 for a store access, is written to the
EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the delayed branch instruction is written to the SPC.
E. The contents of SR at the time of the exception are written into SSR.
F. The mode (MD) bit in SR is set to 1 to place the privileged mode.
G. The block (BL) bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way number causing the exception is written to RC in MMUCR.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100, and the TLB protection violation exception handler starts.
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• Software (TLB Invalid Exception Handler) Operations
The software searches the page tables in external memory and assigns the required page table
entry. Upon retrieving the required page table entry, software must execute the following
operations:
A. Write the values of the physical page number (PPN) field and the values of the protection
key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of
the page table entry recorded in the external memory to the PTEL register.
B. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
C. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
D. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
RTE instruction should be issued after two instructions form the LDTLB instruction.
4.5.4
Initial Page Write Exception
An initial page write exception results in a write access when the virtual address and the address
array of the selected TLB entry are compared and a valid entry with the appropriate access rights
is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial
page write exception processing includes both hardware and software operations.
• Hardware Operations
In an initial page write exception, this hardware executes a set of prescribed operations, as
follows:
A. The VPN field of the virtual address causing the exception is written to the PTEH register.
B. The virtual address causing the exception is written to the TEA register.
C. Exception code H'080 is written to the EXPEVT register.
D. The PC value indicating the address of the instruction in which the exception occurred is
written to the SPC. If the exception occurred in a delay slot, the PC value indicating the
address of the related delayed branch instruction is written to the SPC.
E. The contents of SR at the time of the exception are written to SSR.
F. The MD bit in SR is set to 1 to place the privileged mode.
G. The BL bit in SR is set to 1 to mask any further exception requests.
H. The RB bit in SR is set to 1.
I. The way that caused the exception is set in the RC field in MMUCR.
J. Execution branches to the address obtained by adding the value of the VBR contents and
H'0000 0100 to invoke the user-written initial page write exception handler.
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• Software (Initial Page Write Handler) Operations
The software must execute the following operations:
A. Retrieve the required page table entry from external memory.
B. Set the D bit of the page table entry in the external memory to 1.
C. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table
entry in the external memory to the PTEL register.
D. If using software for way selection for entry replacement, write the desired value to the RC
field in MMUCR.
E. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB.
F. Issue the RTE instruction to terminate the handler and return to the instruction stream. The
RTE instruction must be issued after two LDTLB instructions.
4.5.5
MMU Exception in Repeat Loop
If a CPU address error or MMU exception occurs in a specific instruction in the repeat loop, the
SPC may indicate an illegal address or the repeat loop cannot be reexecuted correctly even if the
SPC is correct. Accordingly, if a CPU address error or MMU exception occurs in a specific
instruction in the repeat loop, this LSI generates a specific exception code to set the EXPEVT to
H′070 for a TLB miss exception, TLB invalid exception, initial page write exception, and CPU
address error and to H'0D0 for a TLB protection violation exception. In addition, a vector offset
for TLB miss exception is H'100. For details, refer to section 7.4.3, Exception in Repeat Control
Period.
Rev. 3.00 Jan. 18, 2008 Page 192 of 1458
REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
Start
Yes
Address error?
CPU address
error
No
No
SH = 0 and
(MMUCR.SV = 0 or
SR.MD = 0)?
Yes
No
VPNs match?
VPNs
and ASIDs
match?
No
Yes
Yes
No
V = 1?
TLB miss
exception
TLB invalid
exception
Yes
User or
privileged?
User mode
Privileged mode
PR?
PR?
00/01
W
10
R/W?
R
11
R/W?
01/11
W
W
R
No
00/10
R/W?
R/W?
R
R
W
D = 1?
Yes
TLB protection
violation exception
TLB protection
violation exception
Initial page write
exception
No (Non-cacheable)
Memory
access
C = 1?
Yes (Cacheable)
Cache
access
Figure 4.13 MMU Exception Generation Flowchart
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REJ09B0033-0300
Section 4 Memory Management Unit (MMU)
4.6
Memory-Mapped TLB
In order for TLB operations to be managed by software, TLB contents can be read or written to in
the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual
address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F200 0000 to
H'F2FF FFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F300 0000 to H'F3FF
FFFF. The V bit in the address array can also be accessed from the data array. Only longword
access is possible for both the address array and the data array. However, the instruction data
cannot be fetched from both arrays.
4.6.1
Address Array
The address array is assigned to H'F200 0000 to H'F2FF FFFF. To access an address array, the 32bit address field (for read/write operations) and 32-bit data field (for write operations) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the VPN, V bit and ASID to be written to the address array (figure 4.14 (1)).
In the address field, specify the entry address for selecting the entry (bits 16 to 12), W for
selecting the way (bits 9 to 8) and H′F2 to indicate address array access (bits 31 to 24). The IX bit
in MMUCR indicates whether an EX-OR is taken of the entry address and ASID.
The following two operations can be used on the address array:
1. Address array read
VPN, V, and ASID are read from the TLB entry corresponding to the entry address and way
set in the address field.
2. TLB address array write
The data specified in the data field are written to the TLB entry corresponding to the entry
address and way set in the address field.
4.6.2
Data Array
The data array is assigned to H'F300 0000 to H'F3FF FFFF. To access a data array, the 32-bit
address field (for read/write operations), and 32-bit data field (for write operations) must be
specified. The address section specifies information for selecting the entry to be accessed; the data
section specifies the longword data to be written to the data array (figure 4.14 (2)).
In the address section, specify the entry address for selecting the entry (bits 16 to 12), W for
selecting the way (bits 9 to 8), and H'F3 to indicate data array access (bits 31 to 24). The IX bit in
MMUCR indicates whether an EX-OR is taken of the entry address and ASID.
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Section 4 Memory Management Unit (MMU)
Both reading and writing use the longword of the data array specified by the entry address and
way number. The access size of the data array is fixed at longword.
(1) TLB Address Array Access
• Read Access
31
Address field
24 23
17 16
12 1110 9 8 7 6
2 1 0
*............*
VPN
* * W 0 * . . . . . . . . . * 00
1 1 1 1 0 0 1 0
31
17 16
12 1110 9 8 7
0 . . . . . . . 0 VPN 0 V
VPN
Data field
0
ASID
• Write Access
31
Address field
24 23
17 16
12 11 10 9 8 7 6
2 1 0
*............*
VPN
* * W 0 * . . . . . . . . . * 00
1 1 1 1 0 0 1 0
31
17 16
12 11 10 9 8 7
* . . . . . . . * VPN * V
VPN
Data field
VPN:
V:
W:
ASID:
*:
0
ASID
Virtual page number
Valid bit
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Address space identifier
Don’t care bit
(2) TLB Data Array Access
• Read/Write Access
31
Address field
31
Data field
24 23
17 16
12 1110 9 8 7
2 1 0
*............*
VPN
* * W * . . . . . . . . . . . * 00
1 1 1 1 0 0 1 1
29 28
0 0 0
PPN:
PR:
C:
SH:
VPN:
X:
W:
V:
SZ:
D:
*:
10 9 8 7 6 5 4 3 2 1 0
PPN
X V X PR SZ C D SH X
Physical page number
Protection key field
Cacheable bit
Share status bit
Virtual page number
0 for read, don’t care bit for write
Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3)
Valid bit
Page-size bit
Dirty bit
Don’t care bit
Figure 4.14 Specifying Address and Data for Memory-Mapped TLB Access
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Section 4 Memory Management Unit (MMU)
4.6.3
(1)
Usage Examples
Invalidating Specific Entries
Specific TLB entries can be invalidated by writing 0 to the entry’s V bit. R0 specifies the write
data and R1 specifies the address.
; R0=H'1547 381C
R1=H'F201 3000
; MMUCR.IX=0
; the V bit of way 0 of the entry selected by the VPN(16–12)=B'1 0011
; index is cleared to 0,achieving invalidation.
MOV.L
(2)
R0,@R1
Reading the Data of a Specific Entry
This example reads the data section of a specific TLB entry. The bit order indicated in the data
field in figure 4.17 (2) is read. R0 specifies the address and the data section of a selected entry is
read to R1.
; R0=H'F300 4300
VPN(16-12)=B'00100
Way 3
; MOV.L @R0,R1
4.7
Usage Note
The following operations should be performed in the P1 or P2 area. In addition, when the P0, P3,
or U0 area is accessed consecutively (this access includes instruction fetching), the instruction
code should be placed at least two instructions after the instruction that executes the following
operations.
1.
2.
3.
4.
5.
Modification of SR.MD or SR.BL
Execution of the LDTLB instruction
Write to the memory-mapped TLB
Modification of MMUCR
Modification of PTEH.ASID
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Section 5 Cache
Section 5 Cache
5.1
Features
•
•
•
•
•
•
Capacity: 16 or 32 kbytes
Structure: Instructions/data mixed, 4-way set associative
Locking: Way 2 and way 3 are lockable
Line size: 16 bytes
Number of entries: 256 entries/way in 16-kbyte mode to 512 entries/way in 32-kbyte mode
Write system: Write-back/write-through is selectable for spaces P0, P1, P3, and U0
Group 1 (P0, P3, and U0 areas)
Group 2 (P1 area)
• Replacement method: Least-recently used (LRU) algorithm
Note: After power-on reset or manual reset, initialized as 16-kbyte mode (256 entries/way).
5.1.1
Cache Structure
The cache mixes instructions and data and uses a 4-way set associative system. It is composed of
four ways (banks), and each of which is divided into an address section and a data section. Note
that the following sections will be described for the 16-kbyte mode as an example. For other cache
size modes, change the number of entries and size/way according to table 5.1. Each of the address
and data sections is divided into 256 entries. The entry data is called a line. Each line consists of
16 bytes (4 bytes × 4). The data capacity per way is 4 kbytes (16 bytes × 256 entries) in the cache
as a whole (4 ways). The cache capacity is 16 kbytes as a whole.
Table 5.1
Number of Entries and Size/Way in Each Cache Size
Cache Size
Number of Entries
Size/Way
16 kbytes
256
4 kbytes
32 kbytes
512
8 kbytes
CACH001A_000020020800
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Section 5 Cache
Figure 5.1 shows the cache structure.
Address array (ways 0 to 3)
Entry 0 V U Tag address
Entry 1
Data array (ways 0 to 3)
0
.
.
.
.
.
.
Entry 255
LW0
LW1
LW2
LW3
0
1
1
.
.
.
.
.
.
.
.
.
.
.
.
255
255
128 (32 × 4) bits
24 (1 + 1 + 22) bits
LRU
6 bits
LW0 to LW3: Longword data 0 to 3
Figure 5.1 Cache Structure
(1)
Address Array
The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data
is not valid. The U bit indicates whether the entry has been written to in write-back mode. When
the U bit is 1, the entry has been written to; when 0, it has not. The tag address holds the physical
address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used
for comparison during cache searches.
In this LSI, the top three of 32 physical address bits are used as shadow bits (see section 9, Bus
State Controller (BSC)), and therefore the top three bits of the tag address are cleared to 0.
The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset.
The tag address is not initialized by either a power-on or manual reset.
(2)
Data Array
Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The
data array is not initialized by a power-on or manual reset.
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Section 5 Cache
(3)
LRU
With the 4-way set associative system, up to four instructions or data with the same entry address
can be registered in the cache. When an entry is registered, LRU shows which of the four ways it
is recorded in. There are six LRU bits, controlled by hardware. A least-recently-used (LRU)
algorithm is used to select the way.
Six LRU bits indicate the way to be replaced, when a cache miss occurs. Table 5.2 shows the
relationship between the LRU bits and the way to be replaced when the cache locking mechanism
is disabled. (For the relationship when the cache locking mechanism is enabled, refer to section
5.2.2, Cache Control Register 2 (CCR2).) If a bit pattern other than those listed in table 5.2 is set
in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits
by software, set one of the patterns listed in table 5.2.
The LRU bits are initialized to H'000000 by a power-on reset, but are not initialized by a manual
reset.
Table 5.2
LRU and Way Replacement (when Cache Locking Mechanism is Disabled)
LRU (Bits 5 to 0)
Way to be Replaced
000000, 000100, 010100, 100000, 110000, 110100
3
000001, 000011, 001011, 100001, 101001, 101011
2
000110, 000111, 001111, 010110, 011110, 011111
1
111000, 111001, 111011, 111100, 111110, 111111
0
5.2
Register Descriptions
The cache has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and access size of these registers.
• Cache control register 1 (CCR1)
• Cache control register 2 (CCR2)
• Cache control register 3 (CCR3)
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Section 5 Cache
5.2.1
Cache Control Register 1 (CCR1)
The cache is enabled or disabled using the CE bit in CCR1. CCR1 also has a CF bit (which
invalidates all cache entries), and WT and CB bits (which select either write-through mode or
write-back mode). Programs that change the contents of the CCR1 register should be placed in
address space that is not cached.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 4

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
3
CF
0
R/W
Cache Flush
Writing 1 flushes all cache entries (clears the V, U, and
LRU bits of all cache entries to 0). This bit is always
read as 0. Write-back to external memory is not
performed when the cache is flushed.
2
CB
0
R/W
Write-Back
Indicates the cache’s operating mode for space P1.
0: Write-through mode
1: Write-back mode
1
WT
0
R/W
Write-Through
Indicates the cache’s operating mode for spaces P0,
U0, and P3.
0: Write-back mode
1: Write-through mode
0
CE
0
R/W
Cache Enable
Indicates whether the cache function is used.
0: The cache function is not used.
1: The cache function is used.
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Section 5 Cache
5.2.2
Cache Control Register 2 (CCR2)
The CCR2 register controls the cache locking mechanism in cache lock mode only. The CPU
enters the cache lock mode when the DSP bit (bit 12) in the status register (SR) is set to 1 or the
lock enable bit (bit 16) in the cache control register 2 (CCR2) is set to 1. The cache locking
mechanism is disabled in non-cache lock mode (DSP bit = 0).
When a prefetch instruction (PREF@Rn) is issued in cache lock mode and a cache miss occurs,
the line of data pointed to by Rn will be loaded into the cache, according to the setting of bits 9
and 8 (W3LOAD, W3LOCK) and bits 1 and 0 (W2LOAD, W2LOCK in CCR2).
Table 5.3 shows the relationship between the settings of bits and the way that is to be replaced
when the cache is missed by a prefetch instruction.
On the other hand, when the cache is hit by a prefetch instruction, new data is not loaded into the
cache and the valid entry is held. For example, a prefetch instruction is issued while bits
W3LOAD and W3LOCK are set to 1 and the line of data to which Rn points is already in way 0,
the cache is hit and new data is not loaded into way 3.
In cache lock mode, bits W3LOCK and W2LOCK restrict the way that is to be replaced, when
instructions other than the prefetch instruction are issued. Table 5.4 shows the relationship
between the settings of bits in CCR2 and the way that is to be replaced when the cache is missed
by instructions other than the prefetch instruction.
Programs that change the contents of the CCR2 register should be placed in address space that is
not cached.
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Section 5 Cache
Bit
Bit Name
Initial
Value
R/W
Description
31 to 17

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
16
LE
0
R/W
Lock enable (LE)
Controls cache lock mode.
0: Enters cache lock mode when the DSP bit in the SR
register is set to 1.
1: Enters cache lock mode regardless of the DSP bit
value.
15 to 10

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
9
W3LOAD
0
R/W
8
W3LOCK
0
R/W
Way 3 Load (W3LOAD)
Way 3 Lock (W3LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W3LOAD and
W3LOCK in CCR2 are set to 1, the data is always
loaded into way 3. Under any other condition, the
prefetched data is loaded into the way to which LRU
points.
7 to 2

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
W2LOAD
0
R/W
0
W2LOCK
0
R/W
Way 2 Load (W2LOAD)
Way 2 Lock (W2LOCK)
When the cache is missed by a prefetch instruction
while in cache lock mode and when bits W2LOAD and
W2LOCK in CCR2 are set to 1, the data is always
loaded into way 2. Under any other condition, the
prefetched data is loaded into the way to which LRU
points.
Note: W2LOAD and W3LOAD should not be set to 1 at the same time.
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Section 5 Cache
Table 5.3
Way Replacement when a PREF Instruction Misses the Cache
DSP Bit
W3LOAD
W3LOCK
W2LOAD
W2LOCK
Way to be Replaced
0
*
*
*
*
Determined by LRU (table 5.2)
1
*
0
*
0
Determined by LRU (table 5.2)
1
*
0
0
1
Determined by LRU (table 5.5)
1
0
1
*
0
Determined by LRU (table 5.6)
1
0
1
0
1
Determined by LRU (table 5.7)
1
0
*
1
1
Way 2
1
1
0
*
Way 3
1
Note:
*
Table 5.4
Don’t care
W3LOAD and W2LOAD should not be set to 1 at the same time.
Way Replacement when Instructions other than the PREF Instruction Miss the
Cache
DSP Bit
W3LOAD
W3LOCK
W2LOAD
W2LOCK
Way to be Replaced
0
*
*
*
*
Determined by LRU (table 5.2)
1
*
0
*
0
Determined by LRU (table 5.2)
1
*
0
*
1
Determined by LRU (table 5.5)
1
*
1
*
0
Determined by LRU (table 5.6)
1
*
1
*
1
Determined by LRU (table 5.7)
Note:
*
Table 5.5
Don’t care
W3LOAD and W2LOAD should not be set to 1 at the same time.
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =0)
LRU (Bits 5 to 0)
Way to be Replaced
000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100
3
000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111
1
101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111
0
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Section 5 Cache
Table 5.6
LRU and Way Replacement (when W2LOCK = 0 and W3LOCK =1)
LRU (Bits 5 to 0)
Way to be Replaced
000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011
2
000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111
1
110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111
0
Table 5.7
LRU and Way Replacement (when W2LOCK = 1 and W3LOCK =1)
LRU (Bits 5 to 0)
Way to be Replaced
000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111,
010100, 010110, 011110, 011111
1
100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001,
111011, 111100, 111110, 111111
0
5.2.3
Cache Control Register 3 (CCR3)
The CCR3 register controls the cache size to be used. The cache size must be specified according
to the LSI to be selected. If the specified cache size exceeds the size of cache incorporated in the
LSI, correct operation cannot be guaranteed. Note that programs that change the contents of the
CCR3 register should be placed in un-cached address space. In addition, note that all cache entries
must be invalidated by setting the CF bit in the CCR1 to 1 before accessing the cache after the
CCR3 is modified.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 24

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
23 to 16
CSIZE7 to
CSIZE0
H'01
R/W
Cache Size
Specify the cache size as shown below.
0000 0001: 16-kbyte cache
0000 0010: 32-kbyte cache
Settings other than above are prohibited.
15 to 0

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
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Section 5 Cache
5.3
Operation
5.3.1
Searching the Cache
If the cache is enabled (the CE bit in CCR1 = 1), whenever instructions or data in spaces P0, P1,
P3, and U0 are accessed the cache will be searched to see if the desired instruction or data is in the
cache. Figure 5.2 illustrates the method by which the cache is searched. The cache is a physical
cache and holds physical addresses in its address section. The example of operation in 16-kbyte
mode is described below:
Entries are selected using bits 11 to 4 of the address (virtual) of the access to memory and the tag
address of that entry is read. In parallel with reading the tag address, the virtual address is
converted into the physical address. The virtual address of the access to memory and the physical
address (tag address) read from the address array are compared. The address comparison uses all
four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit
occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a
cache miss occurs. Figure 5.2 shows a hit on way 1.
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Section 5 Cache
Virtual address
31
12 11
4 3 21 0
Entry selection
Longword (LW) selection
Ways 0 to 3
Ways 0 to 3
0
1
MMU
V U Tag address
LW0
LW1
255
Physical address
CMP0 CMP1 CMP2 CMP3
Hit signal 1
CMP0: Comparison circuit 0
CMP1: Comparison circuit 1
CMP2: Comparison circuit 2
CMP3: Comparison circuit 3
Figure 5.2 Cache Search Scheme
Rev. 3.00 Jan. 18, 2008 Page 206 of 1458
REJ09B0033-0300
LW2
LW3
Section 5 Cache
5.3.2
(1)
Read Access
Read Hit
In a read access, instructions and data are transferred from the cache to the CPU. The LRU is
updated to indicate that the hit way is the most recently hit way.
(2)
Read Miss
An external bus cycle starts and the entry is updated. The way to be replaced is shown in table 5.4.
Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is
loaded from external memory to the cache, the instruction or data is transferred to the CPU in
parallel with being loaded to the cache. When it is loaded to the cache, the U bit is cleared to 0 and
the V bit is set to 1 to indicate that the hit way is the most recently hit way. When the U bit for the
entry which is to be replaced by entry updating in write-back mode is 1, the cache-update cycle
starts after the entry is transferred to the write-back buffer. After the cache completes its update
cycle, the write-back buffer writes the entry back to the memory. Transfer is in 16-byte units.
5.3.3
(1)
Prefetch Operation
Prefetch Hit
The LRU is updated to indicate that the hit way is the most recently hit way. The other contents of
the cache are not changed. Instructions and data are not transferred from the cache to the CPU.
(2)
Prefetch Miss
Instructions and data are not transferred from the cache to the CPU. The way that is to be replaced
is shown in table 5.3. The other operations are the same as those for a read miss.
5.3.4
(1)
Write Access
Write Hit
In a write access in write-back mode, the data is written to the cache and no external memory
write cycle is issued. The U bit of the entry that has been written to is set to 1, and the LRU is
updated to indicate that the hit way is the most recently hit way. In write-through mode, the data is
written to the cache and an external memory write cycle is issued. The U bit of the entry that has
been written to is not updated, and the LRU is updated to indicate that the hit way is the most
recently hit way.
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Section 5 Cache
(2)
Write Miss
In write-back mode, an external write cycle starts when a write miss occurs, and the entry is
updated. The way to be replaced is shown in table 5.4. When the U bit of the entry which is to be
replaced by entry updating is 1, the cache-update cycle starts after the entry has been transferred to
the write-back buffer. Data is written to the cache and the U bit and the V bit are set to 1. The
LRU is updated to indicate that the replaced way is the most recently updated way. After the cache
has completed its update cycle, the write-back buffer writes the entry back to the memory.
Transfer is in 16-byte units. In write-through mode, no write to cache occurs in a write miss; the
write is only to the external memory.
5.3.5
Write-Back Buffer
When the U bit of the entry to be replaced in write-back mode is 1, the entry must be written back
to the external memory. To increase performance, the entry to be replaced is first transferred to the
write-back buffer and fetching of new entries to the cache takes priority over writing back to the
external memory. After the fetching of new entries to the cache completes, the write-back buffer
writes the entry back to the external memory. During the write-back cycles, the cache can be
accessed. The write-back buffer can hold one line of cache data (16 bytes) and its physical
address. Figure 5.3 shows the configuration of the write-back buffer.
PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3
PA (31 to 4):
Physical address written to external memory
Longword 0 to 3: One line of cache data to be written to external
memory
Figure 5.3 Write-Back Buffer Configuration
5.3.6
Coherency of Cache and External Memory
Use software to ensure coherency between the cache and the external memory. When memory
shared by this LSI and another device is placed in an address space to which caching applies, use
the memory-mapped cache to make the data invalid and written back, as required. Memory that is
shared by this LSI’s CPU and DMAC should also be handled in this way.
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Section 5 Cache
5.4
Memory-Mapped Cache
To allow software management of the cache, cache contents can be read and written by means of
MOV instructions in privileged mode. The cache is mapped onto the P4 area in virtual address
space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data
array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size
for the address array and data array, and instruction fetches cannot be performed.
5.4.1
Address Array
The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the
32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be
specified. The address field specifies information for selecting the entry to be accessed; the data
field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array.
In the address field, specify the entry address for selecting the entry, W for selecting the way, A
for enabling or disabling the associative operation, and H'F0 for indicating address array access.
As for W, B'00 indicates way 0, B'01 indicates way 1, B'10 indicates way 2, and B'11 indicates
way 3.
In the data field, specify the tag address, LRU bits, U bit, and V bit. Figure 5.4 shows the address
and data formats in 16-byte mode. For other cache size modes, change the entry address and Was
shown in table 5.8. The following three operations are available in the address array.
(1)
Address-Array Read
Read the tag address, LRU bits, U bit, and V bit for the entry that corresponds to the entry address
and way specified by the address field of the read instruction. In reading, the associative operation
is not performed, regardless of whether the associative bit (A bit) specified in the address is 1 or 0.
(2)
Address-Array Write (Non-Associative Operation)
Write the tag address, LRU bits, U bit, and V bit, specified by the data field of the write
instruction, to the entry that corresponds to the entry address and way as specified by the address
field of the write instruction. Ensure that the associative bit (A bit) in the address field is set to 0.
When writing to a cache line for which the U bit = 1 and the V bit =1, write the contents of the
cache line back to memory, then write the tag address, LRU bits, U bit, and V bit specified by the
data field of the write instruction. Always clear the uppermost 3 bits (bits 31 to 29) of the tag
address to 0. When 0 is written to the V bit, 0 must also be written to the U bit for that entry.
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Section 5 Cache
(3)
Address-Array Write (Associative Operation)
When writing with the associative bit (A bit) of the address = 1, the addresses in the four ways for
the entry specified by the address field of the write instruction are compared with the tag address
that is specified by the data field of the write instruction. If the MMU is enabled in this case, a
virtual address specified by data is translated into a physical address via the TLB before
comparison. Write the U bit and the V bit specified by the data field of the write instruction to the
entry of the way that has a hit. However, the tag address and LRU bits remain unchanged. When
there is no way that receives a hit, nothing is written and there is no operation. This function is
used to invalidate a specific entry in the cache. When the U bit of the entry that has received a hit
is 1 at this point, writing back should be performed. However, when 0 is written to the V bit, 0
must also be written to the U bit of that entry.
5.4.2
Data Array
The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit
address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified.
The address field specifies information for selecting the entry to be accessed; the data field
specifies the longword data to be written to the data array.
In the address field, specify the entry address for selecting the entry, L for indicating the longword
position within the (16-byte) line, W for selecting the way, and H'F1 for indicating data array
access. As for L, B'00 indicates longword 0, B'01 indicates longword 1, B'10 indicates longword
2, and B'11 indicates longword 3. As for W, B'00 indicates way 0, B′01 indicates way 1, B'10
indicates way 2, and B′11 indicates way 3.
Since access size of the data array is fixed at longword, bits 1 and 0 of the address field should be
set to B'00.
Figure 5.4 shows the address and data formats in 16-kbyte mode. For other cache size modes,
change the entry address and W as shown in table 5.8.
The following two operations on the data array are available. The information in the address array
is not affected by these operations.
(1)
Data-Array Read
Read the data specified by L of the address filed, from the entry that corresponds to the entry
address and the way that is specified by the address filed.
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Section 5 Cache
(2)
Data-Array Write
Write the longword data specified by the data filed, to the position specified by L of the address
field, in the entry that corresponds to the entry address and the way specified by the address field.
(1) Address array access
(a) Address specification
Read access
31
24
23
1111 0000
14
13
12
11
W
*--------*
4
Entry address
2
3
0
*
0
0
0
0
0
Write access
31
24
23
1111 0000
14
13
12
11
W
*--------*
4
Entry address
3
0
2
A
*
(b) Data specification (both read and write accesses)
31
10
9
4
3
LRU
Tag address (31 to 10)
X
2
1
0
X
U
V
(2) Data array access (both read and write accesses)
(a) Address specification
31
24
1111 0001
23
14
*--------*
13
12
11
W
4
3
Entry address
2
L
0
1
0
0
(b) Data specification
31
0
Longword
*: Don’t care bit
X: 0 for read, don’t care for write
Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access
(16-kbyte mode)
Table 5.8
Address Format Based on the Size of Cache to be Assigned to Memory
Cache Size
Entry Address Bits
W Bit
16 kbytes
11 to 4
13 and 12
32 kbytes
12 to 4
14 to 13
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Section 5 Cache
5.4.3
(1)
Usage Examples
Invalidating Specific Entries
Specific cache entries can be invalidated by writing 0 to the entry’s V bit in the memory-mapped
cache access. When the A bit is 1, the tag address specified by the write data is compared to the
tag address within the cache selected by the entry address, and a match is found, the entry is
written back if the entry’s U bit is 1 and the V bit and U bit specified by the write data are written.
If no match is found, there is no operation. In the example shown below, R0 specifies the write
data and R1 specifies the address.
; R0=H'01100010; VPN=B'0000 0001 0001 0000 0000 00, U=0, V=0
; R1=H'F0000088; address array access, entry=B'00001000, A=1
;
MOV.L R0,@R1
(2)
Reading the Data of a Specific Entry
To read the data field of a specific entry is enabled by the memory-mapped cache access. The
longword indicated in the data field of the data array in figure 5.4 is read into the register. In the
example shown below, R0 specifies the address and R1 shows what is read.
; R0=H'F100 004C; data array access, entry=B'00000100
; Way = 0, longword address = 3
;
MOV.L @R0,R1 ; Longword 3 is read.
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Section 6 X/Y Memory
Section 6 X/Y Memory
This LSI has on-chip X-memory and Y-memory which can be used to store instructions or data.
6.1
Features
• Page
There are four pages. The X memory is divided into two pages (pages 0 and 1) and the Y
memory is divided into two pages (pages 0 and 1).
• Memory map
The X/Y memory is located in the virtual address space, physical address space, and X-bus and
Y-bus address spaces.
In the virtual address space, this memory is located in the addresses shown in table 6.1. These
addresses are included in space P2 (when SR.MD = 1) or Uxy (when SR.MD = 0 and SR.DSP
= 1) according to the CPU operating mode.
Table 6.1
X/Y Memory Virtual Addresses
Page
Memory Size (Total Four Pages) 16 kbytes
Page 0 of X memory
H'A5007000 to H'A5007FFF
Page 1 of X memory
H'A5008000 to H'A5008FFF
Page 0 of Y memory
H'A5017000 to H'A5017FFF
Page 1 of Y memory
H'A5018000 to H'A5018FFF
On the other hand, this memory is located in a part of area 1 in the physical address space. When
this memory is accessed from the physical address space, addresses in which the upper three bits
are 0 in addresses shown in table 6.1 are used. In the X-bus and Y-bus address spaces, addresses in
which the upper 16 bits are ignored in addresses of X memory and Y memory shown in table 6.1
are used.
• Ports
Each page has three independent read/write ports and is connected to each bus. The X memory
is connected to the I bus, X bus, and L bus. The Y memory is connected to the I bus, Y bus,
and L bus. The L bus is used when this memory is accessed from the virtual address space.
The I bus is used when this memory is accessed from the physical address space. The X bus
and Y bus are used when this memory is accessed from the X-bus and Y-bus address spaces.
XYM0000S_000020020300
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Section 6 X/Y Memory
• Priority order
In the event of simultaneous accesses to the same page from different buses, the accesses are
processed according to the priority order. The priority order is: I bus > X bus > L bus in the X
memory and I bus > Y bus > L bus in the Y memory.
6.2
Operation
6.2.1
Access from CPU
Methods for accessing by the CPU are directly via the L bus from the virtual addresses, and via
the I bus after the virtual addresses are converted to be the physical addresses using the MMU. As
long as a conflict on the page does not occur, access via the L bus is performed in one cycle.
Several cycles are necessary for accessing via the I bus. According to the CPU operating mode,
access from the CPU is as follows:
(1)
Privileged mode and privileged DSP mode (SR. MD = 1)
The X/Y memory can be accessed by the CPU directly from space P2. The MMU can be used to
map the virtual addresses in spaces P0 and P3 to this memory.
(2)
User DSP mode (SR.MD = 0 and SR.DSP = 1)
The X/Y memory can be accessed by the CPU directly from space Uxy. The MMU can be used to
map the virtual addresses in space U0 to this memory.
(3)
User mode (SR.MD = 0 and SR.DSP = 0)
The MMU can be used to map the virtual addresses in space U0 to this memory.
6.2.2
Access from DSP
Methods for accessing from the DSP differ according to instructions.
With a X data transfer instruction and a Y data transfer instruction, the X/Y memory is always
accessed via the X bus or Y bus. As long as a conflict on the page does not occur, access via the X
bus or Y bus is performed in one cycle. The X memory access via the X bus and the Y memory
access via the Y bus can be performed simultaneously.
In the case of a single data transfer instruction, methods for accessing from the DSP are directly
via the L bus from the virtual addresses, and via the I bus after the virtual addresses are converted
to be the physical addresses using the MMU. As long as a conflict on the page does not occur,
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Section 6 X/Y Memory
access via the L bus is performed in one cycle. Several cycles are necessary for accessing via the I
bus. According to the CPU operating mode, access from the CPU is as follows:
(1)
Privileged DSP mode (SR. MD = 1 and SR.DSP = 1)
The X/Y memory can be accessed by the DSP directly from space P2. The MMU can be used to
map the virtual addresses in spaces P0 and P3 to this memory.
(2)
User DSP mode (SR.MD = 0 and SR.DSP = 1)
The X/Y memory can be accessed by the DSP directly from space Uxy. The MMU can be used to
map the virtual addresses in space U0 to this memory.
6.2.3
Access from Bus Master Module
The X/Y memory is always accessed by bus master modules such as the DMAC and USB host via
the I bus, which is a physical address bus. Addresses in which the upper three bits are 0 in
addresses shown in table 6.1 must be used.
6.3
Usage Notes
6.3.1
Page Conflict
In the event of simultaneous accesses to the same page from different buses, the conflict on the
pages occurs. Although each access is completed correctly, this kind of conflict tends to lower
X/Y memory accessibility. Therefore it is advisable to provide software measures to prevent such
conflict as far as possible. For example, conflict will not arise if different memory or different
pages are accessed by each bus.
6.3.2
Bus Conflict
The I bus is shared by several bus master modules. When the X/Y memory is accessed via the I
bus, a conflict between the other I-bus master modules may occur on the I bus. This kind of
conflict tends to lower X/Y memory accessibility. Therefore it is advisable to provide software
measures to prevent such conflict as far as possible. For example, by accessing the X/Y memory
by the CPU not via the I bus but directly from space P2 or Uxy, conflict on the I bus can be
prevented.
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Section 6 X/Y Memory
6.3.3
MMU and Cache Settings
When the X/Y memory is accessed via the I bus using the cache from the CPU and DSP, correct
operation cannot be guaranteed. If the X/Y memory is accessed while the cache is enabled
(CCR1.CE = 1), it is advisable to access the X/Y memory via the L bus from space P2 or Uxy. If
the X/Y memory is accessed from space P0, P3, or U0, it is advisable to access the X/Y memory
via the I bus, which does not use the cache, with MMU setting enabled (MMUCR.AT = 1) and
cache disabled (C bit = 0) as page attributes. Since access using the MMU occurs via the I bus,
several cycles are necessary (the number of necessary cycles varies according to the ratio between
the internal clock (Iφ) and bus clock (Bφ) or the operation state of the DMAC). In a program that
requires high performance, it is advisable to access the X/Y memory from space P2 or Uxy. The
relationship described above is summarized in table 6.2.
Table 6.2
MMU and Cache Settings
Setting
Virtual Address Space and Access Enabled or Disabled
CCR1.CE
MMUCR.AT
P0, U0
P1
P2, Uxy
P3
0
0
B
B
A
B
0
1
B
B
A
B
1
0
X
X
A
X
1
1
C
X
A
C
Note:
6.3.4
A: Accessible (recommended)
B: Accessible
C: Accessible (Note that MMU page attribute must be specified as cache disabled by
clearing the C bit to 0.)
X: Not accessible
Sleep Mode
In sleep mode, I bus master modules such as the DMAC cannot access the X/Y memory.
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Section 7 Exception Handling
Section 7 Exception Handling
Exception handling is separate from normal program processing, and is performed by a routine
separate from the normal program. For example, if an attempt is made to execute an undefined
instruction code or an instruction protected by the CPU processing mode, a control function may
be required to return to the source program by executing the appropriate operation or to report an
abnormality and carry out end processing. In addition, a function to control processing requested
by LSI on-chip modules or an LSI external module to the CPU may also be required.
Transferring control to a user-defined exception processing routine and executing the process to
support the above functions are called exception handling. This LSI has two types of exceptions:
general exceptions and interrupts. The user can execute the required processing by assigning
exception handling routines corresponding to the required exception processing and then return to
the source program.
A reset input can terminate the normal program execution and pass control to the reset vector after
register initialization. This reset operation can also be regarded as an exception handling. This
section describes an overview of the exception handling operation. Here, general exceptions and
interrupts are referred to as exception handling. For interrupts, this section describes only the
process executed for interrupt requests. For details on how to generate an interrupt request, refer to
section 8, Interrupt Controller (INTC).
7.1
Register Descriptions
There are five registers for exception handling. A register with an undefined initial value should
be initialized by the software. Refer to section 37, List of Registers, for more details on the
addresses and access size of these registers.
•
•
•
•
•
TRAPA exception register (TRA)
Exception event register (EXPEVT)
Interrupt event register (INTEVT)
Interrupt event register 2 (INTEVT2)
Exception address register (TEA)
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Section 7 Exception Handling
Figure 7.1 shows the bit configuration of each register.
31
10 9
0
21 0
TRA
31
12 11
0
0
TRA
0
EXPEVT
31
12 11
0
EXPEVT
0
INTEVT
31
12 11
0
INTEVT
0
INTEVT2
31
INTEVT2
0
TEA
TEA
Figure 7.1 Register Bit Configuration
7.1.1
TRAPA Exception Register (TRA)
TRA is assigned to address H'FFFFFFD0 and consists of the 8-bit immediate data (imm) of the
TRAPA instruction. TRA is automatically specified by the hardware when the TRAPA instruction
is executed. Only bits 9 to 2 of the TRA can be re-written using the software.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 10


R
Reserved
These bits are always read as 0. The write value
should always be 0.
9 to 2
TRA

R/W
1, 0


R
8-bit Immediate Data
Reserved
These bits are always read as 0. The write value
should always be 0.
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Section 7 Exception Handling
7.1.2
Exception Event Register (EXPEVT)
EXPEVT is assigned to address H'FFFFFFD4 and consists of a 12-bit exception code. Exception
codes to be specified in EXPEVT are those for resets and general exceptions. These exception
codes are automatically specified the hardware when an exception occurs. Only bits 11 to 0 of
EXPEVT can be re-written using the software.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 12

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0
EXPEVT
*
R/W
12-bit Exception Code
Note: Initialized to H'000 at power-on reset and H'020 at manual reset.
7.1.3
Interrupt Event Register (INTEVT)
INTEVT is assigned to address H'FFFFFFD8 and stores an exception code or a code which
indicates interrupt priority order. A code to be specified when an interrupt occurs is determined by
an interrupt source. (For details, see section 8.4.6, Interrupt Exception Handling and Priority.)
These exception and interrupt priority order codes are automatically specified by the hardware
when an exception occurs. INTEVT can be modified using the software. Only bits 11 to 0 of
INTEVT can be modified using the software.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 12

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0
INTEVT

R
12-bit Exception Code
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Section 7 Exception Handling
7.1.4
Interrupt Event Register 2 (INTEVT2)
INTEVT2 is assigned to address H'A4000000 and consists of a 12-bit exception code. Exception
codes to be specified in INTEVT2 are those for interrupt requests. These exception codes are
automatically specified by the hardware when an exception occurs. INTEVT2 cannot be modified
using the software.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 12

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11 to 0
7.1.5
INTEVT2

R
12-bit Exception Code
Exception Address Register (TEA)
TEA is assigned to address H'FFFFFFFC and the virtual address for an exception occurrence is
stored in this register when an exception related to memory accesses occurs. TEA can be modified
using the software.
Bit
Bit Name
Initial
Value
R/W
Description
31 to 0
TEA
All 0
R/W
The virtual address for an exception occurrence
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Section 7 Exception Handling
7.2
Exception Handling Function
7.2.1
Exception Handling Flow
In exception handling, the contents of the program counter (PC) and status register (SR) are saved
in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of
the exception handler is invoked from a vector address. By executing the return from exception
handler (RTE) in the exception handler routine, it restores the contents of PC and SR, and returns
to the processor state at the point of interruption and the address where the exception occurred.
A basic exception handling sequence consists of the following operations. If an exception occurs
and the CPU accepts it, operations 1 to 8 are executed.
1.
2.
3.
4.
5.
6.
7.
8.
The contents of PC is saved in SPC.
The contents of SR is saved in SSR.
The block (BL) bit in SR is set to 1, masking any subsequent exceptions.
The mode (MD) bit in SR is set to 1 to place the privileged mode.
The register bank (RB) bit in SR is set to 1.
An exception code identifying the exception event is written to bits 11 to 0 of the exception
event register (EXPEVT); an exception code identifying the interrupt request is written to bits
11 to 0 of the interrupt event register (INTEVT) or interrupt event register 2 (INTEVT2).
If a TRAPA instruction is executed, an 8-bit immediate data specified by the TRAPA
instruction is set to TRA. For an exception related to memory accesses, the logic address
where the exception occurred is written to TEA.*1
Instruction execution jumps to the designated exception vector address to invoke the handler
routine.
The above operations from 1 to 8 are executed in sequence. During these operations, no other
exceptions may be accepted unless multiple exception acceptance is enabled.
In an exception handling routine for a general exception, the appropriate exception handling must
be executed based on an exception source determined by the EXPEVT. In an interrupt exception
handling routine, the appropriate exception handling must be executed based on an exception
source determined by the INTEVT or INTEVT2. After the exception handling routine has been
completed, program execution can be resumed by executing an RTE instruction. The RTE
instruction causes the following operations to be executed.
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Section 7 Exception Handling
1. The contents of the SSR are restored into the SR to return to the processing state in effect
before the exception handling took place.
2. A delay slot instruction of the RTE instruction is executed.*2
3. Control is passed to the address stored in the SPC.
The above operations from 1 to 3 are executed in sequence. During these operations, no other
exceptions may be accepted. By changing the SPC and SSR before executing the RTE instruction,
a status different from that in effect before the exception handling can also be specified.
Notes: 1. The MMU registers are also modified if an MMU exception occurs.
2. For details on the CPU processing mode in which RTE delay slot instructions are
executed, please refer to section 7.5, Usage Notes.
7.2.2
Exception Vector Addresses
A vector address for general exceptions is determined by adding a vector offset to a vector base
address. The vector offset for general exceptions other than the TLB miss exception is
H'00000100. The vector offset for interrupts is H'00000600. The vector base address is loaded into
the vector base register (VBR) using the software. The vector base address should reside in the P1
or P2 fixed physical address space.
7.2.3
Exception Codes
The exception codes are written to bits 11 to 0 of the EXPEVT (for reset or general exceptions) or
the INTEVT and INTEVT2 (for interrupt requests) to identify each specific exception event. See
section 8, Interrupt Controller (INTC), for details of the exception codes for interrupt requests.
Table 7.1 lists exception codes for resets and general exceptions.
7.2.4
Exception Request and BL Bit (Multiple Exception Prevention)
The BL bit in SR is set to 1 when a reset or exception is accepted. While the BL bit is set to 1,
acceptance of general exceptions is restricted as described below, making it possible to effectively
prevent multiple exceptions from being accepted.
If the BL bit is set to 1, an interrupt request is not accepted and is retained. The interrupt request is
accepted when the BL bit is cleared to 0. If the CPU is in low power consumption mode, an
interrupt is accepted even if the BL bit is set to 1 and the CPU returns from the low power
consumption mode.
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Section 7 Exception Handling
A DMA error is not accepted and is retained if the BL bit is set to 1 and accepted when the BL bit
is cleared to 0. User break requests generated while the BL bit is set are ignored and are not
retained. Accordingly, user breaks are not accepted even if the BL bit is cleared to 0.
If a general exception other than a DMA address error or user break occurs while the BL bit is set
to 1, the CPU enters a state similar to that in effect immediately after a reset, and passes control to
the reset vector (H'A0000000) (multiple exception). In this case, unlike a normal reset, modules
other than the CPU are not initialized, the contents of EXPEVT, SPC, and SSR are undefined, and
this status is not detected by an external device.
To enable acceptance of multiple exceptions, the contents of SPC and SSR must be saved while
the BL bit is set to 1 after an exception has been accepted, and then the BL bit must be cleared to
0. Before restoring the SPC and SSR, the BL bit must be set to 1.
7.2.5
(1)
Exception Source Acceptance Timing and Priority
Exception Request of Instruction Synchronous Type and Instruction Asynchronous
Type
Resets and interrupts are requested asynchronously regardless of the program flow. In general
exceptions, a DMA address error and a user break under the specific condition are also requested
asynchronously. The user cannot expect on which instruction an exception is requested. For
general exceptions other than a DMA address error and a user break under a specific condition,
each general exception corresponds to a specific instruction.
(2)
Re-execution Type and Processing-completion Type Exceptions
All exceptions are classified into two types: a re-execution type and a processing-completion type.
If a re-execution type exception is accepted, the current instruction executed when the exception is
accepted is terminated and the instruction address is saved to the SPC. After returning from the
exception processing, program execution resumes from the instruction where the exception was
accepted. In a processing-completion type exception, the current instruction executed when the
exception is accepted is completed, the next instruction address is saved to the SPC, and then the
exception processing is executed.
During a delayed branch instruction and delay slot, the following operations are executed. A reexecution type exception detected in a delay slot is accepted before executing the delayed branch
instruction. A processing-completion type exception detected in a delayed branch instruction or a
delay slot is accepted when the delayed branch instruction has been executed. In this case, the
acceptance of delayed branch instruction or a delay slot precedes the execution of the branch
destination instruction. In the above description, a delay slot indicates an instruction following an
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Section 7 Exception Handling
unconditional delayed branch instruction or an instruction following a conditional delayed branch
instruction whose branch condition is satisfied. If a branch does not occur in a conditional delayed
branch, the normal processing is executed.
(3)
Acceptance Priority and Test Priority
Acceptance priorities are determined for all exception requests. The priority of resets, general
exceptions, and interrupts are determined in this order: a reset is always accepted regardless of the
CPU status. Interrupts are accepted only when resets or general exceptions are not requested.
If multiple general exceptions occur simultaneously in the same instruction, the priority is
determined as follows.
1.
2.
3.
4.
5.
6.
7.
8.
A processing-completion type exception generated at the previous instruction*
A user break before instruction execution (re-execution type)
An exception related to an instruction fetch (CPU address error and MMU related exceptions:
re-execution type)
An exception caused by an instruction decode (General illegal instruction exceptions and slot
illegal instruction exceptions: re-execution type, unconditional trap: processing-completion
type)
An exception related to data access (CPU address error and MMU related exceptions: reexecution type)
Unconditional trap (processing-completion type)
A user break other than one before instruction execution (processing-completion type)
DMA address error (processing-completion type)
Note: * If a processing-completion type exception is accepted at an instruction, exception
processing starts before the next instruction is executed. This exception processing
executed before an exception generated at the next instruction is detected.
Only one exception is accepted at a time. Accepting multiple exceptions sequentially results in all
exception requests being processed.
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Section 7 Exception Handling
Table 7.1
Exception Event Vectors
Exception Current
Type
Instruction
Exception Event
Exception Process Vector
1
Priority* Order
at BL=1 Code
Vector
Offset
Power-on reset
1
1
Reset
H'000
—
Manual reset
1
2
Reset
H'020
—
Re-executed User break(before
instruction execution)
2
0
Ignored
H'1E0
H'00000100
CPU address error
4
(instruction access) *
2
1
Reset
H'0E0
H'00000100
TLB miss
4 5
(instruction access) * *
2
1-1
Reset
H'040
H'00000400
TLB invalid (instruction
4 5
access)* *
2
1-2
Reset
H'040
H'00000100
TLB protection violation
4 5
(instruction access)* *
2
1-3
Reset
H'0A0
H'00000100
Illegal general instruction 2
exception
2
Reset
H'180
H'00000100
Illegal slot
instruction exception
2
2
Reset
H'1A0
H'00000100
CPU address error
4
(data access)*
2
3
Reset
H'0E0/
H'100
H'00000100
TLB miss
4 5
(data access)* *
2
3-1
Reset
H'040/
H'060
H'00000400
Re-executed TLB invalid
4 5
(data access)* *
2
3-2
Reset
H'040/
H'060
H'00000100
TLB protection violation
4 5
(data access)* *
2
3-3
Reset
H'0A0/
H'0C0
H'00000100
Initial page write
4 5
(data access)* *
2
3-4
Reset
H'080
H'00000100
Unconditional trap
(TRAPA instruction)
2
4
Reset
H'160
H'00000100
User breakpoint (After
instruction execution,
address)
2
5
Ignored
H'1E0
H'00000100
Reset
Aborted
(asynchronous)
General
exception
events
(synchronous)
Completed
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Section 7 Exception Handling
Exception Current
Type
Instruction
Exception Event
Exception Process Vector
1
Priority* Order
at BL=1 Code
Vector
Offset
Completed
General
exception
events
(asynchronous)
User breakpoint
(Data break, I-BUS
break)
2
5
Ignored
H'1E0
H'00000100
DMA address error
2
6
Retained H'5C0
H'00000100
Completed
General
interrupt
requests
(asynchronous)
Interrupt requests
3
—*
2
3
Retained —*
H'00000600
Notes: 1. Priorities are indicated from high to low, 1 being the highest and 3 the lowest.
A reset has the highest priority. An interrupt is accepted only when general exceptions
are not requested.
2. For details on priorities in multiple interrupt sources, refer to section 8, Interrupt
Controller (INTC).
3. If an interrupt is accepted, the exception event register (EXPEVT) is not changed. The
interrupt source code is specified in the interrupt event registers (INTEVT and
INTEVT2). For details, refer to section 8, Interrupt Controller (INTC).
4. If one of these exceptions occurs in a specific part of the repeat loop, a specific code
and vector offset are specified.
5. These exception codes are valid when the MMU is used.
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Section 7 Exception Handling
7.3
Individual Exception Operations
This section describes the conditions for specific exception handling, and the processor operations.
This section describes resets and general exceptions. For interrupt operations, refer to section 8,
Interrupt Controller (INTC).
7.3.1
(1)
Resets
Power-On Reset
• Conditions
Power-on reset is request
• Operations
Set EXPEVT to H'000, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
(2)
Manual Reset
• Conditions
Manual reset is request
• Operations
Set EXPEVT to H'020, initialize the CPU and on-chip peripheral modules, and branch to the
reset vector H'A0000000. For details, refer to the register descriptions in the relevant sections.
7.3.2
(1)
General Exceptions
CPU address error
• Conditions
 Instruction is fetched from odd address (4n + 1, 4n + 3)
 Word data is accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword is accessed from addresses other than longword boundaries (4n + 1, 4n + 2,
4n + 3)
 The area ranging from H'80000000 to H'FFFFFFFF in virtual space is accessed in user
mode
• Types
Instruction synchronous, re-execution type
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Section 7 Exception Handling
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'0E0
An exception occurred during write: H'100
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA.
(2)
Illegal general instruction exception
• Conditions
 When undefined code not in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
Note: For details on undefined code, refer to table 2.12. When an undefined code other than
H'F000 to H'FFFF is decoded, operation cannot be guaranteed.
•
•
•
•
 When a privileged instruction not in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
Types
Instruction synchronous, re-execution type
Save address
An instruction address where an exception occurs
Exception code
H'180
Remarks
None
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Section 7 Exception Handling
(3)
Illegal slot instruction
• Conditions
 When undefined code in a delay slot is decoded
Delayed branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S
 When a privileged instruction in a delay slot is decoded in user mode
Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR
with LDC/STC are not privileged instructions.
 When an instruction that rewrites PC in a delay slot is decoded
Instructions that rewrite PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF,
BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR
• Types
Instruction synchronous, re-execution type
• Save address
A delayed branch instruction address
• Exception code
H'1A0
• Remarks
None
(4)
Unconditional trap
• Conditions
TRAPA instruction executed
• Types
Instruction synchronous, processing-completion type
• Save address
An address of an instruction following TRAPA
• Exception code
H'160
• Remarks
The exception is a processing-completion type, so an instruction after the TRAPA instruction
is saved to SPC. The 8-bit immediate value in the TRAPA instruction is set in TRA[9:2].
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Section 7 Exception Handling
(5)
User break point trap
• Conditions
When a break condition set in the user break controller is satisfied
• Types
Break (L bus) before instruction execution: Instruction synchronous, re-execution type
Operand break (L bus): Instruction synchronous, processing-completion type
Data break (L bus): Instruction asynchronous, processing-completion type
I bus break: Instruction asynchronous, processing-completion type
• Save address
Re-execution type: An address of the instruction where a break occurs (a delayed branch
instruction address if an instruction is assigned to a delay slot)
Processing-completion type: An address of the instruction following the instruction where a
break occurs (a delayed branch instruction destination address if an instruction is assigned to a
delay slot)
• Exception code
H'1E0
• Remarks
For details on user break controller, refer to section 33, User Break Controller (UBC).
(6)
DMA address error
• Conditions
 Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3)
 Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n +
3)
• Types
Instruction asynchronous, processing-completion type
• Save address
An address of the instruction following the instruction where a break occurs (a delayed branch
instruction destination address if an instruction is assigned to a delay slot)
• Exception code
H'5C0
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Section 7 Exception Handling
• Remarks
An exception occurs when a DMA transfer is executed while an exception instruction address
described above is specified in the DMAC. Since the DMA transfer is performed
asynchronously with the CPU instruction operation, an exception is also requested
asynchronously with the instruction execution. For details on DMAC, refer to section 10,
Direct Memory Access Controller (DMAC).
7.3.3
General Exceptions (MMU Exceptions)
When the address translation unit of the memory management unit (MMU) is valid, MMU
exceptions are checked after a CPU address error has been checked. Four types of MMU
exceptions are defined: TLB miss exception, TLB invalid exception, TLB protection exception,
initial page write exception. These exceptions are checked in this order.
A vector offset for a TLB miss exception is defined as H'00000400 to simplify exception source
determination. For details on MMU exception operations, refer to section 4, Memory Management
Unit (MMU).
(1)
TLB miss exception
• Conditions
Comparison of TLB addresses shows no address match.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'040
An exception occurred during write: H'060
• Remarks
• The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated. The vector address for TLB miss exception is VBR + H'0400. To speed up TLB miss
processing, the offset differs from other exceptions.
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Section 7 Exception Handling
(2)
TLB invalid exception
• Conditions
Comparison of TLB addresses shows address match but V = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'040
An exception occurred during write: H'060
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
(3)
TLB protection exception
• Conditions
When a hit access violates the TLB protection information (PR bits).
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
An exception occurred during read: H'0A0
An exception occurred during write: H'0C0
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
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Section 7 Exception Handling
(4)
Initial page write exception
• Conditions
A hit occurred to the TLB for a store access, but D = 0.
• Types
Instruction synchronous, re-execution type
• Save address
Instruction fetch: An instruction address to be fetched when an exception occurred
Data access: An instruction address where an exception occurs (a delayed branch instruction
address if an instruction is assigned to a delay slot)
• Exception code
H'080
• Remarks
The virtual address (32 bits) that caused the exception is set in TEA, and the MMU register is
updated.
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Section 7 Exception Handling
7.4
Exception Processing While DSP Extension Function is Valid
When the DSP extension function is valid (the DSP bit in SR is set to 1), some exception
processing acceptance conditions or exception processing may be changed.
7.4.1
Illegal Instruction Exception and Illegal Slot Instruction Exception
In the DSP mode, a DSP extension instruction can be executed. If a DSP extension instruction is
executed when the DSP bit in SR is cleared to 0 (in a mode other than the DSP mode), an illegal
instruction exception occurs.
In the DSP mode, STC and LDC instructions for the SR register can be executed even in user
mode. (Note, however, that only the RC[11:0], DMX, DMY, and RF[1:0] bits in the DSP
extension bits can be changed.)
7.4.2
CPU Address Error
In the DSP mode, a part of the space P2 (Uxy area: H'A5000000 to H'A5FFFFFF) can be accessed
in user mode and no CPU address error will occur even if the area is accessed.
7.4.3
Exception in Repeat Control Period
If an exception is requested or an exception is accepted during repeat control, the exception may
not be accepted correctly or a program execution may not be returned correctly from exception
processing that is different from the normal state. These restrictions may occur from repeat
detection instruction to repeat end instruction while the repeat counter is 1 or more. In this section,
this period is called the repeat control period.
The following shows program examples where the number of instructions in the repeat loop are 4
or more, 3, 2, and 1, respectively. In this section, a repeat detection instruction and its instruction
address are described as RptDtct. The first, second, and third instructions following the repeat
detection instruction are described as RptDtct1, RptDtct2, and RptDtct3. In addition, [A], [B],
[C1], and [C2] in the following examples indicate instructions where a restriction occurs. Table
7.2 summarizes the instruction positions and restriction types.
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Section 7 Exception Handling
Table 7.2
Instruction Positions and Restriction Types
Instruction
Position
Illegal
Instruction*2
1
SPC*
Interrupt,
Break*3
CPU Address
Error*4
[A]
[B]
Retained
[C1]
[C2]
Illegal
Added
Retained
Instruction/data
Added
Retained
Instruction/data
Notes: 1. A specific address is specified in the SPC if an exception occurs while SR.RC[11:0] ≥ 2.
2. There are a greater number of instructions that can be illegal instructions while
SR.RC[11:0] ≥ 1.
3. An interrupt, break or DMA address error request is retained while SR.RC[11:0] ≥1.
4. A specific exception code is specified while SR.RC[11:0] ≥1.
• Example 1: Repeat loop consisting of four or greater instructions
LDRS RptStart
; [A]
LDRE RptDtct + 4
SETRC #4
; [A]
instr0
; [A]
RptStart: instr1
RptDtct:
RptEnd:
; [A]
; [A][Repeat start instruction]
………
; [A]
………
; [A]
RptDtct
; [B] A repeat detection
instruction is an
instruction three
instructions before a
repeat end instruction
RptDtct1
; [C1]
RptDtct2
; [C2]
RptDtct3
; [C2][Repeat end instruction]
instrNext
; [A]
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Section 7 Exception Handling
• Example 2: Repeat loop consisting of three instructions
RptDtct:
LDRS
RptDtct + 4
; [A]
LDRE
RptDtct + 4
; [A]
SETRC #4
; [A]
RptDtct
; [B] A repeat detection
instruction is an
instruction prior to a
repeat start instruction
RptStart: RptDtct1
RptEnd:
; [C1][Repeat start instruction]
RptDtct2
; [C2]
RptDtct3
; [C2][Repeat end instruction]
instrNext
; [A]
• Example 3: Repeat loop consisting of two instructions
RptDtct:
LDRS
RptDtct + 6
; [A]
LDRE
RptDtct + 4
; [A]
SETRC #4
; [A]
RptDtct
; [B] A repeat detection
instruction is an
instruction prior to a
repeat start instruction
RptStart: RptDtct1
RptEnd:
; [C1][Repeat start instruction]
RptDtct2
; [C2][Repeat end instruction]
instrNext
; [A]
• Example 4: Repeat loop consisting of one instruction
RptDtct:
LDRS
RptDtct + 8
; [A]
LDRE
RptDtct + 4
; [A]
SETRC #4
; [A]
RptDtct
; [B] A repeat detection
instruction is an
instruction prior to a
repeat start instruction
RptDtct1
; [C1][Repeat start
instruction]== [Repeat end
instruction]
instrNext
; [A]
RptStart:
RptEnd:
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Section 7 Exception Handling
(1)
SPC Saved by an Exception in Repeat Control Period
If an exception is accepted in the repeat control period while the repeat counter (RC[11:0]) in the
SR register is two or greater, the program counter to be saved may not indicate the value to be
returned correctly. To execute the repeat control after returning from an exception processing, the
return address must indicate an instruction prior to a repeat detection instruction. Accordingly, if
an exception is accepted in repeat control period, an exception other than re-execution type
exception by a repeat detection instruction cannot return to the repeat control correctly.
Table 7.3
SPC Value When a Re-Execution Type Exception Occurs in Repeat Control
(SR.RC[11:0]≥2)
Instruction Where an
Exception Occurs
Number of Instructions in a Repeat Loop
1
2
3
4 or Greater
RptDtct
RptDtct
RptDtct
RptDtct
RptDtct
RptDtct1
RptDtct1
RptDtct1
RptDtct1
RptDtct1
RptDtct2

RptDtct1
RptDtct1
RS-4
RptDtct3


RptDtct1
RS-2
Note: The following labels are used here.
RptDtct: Repeat detection instruction address
RptDtct1: Instruction address immediately after the repeat detect instruction
RptDtct2: Second instruction address from the repeat detect instruction
RptDtct3: Third instruction address from the repeat detect instruction
RS:
Repeat start instruction address
If a re-execution type exception is accepted at an instruction in the hatched areas above, a
return address to be saved in the SPC is incorrect. If SR.RC[11:0] is 1 or 0, a correct return
address is saved in the SPC.
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Section 7 Exception Handling
(2)
Illegal Instruction Exception in Repeat Control Period
If one of the following instructions is executed at the address following RptDtct1, a general illegal
instruction exception occurs. For details on an address to be saved in the SPC, refer to SPC Saved
by an Exception in Repeat Control Period in section 7.4.3, Exception in Repeat Control Period.
• Branch instructions
BRA, BSR, BT, BF, BT/S, BF/S, BSRF, RTS, BRAF, RTE, JSR, JMP, TRAPA
• Repeat control instructions
SETRC, LDRS, LDRE
• Load instructions for SR, RS, and RE
LDC Rn,SR, LDC @Rn+,SR, LDC Rn,RE, LDC @Rn+,RE, LDC Rn,RS, LDC @Rn+, Rs
Note: An extension instruction of this LSI and is not disclosed to the user.
In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction.
(3)
An Exception Retained in Repeat Control Period
In the repeat control period, an interrupt or some exception will be retained to prevent an
exception acceptance at an instruction where returning from the exception cannot be performed
correctly. For details, refer to repeat loop program examples 1 to 4. In the examples, exceptions
generated at instructions indicated as [B], [C], ([C1], or [C2]), the following processing is
executed.
• Interrupt, DMA address error
An exception request is not accepted and retained at instructions [B] and [C]. If an instruction
indicates as [A] is executed at the next time, an exception request is accepted.* As shown in
examples 1 to 4, any interrupt or DMA address error cannot be accepted in a repeat loop
consisting of four instructions or less.
Note: An interrupt request or a DMA address error exception request is retained in the interrupt
controller (INTC) and the direct memory access controller (DMAC) until the CPU can
accept a request.
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Section 7 Exception Handling
• User break before instruction execution
A user break before instruction execution is accepted at instruction [B], and an address of
instruction [B] is saved in the SPC. This exception cannot be accepted at instruction [C] but
the exception request is retained until an instruction [A] or [B] is executed at the next time.
Then, the exception request is accepted before an instruction [A] or [B] is executed. In this
case, an address of instruction [A] or [B] is saved in the SPC.
• User break after instruction execution
A user break after instruction execution cannot be accepted at instructions [B] and [C] but the
exception request is retained until an instruction [A] or [B] is executed at the next time. Then,
the exception request is accepted before an instruction [A] or [B] is executed. In this case, an
address of instruction [A] or [B] is saved in the SPC.
Table 7.4
Exception Acceptance in the Repeat Loop
Exception Type
Instruction [B]
Instruction [C]
Interrupt
Not accepted
Not accepted
DMA address error
Not accepted
Not accepted
User break before instruction execution
Accepted
Not accepted
User break after instruction execution
Not accepted
Not accepted
(4)
CPU Address Error in Repeat Control Period
If a CPU address error occurs in the repeat control period, the exception is accepted but an
exception code (H'070) indicating the repeat loop period is specified in the EXPEVT. If a CPU
address error occurs in instructions following a repeat detection instruction to repeat end
instruction, an exception code for instruction access or data access is specified in the EXPEVT.
The SPC is saved according to the description, SPC Saved by an Exception in Repeat Control
Period in section 7.4.3, Exception in Repeat Control Period.
After the CPU address error exception processing, the repeat control cannot be returned correctly.
To execute a repeat loop correctly, care must be taken not to generate a CPU address error in the
repeat control period.
Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
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Section 7 Exception Handling
Table 7.5
Instruction Where a Specific Exception Occurs When a Memory Access
Exception Occurs in Repeat Control (SR.RC[11:0]≥1)
Number of Instructions in a Repeat Loop
Instruction Where an
Exception Occurs
1
2
3
4 or Greater
RptDtct




RptDtct1
Instruction/data
access
Instruction/data
access
Instruction/data
access
Instruction/data
access
RptDtct2

Instruction/data
access
Instruction/data
access
Instruction/data
access
RptDtct3


Instruction/data
access
Instruction/data
access
Note: The following labels are used here.
RptDtct: Repeat detection instruction address
RptDtct1: Instruction address immediately after the repeat detect instruction
RptDtct2: Second instruction address from the repeat detect instruction
RptDtct3: Third instruction address from the repeat detect instruction
(5)
MMU Exception in Repeat Control Period
If an MMU exception occurs in the repeat control period, a specific exception code is generated as
well as a CPU address error. For a TLB miss exception, TLB invalid exception, and initial page
write exception, an exception code (H'070) indicating the repeat loop period is specified in the
EXPEVT. For a TLB protection exception, an exception code (H'0D0) is specified in the
EXPEVT. In a TLB miss exception, vector offset is specified as H'00000100.
An instruction where an exception occurs and the SPC value to be saved are the same as those for
the CPU address error.
After this exception processing, the repeat control cannot be returned correctly. To execute a
repeat loop correctly, care must be taken not to generate an MMU related exception in the repeat
control period.
Note: In a repeat loop consisting of one to three instructions, some restrictions apply to repeat
detection instructions and all the remaining instructions. In a repeat loop consisting of four
or more instructions, restrictions apply to only the three instructions that include a repeat
end instruction. The restriction occurs when SR.RC[11:0] ≥ 1.
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Section 7 Exception Handling
7.5
1.
2.
3.
Usage Notes
An instruction assigned at a delay slot of the RTE instruction is executed after the contents of
the SSR is restored into the SR. An acceptance of an exception related to instruction access is
determined according to the SR before restore. An acceptance of other exceptions is
determined by processing mode of the SR after restore, and BL bit value. A processingcompletion type exception is accepted before an instruction at the RTE branch destination
address is executed. However, note that the correct operation cannot be guaranteed if a reexecution type exception occurs.
In an instruction assigned at a delay slot of the RTE instruction, a user break cannot be
accepted.
If the MD and BL bits of the SR register are changed by the LDC instruction, an exception is
accepted according to the changed SR value from the next instruction.* A processingcompletion type exception is accepted before the next instruction is executed. An interrupt
and DMA address error in re-execution type exceptions are accepted before the next
instruction is executed.
Note: * If an LDC instruction is executed for the SR, the following instructions are re-fetched
and an instruction fetch exception is accepted according to the modified SR value.
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Section 7 Exception Handling
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Section 8
Section 8
Interrupt Controller (INTC)
Interrupt Controller (INTC)
The interrupt controller (INTC) determines the priority of interrupt sources and controls interrupt
requests to the CPU. The INTC registers set the priority of each interrupt, allowing the user to
process interrupt requests according to the user-set priority.
8.1
Features
• 16 levels of interrupt priority can be set
By setting the interrupt-priority registers, the priorities of on-chip peripheral modules, and IRQ
and PINT interrupts can be selected from 16 levels for individual request sources.
• NMI noise canceller function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt
exception service routine, the pin state can be checked, enabling it to be used as a noise
canceller.
• IRQ interrupts can be set
Detection of low level, high level, rising edge, or falling edge
• Interrupt request signal can be externally output (IRQOUT pin)
By notifying the external bus master that the external interrupt and on-chip peripheral module
interrupt requests have been generated, the bus mastership can be requested.
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Section 8
Interrupt Controller (INTC)
Figure 8.1 shows a block diagram of the interrupt controller.
IRLQOUT
NMI
IRQ5 to IRQ0
IRL3 to IRL0
PINT5 to PINT0
DMAC
SCIF
SIOF
TMU
TPU
WDT
ADC
USBF
USBH
RTC
SIM
LCDC
PCC
MMC
I2C
CMT
AFEIF
SSL
SDHI
REF
6
4
16
Input/output
control
Comparator
(Interrupt request)
Interrupt
request
SR
I3 I2 I1 I0
CPU
Priority
identifier
PINTER
IPR
ICR
Internal bus
IRR0
Bus
interface
[Legend]
ICR:
IPR:
IRR:
PINTER:
REF:
INTC
Interrupt control register
Interrupt priority register
Interrupt request register
PINT interrupt enable register
Refresh request in bus state controller
Figure 8.1
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REJ09B0033-0300
Block Diagram of INTC
Section 8
8.2
Interrupt Controller (INTC)
Input/Output Pins
Table 8.1 shows the INTC pin configuration.
Table 8.1
Pin Configuration
Name
Abbreviation
I/O
Description
Nonmaskable interrupt input pin
NMI
Input
Input of interrupt request signal, not
maskable by the interrupt mask bits
in SR
Interrupt input pins
IRQ5 to IRQ0
Input
Input of interrupt request signals
Input of port interrupt signals
IRL3 to IRL0*
1
Port interrupt input pins
PINT15 to
PINT0
Input
Bus request signal pin
IRQOUT*2
Output Bus request signal for an interrupt
Notes: 1. IRL3 to IRL0 and IRQ3 to IRQ0 cannot be used simultaneously because these pins are
multiplexed.
2. When the NMI or H-UDI interrupt requests are generated and the response time of CPU
is short, this pin may not be asserted.
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Section 8
8.3
Interrupt Controller (INTC)
Register Descriptions
The INTC has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and access size of these registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interrupt control register 0 (ICR0)
Interrupt control register 1 (ICR1)
Interrupt control register 2 (ICR2)
PINT interrupt enable register (PINTER)
Interrupt priority register A (IPRA)
Interrupt priority register B (IPRB)
Interrupt priority register C (IPRC)
Interrupt priority register D (IPRD)
Interrupt priority register E (IPRE)
Interrupt priority register F (IPRF)
Interrupt priority register G (IPRG)
Interrupt priority register H (IPRH)
Interrupt priority register I (IPRI)
Interrupt priority register J (IPRJ)
Interrupt request register 0 (IRR0)
Interrupt request register 1 (IRR1)
Interrupt request register 2 (IRR2)
Interrupt request register 3 (IRR3)
Interrupt request register 4 (IRR4)
Interrupt request register 5 (IRR5)
Interrupt request register 6 (IRR6)
Interrupt request register 7 (IRR7)
Interrupt request register 8 (IRR8)
Interrupt request register 9 (IRR9)
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Section 8
8.3.1
Interrupt Controller (INTC)
Interrupt Priority Registers A to J (IPRA to IPRJ)
IPRA to IPRJ are 16-bit readable/writable registers in which priority levels from 0 to 15 are set for
on-chip peripheral module and IRQ interrupts.
Bit
Bit Name
Initial Value
R/W
Description
15
IPR15
0
R/W
14
IPR14
0
R/W
These bits set the priority level for each interrupt
source in 4-bit units. For details, see table 8.2.
13
IPR13
0
R/W
12
IPR12
0
R/W
11
IPR11
0
R/W
10
IPR10
0
R/W
9
IPR9
0
R/W
8
IPR8
0
R/W
7
IPR7
0
R/W
6
IPR6
0
R/W
5
IPR5
0
R/W
4
IPR4
0
R/W
3
IPR3
0
R/W
2
IPR2
0
R/W
1
IPR1
0
R/W
0
IPR0
0
R/W
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Section 8
Table 8.2
Interrupt Controller (INTC)
Interrupt Sources and IPRA to IPRJ
Register
Bits 15 to 12
IPRA
TMU0
TMU1
TMU2
RTC
IPRB
WDT
REF
SIM
Reserved*
IPRC
IRQ3
IRQ2
IRQ1
IRQ0
IPRD
Reserved*
TMU (TMU_SUNI) IRQ5
IRQ4
IPRE
DMAC (1)
Reserved*
LCDC
SSL
IPRF
ADC
DMAC (2)
USBF
CMT
IPRG
SCIF0
SCIF1
Reserved*
Reserved*
IPRH
PINTA
PINTB
TPU
I 2C
IPRI
SIOF0
SIOF1
MMC
PCC
IPRJ
Reserved*
USBH
SDHI
AFEIF
Note:
*
Bits 11 to 8
Bits 7 to 4
Bits 3 to 0
Reserved. Always read as 0. The write value should always be 0. The SSL and SDHIrelated bits are effective only for the models that include them. Reserved bits apply if
they are not included.
As shown in table 8.2, on-chip peripheral module or IRQ interrupts are assigned to four 4-bit
groups in each register. These 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0)
are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is
requested); H'F means priority level 15 (the highest level).
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Section 8
8.3.2
Interrupt Controller (INTC)
Interrupt Control Register 0 (ICR0)
ICR0 is a register that sets the input signal detection mode of the external interrupt input pin NMI,
and indicates the input signal level at the NMI pin.
Bit
Bit Name
Initial
Value
R/W
Description
15
NMIL
0/1*
R
NMI Input Level
Sets the level of the signal input at the NMI pin. This bit
can be read from to determine the NMI pin level. This bit
cannot be modified.
0: NMI input level is low
1: NMI input level is high
14 to 9 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
8
NMIE
0
R/W
NMI Edge Select
Selects whether the falling or rising edge of the interrupt
request signal at the NMI pin is detected.
0: Interrupt request is detected on falling edge of NMI
input
1: Interrupt request is detected on rising edge of NMI
input
7 to 0
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note:
*
The initial value is 1 when NMI input is high, 0 when NMI input is low.
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Section 8
8.3.3
Interrupt Controller (INTC)
Interrupt Control Register 1 (ICR1)
ICR1 is a 16-bit register that specifies the detection mode for external interrupt input pins IRQ5 to
IRQ0 individually: rising edge, falling edge, high level, or low level.
Bit
Bit Name
Initial
Value
R/W
Description
15
MAI
0
R/W
All Interrupt Mask
When this bit is set to 1, all interrupt requests are masked
while low level is input to the NMI pin. The NMI interrupt
is masked in standby mode.
0: When the NMI pin is low, all interrupt requests are not
masked
1: When the NMI pin is low, all interrupt requests are
masked
14
IRQLVL
1
R/W
Interrupt Request Level Detection
Enables or disables the use of pins IRQ3 to IRQ0 as four
independent interrupt pins. The IRQ4 and IRQ5 are not
affected.
0: Use of pins IRQ3 to IRQ0 as four independent interrupt
pins enabled
1: Use of pins IRL3 to IRL0 as encoded 15 level interrupt
pins
13
BLMSK
0
R/W
BL Bit Mask
When the BL bit in the SR register is set to 1, specifies
whether the NMI interrupt is masked.
0: When the BL bit is set to 1, the NMI interrupt is masked
1: The NMI interrupt is accepted regardless of the BL bit
setting
12
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
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Section 8
Interrupt Controller (INTC)
Bit
Bit Name
Initial
Value
R/W
Description
11
IRQ51S
0
R/W
IRQn Sense Select
10
IRQ50S
0
R/W
9
IRQ41S
0
R/W
8
IRQ40S
0
R/W
These bits select whether interrupt request signals
corresponding to pins IRQ5 to IRQ0 are detected by a
rising edge, falling edge, high level, or low level.
7
IRQ31S
0
R/W
6
IRQ30S
0
R/W
5
IRQ21S
0
R/W
4
IRQ20S
0
R/W
3
IRQ11S
0
R/W
2
IRQ10S
0
R/W
1
IRQ01S
0
R/W
0
IRQ00S
0
R/W
Bit 2n + 1 Bit 2n
IRQn1S
IRQn0S
0
0
Interrupt request is detected on
falling edge of IRQn input
0
1
Interrupt request is detected on
rising edge of IRQn input
1
0
Interrupt request is detected on
low level of IRQn input
1
1
Interrupt request is detected on
high level of IRQn input
[Legend] n= 0 to 5
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Section 8
8.3.4
Interrupt Controller (INTC)
Interrupt Request Register 0 (IRR0)
IRR0 is an 8-bit register that indicates interrupt requests from the TMU and IRQ0 to IRQ5.
Bit
Bit Name
Initial
Value
R/W
7

0
R
Description
Reserved
This bit is always read as 0. The write value should
always be 0.
6
TMU_
SUNIR
0
R/W
TMU_SUNI Interrupt Request
Indicates whether the TMU_SUNI (TMU) interrupt request
is generated.
0: TMU_SUNI interrupt request is not generated
1: TMU_SUNI interrupt request is generated
5
IRQ5R
0
R/W
IRQn Interrupt Request
4
IRQ4R
0
R/W
3
IRQ3R
0
R/W
2
IRQ2R
0
R/W
1
IRQ1R
0
R/W
0
IRQ0R
0
R/W
Indicates whether there is interrupt request input to the
IRQn pin. When edge-detection mode is set for IRQn, an
interrupt request is cleared by writing 0 to the IRQnR bit
after reading IRQnR = 1.
When level-detection mode is set for IRQn, these bits
indicate whether an interrupt request is input. The
interrupt request is set/cleared by only 1/0 input to the
IRQn pin.
IRQnR
0: No interrupt request input to IRQn pin
1: Interrupt request input to IRQn pin
[Legend] n = 0 to 5
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Section 8
8.3.5
Interrupt Controller (INTC)
Interrupt Request Register 1 (IRR1)
IRR1 is an 8-bit register that indicates whether interrupt requests from the DMAC are generated.
This register is initialized to H'00 by a power-on reset or manual reset, but is not initialized in
standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7 to 4

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
3
DEI3R
0
R/W
DEI3 Interrupt Request
Indicates whether the DEI3 (DMAC) interrupt is
generated.
0: DEI3 interrupt request is not generated
1: DEI3 interrupt request is generated
2
DEI2R
0
R/W
DEI2 Interrupt Request
Indicates whether the DEI2 (DMAC) interrupt
request is generated.
0: DEI2 interrupt request is not generated
1: DEI2 interrupt request is generated
1
DEI1R
0
R/W
DEI1 Interrupt Request
Indicates whether the DEI1 (DMAC) interrupt
request is generated.
0: DEI1 interrupt request is not generated
1: DEI1 interrupt request is generated
0
DEI0R
0
R/W
DEI0 Interrupt Request
Indicates whether the DEI0 (DMAC) interrupt
request is generated.
0: DEI0 interrupt request is not generated
1: DEI0 interrupt request is generated
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Section 8
8.3.6
Interrupt Controller (INTC)
Interrupt Request Register 2 (IRR2)
IRR2 is an 8-bit register that indicates whether interrupt requests from the SSL and LCDC are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Note: On the models not having the SSL, the SSL-related bits are reserved. The write value
should always be 0.
Bit
Bit Name
Initial Value
R/W
Description
7 to 5

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
4
SSLIR
0
R/W
SSLI Interrupt Request
Indicates whether the SSLI (SSL) interrupt
request is generated.
0: SSLI interrupt request is not generated
1: SSLI interrupt request is generated
Note: On the models not having the SSL, this bit
is reserved and always read as 0. The write
value should always be 0.
3 to 1

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
LCDIR
0
R/W
LCDCI Interrupt Request
Indicates whether the LCDCI (LCDC) interrupt
request is generated.
0: LCDCI interrupt request is not generated
1: LCDCI interrupt request is generated
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Section 8
8.3.7
Interrupt Controller (INTC)
Interrupt Request Register 3 (IRR3)
IRR3 is an 8-bit register that indicates whether interrupt requests from the RTC and SIM are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
TENDIR
0
R/W
TENDI Interrupt Request
Indicates whether the TENDI (SIM) interrupt is
generated.
0: TENDI interrupt request is not generated
1: TENDI interrupt request is generated
6
TXIR
0
R/W
TXI Interrupt Request
Indicates whether the TXI (SIM) interrupt request
is generated.
0: TXI interrupt request is not generated
1: TXI interrupt request is generated
5
RXIR
0
R/W
RXI Interrupt Request
Indicates whether the RXI (SIM) interrupt request
is generated.
0: RXI interrupt request is not generated
1: RXI interrupt request is generated
4
ERIR
0
R/W
ERI Interrupt Request
Indicates whether the ERI (SIM) interrupt request
is generated.
0: ERI interrupt request is not generated
1: ERI interrupt request is generated
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
2
CUIR
0
R/W
CUI Interrupt Request
Indicates whether the CUI (RTC) interrupt request
is generated.
0: CUI interrupt request is not generated
1: CUI interrupt request is generated
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Section 8
Interrupt Controller (INTC)
Bit
Bit Name
Initial Value
R/W
Description
1
PRIR
0
R/W
PRI Interrupt Request
Indicates whether the PRI (RTC) interrupt request
is generated.
0: PRI interrupt request is not generated
1: PRI interrupt request is generated
0
ATIR
0
R/W
ATI Interrupt Request
Indicates whether the ATI (RTC) interrupt request
is generated.
0: ATI interrupt request is not generated
1: ATI interrupt request is generated
8.3.8
Interrupt Request Register 4 (IRR4)
IRR4 is an 8-bit register that indicates whether interrupt requests from the REF, WDT, and TMU
are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7

0
R
Reserved
This bit always read as 0. The write value should
always be 0.
6
TUNI2R
0
R/W
TUNI2 Interrupt Request
Indicates whether the TUNI2 (TMU) interrupt
request is generated.
0: TUNI2 interrupt request is not generated
1: TUNI2 interrupt request is generated
5
TUNI1R
0
R/W
TUNI1Interrupt Request
Indicates whether the TUNI1 (TMU) interrupt
request is generated.
0: TUNI1 interrupt request is not generated
1: TUNI1 interrupt request is generated
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Section 8
Bit
Bit Name
Initial Value
R/W
Description
4
TUNI0R
0
R/W
TUNI0 Interrupt Request
Interrupt Controller (INTC)
Indicates whether the TUNI0 (TMU) interrupt
request is generated.
0: TUNI0 interrupt request is not generated
1: TUNI0 interrupt request is generated
3
ITIR
0
R/W
ITI Interrupt Request
Indicates whether the ITI (WDT) interrupt request
is generated.
0: ITI interrupt request is not generated
1: ITI interrupt request is generated
2, 1

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
RCMIR
0
R/W
RCMI Interrupt Request
Indicates whether the RCMI (REF) interrupt
request is generated.
0: RCMI interrupt request is not generated
1: RCMI interrupt request is generated
8.3.9
Interrupt Request Register 5 (IRR5)
IRR5 is an 8-bit register that indicates whether interrupt requests from the SCIF0, SCIF1, DMAC,
and ADC are generated. This register is initialized to H'00 by a power-on reset or manual reset,
but is not initialized in standby mode.
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Section 8
Interrupt Controller (INTC)
Bit
Bit Name
Initial Value
R/W
Description
7
ADCIR
0
R/W
ADCI Interrupt Request
Indicates whether the ADCI (ADC) interrupt
request is generated.
0: ADCI interrupt request is not generated
1: ADCI interrupt request is generated
6

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
5
DEI5R
0
R/W
DEI5 Interrupt Request
Indicates whether the DEI5 (DMAC) interrupt
request is generated.
0: DEI5 interrupt request is not generated
1: DEI5 interrupt request is generated
4
DEI4R
0
R/W
DEI4 Interrupt Request
Indicates whether the DEI4 (DMAC) interrupt
request is generated.
0: DEI4 interrupt request is not generated
1: DEI4 interrupt request is generated
3, 2

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
SCIF1IR
0
R/W
SCIF1I Interrupt Request
Indicates whether the SCIF1I (SCIF1) interrupt
request is generated.
0: SCIF1I interrupt request is not generated
1: SCIF1I interrupt request is generated
0
SCIF0IR
0
R/W
SCIF0I Interrupt Request
Indicates whether the SCIF0I (SCIF0) interrupt
request is generated.
0: SCIF0I interrupt request is not generated
1: SCIF0I interrupt request is generated
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Section 8
8.3.10
Interrupt Controller (INTC)
Interrupt Request Register 6 (IRR6)
IRR6 is an 8-bit register that indicates whether interrupt requests from the PINT, SIOF0, and
SIOF1 are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is
not initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7, 6

All 0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
5
SIOF1IR
0
R/W
SIOF1I Interrupt Request
Indicates whether the SIOF1I (SIOF1) interrupt
request is generated.
0: SIOF1I interrupt request is not generated
1: SIOF1I interrupt request is generated
4
SIOF0IR
0
R/W
SIOF0I Interrupt Request
Indicates whether the SIOF0I (SIOF0) interrupt
request is generated.
0: SIOF0I interrupt request is not generated
1: SIOF0I interrupt request is generated
3, 2

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
1
PINTBR
0
R/W
PINTB Interrupt Request
Indicates whether the PINTB (PINT) interrupt
request is generated.
0: PINTB interrupt request is not generated
1: PINTB interrupt request is generated
0
PINTAR
0
R/W
PINTA Interrupt Request
Indicates whether the PINTA (PINT) interrupt
request is generated.
0: PINTA interrupt request is not generated
1: PINTA interrupt request is generated
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Section 8
8.3.11
Interrupt Controller (INTC)
Interrupt Request Register 7 (IRR7)
IRR7 is an 8-bit register that indicates whether interrupt requests from the TPU and IIC are
generated. This register is initialized to H'00 by a power-on reset or manual reset, but is not
initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7 to 5

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
4
IICIR
0
R/W
IICI Interrupt Request
Indicates whether the IICI (IIC) interrupt request
is generated.
0: IICI interrupt request is not generated
1: IICI interrupt request is generated
3
TPI3R
0
R/W
TPI3 Interrupt Request
Indicates whether the TPI3 (TPU) interrupt
request is generated.
0: TPI3 interrupt request is not generated
1: TPI3 interrupt request is generated
2
TPI2R
0
R/W
TPI2 Interrupt Request
Indicates whether the TPI2 (TPU) interrupt
request is generated.
0: TPI2 interrupt request is not generated
1: TPI2 interrupt request is generated
1
TPI1R
0
R/W
TPI1 Interrupt Request
Indicates whether the TPI1 (TPU) interrupt
request is generated.
0: TPI1 interrupt request is not generated
1: TPI1 interrupt request is generated
0
TPI0R
0
R/W
TPI0 Interrupt Request
Indicates whether the TPI0 (TPU) interrupt
request is generated.
0: TPI0 interrupt request is not generated
1: TPI0 interrupt request is generated
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Section 8
8.3.12
Interrupt Controller (INTC)
Interrupt Request Register 8 (IRR8)
IRR8 is an 8-bit register that indicates whether interrupt requests from the SDHI, MMC, and
AFEIF are generated. This register is initialized to H'00 by a power-on reset or manual reset, but is
not initialized in standby mode.
Note: Note: On the models not having the SDHI, the SDHI-related bits are reserved. The write
value should always be 0.
Bit
Bit Name
Initial Value
R/W
7
MMCI3R
0
R/W
Description
MMCI3 Interrupt Request
Indicates whether the MMCI3 (MMC) interrupt
request is generated.
0: MMCI3 interrupt request is not generated
1: MMCI3 interrupt request is generated
6
MMCI2R
0
R/W
MMCI2 Interrupt Request
Indicates whether the MMCI2 (MMC) interrupt
request is generated.
0: MMCI2 interrupt request is not generated
1: MMCI2 interrupt request is generated
5
MMCI1R
0
R/W
MMCI1 Interrupt Request
Indicates whether the MMCI1 (MMC) interrupt
request is generated.
0: MMCI1 interrupt request is not generated
1: MMCI1 interrupt request is generated
4
MMCI0R
0
R/W
MMCI0 Interrupt Request
Indicates whether the MMCI0 (MMC) interrupt
request is generated.
0: MMCI0 interrupt request is not generated
1: MMCI0 interrupt request is generated
3
AFECIR
0
R/W
AFECI Interrupt Request
Indicates whether the AFECI (AFEIF) interrupt
request is generated.
0: AFECI interrupt request is not generated
1: AFECI interrupt request is generated
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Section 8
Interrupt Controller (INTC)
Bit
Bit Name
Initial Value
R/W
Description
2, 1

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
SDIR
0
R/W
SDI Interrupt Request
Indicates whether the SDI (SDHI) interrupt
request is generated.
0: SDI interrupt request is not generated
1: SDI interrupt request is generated
Note: On the models not having the SDHI, this bit
is reserved and always read as 0. The write
value should always be 0.
8.3.13
Interrupt Request Register 9 (IRR9)
IRR9 is an 8-bit register that indicates whether interrupt requests from the PCC, USBH, USBF,
and CMT are generated. This register is initialized to H'00 by a power-on reset or manual reset,
but is not initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
PCCIR
0
R/W
PCCI Interrupt Request
Indicates whether the PCCI (PCC) interrupt
request is generated.
0: PCCI interrupt request is not generated
1: PCCI interrupt request is generated
6
USBHIR
0
R
USBHI Interrupt Request
Indicates whether the USBHI (USBH) interrupt
request is generated.
0: USBHI interrupt request is not generated
1: USBHI interrupt request is generated
5

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 262 of 1458
REJ09B0033-0300
Section 8
Bit
Bit Name
Initial Value
R/W
Description
4
CMIR
0
R/W
CMI Interrupt Request
Interrupt Controller (INTC)
Indicates whether the CMI (CMT) interrupt
request is generated.
0: CMI interrupt request is not generated
1: CMI interrupt request is generated
3

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
2
USBFI1R
0
R
USBFI1 Interrupt Request
Indicates whether the USBFI1 (USBF) interrupt
request is generated.
0: USBFI1interrupt request is not generated
1: USBFI1 interrupt request is generated
1
USBFI0R
0
R
USBFI0 Interrupt Request
Indicates whether the USBFI0 (USBF) interrupt
request is generated.
0: USBFI0 interrupt request is not generated
1: USBFI0 interrupt request is generated
0

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
Rev. 3.00 Jan. 18, 2008 Page 263 of 1458
REJ09B0033-0300
Section 8
8.3.14
Interrupt Controller (INTC)
PINT Interrupt Enable Register (PINTER)
PINTER is a 16-bit register which enables interrupt requests input to the external interrupt input
pins PINT0 to PINT15. This register is initialized to H'0000 by a power-on reset or manual reset,
but is not initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
15
PINT15E
0
R/W
PINTn Interrupt Enable
14
PINT14E
0
R/W
13
PINT13E
0
R/W
Select whether the interrupt requests input to the
pins PINT15 to PINT0 is enabled.
12
PINT12E
0
R/W
0: Disable PINTn input interrupt requests
11
PINT11E
0
R/W
1: Enable PINTn input interrupt requests
10
PINT10E
0
R/W
n = 0 to 15
9
PINT9E
0
R/W
8
PINT8E
0
R/W
7
PINT7E
0
R/W
6
PINT6E
0
R/W
5
PINT5E
0
R/W
4
PINT4E
0
R/W
3
PINT3E
0
R/W
2
PINT2E
0
R/W
1
PINT1E
0
R/W
0
PINT0E
0
R/W
Rev. 3.00 Jan. 18, 2008 Page 264 of 1458
REJ09B0033-0300
Section 8
8.3.15
Interrupt Controller (INTC)
Interrupt Control Register 2 (ICR2)
INCR2 is a 16-bit register which specifies low or high detection mode to the external interrupt
input pins PINT0 to PINT15 individually. This register is initialized to H'0000 by a power-on reset
or manual reset, but is not initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
15
PINT15S
0
R/W
PINTn Sense Select
14
PINT14S
0
R/W
13
PINT13S
0
R/W
12
PINT12S
0
R/W
Selects whether to detect an interrupt request
signal for the pins PINT15 to PINT0 by a highlevel or low-level.
11
PINT11S
0
R/W
10
PINT10S
0
R/W
9
PINT9S
0
R/W
8
PINT8S
0
R/W
7
PINT7S
0
R/W
6
PINT6S
0
R/W
5
PINT5S
0
R/W
4
PINT4S
0
R/W
3
PINT3S
0
R/W
2
PINT2S
0
R/W
1
PINT1S
0
R/W
0
PINT0S
0
R/W
0: Detects interrupt request by PINTn input low
1: Detects interrupt request by PINTn input high
n = 0 to 15
Rev. 3.00 Jan. 18, 2008 Page 265 of 1458
REJ09B0033-0300
Section 8
8.4
Interrupt Controller (INTC)
Interrupt Sources
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. Each
interrupt has a priority level (0 to 16), with 1 the lowest and 16 the highest. Priority level 0 masks
an interrupt, so the interrupt request is ignored.
8.4.1
NMI Interrupt
The NMI interrupt has the highest priority level of 16. When the BLMSK bit in the interrupt
control register 1 (ICR1) is 1 or the BL bit in the status register (SR) is 0, NMI interrupts are
accepted if the MAI bit in ICR1 is 0. NMI interrupts are edge-detected. In sleep or standby mode,
the interrupt is accepted regardless of the BL setting. The NMI edge select bit (NMIE) in the
interrupt control register 0 (ICR0) is used to select either rising or falling edge detection.
When using edge-input detection for NMI interrupts, a pulse width of at least two Pφ cycles
(peripheral clock) is necessary. NMI interrupt exception handling does not affect the interrupt
mask bits (I3 to I0) in the status register (SR). When the BL bit is 1, only an NMI interrupt is
accepted if the BLMSK bit in ICR1 is 1.
It is possible to wake the chip up from sleep mode or standby mode with an NMI interrupt.
8.4.2
IRQ Interrupts
IRQ interrupts are input by level or edge from pins IRQ0 to IRQ5. The priority level can be set by
interrupt priority registers C and D (IPRC and IPRD) in a range from 0 to 15.
When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1
from the corresponding bit in IRR0, then write 0 to the bit.
When ICR1 is rewritten, IRQ interrupts may be mistakenly detected, depending on the IRQ pin
states. To prevent this, rewrite the register while interrupts are masked, then release the mask after
clearing the illegal interrupt by reading the interrupt request register 0 (IRR0) and writing 0 to
IRR0.
Edge input interrupt detection requires input of a pulse width of more than two cycles on a Pφ
clock basis.
When using level-sensing for IRQ interrupts, the pin levels must be retained until the CPU
samples the pins. Therefore, the interrupt source must be cleared by the interrupt handler.
Rev. 3.00 Jan. 18, 2008 Page 266 of 1458
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Section 8
Interrupt Controller (INTC)
The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRQ interrupt
handling. IRQ interrupts specified for edge detection can be used to recover from a standby state
when the corresponding interrupt level is higher than that set in the I3 to I0 bits of the SR register.
(However, when RTC is used, recovering from standby by using the clock for RTC is enabled.)
8.4.3
IRL interrupts
IRL interrupts are input by pins IRL3 to IRL0 as level. The priority level is the higher level that is
indicated by IRL3 to IRL0 pins. When the values of IRL3 to IRL0 pins are 0 (B'0000), it indicates
the highest level interrupt request (interrupt priority level 15). When the values of the pins are 15
(B'1111), no interrupt is requested (interrupt priority level 0). Figure 8.2 shows an example of
connection for IRL interrupt.
IRL interrupts are included with noise canceller function and detected when the sampled levels of
each peripheral module clock keep same value for 2 cycles. This prevents sampling error level in
IRL pin changing.
IRL interrupts priority level should be kept until interrupt is accepted and its handling is started.
However, changing to higher level is enabled.
The interrupt mask bits I3 to I0 in the status register (SR) are not affected by the IRL interrupt
handling.
SH7720 / SH7721 Group
Priority
encoder
Interrupt
request
4
IRL3 to IRL0
IRL3 to IRL0
Figure 8.2
Example of IRL Interrupt Connection
Rev. 3.00 Jan. 18, 2008 Page 267 of 1458
REJ09B0033-0300
Section 8
8.4.4
Interrupt Controller (INTC)
PINT Interrupts
PINT interrupts are input by level from pins PINT0 to PINT15. The priority level of PINT0 to
PINT7 (PINTA) and PINT8 to PINT15 (PINTB) can be set by the interrupt priority level register
H (IPRH) in a range from 0 to 15. The PINT interrupt level should be retained until the interrupt
processing starts after an interrupt request has been accepted.
The interrupt mask bits I3 to I0 in the status register (SR) are not affected by the PIN interrupt
processing routine.
While an RTC clock is supplied, recovery from a standby state on a PINT interrupt is possible if
the interrupt level is higher than that set in the I3 to I0 bits of the SR register.
8.4.5
On-Chip Peripheral Module Interrupts
On-chip peripheral module interrupts are generated by the following modules:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
DMA controller (DMAC)
I2C bus interface (IIC)
Smart card interface (SIM)
Compare match timer (CMT)
Timer unit (TMU)
Timer pulse unit (TPU)
Watchdog timer (WDT)
User debugging interface (H-UDI)
LCD controller (LCDC)
Secure sockets layer (SSL)
Analog front end interface (AFEIF)
USB function controller (USBF)
USB host controller (USBH)
Bus state controller (BSC)
Serial I/O with FIFO 0 (SIOF0)
Serial I/O with FIFO 1 (SIOF1)
Serial communication interface with FIFO 0 (SCIF0)
Serial communication interface with FIFO 1 (SCIF1)
MultiMediaCard interface (MMC)
SD host interface (SDHI)
Rev. 3.00 Jan. 18, 2008 Page 268 of 1458
REJ09B0033-0300
Section 8
Interrupt Controller (INTC)
• Realtime clock (RTC)
• A/D converter (ADC)
• PC card controller (PCC)
Not every interrupt source is assigned a different interrupt vector. Sources are reflected in the
interrupt event registers (INTEVT and INTEVT2). It is easy to identify sources by using the value
of INTEVT or INTEVT2 as a branch offset.
A priority level (from 0 to 15) can be set for each module except H-UDI by writing to the interrupt
priority registers A, B, and E to J (IPRA, IPRB, and IPRE to IPRJ). The priority level of the HUDI interrupt is 15 (fixed).
The interrupt mask bits (I3 to I0) in the status register are not affected by on-chip peripheral
module interrupt handling.
8.4.6
Interrupt Exception Handling and Priority
There are four types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The
priority of each interrupt source is set within priority levels 0 to 16; level 16 is the highest and
level 1 is the lowest. When the priority is set to level 0, that interrupt is masked and the interrupt
request is ignored.
Tables 8.3 and 8.4 list the interrupt sources, the codes for the interrupt event registers (INTEVT
and INTEVT2), and the interrupt priority.
Each interrupt source is assigned a unique code by INTEVT and INTEVT2. The start address of
the exception handling routine is common for each interrupt source. This is why, for instance, the
value of INTEVT or INTEVT2 is used as an offset at the start of the exception handling routine
and branched to in order to identify the interrupt source.
IRQ interrupt and on-chip peripheral module interrupt priorities can be set freely between 0 and 15
for each module by setting interrupt priority registers A to J (IPRA to IPRJ). A reset assigns
priority level 0 to IRQ and on-chip peripheral module interrupts.
If the same priority level is assigned to two or more interrupt sources and interrupts from those
sources occur simultaneously, their priority order is the default priority order indicated at the right
in tables 8.3 and 8.4.
Rev. 3.00 Jan. 18, 2008 Page 269 of 1458
REJ09B0033-0300
Section 8
Table 8.3
Interrupt Controller (INTC)
Interrupt Exception Handling Sources and Priority (IRQ Mode)
Interrupt
Priority
(Initial Value)
IPR
(Bit Numbers)
Priority
within IPR
Default
Setting Unit Priority
2
16


2
15


3
0 to 15 (0)
IPRC (3 to 0)

3
0 to 15 (0)
IPRC (7 to 4)

IRQ2
H'640*
3
0 to 15 (0)
IPRC (11 to 8)

IRQ3
H'660*3
0 to 15 (0)
IPRC (15 to 12)

IRQ4
3
0 to 15 (0)
IPRD (3 to 0)

3
0 to 15 (0)
IPRD (7 to 4)

3
TMU_SUNI H'6C0*
0 to 15 (0)
IPRD (11 to 8)

3
0 to 15 (0)
IPRE (15 to 12)
High
3
0 to 15 (0)
3
0 to 15 (0)
3
Interrupt Source
Interrupt
Code *1
NMI
H'1C0*
H-UDI
IRQ
H'5E0*
IRQ0
IRQ1
IRQ5
TMU
DMAC (1) DEI0
DEI1
DEI2
H'600*
H'620*
H'680*
H'6A0*
H'800*
H'820*
H'840*
DEI3
H'860*
0 to 15 (0)
LCDC
LCDCI
H'900*3
0 to 15 (0)
IPRE (7 to 4)

SSL
SSLI
H'980*3
0 to 15 (0)
IPRE (3 to 0)

H'A20*
3
0 to 15 (0)
IPRF (7 to 4)
High
H'A40*
3
H'A60*
3
0 to 15 (0)
IPRJ (11 to 8)

H'B80*
3
0 to 15 (0)
IPRF (11 to 8)
High
USBF
USBFI0
USBFI1
USBH
USBHI
DMAC (2) DEI4
DEI5
Low
Low
3
H'BA0*
3
Low

ADC
ADCI
H'BE0*
0 to 15 (0)
IPRF (15 to 12)
SCIF0
SCIFI0
H'C00*3
0 to 15 (0)
IPRG (15 to 12) 
SCIF1
SCIFI1
H'C20*3
0 to 15 (0)
IPRG (11 to 8)

3
0 to 15 (0)
IPRH (15 to 12)

3
0 to 15 (0)
IPRH (11 to 8)

3
0 to 15 (0)
IPRI (15 to 12)

3
0 to 15 (0)
IPRI (11 to 8)

PINT
PINTA
PINTB
SIOF0
SIOF1
SIOFI0
SIOFI1
H'C80*
H'CA0*
H'D00*
H'D20*
Rev. 3.00 Jan. 18, 2008 Page 270 of 1458
REJ09B0033-0300
High
Low
Section 8
Interrupt Source
Interrupt
Code *1
TPU
H'D80*
IIC
MMC
CMT
PCC
SDHI
AFEIF
TMU0
TMU1
TMU2
RTC
SIM
WDT
REF
TPI0
3
H'DA0*
TPI2
H'DC0*3
TPI3
H'DE0*3
MMCI0
0 to 15 (0)
IPRH (7 to 4)
High
IPRH (3 to 0)

0 to 15 (0)
IPRI (7 to 4)
High
H'E80*
3
H'EC0*3
MMCI3
H'EE0*3
Low
H'F00*
3
0 to 15 (0)
IPRF (3 to 0)

H'F60*
3
0 to 15 (0)
IPRI (3 to 0)

H'F80*
3
0 to 15 (0)
IPRJ (7 to 4)

3
AFECI
H'FE0*
0 to 15 (0)
IPRJ (3 to 0)

TUNI0
H'400*
2
0 to 15 (0)
IPRA (15 to 12)

H'420*
2
0 to 15 (0)
IPRA (11 to 8)

H'440*
2
0 to 15 (0)
IPRA (7 to 4)

H'480*
2
0 to 15 (0)
IPRA (3 to 0)
High
TUNI1
TUNI2
ATI
2
PRI
H'4A0*
CUI
H'4C0*2
ERI
2
H'4E0*
H'500*
TXI
H'520*2
TEND
H'540*2
RCMI
Low
0 to 15 (0)
IPRB (7 to 4)
High
2
RXI
ITI
High
Low
0 to 15 (0)
MMCI2
SDI
Priority
within IPR
Default
Setting Unit Priority
3
H'E00*
H'EA0*
PCCI
IPR
(Bit Numbers)
3
MMCI1
CMI
Interrupt
Priority
(Initial Value)
3
TPI1
IICI
Interrupt Controller (INTC)
Low
H'560*
2
0 to 15 (0)
IPRB (15 to 12)

H'580*
2
0 to 15 (0)
IPRB (11 to 8)

Low
Notes: 1. INTEVT2 code.
2. The code set in INTEVT is as same as INTEVT2.
3. The code set in INTEVT indicates interrupt level H'200 to H'3C0. For the
correspondence of interrupt level and INTEVT, see table 8.5.
Rev. 3.00 Jan. 18, 2008 Page 271 of 1458
REJ09B0033-0300
Section 8
Interrupt Controller (INTC)
Table 8.4
Interrupt Exception Handling Sources and Priority (IRL Mode)
Interrupt Source
Priority
Interrupt Interrupt Priority IPR
within IPR Default
Code *1 (Initial Value)
(Bit Numbers) Setting Unit Priority
NMI
H'1C0*
2
16


2
H'5E0*
15


3
IRL3 to RL0=B'0000 H'200*
15


IRL3 to IRL0=B'0001 H'220*
14


IRL3 to IRL0=B'0010 H'240*
13


IRL3 to IRL0=B'0011 H'260*3
12


IRL3 to IRL0=B'0100 H'280*
11


H-UDI
IRL
3
3
3
IRL3 to IRL0=B'0101 H'2A0*
10


3
IRL3 to IRL0=B'0110 H'2C0*
9


3
IRL3 to IRL0=B'0111 H'2E0*
8


3
IRL3 to IRL0=B'1000 H'300*
7


IRL3 to IRL0=B'1001 H'320*
6


IRL3 to IRL0=B'1010 H'340*
5


IRL3 to IRL0=B'1011 H'360*3
4


IRL3 to IRL0=B'1100 H'380*
3


2


3
3
3
3
IRL3 to IRL0=B'1101 H'3A0*
3
IRL3 to IRL0=B'1110 H'3C0*
1


3
0 to 15 (0)
IPRD (3 to 0)

3
0 to 15 (0)
IPRD (7 to 4)

3
3
IRQ
IRQ4
IRQ5
H'680*
H'6A0*
0 to 15 (0)
IPRD (11 to 8) 
DMAC DEI0
(1)
H'800*
3
0 to 15 (0)
IPRE
(15 to 12)
DEI1
H'820*3
0 to 15 (0)
DEI2
H'840*
3
0 to 15 (0)
H'860*
3
0 to 15 (0)
H'900*
3
0 to 15 (0)
IPRE (7 to 4)

H'980*
3
0 to 15 (0)
IPRE (3 to 0)

TMU
TMU_SUNI
DEI3
LCDC LCDCI
SSL
SSLI
H'6C0*
Rev. 3.00 Jan. 18, 2008 Page 272 of 1458
REJ09B0033-0300
High
High
Low
Low
Section 8
Interrupt Source
Interrupt Interrupt Priority
Code *1 (Initial Value)
USBF
H'A20*
USBFI0
USBFI1
USBH
USBHI
DMAC DEI4
(2)
DEI5
3
0 to 15 (0)
Interrupt Controller (INTC)
Priority
IPR
within IPR Default
(Bit Numbers) Setting Unit Priority
IPRF (7 to 4)
3
H'A40*
High
Low
3
H'A60*
0 to 15 (0)
IPRJ (11 to 8) 
H'B80*3
0 to 15 (0)
IPRF (11 to 8) High
H'BA0*3
Low
3
0 to 15 (0)
IPRF
(15 to 12)


ADC
ADCI
H'BE0*
SCIF0
SCIFI0
H'C00*3
0 to 15 (0)
IPRG (15 to
12)
SCIF1
SCUFI1
H'C20*3
0 to 15 (0)
IPRG (11 to 8) 
PINTA
H'C80*
3
0 to 15 (0)
IPRH (15 to
12)
PINTB
H'CA0*3
0 to 15 (0)
IPRH (11 to 8) 
3
0 to 15 (0)
IPRI (15 to 12) 
3
0 to 15 (0)
IPRI (11 to 8)

3
0 to 15 (0)
IPRH (7 to 4)
High
PINT
SIOF0
SIOF1
TPU
IIC
MMC
CMT
PCC
SDHI
AFEIF
SIOFI0
SIOFI1
TPI0
H'D00*
H'D20*
H'D80*
H'DA0*
TPI2
H'DC0*3
TPI3
H'DE0*3
MMCI0
0 to 15 (0)
IPRH (3 to 0)

3
0 to 15 (0)
IPRI (7 to 4)
High
H'E00*
H'E80*
3
H'EA0*
MMCI2
H'EC0*3
MMCI3
H'EE0*3
PCCI
SDI
AFECI
Low
3
MMCI1
CMI

3
TPI1
IICI
Low
H'F00*
3
0 to 15 (0)
IPRF (3 to 0)

H'F60*
3
0 to 15 (0)
IPRI (3 to 0)

H'F80*
3
0 to 15 (0)
IPRJ (7 to 4)

3
0 to 15 (0)
IPRJ (3 to 0)

H'FE0*
High
Low
Rev. 3.00 Jan. 18, 2008 Page 273 of 1458
REJ09B0033-0300
Section 8
Interrupt Controller (INTC)
Priority
IPR
within IPR Default
(Bit Numbers) Setting Unit Priority
Interrupt Source
Interrupt Interrupt Priority
Code *1 (Initial Value)
TMU0
TUNI0
H'400*
2
0 to 15 (0)
IPRA
(15 to 12)
TMU1
TUNI1
H'420*2
0 to 15 (0)
IPRA (11 to 8) 
TUNI2
H'440*
2
0 to 15 (0)
IPRA (7 to 4)

H'480*
2
0 to 15 (0)
IPRA (3 to 0)
High
TMU2
RTC
SIM
ATI

2
PRI
H'4A0*
CUI
H'4C0*2
ERI
2
H'4E0*
Low
0 to 15 (0)
IPRB (7 to 4)
High
2
RXI
H'500*
TXI
H'520*2
TEND
H'540*2
Low

2
0 to 15 (0)
IPRB (15 to
12)
0 to 15 (0)
IPRB (11 to 8) 
WDT
ITI
H'560*
REF
RCMI
H'580*2
Notes: 1. INTEVT2 code.
2. The code set in INTEVT is as same as INTEVT2.
3. The code set in INTEVT indicates interrupt level H'200 to H'3C0. For the
correspondence of interrupt level and INTEVT, see table 8.5.
Rev. 3.00 Jan. 18, 2008 Page 274 of 1458
REJ09B0033-0300
High
Low
Section 8
Table 8.5
Interrupt Controller (INTC)
Interrupt Level and INTEVT Code
Interrupt Level
INTEVT Code
15
H'200
14
H'220
13
H'240
12
H'260
11
H'280
10
H'2A0
9
H'2C0
8
H'2E0
7
H'300
6
H'320
5
H'340
4
H'360
3
H'380
2
H'3A0
1
H'3C0
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Section 8
Interrupt Controller (INTC)
8.5
Operation
8.5.1
Interrupt Sequence
The sequence of interrupt operations is described below. Figure 8.3 is a flowchart of the
operations.
1. The interrupt request sources send interrupt request signals to the interrupt controller.
2. The interrupt controller selects the highest-priority interrupt from the interrupt requests sent,
following the priority levels set in the interrupt priority registers A to J (IPRA to IPRJ). Lower
priority interrupts are held pending. If two of these interrupts have the same priority level or if
multiple interrupts occur within a single module, the interrupt with the highest priority is
selected, according to table 8.3, Interrupt Exception Handling Sources and Priority (IRQ
Mode) and table 8.4, Interrupt Exception Handling Sources and Priority (IRL Mode).
3. The priority level of the interrupt selected by the interrupt controller is compared with the
interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level
is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends
an interrupt request signal to the CPU.
4. Detection timing: The INTC operates, and notifies the CPU of interrupt requests, in
synchronization with the peripheral clock (Pφ). The CPU receives an interrupt at a break in
instructions.
5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2).
6. The status register (SR) and program counter (PC) are saved to SSR and SPC, respectively.
7. The block bit (BL), mode bit (MD), and register bank bit (RB) in SR are set to 1.
8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the
vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt
handler may branch with the INTEVT or INTEVT2 value as its offset in order to identify the
interrupt source. This enables it to branch to the handling routine for the individual interrupt
source.
Notes: 1. The interrupt mask bits (I3 to I0) in the status register (SR) are not changed by
acceptance of an interrupt in this LSI.
2. The interrupt source flag should be cleared in the interrupt handler. To ensure that an
interrupt source that should have been cleared is not inadvertently accepted again, read
the interrupt source flag after it has been cleared, and then clear the BL bit or execute
an RTE instruction.
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Section 8
Interrupt Controller (INTC)
Program
execution state
Interrupt
generated?
No
Yes
No
SR.BL=0,
sleep mode,
or standby mode?
Yes
NMI?
Yes
No
Level 15
interrupt?
Yes
Set interrupt source in
INTEVT and INTEVT2
Yes
I3 to I0 levels are
14 or lower?
No
Save SR to SSR;
save PC to SPC
Yes
No
Yes
Level 1
interrupt?
I3 to I0 levels are
13 or lower?
No
Set BL, MD, and RB
bits in SR to 1
No
Level 14
interrupt?
No
Yes
I3 to I0 levels are 0?
Yes
No
Branch to exception
handler
I3 to I0: Interrupt mask bits in status register (SR)
Figure 8.3
Interrupt Operation Flowchart
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REJ09B0033-0300
Section 8
8.5.2
Interrupt Controller (INTC)
Multiple Interrupts
When handling multiple interrupts, an interrupt handler should include the following procedures:
1. To determine the interrupt source, branch to a specific interrupt handler corresponding to a
code set in INTEVT or INTEVT2. The code in INTEVT or INTEVT2 can be used as an offset
for branching to the specific handler.
2. Clear the interrupt source in each specific handler.
3. Save SSR and SPC to memory.
4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR.
5. Handle the interrupt.
6. Execute the RTE instruction.
When these procedures are followed in order, an interrupt of higher priority than the one being
handled can be accepted after clearing BL in step 4. Figure 8.3 shows a sample interrupt operation
flowchart.
Rev. 3.00 Jan. 18, 2008 Page 278 of 1458
REJ09B0033-0300
Section 9
Section 9
Bus State Controller (BSC)
Bus State Controller (BSC)
The bus state controller (BSC) outputs control signals for various types of memory that is
connected to the external address space and external devices. The BSC functions enable this LSI
to connect directly with SRAM, SDRAM, and other memory storage devices, and external
devices.
9.1
Features
The BSC has the following features:
(1) External address space
• A maximum 32 or 64 Mbytes for each of the eight areas, CS0, CS2 to CS4, CS5A, CS5B,
CS6A and CS6B, totally 384 Mbytes (divided into eight areas).
• A maximum 64 Mbytes for each of the six areas, CS0, CS2 to CS4, CS5, and CS6, totally a
total of 384 Mbytes (divided into six areas).
• Can specify the normal space interface, byte-selection SRAM, burst ROM (clock synchronous
or asynchronous), SDRAM, PCMCIA for each address space.
• Can select the data bus width (8, 16, or 32 bits) for each address space.
• Controls the insertion of the wait state for each address space.
• Controls the insertion of the wait state for each read access and write access.
• Can set the independent idling cycle in the continuous access for five cases: read-write (in
same space/different space), read-read (in same space/different space), or the first cycle is a
write access.
(2) Normal space interface
• Supports the interface that can directly connect to the SRAM.
(3) Burst ROM (clock asynchronous) interface
• High-speed access to the ROM that has the page mode function.
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Section 9
Bus State Controller (BSC)
(4) SDRAM interface
•
•
•
•
•
•
Can set the SDRAM in up to two areas.
Multiplex output for row address/column address.
Efficient access by single read/single write.
High-speed access by bank-active mode.
Supports an auto-refresh and self-refresh.
Supports low-power function.
(5) Byte-selection SRAM interface
• Can connect directly to a byte-selection SRAM.
(6) PCMCIA direct interface
• Supports IC memory cards and I/O card interfaces defined in the JEIDA specifications Ver. 4.2
(PCMCIA2.1 Rev 2.1).
• Controls the insertion of the wait state using software.
• Supports the bus sizing function of the I/O bus width (only in little endian mode).
(7) Burst ROM (clock synchronous) interface
• Can connect directly to a burst ROM of the clock synchronous type.
(8) Bus arbitration
• Shares all of the resources with other CPU and outputs the bus enable after receiving the bus
request from external devices.
(9) Refresh function
• Supports the auto-refresh and self-refresh functions.
• Specifies the refresh interval using the refresh counter and clock selection.
• Can execute concentrated refresh by specifying the refresh counts (1, 2, 4, 6, or 8).
Rev. 3.00 Jan. 18, 2008 Page 280 of 1458
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Section 9
Bus State Controller (BSC)
(10) Interval timer using refresh counter
• Generates an interrupt request by a compare match.
Note: The PCMCIA direct interfaces supported by the BSC are only signals and bus protocols
shown in table 9.1. For details on other control signals, see section 29, PC Card Controller
(PCC) (external circuits and this LSI on-chip PC card controller).
Both area 5 and area 6 have the PCMCIA direct interface function which is common to the
SH3. The on-chip PC card controller supports only area 6.
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Section 9
Bus State Controller (BSC)
BACK
BREQ
Bus
mastership
controller
Internal bus
The block diagram of the BSC is shown in figure 9.1.
CMNCR
CS0WCR
...
Wait
controller
...
WAIT
CS6BWCR
RWTCNT
...
Module bus
CS6BBCR
MD5 to MD3
A25 to A0,
D31 to D0
BS, RD/WR, RD,
WE3(BE3) to WE0(BE0),
RAS, CAS,
CKE, DQMxx,
CE2A, CE2B
CE1A, CE1B
ICIORD, ICIOWR
CS0BCR
...
Area
controller
...
CS0, CS2, CS3,
CS4, CS5A, CS5B,
CS6A, CS6B
Memory
controller
SDCR
IOIS16
RTCSR
RTCNT
REFOUT
Refresh
controller
Comparator
Interrupt
controller
RTCOR
[Legend]
CMNCR: Common control register
CSnWCR: CSn space wait control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
RWTCNT: Reset wait counter
CSnBCR: CSn space bus control register (n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
SDCR:
SDRAM control register
RTCSR: Refresh timer control/status register
RTCNT: Refresh timer counter
RTCOR: Refresh time constant register
Figure 9.1
Rev. 3.00 Jan. 18, 2008 Page 282 of 1458
REJ09B0033-0300
BSC
Block Diagram of BSC
Internal master
module
Internal slave
module
Section 9
9.2
Bus State Controller (BSC)
Input/Output Pins
The configuration of pins in this module is shown in table 9.1.
Table 9.1
Pin Configuration
Name
I/O
Function
A25 to A0
O
Address bus
D31 to D0
I/O
Data bus
BS
O
Bus cycle start
Asserted when a normal space, burst ROM (clock
synchronous/asynchronous), or PCMCIA is accessed. Asserted by
the same timing as CAS in SDRAM access.
CS0, CS2 to CS4
O
Chip select
CS5A/CE2A
O
Chip select
Active only for address map 1
Corresponds to PCMCIA card select signals D15 to D8 when the
PCMCIA is used.
CS5B/CE1A
O
Chip select
Corresponds to PCMCIA card select signals D7 to D0 when the
PCMCIA is used.
CS6A/CE2B
O
Chip select
Active only for address map 1
Corresponds to PCMCIA card select signals D15 to D8 when the
PCMCIA is used.
CS6B/CE1B
O
Chip select
Corresponds to PCMCIA card select signals D7 to D0 when the
PCMCIA is used.
RD/WR
O
Read/write signal
Connects to WE pins when SDRAM or byte-selection SRAM is
connected.
RD
O
Read strobe (read data output enable signal)
A strobe signal to indicate the memory read cycle when the
PCMCIA is used.
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Name
I/O
Function
WE3(BE3)/DQMUU/
ICIOWR
O
Indicates that D31 to D24 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to signals D31 to D24 when SDRAM is connected.
Functions as the I/O write strobe signal when the PCMCIA is
used.
WE2(BE2)/DQMUL/
ICIORD
O
Indicates that D23 to D16 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to signals D23 to D16 when the SDRAM is used.
Functions as the I/O read strobe signal when the PCMCIA is used.
WE1(BE1)/DQMLU/
WE
O
Indicates that D15 to D8 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to signals D15 to D8 when the SDRAM is used.
Functions as the memory write strobe signal when the PCMCIA is
used.
WE0(BE0)/DQMLL
O
Indicates that D7 to D0 are being written to.
Connected to the byte select signal when a byte-selection SRAM
is connected.
Corresponds to select signals D7 to D0 when the SDRAM is used.
RAS
O
Connects to RAS pin when SDRAM is connected.
CAS
O
Connects to CAS pin when SDRAM is connected.
CKE
O
Connects to CKE pin when SDRAM is connected.
IOIS16
I
PCMCIA 16-bit I/O signal
Valid only in little endian mode.
Pulled low in bit endian mode.
WAIT
I
External wait input (sampled at the falling edge of CKIO)
BREQ
I
Bus request input
BACK
O
Bus acknowledge output
MD5 to MD3
I
MD5: Selects data alignment (big endian or little endian)
MD4 and MD3: Specify area 0 bus width (8/16/32 bits)
REFOUT
O
Bus mastership request signal for refreshing
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REJ09B0033-0300
Section 9
9.3
Area Overview
9.3.1
Area Division
Bus State Controller (BSC)
In the architecture of this LSI, both virtual spaces and physical spaces have 32-bit address spaces.
The upper three bits divide into the P0 to P4 areas, and specify the cache access method. For
details see section 5, Cache. The remaining 29 bits are used for division of the space into ten areas
(address map 1) or eight areas (address map 2) according to the MAP bit in CMNCR setting. The
BSC performs control for this 29-bit space.
As listed in tables 9.2 and 9.3, this LSI can be connected directly to eight or six areas of memory,
and it outputs chip select signals (CS0, CS2 to CS4, CS5A, CS5B, CS6A, and CS6B) for each of
them. CS0 is asserted during area 0 access; CS5A is asserted during area 5A access when address
map 1 is selected; and CS5B is asserted when address map 2 is selected.
9.3.2
Shadow Area
The BSC decodes A28 to A25 of the physical address and generates chip select signals that
correspond to areas 0, 2 to 4, 5A, 5B, 6A, and 6B. Address bits A31 to A29 are ignored. This
means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its
corresponding shadow space is the address space in P1 to P3 areas obtained by adding to it
H'20000000 × n (n = 1 to 6).
The address range for area 7 is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 +
H'20000000 × n to H'1FFFFFFF + H'20000000 × n (n = 0 to 6) corresponding to the area 7
shadow space is reserved, so do not use it.
Area P4 (H'E0000000 to H'EFFFFFFF) is an I/O area and is assigned for internal register
addresses. Therefore, area P4 does not become shadow space.
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
H'00000000
Area 0 (CS0)
Area 1 (Internal I/O)
H'20000000
H'40000000
Area 2 (CS2)
Area 3 (CS3)
P0
Area 4 (CS4)
H'60000000
Area 5A (CS5A)
Area 5B (CS5B)
H'80000000
Area 6A (CS6A)
Area 6B (CS6B)
P1
Area 7 (Reserved area)
H'A0000000
P2
Physical address space
H'C0000000
P3
H'E0000000
P4
Address space
Figure 9.2
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REJ09B0033-0300
Address Space
Section 9
9.3.3
Bus State Controller (BSC)
Address Map
The external address space has a capacity of 384 Mbytes and is used by dividing eight partial
spaces (address map 1) or six partial spaces (address map 2). The kind of memory to be connected
and the data bus width are specified in each partial space. The address map for the external address
space is listed below.
Table 9.2
Address Space Map 1 (CMNCR.MAP = 0)
Physical Address
Area
Memory to be Connected
Capacity
H'00000000 to H'03FFFFFF
Area 0
Normal memory
64 Mbytes
Burst ROM (Asynchronous)
Burst ROM (Synchronous)
H'04000000 to H'07FFFFFF
Area 1
Internal I/O register area*2
64 Mbytes
H'08000000 to H'0BFFFFFF
Area 2
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'0C000000 to H'0FFFFFFF
Area 3
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'10000000 to H'13FFFFFF
Area 4
Normal memory
64 Mbytes
Byte-selection SRAM
Burst ROM (Asynchronous)
H'14000000 to H'15FFFFFF
Area 5A
Normal memory
32 Mbytes
H'16000000 to H'17FFFFFF
Area 5B
Normal memory
32 Mbytes
Byte-selection SRAM
H'18000000 to H'19FFFFFF
Area 6A
Normal memory
32 Mbytes
H'1A000000 to H'1BFFFFFF
Area 6B
Normal memory
32 Mbytes
H'1C000000 to H'1FFFFFFF
Area 7
Byte-selection SRAM
Reserved area*1
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. Set the top three bits of the address to 101 to allocate in the P2 space.
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Section 9
Table 9.3
Bus State Controller (BSC)
Address Space Map 2 (CMNCR.MAP = 1)
Physical Address
Area
Memory to be Connected
Capacity
H'00000000 to H'03FFFFFF
Area 0
Normal memory
64 Mbytes
Burst ROM (Asynchronous)
Burst ROM (Synchronous)
H'04000000 to H'07FFFFFF
Area 1
Internal I/O register area*3
64 Mbytes
H'08000000 to H'0BFFFFFF
Area 2
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'0C000000 to H'0FFFFFFF
Area 3
Normal memory
64 Mbytes
Byte-selection SRAM
SDRAM
H'10000000 to H'13FFFFFF
Area 4
Normal memory
64 Mbytes
Byte-selection SRAM
Burst ROM (Asynchronous)
H'14000000 to H'17FFFFFF
Area 5*
2
Normal memory
64 Mbytes
Byte-selection SRAM
PCMCIA
H'18000000 to H'1BFFFFFF
Area 6*
2
Normal memory
64 Mbytes
Byte-selection SRAM
PCMCIA
H'1C000000 to H'1FFFFFFF
Area 7
Reserved area*1
64 Mbytes
Notes: 1. Do not access the reserved area. If the reserved area is accessed, the correct
operation cannot be guaranteed.
2. For area 5, CS5BBCR and CS5BWCR are valid.
For area 6, CS6BBCR and CS6BWCR are valid.
3. Set the top three bits of the address to 101 to allocate in the P2 space.
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Section 9
9.3.4
Bus State Controller (BSC)
Area 0 Memory Type and Memory Bus Width
The memory bus width in this LSI can be set for each area. In area 0, external pins can be used to
select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The memory bus
width of the other area is set by the register. The correspondence between the memory type,
external pins (MD3, MD4), and bus width is listed in the table below.
Table 9.4
Correspondence between External Pins (MD3 and MD4), Memory Type of CS0,
and Memory Bus Width
MD4
MD3
Memory Type
Bus Width
0
0
Normal memory
Reserved (Setting prohibited)
1
Note:
*
9.3.5
1
8 bits*
0
16 bits
1
32 bits
The bus width must not be specified as eight bits if the burst ROM (clock synchronous)
interface is selected.
Data Alignment
This LSI supports the big endian and little endian methods of data alignment. The data alignment
is specified using the external pin (MD5) at power-on reset as shown in table 9.5.
Table 9.5
Correspondence between External Pin (MD5) and Endians
MD5
Endian
0
Big endian
1
Little endian
Rev. 3.00 Jan. 18, 2008 Page 289 of 1458
REJ09B0033-0300
Section 9
9.4
Bus State Controller (BSC)
Register Descriptions
The BSC has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and access size of these registers.
Do not access spaces other than CS0 until the termination of the setting the memory interface.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Common control register (CMNCR)
Bus control register for CS0 (CS0BCR)
Bus control register for CS2 (CS2BCR)
Bus control register for CS3 (CS3BCR)
Bus control register for CS4 (CS4BCR)
Bus control register for CS5A (CS5ABCR)
Bus control register for CS5B (CS5BBCR)
Bus control register for CS6A (CS6ABCR)
Bus control register for CS6B (CS6BBCR)
Wait control register for CS0 (CS0WCR)
Wait control register for CS2 (CS2WCR)
Wait control register for CS3 (CS3WCR)
Wait control register for CS4 (CS4WCR)
Wait control register for CS5A (CS5AWCR)
Wait control register for CS5B (CS5BWCR)
Wait control register for CS6A (CS6AWCR)
Wait control register for CS6B (CS6BWCR)
SDRAM control register (SDCR)
Refresh timer control/status register (RTCSR)
Refresh timer counter (RTCNT)
Refresh time constant register (RTCOR)
SDRAM mode register (SDMR2)
SDRAM mode register (SDMR3)
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Section 9
9.4.1
Bus State Controller (BSC)
Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area. Do not access external
memory other than area 0 until the CMNCR initialization is complete.
Bit
Initial
Bit Name Value
31 to 15 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
14
BSD
0
R/W Bus Access Start Timing Specification After Bus
Acknowledge
Specifies the bus access start timing after the external bus
acknowledge signal is received.
0: Starts the external access at the same timing as the
address drive start after the bus acknowledge signal is
received.
1: Starts the external access one cycle following the address
drive start after the bus acknowledge signal is received.
13

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
12
MAP
0
R/W Space Specification
Selects the address map for the external address space. The
address maps to be selected are shown in tables 9.2 and 9.3.
0: Selects address map 1
1: Selects address map 2
11
BLOCK
0
R/W Bus Lock Bit
Specifies whether or not the BREQ signal is received.
0: Receives BREQ
1: Does not receive BREQ
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Section 9
Bus State Controller (BSC)
Bit
Initial
Bit Name Value
R/W Description
10
DPRTY1
0
R/W DMA Burst Transfer Priority
9
DPRTY0
0
R/W Specify the priority for a refresh request/bus mastership request
during DMA burst transfer.
00: Accepts a refresh request and bus mastership request
during DMA burst transfer
01: Accepts a refresh request but does not accept a bus
mastership request during DMA burst transfer
10: Accepts neither a refresh request nor a bus mastership
request during DMA burst transfer
11: Reserved (Setting prohibited)
8
DMAIW2
0
7
DMAIW1
0
6
DMAIW0
0
R/W Wait States between Access Cycles when DMA Single Address
R/W is Transferred
R/W Specify the number of idle cycles to be inserted after an access
to an external device with DACK when DMA single address
transfer is performed. The method of inserting idle cycles
depends on the contents of DMAIWA.
000: No idle cycle inserted
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycled inserted
100: 6 idle cycled inserted
101: 8 idle cycle inserted
110: 10 idle cycles inserted
111: 12 idle cycled inserted
5
DMAIWA 0
R/W Method of Inserting Wait States between Access Cycles when
DMA Single Address is Transferred
Specifies the method of inserting the idle cycles specified by the
DMAIW1 and DMAIW0 bits. Clearing this bit will make this LSI
insert the idle cycles when another device, which includes this
LSI, drives the data bus after an external device with DACK
drove it. Setting this bit will make this LSI insert the idle cycles
even when the continuous accesses to an external device with
DACK are performed.
0: Inserts the idle cycles when another device drives the data
bus after an external device with DACK drove it.
1: Inserts the idle cycles every time when an external device
with DACK is accessed.
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REJ09B0033-0300
Section 9
Bit
Bit Name
Initial
Value
R/W
Description
4

1
R
Reserved
Bus State Controller (BSC)
This bit is always read as 1. The write value should always
be 1.
3
ENDIAN
0/1*
R
Endian Flag
Samples the external pin for specifying endian on power-on
reset (MD5). All address spaces are defined by this bit. This
is a read-only bit.
0: The external pin for specifying endian (MD5) was low level
on power-on reset. This LSI is being operated as big
endian.
1: The external pin for specifying endian (MD5) was high
level on power-on reset. This LSI is being operated as
little endian.
2

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
1
HIZMEM
0
R/W
High-Z Memory Control
Specifies the pin state in standby mode for A25 to A0, BS,
CSn, RD/WR, WEn(BEn)/DQMxx, and RD. When a bus is
released, these pins enter the high-impedance state
regardless of the setting of this bit.
0: High impedance in standby mode
1: Driven in standby mode
0
HIZCNT
0
R/W
High-Z Control
Specifies the state in standby mode and bus released for
CKIO, CKE, RAS, and CAS.
0: High impedance in standby mode and bus released for
CKIO, CKE, RAS, and CAS.
1: Driven in standby mode and bus released for CKIO, CKE,
RAS, and CAS.
Note:
*
The external pin (MD5) for specifying endian is sampled on power-on reset. When big
endian is specified, this bit is read as 0 and when little endian is specified, this bit is
read as 1.
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Section 9
9.4.2
Bus State Controller (BSC)
CSn Space Bus Control Register (CSnBCR)
This register specifies the type of memory connected to each space, data-bus width of each space,
and the number of wait cycles between access cycles.
Do not access external memory other than area 0 until the CSnBCR initialization is completed.
(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
Bit
Bit Name
Initial
Value
R/W
Description
31

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
30
IWW2
0
R/W
29
IWW1
1
R/W
28
IWW0
1
R/W
Idle Cycles between Write-Read Cycles and Write-Write
Cycles
These bits specify the number of idle cycles to be inserted
after the access to a memory that is connected to the space.
The target access cycles are the write-read cycle and writewrite cycle.
000: No idle cycle
001: 1 idle cycle inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
27
IWRWD2
0
R/W
Idle Cycles for Another Space Read-Write
26
IWRWD1
1
R/W
25
IWRWD0
1
R/W
Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target access cycle is a read-write one in which continuous
accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
24
IWRWS2
0
R/W
Idle Cycles for Read-Write in Same Space
23
IWRWS1
1
R/W
22
IWRWS0
1
R/W
Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target cycle is a read-write cycle of which continuous
accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
21
IWRRD2
0
R/W
Idle Cycles for Read-Read in Another Space
20
IWRRD1
1
R/W
19
IWRRD0
1
R/W
Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target cycle is a read-read cycle of which continuous
accesses switch between different spaces.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
18
IWRRS2
0
R/W
Idle Cycles for Read-Read in Same Space
17
IWRRS1
1
R/W
16
IWRRS0
1
R/W
Specify the number of idle cycles to be inserted after the
access to a memory that is connected to the space. The
target cycle is a read-read cycle of which continuous
accesses are for the same space.
000: No idle cycle inserted
001: 1 idle cycles inserted
010: 2 idle cycles inserted
011: 4 idle cycles inserted
100: 6 idle cycles inserted
101: 8 idle cycles inserted
110: 10 idle cycles inserted
111: 12 idle cycles inserted
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
15
TYPE3
0
R/W
Memory Type
14
TYPE2
0
R/W
Specify the type of memory connected to a space.
13
TYPE1
0
R/W
0000: Normal space
12
TYPE0
0
R/W
0001: Burst ROM (clock asynchronous)
0010: Reserved (setting prohibited)
0011: Byte-selection SRAM
0100: SDRAM
0101: PCMCIA
0110: Reserved (setting prohibited)
0111: Burst ROM (clock synchronous)
1000: Reserved (setting prohibited)
1001: Reserved (setting prohibited)
1010: Reserved (setting prohibited)
1011: Reserved (setting prohibited)
1100: Reserved (setting prohibited)
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Note: Memory type for area 0 immediately after reset is
normal space. The normal space, burst ROM (clock
asynchronous), or burst ROM (clock synchronous) can
be selected by these bits.
For details on memory type in each area, see tables 9.2 and
9.3.
11

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10
BSZ1
1*
R/W
Data Bus Width
9
BSZ0
1*
R/W
Specify the data bus width of spaces.
00: Reserved (setting prohibited)
01: 8-bit size
10: 16-bit size
11: 32-bit size
Notes: 1. The data bus width for area 0 is specified by the
external pin. The BSZ1 and BSZ0 bit settings in
CS0BCR are ignored.
2. If area 5 or area 6 is specified as PCMCIA space,
the bus width can be specified as either 8 bits or
16 bits.
3. If area 2 or area 3 is specified as SDRAM space,
the bus width can be specified as either 16 bits or
32 bits.
8 to 0

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Note:
*
CS0BCR samples the external pins (MD3 and MD4) that specify the bus width at
power-on reset.
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Section 9
9.4.3
Bus State Controller (BSC)
CSn Space Wait Control Register (CSnWCR)
This register specifies various wait cycles for memory accesses. The bit configuration of this
register varies as shown below according to the memory type (TYPE3, TYPE2, TYPE1, or
TYPE0) specified by the CSn space bus control register (CSnBCR). Specify CSnWCR before
accessing the target area. Specify CSnBCR first, then specify CSnWCR.
(n = 0, 2, 3, 4, 5A, 5B, 6A, 6B)
(1)
Normal Space, Byte-Selection SRAM
• CS0WCR, CS6BWCR
Bit
Bit Name
Initial
Value
R/W
31 to 21

All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19 to 13

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
12
SW1
0
R/W
11
SW0
0
R/W
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10
WR3
1
R/W
Number of Access Wait Cycles
9
WR2
0
R/W
8
WR1
1
R/W
Specify the number of wait cycles that are necessary for
read or write access.
7
WR0
0
R/W
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (Setting prohibited)
1110: Reserved (Setting prohibited)
1111: Reserved (Setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5 to 2

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
1
HW1
0
R/W
0
HW0
0
R/W
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS2WCR, CS3WCR
Bit
Bit Name
Initial
Value
R/W
31 to 21

All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19 to 11

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10
WR3
1
R/W
Number of Access Wait Cycles
9
WR2
0
R/W
8
WR1
1
R/W
Specify the number of wait cycles that are necessary for
read or write access.
7
WR0
0
R/W
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5 to 0

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 9
Bus State Controller (BSC)
• CS4WCR
Bit
Initial
Bit Name Value
31 to 21 
All 0
R/W
Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
18
WW2
0
R/W
Number of Write Access Wait Cycles
17
WW1
0
R/W
16
WW0
0
R/W
Specify the number of cycles that are necessary for write
access.
000: The same cycles as WR3 to WR0 setting (read or
write access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 9
Bus State Controller (BSC)
Bit
Initial
Bit Name Value
R/W
Description
12
SW1
0
R/W
11
SW0
0
R/W
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) AssertionSpecify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10
WR3
1
R/W
Number of Access Wait Cycles
9
WR2
0
R/W
8
WR1
1
R/W
Specify the number of wait cycles that are necessary for
read or write access.
7
WR0
0
R/W
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the number
of access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
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Section 9
Bit
Initial
Bit Name Value
R/W
Description
5 to 2

R
Reserved
All 0
Bus State Controller (BSC)
These bits are always read as 0. The write value should
always be 0.
1
HW1
0
R/W
0
HW0
0
R/W
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5AWCR
Bit
Bit Name
Initial
Value
R/W
Description
31 to 19

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
18
WW2
0
R/W
Number of Write Access Wait Cycles
17
WW1
0
R/W
16
WW0
0
R/W
Specify the number of cycles that are necessary for write
access.
000: The same cycles as WR3 to WR0 setting (read or
write access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
12
SW1
0
R/W
11
SW0
0
R/W
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10
WR3
1
R/W
Number of Access Wait Cycles
9
WR2
0
R/W
8
WR1
1
R/W
Specify the number of wait cycles that are necessary for
read or write access.
7
WR0
0
R/W
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
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Section 9
Bit
Bit Name
Initial
Value
R/W
Description
5 to 2

All 0
R
Reserved
Bus State Controller (BSC)
These bits are always read as 0. The write value should
always be 0.
1
HW1
0
R/W
0
HW0
0
R/W
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
• CS5BWCR
Bit
Bit Name
Initial
Value
R/W
Description
31 to 21

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BAS
0
R/W
Byte Access Selection for Byte-Selection SRAM
Specifies the WEn (BEn) and RD/WR signal timing when
the byte-selection SRAM interface is used.
0: Asserts the WEn (BEn) signal at the read/write timing
and asserts the RD/WR signal during the write access
cycle.
1: Asserts the WEn (BEn) signal during the read/write
access cycle and asserts the RD/WR signal at the write
timing.
19

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
18
WW2
0
R/W
Number of Write Access Wait Cycles
17
WW1
0
R/W
16
WW0
0
R/W
Specify the number of cycles that are necessary for write
access.
000: The same cycles as WR3 to WR0 setting (read or
write access wait)
001: 0 cycles
010: 1 cycle
011: 2 cycles
100: 3 cycles
101: 4 cycles
110: 5 cycles
111: 6 cycles
15 to 13

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
12
SW1
0
R/W
11
SW0
0
R/W
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
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REJ09B0033-0300
Section 9
Bit
Initial
Bit Name Value
10
WR3
9
WR2
8
7
Bus State Controller (BSC)
R/W
Description
1
R/W
Number of Access Wait Cycles
0
R/W
WR1
1
R/W
Specify the number of wait cycles that are necessary for read
or write access.
WR0
0
R/W
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
5 to 2

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
HW1
0
R/W
0
HW0
0
R/W
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn (BEn)
negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
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Section 9
Bus State Controller (BSC)
• CS6AWCR
Bit
Bit Name
Initial
Value
R/W
31 to 13

All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
12
SW1
0
R/W
11
SW0
0
R/W
Number of Delay Cycles from Address, CSn Assertion to
RD, WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
10
WR3
1
R/W
Number of Access Wait Cycles
9
WR2
0
R/W
8
WR1
1
R/W
Specify the number of wait cycles that are necessary for
read or write access.
7
WR0
0
R/W
0000: 0 cycle
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
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Section 9
Bit
Bit Name
Initial
Value
R/W
Description
5 to 2

All 0
R
Reserved
Bus State Controller (BSC)
These bits are always read as 0. The write value should
always be 0.
1
HW1
0
R/W
0
HW0
0
R/W
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
(2)
Burst ROM (Clock Asynchronous)
• CS0WCR
Bit
Initial
Bit Name Value
31 to 21 
All 0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BEN
0
R/W
Burst Enable Specification
Enables or disables 8-burst access for a 16-bit bus width or
16-burst access for an 8-bit bus width during 16-byte access.
If this bit is set to 1, 2-burst access is performed four times
when the bus width is 16 bits and 4-burst access is
performed four times when the bus width is 8 bits.
To use a device that does not support 8-burst access or 16burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
1: Disables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
19, 18

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
17
BW1
0
R/W
Number of Burst Wait Cycles
16
BW0
0
R/W
Specify the number of wait cycles to be inserted between
the second or later access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
10
W3
1
R/W
Number of Access Wait Cycles
9
W2
0
R/W
8
W1
1
R/W
Specify the number of wait cycles to be inserted in the first
access cycle.
7
W0
0
R/W
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
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Section 9
Bit
Bit Name
Initial
Value
R/W
Description
6
WM
0
R/W
External Wait Mask Specification
Bus State Controller (BSC)
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
5 to 0

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
• CS4WCR
Bit
Initial
Bit Name Value
31 to 21 
All 0
R/W
Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
BEN
0
R/W
Burst Enable Specification
Enables or disables 8-burst access for a 16-bit bus width or
16- burst access for an 8-bit bus width during 16-byte access.
If this bit is set to 1, 2-burst access is performed four times
when the bus width is 16 bits and 4-burst access is
performed four times when the bus width is 8 bits.
To use a device that does not support 8-burst access or 16burst access, set this bit to 1.
0: Enables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
1: Disables 8-burst access for a 16-bit bus width and 16-burst
access for an 8-bit bus width.
19, 18

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 313 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Initial
Bit Name Value
R/W
Description
17
BW1
0
R/W
Number of Burst Wait Cycles
16
BW0
0
R/W
Specify the number of wait cycles to be inserted between the
second or later access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 13 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
12
SW1
0
R/W
11
SW0
0
R/W
Number of Delay Cycles from Address, CSn Assertion to RD,
WEn (BEn) Assertion
Specify the number of delay cycles from address and CSn
assertion to RD and WEn (BEn) assertion. These bits can be
specified only in area 4.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 3.00 Jan. 18, 2008 Page 314 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10
W3
1
R/W
Number of Access Wait Cycles
9
W2
0
R/W
8
W1
1
R/W
Specify the number of wait cycles to be inserted in the first
access cycle.
7
W0
0
R/W
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
6
WM
0
R/W
External Wait Mask Specification
Specifies whether or not the external wait input is valid.
The specification by this bit is valid even when the number
of access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
5 to 2

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
HW1
0
R/W
0
HW0
0
R/W
Number of Delay Cycles from RD, WEn (BEn) negation to
Address, CSn negation
Specify the number of delay cycles from RD and WEn
(BEn) negation to address and CSn negation. These bits
can be specified only in area 4.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 3.00 Jan. 18, 2008 Page 315 of 1458
REJ09B0033-0300
Section 9
(3)
Bus State Controller (BSC)
SDRAM
• CS2WCR
Bit
Initial
Bit Name Value
R/W
31 to 9

R
All 0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
8
A2CL1
1
R/W
CAS Latency for Area 2
7
A2CL0
0
R/W
Specify the CAS latency for area 2.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
6 to 0

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
• CS3WCR
Bit
Initial
Bit Name Value
R/W Description
31 to 15

R
All 0
Reserved
These bits are always read as 0. The write value should
always be 0.
14
TRP1
0
13
TRP0
0
R/W Number of Cycles from Auto-Precharge/PRE Command to
R/W ACTV Command
Specify the number of minimum cycles from the start of autoprecharge or issuing of PRE command to the issuing of
ACTV command for the same bank. The setting for areas 2
and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
12

0
R
Reserved
This bit is always read as 0. The write value should always be
0.
Rev. 3.00 Jan. 18, 2008 Page 316 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
11
TRCD1
0
R/W
10
TRCD0
1
R/W
Number of Cycles from ACTV Command to
READ(A)/WRIT(A) Command
Specify the number of minimum cycles from issuing ACTV
command to issuing READ(A)/WRIT(A) command. The
setting for areas 2 and 3 is common.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
9

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
8
A3CL1
1
R/W
CAS Latency for Area 3.
7
A3CL0
0
R/W
Specify the CAS latency for area 3.
00: 1 cycle
01: 2 cycles
10: 3 cycles
11: 4 cycles
When connecting the SDRAM to area 2 and area 3, set
the CAS latency to the bits 8 and 7 in the CS2WCR
register and the SDMR2 and SDMR3 registers for SDRAM
mode setting. (See table 9.19.)
6, 5

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
TRWL1
0
R/W
3
TRWL0
0
R/W
Number of Cycles from WRITA/WRIT Command to AutoPrecharge/PRE Command
Specifies the number of cycles from issuing WRITA/WRIT
command to the start of auto-precharge or to issuing PRE
command. The setting for areas 2 and 3 is common.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
Rev. 3.00 Jan. 18, 2008 Page 317 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
2

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
1
TRC1
0
R/W
0
TRC0
0
R/W
Number of Cycles from REF Command/Self-Refresh
Release to ACTV Command
Specify the number of minimum cycles from issuing the
REF command or releasing self-refresh to issuing the
ACTV command. The setting for areas 2 and 3 is
common.
00: 3 cycles
01: 4 cycles
10: 6 cycles
11: 9 cycles
Note:
*
If both areas 2 and 3 are specified as SDRAM, TRP1/0, TRCD0/1, TRWL1/0, and
TRC1/0 bit settings are common.
If only one area is connected to the SDRAM, specify area 3. In this case, specify area 2
as normal space or byte-selection SRAM.
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REJ09B0033-0300
Section 9
(4)
Bus State Controller (BSC)
PCMCIA
• CS5BWCR, CS6BWCR
Bit
Initial
Bit Name Value
31 to 22 
All 0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
21
SA1
0
R/W
Space Attribute Specification
20
SA0
0
R/W
Specify memory card interface or I/O card interface when the
PCMCIA interface is selected.
SA1
0: Specifies memory card interface when A25 = 1
1: Specifies I/O card interface when A25 = 1
SA0
0: Specifies memory card interface when A25 = 0
1: Specifies I/O card interface when A25 = 0
Note: When using the PC card controller, specifies the
following settings.
When the bit 4 (P0USE) in the PCC0GCR register of
PCC is 1 and the bit 5 (P0PCCT) of the PCC0GCR
register is 0, both SA1 and SA0 should be 0. When
the bit 4 (P0USE) and the bit 5 (P0PCCT) in the
PCC0GCR register of PCC are 1, both SA1 and SA0
should be 1.
19 to 15 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 319 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
14
TED3
0
R/W
Delay from Address to RD or WE Assert
13
TED2
0
R/W
12
TED1
0
R/W
Specify the delay time from address output to RD or WE
assert in PCMCIA interface.
11
TED0
0
R/W
0000: 0.5 cycle
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycles
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycles
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
Rev. 3.00 Jan. 18, 2008 Page 320 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
10
9
8
7
PCW3
PCW2
PCW1
PCW0
1
0
1
0
R/W
R/W
R/W
R/W
Number of Access Wait Cycles
Specify the number of wait cycles to be inserted.
0000: 3 cycles
0001: 6 cycles
0010: 9 cycles
0011: 12 cycles
0100: 15 cycles
0101: 18 cycles
0110: 22 cycles
0111: 26 cycles
1000: 30 cycles
1001: 33 cycles
1010: 36 cycles
1011: 38 cycles
1100: 52 cycles
1101: 60 cycles
1110: 64 cycles
1111: 80 cycles
6
WM
0
R/W
External Wait Mask Specification
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycle is 0.
0: External wait is valid
1: External wait is ignored
5, 4

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 321 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
3
TEH3
0
R/W
Delay from RD or WE Negate to Address
2
TEH2
0
R/W
1
TEH1
0
R/W
Specify the address hold time from RD or WE negate in the
PCMCIA interface.
0
TEH0
0
R/W
0000: 0.5 cycle
0001: 1.5 cycles
0010: 2.5 cycles
0011: 3.5 cycles
0100: 4.5 cycles
0101: 5.5 cycles
0110: 6.5 cycles
0111: 7.5 cycles
1000: 8.5 cycles
1001: 9.5 cycles
1010: 10.5 cycles
1011: 11.5 cycles
1100: 12.5 cycles
1101: 13.5 cycles
1110: 14.5 cycles
1111: 15.5 cycles
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REJ09B0033-0300
Section 9
(5)
Bus State Controller (BSC)
Burst ROM (Clock Synchronous)
• CS0WCR
Bit
Initial
Bit Name Value
31 to 18 
All 0
R/W
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
17
BW1
0
R/W
Number of Burst Wait Cycles
16
BW0
0
R/W
Specify the number of wait cycles to be inserted between the
second or later access cycles in burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 11 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
10
W3
1
R/W
Number of Access Wait Cycles
9
W2
0
R/W
8
W1
1
R/W
Specify the number of wait cycles to be inserted in the first
access cycle.
7
W0
0
R/W
0000: 0 cycles
0001: 1 cycle
0010: 2 cycles
0011: 3 cycles
0100: 4 cycles
0101: 5 cycles
0110: 6 cycles
0111: 8 cycles
1000: 10 cycles
1001: 12 cycles
1010: 14 cycles
1011: 18 cycles
1100: 24 cycles
1101: Reserved (setting prohibited)
1110: Reserved (setting prohibited)
1111: Reserved (setting prohibited)
Rev. 3.00 Jan. 18, 2008 Page 323 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value R/W
Description
6
WM
0
External Wait Mask Specification
R/W
Specify whether or not the external wait input is valid. The
specification by this bit is valid even when the number of
access wait cycles is 0.
0: External wait is valid
1: External wait is ignored
5 to 0

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 324 of 1458
REJ09B0033-0300
Section 9
9.4.4
Bus State Controller (BSC)
SDRAM Control Register (SDCR)
SDCR specifies the method to refresh and access SDRAM, and the types of SDRAMs to be
connected.
Bit
Initial
Bit Name Value
31 to 21 
All 0
R/W
Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
20
A2ROW1 0
R/W
Number of Bits of Row Address for Area 2
19
A2ROW0 0
R/W
Specify the number of bits of row address for area 2.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
18

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
17
A2COL1
0
R/W
Number of Bits of Column Address for Area 2
16
A2COL0
0
R/W
Specify the number of bits of column address for area 2.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
15, 14

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
13
DEEP
0
R/W
Deep Power-Down Mode
This bit is valid for low-power SDRAM. If the RMODE bit is
set to 1 while this bit is set to 1, the deep power-down entry
command is issued and the low-power SDRAM enters the
deep power-down mode.
0: Self-refresh mode
1: Deep power-down mode
Rev. 3.00 Jan. 18, 2008 Page 325 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Bit Name
Initial
Value
R/W
Description
12

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
11
RFSH
0
R/W
Refresh Control
Specifies whether or not the refresh operation of the SDRAM
is performed.
0: No refresh
1: Refresh
10
RMODE
0
R/W
Refresh Control
Specifies whether to perform auto-refresh or self-refresh
when the RFSH bit is 1. When the RFSH bit is 1 and this bit
is 1, self-refresh starts immediately. When the RFSH bit is 1
and this bit is 0, auto-refresh starts according to the contents
that are set in RTCSR, RTCNT, and RTCOR.
0: Auto-refresh is performed
1: Self-refresh is performed
9
PDOWN
0
R
Power-Down Mode
Specifies whether the SDRAM is entered in power-down
mode or not after the access to SDRAM is completed. If this
bit is set to 1, the CKE pin is pulled to low to place the
SDRAM to power-down mode.
0: Does not place the SDRAM in power-down mode after
access completion.
1: Places the SDRAM in power-down mode after access
completion.
Rev. 3.00 Jan. 18, 2008 Page 326 of 1458
REJ09B0033-0300
Section 9
Bit
Initial
Bit Name Value
R/W
Description
8
BACTV
R/W
Bank Active Mode
0
Bus State Controller (BSC)
Specifies to access whether in auto-precharge mode (using
READA and WRITA commands) or in bank active mode
(using READ and WRIT commands).
0: Auto-precharge mode (using READA and WRITA
commands)
1: Bank active mode (using READ and WRIT commands)
Note: Bank active mode can be used only in area 3. In this
case, the bus width can be selected as 16 or 32 bits.
When both areas 2 and 3 are set to SDRAM, specify
auto-precharge mode.
7 to 5

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
A3ROW1 0
R/W
Number of Bits of Row Address for Area 3
3
A3ROW0 0
R/W
Specify the number of bits of the row address for area 3.
00: 11 bits
01: 12 bits
10: 13 bits
11: Reserved (setting prohibited)
2

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
1
A3COL1
0
R/W
Number of Bits of Column Address for Area 3
0
A3COL0
0
R/W
Specify the number of bits of the column address for area 3.
00: 8 bits
01: 9 bits
10: 10 bits
11: Reserved (setting prohibited)
Rev. 3.00 Jan. 18, 2008 Page 327 of 1458
REJ09B0033-0300
Section 9
9.4.5
Bus State Controller (BSC)
Refresh Timer Control/Status Register (RTCSR)
RTCSR specifies various items about refresh for SDRAM.
When RTCSR is written, the upper 16 bits of the write data must be H'A55A to cancel write
protection.
Bit
Bit Name
31 to 8 
Initial
Value
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
7
CMF
0
R/W
Compare Match Flag
Indicates that a compare match occurs between the refresh
timer counter (RTCNT) and refresh time constant register
(RTCOR). This bit is set or cleared in the following
conditions.
0: Clearing condition: When 0 is written in CMF after reading
out RTCSR during CMF = 1.
1: Setting condition: When the condition RTCNT = RTCOR is
satisfied.
6
CMIE
0
R/W
Compare Match Interrupt Enable
Enables or disables a CMF interrupt request when the CMF
bit of RTCSR is set to 1.
0: Disables the CMF interrupt request
1: Enables the CMF interrupt request
5
CKS2
0
R/W
Clock Select
4
CKS1
0
R/W
3
CKS0
0
R/W
Select the clock input to count-up the refresh timer counter
(RTCNT).
000: Stop the counting-up
001: Bφ/4
010: Bφ/16
011: Bφ/64
100: Bφ/256
101: Bφ/1024
110: Bφ/2048
111: Bφ/4096
Rev. 3.00 Jan. 18, 2008 Page 328 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Bit
Initial
Bit Name Value
R/W
Description
2
RRC2
0
R/W
Refresh Count
1
RRC1
0
R/W
0
RRC0
0
R/W
Specify the number of continuous refresh cycles, when the
refresh request occurs after the coincidence of the values of
the refresh timer counter (RTCNT) and the refresh time
constant register (RTCOR). These bits can make the period
of occurrence of refresh long.
000: Once
001: Twice
010: 4 times
011: 6 times
100: 8 times
101: Reserved (setting prohibited)
110: Reserved (setting prohibited)
111: Reserved (setting prohibited)
9.4.6
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit counter that increments using the clock selected by bits CKS2 to CKS0 in
RTCSR. When RTCNT matches RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to
0 after counting up to 255. When the RTCNT is written, the upper 16 bits of the write data must
be H'A55A to cancel write protection.
Bit
Initial
Bit Name Value
R/W
31 to 8

R
All 0
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 0

All 0
R/W
8-bit Counter
Rev. 3.00 Jan. 18, 2008 Page 329 of 1458
REJ09B0033-0300
Section 9
9.4.7
Bus State Controller (BSC)
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1
and RTCNT is cleared to 0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal.
This request is maintained until the refresh operation is performed. If the request is not processed
when the next matching occurs, the previous request is ignored.
If the CMIE bit of the RTCSR is set to 1, an interrupt is requested by this matching signal. This
request is maintained until the CMF bit in RTCSR is cleared to 0. Clearing the CMF bit in RTCSR
affects only interrupts and does not affect refresh requests. This makes it possible to count the
number of refresh requests during refresh by interrupts, and to specify the refresh and interval
timer interrupts simultaneously. When the RTCOR is written, the upper 16 bits of the write data
must be H'A55A to cancel write protection.
Bit
Bit Name
31 to 8 
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
7 to 0

9.4.8
SDRAM Mode Registers 2, 3 (SDMR2 and SRMR3)
All 0
R/W
8-bit Counter
For the settings of SDRAM mode registers (SDMR2 and SDMR3), see table 9.19.
Rev. 3.00 Jan. 18, 2008 Page 330 of 1458
REJ09B0033-0300
Section 9
9.5
Operation
9.5.1
Endian/Access Size and Data Alignment
Bus State Controller (BSC)
This LSI supports big endian, in which the 0 address is the most significant byte (MSByte) in the
byte data and little endian, in which the 0 address is the least significant byte (LSByte) in the byte
data. Endian is specified on power-on reset by the external pin (MD5). When MD5 pin is low
level on power-on reset, the endian will become big endian and when MD5 pin is high level on
power-on reset, the endian will become little endian.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and byteselection SRAM. Two data bus widths (16 bits and 32 bits) are available for SDRAM. Two data
bus widths (8 bits and 16 bits) are available for PCMCIA interface. Data alignment is performed
in accordance with the data bus width of the device and endian. This also means that when
longword data is read from a byte-width device, the read operation must be done four times. In
this LSI, data alignment and conversion of data length is performed automatically between the
respective interfaces.
Tables 9.6 to 9.11 show the relationship between endian, device data width, and access unit.
Table 9.6
32-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to
D24
D23 to
D16
D15 to
D8
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
D7 to D0 DQMUU
DQMUL
DQMLU
DQMLL
Byte access
at 0
Data
7 to 0



Assert



Byte access
at 1

Data
7 to 0



Assert


Byte access
at 2


Data
7 to 0



Assert

Byte access
at 3



Data
7 to 0



Assert
Word access
at 0
Data
15 to 8
Data
7 to 0


Assert
Assert


Word access 
at 2

Data
15 to 8
Data
7 to 0


Assert
Assert
Longword
access at 0
Data
23 to 16
Data
15 to 8
Data
7 to 0
Assert
Assert
Assert
Assert
Data
31 to 24
Rev. 3.00 Jan. 18, 2008 Page 331 of 1458
REJ09B0033-0300
Section 9
Table 9.7
Bus State Controller (BSC)
16-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to D23 to D15 to D7 to
D24
D16
D8
D0
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
DQMUU
DQMUL
DQMLU
DQMLL
Byte access at 0


Data
7 to 0



Assert

Byte access at 1



Data
7 to 0



Assert
Byte access at 2


Data
7 to 0



Assert

Byte access at 3



Data
7 to 0



Assert
Word access at 0


Data
Data
15 to 8 7 to 0


Assert
Assert
Word access at 2


Data
Data
15 to 8 7 to 0


Assert
Assert
1st

time at 0

Data
31 to
24
Data
23 to
16


Assert
Assert
2nd

time at 2

Data
Data
15 to 8 7 to 0


Assert
Assert
Longword
access
at 0
Rev. 3.00 Jan. 18, 2008 Page 332 of 1458
REJ09B0033-0300
Section 9
Table 9.8
Bus State Controller (BSC)
8-Bit External Device/Big Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to D23 to D15 to D7 to
D24
D16
D8
D0
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
DQMUU
DQMUL
DQMLU
DQMLL
Byte access at 0



Data
7 to 0



Assert
Byte access at 1



Data
7 to 0



Assert
Byte access at 2



Data
7 to 0



Assert
Byte access at 3



Data
7 to 0



Assert
Word
access at 0



Data
15 to 8



Assert
2nd time 
at 1


Data
7 to 0



Assert



Data
15 to 8



Assert
2nd time 
at 3


Data
7 to 0



Assert



Data

31 to 24


Assert
2nd time 
at 1


Data

23 to 16


Assert
3rd time 
at 2


Data
15 to 8



Assert
4th time 
at 3


Data
7 to 0



Assert
Word
access at 2
Longword
access at 0
1st time
at 0
1st time
at 2
1st time
at 0
Rev. 3.00 Jan. 18, 2008 Page 333 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.9
32-Bit External Device/Little Endian Access and Data Alignment
Data Bus
Strobe Signals
D31 to
D24
D23 to
D16
D15 to
D8
D7 to
D0
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
DQMUU
DQMUL
DQMLU
DQMLL
Byte access
at 0



Data
7 to 0


Byte access
at 1


Data
7 to 0



Assert

Byte access
at 2

Data
7 to 0



Assert


Byte access
at 3
Data
7 to 0



Assert



Word access 
at 0

Data
15 to 8
Data
7 to 0


Assert
Assert
Word access Data
at 2
15 to 8
Data
7 to 0


Assert
Assert


Longword
access at 0
Data
23 to 16
Data
15 to 8
Data
7 to 0
Assert
Assert
Assert
Assert
Operation
Data
31 to 24
Rev. 3.00 Jan. 18, 2008 Page 334 of 1458
REJ09B0033-0300
Assert
Section 9
Bus State Controller (BSC)
Table 9.10 16-Bit External Device/Little Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to D23 to D15 to
D24
D16
D8
D7 to
D0
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
DQMUU
DQMUL
DQMLU
DQMLL
Byte access at 0



Data
7 to 0



Assert
Byte access at 1


Data
7 to 0



Assert

Byte access at 2



Data
7 to 0



Assert
Byte access at 3


Data
7 to 0



Assert

Word access at 0


Data
15 to 8
Data
7 to 0


Assert
Assert
Word access at 2


Data
15 to 8
Data
7 to 0


Assert
Assert
1st

time at 0

Data
15 to 8
Data
7 to 0


Assert
Assert
2nd

time at 1

Data
31 to 24
Data

23 to 16

Assert
Assert
Longword
access
at 0
Rev. 3.00 Jan. 18, 2008 Page 335 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.11 8-Bit External Device/Little Endian Access and Data Alignment
Data Bus
Strobe Signals
Operation
D31 to D23 to D15
D7 to
D24
D16
to D8 D0
WE3(BE3), WE2(BE2), WE1(BE1), WE0(BE0),
DQMUU
DQMUL
DQMLU
DQMLL
Byte access at 0



Data
7 to 0



Assert
Byte access at 1



Data
7 to 0



Assert
Byte access at 2



Data
7 to 0



Assert
Byte access at 3



Data
7 to 0



Assert
Word
access at 0



Data
7 to 0



Assert
2nd time 
at 1


Data
15 to 8



Assert



Data
7 to 0



Assert
2nd time 
at 3


Data
15 to 8



Assert



Data
7 to 0



Assert
2nd time 
at 1


Data
15 to 8



Assert
3rd time 
at 2


Data

23 to 16


Assert
4th time 
at 3


Data

31 to 24


Assert
Word
access at 2
Longword
access at 0
1st time
at 0
1st time
at 2
1st time
at 0
Rev. 3.00 Jan. 18, 2008 Page 336 of 1458
REJ09B0033-0300
Section 9
9.5.2
(1)
Bus State Controller (BSC)
Normal Space Interface
Basic Timing
For access to a normal space, this LSI uses strobe signal output in consideration of the fact that
mainly static RAM will be directly connected. When using SRAM with a byte-selection pin, see
section 9.5.7, Byte-Selection SRAM Interface. Figure 9.3 shows the basic timings of normal space
access. A no-wait normal access is completed in two cycles. The BS signal is asserted for one
cycle to indicate the start of a bus cycle.
T1
T2
CKIO
A
CSn
RD/WR
Read
RD
D
RD/WR
WEn(BEn)
Write
D
BS
DACKn *
Note: * The waveform for DACKn is when active low is specified.
Figure 9.3
Normal Space Basic Access Timing (Access Wait 0)
Rev. 3.00 Jan. 18, 2008 Page 337 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
There is no access size specification when reading. The correct access start address is output in the
least significant bit of the address, but since there is no access size specification, 32 bits are always
read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WEn
(BEn) signal for the byte to be written is asserted.
It is necessary to output the data that has been read using RD when a buffer is established in the
data bus. The RD/WR signal is in a read state (high output) when no access has been carried out.
Therefore, care must be taken when controlling the external data buffer, to avoid collision.
Figures 9.4 and 9.5 show the basic timings of normal space accesses. If the WM bit of the
CSnWCR is cleared to 0, a Tnop cycle is inserted to evaluate the external wait (figure 9.4). If the
WM bit of the CSnWCR is set to 1, external waits are ignored and no Tnop cycle is inserted
(figure 9.5).
Rev. 3.00 Jan. 18, 2008 Page 338 of 1458
REJ09B0033-0300
Section 9
T1
T2
Tnop
T1
Bus State Controller (BSC)
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WEn(BEn)
Write
D15 to D0
BS
DACKn*
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 9.4
Continuous Access for Normal Space 1, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 0 (Access Wait = 0, Cycle Wait = 0)
Rev. 3.00 Jan. 18, 2008 Page 339 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
T1
T2
T1
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D15 to D0
WEn(BEn)
Write
D15 to D0
BS
DACKn*
WAIT
Note: * The waveform for DACKn is when active low is specified.
Figure 9.5
Continuous Access for Normal Space 2, Bus Width = 16 bits, Longword Access,
CSnWCR.WM Bit = 1 (Access Wait = 0, Cycle Wait = 0)
Rev. 3.00 Jan. 18, 2008 Page 340 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
128k × 8-bit
SRAM
••••
••••
••••
••••
••••
••••
A0
CS
OE
I/O7
••••
••••
••••
A16
I/O0
WE
••••
••••
D0
WE0(BE0)
A16
••••
••••
D8
WE1(BE1)
D7
A0
CS
OE
I/O7
A0
CS
OE
I/O7
••••
••••
D16
WE2(BE2)
D15
A16
I/O0
WE
••••
••••
D24
WE3(BE3)
D23
••••
••••
A2
CSn
RD
D31
••••
••••
A18
••••
This LSI
••••
A16
A0
CS
OE
I/O7
••••
••••
••••
I/O0
WE
I/O0
WE
Figure 9.6
Example of 32-Bit Data-Width SRAM Connection
Rev. 3.00 Jan. 18, 2008 Page 341 of 1458
REJ09B0033-0300
Bus State Controller (BSC)
128k × 8-bit
SRAM
••••
••••
••••
••••
A0
CS
OE
I/O7
I/O0
WE
••••
••••
D0
WE0(BE0)
A16
••••
••••
D8
WE1(BE1)
D7
A16
••••
••••
A1
CSn
RD
D15
••••
••••
A17
••••
This LSI
A0
CS
OE
I/O7
••••
Section 9
I/O0
WE
Figure 9.7
Example of 16-Bit Data-Width SRAM Connection
128 k x 8 bits
SRAM
This LSI
A16
...
A0
CS
RD
OE
D7
I/O7
...
A0
CSn
...
...
A16
D0
I/O0
WE0(BE0)
WE
Figure 9.8
Example of 8-Bit Data-Width SRAM Connection
Rev. 3.00 Jan. 18, 2008 Page 342 of 1458
REJ09B0033-0300
Section 9
9.5.3
Bus State Controller (BSC)
Access Wait Control
Wait cycle insertion on a normal space access can be controlled by the settings of bits WR3 to
WR0 in CSnWCR. It is possible for areas 4, 5A, and 5B to insert wait cycles independently in
read access and in write access. The areas other than 4, 5A, and 5B have common access wait for
read cycle and write cycle. The specified number of Tw cycles is inserted as wait cycles in a
normal space access shown in figure 9.9.
T1
Tw
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn(BEn)
Write
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.9
Wait Timing for Normal Space Access (Software Wait Only)
When the WM bit in CSnWCR is cleared to 0, the external wait input WAIT signal is also
sampled. WAIT pin sampling is shown in figure 9.10. A 2-cycle wait is specified as a software
wait. The WAIT signal is sampled on the falling edge of CKIO at the transition from the T1 or Tw
cycle to the T2 cycle.
Rev. 3.00 Jan. 18, 2008 Page 343 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
T1
Tw
Tw
Wait states inserted
by WAIT signal
Twx
T2
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn(BEn)
Write
D31 to D0
WAIT
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.10 Wait State Timing for Normal Space Access
(Wait State Insertion using WAIT Signal)
Rev. 3.00 Jan. 18, 2008 Page 344 of 1458
REJ09B0033-0300
Section 9
9.5.4
Bus State Controller (BSC)
CSn Assert Period Expansion
The number of cycles from CSn assertion to RD and WEn (BEn) assertion can be specified by
setting bits SW1 and SW0 in CSnWCR. The number of cycles from RD and WEn (BEn) negation
to CSn negation can be specified by setting bits HW1 and HW0. Therefore, a flexible interface to
an external device can be obtained. Figure 9.11 shows an example. A Th cycle and a Tf cycle are
added before and after an ordinary cycle, respectively. In these cycles, RD and WEn (BEn) are not
asserted, while other signals are asserted. The data output is prolonged to the Tf cycle, and this
prolongation is useful for devices with slow writing operations.
Th
T1
T2
Tf
CKIO
A25 to A0
CSn
RD/WR
RD
Read
D31 to D0
WEn(BEn)
Write
D31 to D0
BS
DACKn*
Note: * The waveform for DACKn is when active low is specified.
Figure 9.11
CSn Assert Period Expansion
Rev. 3.00 Jan. 18, 2008 Page 345 of 1458
REJ09B0033-0300
Section 9
9.5.5
(1)
Bus State Controller (BSC)
SDRAM Interface
SDRAM Direct Connection
The SDRAM that can be connected to this LSI is a product that has 11/12/13 bits of row address,
8/9/10 bits of column address, 4 or less banks, and uses the A10 pin for setting precharge mode in
read and write command cycles.
The control signals for direct connection of SDRAM are RAS, CAS, RD/WR, DQMUU,
DQMUL, DQMLU, DQMLL, CKE, CS2, and CS3. All the signals other than CS2 and CS3 are
common to all areas, and signals other than CKE are valid when CS2 or CS3 is asserted. SDRAM
can be connected to up to 2 spaces. The data bus width of the area that is connected to SDRAM
can be set to 32 or 16 bits.
Burst read/single write (burst length 1) and burst read/burst write (burst length 1) are supported as
the SDRAM operating mode.
Commands for SDRAM can be specified by RAS, CAS, RD/WR, and specific address signals.
These commands are shown below.
•
•
•
•
•
•
•
•
•
•
•
NOP
Auto-refresh (REF)
Self-refresh (SELF)
All banks precharge (PALL)
Specified bank precharge (PRE)
Bank active (ACTV)
Read (READ)
Read with precharge (READA)
Write (WRIT)
Write with precharge (WRITA)
Write mode register (MRS)
The byte to be accessed is specified by DQMUU, DQMUL, DQMLU, and DQMLL. Reading or
writing is performed for a byte whose corresponding DQMxx is low. For details on the
relationship between DQMxx and the byte to be accessed, refer to section 9.5.1, Endian/Access
Size and Data Alignment.
Rev. 3.00 Jan. 18, 2008 Page 346 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Figures 9.12 and 9.13 show examples of the connection of the SDRAM with the LSI.
64-Mbit SDRAM
(1M x 16 bits x 4 banks)
A2
CKE
CKIO
CSn
...
RAS
CAS
RD/WR
D31
...
D16
DQMUU
DQMUL
D15
D0
DQMLU
DQMLL
...
A13
A0
CKE
CLK
CS
RAS
CAS
WE
I/O15
...
...
A15
I/O0
DQMU
DQML
A13
...
This LSI
A0
CKE
CLK
CS
...
RAS
CAS
WE
I/O15
I/O0
DQMU
DQML
Figure 9.12
Example of 32-Bit Data-Width SDRAM Connection
Rev. 3.00 Jan. 18, 2008 Page 347 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
64-Mbit SDRAM
(1M x 16 bits x 4 banks)
This LSI
A13
...
...
A14
A0
CKE
CLK
CS
A1
CKE
CKIO
CSn
RAS
CAS
WE
I/O15
...
...
RAS
CAS
RD/WR
D15
I/O0
DQMU
DQML
D0
DQMLU
DQMLL
Figure 9.13
(2)
Example of 16-Bit Data-Width SDRAM Connection
Address Multiplexing
An address multiplexing is specified so that SDRAM can be connected without external
multiplexing circuitry according to the setting of bits BSZ[1:0]in CSnBCR, AxROW[1:0] and
AxCOL[1:0] in SDCR. Tables 9.12 to 9.17 show the relationship between the settings of bits
BSZ[1:0], AxROW[1:0], and AxCOL[1:0] and the bits output at the address pins. Do not specify
those bits in the manner other than this table, otherwise the operation of this LSI is not guaranteed.
A25 to A18 are not multiplexed and the original values of address are always output at these pins.
When the data bus width is 16 bits (BSZ[1:0] =B'10), A0 of SDRAM specifies a word address.
Therefore, connect this A0 pin of SDRAM to the A1 pin of the LSI; the A1 pin of SDRAM to the
A2 pin of the LSI, and so on. When the data bus width is 32 bits (BSZ[1:0] =B'11), the A0 pin of
SDRAM specifies a longword address. Therefore, connect this A0 pin of SDRAM to the A2 pin of
the LSI; the A1 pin of SDRAM to the A3 pin of the LSI, and so on.
Rev. 3.00 Jan. 18, 2008 Page 348 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (1)-1
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits)
00 (11 bits)
00 (8 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A25
A17
A16
A24
A16
A15
A23
A14
Synchronous
DRAM Pin
Function
Unused
A15
2
A22*2
2
2
A22*
A12 (BA1)
Specifies bank
A13
A21*
A21*
A12
A20
L/H*1
A10/AP
A11 (BA0)
Specifies
address/precharge
A11
A19
A11
A9
Address
A10
A18
A10
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
A9
A1
A0
A8
A0
Unused
Example of connected memory
64-Mbit product (512 kwords x 32 bits x 4 banks, column 8 bits product): 1
16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 349 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.12 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (1)-2
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits)
01 (12 bits)
00 (8 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A24
A17
A16
A23
A15
Synchronous
DRAM Pin
Function
Unused
A16
2
A23*2
A13 (BA1)
2
2
A12 (BA0)
A23*
Specifies bank
A14
A22*
A22*
A13
A21
A13
A11
Address
A12
A20
L/H*1
A10/AP
Specifies
address/precharge
A11
A19
A11
A9
Address
A10
A18
A10
A8
A9
A17
A9
A7
A8
A16
A8
A6
A7
A15
A7
A5
A6
A14
A6
A4
A5
A13
A5
A3
A4
A12
A4
A2
A3
A11
A3
A1
A2
A10
A2
A0
A1
A9
A1
A0
A8
A0
Unused
Example of connected memory
128-Mbit product (1 Mword x 32 bits x 4 banks, column 8 bits product): 1
64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 350 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (2)-1
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits)
01 (12 bits)
01 (9 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A26
A17
A16
A25
A15
Synchronous
DRAM Pin
Function
Unused
A16
2
A24*2
A13 (BA1)
2
2
A12 (BA0)
A24*
Specifies bank
A14
A23*
A23*
A13
A22
A13
A11
Address
A12
A21
L/H*1
A10/AP
Specifies
address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
A0
A9
A0
Unused
Example of connected memory
256-Mbit product (2 Mwords x 32 bits x 4 banks, column 9 bits product): 1
128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 351 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.13 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (2)-2
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits)
01 (12 bits)
10 (10 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A27
A17
A16
A26
A15
Synchronous
DRAM Pin
Function
Unused
A16
2
A25*2
A13 (BA1)
2
2
A12 (BA0)
A25*
Specifies bank
A14
A24*
A24*
A13
A23
A13
A11
Address
A12
A22
L/H*1
A10/AP
Specifies
address/precharge
A11
A21
A11
A9
Address
A10
A20
A10
A8
A9
A19
A9
A7
A8
A18
A8
A6
A7
A17
A7
A5
A6
A16
A6
A4
A5
A15
A5
A3
A4
A14
A4
A2
A3
A13
A3
A1
A2
A12
A2
A0
A1
A11
A1
A0
A10
A0
Unused
Example of connected memory
512-Mbit product (4 Mwords x 32 bits x 4 banks, column 10 bits product): 1
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 352 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.14 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (3)
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
11 (32 bits)
10 (13 bits)
01 (9 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A26
A17
A16
2
A25*
2
Synchronous
DRAM Pin
Function
Unused
A25*
2
A14 (BA1)
2
A13 (BA0)
Specifies bank
A15
A24*
A24*
A14
A23
A14
A12
A13
A22
A13
A11
A12
A21
L/H*1
A10/AP
Specifies
address/precharge
A11
A20
A11
A9
Address
A10
A19
A10
A8
A9
A18
A9
A7
A8
A17
A8
A6
A7
A16
A7
A5
A6
A15
A6
A4
A5
A14
A5
A3
A4
A13
A4
A2
A3
A12
A3
A1
A2
A11
A2
A0
A1
A10
A1
A0
A9
A0
Address
Unused
Example of connected memory
512-Mbit product (4 Mwords x 32 bits x 4 banks, column 9 bits product): 1
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 2
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 353 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (4)-1
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
00 (11 bits)
00 (8 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A25
A17
A16
A24
A16
A15
A23
A15
A14
A22
Synchronous
DRAM Pin
Function
Unused
A14
A13
2
A21*
A21*2
A12 (BA1)
A12
A20*2
A20*2
A11 (BA0)
A11
A19
L/H*
A10
A18
A9
1
Specifies bank
A10/AP
Specifies
address/precharge
A10
A9
Address
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
A0
A8
A0
Unused
Example of connected memory
16-Mbit product (512 kwords x 16 bits x 2 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 354 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.15 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (4)-2
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
01 (12 bits)
00 (8 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A25
A17
A16
A24
A16
A15
A23
A14
Synchronous
DRAM Pin
Function
Unused
A15
2
A22*2
A13 (BA1)
2
2
A12 (BA0)
A22*
A13
A21*
A21*
A12
A20
A12
1
Specifies bank
A11
Address
A11
A19
L/H*
A10/AP
Specifies
address/precharge
A10
A18
A10
A9
Address
A9
A17
A9
A8
A8
A16
A8
A7
A7
A15
A7
A6
A6
A14
A6
A5
A5
A13
A5
A4
A4
A12
A4
A3
A3
A11
A3
A2
A2
A10
A2
A1
A1
A9
A1
A0
A0
A8
A0
Unused
Example of connected memory
64-Mbit product (1 Mword x 16 bits x 4 banks, column 8 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 355 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.16 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (5)-1
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
01 (12 bits)
01 (9 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A26
A17
A16
A25
A16
A15
A24
A14
Synchronous
DRAM Pin
Function
Unused
A15
2
A23*2
A13 (BA1)
2
2
A12 (BA0)
A23*
A13
A22*
A22*
A12
A21
A12
1
Specifies bank
A11
Address
A10/AP
Specifies
address/precharge
Address
A11
A20
L/H*
A10
A19
A10
A9
A9
A18
A9
A8
A8
A17
A8
A7
A7
A16
A7
A6
A6
A15
A6
A5
A5
A14
A5
A4
A4
A13
A4
A3
A3
A12
A3
A2
A2
A11
A2
A1
A1
A10
A1
A0
A0
A9
A0
Unused
Example of connected memory
128-Mbit product (2 Mwords x 16 bits x 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 356 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.16 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (5)-2
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
01 (12 bits)
10 (10 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A27
A17
A16
A26
A16
A15
A25
A14
Synchronous
DRAM Pin
Function
Unused
A15
2
A24*2
A13 (BA1)
2
2
A12 (BA0)
A24*
A13
A23*
A23*
A12
A22
A12
1
Specifies bank
A11
Address
A11
A21
L/H*
A10/AP
Specifies
address/precharge
A10
A20
A10
A9
Address
A9
A19
A9
A8
A8
A18
A8
A7
A7
A17
A7
A6
A6
A16
A6
A5
A5
A15
A5
A4
A4
A14
A4
A3
A3
A13
A3
A2
A2
A12
A2
A1
A1
A11
A1
A0
A0
A10
A0
Unused
Example of connected memory
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 357 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.17 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (6)-1
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
10 (13 bits)
01 (9 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A26
A17
A16
A25
A15
Synchronous
DRAM Pin
Function
Unused
A16
2
A24*2
A14 (BA1)
2
2
A13 (BA0)
A24*
A14
A23*
A23*
A13
A22
A13
A12
A12
A21
A12
A11
A11
A20
L/H*
A10
A19
A9
1
Specifies bank
Address
A10/AP
Specifies
address/precharge
A10
A9
Address
A18
A9
A8
A8
A17
A8
A7
A7
A16
A7
A6
A6
A15
A6
A5
A5
A14
A5
A4
A4
A13
A4
A3
A3
A12
A3
A2
A2
A11
A2
A1
A1
A10
A1
A0
A0
A9
A0
Unused
Example of connected memory
256-Mbit product (4 Mwords x 16 bits x 4 banks, column 9 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 358 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.17 Relationship between A2/3BSZ[1:0], A2/3ROW[1:0], A2/3COL[1:0], and
Address Multiplex Output (6)-2
Setting
A2/3
BSZ
[1:0]
A2/3
ROW
[1:0]
A2/3
COL
[1:0]
10 (16 bits)
10 (13 bits)
10 (10 bits)
Output Pin of
This LSI
Row Address
Output
Column Address
Output
A17
A27
A17
A16
A26
A15
Synchronous
DRAM Pin
Function
Unused
A16
2
A25*2
A14 (BA1)
2
2
A13 (BA0)
A25*
Specifies bank
A14
A24*
A24*
A13
A23
A13
A12
A12
A22
A12
A11
A11
A21
L/H*
A10/AP
Specifies
address/precharge
A10
A20
A10
A9
Address
A9
A19
A9
A8
A8
A18
A8
A7
A7
A17
A7
A6
A6
A16
A6
A5
A5
A15
A5
A4
A4
A14
A4
A3
A3
A13
A3
A2
A2
A12
A2
A1
A1
A11
A1
A0
A0
A10
A0
1
Address
Unused
Example of connected memory
512-Mbit product (8 Mwords x 16 bits x 4 banks, column 10 bits product): 1
Notes: 1. L/H is a bit used in the command specification; it is fixed at low or high according to the
access mode.
2. Bank address specification
Rev. 3.00 Jan. 18, 2008 Page 359 of 1458
REJ09B0033-0300
Section 9
(3)
Bus State Controller (BSC)
Burst Read
A burst read occurs in the following cases with this LSI.
1.
2.
3.
4.
Access size in reading is larger than data bus width.
16-byte transfer in cache miss.
16-byte transfer in DMAC or USDH(access to non-cacheable area)
16- to 128-byte transfer by LCDC*
This LSI always accesses the SDRAM with burst length 1. For example, read access of burst
length 1 is performed consecutively four times to read 16-byte continuous data from the SDRAM
that is connected to a 32-bit data bus.
Table 9.18 shows the relationship between the access size and the number of bursts.
Note: * For details, see section 26, LCD Controller (LCDC).
Table 9.18 Relationship between Access Size and Number of Bursts
Bus Width
Access Size
Number of Bursts
16 bits
8 bits
1
16 bits
1
32 bits
2
16 bytes
8
128 bytes
64
8 bits
1
16 bits
1
32 bits
1
16 bytes
4
128 bytes
32
32 bits
Figures 9.14 and 9.15 show a timing chart in burst read. In burst read, an ACTV command is
output in the Tr cycle, the READ command is issued in the Tc1, Tc2, and Tc3 cycles, the READA
command is issued in the Tc4 cycle, and the read data is received at the rising edge of the external
clock (CKIO) in the Td1 to Td4 cycles. The Tap cycle is used to wait for the completion of an
auto-precharge induced by the READ command in the SDRAM. In the Tap cycle, a new
command will not be issued to the same bank. However, access to another CS space or another
bank in the same SDRAM space is enabled. The number of Tap cycles is specified by the TRP1
and TRP0 bits in CS3WCR.
Rev. 3.00 Jan. 18, 2008 Page 360 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
In this LSI, wait cycles can be inserted by specifying each bit in CSnWCR to connect the SDRAM
in variable frequencies. Figure 9.15 shows an example in which wait cycles are inserted. The
number of cycles from the Tr cycle where the ACTV command is output to the Tc1 cycle where
the READA command is output can be specified using the TRCD1 and TRCD0 bits in CS3WCR.
If the TRCD1 and TRCD0 bits specify two cycles or more, a Trw cycle where the NOT command
is issued is inserted between the Tr cycle and Tc1 cycle. The number of cycles from the Tc1 cycle
where the READA command is output to the Td1 cycle where the read data is latched can be
specified for the CS2 and CS3 spaces independently, using the A2CL1 and A2CL0 bits in
CS2WCR or the A3CL1 and A3CL0 bits in CS3WCR and TRCD0 bit in CS3WCR. The number
of cycles from Tc1 to Td1 corresponds to the synchronous DRAM CAS latency. The CAS latency
for the synchronous DRAM is normally defined as up to three cycles. However, the CAS latency
in this LSI can be specified as 1 to 4 cycles. This CAS latency can be achieved by connecting a
latch circuit between this LSI and the synchronous DRAM.
Tr
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Td4
Tde
Tap
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.14
Burst Read Basic Timing (Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 361 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Tr
Trw
Tc1
Tw
Tc2
Td1
Tc3
Td2
Tc4
Td3
Td4
Tde
Tap
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.15
Burst Read Wait Specification Timing (Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 362 of 1458
REJ09B0033-0300
Section 9
(4)
Bus State Controller (BSC)
Single Read
A read access ends in one cycle when data exists in non-cacheable region and the data bus width is
larger than or equal to access size. As the burst length is set to 1 in SDRAM burst read/single
write mode, only the required data is output. Consequently, no unnecessary bus cycles are
generated even when a cache-through area is accessed.
Figure 9.16 shows the single read basic timing.
Tr
Tc1
Td1
Tde
Tap
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.16
Basic Timing for Single Read (Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 363 of 1458
REJ09B0033-0300
Section 9
(5)
Bus State Controller (BSC)
Burst Write
A burst write occurs in the following cases in this LSI.
1. Access size in writing is larger than data bus width.
2. Copyback of the cache
3. 16-byte transfer in DMAC (access to non-cacheable region)
This LSI always accesses SDRAM with burst length 1. For example, write access of burst length 1
is performed continuously 4 times to write 16-byte continuous data to the SDRAM that is
connected to a 32-bit data bus. The relationship between the access size and the number of bursts
is shown in table 9.18.
Figure 9.17 shows a timing chart for burst writes. In burst write, an ACTV command is output in
the Tr cycle, the WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and the WRITA
command is issued to execute an auto-precharge in the Tc4 cycle. In the write cycle, the write data
is output simultaneously with the write command. After the write command with the autoprecharge is output, the Trw1 cycle that waits for the auto-precharge initiation is followed by the
Tap cycle that waits for completion of the auto-precharge induced by the WRITA command in the
SDRAM. In the Tap cycle, a new command will not be issued to the same bank. However, access
to another CS space or another bank in the same SDRAM space is enabled. The number of Trw1
cycles is specified by the TRWL1 and TRWL0 bits in CS3WCR. The number of Tap cycles is
specified by the TRP1 and TRP0 bits in CS3WCR.
Rev. 3.00 Jan. 18, 2008 Page 364 of 1458
REJ09B0033-0300
Section 9
Tr
Tc1
Tc2
Tc3
Tc4
Trwl
Bus State Controller (BSC)
Tap
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.17
Basic Timing for Burst Write (Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 365 of 1458
REJ09B0033-0300
Section 9
(6)
Bus State Controller (BSC)
Single Write
A write access ends in one cycle when data is written in non-cacheable region and the data bus
width is larger than or equal to access size.
Figure 9.18 shows the single write basic timing.
Tr
Tc1
Trwl
Tap
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.18
Basic Timing for Single Write (Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 366 of 1458
REJ09B0033-0300
Section 9
(7)
Bus State Controller (BSC)
Bank Active
The SDRAM bank function is used to support high-speed accesses to the same row address. When
the BACTV bit in SDCR is 1, accesses are performed using commands without auto-precharge
(READ or WRIT). This function is called bank-active function. This function is valid only for
either the upper or lower bits of area 3. When area 3 is set to bank-active mode, area 2 should be
set to normal space or byte-selection SRAM. When areas 2 and 3 are both set to SDRAM, autoprecharge mode must be set.
When a bank-active function is used, precharging is not performed when the access ends. When
accessing the same row address in the same bank, it is possible to issue the READ or WRIT
command immediately, without issuing an ACTV command. As SDRAM is internally divided
into several banks, it is possible to activate one row address in each bank. If the next access is to a
different row address, a PRE command is first issued to precharge the relevant bank, then when
precharging is completed, the access is performed by issuing an ACTV command followed by a
READ or WRIT command. If this is followed by an access to a different row address, the access
time will be longer because of the precharging performed after the access request is issued. The
number of cycles between issuance of the PRE command and the ACTV command is determined
by the TRP[1:0] bits in CSnWCR.
In a write, when an auto-precharge is performed, a command cannot be issued to the same bank
for a period of Trwl + Tap cycles after issuance of the WRITA command. When bank active mode
is used, READ or WRIT commands can be issued successively if the row address is the same. The
number of cycles can thus be reduced by Trwl + Tap cycles for each write.
There is a limit on tRAS, the time for placing each bank in the active state. If there is no guarantee
that there will not be a cache hit and another row address will be accessed within the period in
which this value is maintained by program execution, it is necessary to set auto-refresh and set the
refresh cycle to no more than the maximum value of tRAS.
A burst read cycle without auto-precharge is shown in figure 9.19, a burst read cycle for the same
row address in figure 9.20, and a burst read cycle for different row addresses in figure 9.21.
Similarly, a single write cycle without auto-precharge is shown in figure 9.22, a single write cycle
for the same row address in figure 9.23, and a single write cycle for different row addresses in
figure 9.24.
In figure 9.20, a Tnop cycle in which no operation is performed is inserted before the Tc cycle that
issues the READ command. The Tnop cycle is inserted to acquire two cycles of CAS latency for
the DQMxx signal that specifies the read byte in the data read from the SDRAM. If the CAS
latency is specified as two cycles or more, the Tnop cycle is not inserted because the two cycles of
latency can be acquired even if the DQMxx signal is asserted after the Tc cycle.
Rev. 3.00 Jan. 18, 2008 Page 367 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
When bank active mode is set, if only accesses to the respective banks in the area 3 space are
considered, as long as accesses to the same row address continue, the operation starts with the
cycle in figure 9.19 or 9.22, followed by repetition of the cycle in figure 9.20 or 9.23. An access to
a different area during this time has no effect. If there is an access to a different row address in the
bank active state, after this is detected the bus cycle in figure 9.21 or 9.24 is executed instead of
that in figure 9.20 or 9.23. In bank active mode, too, all banks become inactive after a refresh
cycle or after the bus is released as the result of bus arbitration.
Tr
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Td4
Tde
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.19
Burst Read Timing (No Auto-Precharge)
Rev. 3.00 Jan. 18, 2008 Page 368 of 1458
REJ09B0033-0300
Section 9
Tnop
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Bus State Controller (BSC)
Td4
Tde
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.20
Burst Read Timing (Bank Active, Same Row Address)
Rev. 3.00 Jan. 18, 2008 Page 369 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Tp
Tpw
Tr
Tc1
Td1
Tc2
Td2
Tc3
Td3
Tc4
Td4
Tde
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.21
Burst Read Timing (Bank Active, Different Row Addresses)
Rev. 3.00 Jan. 18, 2008 Page 370 of 1458
REJ09B0033-0300
Section 9
Tr
Bus State Controller (BSC)
Tc1
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.22
Single Write Timing (No Auto-Precharge)
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Tnop
Tc1
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.23
Single Write Timing (Bank Active, Same Row Address)
Rev. 3.00 Jan. 18, 2008 Page 372 of 1458
REJ09B0033-0300
Section 9
Tp
Tpw
Tr
Bus State Controller (BSC)
Tc1
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.24
Single Write Timing (Bank Active, Different Row Addresses)
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REJ09B0033-0300
Section 9
(8)
Bus State Controller (BSC)
Refreshing
This LSI has a function for controlling SDRAM refreshing. Auto-refreshing can be performed by
clearing the RMODE bit to 0 and setting the RFSH bit to 1 in SDCR. A continuous refreshing can
be performed by setting the RRC[2:0] bits in RTCSR. If SDRAM is not accessed for a long
period, self-refresh mode, in which the power consumption for data retention is low, can be
activated by setting both the RMODE bit and the RFSH bit to 1.
(a)
Auto-refreshing
Refreshing is performed at intervals determined by the input clock selected by bits CKS[2:0] in
RTCSR, and the value set by in RTCOR. The value of bits CKS[2:0] in RTCOR should be set so
as to satisfy the refresh interval stipulation for the SDRAM used. First make the settings for
RTCOR, RTCNT, and the RMODE and RFSH bits in SDCR, then make the CKS[2:0] and
RRC[2:0] settings. When the clock is selected by bits CKS[2:0], RTCNT starts counting up from
the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if
the two values are the same, a refresh request is generated and an auto-refresh is performed for the
number of times specified by the RRC[2:0]. At the same time, RTCNT is cleared to 0 and the
count-up is restarted. Figure 9.25 shows the auto-refresh cycle timing.
After starting, the auto refreshing, PALL command is issued in the Tp cycle to make all the banks
to precharged state from active state when some bank is being precharged. Then REF command is
issued in the Trr cycle after inserting idle cycles of which number is specified by the TRP[1:0]bits
in CSnWCR. A new command is not issued for the duration of the number of cycles specified by
the TRC[1:0] bits in CSnWCR after the Trr cycle. The TRC[1:0] bits must be set so as to satisfy
the SDRAM refreshing cycle time stipulation (tRC). A NOP cycle is inserted between the Tp
cycle and Trr cycle when the setting value of the TRP[1:0] bits in CSnWCR is longer than or
equal to 2 cycles.
Rev. 3.00 Jan. 18, 2008 Page 374 of 1458
REJ09B0033-0300
Section 9
Tp
Tpw
Trr
Trc
Trc
Bus State Controller (BSC)
Trc
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
Hi-z
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.25
(b)
Auto-Refresh Timing
Self-refreshing
Self-refresh mode in which the refresh timing and refresh addresses are generated within the
SDRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit in SDCR
to 1. After starting the self-refreshing, PALL command is issued in Tp cycle after the completion
of the pre-charging bank. A SELF command is then issued after inserting idle cycles of which
number is specified by the TRP[1:0] bits in CSnWSR. SDRAM cannot be accessed while in the
self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh
mode has been cleared, command issuance is disabled for the number of cycles specified by the
TRC[1:0] bits in CSnWCR.
Self-refresh timing is shown in figure 9.26. Settings must be made so that self-refresh clearing and
data retention are performed correctly, and auto-refreshing is performed at the correct intervals.
When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting
standby mode other than through a power-on reset, auto-refreshing is restarted if the RFSH bit is
set to 1 and the RMODE bit is cleared to 0 when self-refresh mode is cleared. If the transition
from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be
Rev. 3.00 Jan. 18, 2008 Page 375 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less
than the RTCOR value will enable refreshing to be started immediately.
After self-refreshing has been set, the self-refresh state continues even if the chip standby state is
entered using the LSI standby function, and is maintained even after recovery from standby mode
by an interrupt.
The self-refresh state is not cleared by a manual reset.
In case of a power-on reset, the bus state controller's registers are initialized, and therefore the
self-refresh state is cleared.
Tp
Tpw
Trr
Trc
Trc
CKIO
CKE
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
Hi-z
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.26
Rev. 3.00 Jan. 18, 2008 Page 376 of 1458
REJ09B0033-0300
Self-Refresh Timing
Trc
Trc
Trc
Section 9
(9)
Bus State Controller (BSC)
Relationship between Refresh Requests and Bus Cycles
If a refresh request occurs during bus cycle execution, the refresh cycle must wait for the bus cycle
to be completed. If a refresh request occurs while the bus is released by the bus arbitration
function, the refresh will not be executed until the bus mastership is acquired. This LSI supports
requests by the REFOUT pin for the bus mastership while waiting for the refresh request. The
REFOUT pin is asserted low until the bus mastership is acquired.
If a new refresh request occurs while waiting for the previous refresh request, the previous refresh
request is deleted. To refresh correctly, a bus cycle longer than the refresh interval or the bus
mastership occupation must be prevented from occurring.
If a bus mastership is requested during self-refresh, the bus will not be released until the selfrefresh is completed.
Rev. 3.00 Jan. 18, 2008 Page 377 of 1458
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Section 9
Bus State Controller (BSC)
(10) Power-Down Mode
If the PDOWN bit in SDCR is set to 1, the SDRAM is placed in the power-down mode by
bringing the CKE signal to the low level in the non-access cycle. This power-down mode can
effectively lower the power consumption in the non-access cycle. However, please note that if an
access occurs in power-down mode, a cycle of overhead occurs because a cycle that asserts the
CKE in order to cancel power-down mode is inserted.
Figure 9.27 shows the access timing in power-down mode.
Power-down
Tnop
Tr
Tc1
Td1
Tde
Tap
CKIO
CKE
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.27
Access Timing in Power-Down Mode
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REJ09B0033-0300
Power-down
Section 9
Bus State Controller (BSC)
(11) Power-On Sequence
In order to use SDRAM, mode setting must first be performed after powering on. To perform
SDRAM initialization correctly, the bus state controller registers must first be set, followed by a
write to the SDRAM mode register. In SDRAM mode register setting, the address signal value at
that time is latched by a combination of the CSn, RAS, CAS, and RD/WR signals. If the value to
be set is X, the bus state controller provides for value X to be written to the SDRAM mode
register by performing a write to address H'A4FD4000 + X for area 2 SDRAM, and to address
H'A4FD5000 + X for area 3 SDRAM. In this operation the data is ignored, but the mode write is
performed as a byte-size access. To set burst read/single write, CAS latency 2 to 3, wrap type =
sequential, and burst length 1 supported by the LSI, arbitrary data is written in a byte-size access
to the addresses shown in table 9.19. In this time 0 is output at the external address pins of A12 or
later.
Rev. 3.00 Jan. 18, 2008 Page 379 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.19 Access Address in SDRAM Mode Register Write
• Setting for Area 2 (SDMR2)
Burst read/single write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'A4FD4440
H'0000440
3
H'A4FD4460
H'0000460
2
H'A4FD4880
H'0000880
3
H'A4FD48C0
H'00008C0
32 bits
Burst read/burst write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'A4FD4040
H'0000040
3
H'A4FD4060
H'0000060
2
H'A4FD4080
H'0000080
3
H'A4FD40C0
H'00000C0
32 bits
• Setting for Area 3 (SDMR3)
Burst read/single write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'A4FD5440
H'0000440
3
H'A4FD5460
H'0000460
2
H'A4FD5880
H'0000880
3
H'A4FD58C0
H'00008C0
32 bits
Burst read/burst write (burst length 1):
Data Bus Width
CAS Latency
Access Address
External Address Pin
16 bits
2
H'A4FD5040
H'0000040
3
H'A4FD5060
H'0000060
2
H'A4FD5080
H'0000080
3
H'A4FD50C0
H'00000C0
32 bits
Rev. 3.00 Jan. 18, 2008 Page 380 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Mode register setting timing is shown in figure 9.28. A PALL command (all bank precharge
command) is firstly issued. A REF command (auto-refresh command) is then issued 8 times. An
MRS command (mode register write command) is finally issued. Idle cycles, of which number is
specified by the TRP[1:0] bits in CSnWCR, are inserted between the PALL and the first REF. Idle
cycles, of which number is specified by the TRC[1:0]bits in CSnWCR, are inserted between REF
and REF, and between the 8th REF and MRS. Idle cycles, of which number is one or more, are
inserted between the MRS and a command to be issued next.
It is necessary to keep idle time of certain cycles for SDRAM before issuing PALL command after
power-on. Refer the manual of the SDRAM for the idle time to be needed. When the pulse width
of the reset signal is longer then the idle time, mode register setting can be started immediately
after the reset, but care should be taken when the pulse width of the reset signal is shorter than the
idle time.
Tp
PALL
Tpw
Trr
REF
Trc
Trc
Trr
REF
Trc
Trc
Tmw
MRS
Tnop
CKIO
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
Hi-Z
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.28
Write Timing for SDRAM Mode Register (Based on JEDEC)
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
(12) Low-Power SDRAM
The low-power SDRAM can be accessed using the same protocol as the normal SDRAM. The
differences between the low-power SDRAM and normal SDRAM are that partial refresh takes
place that puts only a part of the SDRAM in the self-refresh state during the self-refresh function,
and that power consumption is low during refresh under user conditions such as the operating
temperature. The partial refresh is effective in systems in which data in a work area other than the
specific area can be lost without severe repercussions. For details, refer to the data sheet for the
low-power SDRAM to be used.
The low-power SDRAM supports the extension mode register (EMRS) in addition to the mode
registers as the normal SDRAM. This LSI supports issuing of the EMRS command.
The EMRS command is issued according to the conditions specified in table 9.20. For example, if
data H'0YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued
to the CS3 space in the following sequence: PALL -> REF × 8 -> MRS -> EMRS. In this case, the
MRS and EMRS issue addresses are H'0000XXX and H'YYYYYYY, respectively. If data
H'1YYYYYYY is written to address H'A4FD5XXX in long-word, the commands are issued to the
CS3 space in the following sequence: PALL -> MRS -> EMRS.
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Section 9
Bus State Controller (BSC)
Table 9.20 Output Addresses when EMRS Command is Issued
Command to Access
be Issued
Address
Access Data
EMRS
Write
MRS Command Command Issue
Access Size Issue Address Address
CS2 MRS
H'A4FD4XXX
H'********
16 bits
H'0000XXX

CS3 MRS
H'A4FD5XXX
H'********
16 bits
H'0000XXX

CS2MRS
+EMRS
H'A4FD4XXX
H'0YYYYYYY
32 bits
H'0000XXX
H'YYYYYYY
H'A4FD5XXX
H'0YYYYYYY
32 bits
H'0000XXX
H'YYYYYYY
H'A4FD4XXX
H'1YYYYYYY
32 bits
H'0000XXX
H'YYYYYYY
H'A4FD5XXX
H'1YYYYYYY
32 bits
H'0000XXX
H'YYYYYYY
(with refresh)
CS3 MRS
+EMRS
(with refresh)
CS2 MRS
+EMRS
(without
refresh)
CS3 MRS
+EMRS
(without
refresh)
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Tp
PALL
Tpw
Trr
REF
Trc
Trc
Trr
REF
Trc
Trc
Tmw
MRS
Tnop
Temw
EMRS
Tnop
CKIO
A25 to A0
BA1*1
BA0*2
A12/A11*3
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
Hi-Z
BS
DACKn*4
Notes: 1. Address pin to be connected to the BA1 pin of SDRAM.
2. Address pin to be connected to the BA0 pin of SDRAM.
3. Address pin to be connected to the A10 pin of SDRAM.
4. The waveform for DACKn is when active low is specified.
Figure 9.29
EMRS Command Issue Timing
• Deep power-down mode
The low-power SDRAM supports the deep power-down mode as a low-power consumption
mode. In the partial self-refresh function, self-refresh is performed on a specific area. In the
deep power-down mode, self-refresh will not be performed on any memory area. This mode is
effective in systems where all of the system memory areas are used as work areas.
If the RMODE bit of the SDCR is set to 1 while the DEEP and RFSH bits of the SDCR are set to
1, the low-power SDRAM enters the deep power-down mode. If the RMODE bit is cleared to 0,
the CKE signal is pulled high to cancel the deep power-down mode. Before executing an access
after returning from the deep power-down mode, the power-up sequence must be re-executed.
Rev. 3.00 Jan. 18, 2008 Page 384 of 1458
REJ09B0033-0300
Section 9
Tp
Tpw
Tdpd
Trc
Trc
Trc
Trc
Bus State Controller (BSC)
Trc
CKIO
CKE
A25 to A0
A12/A11*1
CSn
RAS
CAS
RD/WR
DQMxx
D31 to D0
Hi-Z
BS
DACKn*2
Notes: 1. Address pin to be connected to the A10 pin of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.30
9.5.6
Transition Timing in Deep Power-Down Mode
Burst ROM (Clock Asynchronous) Interface
The burst ROM (clock asynchronous) interface is used to access a memory with a high-speed read
function using a method of address switching called the burst mode or page mode. In a burst ROM
(clock asynchronous) interface, basically the same access as the normal space is performed, but
the 2nd and subsequent accesses are performed only by changing the address, without negating the
RD signal at the end of the 1st cycle. In the 2nd and subsequent accesses, addresses are changed at
the falling edge of the CKIO.
For the 1st access cycle, the number of wait cycles specified by the W[3:0] bits in CSnWCR is
inserted. For the 2nd and subsequent access cycles, the number of wait cycles specified by the
BW[1:0] bits in CSnWCR is inserted.
In the access to the burst ROM (clock asynchronous), the BS signal is asserted only to the first
access cycle. An external wait input is valid only to the first access cycle.
In the single access or write access that do not perform the burst operation in the burst ROM
(clock asynchronous) interface, access timing is same as a normal space.
Rev. 3.00 Jan. 18, 2008 Page 385 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Table 9.21 lists a relationship between bus width, access size, and the number of bursts. Figure
9.31 shows a timing chart.
Table 9.21 Relationship between Bus Width, Access Size, and Number of Bursts
Bus Width
BEN Bit
Access Size
Number of
Bursts
Number of
Accesses
8 bits
Not affected
8 bits
1
1
Not affected
16 bits
2
1
Not affected
32 bits
4
1
0
16 bytes
16
1
4
4
1
16 bits
Not affected
8 bits
1
1
Not affected
16 bits
1
1
Not affected
32 bits
2
1
0
16 bytes
8
1
2
4
1
32 bits
Not affected
8 bits
1
1
Not affected
16 bits
1
1
Not affected
32 bits
1
1
Not affected
16 bytes
4
1
Rev. 3.00 Jan. 18, 2008 Page 386 of 1458
REJ09B0033-0300
Section 9
T1
Tw
Tw
TB2
Twb
TB2
Twb
TB2
Bus State Controller (BSC)
Twb
T2
CKIO
Address
CS
RD/WR
RD
Data
WAIT
BS
DACK
Figure 9.31 Burst ROM (Clock Asynchronous) Access (Bus Width = 32 Bits,
16-byte Transfer (Number of Bursts = 4), Access Wait for First Time = 2,
Access Wait for 2nd Time and after = 1)
9.5.7
Byte-Selection SRAM Interface
The byte-selection SRAM interface is for access to an SRAM which has a byte-selection pin
(WEn (BEn)). This interface has 16-bit data pins and accesses SRAMs having upper and lower
byte selection pins, such as UB and LB.
When the BAS bit in CSnWCR is cleared to 0 (initial value), the write access timing of the byteselection SRAM interface is the same as that for the normal space interface. While in read access
of a byte-selection SRAM interface, the byte-selection signal is output from the WEn (BEn) pin,
which is different from that for the normal space interface. The basic access timing is shown in
figure 9.32. In write access, data is written to the memory according to the timing of the byteselection pin (WEn (BEn)). For details, refer to the data sheet for the corresponding memory.
If the BAS bit in CSnWCR is set to 1, the WEn (BEn) pin and RD/WR pin timings change. Figure
9.33 shows the basic access timing. In write access, data is written to the memory according to the
timing of the write enable pin (RD/WR). The data hold timing from RD/WR negation to data write
must be acquired by setting the HW[1:0] bits in CSnWCR. Figure 9.34 shows the access timing
when a software wait is specified.
Rev. 3.00 Jan. 18, 2008 Page 387 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
T2
T1
CKIO
A25 to A0
CSn
WEn(BEn)
RD/WR
Read
RD
D31 to D0
RD/WR
Write
RD
High
D31 to D0
BS
DACKn*
Note: The waveform for DACKn is when active low is specified.
Figure 9.32
Basic Access Timing for Byte-Selection SRAM (BAS = 0)
Rev. 3.00 Jan. 18, 2008 Page 388 of 1458
REJ09B0033-0300
Section 9
T1
Bus State Controller (BSC)
T2
CKIO
A25 to A0
CSn
WEn(BEn)
RD/WR
Read
RD
D31 to D0
RD/WR
Write
High
RD
D31 to D0
BS
DACKn*
Note: The waveform for DACKn is when active low is specified.
Figure 9.33
Basic Access Timing for Byte-Selection SRAM (BAS = 1)
Rev. 3.00 Jan. 18, 2008 Page 389 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
Th
T1
Tw
T2
Tf
CKIO
A25 to A0
CSn
WEn(BEn)
RD/WR
Read
RD
D31 to D0
RD/WR
High
RD
Write
D31 to D0
BS
DACKn*
Note: The waveform for DACKn is when active low is specified.
Figure 9.34
Wait Timing for Byte-Selection SRAM (BAS = 1) (Software Wait Only)
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
64 k x 16 bits
SRAM
This LSI
A17
...
...
A15
A2
A0
CSn
CS
RD
OE
RD/WR
WE
D31
...
...
I/O15
D16
I/O0
WE3(BE3)
UB
WE2(BE2)
LB
...
D15
...
A15
D0
WE1(BE1)
A0
WE0(BE0)
CS
OE
WE
...
I/O15
I/O0
UB
LB
Figure 9.35
Example of Connection with 32-Bit Data-Width Byte-Selection SRAM
64Kx16bit
SRAM
This LSI
A16
A1
A0
CSn
CS
RD
RD/WR
D15
D0
WE1(BE1)
WE0(BE0)
Figure 9.36
A15
OE
WE
I/O 15
I/O 0
UB
LB
Example of Connection with 16-Bit Data-Width Byte-Selection SRAM
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Section 9
9.5.8
Bus State Controller (BSC)
PCMCIA Interface
With this LSI, if address map (2) is selected using the MAP bit in CMNCR, the PCMCIA
interface can be specified in areas 5 and 6. Areas 5 and 6 in the physical space can be used for the
IC memory card and I/O card interface defined in the JEIDA specifications version 4.2
(PCMCIA2.1 Rev. 2.1) by specifying the TYPE[3:0] bits of CSnBCR (n = 5B, 6B) to B'0101. In
addition, the SA[1:0] bits of CSnWCR (n = 5B, 6B) assign the upper or lower 32 Mbytes of each
area to an IC memory card or I/O card interface. For example, if the SA1 and SA0 bits of the
CS5BWCR are set to 1 and cleared to 0, respectively, the upper 32 Mbytes and the lower 32
Mbytes of area 5B are used as an IC memory card interface and I/O card interface, respectively.
When the PCMCIA interface is used, the bus size must be specified as 8 bits or 16 bits using the
BSZ[1:0] bits in CS5BBCR or CS6BBCR.
Figure 9.37 shows an example of a connection between this LSI and the PCMCIA card. To enable
insertion and removal of the PCMCIA card during system power-on, a three-state buffer must be
connected between the LSI and the PCMCIA card.
In the JEIDA and PCMCIA standards, operation in the big endian mode is not clearly defined.
Consequently, an original definition is provided for the PCMCIA interface in big endian mode in
this LSI.
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Section 9
Bus State Controller (BSC)
PC card
(memory I/O)
This LSI
A25 to A0
G
A25 to A0
D7 to D0
D15 to D8
D7 to D0
RD/WR
CE1A
CE2A
G
DIR
D15 to D8
G
DIR
CE1
CE2
RD
OE
WE
WE/PGM
ICIORD
IORD
ICIOWR
IOWR
REG
I/O Port
G
WAIT
WAIT
IOIS16
IOIS16
Card
detection
circuit
Figure 9.37
CD1,CD2
Example of PCMCIA Interface Connection
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REJ09B0033-0300
Section 9
(1)
Bus State Controller (BSC)
Basic Timing for Memory Card Interface
Figure 9.38 shows the basic timing of the PCMCIA IC memory card interface. If areas 5 and 6 in
the physical space are specified as the PCMCIA interface, accessing the common memory areas in
areas 5 and 6 automatically accesses the IC memory card interface. If the external bus frequency
(CKIO) increases, the setup times and hold times for the address pins (A25 to A0) to RD and WE,
card enable signals (CE1A, CE2A, CE1B, CE2B), and write data (D15 to D0) become
insufficient. To prevent this error, the LSI can specify the setup times and hold times for areas 5
and 6 in the physical space independently, using CS5BWCR and CS6BWCR. In the PCMCIA
interface, as in the normal space interface, a software wait or hardware wait can be inserted using
the WAIT pin. Figure 9.39 shows the PCMCIA memory bus wait timing.
Tpcm1
Tpcm1w
Tpcm1w
Tpcm1w
Tpcm2
CKIO
A25 to A0
CExx
RD/WR
RD
Read
D15 to D0
WE
Write
D15 to D0
BS
Figure 9.38
Basic Access Timing for PCMCIA Memory Card Interface
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REJ09B0033-0300
Section 9
Tpcm0
Tpcm0w
Tpcm1
Tpcm1w
Tpcm1w Tpcm1w
Bus State Controller (BSC)
Tpcm1w
Tpcm2
Tpcm2w
CKIO
A25 to A0
CExx
RD/WR
RD
Read
D15 to D0
WE
Write
D15 to D0
BS
WAIT
Figure 9.39 Wait Timing for PCMCIA Memory Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)
If all 32 Mbytes of the memory space are used as an IC memory card interface, the REG signal
that switches between the common memory and attribute memory can be generated by an I/O port.
If the memory space used for the IC memory card interface is 16 Mbytes or less, the A24 pin can
be used as the REG signal by using the memory space as a 16-Mbyte common memory space and
a 16-Mbyte attribute memory space.
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
PCMCIA interface area is 32 Mbytes (An I/O port is used as the REG)
Area 5 : H'14000000
Attribute memory/common memory
Area 5 : H'16000000
I/O space
Area 6 : H'18000000
Attribute memory/common memory
Area 6 : H'1A000000
I/O space
PCMCIA interface area is 16 Mbytes (A24 is used as the REG)
Area 5 : H'14000000
Area 5 : H'15000000
Area 5 : H'16000000
Attribute memory
Common memory
I/O space
H'17000000
Area 6 : H'18000000
Area 6 : H'19000000
Area 6 : H'1A000000
Attribute memory
Common memory
I/O space
H'1B000000
Figure 9.40
Example of PCMCIA Space Assignment (CS5BWCR.SA[1:0] = B'10,
CS6BWCR.SA[1:0] = B'10)
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Section 9
(2)
Bus State Controller (BSC)
Basic Timing for I/O Card Interface
Figures 9.41 and 9.42 show the basic timings for the PCMCIA I/O card interface.
The I/O card and IC memory card interfaces can be switched using an address to be accessed. If
area 5 of the physical space is specified as the PCMCIA, the I/O card interface can automatically
be accessed by accessing the physical addresses from H'16000000 to H'17FFFFFF. If area 6 of the
physical space is specified as the PCMCIA, the I/O card interface can automatically be accessed
by accessing the physical addresses from H'1A000000 to H'1BFFFFFF.
Note that areas to be accessed as the PCMCIA I/O card must be non-cached if they are virtual
space (space P2 or P3) areas, or a non-cached area specified by the MMU.
If the PCMCIA card is accessed as an I/O card in little endian mode, dynamic bus sizing for the
I/O bus can be achieved using the IOIS16 signal. If the IOIS16 signal is brought high in a wordsize I/O bus cycle while the bus width of area 6 is specified as 16 bits, the bus width is recognized
as 8 bits and data is accessed twice in 8-bit units in the I/O bus cycle to be executed.
The IOIS16 signal is sampled at the falling edge of CKIO in the Tpci0, Tpci0w, and Tpci1 cycles
when the TED[3:0] bits are specified as 1.5 cycles or more, and is reflected in the CE2 signal 1.5
cycles after the CKIO sampling point. The TED[3:0] bits must be specified appropriately to satisfy
the setup time from ICIORD and ICIOWR of the PC card to CEn.
Figure 9.43 shows the dynamic bus sizing basic timing.
Note that the IOIS16 signal is not supported in big endian mode. In the big endian mode, the
IOIS16 signal must be fixed low.
Rev. 3.00 Jan. 18, 2008 Page 397 of 1458
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Section 9
Bus State Controller (BSC)
Tpci1
Tpci1w
Tpci1w
Tpci1w
Tpci2
CKIO
A25 to A0
CExx
RD/WR
ICIORD
Read
D15 to D0
ICIOWR
Write
D15 to D0
BS
Figure 9.41
Basic Timing for PCMCIA I/O Card Interface
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REJ09B0033-0300
Section 9
Tpci0
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci1w
Bus State Controller (BSC)
Tpci1w
Tpci2
Tpci2w
CKIO
A25 to A0
CExx
RD/WR
ICIORD
Read
D15 to D0
ICIOWR
Write
D15 to D0
BS
WAIT
IOIS16
Figure 9.42 Wait Timing for PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Wait = 1, Hardware Wait = 1)
Tpci0
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci1w
Tpci1w
Tpci2
Tpci2w
Tpci0
Tpci0w
Tpci1
Tpci1w
Tpci1w
Tpci1w
Tpci1w
Tpci2
Tpci2w
CKIO
A25 to A0
CE1x
CE2x
RD/WR
ICIORD
Read
D15 to D0
ICIOWR
Write
D15 to D0
BS
WAIT
IOIS16
Figure 9.43 Timing for Dynamic Bus Sizing of PCMCIA I/O Card Interface
(TED[3:0] = B'0010, TEH[3:0] = B'0001, Software Waits = 3)
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Section 9
9.5.9
Bus State Controller (BSC)
Burst ROM (Clock Synchronous) Interface
The burst ROM (clock synchronous) interface is supported to access a ROM with a synchronous
burst function at high speed. The burst ROM interface accesses the burst ROM in the same way as
a normal space. This interface is valid only for area 0.
In the first access cycle, wait cycles are inserted. In this case, the number of wait cycles to be
inserted is specified by the W[3:0] bits of the CS0WCR. In the second and subsequent cycles, the
number of wait cycles to be inserted is specified by the BW[1:0] bits of the CS0WCR.
While the burst ROM is accessed (clock synchronous), the BS signal is asserted only for the first
access cycle and an external wait input is also valid for the first access cycle.
If the bus width is 16 bits, the burst length must be specified as 8. If the bus width is 32 bits, the
burst length must be specified as 4. The burst ROM interface does not support the 8-bit bus width
for the burst ROM. The burst ROM interface performs burst operations for all read accesses. For
example, in a longword access over a 16-bit bus, valid 16-bit data is read two times and invalid
16-bit data is read six times.
These invalid data read cycles increase the memory access time and degrade the program
execution speed and DMA transfer speed. To prevent this problem, a 16-byte read by cache fill or
16-byte read by the DMA should be used. The burst ROM interface performs write accesses in the
same way as normal space access.
T1
Tw
Tw
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
Twb
T2B
CKIO
Address
CSn
RD/WR
RD
D15 to D0
WAIT
BS
DACKn*
Note: The waveform for DACKn is when active low is specified.
Figure 9.44 Burst ROM (Clock Synchronous) Access Timing
(Burst Length = 8, Wait Cycles inserted in First Access = 2,
Wait Cycles inserted in Second and Subsequent Accesses = 1)
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REJ09B0033-0300
Twb
T2
Section 9
9.5.10
Bus State Controller (BSC)
Wait between Access Cycles
As the operating frequency of LSIs becomes higher, the off-operation of the data buffer often
collides with the next data access when the read operation from devices with slow access speed is
completed. As a result of these collisions, the reliability of the device is low and malfunctions may
occur. This LSI has a function that avoids data collisions by inserting wait cycles between
continuous access cycles.
The number of wait cycles between access cycles can be set by bits IWW[2:0], IWRWD[2:0],
IWRWS[2:0], IWRRD[2:0], and IWRRS[2:0] in CSnBCR, and bits DMAIW[2:0] and DMAIWA
in CMNCR. The conditions for setting the wait cycles between access cycles (idle cycles) are
shown below.
1.
2.
3.
4.
5.
6.
Continuous accesses are write-read or write-write
Continuous accesses are read-write for different spaces
Continuous accesses are read-write for the same space
Continuous accesses are read-read for different spaces
Continuous accesses are read-read for the same space
Data output from an external device caused by DMA single transfer is followed by data output
from another device that includes this LSI (DMAIWA = 0)
7. Data output from an external device caused by DMA single transfer is followed by any type of
access (DMAIWA = 1)
9.5.11
Bus Arbitration
To prevent device malfunction while the bus mastership is transferred between master and slave,
the LSI negates all of the bus control signals before bus release. When the bus mastership is
received, all of the bus control signals are first negated and then driven appropriately. In this case,
output buffer contention can be prevented because the master and slave drive the same signals
with the same values. In addition, to prevent noise while the bus control signal is in the high
impedance state, pull-up resistors must be connected to these control signals.
Bus mastership is transferred at the boundary of bus cycles. Namely, bus mastership is released
immediately after receiving a bus request when a bus cycle is not being performed. The release of
bus mastership is delayed until the bus cycle is complete when a bus cycle is in progress. Even
when from outside the LSI it looks like a bus cycle is not being performed, a bus cycle may be
performing internally, started by inserting wait cycles between access cycles. Therefore, it cannot
be immediately determined whether or not bus mastership has been released by looking at the CSn
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Section 9
Bus State Controller (BSC)
signal or other bus control signals. The states that do not allow bus mastership release are shown
below.
1.
2.
3.
4.
5.
6.
7.
8.
16-byte transfer because of a cache miss
During copyback operation for the cache
Between the read and write cycles of a TAS instruction
Multiple bus cycles generated when the data bus width is smaller than the access size (for
example, between bus cycles when longword access is made to a memory with a data bus
width of 8 bits)
16-byte transfer by the DMAC or USBH
Setting the BLOCK bit in CMNCR to 1
16 to 128-byte transfer by LCDC
Transfer by USBH
Bits DPRTY[1:0] in CMNCR can select whether or not the bus request is received during DMAC
burst transfer.
This LSI has the bus mastership until a bus request is received from another device. Upon
acknowledging the assertion (low level) of the external bus request signal BREQ, the LSI releases
the bus at the completion of the current bus cycle and asserts the BACK signal. After the LSI
acknowledges the negation (high level) of the BREQ signal that indicates the slave has released
the bus, it negates the BACK signal and resumes the bus usage.
The SDRAM issues an all bank precharge command (PALL) when active banks exist and releases
the bus after completion of a PALL command.
The bus sequence is as follows. The address bus and data bus are placed in a high-impedance state
synchronized with the rising edge of CKIO. The bus mastership enable signal is asserted 0.5
cycles after the above timing, synchronized with the falling edge of CKIO. The bus control signals
(BS, CSn, RAS, CAS, DQMxx, WEn (BEn), RD, and RD/WR) are placed in the high-impedance
state at subsequent rising edges of CKIO. Bus request signals are sampled at the falling edge of
CKIO.
The sequence for reclaiming the bus mastership from a slave is described below. 1.5 cycles after
the negation of BREQ is detected at the falling edge of CKIO, the bus control signals are driven
high. The BACK is negated at the next falling edge of the clock. The fastest timing at which actual
bus cycles can be resumed after bus control signal assertion is at the rising edge of the CKIO
where address and data signals are driven. Figure 9.45 shows the bus arbitration timing.
In an original slave device designed by the user, multiple bus accesses are generated continuously
to reduce the overhead caused by bus arbitration. In this case, to execute SDRAM refresh
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REJ09B0033-0300
Section 9
Bus State Controller (BSC)
correctly, the slave device must be designed to release the bus mastership within the refresh
interval time. To achieve this, the LSI instructs the REFOUT pin to request the bus mastership
while the SDRAM waits for the refresh. The LSI asserts the REFOUT pin until the bus mastership
is received. If the slave releases the bus, the LSI acquires the bus mastership to execute the
SDRAM refresh.
The bus release by the BREQ and BACK signal handshaking requires some overhead. If the slave
has many tasks, multiple bus cycles should be executed in a bus mastership acquisition. Reducing
the cycles required for master to slave bus mastership transitions streamlines the system design.
CKIO
BREQ
BACK
A25 to A0
D31 to D0
CSn
Other bus
control signals
Figure 9.45
Bus Arbitration Timing
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REJ09B0033-0300
Section 9
9.6
(1)
Bus State Controller (BSC)
Usage Notes
Reset
The bus state controller (BSC) can be initialized completely only at power-on reset. At power-on
reset, all signals are negated and output buffers are turned off regardless of the bus cycle state. All
control registers are initialized. In standby, sleep, and manual reset, control registers of the bus
state controller are not initialized. At manual reset, the current bus cycle being executed is
completed and then the access wait state is entered. If a 16-byte transfer is performed by a cache
or if another LSI on-chip bus master module is executed when a manual reset occurs, the current
access is cancelled in longword units because the access request is cancelled by the bus master at
manual reset. If a manual reset is requested during cache fill operations, the contents of the cache
cannot be guaranteed. Since the RTCNT continues counting up during manual reset signal
assertion, a refresh request occurs to initiate the refresh cycle. In addition, a bus arbitration request
by the BREQ signal can be accepted during manual reset signal assertion.
Some flash memories may specify a minimum time from reset release to the first access. To
ensure this minimum time, the bus state controller supports a 5-bit counter (RWTCNT). At poweron reset, the RWTCNT is cleared to 0. After power-on reset, RWTCNT is counted up
synchronously together with CKIO and an external access will not be generated until RWTCNT is
counted up to H′001F. At manual reset, RWTCNT is not cleared.
(2)
Access from the Site of the LSI Internal Bus Master
There are three types of LSI internal buses: a cache bus, internal bus, and peripheral bus. The CPU
and cache memory are connected to the cache bus. Internal bus masters other than the CPU and
bus state controller are connected to the internal bus. Low-speed peripheral modules are connected
to the peripheral bus. Internal memories other than the cache memory and debugging modules
such as a UBC and AUD are connected bidirectionally to the cache bus and internal bus. Access
from the cache bus to the internal bus is enabled but access from the internal bus to the cache bus
is disabled. This gives rise to the following problems.
Internal bus masters such as DMAC other than the CPU can access on-chip memory other than the
cache memory but cannot access the cache memory. If an on-chip bus master other than the CPU
writes data to an external memory other than the cache, the contents of the external memory may
differ from that of the cache memory. To prevent this problem, if the external memory whose
contents is cached is written by an on-chip bus master other than the CPU, the corresponding
cache memory should be purged by software.
If the CPU initiates read access for the cache, the cache is searched. If the cache stores data, the
CPU latches the data and completes the read access. If the cache does not store data, the CPU
Rev. 3.00 Jan. 18, 2008 Page 404 of 1458
REJ09B0033-0300
Section 9
Bus State Controller (BSC)
performs four contiguous longword read cycles to perform cache fill operations via the internal
bus. If a cache miss occurs in byte or word operand access or at a branch to an odd word boundary
(4n + 2), the CPU performs four contiguous longword accesses to perform a cache fill operation
on the external interface. For a cache-through area, the CPU performs access according to the
actual access addresses. For an instruction fetch to an even word boundary (4n), the CPU performs
longword access. For an instruction fetch to an odd word boundary (4n + 2), the CPU performs
word access.
For a read cycle of a cache-through area or an on-chip peripheral module, the read cycle is first
accepted and then read cycle is initiated. The read data is sent to the CPU via the cache bus.
In a write cycle for the cache area, the write cycle operation differs according to the cache write
methods.
In write-back mode, the cache is first searched. If data is detected at the address corresponding to
the cache, the data is then re-written to the cache. In the actual memory, data will not be re-written
until data in the corresponding address is re-written. If data is not detected at the address
corresponding to the cache, the cache is modified. In this case, data to be modified is first saved to
the internal buffer, 16-byte data including the data corresponding to the address is then read, and
data in the corresponding access of the cache is finally modified. Following these operations, a
write-back cycle for the saved 16-byte data is executed.
In write-through mode, the cache is first searched. If data is detected at the address corresponding
to the cache, the data is re-written to the cache simultaneously with the actual write via the internal
bus. If data is not detected at the address corresponding to the cache, the cache is not modified but
an actual write is performed via the internal bus.
Since the bus state controller (BSC) incorporates a one-stage write buffer, the BSC can execute an
access via the internal bus before the previous external bus cycle is completed in a write cycle. If
the on-chip module is read or written after the external low-speed memory is written, the on-chip
module can be accessed before the completion of the external low-speed memory write cycle.
In read cycles, the CPU is placed in the wait state until read operation has been completed. To
continue the process after the data write to the device has been completed, perform a dummy read
to the same address to check for completion of the write before the next process to be executed.
The write buffer of the BSC functions in the same way for an access by a bus master other than the
CPU such as the DMAC. Accordingly, to perform dual address DMA transfers, the next read cycle
is initiated before the previous write cycle is completed. Note, however, that if both the DMA
source and destination addresses exist in external memory space, the next write cycle will not be
initiated until the previous write cycle is completed.
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REJ09B0033-0300
Section 9
(3)
Bus State Controller (BSC)
On-Chip Peripheral Module Access
To access an on-chip module register, two or more peripheral module clock (Pφ) cycles are
required. Care must be taken in system design.
(4)
External Bus Priority Order
Access via an external bus is performed in the priority order below:
BREQ > Refresh > LCDC > USBH > DMAC > CPU
Note that next transfer is not performed until current transfer (e.g. burst transfer) has completed.
Rev. 3.00 Jan. 18, 2008 Page 406 of 1458
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Section 10
Section 10
Direct Memory Access Controller (DMAC)
Direct Memory Access Controller (DMAC)
This LSI includes the direct memory access controller (DMAC).
The DMAC can be used in place of the CPU to perform high-speed transfers between external
devices that have DACK (transfer request acknowledge signal), external memory, on-chip
memory, memory-mapped external devices, and on-chip peripheral modules.
10.1
Features
• Six channels (two channels can receive an external request)
• 4-Gbyte physical address space
• Data transfer unit is selectable: Byte, word (2 bytes), longword (4 bytes), and 16 bytes
(longword × 4)
• Maximum transfer count: 16,777,216 transfers
• Address mode: Dual address mode or single address mode can be selected.
• Transfer requests:
External request, on-chip peripheral module request, or auto request can be selected.
The following modules can issue an on-chip peripheral module request.
 SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, ADC, and
SDHI
• Selectable bus modes:
Cycle steal mode (normal mode and intermittent mode) or burst mode can be selected.
• Selectable channel priority levels:
The channel priority levels are selectable between fixed mode and round-robin mode.
• Interrupt request: An interrupt request can be generated to the CPU after transfers end by the
specified counts.
• External request detection: There are following four types of DREQ input detection.
 Low level detection
 High level detection
 Rising edge detection
 Falling edge detection
• Transfer request acknowledge signal:
Active levels for DACK and TEND can be set independently.
DMAS301A_010020030200
Rev. 3.00 Jan. 18, 2008 Page 407 of 1458
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Section 10
Direct Memory Access Controller (DMAC)
Figure 10.1 shows the block diagram of the DMAC.
DMAC module
SARn
Iteration
control
On-chip
memory
DARn
Register
control
Internal bus
Peripheral bus
On-chip peripheral
module
DMATCRn
Start-up
control
CHCRn
DMA transfer
request signal
DMAOR
DMA transfer acknowledge signal
DEIn
Interrupt controller
External
ROM
Request
priority
control
DMARS0 to
DMARS2
Bus
interface
External
RAM
External
I/O (memory
mapped)
External
I/O (with
acknowledgement)
Bus state
controller
DACK0, DACK1
TEND0, TEND1
[Legend]
SARn:
DARn:
DMATCRn:
CHCRn:
DMAOR:
DMARS0 to
DMARS2:
DEIn:
n:
DMA source address register
DMA destination address register
DMA transfer count register
DMA channel control register
DMA operation register
DMA extended resource selector 0 to 2
DMA transfer-end interrupt request to the CPU
0, 1, 2, 3, 4, 5
DREQ0, DREQ1
Figure 10.1
Rev. 3.00 Jan. 18, 2008 Page 408 of 1458
REJ09B0033-0300
Block Diagram of DMAC
Section 10
10.2
Direct Memory Access Controller (DMAC)
Input/Output Pins
The external pins for the DMAC are described below. Table 10.1 lists the configuration of the pins
that are connected to external bus. The DMAC has pins for 2 channels (channels 0 and 1) for
external bus use.
Table 10.1 Pin Configuration
Channel Name
Pin Name
I/O
Function
0
DMA transfer request
DREQ0
Input
DMA transfer request input from
external device to channel 0
DMA transfer request
reception
DACK0
Output DMA transfer request acknowledge
output from channel 0 to external
device
DMA transfer end
TEND0
Output DMA transfer end of DMAC channel 0
output of
DMA transfer request
DREQ1
Input
DMA transfer request
reception
DACK1
Output DMA transfer request acknowledge
output from channel 1 to external
device
DMA transfer end
TEND1
Output DMA transfer end of DMAC channel 1
output
1
DMA transfer request input from
external device to channel 1
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Section 10
10.3
Direct Memory Access Controller (DMAC)
Register Descriptions
The DMAC has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and states of these registers in each operating mode. The SAR for channel 0 is
expressed such as SAR_0.
(1) Channel 0
•
•
•
•
DMA source address register_0 (SAR_0)
DMA destination address register_0 (DAR_0)
DMA transfer count register_0 (DMATCR_0)
DMA channel control register_0 (CHCR_0)
(2) Channel 1
•
•
•
•
DMA source address register_1 (SAR_1)
DMA destination address register_1 (DAR_1)
DMA transfer count register_1 (DMATCR_1)
DMA channel control register _1 (CHCR_1)
(3) Channel 2
•
•
•
•
DMA source address register_2 (SAR_2)
DMA destination address register_2 (DAR_2)
DMA transfer count register_2 (DMATCR_2)
DMA channel control register_2 (CHCR_2)
(4) Channel 3
•
•
•
•
DMA source address register_3 (SAR_3)
DMA destination address register_3 (DAR_3)
DMA transfer count register_3 (DMATCR_3)
DMA channel control register_3 (CHCR_3)
(5) Channel 4
•
•
•
•
DMA source address register_4 (SAR_4)
DMA destination address register_4 (DAR_4)
DMA transfer count register_4 (DMATCR_4)
DMA channel control register_4 (CHCR_4)
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Section 10
Direct Memory Access Controller (DMAC)
(6) Channel 5
•
•
•
•
DMA source address register_5 (SAR_5)
DMA destination address register_5 (DAR_5)
DMA transfer count register_5 (DMATCR_5)
DMA channel control register_5 (CHCR_5)
(7) Common
•
•
•
•
DMA operation register (DMAOR)
DMA extended resource selector 0 (DMARS0)
DMA extended resource selector 1 (DMARS1)
DMA extended resource selector 2 (DMARS2)
10.3.1
DMA Source Address Registers (SAR_0 to SAR_5)
SAR are 32-bit readable/writable registers that specify the source address of a DMA transfer.
During a DMA transfer, these registers indicate the next source address. When the data is
transferred from an external device with the DACK in single address mode, the SAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the source address
value. The initial value is undefined.
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Section 10
10.3.2
Direct Memory Access Controller (DMAC)
DMA Destination Address Registers (DAR_0 to DAR_5)
DAR are 32-bit readable/writable registers that specify the destination address of a DMA transfer.
During a DMA transfer, these registers indicate the next destination address. When the data is
transferred from an external device with the DACK in single address mode, the DAR is ignored.
To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary.
When transferring data in 16-byte units, a 16-byte boundary must be set for the destination address
value. The initial value is undefined.
10.3.3
DMA Transfer Count Registers (DMATCR_0 to DMATCR_5)
DMATCR are 32-bit readable/writable registers that specify the DMA transfer count. The number
of transfers is 1 when the setting is H'00000001, 16,777,215 when H'00FFFFFF is set, and
16,777,216 (the maximum) when H'00000000 is set. During a DMA transfer, these registers
indicate the remaining transfer count.
The upper eight bits of DMATCR are always read as 0, and the write value should always be 0. To
transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. The initial value is undefined.
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Section 10
10.3.4
Direct Memory Access Controller (DMAC)
DMA Channel Control Registers (CHCR_0 to CHCR_5)
CHCR are 32-bit readable/writable registers that control the DMA transfer mode.
Bit
Bit Name
Initial
Value
R/W
31 to 24

All 0
R
Descriptions
Reserved
These bits are always read as 0. The write value should
always be 0.
23
DO
0
R/W
DMA Overrun
Selects whether DREQ is detected by overrun 0 or by
overrun 1. This bit is valid only in CHCR_0 and
CHCR_1. This bit is always reserved and read as 0 in
CHCR_2 to CHCR_5. The write value should always be
0.
0: Detects DREQ by overrun 0
1: Detects DREQ by overrun 1
22
TL
0
R/W
Transfer End Level
Specifies whether the TEND signal output is high active
or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR2 to
CHCR_5. The write value should always be 0.
0: Low-active output of TEND
1: High-active output of TEND
21 to 18

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
17
AM
0
R/W
Acknowledge Mode
Selects whether DACK is output in data read cycle or in
data write cycle in dual address mode.
In single address mode, DACK is always output
regardless of the specification by this bit.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR_2 to
CHCR_5. The write value should always be 0.
0: DACK output in read cycle (dual address mode)
1: DACK output in write cycle (dual address mode)
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Section 10
Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
16
AL
0
R/W
Acknowledge Level
Specifies whether the DACK signal output is high active
or low active.
This bit is valid only in CHCR_0 and CHCR_1. This bit
is always reserved and read as 0 in CHCR_2 to
CHCR_5. The write value should always be 0.
0: Low-active output of DACK
1: High-active output of DACK
15
DM1
0
R/W
Destination Address Mode 1, 0
14
DM0
0
R/W
Specify whether the DMA destination address is
incremented, decremented, or left fixed. (In single
address mode, the DM1 and DM0 bits are ignored
when data is transferred to an external device with
DACK.)
00: Fixed destination address (setting prohibited in 16byte transfer)
01: Destination address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte transfer)
10: Destination address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longwordunit transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
13
SM1
0
R/W
Source Address Mode 1, 0
12
SM0
0
R/W
Specify whether the DMA source address is
incremented, decremented, or left fixed. (In single
address mode, SM1 and SM0 bits are ignored when
data is transferred from an external device with DACK.)
00: Fixed source address (setting prohibited in 16-byte
transfer)
01: Source address is incremented (+1 in byte-unit
transfer, +2 in word-unit transfer, +4 in longwordunit transfer, +16 in 16-byte transfer)
10: Source address is decremented (–1 in byte-unit
transfer, –2 in word-unit transfer, –4 in longwordunit transfer; setting prohibited in 16-byte transfer)
11: Setting prohibited
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Section 10
Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
11
RS3
0
R/W
Resource Select 3 to 0
10
RS2
0
R/W
9
RS1
0
R/W
8
RS0
0
R/W
Specify which transfer requests will be sent to the DMAC.
The changing of transfer request source should be done
in the state that the DMA enable bit (DE) is set to 0.
0
0
0
0
External request, dual address mode
0
0
0
1
Setting prohibited
0
0
1
0
External request, single address mode
External address space → External device with
DACK
0
0
1
1
External request, single address mode
External device with DACK → External address
space
0
1
0
0
Auto request
0
1
0
1
Setting prohibited
0
1
1
0
Setting prohibited
0
1
1
1
Setting prohibited
1
0
0
0
Selected by DMA extended resource selector
1
0
0
1
Setting prohibited
1
0
1
0
Setting prohibited
1
0
1
1
Setting prohibited
1
1
0
0
Setting prohibited
1
1
0
1
Setting prohibited
1
1
1
0
ADC
1
1
1
1
Setting prohibited
Note: External request specification is valid only in
CHCR_0 and CHCR_1. None of the external
request can be selected in CHCR_2 to CHCR_5.
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Section 10
Direct Memory Access Controller (DMAC)
Bit
Bit Name
Initial
Value
R/W
Descriptions
7
DL
0
R/W
DREQ Level and DREQ Edge Select
6
DS
0
R/W
Specify the detecting method of the DREQ pin input and
the detecting level.
These bits are valid only in CHCR_0 and CHCR_1.
These bits are always reserved and read as 0 in CHCR_2
to CHCR_5. The write value should always be 0.
In channels 0 and 1, also, if the transfer request source is
specified as an on-chip peripheral module or if an autorequest is specified, these bits are invalid.
00: DREQ detected in low level
01: DREQ detected at falling edge
10: DREQ detected in high level
11: DREQ detected at rising edge
5
TB
0
R/W
Transfer Bus Mode
Specifies the bus mode when DMA transfers data.
0: Cycle steal mode
1: Burst mode
4
TS1
0
R/W
Transfer Size 1, 0
3
TS0
0
R/W
Specify the size of data to be transferred.
Select the size of data to be transferred when the source
or destination is an on-chip peripheral module register of
which transfer size is specified.
00: Byte size
01: Word size (2 bytes)
10: Longword size (4 bytes)
11: 16-byte unit (four longword transfers)
2
IE
0
R/W
Interrupt Enable
Specifies whether or not an interrupt request is generated
to the CPU at the end of the DMA transfer. Setting this bit
to 1 generates an interrupt request (DEI) to the CPU
when the TE bit is set to 1.
0: Interrupt request is disabled.
1: Interrupt request is enabled.
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Section 10
Bit
Bit Name
Initial
Value
R/W
1
TE
0
R/(W)* Transfer End Flag
Direct Memory Access Controller (DMAC)
Descriptions
Shows that DMA transfer ends. The TE bit is set to 1
when data transfer ends when DMATCR becomes to 0.
The TE bit is not set to 1 in the following cases.
•
DMA transfer ends due to an NMI interrupt or DMA
address error before DMATCR is cleared to 0.
•
DMA transfer is ended by clearing the DE bit and
DME bit in the DMA operation register (DMAOR).
To clear the TE bit, the TE bit should be written to 0 after
reading 1.
Even if the DE bit is set to 1 while this bit is set to 1,
transfer is not enabled.
0: During the DMA transfer or DMA transfer has been
interrupted
[Clearing condition]
Writing 0 after TE = 1 read
1: DMA transfer ends by the specified count (DMATCR =
0)
0
DE
0
R/W
DMA Enable
Enables or disables the DMA transfer. In auto request
mode, DMA transfer starts by setting the DE bit and DME
bit in DMAOR to 1. In this time, all of the bits TE, NMIF,
and AE in DMAOR must be 0. In an external request or
peripheral module request, DMA transfer starts if DMA
transfer request is generated by the devices or peripheral
modules after setting the bits DE and DME to 1. In this
case, however, all of the bits TE, NMIF, and AE must be
0, which is the same as in the case of auto request
mode. Clearing the DE bit to 0 can terminate the DMA
transfer.
0: DMA transfer disabled
1: DMA transfer enabled
Note:
*
Writing 0 is possible to clear the flag.
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Section 10
10.3.5
Direct Memory Access Controller (DMAC)
DMA Operation Register (DMAOR)
DMAOR is a 16-bit readable/writable register that specifies the priority level of channels at the
DMA transfer. This register shows the DMA transfer status.
Bit
Bit Name
Initial
Value
R/W
Description
15, 14

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
13
CMS1
0
R/W
Cycle Steal Mode Select 1, 0
12
CMS0
0
R/W
Select either normal mode or intermittent mode in cycle
steal mode.
It is necessary that all channel's bus modes are set to
cycle steal mode to make valid intermittent mode.
00: Normal mode
01: Setting prohibited
10: Intermittent mode 16
Executes one DMA transfer in each of 16 clocks of an
external bus clock.
11: Intermittent mode 64
Executes one DMA transfer in each of 64 clocks of an
external bus clock.
11, 10

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
PR1
0
R/W
Priority Mode 1, 0
8
PR0
0
R/W
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3 > CH4 > CH5
01: CH0 > CH2 > CH3 > CH1 > CH4 > CH5
10: Setting prohibited
11: Round-robin mode
7 to 3

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
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Section 10
Bit
Bit Name
Initial
Value
R/W
2
AE
0
R/(W)* Address Error Flag
Direct Memory Access Controller (DMAC)
Description
Indicates that an address error occurred during DMA
transfer. If this bit is set, DMA transfer is disabled even if
the DE bit in CHCR and the DME bit in DMAOR are set to
1. This bit can only be cleared by writing 0 after reading
1.
0: No DMAC address error
[Clearing condition]
Writing AE = 0 after AE = 1 read
1: DMAC address error occurs
1
NMIF
0
R/(W)* NMI Flag
Indicates that an NMI interrupt occurred. If this bit is set,
DMA transfer is disabled even if the DE bit in CHCR and
the DME bit in DMAOR are set to 1. This bit can only be
cleared by writing 0 after reading 1.
When the NMI is input, the DMA transfer in progress can
be done in one transfer unit. When the DMAC is not in
operational, the NMIF bit is set to 1 even if the NMI
interrupt was input.
0: No NMI interrupt
[Clearing condition]
Writing NMIF = 0 after NMIF = 1 read
1: NMI interrupt occurs
0
DME
0
R/W
DMA Master Enable
Enables or disables DMA transfers on all channels. If the
DME bit and the DE bit in CHCR are set to 1, transfer is
enabled. In this time, all of the bits TE in CHCR, NMIF,
and AE in DMAOR must be 0. If this bit is cleared during
transfer, transfers in all channels are terminated.
0: Disables DMA transfers on all channels
1: Enables DMA transfers on all channels
Note:
*
Writing 0 is possible to clear the flag.
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Section 10
10.3.6
Direct Memory Access Controller (DMAC)
DMA Extended Resource Selectors 0 to 2 (DMARS0 to DMARS2)
DMARS are 16-bit readable/writable registers that specify the DMA transfer sources from
peripheral modules in each channel. DMARS0 specifies for channels 0 and 1, DMARS1 specifies
for channels 2 and 3, and DMARS2 specifies for channels 4 and 5. This register can set the
transfer request of SCIF0, SIOF1, MMC, CMT (channels 0 to 4), SIM, USBF, SIOF0, SIOF1, and
SDHI.
When MID/RID other than the values listed in table 10.2 is set, the operation of this LSI is not
guaranteed. The transfer request from DMARS is valid only when the resource select bits (RS3 to
RS0) have been set to B'1000 for CHCR_0 to CHCR_5 registers. Otherwise, even if DMARS has
been set, transfer request source is not accepted.
• DMARS0
Bit
Bit Name
Initial
Value
R/W
Description
15
C1MID5
0
R/W
14
C1MID4
0
R/W
Transfer request module ID5 to ID0 for DMA channel 1
(MID)
13
C1MID3
0
R/W
See table 10.2.
12
C1MID2
0
R/W
11
C1MID1
0
R/W
10
C1MID0
0
R/W
9
C1RID1
0
R/W
8
C1RID0
0
R/W
Transfer request register ID1 and ID0 for DMA channel 1
(RID)
See table 10.2.
7
C0MID5
0
R/W
6
C0MID4
0
R/W
Transfer request module ID5 to ID0 for DMA channel 0
(MID)
5
C0MID3
0
R/W
See table 10.2.
4
C0MID2
0
R/W
3
C0MID1
0
R/W
2
C0MID0
0
R/W
1
C0RID1
0
R/W
0
C0RID0
0
R/W
Transfer request register ID1 and ID0 for DMA channel 0
(RID)
See table 10.2.
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Section 10
Direct Memory Access Controller (DMAC)
• DMARS1
Bit
Bit Name
Initial
Value
R/W
Description
15
C3MID5
0
R/W
14
C3MID4
0
R/W
Transfer request module ID5 to ID0 for DMA channel 3
(MID)
13
C3MID3
0
R/W
See table 10.2.
12
C3MID2
0
R/W
11
C3MID1
0
R/W
10
C3MID0
0
R/W
9
C3RID1
0
R/W
8
C3RID0
0
R/W
Transfer request register ID1 and ID0 for DMA channel 3
(RID)
See table 10.2.
7
C2MID5
0
R/W
6
C2MID4
0
R/W
Transfer request module ID5 to ID0 for DMA channel 2
(MID)
5
C2MID3
0
R/W
See table 10.2.
4
C2MID2
0
R/W
3
C2MID1
0
R/W
2
C2MID0
0
R/W
1
C2RID1
0
R/W
0
C2RID0
0
R/W
Transfer request register ID1 and ID0 for DMA channel 2
(RID)
See table 10.2.
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Section 10
Direct Memory Access Controller (DMAC)
• DMARS2
Bit
Bit Name
Initial
Value
R/W
Description
15
C5MID5
0
R/W
14
C5MID4
0
R/W
Transfer request module ID5 to ID0 for DMA channel 5
(MID)
13
C5MID3
0
R/W
See table 10.2.
12
C5MID2
0
R/W
11
C5MID1
0
R/W
10
C5MID0
0
R/W
9
C5RID1
0
R/W
8
C5RID0
0
R/W
Transfer request register ID1 and ID0 for DMA channel 5
(RID)
See table 10.2.
7
C4MID5
0
R/W
6
C4MID4
0
R/W
Transfer request module ID5 to ID0 for DMA channel 4
(MID)
5
C4MID3
0
R/W
See table 10.2.
4
C4MID2
0
R/W
3
C4MID1
0
R/W
2
C4MID0
0
R/W
1
C4RID1
0
R/W
0
C4RID0
0
R/W
Transfer request register ID1 and ID0 for DMA channel 4
(RID)
See table 10.2.
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Section 10
Direct Memory Access Controller (DMAC)
Table 10.2 Transfer Request Sources
Peripheral
Module
Setting Value for One
Channel (MID + RID)
MID
RID
Function
SCIF0
H'21
B'001000
B'01
Transmit
B'10
Receive
B'01
Transmit
B'10
Receive
H'22
SCIF1
H'29
B'001010
H'2A
CMT
(channel 0)
H'03
B'000000
B'11

CMT
(channel 1)
H'07
B'000001
B'11

CMT
(channel 2)
H'0B
B'000010
B'11

CMT
(channel 3)
H'0F
B'000011
B'11

CMT
(channel 4)
H'13
B'000100
B'11

USBF
H'83
B'100000
B'11
Transmit
B'00
Receive
B'01
Transmit
H'80
SIM
H'A1
B'101000
B'10
Receive
MMC
H'A8
B'101010
B'00
Transmit/receive
SIOF0
H'B1
B'101100
B'01
Transmit
B'10
Receive
B'01
Transmit
B'10
Receive
B'01
Transmit
B'10
Receive
H'A2
H'B2
SIOF1
H'B5
B'101101
H'B6
SDHI
H'C1
H'C2
B'110000
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Section 10
10.4
Direct Memory Access Controller (DMAC)
Operation
When there is a DMA transfer request, the DMAC starts the transfer according to the
predetermined channel priority; when the transfer end conditions are satisfied, it ends the transfer.
Transfers can be requested in three modes: auto request, external request, and on-chip peripheral
module request. In bus mode, burst mode or cycle steal mode can be selected.
10.4.1
DMA Transfer Flow
After the DMA source address registers (SAR), DMA destination address registers (DAR), DMA
transfer count registers (DMATCR), DMA channel control registers (CHCR), DMA operation
register (DMAOR), and DMA extended resource selectors (DMARS) are set, the DMAC transfers
data according to the following procedure:
1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0)
2. When a transfer request occurs while transfer is enabled, the DMAC transfers one transfer unit
of data (depending on the TS0 and TS1 settings). In auto request mode, the transfer begins
automatically when the DE bit and DME bit are set to 1. The DMATCR value will be
decremented for each transfer. The actual transfer flows vary by address mode and bus mode.
3. When the specified number of transfer have been completed (when DMATCR reaches 0), the
transfer ends normally. If the IE bit in CHCR is set to 1 at this time, a DEI interrupt is sent to
the CPU.
4. When an address error or an NMI interrupt is generated, the transfer is aborted. Transfers are
also aborted when the DE bit in CHCR or the DME bit in DMAOR is changed to 0.
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Section 10
Direct Memory Access Controller (DMAC)
Figure 10.2 shows a flowchart of this procedure.
Start
Initial settings
(SAR, DAR, DMATCR, CHCR, DMAOR, DMARS)
DE, DME = 1 and
NMIF, AE, TE = 0?
No
Yes
Transfer request
occurs?*1
No
*2
*3
Yes
Transfer (1 transfer unit);
DMATCR – 1 → DMATCR, SAR and DAR
updated
DMATCR = 0?
No
Yes
Bus mode,
transfer request mode,
DREQ detection selection
system
NMIF = 1
or AE = 1 or DE = 0
or DME = 0?
No
Yes
Transfer aborted
TE = 1
DEI interrupt request (when IE = 1)
NMIF = 1
or AE = 1 or DE = 0
or DME = 0?
No
Yes
Transfer end
Normal end
Notes: 1. In auto-request mode, transfer begins when the NMIF, AE, and TE bits are all 0 and the DE and
DME bits are set to 1.
2. DREQ = level detection in burst mode (external request) or cycle-steal mode.
3. DREQ = edge detection in burst mode (external request), or auto-request mode in burst mode.
Figure 10.2
DMA Transfer Flowchart
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Section 10
10.4.2
Direct Memory Access Controller (DMAC)
DMA Transfer Requests
DMA transfer requests are basically generated in either the data transfer source or destination, but
they can also be generated by external devices or on-chip peripheral modules that are neither the
source nor the destination. Transfers can be requested in three modes: auto request, external
request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0
bits in CHCR0 to CHCR3, and DMARS0 to DMARS2.
(1)
Auto-Request Mode
When there is no transfer request signal from an external source, as in a memory-to-memory
transfer or a transfer between memory and an on-chip peripheral module unable to request a
transfer, auto-request mode allows the DMAC to automatically generate a transfer request signal
internally. When the DE bits in CHCR and the DME bit in DMAOR are set to 1, the transfer
begins so long as the AE and NMIF bits in DMAOR are all 0.
(2)
External Request Mode
In this mode, a transfer is performed at the request signals (DREQ0 and DREQ1) of an external
device. This mode is valid only in channel 0 and channel 1. Choose one of the modes shown in
table 10.3 according to the application system. When this mode is selected, if the DMA transfer is
enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at
the DREQ input.
Table 10.3 Selecting External Request Modes with RS Bits
RS3
RS2
RS1
RS0
Address Mode
Source
Destination
0
0
0
0
Dual address
mode
Any
Any
1
0
Single address
mode
External memory,
memory-mapped
external device
External device with
DACK
External device with
DACK
External memory,
memory-mapped
external device
1
Rev. 3.00 Jan. 18, 2008 Page 426 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
Choose to detect DREQ by either the edge or level of the signal input with the DL bit and DS bit
in CHCR_0 and CHCR_1 as shown in table 10.4. The source of the transfer request does not have
to be the data transfer source or destination.
Table 10.4 Selecting External Request Detection with DL, DS Bits
CHCR_0 or CHCR_1
DL
DS
Detection of External Request
0
0
Low level detection
1
Falling edge detection
0
High level detection
1
Rising edge detection
1
When DREQ is accepted, the DREQ pin becomes request accept disabled state. After issuing
acknowledge signal DACK for the accepted DREQ, the DREQ pin again becomes request accept
enabled state.
When DREQ is used by level detection, there are following two cases by the timing to detect the
next DREQ after outputting DACK.
• Overrun 0: Transfer is aborted after the same number of transfer has been performed as
requests.
• Overrun 1: Transfer is aborted after transfers have been performed for (the number of requests
plus 1) times.
The DO bit in CHCR selects this overrun 0 or overrun 1.
Table 10.5 Selecting External Request Detection with DO Bit
CHCR_0 or CHCR_1
DO
External Request
0
Overrun 0
1
Overrun 1
Rev. 3.00 Jan. 18, 2008 Page 427 of 1458
REJ09B0033-0300
Section 10
(3)
Direct Memory Access Controller (DMAC)
On-Chip Peripheral Module Request Mode
In this mode, a transfer is performed at the transfer request signal of an on-chip peripheral module.
Transfer request signals comprise the transmit data empty transfer request and receive data full
transfer request from the ADC set by CHCR0 to CHCR5 and the SCIF0, SCIF1, MMC, USBF,
SIM, SIOF0, SIOF1, and SDHI set by DMARS0/1/2, and the compare-match timer transfer
request from the CMT (channels 0 to 4).
When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0,
NMIF = 0), a transfer is performed upon the input of a transfer request signal.
When a transmit data empty transfer request of the SCIF0 is set as the transfer request, the transfer
destination must be the SCIF0's transmit data register. Likewise, when receive data full transfer
request of the SCIF0 is set as the transfer request, the transfer source must be the SCIF0's receive
data register. These conditions also apply to the SIOF1, MMC, USBF, SIM, SIOF0, SIOF1, and
SDHI. When the ADC is set as the transfer request, the transfer source must be the A/D data
register. Any address can be specified for data source and destination, when transfer request is
generated by the CMT (channels 0 to 4).
The number of the receive FIFO triggers can be set as a transfer request depending on an on-chip
peripheral module. Data needs to be read after the DMA transfer is ended, because data may be
remained in the receive FIFO when the receive FIFO trigger condition is not satisfied.
Rev. 3.00 Jan. 18, 2008 Page 428 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
Table 10.6 Selecting On-Chip Peripheral Module Request Modes with RS3 to RS0 Bits
CHCR
DMARS
DMA Transfer
DMA Transfer
Request
Source
Request Signal
Bus
Mode
Source
Destination
TXI0 (transmit FIFO data
empty interrupt)
Any
SCFTDR0
Cycle
steal
RXI0 (receive FIFO data
full interrupt)
SCFRDR0
Any
Cycle
steal
SCIF1transmitt TXI1 (transmit FIFO data
er
empty interrupt)
Any
SITDR
Cycle
steal
10
SCIF1
receiver
RXI1 (receive FIFO data
full interrupt)
SCFRDR1
Any
Cycle
steal
000000
11
CMT
(channel 0)
Compare-match transfer
request
Any
Any
Cycle
steal/
burst
000001
11
CMT
(channel 1)
Compare-match transfer
request
Any
Any
Cycle
steal/
burst
000010
11
CMT
(channel 2)
Compare-match transfer
request
Any
Any
Cycle
steal/
burst
000011
11
CMT
(channel 3)
Compare-match transfer
request
Any
Any
Cycle
steal/
burst
000100
11
CMT
(channel 4)
Compare-match transfer
request
Any
Any
Cycle
steal/
burst
RS[3:0]
MID
RID
1000
001000
01
SCIF0
transmitter
10
SCIF0
receiver
01
001010
Rev. 3.00 Jan. 18, 2008 Page 429 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
CHCR
DMARS
DMA Transfer
DMA Transfer
Request
Source
Request Signal
RS[3:0]
MID
RID
1000
100000
11
USBF
transmitter
00
USBF receiver Transmit data full request
01
SIM
transmitter
10
00
101000
101010
101100
101101
110000
1110

Destination
Bus
Mode
EPDR2
Cycle
steal
EPDR1
Any
Cycle
steal
TXI (transmit data empty)
Any
SCTDR
Cycle
steal
SIM receiver
RXI (receive data full)
SCRDR
Any
Cycle
steal
MMC
transmitter
Receive data empty request
Any
Data register Cycle
steal
MMC receiver Receive data full request
Data register
Any
Cycle
steal
01
SIOF0
transmitter
TXI0 (transmit FIFO data
empty)
Any
SITDR0
Cycle
steal
10
SIOF0
receiver
RXI0 (receive FIFO data full) SIRDR0
Any
Cycle
steal
01
SIOF1
transmitter
TXI1 (transmit FIFO data
empty)
SITDR1
Cycle
steal
10
SIOF1
receiver
RXI1 (receive FIFO data full) SIRDR0
Any
Cycle
steal
01
SD transmitter Transmit data empty request Any
Data register Cycle
steal
10
SD receiver
Receive data full request
Data register
Any
Cycle
steal

ADC
ADI (A/D conversion end)
ADDR
Any
Cycle
steal
Transmit data empty request Any
Rev. 3.00 Jan. 18, 2008 Page 430 of 1458
REJ09B0033-0300
Source
Any
Section 10
10.4.3
Direct Memory Access Controller (DMAC)
Channel Priority
When the DMAC receives simultaneous transfer requests on two or more channels, it transfers
data according to a predetermined priority. Two modes (fixed mode and round-robin mode) are
selected by the PR1 and PR0 bits in DMAOR.
(1)
Fixed Mode
In this mode, the priority levels among the channels remain fixed. There are two kinds of fixed
modes as follows:
• CH0 > CH1 > CH2 > CH3 > CH4 > CH5
• CH0 > CH2 > CH3 > CH1 > CH4 > CH5
These are selected by the PR1 and the PR0 bits in DMAOR.
(2)
Round-Robin Mode
In round-robin mode each time data of one transfer unit (word, byte, longword, or 16-byte unit) is
transferred on one channel, the priority is rotated. The channel on which the transfer was just
finished rotates to the bottom of the priority. The round-robin mode operation is shown in figure
10.3. The priority of round-robin mode is CH0 > CH1 > CH2 > CH3 > CH4 > CH5 immediately
after a reset. When round-robin mode is specified, the same bus mode, either cycle steal mode or
burst mode, must be specified for all of the channels.
Rev. 3.00 Jan. 18, 2008 Page 431 of 1458
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Section 10
Direct Memory Access Controller (DMAC)
(1) When channel 0 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Priority order
after transfer
Channel 0 becomes bottom
priority
CH1 > CH2 > CH3 > CH4 > CH5 > CH0
(2) When channel 1 transfers
Initial priority order
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Channel 1 becomes bottom
priority.
The priority of channel 0, which
was higher than channel 1, is also
shifted.
CH2 > CH3 > CH4 > CH5 > CH0 > CH1
(3) When channel 2 transfers
Initial priority order
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
CH3 > CH4 > CH5 > CH0 > CH1 > CH2
Post-transfer priority order
when there is an
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
immediate transfer
request to channel 5 only
Channel 2 becomes bottom
priority.
The priority of channels 0 and 1,
which were higher than channel 2,
are also shifted. If immediately
after there is a request to transfer
channel 5 only, channel 5 becomes
bottom priority and the priority of
channels 3 and 4, which were
higher than channel 5, are also
shifted.
(4) When channel 5 transfers
Initial priority order
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Priority order
after transfer
CH0 > CH1 > CH2 > CH3 > CH4 > CH5
Figure 10.3
Rev. 3.00 Jan. 18, 2008 Page 432 of 1458
REJ09B0033-0300
Priority order does not change.
Round-Robin Mode
Section 10
Direct Memory Access Controller (DMAC)
Figure 10.4 shows how the priority changes when channel 0 and channel 3 transfers are requested
simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC
operates as follows:
1. Transfer requests are generated simultaneously to channels 0 and 3.
2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for
transfer).
3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both
waiting)
4. When the channel 0 transfer ends, channel 0 becomes lowest priority.
5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins
(channel 3 waits for transfer).
6. When the channel 1 transfer ends, channel 1 becomes lowest priority.
7. The channel 3 transfer begins.
8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel
3 becomes the lowest priority.
Transfer request
Waiting channel(s) DMAC operation
Channel priority
(1) Channels 0 and 3
(3) Channel 1
3
(2) Channel 0 transfer
starts
1,3
(4) Channel 0 transfer
ends
0>1>2>3>4>5
Priority order
changes
1>2>3>4>5>0
(5) Channel 1 transfer
starts
3
(6) Channel 1 transfer
ends
(7) Channel 3 transfer
starts
None
(8) Channel 3 transfer
ends
Figure 10.4
Priority order
changes
Priority order
changes
2>3>4>5>0>1
4>5>0>1>2>3
Changes in Channel Priority in Round-Robin Mode
Rev. 3.00 Jan. 18, 2008 Page 433 of 1458
REJ09B0033-0300
Section 10
10.4.4
Direct Memory Access Controller (DMAC)
DMA Transfer Types
DMA transfer has two types; single address mode transfer and dual address mode transfer. They
depend on the number of bus cycles of access to source and destination. A data transfer timing
depends on the bus mode, which has cycle steal mode and burst mode. The DMAC supports the
transfers shown in table 10.7.
Table 10.7 Supported DMA Transfers
Destination
External
Device with External
DACK
Memory
MemoryMapped
External
Device
On-Chip
Peripheral
Module
X/Y Memory
U Memory
External device with DACK
Not
available
Dual,
single
Not
available
Not
available
External memory
Dual, single Dual
Dual
Dual
Dual
Memory-mapped external
device
Dual, single Dual
Dual
Dual
Dual
On-chip peripheral module
Not
available
Dual
Dual
Dual
Dual
X/Y memory
Not
available
Dual
Dual
Dual
Dual
Source
Dual,
single
Notes: 1. Dual: Dual address mode
2. Single: Single address mode
3. For on-chip peripheral modules, 16-byte transfer is available only by registers which
can be accessed in longword units.
Rev. 3.00 Jan. 18, 2008 Page 434 of 1458
REJ09B0033-0300
Section 10
(1)
Address Modes
(a)
Dual Address Mode
Direct Memory Access Controller (DMAC)
In dual address mode, both the transfer source and destination are accessed by an address. The
source and destination can be located externally or internally.
DMA transfer requires two bus cycles because data is read from the transfer source in a data read
cycle and written to the transfer destination in a data write cycle. At this time, transfer data is
temporarily stored in the DMAC. In the transfer between external memories as shown in figure
10.5, data is read to the DMAC from one external memory in a data read cycle, and then that data
is written to the other external memory in a write cycle.
DMAC
SAR
Data bus
Address bus
DAR
Memory
Data buffer
Transfer source
module
Transfer destination
module
The SAR value is an address, data is read from the transfer source module,
and the data is temporarily stored in the DMAC.
First bus cycle
DMAC
SAR
Data bus
Address bus
DAR
Memory
Transfer source
module
Transfer destination
module
Data buffer
The DAR value is an address and the value stored in the data buffer in the
DMAC is written to the transfer destination module.
Second bus cycle
Figure 10.5
Data Flow of Dual Address Mode
Auto request, external request, and on-chip peripheral module request are available for the transfer
request. DACK can be output in read cycle or write cycle in dual address mode. The channel
control register (CHCR) can specify whether the DACK is output in read cycle or write cycle.
Rev. 3.00 Jan. 18, 2008 Page 435 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
Figure 10.6 shows an example of DMA transfer timing in dual address mode.
CKIO
A25 to A0
Transfer source
address
Transfer destination
address
Data read cycle
Data write cycle
(1st cycle)
(2nd cycle)
CSn
D31 to D0
RD
WEn
DACKn
(Active-low)
Note: In transfer between external memories, with DACK output in the read cycle,
DACK output timing is the same as that of CSn.
Figure 10.6 Example of DMA Transfer Timing in Dual Mode
(Source: Ordinary Memory, Destination: Ordinary Memory)
Rev. 3.00 Jan. 18, 2008 Page 436 of 1458
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Section 10
(b)
Direct Memory Access Controller (DMAC)
Single Address Mode
In single address mode, either the transfer source or transfer destination peripheral device is
accessed (selected) by means of the DACK signal, and the other device is accessed by an address.
In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the
external devices by outputting the DACK transfer request acknowledge signal to it, and at the
same time outputting an address to the other device involved in the transfer. For example, in the
case of transfer between external memory and an external device with DACK shown in figure
10.7, when the external device outputs data to the data bus, that data is written to the external
memory in the same bus cycle.
External address bus
External data bus
This LSI
External
memory
DMAC
External device
with DACK
DACK
DREQ
Data flow
Figure 10.7
Data Flow in Single Address Mode
Two kinds of transfer are possible in single address mode: (1) transfer between an external device
with DACK and a memory-mapped external device, and (2) transfer between an external device
with DACK and external memory. In both cases, only the external request signal (DREQ) is used
for transfer requests.
Rev. 3.00 Jan. 18, 2008 Page 437 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
Figure 10.8 shows an example of DMA transfer timing in single address mode.
CKIO
A25 to A0
Address output to external memory space
CSn
Select signal to external memory space
WE
Write strobe signal to external memory space
Data output from external device with DACK
D31 to D0
DACKn
DACK signal (active-low) to external device with DACK
(a) External device with DACK → external memory space (ordinary memory)
CKIO
A25 to A0
Address output to external memory space
CSn
Select signal to external memory space
RD
Read strobe signal to external memory space
Data output from external memory space
D31 to D0
DACKn
DACK signal (active-low) to external device with DACK
(b) External memory space (ordinary memory) → external device with DACK
Figure 10.8
Example of DMA Transfer Timing in Single Address Mode
Rev. 3.00 Jan. 18, 2008 Page 438 of 1458
REJ09B0033-0300
Section 10
(2)
Direct Memory Access Controller (DMAC)
Bus Modes
There are two bus modes: cycle steal mode and burst mode. Select the mode in the TB bits in the
channel control register (CHCR).
(a)
Cycle-Steal Mode
• Normal mode
In cycle-steal normal mode, the bus mastership is given to another bus master after a onetransfer-unit (byte, word, longword, or 16-byte unit) DMA transfer. When another transfer
request occurs, the bus mastership is obtained from the other bus master and a transfer is
performed for one transfer unit. When that transfer ends, the bus mastership is passed to the
other bus master. This is repeated until the transfer end conditions are satisfied.
In cycle-steal normal mode, transfer areas are not affected regardless of settings of the transfer
request source, transfer source, and transfer destination.
Figure 10.9 shows an example of DMA transfer timing in cycle-steal normal mode. Transfer
conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
DREQ
Bus mastership returned to CPU once
Bus cycle
CPU
CPU
CPU
DMAC DMAC
Read/Write
Figure 10.9
CPU
DMAC
DMAC
CPU
Read/Write
DMA Transfer Example in Cycle-Steal Normal Mode
(Dual Address, DREQ Low Level Detection)
• Intermittent mode 16 and intermittent mode 64
In intermittent mode of cycle steal, the DMAC returns the bus mastership to other bus master
whenever a unit of transfer (byte, word, longword, or 16-byte unit) is complete. If the next
transfer request occurs after that, the DMAC gets the bus mastership from other bus master
after waiting for 16 or 64 clocks in Bφ count. The DMAC then transfers data of one unit and
returns the bus mastership to other bus master. These operations are repeated until the transfer
end condition is satisfied. It is thus possible to make lower the ratio of bus occupation by DMA
transfer than cycle-steal normal mode.
When the DMAC gets again the bus mastership, DMA transfer can be postponed in case of
entry updating due to cache miss.
Rev. 3.00 Jan. 18, 2008 Page 439 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
This intermittent mode can be used for all transfer section; transfer request source, transfer
source, and transfer destination. The bus modes, however, must be cycle steal mode in all
channels.
Figure 10.10 shows an example of DMA transfer timing in cycle steal intermittent mode.
Transfer conditions shown in the figure are:
 Dual address mode
 DREQ low level detection
DREQ
More than 16 or 64 Bφ
(change by the CPU, LCDC, and USBH states of using bus)
Bus cycle
CPU
CPU
CPU DMAC DMAC
CPU
CPU
DMAC DMAC
Read/Write
Figure 10.10
(b)
CPU
Read/Write
Example of DMA Transfer in Cycle Steal Intermittent Mode
(Dual Address, DREQ Low Level Detection)
Burst Mode
In burst mode, once the DMAC obtains the bus mastership, the transfer is performed continuously
without releasing the bus mastership until the transfer end condition is satisfied. In external
request mode with level detection of the DREQ pin, however, when the DREQ pin is not active,
the bus mastership passes to the other bus master after the DMAC transfer request that has already
been accepted ends, even if the transfer end conditions have not been satisfied.
Burst mode cannot be used for other than CMT (channels 0 to 4) when the on-chip peripheral
module is the transfer request source.
Figure 10.11 shows DMA transfer timing in burst mode.
DREQ
Bus cycle
CPU
CPU
CPU
DMAC DMAC DMAC DMAC DMAC DMAC
Read
Write
Read
Write
Read
Write
Figure 10.11 DMA Transfer Example in Burst Mode
(Dual Address, DREQ Low Level Detection)
Rev. 3.00 Jan. 18, 2008 Page 440 of 1458
REJ09B0033-0300
CPU
Section 10
(3)
Direct Memory Access Controller (DMAC)
Relationship between Request Modes and Bus Modes by DMA Transfer Category
Table 10.8 shows the relationship between request modes and bus modes by DMA transfer
category.
Table 10.8 Relationship between Request Modes and Bus Modes by DMA Transfer
Category
Address
Mode
Transfer Category
Request Bus
Mode
Mode
Transfer
Size (Bits)
Usable
Channels
Dual
External
B/C
8/16/32/128
0,1
External device with DACK and memory- External
mapped external device
B/C
8/16/32/128
0, 1
1
B/C
8/16/32/128
0 to 5*
External memory and memory-mapped
external device
1
All*
B/C
8/16/32/128
0 to 5*5
Memory-mapped external device and
memory-mapped external device
All*1
B/C
8/16/32/128
0 to 5*5
External memory and on-chip peripheral
module
All*2
B/C*3
8/16/32/128*4 0 to 5*5
Memory-mapped external device and
on-chip peripheral module
All*2
B/C*3
8/16/32/128*4 0 to 5*5
On-chip peripheral module and on-chip
peripheral module
All*2
B/C*3
8/16/32/128*4 0 to 5*5
X/Y memory and X/Y memory
All*1
B/C
8/16/32/128
0 to 5*5
X/Y memory and memory-mapped
external device
All*1
B/C
8/16/32/128
0 to 5*5
X/Y memory and on-chip peripheral
module
All*2
B/C*3
8/16/32/128*4 0 to 5*5
X/Y memory and external memory
All*1
B/C
8/16/32/128
0 to 5*5
External device with DACK and external
memory
External
B/C
8/16/32
0, 1
External device with DACK and memory- External
mapped external device
B/C
8/16/32
0, 1
External device with DACK and external
memory
External memory and external memory
Single
All*
5
B: Burst mode, C: Cycle steal mode
Rev. 3.00 Jan. 18, 2008 Page 441 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
Notes: 1. External requests, auto requests, and on-chip peripheral module requests are all
available. In the case of on-chip peripheral module requests, however, the CMT
(channels 0 to 4) are only available.
2. External requests, auto requests, and on-chip peripheral module requests are all
available. However, with the exception of the CMT (channels 0 to 4) as the transfer
request source, the request source register must be designated as the transfer source
or the transfer destination.
3. Only cycle steal except for the CMT (channels 0 to 4) as the transfer request source.
4. Access size permitted for the on-chip peripheral module register functioning as the
transfer source or transfer destination.
5. If the transfer request is an external request, channels 0 and 1 are only available.
Rev. 3.00 Jan. 18, 2008 Page 442 of 1458
REJ09B0033-0300
Section 10
(4)
Direct Memory Access Controller (DMAC)
Bus Mode and Channel Priority
When the priority is set in fixed mode (CH0 > CH1), even though channel 1 is transferring in burst
mode, if there is a transfer request to channel 0 which has a higher priority, the transfer of channel
0 will begin immediately.
At this time, if channel 0 is also operating in burst mode, the channel 1 transfer will continue when
the channel 0 transfer with a higher priority has completely finished.
If channel 0 is operating in cycle steal mode, immediately after channel 0 with a higher priority
completes the transfer of one transfer unit, the channel 1 transfer will begin again without
releasing the bus mastership. Transfer will then switch between the two in the order of channel 0,
channel 1, channel 0, and channel 1. For the bus state, the CPU cycle after cycle steal mode
transfer finishes is replaced with a burst mode transfer cycle (hereafter referred to as burst mode
high-priority execution).
This example is illustrated in figure 10.12. If there are channels with conflicting burst transfers,
transfer for the channel with the highest priority is performed first.
In DMA transfer for more than one channel, the DMAC does not give the bus mastership to the
bus master until all conflicting burst transfers have finished.
CPU
CPU
DMA
CH1
DMA
CH1
DMAC CH1
Burst mode
DMA
CH0
DMA
CH1
DMA
CH0
CH0
CH1
CH0
DMAC CH0 and CH1
Cycle-steal mode
DMA
CH1
DMA
CH1
DMAC CH1
Burst mode
CPU
CPU
Priority: CH0 > CH1
CH0: Cycle-steal mode
CH1: Burst mode
Figure 10.12
Bus State when Multiple Channels are Operating
In round-robin mode, the priority changes according to the specifications shown in figure 10.3.
Note that a channel operating in cycle steal mode cannot be handled together with a channel
operating in burst mode.
Rev. 3.00 Jan. 18, 2008 Page 443 of 1458
REJ09B0033-0300
Section 10
10.4.5
(1)
Direct Memory Access Controller (DMAC)
Number of Bus Cycle States and DREQ Pin Sampling Timing
Number of Bus Cycle States
When the DMAC is the bus master, the number of bus cycle states is controlled by the bus state
controller (BSC) in the same way as when the CPU is the bus master. For details, see section 9,
Bus State Controller (BSC).
(2)
DREQ Pin Sampling Timing
Figures 10.13, 10.14, 10.15, and 10.16 show the sample timing of the DREQ input in each bus
mode, respectively.
CKIO
Bus cycle
DREQ
(Rising edge)
CPU
CPU
1st acceptance
Non-sensitive period
DACK
(High-active)
Figure 10.13
Acceptance started
Example of DREQ Input Detection in Cycle Steal Mode Edge Detection
Rev. 3.00 Jan. 18, 2008 Page 444 of 1458
REJ09B0033-0300
CPU
DMAC
2nd acceptance
Section 10
Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
CPU
1st acceptance
CPU
DMAC
CPU
2nd acceptance
Non-sensitive period
DACK
(High-active)
Acceptance started
CKIO
Bus cycle
DREQ
(Overrun 1,
high-level)
CPU
1st acceptance
CPU
Non-sensitive period
DACKn
(High-active)
Figure 10.14
DMAC
CPU
2nd acceptance
Non-sensitive period
Acceptance started
Example of DREQ Input Detection in Cycle Steal Mode Level Detection
CKIO
Bus cycle
DREQ
(Rising edge)
CPU
CPU
Burst acceptance
DMAC
DMAC
Non-sensitive period
DACK
(High-active)
Figure 10.15
Example of DREQ Input Detection in Burst Mode Edge Detection
Rev. 3.00 Jan. 18, 2008 Page 445 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(Overrun 0,
high-level)
CPU
1st acceptance
CPU
DMAC
2nd acceptance
Non-sensitive period
DACK
(High-active)
Acceptance
started
CKIO
Bus cycle
DREQ
(Overrun 1,
high-level)
CPU
1st acceptance
CPU
DMAC
2nd acceptance
DMAC
3rd acceptance
Acceptance
started
Acceptance
started
Non-sensitive period
DACK
(High-active)
Figure 10.16
Example of DREQ Input Detection in Burst Mode Level Detection
CKIO
Last DMA transfer
Bus cycle
DMAC
CPU
DMAC
CPU
CPU
DREQ
DACK
TEND
Figure 10.17
Example of DMA Transfer End in Cycle Steal Mode Level Detection
Rev. 3.00 Jan. 18, 2008 Page 446 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
When an 8-bit or 16-bit external device is accessed in longword units, or when an 8-bit external
device is accessed in word units, the DACK output is divided because of the data alignment. This
example is illustrated in figure 10.18.
T1
T2
Taw
T1
T2
CKIO
Address
CSn
RD
Data
WEn
DACKn
(Active-low)
WAIT
Note: The DACK is asserted for the last transfer unit
of the DMA transfer. When the transfer unit is
divided into several bus cycles and the CSn is
negated between bus cycles, the DACK is also
divided.
Figure 10.18 Example of BSC Ordinary Memory Access
(No Wait, Idle Cycle 1, Longword Access to 16-Bit Device)
Rev. 3.00 Jan. 18, 2008 Page 447 of 1458
REJ09B0033-0300
Section 10
10.5
Direct Memory Access Controller (DMAC)
Usage Notes
Pay attentions to the following notes when the DMAC is used.
10.5.1
Notes on DACK Pin Output
When burst mode and cycle steal mode are simultaneously set in two or more channels, an
additional DACK may be asserted at the end of burst transfer. This phenomenon will occur when
all of the conditions described below are satisfied.
1. When the DMA transfer is simultaneously performed in two or more channels support both
burst mode and cycle steal mode
2. When the channel to be used in burst mode is set to dual address mode, and DACK is output in
data write cycle
3. When the DMAC cannot obtain the bus mastership consecutively even though a transfer
demand of cycle steal has been received after the completion of burst transfer
This phenomenon is avoided by taking either of three measures shown below.
• Measure 1
After confirming the completion of burst transfer (TE bit = 1), perform the DMA transfer of
other cycle steal mode
• Measure 2
The channel to be used in burst mode should not be set to output DACK in data write cycle
• Measure 3
When the DMA transfer is simultaneously performed in two or more channels, set all of the
channels to burst mode or cycle steal mode
10.5.2
(1)
Notes on the Cases When DACK is Divided
Overview
When DACK is divided for output while the DMAC is accessing an external device, sampling of
DREQ may be accepted once more during the access.
(2)
Conditions and Phenomena
Conditions: In the cases when DACK is divided for output during external access, specifically, the
following cases:
Rev. 3.00 Jan. 18, 2008 Page 448 of 1458
REJ09B0033-0300
Section 10
•
•
•
•
Direct Memory Access Controller (DMAC)
16-byte access
32-bit access in an 8-bit space
16-bit access in an 8-bit space
32-bit access in a 16-bit space,
Any one of the following inter-access idle cycle specifications has been made for that space:
• Idle between write cycles (IWW = 001 or more)
• Idle between read cycles in the same space (IWRRS = 001 or more)
• External wait masking (WM = 0)
Phenomena: For the access patterns above, the DREQ pin signal is detected with the timing shown
in figures 10.19 and 10.21. For other access patterns, DREQ is detected normally as shown in
figures 10.20 and 10.22.
(3)
How to Avoid the Problem
For the external accesses under the conditions of 2 above, the problems can be avoided in the
following way:
1. Detection of DREQ edges: During the bus cycle, input a DREQ edge (rising edge) only once at
most.
2. When overrun-0 in DREQ level detection is specified: During the bus cycle, negate the DREQ
input after detection of the first DACK output negation but before the second DACK output
negation takes place.
3. When overrun-1 in DREQ level detection is specified: During the bus cycle, negate the DREQ
input after detection of the first DACK output assertion but before the second DACK output
assertion takes place.
Rev. 3.00 Jan. 18, 2008 Page 449 of 1458
REJ09B0033-0300
Section 10
(4)
Direct Memory Access Controller (DMAC)
DREQ Pin Detection Timing Charts
CKIO
Bus cycle
CPU
First acceptance
DMAC write or read
Second acceptance
Third acceptance (possible)
DREQ
(rising edge)
Dead zone
Dead zone
Dead zone
DACK
(active-high)
Acceptance started
Acceptance started
Figure 10.19 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles and So
DREQ Sampling is Accepted One Extra Time)
CKIO
Bus cycle
CPU
First acceptance
DMAC write or read
Second acceptance
Third
acceptance
DREQ
(rising edge)
Dead zone
Dead zone
Dead zone
DACK
(active-high)
Acceptance
started
Acceptance
started
Figure 10.20 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles and So DREQ
Sampling is Accepted Normally)
Rev. 3.00 Jan. 18, 2008 Page 450 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(overrun 0,
high level)
DMAC write or read
CPU
First acceptance
Second
acceptance
Dead zone
Third acceptance (possible)
Dead zone
DACK
(active-high)
Acceptance started
CKIO
Bus cycle
DREQ
(overrun 1,
high level)
CPU
DMAC write or read
Second
First acceptance acceptance
Dead zone
Third acceptance (possible)
Dead zone
DACK
(active-high)
Acceptance
started
Figure 10.21 Timing of DREQ Input Detection by Level Detection in Cycle Stealing Mode
(DACK is Divided into Four due to Idle Cycle Insertion between Access Cycles and So
DREQ Sampling is Accepted One Extra Time)
Rev. 3.00 Jan. 18, 2008 Page 451 of 1458
REJ09B0033-0300
Section 10
Direct Memory Access Controller (DMAC)
CKIO
Bus cycle
DREQ
(overrun 0,
high level)
DMAC write or read
CPU
First acceptance
Second acceptance
Dead zone
Dead zone
Third acceptance
Dead zone
DACK
(high active)
Acceptance
started
Acceptance
started
CKIO
Bus cycle
DREQ
(overrun 1,
high level)
CPU
DMAC write or read
First acceptance Second acceptance
Dead zone
Third acceptance
Dead zone
Dead zone
DACK
(active-high)
Acceptance started
Acceptance started
Figure 10.22 Timing of DREQ Input Detection by Edge Detection in Cycle Stealing Mode
(DACK is Not Divided By Idle Cycle Insertion between Access Cycles and So DREQ
Sampling is Accepted Normally)
10.5.3
Other Notes
1. Before making a transition to standby mode, either wait until DMA transfer finishes or
suspend DMA transfer.
2. If an on-chip peripheral module whose clock supply is to be stopped by the module standby
function is performing DMA transfer, either wait until DMA transfer finishes or suspend DMA
transfer before making a transition to module standby mode.
3. Do not write to SAR, DAR, DMATCR, or DMARS during DMA transfer.
Concerning Above Notes 1 and 2:
DMA transfer end can be confirmed by checking whether the TE bit in CHCR is set to 1.
To suspend DMA transfer, clear the DE bit in CHCR to 0.
Rev. 3.00 Jan. 18, 2008 Page 452 of 1458
REJ09B0033-0300
Section 11
Section 11
Clock Pulse Generator (CPG)
Clock Pulse Generator (CPG)
This LSI has a clock pulse generator which generates an internal clock (Iφ), a peripheral clock
(Pφ), and a bus clock (Bφ). The clock pulse generator consists of oscillators, PLL circuits, and a
divider.
11.1
Features
The CPG has the following features:
• Four clock modes: Selection of four clock modes according to the frequency range to be used
and direct connection of crystal resonator or external clock input.
• Three clocks generated independently: An internal clock for the CPU and cache (Iφ); a
peripheral clock (Pφ) for the on-chip supporting modules; and a bus clock (Bφ=CKIO) for the
external bus interface.
• Frequency change function: Internal and peripheral clock frequencies can be changed
independently using the PLL circuit and divider circuit within the CPG. Frequencies are
changed by software using frequency control register (FRQCR) settings.
• Power-down mode control: The clock can be stopped for sleep mode and standby mode and
specific modules can be stopped using the module standby function.
Rev. 3.00 Jan. 18, 2008 Page 453 of 1458
REJ09B0033-0300
Section 11
Clock Pulse Generator (CPG)
A block diagram of the CPG is shown in figure 11.1.
Oscillator circuit
Crystal
oscillator
XTAL_USB
USBH/USBF clock
EXTAL_USB
Divider 1
×1
× 1/2
× 1/3
× 1/4
× 1/6
PLL circuit 1
(×1, 2, 3, 4)
CKIO
Crystal
oscillator
XTAL
EXTAL
Internal clock
(Iφ)
Bus clock
(Bφ frequency is the same
as CKIO frequency.)
PLL circuit 2
(×1, 4)
Peripheral clock
(Pφ)
CPG control unit
Clock frequency
control unit
MD2 to MD0
Standby control unit
FRQCR UCLKCR
STBCR
STBCR2 STBCR3 STBCR4 STBCR5
Bus interface
Internal bus
FRQCR : Frequency control register
UCKCR : USBH/USBF clock control register
STBCR : Standby control register 1
STBCR2 : Standby control register 2
Figure 11.1
Rev. 3.00 Jan. 18, 2008 Page 454 of 1458
REJ09B0033-0300
STBCR3 : Standby control register 3
STBCR4 : Standby control register 4
STBCR5 : Standby control register 5
Block Diagram of CPG
Section 11
Clock Pulse Generator (CPG)
The individual clock pulse generator blocks function as follows:
(1) PLL Circuit 1
PLL circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the
CKIO terminal. The multiplication rate is set by the frequency control register. When this is done,
the phase of the leading edge of the internal clock is controlled so that it will agree with the phase
of the leading edge of the CKIO pin.
(2) PLL Circuit 2
PLL circuit 2 quadruples or leaves unchanged the input clock frequency from the crystal oscillator
or EXTAL pin. The multiplication rate is set in the clock operating modes. The clock operating
modes are set by pins MD0, MD1, and MD2. See table 11.2 for more information on clock
operating modes.
(3) Crystal Oscillator
This oscillator is used when a crystal resonator is connected to the XTAL or EXTAL pin. It
operates according to the clock operating mode setting.
(4) Divider 1
Divider 1 generates a clock at the operating frequency used by the internal or peripheral clock.
The operating frequency of the internal clock (Iφ) can be 1, 1/2, 1/3, or 1/4 times the output
frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin.
The operating frequency of the peripheral clock (Pφ) can be 1, 1/2, 1/3, 1/4, or 1/6 times the output
frequency of PLL circuit 1 within 8.34 MHz ≤ Pφ ≤ 33.34 MHz. The division ratio is set in the
frequency control register.
(5) Clock Frequency Control Circuit
The clock frequency control circuit controls the clock frequency using the MD0, MD1, and MD2
pins and the frequency control register.
(6) Standby Control Circuit
The standby control circuit controls the state of the clock pulse generator and other modules
during clock switching or in sleep or standby mode.
Rev. 3.00 Jan. 18, 2008 Page 455 of 1458
REJ09B0033-0300
Section 11
Clock Pulse Generator (CPG)
(7) Frequency Control Register
The frequency control register has control bits assigned for the following functions: clock
output/non-output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the
frequency division ratio of the internal clock and the peripheral clock.
(8) Standby Control Register
The standby control register has bits for controlling the power-down modes. See section 13,
Power-Down Modes, for more information.
(9) USBH/USBF Clock Control Register
The USBH/USBF clock control register specifies a signal source for generation of the
USBH/USBF clock.
Rev. 3.00 Jan. 18, 2008 Page 456 of 1458
REJ09B0033-0300
Section 11
11.2
Clock Pulse Generator (CPG)
Input/Output Pins
Table 11.1 lists the CPG pins and their functions.
Table 11.1 Pin Configuration
Pin Name
Abbreviation
I/O
Description
Mode control pins MD0
Input
Set the clock operating mode
MD1
Input
Set the clock operating mode
MD2
Input
Set the clock operating mode
Crystal I/O pins
XTAL
(clock input pins)
EXTAL
Output
Connects a crystal resonator
Input
Connects a crystal resonator. Also used to input
an external clock.
Clock I/O pin
I/O
Inputs or outputs an external clock
Input
Inputs an external clock to USBH/USBF (48 MHz)
CKIO
External clock pin EXTAL_USB
for USBH/USBF XTAL_USB
Output
Note: To prevent device malfunction, the value of the mode control pin is sampled only upon a
power-on reset.
Rev. 3.00 Jan. 18, 2008 Page 457 of 1458
REJ09B0033-0300
Section 11
11.3
Clock Pulse Generator (CPG)
Clock Operating Modes
Table 11.2 shows the relationship between the mode control pins (MD2 to MD0) combinations
and the clock modes. Table 11.3 shows the available combinations of the values of the clock
modes and frequency control register (FRQCR).
Table 11.2 Clock Operating Modes
Pin Values
Mode
0
1
MD2
0
0
MD1
0
0
MD0
0
1
Clock I/O
Source
EXTAL
EXTAL
Output
CKIO
CKIO
2
0
1
0
CKIO
Crystal
resonator
7
1
1
1
CKIO

PLL2
On/Off
PLL1
On/Off
CKIO
Frequency
ON
ON
(EXTAL)
(x 1)
(x 1, 2, 3, 4)
ON
ON
(x 4)
(x 1, 2, 3, 4)
ON
ON
(x 4)
(x 1, 2, 3, 4)
OFF
ON
(EXTAL) x 4
(Crystal) x 4
(CKIO)
(x 1, 2, 3, 4)
Mode 0: The LSI is supplied with a clock that is wave-formed by PLL circuit 2 after receiving an
external clock from the EXTAL pin. The frequency of CKIO ranges from 24.00 to 66.67
MHz, because the input clock frequency ranges from 24.00 to 66.67 MHz.
Mode 1: The clock supplied to the internal circuitry in the LSI is generated by PLL circuit 2
quadrupling the frequency after receiving an external clock from the EXTAL pin.
Therefore, the frequency of a clock generated outside the LSI can be lower. The
frequency of CKIO ranges from 40.00 to 66.67 MHz, because an input clock with a
frequency range of 10.00 to 16.67 MHz is used.
Mode 2: The clock is generated by an on-chip crystal oscillator, and its frequency is quadrupled by
PLL circuit 2. Therefore, the frequency of a clock generated outside the LSI can be lower.
The frequency of CKIO ranges from 40.00 to 66.67 MHz, because a crystal oscillator with
a frequency range of 10.00 to 16.67 MHz is used.
Mode 7: The CKIO pin works as an input pin in this mode. The frequency of the external clock
supplied to the LSI is multiplied by the setting ratio after the external clock is input via the
CKIO pin and wave-formed by PLL circuit 1. This mode is suitable for connecting a
synchronous DRAM, because the change in the load in the CKIO pin is controlled by PLL
circuit 1.
Rev. 3.00 Jan. 18, 2008 Page 458 of 1458
REJ09B0033-0300
Section 11
Clock Pulse Generator (CPG)
Table 11.3 Possible Combination of Clock Mode and FRQCR Values
Clock
FRQCR PLL
PLL
Ratio*
Mode Value
Circuit 1 Circuit 2 (I:B:P)
Frequency Range of
Input Clock and
Crystal Resonator
Frequency Range of
CKIO Pin
0
1, 2
1000
on (×1)
on (×1)
1:1:1
33.34 MHz
33.34 MHz
1001
on (×1)
on (×1)
1:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1003
on (×1)
on (×1)
1:1:1/4
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1101
on (×2)
on (×1)
2:1:1
33.34 MHz
33.34 MHz
1103
on (×2)
on (×1)
2:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1111
on (×2)
on (×1)
1:1:1
33.34 MHz
33.34 MHz
1113
on (×2)
on (×1)
1:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1202
on (×3)
on (×1)
3:1:1
33.34 MHz
33.34 MHz
1204
on (×3)
on (×1)
3:1:1/2
33.34 MHz to 44.45 MHz
33.34 MHz to 44.45 MHz
1222
on (×3)
on (×1)
1:1:1
33.34 MHz
33.34 MHz
1224
on (×3)
on (×1)
1:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1303
on (×4)
on (×1)
4:1:1
33.34 MHz
33.34 MHz
1313
on (×4)
on (×1)
2:1:1
33.34 MHz
33.34 MHz
1333
on (×4)
on (×1)
1:1:1
33.34 MHz
33.34 MHz
1001
on (×1)
on (×4)
4:4:2
10.00 MHz to 16.67 MHz
40.00 MHz to 66.67 MHz
1003
on (×1)
on (×4)
4:4:1
10.00 MHz to 16.67 MHz
40.00 MHz to 66.67 MHz
1103
on (×2)
on (×4)
8:4:2
10.00 MHz to 16.67 MHz
40.00 MHz to 66.67 MHz
1113
on (×2)
on (×4)
4:4:2
10.00 MHz to 16.67 MHz
40.00 MHz to 66.67 MHz
1204
on (×3)
on (×4)
12:4:2
10.00 MHz to 16.67 MHz
40.00 MHz to 66.67 MHz
1224
on (×3)
on (×4)
4:4:2
10.00 MHz to 16.67 MHz
40.00 MHz to 66.67 MHz
Rev. 3.00 Jan. 18, 2008 Page 459 of 1458
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Section 11
Clock Pulse Generator (CPG)
Clock
FRQCR PLL
PLL
Ratio*
Mode Value
Circuit 1 Circuit 2 (I:B:P)
Frequency Range of
Input Clock and
Crystal Resonator
Frequency Range of
CKIO Pin
7
1000
on (×1)
OFF
1:1:1
33.34 MHz
33.34 MHz
1001
on (×1)
OFF
1:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1003
on (×1)
OFF
1:1:1/4
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1101
on (×2)
OFF
2:1:1
33.34 MHz
33.34 MHz
1103
on (×2)
OFF
2:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1111
on (×2)
OFF
1:1:1
33.34 MHz
33.34 MHz
1113
on (×2)
OFF
1:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1202
on (×3)
OFF
3:1:1
33.34 MHz to 44.45 MHz
33.34 MHz to 44.45 MHz
1204
on (×3)
OFF
3:1:1/2
33.34 MHz to 44.45 MHz
33.34 MHz to 44.45 MHz
1222
on (×3)
OFF
1:1:1
33.34 MHz
33.34 MHz
1224
on (×3)
OFF
1:1:1/2
33.34 MHz to 66.67 MHz
33.34 MHz to 66.67 MHz
1303
on (×4)
OFF
4:1:1
33.34 MHz
33.34 MHz
1313
on (×4)
OFF
2:1:1
33.34 MHz
33.34 MHz
1333
on (×4)
OFF
1:1:1
33.34 MHz
33.34 MHz
Notes: *
1.
2.
3.
4.
5.
The input clock is 1.
Maximum frequency: Iφ = 133.34 MHz, Bφ (CKIO) = 66.67 MHz, Pφ = 33.34 MHz
Use the CKIO frequency within 33.34 MHz ≤ CKIO ≤ 66.67 MHz.
The input to divider 1 is the output of PLL circuit 1.
Use the internal clock frequency within 33.34 MHz ≤ Iφ ≤ 133.34 MHz.
The internal clock frequency is the product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and
the division ratio selected by the IFC bit in FRQCR.
Do not set the internal clock frequency lower than the CKIO pin frequency.
Use the peripheral clock frequency within 8.34 MHz ≤ Pφ ≤ 33.34 MHz.
The peripheral clock frequency is the product of the frequency of the CKIO pin, the
frequency multiplication ratio of PLL circuit 1 selected by the STC bit in FRQCR, and
the division ratio selected by the PFC bit in FRQCR.
Do not set the peripheral clock frequency higher than the frequency of the CKIO pin.
× 1, × 2, × 3, or × 4 can be used as the multiplication ratio of PLL circuit 1. × 1, × 1/2,
× 1/3, or × 1/4can be selected as the division ratio of an internal clock. × 1, × 1/2, × 1/3,
× 1/4, or
× 1/6 can be selected as the division ratio of a peripheral clock. Set the rate in FRQCR.
Rev. 3.00 Jan. 18, 2008 Page 460 of 1458
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Section 11
11.4
Clock Pulse Generator (CPG)
Register Descriptions
The CPG has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and access size of these registers.
• Frequency control register (FRQCR)
• USBH/USBF clock control register (UCLKCR)
11.4.1
Frequency Control Register (FRQCR)
The frequency control register (FRQCR) is a 16-bit readable/writable register used to specify
whether a clock is output from the CKIO pin, the frequency multiplication ratio of PLL circuit 1,
and the frequency division ratio of the internal clock and the peripheral clock.
Only word access can be used on the FRQCR register. FRQCR is initialized by a power-on reset,
but not initialized by a power-on reset at the WDT overflow. FRQCR retains its value in a manual
reset and in standby mode.
The write values to bits 14, 13, 11, 10, 7, 6, and 3 should always be 0.
Bit
Bit Name
Initial
Value
R/W
Description
15
PLL2EN
0
R/W
PLL2 Enable
PLL2EN specifies whether make the PLL circuit 2 ON in
clock operating mode 7.
PLL circuit 2 is ON in clock operating modes other than
mode 7 regardless of the PLL2EN setting.
0: PLL circuit 2 is OFF
1: PLL circuit 2 is ON
14, 13 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 461 of 1458
REJ09B0033-0300
Section 11
Clock Pulse Generator (CPG)
Bit
Bit Name
Initial
Value
R/W
Description
12
CKOEN
1
R/W
Clock Output Enable
CKOEN specifies whether a clock is output from the
CKIO pin or the CKIO pin is placed in the level-fixed
state in the standby mode, CKIO pin is fixed at low
during STATUS 1 = L, and STATUS0 = H, when CKOEN
is set to 0. Therefore, the malfunction of an external
circuit because of an unstable CKIO clock in releasing
the standby mode can be prevented. The CKIO pin
becomes to input pin regardless of the value of the
CKOEN bit in clock operating mode 7.
0: CKIO pin goes to low level state in standby mode
1: Clock is output from CKIO pin
11, 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
9
STC1
0
R/W
Frequency Multiplication Ratio of PLL Circuit 1
8
STC0
0
R/W
00: × 1 time
01: × 2 times
10: × 3 times
11: × 4 times
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
IFC1
0
R/W
Internal Clock Frequency Division Ratio
4
IFC0
0
R/W
These bits specify the frequency division ratio of the
internal clock (Iφ) with respect to the output frequency of
PLL circuit 1.
00: × 1 time
01: × 1/2 time
10: × 1/3 time
11: × 1/4 time
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
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Section 11
Clock Pulse Generator (CPG)
Bit
Bit Name
Initial
Value
R/W
Description
2
PFC2
0
R/W
Peripheral Clock Frequency Division Ratio
1
PFC1
1
R/W
0
PFC0
1
R/W
These bits specify the division ratio of the peripheral
clock (Pφ) frequency with respect to the output frequency
of PLL circuit 1.
000: × 1 time
001: × 1/2 time
010: × 1/3 time
011: × 1/4 time
100: × 1/6 time
Other than above: Reserved (setting prohibited)
Rev. 3.00 Jan. 18, 2008 Page 463 of 1458
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Section 11
11.4.2
Clock Pulse Generator (CPG)
USBH/USBF Clock Control Register (UCLKCR)
The USBH/USBF clock control register is an 8-bit readable/writable register. UCLKCR is
initialized to H'60 by a power-on reset. Word-size access is used to write to this register. This
writing should be performed with H'A5 in the upper byte and the write data in the lower byte.
Bit
Bit Name
Initial
Value
R/W
Description
7
USSCS2
0
R/W
Source Clock Select
6
USSCS1
1
R/W
These bits select the source clock.
5
USSCS0
1
R/W
000: Clock stopped
001: Setting prohibited
010: Setting prohibited
011: Initial value
(To run the USBH/USB, however, change the setting to
"110: EXTAL_USB" or "111: USB crystal resonator".)
100: Setting prohibited
101: Setting prohibited
110: EXTAL_USB
111: USB crystal resonator
4
USSTB
0
R/W
Standby USB Crystal
Specifies stop or operation of the USB crystal oscillator
in standby mode.
0: USB crystal oscillator stops in standby mode when the
STBXTL bit (bit 4) in the STBCR register is 0.
1: USB crystal oscillator continues operating in standby
mode
3 to 0 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 464 of 1458
REJ09B0033-0300
Section 11
11.5
Clock Pulse Generator (CPG)
Changing Frequency
The frequency of the internal clock and peripheral clock can be changed either by changing the
multiplication rate of PLL circuit 1 or by changing the division rates of divider 1. All of these are
controlled by software through FRQCR. The methods are described below.
11.5.1
Changing Multiplication Rate
A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time.
1. In the initial state, the multiplication rate of PLL circuit 1 is 1.
2. Set a value that will become the specified oscillation settling time in the WDT and stop the
WDT. The following must be set:
TME bit in WTCSR = 0: WDT stops
CKS2 to CKS0 bits in WTCSR: Division ratio of WDT count clock
WTCNT: Initial counter value
3. Set the desired value in the STC1 and STC0 bits. The division ratio can also be set in the IFC1
and IFC0 bits and PFC2 to PFC0 bits.
4. The processor pauses internally and the WDT starts incrementing. The internal and peripheral
clocks both stop and the WDT is supplied with the clock. The clock will continue to be output
at the CKIO pin.
5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins
operating again. The WDT stops after it overflows.
11.5.2
Changing Division Ratio
The WDT will not count unless the multiplication rate is changed simultaneously.
1. In the initial state, IFC1 and IFC0 = 00 and PFC2 to PFC0 = 011.
2. Set the IFC1, IFC0, and PFC2 to PFC0 bits to the new division ratio. The values that can be set
are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the
wrong value is set, the processor will malfunction.
3. The clock is immediately supplied at the new division ratio.
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REJ09B0033-0300
Section 11
11.6
Clock Pulse Generator (CPG)
Usage Notes
Note the following when using the USBH and USBF.
1.
2.
3.
4.
5.
When the USBH and USBF are not used, it is recommended that UCLKCR should be cleared
to H'00 to halt the clock.
Halt the USBH and USBF modules before changing the value of UCLKCR. This is done by
selecting the "Clock stopped" setting with the module stop bit 31 (USBH module stop) and
module stop bit 30 (USBF module stop) in STBCR3.
UCLKCR is initialized only by a power-on reset. In a manual reset, it retains its current set
values.
When using the USBH/USBF, be sure to set the peripheral clock (Pφ) to a frequency higher
than 13 MHz.
When using the USBH, be sure to set the bus clock (Bφ) to a frequency higher than 32 MHz.
11.7
(1)
Notes on Board Design
When Using an External Crystal Resonator
Place the crystal resonator, capacitors CL1 and CL2, and damping resistor R close to the EXTAL
and XTAL pins. To prevent induction from interfering with correct oscillation, use a common
grounding point for the capacitors connected to the resonator, and do not locate a wiring pattern
near these components.
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REJ09B0033-0300
Section 11
Clock Pulse Generator (CPG)
Avoid crossing
signal lines
CL1
CL2
R
EXTAL
XTAL
This LSI
Note: The values for CL1, CL2, and the damping resistance should be determined after
consultation with the crystal manufacturer.
Figure 11.2
(2)
Points for Attention when Using Crystal Resonator
Bypass Capacitors
Insert a laminated ceramic capacitor as a bypass capacitor for each VSS/VCC pair. Mount the bypass
capacitors to the power supply pins, and use components with a frequency characteristic suitable
for the operating frequency of the LSI, as well as a suitable capacitance value.
(3)
When Using a PLL Oscillator Circuit
Keep the wiring from the PLL VCC and VSS connection pattern to the power supply pins short, and
make the pattern width large, to minimize the inductance component.
Connect the EXTAL pin to VCC or VSSQ and make the XTAL pin open in clock mode 7.
The analog power supply system of the PLL is sensitive to a noise. Therefore the system
malfunction may occur by the intervention with other power supply. Do not supply the analog
power supply with the same resource as the digital power supply of VCC and VCCQ.
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REJ09B0033-0300
Section 11
Clock Pulse Generator (CPG)
Avoid crossing
signal lines
Vcc(PLL2)
Power
Vcc supply
Vss(PLL2)
Vcc(PLL1)
Vss
Vss(PLL1)
Figure 11.3
Points for Attention when Using PLL Oscillator Circuit
Rev. 3.00 Jan. 18, 2008 Page 468 of 1458
REJ09B0033-0300
Section 12 Watchdog Timer (WDT)
Section 12 Watchdog Timer (WDT)
This LSI includes the watchdog timer (WDT).
This LSI can be reset by the overflow of the counter when the value of the counter has not been
updated because of a system runaway.
The WDT is a single-channel timer that uses a peripheral clock as an input and counts the clock
settling time when clearing software standby mode and temporary standbys, such as frequency
changes. It can also be used as an interval timer.
12.1
Features
The WDT has the following features:
• Can be used to ensure the clock settling time: Use the WDT to cancel software standby mode
and the temporary standbys which occur when the clock frequency is changed.
• Can switch between watchdog timer mode and interval timer mode.
• Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow.
• An interrupt is generated in interval timer mode
An interval timer interrupt is generated when the counter overflows.
• Choice of eight counter input clocks
Eight clocks (×1 to ×1/4096) that are obtained by dividing the peripheral clock can be chosen.
• Choice of two resets
Power-on reset and manual reset are available.
WDTS300B_000020030200
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Section 12 Watchdog Timer (WDT)
Figures 12.1 shows a block diagram of the WDT.
WDT
Standby
cancellation
Standby
mode
Standby
control
Peripheral
clock
Internal
reset
request
Divider
Reset
control
Clock selection
Clock selector
Interrupt
request
Overflow
Interrupt
control
Clock
WTCSR
WTCNT
Bus interface
[Legend]
WTCSR:
WTCNT:
Watchdog timer control/status register
Watchdog timer counter
Figure 12.1 Block Diagram of WDT
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Section 12 Watchdog Timer (WDT)
12.2
Register Descriptions for WDT
The WDT has the following two registers. Refer to section 37, List of Registers, for more details
on the addresses and states of these registers in each operating mode.
• Watchdog timer counter (WTCNT)
• Watchdog timer control/status register (WTCSR)
12.2.1
Watchdog Timer Counter (WTCNT)
WTCNT is an 8-bit readable/writable register that increments on the selected clock. When an
overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time
mode. The WTCNT counter is not initialized by an internal reset due to the WDT overflow. The
WTCNT counter is initialized to H'00 only by a power-on reset. Use a word access to write to the
WTCNT counter, with H'5A in the upper byte. Use a byte access to read WTCNT.
Note: WTCNT differs from other registers in that it is more difficult to write to. See section
12.2.3, Notes on Register Access, for details.
12.2.2
Watchdog Timer Control/Status Register (WTCSR)
WTCSR is an 8-bit readable/writable register composed of bits to select the clock used for the
count, bits to select the timer mode, and overflow flags. WTCSR holds its value in an internal
reset due to the WDT overflow. WTCSR is initialized to H'00 only by a power-on reset.
When used to count the clock settling time for canceling a software standby, it retains its value
after counter overflow. Use a word access to write to WTCSR, with H'A5 in the upper byte. Use a
byte access to read WTCSR.
Note: WTCSR differs from other registers in that it is more difficult to write to. See section
12.2.3, Notes on Register Access, for details.
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Section 12 Watchdog Timer (WDT)
Bit
Bit Name
Initial
Value
R/W
Description
7
TME
0
R/W
Timer Enable
Starts and stops timer operation. Clear this bit to 0 when
using the WDT in software standby mode or when
changing the clock frequency.
0: Timer disabled: Count-up stops and WTCNT value is
retained
1: Timer enabled
6
WT/IT
0
R/W
Timer Mode Select
Selects whether to use the WDT as a watchdog timer or
an interval timer.
0: Interval timer mode
1: Watchdog timer mode
Note: If WT/IT is modified when the WDT is operating,
the up-count may not be performed correctly.
5
RSTS
0
R/W
Reset Select
Selects the type of reset when the WTCNT overflows in
watchdog timer mode. In interval timer mode, this setting
is ignored.
0: Power-on reset
1: Manual reset
4
WOVF
0
R/W
Watchdog Timer Overflow
Indicates that the WTCNT has overflowed in watchdog
timer mode. This bit is not set in interval timer mode.
0: No overflow
1: WTCNT has overflowed in watchdog timer mode
3
IOVF
0
R/W
Interval Timer Overflow
Indicates that the WTCNT has overflowed in interval timer
mode. This bit is not set in watchdog timer mode.
0: No overflow
1: WTCNT has overflowed in interval timer mode
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Section 12 Watchdog Timer (WDT)
Bit
Bit Name
Initial
Value
R/W
Description
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select the clock to be used for the WTCNT
count from the eight types obtainable by dividing the
peripheral clock (Pφ). The overflow period that is shown
inside the parenthesis in the table is the value when the
peripheral clock (Pφ) is 15 MHz.
000: Pφ (17 µs)
001: Pφ /4 (68 µs)
010: Pφ /16 (273 µs)
011: Pφ /32 (546 µs)
100: Pφ /64 (1.09 ms)
101: Pφ /256 (4.36 ms)
110: Pφ /1024 (17.48 ms)
111: Pφ /4096 (69.91 ms)
Note: If bits CKS2 to CKS0 are modified when the WDT
is operating, the up-count may not be performed
correctly. Ensure that these bits are modified only
when the WDT is not operating.
12.2.3
Notes on Register Access
The watchdog timer counter (WTCNT) and watchdog timer control/status register (WTCSR) are
more difficult to write to than other registers. The procedure for writing to these registers is given
below.
• Writing to WTCNT and WTCSR
These registers must be written by a word transfer instruction. They cannot be written by a
byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A
and transfer the lower byte as the write data, as shown in figure 12.3. When writing to
WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer
procedure writes the lower byte data to WTCNT or WTCSR.
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Section 12 Watchdog Timer (WDT)
WTCNT write
15
Address: H'A415FF84
8
7
H'5A
0
Write data
WTCSR write
15
Address: H'A415FF86
8
H'A5
7
0
Write data
Figure 12.2 Writing to WTCNT and WTCSR
12.3
WDT Operation
12.3.1
Canceling Software Standbys
The WDT can be used to cancel software standby mode with an NMI interrupt or external
interrupt (IRQ). The procedure is described below. (The WDT does not run when resets are used
for canceling, so keep the RESETP pin low until the clock stabilizes.)
1. Before transition to software standby mode, always clear the TME bit in WTCSR to 0. When
the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the
count overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. Move to software standby mode by executing a SLEEP instruction to stop the clock.
4. The WDT starts counting by detecting the edge change of the NMI signal.
5. When the WDT count overflows, the CPG starts supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
6. Since the WDT continues counting from H'00, set the STBY bit in STBCR to 0 in the interrupt
processing program and this will stop the WDT. When the STBY bit remains 1, the LSI again
enters software standby mode when the WDT has counted up to H'80. This software standby
mode can be canceled by a power-on reset.
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Section 12 Watchdog Timer (WDT)
12.3.2
Changing Frequency
To change the frequency used by the PLL, use the WDT. When changing the frequency only by
switching the divider, do not use the WDT.
1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit
is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows.
2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for
the counter in the WTCNT counter. These values should ensure that the time till count
overflow is longer than the clock oscillation settling time.
3. When the frequency control register (FRQCR) is written, the processor stops temporarily. The
WDT starts counting.
4. When the WDT count overflows, the CPG resumes supplying the clock and the processor
resumes operation. The WOVF flag in WTCSR is not set when this happens.
5. The counter stops at the values H'00.
6. Before changing WTCNT after the execution of the frequency change instruction, always
confirm that the value of WTCNT is H'00 by reading WTCNT.
12.3.3
Using Watchdog Timer Mode
1. Set the WT/IT bit in WTCSR to 1, set the reset type in the RSTS bit, set the type of count
clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT
counter.
2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode.
3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent
the counter from overflowing.
4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the
type of reset specified by the RSTS bit. The counter then resumes counting.
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Section 12 Watchdog Timer (WDT)
12.3.4
Using Interval Timer Mode
When operating in interval timer mode, interval timer interrupts are generated at every overflow of
the counter. This enables interrupts to be generated at set periods.
1. Clear the WT/IT bit in WTCSR to 0, set the type of count clock in the CKS2 to CKS0 bits, and
set the initial value of the counter in the WTCNT counter.
2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode.
3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval
timer interrupt request is sent to the INTC. The counter then resumes counting.
Rev. 3.00 Jan. 18, 2008 Page 476 of 1458
REJ09B0033-0300
Section 13
Section 13
Power-Down Modes
Power-Down Modes
This LSI has four types of power-down modes: Sleep mode, software standby mode, module
standby function, and hardware standby mode.
13.1
Features
• Supports sleep/software standby/module standby/hardware standby.
13.1.1
Power-Down Modes
This LSI has the following power-down modes and function:
• Sleep mode
• Software standby mode
• Module standby function (DSP, cache, TLB, X/Y memory, UBC, DMAC, H-UDI, and on-chip
peripheral module)
• Hardware standby mode
LPWS300A_000020011000
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REJ09B0033-0300
Section 13
Power-Down Modes
Table 13.1 shows the transition conditions for entering the modes from the program execution
state, as well as the CPU and peripheral module states in each mode and the procedures for
canceling each mode.
Table 13.1 States of Power-Down Modes
State
CPG
CPU
CPU
Register
Execute SLEEP
Runs
instruction with
STBY bit in STBCR
cleared to 0
Halts
Held
Halts
Software Execute SLEEP
Standby instruction with
STBY bit in STBCR
mode
set to 1
Halts
Transition
Conditions
Mode
Sleep
mode
Held
On-Chip
Memory
On-Chip
Periphera External
l Modules Memory
Halts
(contents
remained)
Run
Halts
(contents
remained)
Halt*
Canceling
Procedure
Auto•
refreshing
•
Interrupt
Reset
Self• Interrupt
refreshing
(NMI, IRQ
(edge
detection),
RTC, TMU,
PINT
•
Module
standby
function
Set MSTP bit in
STBCR to 1
Runs
Runs/ Held
halts
Specified
Specified
module halts module
(contents
halts
remained)
Reset
Auto• Clear
refreshing
MSTP bit to
0
•
Power-on
reset
Hardware Set CA pin to low
standby
mode
Note:
*
13.1.2
Halts
Halts
Held
Held
Halt*
Self• Power-on
refreshing
reset
The RTC operates when the START bit in RCR2 is set to 1. For details, see section 17,
Realtime Clock (RTC).
Reset
Resetting occurs when power is supplied, and when execution is started again from an initialized
state. There are two types of reset: A power-on reset and a manual reset. In a power-on reset, all
processing in execution is suspended, all unprocessed events are canceled, and reset processing
starts immediately. On the other hand, processing to retain the contents of external memory is
continued in a manual reset. The conditions for generating power-on and manual resets are as
follows.
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REJ09B0033-0300
Page 478 of 1458
Section 13
(1)
Power-Down Modes
Power-On Reset
1. Driving the RESETP pin low.
2. While the WT/IT bit in WTCSR is set to 1 and the RSTS bit is cleared to 0, the WDT starts
counting and continues until it overflows.
3. Generation of the H-UDI reset (for details on the H-UDI reset, refer to section 36, User
Debugging Interface (H-UDI)).
(2)
Manual Reset
1. Driving the RESETM pin low.
2. While the WT/IT bit in WTCSR and the RSTS bit are set to 1, the WDT starts counting and
continues until it overflows.
13.2
Input/Output Pins
Table 13.2 lists the pin configuration related to power-down modes.
Table 13.2 Pin Configuration
Pin Name
Abbreviation I/O
Status 1 output
STATUS1
Status 0 output
STATUS0
Description
Output Operating state of the processor.
HH: Reset
HL: Sleep mode
LH: Standby mode
LL: Normal operation
Power-on reset
input
RESETP
Input
Power-on reset occurs at low-level.
Manual-reset input
RESETM
Input
Manual reset occurs at low-level.
Chip active
CA
Input
Hardware standby mode entered at low-level.
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REJ09B0033-0300
Section 13
13.3
Power-Down Modes
Register Descriptions
There are following five registers related to power-down modes. Refer to section 37, List of
Registers, for more details on the addresses and states of these registers in each operating mode.
•
•
•
•
•
Standby control register (STBCR)
Standby control register 2 (STBCR2)
Standby control register 3 (STBCR3)
Standby control register 4 (STBCR4)
Standby control register 5 (STBCR5)
13.3.1
Standby Control Register (STBCR)
STBCR is an 8-bit readable/writable register that specifies the state of power-down modes.
Bit
Bit Name
Initial
Value
R/W
Description
7
STBY
0
R/W
Standby
Specifies transition to software standby mode.
0: Executing SLEEP instruction enters chip into sleep
mode
1: Executing SLEEP instruction enters chip into software
standby mode
6, 5

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
STBXTL
0
R/W
Standby Crystal
Specifies halt/operation of a crystal oscillator in standby
mode.
0: Crystal oscillator is halted in standby mode
1: Crystal oscillator is operated continuously in standby
mode
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Page 480 of 1458
Section 13
Bit
Bit Name
Initial
Value
R/W
Description
3

0
R
Reserved
Power-Down Modes
This bit is always read as 0. The write value should
always be 0.
2
MSTP2
0
R/W
Module Stop Bit 2
When the MSTP2 bit is set to 1, the supply of the clock to
the TMU is halted.
0: TMU operates
1: Clock supply to TMU halted
1
MSTP1
0
R/W
Module Stop Bit 1
When the MSTP1 bit is set to 1, the supply of the clock to
the RTC is halted.
0: RTC operates
1: Clock supply to RTC halted
0

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
13.3.2
Standby Control Register 2 (STBCR2)
STBCR2 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSTP10
0
R/W
Module Stop Bit 10
When the MSTP10 bit is set to 1, the supply of the clock
to the H-UDI is halted.
0: H-UDI operates
1: Clock supply to H-UDI halted
6
MSTP9
0
R/W
Module Stop Bit 9
When the MSTP9 bit is set to 1, the supply of the clock to
the UBC is halted.
0: UBC operates
1: Clock supply to UBC halted
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Section 13
Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
5
MSTP8
0
R/W
Module Stop Bit 8
When the MSTP8 bit is set to 1, the supply of the clock to
the DMAC is halted.
0: DMAC operates
1: Clock supply to DMAC halted
4
MSTP7
0
R/W
Module Stop Bit 7
When the MSTP7 bit is set to 1, the supply of the clock to
the DSP is halted.
0: DSP operates
1: Clock supply to DSP halted
3
MSTP6
0
R/W
Module Stop Bit 6
When the MSTP6 bit is set to 1, the supply of the clock to
the TLB is halted.
0: TLB operates
1: Clock supply to TLB halted
2
MSTP5
0
R/W
Module Stop Bit 5
When the MSTP5 bit is set to 1, the supply of the clock to
the cache memory is halted.
0: Cache memory operates
1: Clock supply to cache memory halted
1

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
0
MSTP3
0
R/W
Module Stop Bit 3
When the MSTP3 bit is set to 1, the supply of the clock to
the X/Y memory is halted.
0: X/Y memory operates
1: Clock supply to X/Y memory halted
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Page 482 of 1458
Section 13
13.3.3
Power-Down Modes
Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode.
Bit
Bit Name
Initial
Value
R/W
Description
7
MSTP37
0
R/W
Module Stop Bit 37
When the MSTP37 bit is set to 1, the supply of the clock
to the SIOF1 is halted.
0: SIOF1 operates
1: Clock supply to SIOF1 halted
6
MSTP36
0
R/W
Module Stop Bit 36
When the MSTP36 bit is set to 1, the supply of the clock
to the SIOF0 is halted.
0: SIOF0 operates
1: Clock supply to SIOF0 halted
5
MSTP35
0
R/W
Module Stop Bit 35
When the MSTP35 bit is set to 1, the supply of the clock
to the CMT is halted. However, count-up operation is
continued when the channel 5 is in the operation.
0: CMT operates
1: Clock supply to CMT halted
4

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
3
MSTP33
0
R/W
Module Stop Bit 33
When the MSTP33 bit is set to 1, the supply of the clock
to the ADC is halted.
0: ADC operates
1: Clock supply to ADC halted
2
MSTP32
0
R/W
Module Stop Bit 32
When the MSTP32 bit is set to 1, the supply of the clock
to the DAC is halted.
0: DAC operates
1: Clock supply to DAC halted
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Section 13
Power-Down Modes
Bit
Bit Name
Initial
Value
R/W
Description
1
MSTP31
0
R/W
Module Stop Bit 31
When the MSTP31 bit is set to 1, the supply of the clock
to the USBH is halted.
0: USBH operates
1: Clock supply to USBH halted
0
MSTP30
0
R/W
Module Stop Bit 30
When the MSTP30 bit is set to 1, the supply of the clock
to the USBF is halted.
0: USBF operates
1: Clock supply to USBF halted
13.3.4
Standby Control Register 4 (STBCR4)
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode.
Bit
Bit Name
Initial
Value
R/W
Description
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
MSTP45
0
R/W
Module Stop Bit 45
When the MSTP45 bit is set to 1, the supply of the clock
to the PCC is halted.
0: PCC operates
1: Clock supply to PCC halted
4
MSTP44
0
R/W
Module Stop Bit 44
When the MSTP44 bit is set to 1, the supply of the clock
2
to the I C is halted.
0: I2C operates
2
1: Clock supply to I C halted
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Section 13
Bit
Bit Name
Initial
Value
R/W
Description
3
MSTP43
0
R/W
Module Stop Bit 43
Power-Down Modes
When the MSTP43 bit is set to 1, the supply of the clock
to the MMC is halted.
0: MMC operates
1: Clock supply to MMC halted
2
MSTP42
0
R/W
Module Stop Bit 42
When the MSTP42 bit is set to 1, the supply of the clock
to the SIM is halted.
0: SIM operates
1: Clock supply to SIM halted
1
MSTP41
0
R/W
Module Stop Bit 41
When the MSTP41 bit is set to 1, the supply of the clock
to the SCIF1 is halted.
0: SCIF1 operates
1: Clock supply to SCIF1 halted
0
MSTP40
0
R/W
Module Stop Bit 40
When the MSTP40 bit is set to 1, the supply of the clock
to the SCIF0 is halted.
0: SCIF0 operates
1: Clock supply to SCIF0 halted
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Section 13
13.3.5
Power-Down Modes
Standby Control Register 5 (STBCR5)
STBCR5 is an 8-bit readable/writable register that controls the operation of modules in powerdown mode.
Bit
Bit Name
Initial
Value
R/W
Description
7

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
MSTP56
0
R/W
Module Stop Bit 56
When the MSTP56 bit is set to 1, the supply of the clock
to the SDHI is halted.
0: Clock supply to SDHI halted
1: SDHI operates
Note: On the models not having the SDHI, this bit is
reserved and is always read as 0. The write value
should always be 0.
5

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
4
MSTP54
0
R/W
Module Stop Bit 54
When the MSTP54 bit is set to 1, the supply of the clock
to the TPU is halted.
0: TPU operates
1: Clock supply to TPU halted
3

0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
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Section 13
Bit
Bit Name
Initial
Value
R/W
Description
2
MSTP52
0
R/W
Module Stop Bit 52
Power-Down Modes
When the MSTP52 bit is set to 1, the supply of the clock
to the SSL is halted.
0: SSL operates
1: Clock supply to SSL halted
Note: On the models not having the SSL, this bit is
reserved. The write value should always be 1.
1
MSTP51
0
R/W
Module Stop Bit 51
When the MSTP51 bit is set to 1, the supply of the clock
to the AFEIF is halted.
0: AFEIF operates
1: Clock supply to AFEIF halted
0
MSTP50
0
R/W
Module Stop Bit 50
When the MSTP50 bit is set to 1, the supply of the clock
to the LCDC is halted.
0: LCDC operates
1: Clock supply to LCDC halted
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Section 13
Power-Down Modes
13.4
Sleep Mode
13.4.1
Transition to Sleep Mode
Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the
program execution state to sleep mode. Although the CPU halts immediately after executing the
SLEEP instruction, the contents of the CPU registers remain unchanged. The on-chip peripheral
modules continue to operate in sleep mode and the clock continues to be output to the CKIO pin.
In sleep mode the output of the STATUS0 pin and STATUS1 pin go high and low, respectively.
13.4.2
Canceling Sleep Mode
Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, PINT, and on-chip peripheral module) or
reset. Interrupts are accepted in sleep mode even when the BL bit in SR is 1. If necessary, save
SPC and SSR to the stack before executing the SLEEP instruction.
(1)
Canceling with Interrupt
When an NMI, IRQ, IRL, PINT, or on-chip peripheral module interrupt occurs, sleep mode is
canceled and interrupt exception handling is executed. A code indicating the interrupt source is set
in INTEVT and INTEVT2.
(2)
Canceling with Reset
Sleep mode is canceled by a power-on reset or a manual reset.
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Section 13
13.5
Software Standby Mode
13.5.1
Transition to Software Standby Mode
Power-Down Modes
Executing the SLEEP instruction when the STBY bit in STBCR is 1 causes a transition from the
program execution state to software standby mode. In software standby mode, not only the CPU
but also the clock and on-chip peripheral modules halt. The clock output from the CKIO pin also
halts.
The contents of the CPU and cache registers remain unchanged. Some registers of the on-chip
peripheral modules are, however, initialized. Refer to section 37, List of Registers, for the register
states of the on-chip peripheral modules in software standby mode. The procedure for a transition
to software standby mode is as follows.
1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT.
2. Clear the WDT's timer counter (WTCNT) to 0 and set the CKS2 to CKS0 bits in WTCSR to
appropriate values to secure the specified oscillation settling time.
3. After the STBY bit in STBCR is set to 1, the SLEEP instruction is executed.
4. Software standby mode is entered and the clocks within the chip are halted. The output of the
STATUS0 pin and STATUS1 pin go high and low, respectively.
13.5.2
Canceling Software Standby Mode
Software standby mode is canceled by interrupts (NMI, IRQ (edge detection), RTC, TMU, and
PINT) or a reset.
(1)
Canceling with Interrupt
The on-chip WDT can be used for hot starts. When the chip detects an NMI, IRQ (edge
detection)*1, RTC*1, TMU*1, or PINT*1 interrupt, the clock will be supplied to the entire chip and
software standby mode will be canceled after the time set in the WDT's timer control/status
register has elapsed. Both STATUS1 and STATUS0 pins go low. Interrupt exception handling
then begins and a code indicating the interrupt source is set in INTEVT and INTEVT2. After the
branch to the interrupt handling routine, clear the STBY bit in STBCR. WDT stops automatically.
If the STBY bit is not cleared, WDT continues operation and a transition is made to software
standby mode*2 when WTCNT reaches H'80. Note that a manual reset is not accepted until the
STBY bit is cleared. Interrupts are accepted in software standby mode even when the BL bit in SR
is 1. If necessary, save SPC and SSR to the stack before executing the SLEEP instruction.
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Section 13
Power-Down Modes
Immediately after an interrupt is detected, the phase of the clock output of the CKIO pin may be
unstable, until software standby mode is canceled.
Notes: 1. Only when the RTC is used, software standby mode can be canceled by IRQ (edge
detection), RTC, TMU, or PINT interrupt.
2. Cancel this software standby mode by a power-on reset.
Interrupt
request
Crystal oscillator settling
time and PLL synchronization
time
WTCNT value
WDT overflow and branch to
interrupt handling routine
Clear the STBY bit in STBCR before
WTCNT reaches H'80. When
he STBY bit in STBCR is cleared,
WTCNT halts automatically.
H'FF
H'80
Time
Figure 13.1
(2)
Canceling Standby Mode with STBY Bit in STBCR
Canceling with Reset
Software standby mode is canceled by a reset with the RESETP pin and RESETM pin. Keep the
RESETP pin and RESETM pin low until the clock oscillation settles in clock operating mode to
use PLL. The internal clock will continue to be output to the CKIO pin.
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Page 490 of 1458
Section 13
13.6
Module Standby Function
13.6.1
Transition to Module Standby Function
Power-Down Modes
Setting the MSTP bits in the standby control register to 1 halts the supply of clocks to the
corresponding on-chip peripheral modules. This function can be used to reduce power
consumption in normal mode. When changing the setting of an MSTP bit to use the module
standby function, be sure to halt operation of the module whose clock supply is to be stopped
before setting the corresponding MSTP bit to 1.
In the module standby state, the states of the external pins of the on-chip peripheral modules differ
depending on the on-chip peripheral module and I/O port settings. Register state is as same as in
standby mode. When changing the setting of an MSTP bit to use the module standby function, be
sure to halt operation of the module whose clock supply is to be stopped before setting the
corresponding MSTP bit to 1.
13.6.2
Canceling Module Standby Function
The module standby function can be canceled by clearing the MSTP bits to 0, or by a power-on
reset.
When canceling the module standby function by clearing the corresponding MSTP bit, be sure to
read the relevant MSTP bit to confirm that it has been cleared to 0.
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REJ09B0033-0300
Section 13
13.7
Power-Down Modes
STATUS Pin Change Timing
The STATUS1 and STATUS0 pin change timings are shown below.
13.7.1
(1)
Reset
Power-on reset
CKIO
RESETP
PLL setting time
2
1
normal *
STATUS
2
reset *
0 to 5 Bcyc *3
normal *
0 to 30 Bcyc*3
Notes: 1. reset : HH (STATUS1 = High, STATUS0 = High)
2. normal : LL (STATUS1 = Low, STATUS0 = Low)
3. Bcyc : Bus clock cycle
Figure 13.2
(2)
STATUS Output at Power-on Reset
Manual reset
CKIO
RESETM
STATUS
normal *
3
reset *
2
3
normal *
0 to 30 Bcyc *4
0Bcyc~ *1,*4
Notes 1. : In manual reset, STATUS = HH (reset) after the current bus cycle is completed
and then internal reset is initiated.
2. : reset: HH (STATUS1 = High, STATUS0 = High)
3. : normal: LL (STATUS1 = Low, STATUS0 = Low)
4. : Bcyc: Bus clock cycle
Figure 13.3
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Jan. 18, 2008
REJ09B0033-0300
STATUS Output at Manual Reset
Page 492 of 1458
Section 13
13.7.2
(1)
Power-Down Modes
Software Standby Mode
Canceling software standby mode by an interrupt
Oscillation stops
Interrupt request
WTD overflow
CKIO
WDT count
STATUS
2
normal *
1
standby *
2
normal *
Notes: 1. standby : LH (STATUS1 = Low, STATUS0 = High)
2. normal : LL (STATUS1 = Low, STATUS0 = Low)
Figure 13.4
(2)
STATUS Output when Software Standby Mode is Canceled by an Interrupt
Canceling software standby mode by a power-on reset
Reset
Oscillation stops
CKIO
*1
RESETP
STATUS
4
normal *
standby *
3
2
4
reset *
Undefined
normal *
0 to 30 Bcyc *5
0 to 10 Bcyc *5
Notes: 1. If a standby mode is canceled by a power on reset, the WDT stops counting.
RESETP must be kept low for the PLL oscillation stabilization time.
2. reset : HH (STATUS1 = High, STATUS0 = High)
3. standby : LH (STATUS1 = Low, STATUS0 = High)
4. normal : LL (STATUS1 = Low, STATUS0 = Low)
5. Bcyc : Bus clock cycle
Figure 13.5
STATUS Output When Software Standby Mode is Canceled by a Power-on
Reset
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REJ09B0033-0300
Section 13
(3)
Power-Down Modes
Canceling software standby mode by a manual reset
Oscillation stops
Reset
CKIO
RESETM
*1
4
3
normal *
STATUS
2
standby *
4
reset *
normal *
0 to 20 Bcyc *5
Notes: 1.
2.
3.
4.
5.
Figure 13.6
13.7.3
(1)
If a standby mode is canceled by a manual reset, the WDT stops counting.
RESETM must be kept low for the PLL oscillation stabilization time.
reset : HH (STATUS1 = High, STATUS0 = High)
standby : LH (STATUS1 = Low, STATUS0 = High)
normal : LL (STATUS1 = Low, STATUS0 = Low)
Bcyc : Bus clock cycle
STATUS Output When Software Standby Mode is Canceled by a Manual
Reset
Sleep Mode
Canceling sleep mode by an interrupt
Interrupt request
CKIO
STATUS
2
1
normal *
sleep *
2
normal *
Notes: 1. sleep : HL (STATUS1 = High, STATUS0 = Low)
2. normal : LL (STATUS1 = Low, STATUS0 = Low)
Figure 13.7
Rev. 3.00
Jan. 18, 2008
REJ09B0033-0300
STATUS Output when Sleep Mode is Canceled by an Interrupt
Page 494 of 1458
Section 13
(2)
Power-Down Modes
Canceling sleep mode by a power-on reset
Reset
CKIO
RESETP
*1
normal *
STATUS
4
sleep *
3
Undefined
2
4
reset *
normal *
0 to 30 Bcyc *5
0 to 10 Bcyc *5
Notes: 1. If PLL1 multiplication rate changed by a power-on reset,
RESETP must be kept low for the oscillation stabilization time.
2. reset : HH (STATUS1 = High, STATUS0 = High)
3. sleep : HL (STSTUS1= High, STATUS0= Low)
4. normal : LL (STATUS1 = Low, STATUS0 = Low)
5. Bcyc : Bus clock cycle
Figure 13.8
(3)
STATUS Output When Sleep Mode is Canceled by a Power-on Reset
Canceling sleep mode by a manual reset
Reset
CKIO
1
RESETM *
STATUS
4
normal *
sleep *
3
reset *
0 to 80 Bcyc *5
2
4
normal *
0 to 30 Bcyc *5
Notes: 1. RESETM must be kept low until STATAU = reset.
2. reset:HH (STATUS1 = High, STATUS0 = High)
3. sleep:HL(STSTUS1= High, STATUS0= Low)
4. normal:LL (STATUS1 = Low, STATUS0 = Low)
5. Bcyc:Bus clock cycle
Figure 13.9
STATUS Output When Sleep Mode is Canceled by a Manual Reset
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REJ09B0033-0300
Section 13
Power-Down Modes
13.8
Hardware Standby Mode
13.8.1
Transition to Hardware Standby Mode
This LSI enters hardware standby mode by driving the CA pin low. In hardware standby mode as
well as a standby mode entered by the SLEEP instruction, all modules stop other than the modules
that operate using the RTC clock.
Hardware standby mode differs from standby mode as follows:
1. Interrupts and manual reset cannot be accepted.
2. TMU does not operate.
3. RTC operates without power supply to the power supply pins other than that of RTC.
If the CA pin goes low, the operation differs according to the CPG status.
• During standby mode
Hardware standby mode is entered with the clock stopped.
Interrupts and manual reset cannot be accepted and TMU halts.
• During WDT operation while the standby mode is canceled by an interrupt
After standby mode is canceled and the CPU restarts operating, a transition to hardware
standby mode occurs.
• Sleep mode
After sleep mode is canceled and the CPU restarts operating, a transition to hardware standby
mode occurs.
Note that the CA pin must be brought low during hardware standby mode.
13.8.2
Canceling the Hardware Standby Mode
Hardware standby mode is canceled by power-on or reset. If the CA pin is pulled high while the
RESETP signal is low, clock oscillation starts. In this case, RESETP must be kept low until clock
oscillation has settled. If RESETP is then pulled high, the CPU initiates the power-on reset
processing. If an interrupt or manual reset is input, correct operation cannot be guaranteed.
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Page 496 of 1458
Section 13
13.8.3
Power-Down Modes
Hardware Standby Mode Timing
Figures 13.10 and 13.11 show signal timings in hardware standby mode. Since the signal on the
CA pin is sampled at the timing of EXTAL_RTC, clock should be input to the EXTAL_RTC pin
when hardware standby mode is entered. In hardware standby mode, the CA pin must be kept low.
The clock oscillation starts if the CA pin is pulled high after the RESETP pin is brought low.
CKIO
CA
RESETP
normal*3
STATUS
standby*2
Undefined
reset*1
0 to 10 Bcyc
Notes: 1.
2.
3.
4.
Figure 13.10
reset : HH (STATUS1 = High, STATUS0 = High)
standby : LHLH (STATUS1 = Low, STATUS0 = High)
normal : LL (STATUS1 = Low, STATUS0 = Low)
Bcyc : Bus clock cycle
Hardware Standby Mode Timing (CA is pulled low in normal operation)
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Section 13
Power-Down Modes
CKIO
CA
RESETP
standby*2
normal*3
standby
STATUS
0 to 10 Bcyc
WDT opeeration
Notes: 1.
2.
3.
4.
reset*1
Undefined
reset : HH (STATUS1 = High, STATUS0 = High)
standby : LH(STATUS1 = Low, STATUS0 = High)
normal : LL (STATUS1 = Low, STATUS0 = Low)
Bcyc : Bus clock cycle
Figure 13.11
Hardware Standby Mode Timing
(CA is pulled low while WDT operates after the standby mode is canceled)
RTC protection
CA
RESETP
STATUS
Normal*3
Standby*2
Power supply
other than Vcc_RTC
and VccQ_RTC
Undefined
Reset*1
0 to 10 Bcyc*4
Normal*3
0 to 30 Bcyc
Specification: Checking the standby state of the STATUS pin
Notes: *1 Reset: HH (STATUS1 = High, STATUS0 = High)
*2 Standby: LH (STATUS1 = Low, STATUS0 = High)
*3 Normal operation: LL (STATUS1 = Low, STATUS0 = Low)
*4 Bcyc: Bus clock cycle
Figure 13.12
Rev. 3.00
Timing When Power of Pins other than VCC_RTC and VCCQ_RTC is Off
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Section 14 Timer Unit (TMU)
Section 14 Timer Unit (TMU)
This LSI includes a three-channel 32-bit timer unit (TMU).
14.1
Features
• Each channel is provided with an auto-reload 32-bit down counter
• All channels are provided with 32-bit constant registers and 32-bit down counters that can be
read or written to at any time
• All channels generate interrupt requests when the 32-bit down counter underflows
(H'00000000 → H'FFFFFFFF)
• Allows selection among five counter input clocks: Pφ/4, Pφ/16, Pφ/64, Pφ/256, and RTC
output clock (16 kHz)
• Allows channels operate when this LSI is in standby mode
Even when this LSI is in standby mode, channels can operate when the RTC output clock is
used as a counter input clock.
TIMTMU0A_000020011000
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REJ09B0033-0300
Section 14 Timer Unit (TMU)
Pφ
RTC output clock
Bus interface
Prescaler
Clock
controller
TSTR
Ch. 0
TCR_0
Counter
controller
TMU_SUNI
TCNT_0
TCOR_0
TUNI0
Ch. 1
TCR_1
Counter
controller
Interrupt
controller
TUNI1
TCNT_1
Peripheral bus
Interrupt
controller
TCOR_1
Ch. 2
TCR_2
Counter
controller
TCNT_2
Interrupt
controller
TUNI2
TCOR_2
TMU
[Legend]
TSTR: Timer start register
TCNT: Timer counter
TCR: Timer control register
TCOR:Timer constant register
TMU_SUNI, TUNI0, TUNI1, and TUNI2: Interrupt requests
Figure 14.1 Block Diagram of TMU
Rev. 3.00 Jan. 18, 2008 Page 500 of 1458
REJ09B0033-0300
Internal bus
Figure 14.1 shows a block diagram of the TMU.
Section 14 Timer Unit (TMU)
14.2
Register Descriptions
The TMU has the following registers. Refer to section 37, List of Registers, for more details on
the addresses and states of these registers in each operating mode. Notation for the CMT registers
takes the form XXX_N, where XXX including the register name and N indicating the channel
number. For example, TCOR_0 denotes the TCOR for channel 0.
(1) Common
• Timer start register (TSTR)
(2) Channel 0
• Timer constant register_0 (TCOR_0)
• Timer counter_0 (TCNT_0)
• Timer control register_0 (TCR_0)
(3) Channel 1
• Timer constant register_1 (TCOR_1)
• Timer counter_1 (TCNT_1)
• Timer control register_1 (TCR_1)
(4) Channel 2
• Timer constant register_2 (TCOR_2)
• Timer counter_2 (TCNT_2)
• Timer control register_2 (TCR_2)
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REJ09B0033-0300
Section 14 Timer Unit (TMU)
14.2.1
Timer Start Register (TSTR)
TSTR is an 8-bit readable/writable register that selects whether to operate or halt the timer
counters (TCNT).
TSTR is initialized to H'00 at a power-on reset, manual reset, or in module stop mode. It is
retained in sleep mode and standby mode.
Bit
Bit Name
Initial
Value
R/W
Description
7 to 3
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
STR2
0
R/W
Counter Start 2
Selects whether to operate or halt timer counter 2
(TCNT_2).
0: TCNT_2 count halted
1: TCNT_2 counts
1
STR1
0
R/W
Counter Start 1
Selects whether to operate or halt timer counter 1
(TCNT_1).
0: TCNT_1 count halted
1: TCNT_1 counts
0
STR0
0
R/W
Counter Start 0
Selects whether to operate or halt timer counter 0
(TCNT_0).
0: TCNT_0 count halted
1: TCNT_0 counts
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Section 14 Timer Unit (TMU)
14.2.2
Timer Control Registers (TCR)
TCR are 16-bit readable/writable registers that control the timer counters (TCNT) and interrupts.
TCR control the issuance of interrupts when the flag indicating timer counter (TCNT) underflow
has been set to 1, and also carry out counter clock selection.
TCR are initialized to H'0000 at a power-on reset or manual reset. They are retained in standby or
sleep mode.
Bit
Bit Name
15 to 9 —
Initial
Value
R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
8
UNF
0
R/(W)* Underflow Flag
Status flag that indicates occurrence of a TCNT
underflow.
0: TCNT has not underflowed
[Clearing condition]
0 is written to UNF
1: TCNT has underflowed
[Setting condition]
TCNT underflows
7, 6
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
UNIE
0
R/W
Underflow Interrupt Control
Controls enabling of interrupt generation when the status
flag (UNF) indicating TCNT underflow has been set to 1.
0: Interrupt due to UNF (TUNI) is disabled
1: Interrupt due to UNF (TUNI) is enabled
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Section 14 Timer Unit (TMU)
Bit
Bit Name
Initial
Value
R/W
Description
4, 3
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
TPSC2
0
R/W
Timer Prescaler 2 to 0
1
TPSC1
0
R/W
Select the TCNT count clock.
0
TPSC0
0
R/W
000: Count on Pφ/4
001: Count on Pφ/16
010: Count on Pφ/64
011: Count on Pφ/256
101: Count on RTC output clock (16 kHz)
Others are setting prohibited.
Note:
14.2.3
*
Only 0 can be written to clear the flag.
Timer Constant Registers (TCOR)
TCOR set the value to be set in TCNT when TCNT underflows.
TCOR are 32-bit readable/writable registers.
TCOR are initialized to H'FFFFFFFF at a power-on reset or manual reset. They are retained in
standby or sleep mode.
14.2.4
Timer Counters (TCNT)
TCNT count down upon input of a clock. The clock input is selected using the TPSC2 to TPSC0
bits in the timer control register (TCR).
When a TCNT count-down results in an underflow (H'00000000 → H'FFFFFFFF), the underflow
flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is
simultaneously set in TCNT itself and the count-down continues from that value.
TCNT are initialized to H'FFFFFFFF at a power-on reset or manual reset. They are retained in
standby or sleep mode.
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REJ09B0033-0300
Section 14 Timer Unit (TMU)
14.3
Operation
Each of the three channels has a 32-bit timer counter (TCNT) and a 32-bit timer constant register
(TCOR). TCNT counts down. The auto-reload function enables synchronized counting.
14.3.1
Counter Operation
When the STR0 to STR2 bits in the timer start register (TSTR) are set to 1, the corresponding
timer counter (TCNT) starts counting. When TCNT underflows, the UNF flag in the
corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an
interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT
and the down-count operation is continued.
(1)
Count Operation Setting Procedure
An example of the procedure for setting the count operation is shown in figure 14.2.
Select operation
Select counter
clock
(1)
(1) Select the counter clock with the
bits TPSC2 to TPSC0 in the
timer control register (TCR).
Set interrupt generation
(2) Use the UNIE bit in TCR to set
(2)
whether to generate an interrupt
when TCNT underflows.
(3) Set a value in the timer constant
Set timer constant
register
(3)
register (TCOR) (the cycle is the
set value plus 1).
(4) Set the initial value in the timer
Initialize timer
counter
counter (TCNT).
(4)
(5) Set the STR bit in the timer start
register (TSTR) to 1 to start
counting.
Start counting
Note:
(5)
When an interrupt has been generated, clear the flag in the interrupt handler that caused it.
If interrupts are enabled without clearing the flag, another interrupt will be generated.
Figure 14.2 Setting Count Operation
Rev. 3.00 Jan. 18, 2008 Page 505 of 1458
REJ09B0033-0300
Section 14 Timer Unit (TMU)
(2)
Auto-Reload Count Operation
Figure 14.3 shows the TCNT auto-reload operation.
TCOR value set to
TCNT during underflow
TCNT value
TCOR
Time
H'00000000
STR0 to STR2
UNF
Figure 14.3 Auto-Reload Count Operation
Rev. 3.00 Jan. 18, 2008 Page 506 of 1458
REJ09B0033-0300
Section 14 Timer Unit (TMU)
(3)
TCNT Count Timing
1. Internal clock
Set the bits TPSC2 to TPSC0 in TCR to select one of the four internal clocks created by
dividing a peripheral module clock (Pφ/4, Pφ/16, Pφ/64, Pφ/256). Figure 14.4 shows the
timing.
Pφ
Divided
clock
TCNT
input clock
TCNT
N+1
N–1
N
Figure 14.4 Count Timing when Internal Clock is Operating
2. Internal RTC clock
Set the bits TPSC2 to TPSC0 in TCR to select the RTC output clock as a clock for timer.
Figure 14.5 shows the timing.
RTC output
clock
TCNT input
clock
TCNT
N+1
N
N-1
Figure 14.5 Count Timing when RTC Clock is Operating
Rev. 3.00 Jan. 18, 2008 Page 507 of 1458
REJ09B0033-0300
Section 14 Timer Unit (TMU)
14.4
Interrupts
There is one source of TMU interrupts: underflow interrupts (TUNI).
14.4.1
Status Flag Set Timing
The UNF bit is set to 1 when TCNT underflows. Figure 14.6 shows the timing.
Pφ
(TCOR value)
H'00000000
TCNT
Underflow
signal
UNF
TUNI
Figure 14.6 UNF Set Timing
14.4.2
Status Flag Clear Timing
The status flag can be cleared by writing 0 from the CPU. Figure 14.7 shows the timing.
TCR write cycle
T1
T2
T3
Pφ
Peripheral address bus
TCR address
UNF, ICPF
Figure 14.7 Status Flag Clear Timing
Rev. 3.00 Jan. 18, 2008 Page 508 of 1458
REJ09B0033-0300
Section 14 Timer Unit (TMU)
14.4.3
Interrupt Sources and Priorities
The TMU generates underflow interrupts for each channel. When the interrupt request flag and
interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the interrupt event
register (INTEVT, INTEVT2) for these interrupts and interrupt processing must be executed
according to the codes.
The relative priorities between channels can be changed using the interrupt controller. For details,
refer to section 7, Exception Handling, and section 8, Interrupt Controller (INTC). Table 14.1 lists
TMU interrupt sources.
Table 14.1 TMU Interrupt Sources
Channel
Interrupt Source
Description
Priority
0
TUNI0
Underflow interrupt 0
High
1
TUNI1
Underflow interrupt 1
2
TUNI2
Underflow interrupt 2
Low
Software standby mode can be cancelled by TSU_SUNI which is OR of an underflow interrupt for
each TMU channel. (It is available when the RTC output clock is selected as a counter input
clock.)
TMU_SUNI is processed as an interrupt which differs from an underflow interrupt for each
channel by the interrupt controller (INTC). Therefore, an underflow interrupt for each channel and
TMU_SUNI should be used differently.
When canceling software standby mode, set the bits 11 to 8 in interrupt priority register D (IPRD)
of INTC to any value and bits 15 to 4 in interrupt priority register A (IPRA) of INTC to H'000 so
that only the TMU_SUNI is accepted. In the TMU_SUNI interrupt routine, clear both the under
flow flag (UNF) in the timer control register (TCR) and the TMU_SUNI interrupt request bit
(TMU_SUNIR) in the interrupt request register 0 of INTC.
In the normal operating state, set the bits 11 to 8 in IPRD to H'0 and bits 15 to 4 in IPRA to any
value so that an underflow interrupt can be accepted for each channel. For details, see section 8,
Interrupt Controller (INTC).
Rev. 3.00 Jan. 18, 2008 Page 509 of 1458
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Section 14 Timer Unit (TMU)
14.5
Usage Notes
14.5.1
Writing to Registers
Synchronization processing is not performed for timer counting during register writes. When
writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in the
timer start register (TSTR) to halt timer counting.
14.5.2
Reading Registers
Synchronization processing is performed for timer counting during register reads. When timer
counting and register read processing are performed simultaneously, the register value before
TCNT counting down with synchronization processing is read.
Rev. 3.00 Jan. 18, 2008 Page 510 of 1458
REJ09B0033-0300
Section 15
Section 15
16-Bit Timer Pulse Unit (TPU)
16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises four 16-bit timer channels.
15.1
Features
• Maximum 4-pulse output
 A total of 16 timer general registers (TGRA to TGRD × 4 ch.) are provided (four each for
channels). TGRA can be set as an output compare register.
 TGRB, TGRC, and TGRD for each channel can also be used as timer counter clearing
registers. TGRC and TGRD can also be used as buffer registers.
• Selection of four counter input clocks for channels 0 and 1, and of six counter input clocks for
channels 2 and 3.
• The following operations can be set for each channel:
 Waveform output at compare match: Selection of 0, 1, or toggle output
 Counter clear operation: Counter clearing possible by compare match
 PWM mode: Any PWM output duty can be set
Maximum of 4-phase PWM output possible
• Buffer operation settable for each channel
 Automatic rewriting of output compare register possible
• Phase counting mode settable independently for each of channels 2, and 3
 Two-phase encoder pulse up/down-count possible
• An interrupt request for each channel
 For channels 0 and 1, compare match interrupts and overflow interrupts can be requested
independently
 For channels 2, and 3, compare match interrupts, overflow interrupts, and underflow
interrupts can be requested independently
Table 15.1 lists the functions of the TPU.
Rev. 3.00 Jan. 18, 2008 Page 511 of 1458
REJ09B0033-0300
Section 15
16-Bit Timer Pulse Unit (TPU)
Table 15.1 TPU Functions
Item
Channel 0
Channel 1
Channel 2
Channel 3
Count clock
Pφ/1
Pφ/4
Pφ/16
Pφ/64


Pφ/1
Pφ/4
Pφ/16
Pφ/64


Pφ/1
Pφ/4
Pφ/16
Pφ/64
TPU_TI2A
TPU_TI2B
Pφ/1
Pφ/4
Pφ/16
Pφ/64
TPU_TI3A
TPU_TI3B
General registers
TGR0A
TGR0B
TGR1A
TGR1B
TGR2A
TGR2B
TGR3A
TGR3B
General registers/
buffer registers
TGR0C
TGR0D
TGR1C
TGR1D
TGR2C
TGR2D
TGR3C
TGR3D
Output pins
TPU_TO0
TPU_TO1
TPU_TO2
TPU_TO3
Counter clear
function
TGR compare
match
TGR compare
match
TGR compare
match
TGR compare
match


5 sources
5 sources
6 sources
6 sources
•
Compare
match
•
Compare
match
•
Compare
match
•
Compare
match
•
Overflow
•
Overflow
•
Overflow
•
Overflow
•
Underflow
•
Underflow
Compare 0 output
match
1 output
output
Toggle
output
PWM mode
Phase counting
mode
Buffer operation
Interrupt sources
[Legend]
:
Possible
:
Not possible
Note: TPU_TI2B and TPU_TI3B are used as count clocks only in phase counting mode.
Rev. 3.00 Jan. 18, 2008 Page 512 of 1458
REJ09B0033-0300
Section 15
16-Bit Timer Pulse Unit (TPU)
Figure 15.1 shows a block diagram of the TPU.
Pφ
Divider
Pφ/1
Pφ/4
Pφ/16
Pφ/64
Clock
selection
Counter
up
Edge
selection
Output
control
TPU_TO0
Note 1
Channel 0
clear
Buffer
Comparator
TGRC
Selecter
TGRA
TGRB
TGRD
Channel 1
Edge
selection
selector
Clock
selection
Same as channel 0
TPU_TO1
Counter
up
Output
control
TPU_TO2
TPU_TI2A
TPU_TI2B
Phase
comparison
down
Note 1
clear
Channel 2
Buffer
TGRB
Comparator
TGRC
Selector
TGRA
TGRD
TPU_TI3A
TPU_TI3B
Channel 3
Figure 15.1
Same as channel 2
Note 1: Output disabled
Initial value
0, 1
Compare match
0, 1, toggle
TPU_TO3
Block Diagram of TPU
Rev. 3.00 Jan. 18, 2008 Page 513 of 1458
REJ09B0033-0300
Section 15
15.2
16-Bit Timer Pulse Unit (TPU)
Input/Output Pins
Table 15.2 summarizes the TPU related external pins.
Table 15.2 TPU Pin Configurations
Channel
Name
Pin Name
I/O
0
TPU compare
match output 0
TPU_TO0
Output TGR0A output compare output/PWM output
pin
1
TPU compare
match output 1
TPU_TO1
Output TGR1A output compare output/PWM output
pin
2
TPU compare
TPU_TO2
match output 2A
Output TGR2A output compare output/PWM output
pin
TPU clock input
2A
TPU_TI2A
Input
External clock channel 2A input pin /channel 2
counting mode A phase input
TPU clock input
2B
TPU_TI2B
Input
Channel 2 counting mode B phase input
3
Function
TPU compare
TPU_TO3
match output 3A
Output TGR3A output compare output/PWM output
pin
TPU clock input
3A
TPU_TI3A
Input
External clock channel 3A input pin /channel 3
counting mode A phase input
TPU clock input
3B
TPU_TI3B
Input
Channel 3 counting mode B phase input
Rev. 3.00 Jan. 18, 2008 Page 514 of 1458
REJ09B0033-0300
Section 15
15.3
16-Bit Timer Pulse Unit (TPU)
Register Descriptions
The TPU has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and states of these registers in each operating mode.
Channel 0:
•
•
•
•
•
•
•
•
•
•
Timer control register_0 (TCR_0)
Timer mode register_0 (TMDR_0)
Timer I/O control register_0 (TIOR_0)
Timer interrupt enable register_0 (TIER_0)
Timer status register_0 (TSR_0)
Timer counter_0 (TCNT_0)
Timer general register A_0 (TGRA_0)
Timer general register B_0 (TGRB_0)
Timer general register C_0 (TGRC_0)
Timer general register D_0 (TGRD_0)
Channel 1:
•
•
•
•
•
•
•
•
•
•
Timer control register_1 (TCR_1)
Timer mode register_1 (TMDR_1)
Timer I/O control register_1 (TIOR_1)
Timer interrupt enable register_1 (TIER_1)
Timer status register_1 (TSR_1)
Timer counter_1 (TCNT_1)
Timer general register A_1 (TGRA_1)
Timer general register B_1 (TGRB_1)
Timer general register C_1 (TGRC_1)
Timer general register D_1 (TGRD_1)
Channel 2:
•
•
•
•
•
Timer control register_2 (TCR_2)
Timer mode register_2 (TMDR_2)
Timer I/O control register_2 (TIOR_2)
Timer interrupt enable register_2 (TIER_2)
Timer status register_2 (TSR_2)
Rev. 3.00 Jan. 18, 2008 Page 515 of 1458
REJ09B0033-0300
Section 15
•
•
•
•
•
16-Bit Timer Pulse Unit (TPU)
Timer counter_2 (TCNT_2)
Timer general register A_2 (TGRA_2)
Timer general register B_2 (TGRB_2)
Timer general register C_2 (TGRC_2)
Timer general register D_2 (TGRD_2)
Channel 3:
•
•
•
•
•
•
•
•
•
•
•
Timer control register_3 (TCR_3)
Timer mode register_3 (TMDR_3)
Timer I/O control register_3 (TIOR_3)
Timer interrupt enable register_3 (TIER_3)
Timer status register_3 (TSR_3)
Timer counter_3 (TCNT_3)
Timer general register A_3 (TGRA_3)
Timer general register B_3 (TGRB_3)
Timer general register C_3 (TGRC_3)
Timer general register D_3 (TGRD_3)
Timer start register (TSTR)
15.3.1
Timer Control Registers (TCR)
The TCR registers are 16-bit registers that control the TCNT channels. The TPU has four TCR
registers, one for each of channels 0 to 3. The TCR registers are initialized to H'0000 by a reset,
but not initialized in standby mode, sleep mode, or module standby.
TCR register settings should be made only when TCNT operation is stopped.
Rev. 3.00 Jan. 18, 2008 Page 516 of 1458
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Section 15
Bit
Bit Name
15 to 8 
Initial
Value
R/W
Description
All 0
R
Reserved
16-Bit Timer Pulse Unit (TPU)
These bits are always read as 0 and cannot be modified.
7
CCLR2
0
R/W
Counter Clear 2, 1, and 0
6
CCLR1
0
R/W
These bits select the TCNT counter clearing source.
5
CCLR0
0
R/W
000: TCNT clearing disabled
001: TCNT cleared by TGRA compare match
010: TCNT cleared by TGRB compare match
011: Reserved (setting prohibited)
100: TCNT clearing disabled
101: TCNT cleared by TGRC compare match
110: TCNT cleared by TGRD compare match
111: Reserved (setting prohibited)
4
CKEG1
0
R/W
Clock Edge 1 and 0
3
CKEG0
0
R/W
These bits select the input clock edge. When the input clock
is counted using both edges, the input clock period is halved
(e.g. φ/4 both edges = φ/2 rising edge). If phase counting
mode is used this setting is ignored.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges*
[Legend] X: Don't care
Note: * If Pφ/1 is selected for the input clock, operation is
disabled.
2
TPSC2
0
R/W
Time Prescaler 2, 1, and 0
1
TPSC1
0
R/W
0
TPSC0
0
R/W
These bits select the TCNT counter clock. The clock source
can be selected independently for each channel. Table 15.3
shows the clock sources that can be set for each channel.
For more in formation on count clock selection, see table
15.4.
Rev. 3.00 Jan. 18, 2008 Page 517 of 1458
REJ09B0033-0300
Section 15
16-Bit Timer Pulse Unit (TPU)
Table 15.3 TPU Clock Sources
Internal Clock
Channel
Pφ/1
Pφ/4
Pφ/16
External Clock
Pφ/64
TPU_TI2A
TPU_TI3A
0
1
2
3
[Legend]
: Setting
Blank : No setting
Table 15.4 TPSC2 to TPSC0 (1)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
*
Reserved (setting prohibited)
1
1
*
(Initial value)
Table 15.4 TPSC2 to TPSC0 (2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
1
*
1
Internal clock: counts on Pφ/64
*
Reserved (setting prohibited)
Rev. 3.00 Jan. 18, 2008 Page 518 of 1458
REJ09B0033-0300
(Initial value)
Section 15
16-Bit Timer Pulse Unit (TPU)
Table 15.4 TPSC2 to TPSC0 (3)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
0
External clock: counts on TPU_TI2A pin input
1
Reserved (setting prohibited)
1
1
0
1
(Initial value)
*
Table 15.4 TPSC2 to TPSC0 (4)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
3
0
0
0
Internal clock: counts on Pφ/1
1
Internal clock: counts on Pφ/4
0
Internal clock: counts on Pφ/16
1
Internal clock: counts on Pφ/64
0
External clock: counts on TPU_TI3A pin input
1
Reserved (setting prohibited)
1
1
0
1
Note:
*
(Initial value)
*
Don't care
Rev. 3.00 Jan. 18, 2008 Page 519 of 1458
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Section 15
15.3.2
16-Bit Timer Pulse Unit (TPU)
Timer Mode Registers (TMDR)
The TMDR registers are 16-bit readable/writable registers that are used to set the operating mode
for each channel. The TPU has four TMDR registers, one for each channel. The TMDR registers
are initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or module
standby.
TMDR register settings should be made only when TCNT operation is stopped.
Bit
Bit Name
15 to 7 
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
6
BFWT
0
R/W
Buffer Write Timing
Specifies TGRA and TGRB update timing when TGRC and
TGRD are used as a compare match buffer. When TGRC
and TGRD are not used as a compare match buffer register,
this bit does not function.
0: TGRA and TGRB are rewritten at compare match of each
register.
1: TGRA and TGRB are rewritten in counter clearing.
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the normal way, or
TGRB and TGRD are to be used together for buffer
operation.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer operation*
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal way, or
TGRA and TGRC are to be used together for buffer
operation.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer operation
3

0
R
Reserved
This bit is always read as 0 and cannot be modified.
Rev. 3.00 Jan. 18, 2008 Page 520 of 1458
REJ09B0033-0300
Section 15
16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial
Value
R/W
Description
2
MD2
0
R/W
Modes 2 to 0
1
MD1
0
R/W
These bits are used to set the timer operating mode.
0
MD0
0
R/W
000: Normal operation
001: Reserved (setting prohibited)
010: PWM mode
011: Reserved (setting prohibited)
100: Phase counting mode 1
101: Phase counting mode 2
110: Phase counting mode 3
111: Phase counting mode 4
Note:
15.3.3
*
Operation when setting (BFWT, BFB, BFA) = (1, 1, 0) is the same as when setting
(BFWT, BFB, BFA) = (1, 0, 1). However, when the BFB bit is set to 1 (TGRB and TGRD
used together for buffer operation), the setting of (BFWT, BFB, BFA) = (1, 1, 1) should
be made. In this case, the value set in TGRA should also be set in TGRC because
TGRA and TGRC are also used together for buffer operation.
Timer I/O Control Registers (TIOR)
The TIOR registers are 16-bit registers that control the TPU_TO pin. The TPU has four TIOR
registers, one for each channel. The TIOR registers are initialized to H'0000 by a reset, but not
initialized in standby mode, sleep mode, or module standby.
TIOR register settings should be made only when TCNT operation is halted.
Care is required since TIOR is affected by the TMDR setting.
If the counting operation is halted, the initial value set by this register is output from the TPU_TO
pin.
Rev. 3.00 Jan. 18, 2008 Page 521 of 1458
REJ09B0033-0300
Section 15
Bit
16-Bit Timer Pulse Unit (TPU)
Bit Name
15 to 3 
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
2
IOA2
0
R/W
I/O Control A2 to A0
1
IOA1
0
R/W
0
IOA0
0
R/W
Bits IOA3 to IOA0 specify the functions of TGRA and the
TPU_TO pin. For details, see table 15.5.
Table 15.5 IOA2 to IOA0
Bit 2
Bit 1
Bit 0
Channels IOA2
IOA1
IOA0
Description
0 to 3
0
0
Always 0 output (Initial value)
1
Initial output is 0
output for
TPU_TO pin
0
1
0
1
1
0
1
Always 1 output
1
Initial output is 1
output for
TPU_TO pin
1
Note:
*
This setting is invalid in PWM mode.
Rev. 3.00 Jan. 18, 2008 Page 522 of 1458
REJ09B0033-0300
1 output at TGRA compare match
Toggle output TGRA at compare match*
0
0
0 output at TGRA compare match*
0 output at TGRA compare match
1 output at TGRA compare match*
Toggle output at TGRA compare match*
Section 15
15.3.4
16-Bit Timer Pulse Unit (TPU)
Timer Interrupt Enable Registers (TIER)
The TIER registers are 16-bit registers that control enabling or disabling of interrupt requests for
each channel. The TPU has four TIER registers, one for each channel. The TIER registers are
initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode or module
standby.
Bit
Bit Name
15 to 6 
Initial
Value
R/W
Description
0
R
Reserved
These bits are always read as 0 and cannot be modified.
5
TC1EU
0
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests by the TCFU bit when
the TCFU bit in TSR is set to 1 in phase counting mode of
channels 2, and 3 (TCNT underflow).
In channels 0 and 1, bit 5 is reserved. It is always read as 0
and cannot be modified.
0: Interrupt requests by TCFU disabled
1: Interrupt requests by TCFU enabled
4
TC1EV
0
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests by the TCFV bit when
the TCFV bit in TSR is set to 1 (TCNT overflow).
0: Interrupt requests by TCFV disabled
1: Interrupt requests by TCFV enabled
3
TG1ED
0
R/W
TGR Interrupt Enable D
Enables or disables interrupt requests by the TGFD bit when
the TGFD bit in TSR is set to (TCNT and TGRD compare
match).
0: Interrupt requests by TGFD disabled
1: Interrupt requests by TGFD enabled
2
TG1EC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests by the TGFC bit when
the TGFC bit in TSR is set to 1 (TCNT and TGRC compare
match).
0: Interrupt requests by TGFC disabled
1: Interrupt requests by TGFC enabled
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Section 15
16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial
Value
R/W
Description
1
TG1EB
0
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests by the TGFB bit when
the TGFB bit in TSR is set to 1 (TCNT and TGRB compare
match).
0: Interrupt requests by TGFB disabled
1: Interrupt requests by TGFB enabled
0
TG1EA
0
R/W
TGR Interrupt Enable A
Enables or disables interrupt requests by the TGFA bit when
the TGFA bit in TSR is set to 1 (TCNT and TGRA compare
match).
0: Interrupt requests by TGFA disabled
1: Interrupt requests by TGFA enabled
15.3.5
Timer Status Registers (TSR)
The TSR registers are 16-bit registers that indicate the status of each channel. The TPU has four
TSR registers, one for each channel. The TSR registers are initialized to H'0000 by a reset, but not
initialized in standby mode, sleep mode or module standby mode.
Bit
Bit Name
15 to 8 
Initial
Value R/W
Description
All 0
Reserved
R
These bits are always read as 0 and cannot be modified.
7
TCFD
0
R
Count Direction Flag
Status flag that shows the direction in which TCNT counts in
phase counting mode of channels 2, and 3.
In channels 0 and 1, bit 7 is reserved. It is always read as 0
and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6

0
R
Reserved
This bit is always read as 0 and cannot be modified.
Rev. 3.00 Jan. 18, 2008 Page 524 of 1458
REJ09B0033-0300
Section 15
Bit
Bit Name
Initial
Value R/W
5
TCFU
0
16-Bit Timer Pulse Unit (TPU)
Description
R/(W)* Underflow Flag
Status flag that indicates that TCNT underflow has occurred
when channels 2, and 3 are set to phase counting mode.
In channels 0 and 1, bit 5 is reserved. It is always read as 0
and cannot be modified.
[Clearing condition] (Initial value)
When 0 is written to TCFU after reading TCFU = 1
[Setting condition]
When the TCNT value underflows (changes from H'0000 to
H'FFFF)
4
TCFV
0
R/(W)* Overflow Flag
Status flag that indicates that TCNT overflow has occurred.
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
[Setting condition]
When the TCNT value overflows (changes from H'FFFF to
H'0000)
3
TGFD
0
R/(W)* Compare Flag D
Status flag that indicates the occurrence of TGRD compare
match.
[Clearing conditions]
When 0 is written to TGFD after reading TGFD = 1
[Setting conditions]
When TCNT = TGRD
2
TGFC
0
R/(W)* Compare Flag C
Status flag that indicates the occurrence of TGRC compare
match.
[Clearing conditions]
When 0 is written to TGFC after reading TGFC = 1
[Setting conditions]
When TCNT = TGRC
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Section 15
16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial
Value R/W
1
TGFB
0
Description
R/(W)* Compare Flag B
Status flag that indicates the occurrence of TGRB compare
match.
[Clearing conditions]
When 0 is written to TGFB after reading TGFB = 1
[Setting conditions]
When TCNT = TGRB
0
TGFA
0
R/(W)* Output Compare Flag A
Status flag that indicates the occurrence of TGRA compare
match.
[Clearing conditions]
When 0 is written to TGFA after reading TGFA = 1
[Setting conditions]
When TCNT = TGRA
Note:
15.3.6
*
Only 0 can be written, to clear the flag.
Timer Counters (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has four TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset.
The TCNT counters are not initialized in standby mode, sleep mode, or module standby.
15.3.7
Timer General Registers (TGR)
The TGR registers are 16-bit registers. The TPU has 16 TGR registers, four each for channels 0
and 3. TGRC and TGRD can also be designated for operation as buffer registers*. The TGR
registers are initialized to H'FFFF by a reset. These registers are not initialized in standby mode,
sleep mode, or module standby.
Note: * TGR buffer register combinations are TGRA—TGRC and TGRB—TGRD.
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Section 15
15.3.8
16-Bit Timer Pulse Unit (TPU)
Timer Start Register (TSTR)
TSTR is a 16-bit readable/writable register that selects TCNT operation/stoppage for channels 0 to
3. TSTR is initialized to H'0000 by a reset, but not initialized in standby mode, sleep mode, or
module standby.
Bit
Bit Name
15 to 4 
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0 and cannot be modified.
3
CST3
0
R/W
Counter Start 3 to 0
2
CST2
0
R/W
These bits select operation or stoppage for TCNT.
1
CST1
0
R/W
0: TCNTn count operation is stopped)
0
CST0
0
R/W
1: TCNTn performs count operation
n=3 to 0
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Section 15
16-Bit Timer Pulse Unit (TPU)
15.4
Operation
15.4.1
Overview
Operation in each mode is outlined below.
(1)
Normal Operation
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, synchronous counting, and external event counting.
(2)
Buffer Operation
When a compare match occurs, the value in the buffer register for the relevant channel is
transferred to TGR. For update timing from a buffer register, rewriting on compare match
occurrence or on counter clearing can be selected.
(3)
PWM Mode
In this mode, a PWM waveform is output. The output level can be set by means of TIOR. A PWM
waveform with a duty of between 0% and 100% can be output, according to the setting of each
TGR register.
(4)
Phase Counting Mode
In this mode, TCNT is incremented or decremented by detecting the phases of two clocks input
from the external clock input pins (TPU_TI2A and TPU_TI2B, or TPU_TI3A and TPU_TI3B) in
channels 2, and 3. When phase counting mode is set, the corresponding TI pin functions as the
clock pin, and TCNT performs up/down-counting.
This can be used for two-phase encoder pulse input.
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Section 15
15.4.2
(1)
16-Bit Timer Pulse Unit (TPU)
Basic Functions
Counter Operation
When one of bits CST0 to CST3 is set to 1 in TSTR, the TCNT counter for the corresponding
channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on.
(a)
Example of count operation setting procedure
Figure 15.2 shows an example of the count operation setting procedure.
[1] Select the counter clock
with bits TPSC2 to TPSC0
in TCR. At the same time
select the input clock edge
with bits CKEG1 and
CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Select counter clearing source
[2]
[2] For periodic counter
operation, select the TGRA
to be used as the TCNT
clearing source with bits
CCLR2 to CCLR0 in TCR.
Select output compare register
[3]
[3] Designate the output compare
register by means of TIOR.
Set period
[4]
Set external pin function
[5]
Periodic counter
Free-running counter
[4] Set the periodic counter cycle
in the TGRA.
Set external pin function
[5]
[5] Set the external pin function
in pin function controller (PFC).
Start count
<Periodic counter>
Figure 15.2
[6]
Start count
<Free-running counter>
[6]
[6]
Set the CST bit in TSTR to 1
to start the counter operation.
Example of Counter Operation Setting Procedure
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Section 15
(b)
16-Bit Timer Pulse Unit (TPU)
Free-running count operation and periodic count operation
Immediately after a reset, the TPU's TCNT counters are all designated as free-running counters.
When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts up-count
operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV
bit in TSR is set to 1. After overflow, TCNT starts counting up again from H'0000.
Figure 15.3 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 15.3
Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the relevant
channel performs periodic count operation. The TGR register for setting the period is designated
as an output compare register, and counter clearing by compare match is selected by means of bits
CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts up-count operation as
a periodic counter when the corresponding bit in TSTR is set to 1. When the count value matches
the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared to H'0000.
After a compare match, TCNT starts counting up again from H'0000.
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Section 15
16-Bit Timer Pulse Unit (TPU)
Figure 15.4 illustrates periodic counter operation.
Counter cleared by TGRA
compare match
TCNT value
TGR
H'0000
Time
CST bit
Flag cleared by software
TGFA
Figure 15.4
Periodic Counter Operation
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Section 15
(2)
16-Bit Timer Pulse Unit (TPU)
Waveform Output by Compare Match
The TPU can perform 0, 1, or toggle output from the corresponding output pin (TPU_TO pin)
using TGRA compare match.
(a)
Example of setting procedure for waveform output by compare match
Figure 15.5 shows an example of the setting procedure for waveform output by compare match.
Output selection
Select waveform output mode
[1]
Set output timing
[2]
Set external pin function
[3]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TPU_TO pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGRA.
[3] Set the external pin function in pin function
controller (PFC).
[4] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[4]
<Waveform output>
Figure 15.5
Example of Setting Procedure for Waveform Output by Compare Match
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Section 15
(b)
16-Bit Timer Pulse Unit (TPU)
Examples of waveform output operation
Figure 15.6 shows an example of 0 output/1 output.
In this example TCNT has been designated as a free-running counter, and settings have been made
so that 1 is output by compare match A, and 0 is output by compare match B. When the set level
and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
TGRA
H'0000
Time
No change
No change
No change
No change
TPU_TO pin (1 output)
TPU_TO pin (0 output)
Figure 15.6
Example of 0 Output/1 Output Operation
Figure 15.7 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing performed
by compare match B), and settings have been made so that output is toggled by compare match A.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
H'0000
TPU_TO pin
Figure 15.7
Time
Toggle output
Example of Toggle Output Operation
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Section 15
15.4.3
16-Bit Timer Pulse Unit (TPU)
Buffer Operation
Buffer operation, enables TGRC and TGRD to be used as buffer registers.
Table 15.6 shows the register combinations used in buffer operation.
Table 15.6 Register Combinations in Buffer Operation
Timer General Register
Buffer Register
TGRA
TGRC
TGRB
TGRD
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. For update timing from a buffer register, rewriting on
compare match occurrence or on counter cleaning can be selected.
This operation is illustrated in figure 15.8.
Counter cleaning signal
Compare match signal
BFWT bit
Timer general
register
Buffer register
Figure 15.8
Compare Match Buffer Operation
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Comparator
TCNT
Section 15
(1)
16-Bit Timer Pulse Unit (TPU)
Example of Buffer Operation Setting Procedure
Figure 15.9 shows an example of the buffer operation setting procedure.
[1] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Buffer operation
Set buffer operation
Set rewriting timing
[1]
[2] Set rewriting timing from the buffer register with
bit BFWT in TMDR.
[2]
[3] Set the external pin function in pin function
controller (PFC).
[4] Set the CST bit in TSTR to 1 to start the count
operation.
Set external pin function
[3]
Start count
[4]
<Buffer operation>
Figure 15.9
(2)
Example of Buffer Operation Setting Procedure
Example of Buffer Operation
Figure 15.10 shows an operation example in which PWM mode has been designated for channel 0,
and buffer operation has been designated for TGRA and TGRC. The settings used in this example
are TCNT clearing by compare match B, 1 output at compare match A (TPU_TO pin), and 0
output at counter clearing. Rewriting timing from the buffer register is set at counter clearing.
As buffer operation has been set, when compare match A occurs the output changes. When
counter clearing occurs by TGRB, the output changes and the value in buffer register TGRC is
simultaneously transferred to timer general register TGRA. This operation is repeated each time
compare match A occurs.
For details of PWM modes, see section 15.4.4, PWM Modes.
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Section 15
16-Bit Timer Pulse Unit (TPU)
TCNT value
N (TGRB+1)
TGRB
TGRA
N (B)
N (A)
Time
H'0000
TGRC
N (B)
N (A)
TGRA
N (A)
N (TGRB+1)
N (B)
N (TGRB+1)
TPU_TO pin
Figure 15.10
15.4.4
Example of Buffer Operation
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, or 1, output can be selected
as the output level in response to compare match of each TGRA.
Designating TGRB compare match as the counter clearing source enables the period to be set in
that register. All channels can be designated for PWM mode independently.
PWM output is generated from the TPU_TO pin using TGRB as the period register and TGRA as
duty registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a period register compare match, the output value of each pin is the initial
value set in TIOR. Set TIOR so that the initial output and an output value by compare match are
different. If the same levels or toggle outputs are selected, operation is disabled.
Conditions of duty 0% and 100% are shown below.
• Duty
0%: The set value of the duty register (TGRA) is TGRB + 1 for the period
register(TGRB).
• Duty 100%: The set value of the duty register (TGRA) is 0.
In PWM mode 1, a maximum 4-phase PWM output is possible.
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Section 15
(1)
16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure
Figure 15.11 shows an example of the PWM mode setting procedure.
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
Select counter clearing source
[2]
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGRB to be used as the TCNT clearing source.
Select waveform output level
[3]
[3] Use TIOR to select the initial value and
output value.
Set period
[4]
[4] Set the period in TGRB, and set the duty in
TGRA.
Set PWM mode
[5]
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set external pin function
[6]
[6] Set the external pin function in pin function
controller (PFC).
Start count
[7]
[7] Set the CST bit in TSTR to 1 to start the count
operation.
PWM mode
<PWM mode>
Figure 15.11
Example of PWM Mode Setting Procedure
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Section 15
(2)
16-Bit Timer Pulse Unit (TPU)
Examples of PWM Mode Operation
Figure 15.12 shows an example of PWM mode operation.
In this example, TGRB compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRA output value.
In this case, the value set in TGRB is used as the period, and the value set in TGRA as the duty.
TCNT value
Counter cleared by
TGRB compare match
TGRB
TGRA
H'0000
Time
TPU_TO pin
Figure 15.12
Example of PWM Mode Operation (1)
Figure 15.13 shows examples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT
2
1
0
2
0
TGRA=0
TGRA=1
TGRA=2
TGRA=3
↑ Rewrite timing for TGRA
Period: TGRB=2
Figure 15.13
Examples of PWM Mode Operation (2)
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Section 15
15.4.5
16-Bit Timer Pulse Unit (TPU)
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 2, and 3.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and compare match and interrupt functions can be used.
The previous set value (initial output value set before the timer was started in phase counting
mode) is output from the TPU_TO pin in TIOR.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 15.7 shows the correspondence between external clock pins and channels.
Table 15.7 Phase Counting Mode Clock Input Pins
External Clock Pins
Channels
A-Phase
B-Phase
When channel 2 is set to phase counting mode
TPU_TI2A
TPU_TI2B
When channel 3 is set to phase counting mode
TPU_TI3A
TPU_TI3B
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Section 15
(1)
16-Bit Timer Pulse Unit (TPU)
Example of Phase Counting Mode Setting Procedure
Figure 15.14 shows an example of the phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
Phase counting mode
Select phase counting mode
[1]
[2] Set the external pin function in pin function
controller (PFC).
Set external pin function
[2]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[3]
<Phase counting mode>
Figure 15.14
Example of Phase Counting Mode Setting Procedure
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Section 15
(2)
16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation
In phase counting mode, TCNT counts up or down according to the phase difference between two
external clocks. There are four modes, according to the count conditions.
(a)
Phase counting mode 1
Figure 15.15 shows an example of phase counting mode 1 operation, and table 15.8 summarizes
the TCNT up/down-count conditions.
TPU_TI2A (channel 2)
TPU_TI3A (channel 3)
TPU_TI2B (channels 2)
TPU_TI3B (channels 3)
TCNT value
Up-count
Down-count
Time
Figure 15.15
Example of Phase Counting Mode 1 Operation
Table 15.8 Up/Down-Count Conditions in Phase Counting Mode 1
TPU_TI2A (Channel 2)
TPU_TI3A (Channel 3)
TPU_TI2B (Channel 2)
TPU_TI3B (Channel 3)
Operation
Up-count
High level
Low level
Low level
High level
Down-count
High level
Low level
High level
Low level
[Legend]
: Rising edge
: Falling edge
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Section 15
(b)
16-Bit Timer Pulse Unit (TPU)
Phase counting mode 2
Figure 15.16 shows an example of phase counting mode 2 operation, and table 15.9 summarizes
the TCNT up/down-count conditions.
TPU_TI2A (Channel 2)
TPU_TI3A (Channel 3)
TPU_TI2B (Channel 2)
TPU_TI3B (Channel 3)
TCNT value
Up-count
Down-count
Time
Figure 15.16
Example of Phase Counting Mode 2 Operation
Table 15.9 Up/Down-Count Conditions in Phase Counting Mode 2
TPU_TI2A (Channel 2)
TPU_TI3A (Channel 3)
TPU_TI2B (Channel 2)
TPU_TI3B (Channel 3)
Operation
Don't care
High level
Low level
Low level
High level
Up-count
Don't care
High level
Low level
High level
Low level
[Legend]
: Rising edge
: Falling edge
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Down-count
Section 15
(c)
16-Bit Timer Pulse Unit (TPU)
Phase counting mode 3
Figure 15.17 shows an example of phase counting mode 3 operation, and table 15.10 summarizes
the TCNT up/down-count conditions.
TPU_TI2A (channel 2)
TPU_TI3A (channel 3)
TPU_TI2B (channel 2)
TPU_TI3B (channel 3)
TCNT value
Down-count
Up-count
Time
Figure 15.17
Example of Phase Counting Mode 3 Operation
Table 15.10 Up/Down-Count Conditions in Phase Counting Mode 3
TPU_TI2A (Channel 2)
TPU_TI3A (Channel 3)
TPU_TI2B (Channel 2)
TPU_TI3B (Channel 3)
Operation
Don't care
High level
Low level
Low level
High level
Up-count
Down-count
High level
Don't care
Low level
High level
Low level
[Legend]
: Rising edge
: Falling edge
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Section 15
(d)
16-Bit Timer Pulse Unit (TPU)
Phase counting mode 4
Figure 15.18 shows an example of phase counting mode 4 operation, and table 15.11 summarizes
the TCNT up/down-count conditions.
TPU_TI2A (channel 2)
TPU_TI3A (channel 3)
TPU_TI2B (channel 2)
TPU_TI3B (channel 3)
TCNT value
Up-count
Down-count
Time
Figure 15.18
Example of Phase Counting Mode 4 Operation
Table 15.11 Up/Down-Count Conditions in Phase Counting Mode 4
TPU_TI2A (Channel 2)
TPU_TI3A (Channel 3)
TPU_TI2B (Channel 2)
TPU_TI3B (Channel 3)
Operation
Up-count
High level
Low level
Low level
Don't care
High level
Down-count
High level
Low level
High level
Low level
[Legend]
: Rising edge
: Falling edge
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Don't care
Section 15
15.5
16-Bit Timer Pulse Unit (TPU)
Usage Notes
Note that the kinds of operation and contention described below can occur during TPU operation.
(1)
Input Clock Restrictions
The input clock pulse width must be at least 2 states in the case of single-edge detection, and at
least 3 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 2 states, and the pulse width must be at least 3 states. Figure 15.19 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
differdifference Overlap ence
Pulse width
Pulse width
TPU_TCLKA
(TPU_TCLKC)
TPU_TCLKB
(TPU_TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 2 states or more
: 3 states or more
Pulse width
Figure 15.19
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 15
16-Bit Timer Pulse Unit (TPU)
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Section 16 Compare Match Timer (CMT)
Section 16 Compare Match Timer (CMT)
This LSI includes a 32-bit compare match timer (CMT) of five channels (channel 0 to channel 4).
16.1
Features
• 16 bits/32 bits can be selected.
• Each channel is provided with an auto-reload up counter.
• All channels are provided with 32-bit constant registers and 32-bit up counters that can be
written or read at any time.
• Allows selection among three counter input clocks for channel 0 to channel 4:
 Peripheral clock (Pφ): 1/8, 1/32, and 1/128
• One-shot operation and free-running operation are selectable.
• Allows selection of compare match or overflow for the interrupt source.
• Generate a DMA transfer request when compare match or overflow occurs in channels 0 to 4.
• Module standby mode can be set.
TIMCMT1A_000020011000
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Section 16 Compare Match Timer (CMT)
Figure 16.1 shows a block diagram of the CMT.
CMT
CMSTR
CH0
Pre-scaller
CMCNT_0
CMCOR_0
CMCSR_0
Interrupt control
Internal interrupt
DMA transfer
CH1
Pre-scaller
CMCNT_1
CMCOR_1
CMCSR_1
Interrupt control
Internal interrupt
DMA transfer
CH2
Pre-scaller
CMCNT_2
CMCOR_2
CMCSR_2
Interrupt control
Internal interrupt
DMA transfer
CH3
Pre-scaller
CMCNT_3
CMCOR_3
CMCSR_3
Interrupt control
Internal interrupt
DMA transfer
CH4
Pre-scaller
CMCNT_4
CMCOR_4
CMCSR_4
Interrupt control
[Legend]
CMSTR: Compare match timer start register
CMCSR: Compare match timer control/status register
Internal interrupt
DMA transfer
CMCNT: Compare match timer counter
CMCOR: Compare match timer constant register
Figure 16.1 Block Diagram of CMT
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Peripheral bus
Pφ
Section 16 Compare Match Timer (CMT)
16.2
Register Descriptions
The CMT has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and states of these registers in each operating mode. Notation for the CMT registers
takes the form XXX_N, where XXX including the register name and N indicating the channel
number. For example, CMCSR_0 denotes the CMCSR for channel 0.
(1) Common
• Compare match timer start register (CMSTR)
(2) Channel 0
• Compare match timer control/status register_0 (CMCSR_0)
• Compare match timer counter_0 (CMCNT_0)
• Compare match timer constant register_0 (CMCOR_0)
(3) Channel 1
• Compare match timer control/status register_1 (CMCSR_1)
• Compare match timer counter_1 (CMCNT_1)
• Compare match timer constant register_1 (CMCOR_1)
(4) Channel 2
• Compare match timer control/status register_2 (CMCSR_2)
• Compare match timer counter_2 (CMCNT_2)
• Compare match timer constant register_2 (CMCOR_2)
(5) Channel 3
• Compare match timer control/status register_3 (CMCSR_3)
• Compare match timer counter_3 (CMCNT_3)
• Compare match timer constant register_3 (CMCOR_3)
(6) Channel 4
• Compare match timer control/status register_4 (CMCSR_4)
• Compare match timer counter_4 (CMCNT_4)
• Compare match timer constant register_4 (CMCOR_4)
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Section 16 Compare Match Timer (CMT)
16.2.1
Compare Match Timer Start Register (CMSTR)
CMSTR is a 16-bit register that selects whether the compare match timer counter (CMCNT) is
operated or halted.
Bit
Bit Name
15 to 5 
Initial
Value
R/W
Description
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
4
STR4
0
R/W
Count Start 4 to 0
3
STR3
0
R/W
2
STR2
0
R/W
Selects whether to operate or halt the compare match
timer counter for each channel (CMCNT_4 to CMCNT_0).
1
STR1
0
R/W
0: CMCNTn count operation halted
0
STR0
0
R/W
1: CMCNTn count operation
n: 4 to 0 (corresponds to each channel)
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Section 16 Compare Match Timer (CMT)
16.2.2
Compare Match Timer Control/Status Register (CMCSR)
CMCSR is a 16-bit register that indicates the occurrence of compare matches, enables interrupts
and DMA transfer request, and sets the counter input clocks.
Do not change bits other than bits CMF and OVF during the compare match timer counter
(CMCNT) operation.
Bit
15
Initial
Bit Name Value
CMF
0
R/W
Description
1
R/(W)* Compare Match Flag
This flag indicates whether or not values of the compare
match timer counter (CMCNT) and compare match timer
constant register (CMCOR) have matched.
Software cannot write 1 to the bit. When one-shot is
selected for the counter operation, counting resumes by
clearing this bit.
0: CMCNT and CMCOR values have not matched
[Clearing condition]
•
Write 0 to CMF after reading CMF=1
1: CMCNT and CMCOR values have matched
14
OVF
0
R/(W)*1 Overflow Flag
This flag indicates whether or not the compare match
timer counter (CMCNT) has overflowed and been cleared
to 0. Software cannot write 1 to this bit.
0: CMCNT has not overflowed
[Clearing condition]
•
Write 0 to OVF after reading OVF=1
1: CMCNT has overflowed
13 to 10 
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 551 of 1458
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Section 16 Compare Match Timer (CMT)
Bit
Initial
Bit Name Value
R/W
Description
9
CMS
R/W
Compare Match Timer Counter Size
0
Selects whether the compare match timer counter
(CMCNT) is used as a 16-bit counter or a 32-bit counter.
This setting becomes the valid size for the compare
match timer constant register (CMCOR).
0: Operates as a 32-bit counter
1: Operates as a 16-bit counter
8
CMM
0
R/W
Compare Match Mode
Selects one-shot operation or free-running operation of
the counter.
0: One-shot operation
1: Free-running operation
7, 6
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
5
CMR1
0
R/W
Compare Match Request 1, 0
4
CMR0
0
R/W
Selects enable or disable for a DMA transfer request or
internal interrupt request in a compare match.
00: Disables a DMA transfer request and internal
interrupt request
01: Enables DMA transfer request
10: Enables an internal interrupt request
11: Setting prohibited
3
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 3.00 Jan. 18, 2008 Page 552 of 1458
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Section 16 Compare Match Timer (CMT)
Bit
Initial
Bit Name Value
R/W
Description
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select the clock input to CMCNT. When the
STRn (n: 4 to 0) bit in CMSTR is set to 1, CMCNT begins
incrementing with the clock selected by these bits.
000: Pφ/8
001: Pφ/32
010: Pφ/128
011: Setting prohibited
100: Setting prohibited
101: Setting prohibited
110: Setting prohibited
111: Setting prohibited
Note:
16.2.3
*
Only 0 can be written to clear the flag.
Compare Match Timer Counter (CMCNT)
CMCNT is a 32-bit register that is used as an up-counter.
A counter operation is set by the compare match timer control/status register (CMCSR).
Therefore, set CMCSR first, before starting a channel operation corresponding to the compare
match timer start register (CMSTR). When the 16-bit counter operation is selected by the CMS
bit, bits 15 to 0 of this register become valid. When the register should be written to, write the data
that is added H'0000 to the upper half in a 32-bit operation. The contents of this register are
initialized to H'00000000.
16.2.4
Compare Match Timer Constant Register (CMCOR)
CMCOR is a 32-bit register that sets the compare match period with CMCNT for each channel.
When the 16-bit counter operation is selected by the CMS bit in CMCSR, bits 15 to 0 of this
register become valid. When the register should be written to, write the data that is added H'0000
to the upper half in a 32-bit operation.
An overflow is detected when CMCNT is cleared to 0 and this register is H'FFFFFFFF. The
contents of this register are initialized to H'FFFFFFFF.
Rev. 3.00 Jan. 18, 2008 Page 553 of 1458
REJ09B0033-0300
Section 16 Compare Match Timer (CMT)
16.3
Operation
16.3.1
Counter Operation
The CMT starts the operation of the counter by writing a 1 to the STRn bit in CMSTR of a
channel that has been selected for operation. Complete all of the settings before starting the
operation. Do not change the register settings other than by clearing flag bits.
The counter operates in one of two ways.
• One-Shot Operation
One-shot operation is selected by setting the CMM bit in CMCSR to 0. When the value in
CMCNT matches the value in CMCOR, the value in CMCNT is cleared to H'00000000 and
the CMF bit in CMCSR is set to 1. Counting by CMCNT stops after it has been cleared.
To detect an overflow interrupt, set the value in CMCOR to H'FFFFFFFF. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and bits CMF and
OVF in CMCSR are set to 1.
Value in
CMCNT
CMCOR
H'00000000
Time
CMF = 1
OVF = 1 (When an overflow is detected)
Figure 16.2 Counter Operation (One-Shot Operation)
Rev. 3.00 Jan. 18, 2008 Page 554 of 1458
REJ09B0033-0300
Section 16 Compare Match Timer (CMT)
• Free-Running Operation
Free-running operation is selected by setting the CMM bit in CMCSR to 1. When the value in
CMCNT matches the value in CMCOR, CMCNT is cleared to H'00000000 and the CMF bit in
CMCSR is set to 1. CMCNT resumes counting-up after it has been cleared.
To detect an overflow interrupt, set CMCOR to H'FFFFFFFF. When the values in CMCNT
and CMCOR match, CMCNT is cleared to H'00000000 and bits CMF and OVF in CMCSR
are set to 1.
Value in
CMCNT
CMCOR
H'00000000
Time
CMF=1
OVF=1 (When an overflow is detected)
Figure 16.3 Counter Operation (Free-Running Operation)
16.3.2
Counter Size
In this module, the size of the counter is selectable as either 16 or 32 bits. This is selected by the
CMS bit in CMCSR.
When the 16-bit size is selected, use a 32-bit value which has H'0000 as its upper half to set
CMCOR.
To detect an overflow interrupt, the value must be set to H'0000FFFF.
Rev. 3.00 Jan. 18, 2008 Page 555 of 1458
REJ09B0033-0300
Section 16 Compare Match Timer (CMT)
16.3.3
Timing for Counting by CMCNT
In this module, the clock for the counter can be selected from among the following:
•
For channels 0 to 4:
 Peripheral clock (Pφ): 1/8, 1/32, or 1/128
The clock for the counter is selected by bits CKS2 to CKS0 in CMCSR. CMCNT is incremented
at the rising edge of the selected clock.
16.3.4
DMA Transfer Requests and Internal Interrupt Requests to CPU
The setting of bits CMR1 and CMR0 in CMCSR selects the sending of a request for a DMA
transfer or for an internal interrupt to the CPU at a compare match.
A DMA transfer request has different specifications according to the CMT channel as described
below.
1. For channels 0 and 1, a single DMA transfer request is output at a compare match.
2. For channels 2 to 4, a DMA transfer request continues until the amount of data transferred has
reached the value set in the DMAC, and the output of the request then automatically stops.
To clear the interrupt request, the CMF bit should be set to 0. Set the CMF bit to 0 in the handling
routine for the CMT interrupt.
Rev. 3.00 Jan. 18, 2008 Page 556 of 1458
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Section 16 Compare Match Timer (CMT)
16.3.5
Compare Match Flag Set Timing (All Channels)
The CMF bit in CMCSR is set to 1 by the compare match signal generated when CMCOR and
CMCNT match. The compare match signal is generated upon the final state of the match (timing
at which the CMCNT value is updated to H'0000). Consequently, after CMCOR and CMCNT
match, a compare match signal will not be generated until a CMCNT counter clock is input.
Figure 16.4 shows the set timing of the CMF bit.
Peripheral operating
clock (Pφ)
N+1
clock
Counter clock
CMCNT
N
CMCOR
N
0
Compare match signal
and interrupt signal
Figure 16.4 CMF Set Timing
Rev. 3.00 Jan. 18, 2008 Page 557 of 1458
REJ09B0033-0300
Section 16 Compare Match Timer (CMT)
Rev. 3.00 Jan. 18, 2008 Page 558 of 1458
REJ09B0033-0300
Section 17 Realtime Clock (RTC)
Section 17 Realtime Clock (RTC)
This LSI has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator.
17.1
Features
• Clock and calendar functions (BCD format): Seconds, minutes, hours, date, day of the week,
month, and year
• 1-Hz to 64-Hz timer (binary format)
64-Hz counter indicates the state of the RTC divider circuit between 64 Hz and 1 Hz
• Start/stop function
• 30-second adjust function
• Alarm interrupt: Frame comparison of seconds, minutes, hours, date, day of the week, month,
and year can be used as conditions for the alarm interrupt
• Periodic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4
second, 1/2 second, 1 second, or 2 seconds
• Carry interrupt: a carry interrupt indicates when a carry occurs during a counter read
• Automatic leap year adjustment
RTCS320B_000020020900
Rev. 3.00 Jan. 18, 2008 Page 559 of 1458
REJ09B0033-0300
Section 17 Realtime Clock (RTC)
Figure 17.1 shows the block diagram of RTC.
RTCCLK (16kHz)
Externally
connected
circuit
EXTAL_RTC
32.768kHz
Oscillator
circuit
Count
128Hz
Prescaler
R64CNT
RSECCNT
RSECAR
RMINCNT
RMINAR
RHRCNT
RHRAR
RDAYCNT
RDAYAR
RWKCNT
RWKAR
RMONCNT
RMONAR
RYRCNT
RYRAR
RTC operation
control circuit
RCR1
RCR2
Bus interface
Peripheral module internal bus
XTAL_RTC
Interrupt
control circuit
RCR3
ATI
PRI
CU
[Legend]
RSECCNT: Second counter (8 bits)
RMINCNT: Minute counter (8 bits)
RHRCNT: Hour counter (8 bits)
RWKCNT: Day of week counter (8 bits)
RDAYCNT: Date counter
RMONCNT: Month counter (8 bits)
RYRCNT: Year counter (16 bits)
R64CNT: 64-Hz counter (8 bits)
RCR1:
RTC control register 1 (8 bits)
RSECAR: Second alarm register (8 bits)
RMINAR: Minute alarm registger (8 bits)
RHRAR: Hour alarm register (8 bits)
RWKAR: Day of week alarm register (8 bits)
RDAYAR: Date alarm register (8 bits)
RMONAR: Month alarm register (8 bits)
RYRAR: Year alarm register (16 bits)
RCR2:
RTC control register 2 (8 bits)
RCR3:
RTC control register 3
Figure 17.1 RTC Block Diagram
Rev. 3.00 Jan. 18, 2008 Page 560 of 1458
REJ09B0033-0300
Interrupt
signals
Section 17 Realtime Clock (RTC)
17.2
Input/Output Pin
Table 17.1 shows the RTC pin configuration.
Table 17.1 Pin Configuration
Name
Abbreviation
I/O
Description
RTC external clock
EXTAL_RTC
Input
Connects crystal resonator for RTC.
Also used to input external clock for
RTC.
RTC crystal
XTAL_RTC
Output Connects crystal resonator for RTC.
RTC power supply
VCC_RTC

Power-supply pin for RTC (1.5 V)*
RTC GND
VSS_RTC

GND pin for RTC*
RTC power supply
VCCQ_RTC
—
Power-supply pin for RTC (3.3 V)*
Note:
*
Power-supply pins for RTC should be power supplied even when the RTC is not used.
Rev. 3.00 Jan. 18, 2008 Page 561 of 1458
REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.3
Register Descriptions
The RTC has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and access size of these registers.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
64-Hz counter (R64CNT)
Second counter (RSECCNT)
Minute counter (RMINCNT)
Hour counter (RHRCNT)
Day of week counter (RWKCNT)
Date counter (RDAYCNT)
Month counter (RMONCNT)
Year counter (RYRCNT)
Second alarm register (RSECAR)
Minute alarm register (RMINAR)
Hour alarm register (RHRAR)
Day of week alarm register (RWKAR)
Date alarm register (RDAYAR)
Month alarm register (RMONAR)
Year alarm register (RYRAR)
RTC control register 1 (RCR1)
RTC control register 2 (RCR2)
RTC control register 3 (RCR3)
Rev. 3.00 Jan. 18, 2008 Page 562 of 1458
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Section 17 Realtime Clock (RTC)
17.3.1
64-Hz Counter (R64CNT)
R64CNT indicates the state of the divider circuit between 64 Hz and 1 Hz.
Reading this register, when carry from 128-Hz divider stage is generated, sets the CF bit in the
RTC control register 1 (RCR1) to 1 so that the carrying and reading 64 Hz counter are performed
at the same time is indicated. In this case, the R64CNT should be read again after writing 0 to the
CF bit in RCR1 since the read value is not valid.
After the RESET bit or ADJ bit in the RTC control register 2 (RCR2) is set to 1, the RTC divider
circuit is initialized and R64CNT is initialized to H'00.
R64CNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7

0
R
Reserved
This bit is always read as 0. Writing has no effect.
6
1 Hz
Undefined
R
5
2 Hz
Undefined
R
4
4 Hz
Undefined
R
3
8 Hz
Undefined
R
2
16 Hz
Undefined
R
1
32 Hz
Undefined
R
0
64 Hz
Undefined
R
Indicate the state of the divider circuit between
64 Hz and 1 Hz.
Rev. 3.00 Jan. 18, 2008 Page 563 of 1458
REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.3.2
Second Counter (RSECCNT)
RSECCNT is used for setting/counting in the BCD-coded second section. The count operation is
performed by a carry for each second of the 64-Hz counter.
The range of second can be set is 00 to 59 (decimal). Errant operation will result if any other value
is set. Carry out write processing after stopping the count operation with the START bit in RCR2.
RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
6 to 4

Undefined
R/W
Counting Ten’s Position of Seconds
Counts on 0 to 5 for 60-seconds counting.
3 to 0

Undefined
R/W
Counting One’s Position of Seconds
Counts on 0 to 9 once per second. When a carry
is generated, 1 is added to the ten’s position.
Rev. 3.00 Jan. 18, 2008 Page 564 of 1458
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Section 17 Realtime Clock (RTC)
17.3.3
Minute Counter (RMINCNT)
RMINCNT is used for setting/counting in the BCD-coded minute section. The count operation is
performed by a carry for each minute of the second counter.
The range of minute can be set is 00 to 59 (decimal). Errant operation will result if any other value
is set. Carry out write processing after stopping the count operation with the START bit in RCR2.
RMINCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7

0
R
Reserved
This bit is always read as 0.The write value
should always be 0.
6 to 4

Undefined
R/W
Counting Ten’s Position of Minutes
Counts on 0 to 5 for 60-minutes counting.
3 to 0

Undefined
R/W
Counting One’s Position of Minutes
Counts on 0 to 9 once per second. When a carry
is generated, 1 is added to the ten’s position.
Rev. 3.00 Jan. 18, 2008 Page 565 of 1458
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Section 17 Realtime Clock (RTC)
17.3.4
Hour Counter (RHRCNT)
RHRCNT is used for setting/counting in the BCD-coded hour section. The count operation is
performed by a carry for each 1 hour of the minute counter.
The range of hour can be set is 00 to 23 (decimal). Errant operation will result if any other value is
set. Carry out write processing after stopping the count operation with the START bit in RCR2.
RHRCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7, 6

All 0
R
Reserved
These bits are always read as 0. Though writing
has no effect, the write value should always be 0.
5, 4

Undefined
R/W
Counting Ten’s Position of Hours
Counts on 0 to 2 for ten’s position of hours.
3 to 0

Undefined
R/W
Counting One’s Position of Hours
Counts on 0 to 9 once per hour. When a carry is
generated, 1 is added to the ten’s position.
Rev. 3.00 Jan. 18, 2008 Page 566 of 1458
REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.3.5
Day of Week Counter (RWKCNT)
RWKCNT is used for setting/counting day of week section. The count operation is performed by a
carry for each day of the date counter.
The range for day of the week can be set is 0 to 6 (decimal). Errant operation will result if any
other value is set. Carry out write processing after stopping the count operation with the START
bit in RCR2.
RWKCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7 to 3

All 0
R
Reserved
These bits are always read as 0. Though writing
has n effect, the write value should always be 0.
2 to 0

Undefined
R/W
Day-of-Week Counting
Day-of-week is indicated with a binary code.
000: Sunday
001: Monday
010: Tuesday
011: Wednesday
100: Thursday
101: Friday
110: Saturday
111: Reserved (setting prohibited)
Rev. 3.00 Jan. 18, 2008 Page 567 of 1458
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Section 17 Realtime Clock (RTC)
17.3.6
Date Counter (RDAYCNT)
RDAYCNT is used for setting/counting in the BCD-coded date section. The count operation is
performed by a carry for each day of the hour counter.
Though the range of date which can be set is 01 to 31 (decimal). Errant operation will result if any
other value is set. Carry out write processing after stopping the count operation with the START
bit in RCR2.
RDAYCNT is not initialized by a power-on reset or manual reset, or in standby mode.
The range of date changes with each month and in leap years. Please confirm the correct setting.
Leap years are recognized by dividing the year counter values by 400, 100, and 4 and obtaining a
fractional result of 0. The year counter value of 0000 is included in the leap year.
Bit
Bit Name
Initial Value
R/W
Description
7, 6

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
5, 4

Undefined
R/W
Counting Ten’s Position of Dates
3 to 0

Undefined
R/W
Counting One’s Position of Dates
Counts on 0 to 9 once per date. When a carry is
generated, 1 is added to the ten’s position.
Rev. 3.00 Jan. 18, 2008 Page 568 of 1458
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Section 17 Realtime Clock (RTC)
17.3.7
Month Counter (RMONCNT)
RMONCNT is used for setting/counting in the BCD-coded month section. The count operation is
performed by a carry for each month of the date counter.
The range of month can be set is 01 to 12 (decimal). Errant operation will result if any other value
is set. Carry out write processing after stopping the count operation with the START bit in RCR2.
RMONCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7 to 5

All 0
R
Reserved
These bits are always read as 0. Though writing
has no effect, the write value should always be 0.
4

Undefined
R/W
Counting Ten’s Position of Months
3 to 0

Undefined
R/W
Counting One’s Position of Months
Counts on 0 to 9 once per month. When a carry
is generated, 1 is added to the ten’s position.
17.3.8
Year Counter (RYRCNT)
RYRCNT is used for setting/counting in the BCD-coded year section. The count operation is
performed by a carry for each year of the month counter.
The range for year which can be set is 0000 to 9999 (decimal). Errant operation will result if any
other value is set. Carry out write processing after halting the count operation with the START bit
in RCR2 or using a carry flag.
RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
15 to 12

Undefined
R/W
Counting Thousand’s Position of Years
11 to 8

Undefined
R/W
Counting Hundred’s Position of Years
7 to 4

Undefined
R/W
Counting Ten’s Position of Years
3 to 0

Undefined
R/W
Counting One’s Position of Years
Rev. 3.00 Jan. 18, 2008 Page 569 of 1458
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Section 17 Realtime Clock (RTC)
17.3.9
Second Alarm Register (RSECAR)
RSECAR is an alarm register corresponding to the BCD coded second counter RSECCNT of the
RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From
among RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and
alarm register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The range of second alarm which can be set is 00 to 59 (decimal) + ENB bits. Errant operation
will result if any other value is set.
The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields
are not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ENB
0
R/W
When this bit is set to 1, a comparison with the
RSECCNT value is performed.
6 to 4

Undefined
R/W
Ten’s position of seconds setting value
3 to 0

Undefined
R/W
One’s position of seconds setting value
17.3.10 Minute Alarm Register (RMINAR)
RMINAR is an alarm register corresponding to the minute counter RMINCNT. When the ENB bit
is set to 1, a comparison with the RMINCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The range of minute alarm which can be set is 00 to 59 (decimal). Errant operation will result if
any other value is set.
The ENB bit in RMINAR is initialized by a power-on reset. The remaining RMINAR fields are
not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ENB
0
R/W
When this bit is set to 1, a comparison with the
RMINCNT value is performed.
6 to 4

Undefined
R/W
Ten’s position of minutes setting value
3 to 0

Undefined
R/W
One’s position of minutes setting value
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Section 17 Realtime Clock (RTC)
17.3.11 Hour Alarm Register (RHRAR)
RHRAR is an alarm register corresponding to the BCD coded hour counter RHRCNT of the RTC.
When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The range of hour alarm which can be set is 00 to 23 (decimal). Errant operation will result if any
other value is set.
The ENB bit in RHRAR is initialized by a power-on reset. The remaining RHRAR fields are not
initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ENB
0
R/W
When this bit is set to 1, a comparison with the
RHRCNT value is performed.
6

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
5, 4

Undefined
R/W
Ten’s position of hours setting value
3 to 0

Undefined
R/W
One’s position of hours setting value
Rev. 3.00 Jan. 18, 2008 Page 571 of 1458
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Section 17 Realtime Clock (RTC)
17.3.12 Day of Week Alarm Register (RWKAR)
RWKAR is an alarm register corresponding to the BCD coded day of week counter RWKCNT.
When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The range of day of the week alarm which can be set is 0 to 6 (decimal). Errant operation will
result if any other value is set.
The ENB bit in RWKAR is initialized by a power-on reset. The remaining RWKAR fields are not
initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ENB
0
R/W
When this bit is set to 1, a comparison with the
RWKCNT value is performed.
6 to 3

0
R
Reserved
These bits are always read as 0. The write value
should always be 0.

2 to 0
Undefined
R/W
Day of week setting value
Code
0
1
2
3
Day
Sunday
Monday
Tuesday
Wednesday Thursday
Rev. 3.00 Jan. 18, 2008 Page 572 of 1458
REJ09B0033-0300
4
5
6
Friday
Saturday
Section 17 Realtime Clock (RTC)
17.3.13 Date Alarm Register (RDAYAR)
RDAYAR is an alarm register corresponding to the BCD coded date counter RDAYCNT. When
the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The range of date alarm which can be set is 01 to 31 (decimal). Errant operation will result if any
other value is set. The RDAYCNT range that can be set changes with some months and in leap
years. Please confirm the correct setting.
The ENB bit in RDAYAR is initialized by a power-on reset. The remaining RDAYAR fields are
not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ENB
0
R/W
When this bit is set to 1, a comparison with the
RDAYCNT value is performed.
6

0
R
Reserved
This bit is always read as 0. The write value
should always be 0.
5, 4

Undefined
R/W
Ten’s position of dates setting value
3 to 0

Undefined
R/W
One’s position of dates setting value
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.3.14 Month Alarm Register (RMONAR)
RMONAR is an alarm register corresponding to the month counter RMONCNT. When the ENB
bit is set to 1, a comparison with the RMONCNT value is performed. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The range of month alarm which can be set is 01 to 12 (decimal). Errant operation will result if
any other value is set.
The ENB bit in RMONAR is initialized by a power-on reset. The remaining RMONAR fields are
not initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ENB
0
R/W
When this bit is set to 1, a comparison with the
RMONCNT value is performed.
6, 5

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
4

Undefined
R/W
Ten’s position of months setting value
3 to 0

Undefined
R/W
One’s position of months setting value
17.3.15 Year Alarm Register (RYRAR)
RYRAR is an alarm register corresponding to the year counter RYRCNT. The range of year alarm
which can be set is 0000 to 9999 (decimal). Errant operation will result if any other value is set.
Bit
Bit Name
Initial Value
R/W
Description
15 to 12

Undefined
R/W
Thousand’s position of years setting value
11 to 8

Undefined
R/W
Hundred’s position of years setting value
7 to 4

Undefined
R/W
Ten’s position of years setting value
3 to 0

Undefined
R/W
One’s position of years setting value
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.3.16 RTC Control Register 1 (RCR1)
RCR1 is a register that affects carry flags and alarm flags. It also selects whether to generate
interrupts for each flag.
RCR1 is initialized to H'00 by a power-on reset or a manual reset, all bits are initialized to 0
except for the CF flag, which is undefined. When using the CF flag, it must be initialized
beforehand. This register is not initialized in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
CF
Undefined
R/W
Carry Flag
Status flag that indicates that a carry has
occurred. CF is set to 1 when a count-up to 64Hz occurs at the second counter carry or 64-Hz
counter read. A count register value read at this
time cannot be guaranteed; another read is
required.
0: No carry of 64-Hz counter by second counter
or 64-Hz counter
[Clearing condition]
When 0 is written to CF
1: Carry of 64-Hz counter by second counter or
64 Hz counter
[Setting condition]
When the second counter or 64-Hz counter is
read during a carry occurrence by the 64-Hz
counter, or 1 is written to CF.
6, 5
—
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
Bit
Bit Name
Initial Value
R/W
Description
4
CIE
0
R/W
Carry Interrupt Enable Flag
When the carry flag (CF) is set to 1, the CIE bit
enables interrupts.
0: A carry interrupt is not generated when the CF
flag is set to 1
1: A carry interrupt is generated when the CF flag
is set to 1
3
AIE
0
R/W
Alarm Interrupt Enable Flag
When the alarm flag (AF) is set to 1, the AIE bit
allows interrupts.
0: An alarm interrupt is not generated when the
AF flag is set to 1
1: An alarm interrupt is generated when the AF
flag is set to 1
2, 1
—
All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
0
AF
0
R/W
Alarm Flag
The AF flag is set when the alarm time, which is
set by an alarm register(ENB bit in RSECAR,
RMINAR, RHRAR, RWKAR, RDAYAR,
RMONAR, or RYRAR is set to 1), and counter
match.
0: Alarm register and counter not match
[Clearing condition]
When 0 is written to AF.
1: Alarm register and counter match*
[Setting condition]
When alarm register (only a register with ENB bit
set to 1) and counter match
Note:
Rev. 3.00 Jan. 18, 2008 Page 576 of 1458
REJ09B0033-0300
*
Writing 1 holds previous value.
Section 17 Realtime Clock (RTC)
17.3.17 RTC Control Register 2 (RCR2)
RCR2 is a register for periodic interrupt control, 30-second adjustment ADJ, divider circuit
RESET, and RTC count control.
RCR2 is initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by
a manual reset. It is not initialized in standby mode, and retains its contents.
Bit
Bit Name
Initial Value
R/W
Description
7
PEF
0
R/W
Periodic Interrupt Flag
Indicates interrupt generation with the period
designated by the PES2 to PES0 bits. When set
to 1, PEF generates periodic interrupts.
0: Interrupts not generated with the period
designated by the bits PES2 to PES0.
[Clearing condition] When 0 is written to PEF
1: Interrupts generated with the period
designated by the PES2 to PES0 bits.
[Setting condition] When an interrupt is
generated with the period designated by the
bits PES0 to PES2 or when 1 is written to the
PEF flag
6
PES2
0
R/W
Interrupt Enable Flags
5
PES1
0
R/W
These bits specify the periodic interrupt.
4
PES0
0
R/W
000: No periodic interrupts generated
001: Periodic interrupt generated every 1/256
second
010: Periodic interrupt generated every 1/64
second
011: Periodic interrupt generated every 1/16
second
100: Periodic interrupt generated every 1/4
second
101: Periodic interrupt generated every 1/2
second
110: Periodic interrupt generated every 1 second
111: Periodic interrupt generated every 2
seconds
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
Bit
Bit Name
Initial Value
R/W
Description
3
RTCEN
1
R/W
Crystal Oscillator Control
Controls the operation of the crystal oscillator for
the RTC.
0: Halts the crystal oscillator for the RTC.
1: Runs the crystal oscillator for the RTC.
2
ADJ
0
R/W
30-Second Adjustment
When 1 is written to the ADJ bit, times of 29
seconds or less will be rounded to 00 seconds
and 30 seconds or more to 1 minute. The divider
circuit (RTC prescaler and R64CNT) will be
simultaneously reset. This bit always reads 0.
0: Runs normally.
1: 30-second adjustment.
1
RESET
0
R/W
Reset
When 1 is written, initializes the divider circuit
(RTC prescaler and R64CNT). This bit always
reads 0.
0: Runs normally.
1: Divider circuit is reset.
0
START
1
R/W
Start Bit
Halts and restarts the counter (clock).
0: Second/minute/hour/day/week/month/year
counter halts.
1: Second/minute/hour/day/week/month/year
counter runs normally.
Note: The 64-Hz counter always runs unless
stopped with the RTCEN bit.
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.3.18 RTC Control Register 3 (RCR3)
When the ENB bit is set to 1, RCR3 performs a comparison with the RYRCNT. From among
RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR/RCR3, the counter and alarm
register comparison is performed only on those with ENB bits set to 1, and if each of those
coincide, an alarm flag of RCR1 is set to 1.
The ENB bit in RYRAR is initialized by a power-on reset. Remaining fields of RCR3 are not
initialized by a power-on reset or manual reset, or in standby mode.
Bit
Bit Name
Initial Value
R/W
Description
7
ENB
0
R/W
When this bit is set to 1, comparison of the year
alarm register (RYRAR) and the year counter
(RYRCNT) is performed.
6 to 0

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.4
Operation
RTC usage is shown below.
17.4.1
Initial Settings of Registers after Power-On
All the registers should be set after the power is turned on.
17.4.2
Setting Time
Figure 17.2 shows how to set the time when the clock is stopped.
Stop clock,
reset divider circuit
Write 1 to RESET and 0 to
START in the RCR2 register
Set seconds, minutes,
hour, day, day of the Order is irrelevant
week, month, and year
Start clock
Write 1 to START in the
RCR2 register
Figure 17.2 Setting Time
Rev. 3.00 Jan. 18, 2008 Page 580 of 1458
REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.4.3
Reading Time
Figure 17.3 shows how to read the time.
(a) To read the time
without using interrupts
Disable the carry interrupt
Clear the carry flag
Write 0 to CIE in RCR1
Write 0 to CF in RCR1
(Set AF in RCR1 to 1 so that alarm
flag is not cleared.)
Read counter register
Yes
Carry flag = 1?
Read RCR1 and check CF bit
No
(b) To use interrupts
Clear the carry flag
Enable the carry interrupt
Clear the carry flag
Write 1 to CIE in RCR1
Write 0 to CF in RCR1
(Set AF in RCR1 to 1 so that alarm
flag is not cleared.)
Read counter register
Yes
interrupt
Read RCR1 and check CF bit
No
Disable the carry interrupt
Write 0 to CIE in RCR1
Figure 17.3 Reading Time
If a carry occurs while reading the time, the correct time will not be obtained, so it must be read
again. Part (a) in figure 17.3 shows the method of reading the time without using interrupts; part
(b) in figure 17.3 shows the method using carry interrupts. To keep programming simple, method
(a) should normally be used.
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.4.4
Alarm Function
Figure 17.4 shows how to use the alarm function.
Clock running
Disable alarm
interrupt
Write 0 to AIE in RCR1
to prevent errorneous interrupt
Set alarm time
Clear alarm flag
Enable alarm
interrupt
Always clear, since the flag may have been
set while the alarm time was being set.
Write 1 to AIE in RCR1
Monitor alarm time
(wait for interrupt or
check alarm flag)
Figure 17.4 Using Alarm Function
Alarms can be generated using seconds, minutes, hours, day of the week, date, month, year, or any
combination of these. Set the ENB bit in the register on which the alarm is placed to 1, and then
set the alarm time in the lower bits. Clear the ENB bit in the register on which the alarm is not
placed to 0.
When the clock and alarm times match, 1 is set in the AF bit in RCR1. Alarm detection can be
checked by reading this bit, but normally it is done by interrupt. If 1 is set in the AIE bit in RCR1,
an interrupt is generated when an alarm occurs.
The alarm flag is set when the clock and alarm times match. However, the alarm flag can be
cleared by writing 0.
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Section 17 Realtime Clock (RTC)
17.5
Usage Notes
17.5.1
Register Writing during RTC Count
The following RTC registers cannot be written to during an RTC count (while bit 0 = 1 in RCR2).
RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT
The RTC count must be stopped before writing to any of the above registers.
17.5.2
Use of Realtime Clock (RTC) Periodic Interrupts
The method of using the periodic interrupt function is shown in figure 17.5.
A periodic interrupt can be generated periodically at the interval set by the flags PES0 to PES2 in
RCR2. When the time set by the PES0 to PES2 has elapsed, the PEF is set to 1.
The PEF is cleared to 0 upon periodic interrupt generation or when the flags PES0 to PES2 are set.
Periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt
function is used.
Set PES, clear PEF
Set PES0 to PES2,
and clear PEF to 0,
in RCR2
Elapse of time set by PES
Clear PEF
Clear PEF to 0
Figure 17.5 Using Periodic Interrupt Function
17.5.3
Transition to Standby Mode after Setting Register
When a transition to standby mode is made after registers in the RTC are set, sometimes counting
is not performed correctly. In case the registers are set, be sure to make a transition to standby
mode after waiting for two RTC clocks or more.
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REJ09B0033-0300
Section 17 Realtime Clock (RTC)
17.5.4
Crystal Oscillator Circuit
Crystal oscillator circuit constants (recommended values) are shown in table 17.2, and the RTC
crystal oscillator circuit in figure 17.5.
Table 17.2 Recommended Oscillator Circuit Constants (Recommended Values)
fosc
Cin
Cout
32.768 kHz
10 to 22 pF
10 to 22 pF
Rf
This LSI
RD
XTAL_RTC
EXTAL_RTC
XTAL
Cin
Cout
Notes: 1. Select either the Cin or Cout side for frequency adjustment variable capacitor
according to requirements such as frequency range, degree of stability, etc.
2. Built-in resistance value Rf (Typ value) = 10 MΩ, RD (Typ value) = 400 kΩ
3. Cin and Cout values include floating capacitance due to the wiring. Take care
when using a ground plane.
4. The crystal oscillation settling time depends on the mounted circuit constants,
stray capacitance, etc., and should be decided after consultation with the crystal
resonator manufacturer.
5. Place the crystal resonator and load capacitors Cin and Cout as close as possible
to the chip.
(Correct oscillation may not be possible if there is externally induced noise in the
EXTAL_RTC and XTAL_RTC pins.)
6. Ensure that the crystal resonator connection pin (EXTAL_RTC, XTAL_RTC)
wiring is routed as far away as possible from other power lines (except GND) and
signal lines.
Figure 17.6 Example of Crystal Oscillator Circuit Connection
Rev. 3.00 Jan. 18, 2008 Page 584 of 1458
REJ09B0033-0300
Section 18
Section 18
Serial Communication Interface with FIFO (SCIF)
Serial Communication Interface with FIFO
(SCIF)
This LSI has single-channel serial communication interface with FIFO (SCIF) that supports
asynchronous serial communication. The SCIF can perform asynchronous and synchronous serial
communication. It also has 64-stage FIFO registers for both transmission and reception that enable
this LSI efficient high-speed continuous communication. Channel 0 operates as an IrDA interface
while optional module IrDA is used.
18.1
Features
• Asynchronous or synchronous mode can be selected for serial communication mode.
• On-chip baud rate generator with selectable bit rates
• Internal or external transmit/receive clock source: From either baud rate generator (internal) or
SCK pin (external)
• Six types of interrupts (asynchronous mode):
Transmit-data-stop, transmit-FIFO-data-empty, receive-FIFO-data-full, receive-error (framing
error/parity error), break-receive, and receive-data-ready interrupts. A common interrupt vector
is assigned to each interrupt source.
• Two types of interrupts (synchronous mode)
• The direct memory access controller (DMAC) can be activated to execute a data transfer by a
transmit-FIFO-data-empty or receive-FIFO-data-full interrupt.
• On-chip modem control functions (CTS and RTS)
• Transmit data stop function is available
• While the SCIF is not used, it can be stopped by stopping the clock for it to reduce power
consumption.
• The number of data in the transmit and receive FIFO registers and the number of receive errors
of the receive data in the receive FIFO register can be known.
• Channel 0 operates as an IrDA interface.
• Full-duplex communication capability
The transmitter and receiver are independent units, enabling transmission and reception to be
performed simultaneously.
The transmitter and receiver both have a 64-stage FIFO buffer structure, enabling fast and
continuous serial data transmission and reception.
SCIS3C0C_000020030200
Rev. 3.00 Jan. 18, 2008 Page 585 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
• Asynchronous mode:
Serial data communications are performed by start-stop in character units. The SCI can
communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous
communication interface adapter (ACIA), or any other communications chip that employs a
standard asynchronous serial system. There are eight selectable serial data communication
formats.
 Data length: Seven or eight bits
 Stop bit length: One or two bits
 Parity: Even, odd, or none
 LSB first
 Receive error detection: Parity, framing, and overrun errors
 Break detection: Break is detected when the receive data next the generated framing error
is the space 0 level and has the framing error.
• Synchronous mode:
Serial data communication is synchronized with a clock. Serial data communication can be
carried out with other chips that have a synchronous communication function.
 Data length: 8 bits
 LSB-first transfer
Rev. 3.00 Jan. 18, 2008 Page 586 of 1458
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Section 18
Serial Communication Interface with FIFO (SCIF)
Module data bus
RxD
SCFRDR (64 stages)
SCFTDR (64 stages)
SCRSR
SCTSR
SCFDR
SCFCR
SCFER
SCSSR
SCSCR
SCSMR
SCTDSR
SCBRR
Pφ
Pφ/4
Pφ/16
Pφ/64
Baud rate
generator
Transmission/
reception control
Parity generation
Peripheral bus
Bus interface
Figure 18.1 shows the block diagram of SCIF.
Clock
Parity check
External clock
SCK
TxD
SCIF
interrupt
CTS
RTS
SCIF
[Legend]
SCRSR:
SCFRDR:
SCTSR:
SCFTDR:
SCSMR:
SCSCR:
Receive shift register
Receive FIFO data register
Transmit shift register
Transmit FIFO data register
Serial mode register
Serial control register
SCFER: FIFO error count register
SCSSR: Serial status register
SCBRR: Bit rate register
SCFCR: FIFO control register
SCFDR: FIFO data count register
SCTDSR: Transmit data stop register
Figure 18.1
Block Diagram of SCIF
Rev. 3.00 Jan. 18, 2008 Page 587 of 1458
REJ09B0033-0300
Section 18
18.2
Serial Communication Interface with FIFO (SCIF)
Input/Output Pins
Table 18.1 shows the pin configuration of SCIF.
Table 18.1 Pin configuration
Channel
0
1
Pin Name
Abbreviation*1
I/O
Function
3
SCIF0_SCK
SCK
Input*
Clock input/output
SCIF0_RxD
RxD
Input
Receive data input
SCIF0_TxD
TxD
SCIF0_CTS
CTS*
SCIF0_RTS
RTS*
Output Request to send
SCIF1_SCK
SCK
Input*3 Clock input/output
SCIF1_RXD
RxD
Input
SCIF1_TXD
TxD
SCIF1_CTS
CTS*
Input
SCIF1_RTS
RTS*
Output Request to send
Output Transmit data output
2
2
Input
Clear to send
Receive data input
Output Transmit data output
2
2
Clear to send
Notes: 1. Pin names SCK, RxD, TxD, CTS, and RTS are used in this manual for all channels,
omitting the channel designation.
2. These pins are used as serial pins by setting the SCIF with the TE and RE bits in SCIF
and the MCE bit in SCFCR.
3. The SCK pin can be set as input (input enabled or disabled).
Rev. 3.00 Jan. 18, 2008 Page 588 of 1458
REJ09B0033-0300
Section 18
18.3
Serial Communication Interface with FIFO (SCIF)
Register Descriptions
SCIF has the following registers. Refer to section 37, List of Registers, for more details on the
addresses and states of these registers in each operating mode. Note that the channel number of
each register is omitted.
(1) Channel 0
•
•
•
•
•
•
•
•
•
•
•
•
Receive shift register_0 (SCRSR_0)
Receive FIFO data register_0 (SCFRDR_0)
Transmit shift register_0 (SCTSR_0)
Transmit FIFO data register_0 (SCFTDR_0)
Serial mode register_0 (SCSMR_0)
Serial control register_0 (SCSCR_0)
FIFO error count register_0 (SCFER_0)
Serial status register_0 (SCSSR_0)
Bit rate register_0 (SCBRR_0)
FIFO control register_0 (SCFCR_0)
FIFO data count register_0 (SCFDR_0)
Transmit data stop register_0 (SCTDSR_0)
(2) Channel 1
•
•
•
•
•
•
•
•
•
•
•
•
Receive shift register_1 (SCRSR_1)
Receive FIFO data register_1 (SCFRDR_1)
Transmit shift register_1 (SCTSR_1)
Transmit FIFO data register_1 (SCFTDR_1)
Serial mode register_1 (SCSMR_1)
Serial control register_1 (SCSCR_1)
FIFO error count register_1 (SCFER_1)
Serial status register_1 (SCSSR_1)
Bit rate register_1 (SCBRR_1)
FIFO control register_1 (SCFCR_1)
FIFO data count register_1 (SCFDR_1)
Transmit data stop register_1 (SCTDSR_1)
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Section 18
18.3.1
Serial Communication Interface with FIFO (SCIF)
Receive Shift Register (SCRSR)
SCRSR receives serial data. Data input at the RxD pin is loaded into the SCRSR in the order
received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received,
it is automatically transferred to the SCFRDR, which is a receive FIFO data register. The CPU
cannot read from or write to the SCRSR directly.
18.3.2
Receive FIFO Data Register (SCFRDR)
The 64-byte receive FIFO data register (SCFRDR) stores serial receive data. The SCIF completes
the reception of one byte of serial data by moving the received data from the receive shift register
(SCRSR) into the SCFRDR for storage. Continuous receive is enabled until 64 bytes are stored.
The CPU can read but not write the SCFRDR. When data is read without received data in the
SCFRDR, the value is undefined. When the received data in this register becomes full, the
subsequent serial data is lost.
Bit
Bit Name
Initial value
R/W
Description
7 to 0
SCFRD7 to SCFRD0
Undefined
R
FIFO Data Registers for Serial Receive
Data
18.3.3
Transmit Shift Register (SCTSR)
SCTSR transmits serial data. The SCIF loads transmit data from the transmit FIFO data register
(SCFTDR) into the SCTSR, then transmits the data serially from the TxD pin, LSB (bit 0) first.
After transmitting one data byte, the SCI automatically loads the next transmit data from the
SCFTDR into the SCTSR and starts transmitting again. The CPU cannot read or write the SCTSR
directly.
18.3.4
Transmit FIFO Data Register (SCFTDR)
SCFTDR is a 64-byte 8-bit-length FIFO register that stores data for serial transmission. When the
SCIF detects that the transmit shift register (SCTSR) is empty, it moves transmit data written in
the SCFTDR into the SCTSR and starts serial transmission. Continuous serial transmission is
performed until the transmit data in the SCFTDR becomes empty. The CPU can always write to
the SCFTDR.
When the transmit data in the SCFTDR is full (64 bytes), next data cannot be written. If attempted
to write, the data is ignored.
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Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial value
R/W
Description
7 to 0
SCFTD7 to SCFTD0
Undefined
R
FIFO Data Registers for Serial Transmit
Data
18.3.5
Serial Mode Register (SCSMR)
SCSMR is a 16-bit register that specifies the SCIF serial communication format and selects the
clock source for the baud rate generator and the sampling rate.
Bit
Bit Name Initial Value R/W
15 to 11 
All 0
R
Description
Reserved
These bits are always read 0. The write value should
always be 0.
10
SRC2
0
R/W
Sampling Control 2 to 0
9
SRC1
0
R/W
Select sampling rate.
8
SRC0
0
R/W
000: Sampling rate 1/16
001: Sampling rate 1/5
010: Sampling rate 1/7
011: Sampling rate 1/11
100: Sampling rate 1/13
101: Sampling rate 1/17
110: Sampling rate 1/19
111: Sampling rate 1/27
7
C/A
0
R/W
Communication Mode
Selects whether the SCI operates in the
asynchronous or synchronous mode.
0: Asynchronous mode
1: Synchronous mode
Rev. 3.00 Jan. 18, 2008 Page 591 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name Initial Value R/W
Description
6
CHR
Character Length
0
R/W
Selects seven-bit or eight-bit data.
This bit is only valid in asynchronous mode. In
synchronous mode, the data length is always eight
bits, regardless of the CHR setting.
0: Eight-bit data
1: Seven-bit data*
Note: * When seven-bit data is selected, the MSB
(bit 7) in SCFTDR is not transmitted.
5
PE
0
R/W
Parity Enable
Selects whether to add a parity bit to transmit data
and to check the parity of receive data. This setting is
only valid in asynchronous mode. In synchronous
mode, parity bit addition and checking is not
performed, regardless of the PE setting.
0: Parity bit not added or checked
1: Parity bit added and checked
Note:
Rev. 3.00 Jan. 18, 2008 Page 592 of 1458
REJ09B0033-0300
*
When PE is set to 1, an even or odd parity
bit is added to transmit data, depending on
the parity mode (O/E) setting. Receive
data parity is checked according to the
even/odd (O/E) mode setting.
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name Initial Value R/W
Description
4
O/E
Parity Mode
0
R/W
Selects even or odd parity when parity bits are added
and checked. The O/E setting is used only when the
PE is set to 1 to enable parity addition and check. The
O/E setting is ignored when parity addition and check
is disabled.
0: Even parity*
1
2
1: Odd parity*
Notes: 1. If even parity is selected, the parity bit is
added to transmit data to make an even
number of 1s in the transmitted character
and parity bit combined. Receive data is
checked to see if it has an even number of
1s in the received character and parity bit
combined.
2. If odd parity is selected, the parity bit is
added to transmit data to make an odd
number of 1s in the transmitted character
and parity bit combined. Receive data is
checked to see if it has an odd number of
1s in the received character and parity bit
combined.
Rev. 3.00 Jan. 18, 2008 Page 593 of 1458
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Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
3
STOP
0
Stop Bit Length
R/W
Selects one or two bits as the stop bit length.
In receiving, only the first stop bit is checked,
regardless of the STOP bit setting. If the second stop
bit is 1, it is treated as a stop bit, but if the second stop
bit is 0, it is treated as the start bit of the next incoming
character.
This setting is only valid in asynchronous mode. In
synchronous mode, this setting is invalid since stop
bits are not added.
1
0: One stop bit*
1: Two stop bits*
2
Notes: 1. In transmitting, a single bit of 1 is added at
the end of each transmitted character.
2. In transmitting, two bits of 1 are added at
the end of each transmitted character.
2
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
1
CKS1
0
R/W
Clock Select 1 and 0
0
CKS0
0
R/W
These bits select the internal clock source of the onchip baud rate generator.
00: Pφ
01: Pφ/4
10: Pφ/16
11: Pφ/64
Note: In synchronous mode, bits other than CKS1 and CKS0 are fixed 0.
Rev. 3.00 Jan. 18, 2008 Page 594 of 1458
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Section 18
18.3.6
Serial Communication Interface with FIFO (SCIF)
Serial Control Register (SCSCR)
SCSCR is a 16-bit readable/writable register that operates the SCI transmitter/receiver,
enables/disables interrupt requests, and selects the transmit/receive clock source.
Bit
Bit Name
Initial Value R/W
Description
15
TDRQE
0
Transmit Data Transfer Request Enable
R/W
Selects whether to issue the transmit-FIFO-dataempty interrupt request or DMA transfer request when
TIE = 1 and transmit FIFO empty interrupt is
generated at the transmission.
0: Interrupt request is issued to CPU
1: Transmit data transfer request is issued to DMAC
14
RDRQE
0
R/W
Receive Data Transfer Request Enable
Selects whether to issue the receive-FIFO-data-full
interrupt or DMA transfer request when RIE = 1 and
receive FIFO data full interrupt is generated at the
reception.
0: Interrupt request is issued to CPU
1: Receive data transfer request is issued to DMAC
13,12

All 0
R
Reserved
These bits are always read as 0. The write value
should always be 0.
11
TSIE
0
R/W
Transmit Data Stop Interrupt Enable
Enables or disables the generation of the transmitdata-stop interrupt requested when the TSE bit in
SCFCR is enabled and the TSF flag in SCSSR is set
to 1.
0: The transmit-data-stop-interrupt disabled*
1: The transmit-data-stop-interrupt enabled
Note:
*
The transmit data stop interrupt request is
cleared by reading the TSF flag after it has
been set to 1, then clearing the flag to 0,
or clearing the TSIE bit to 0.
Rev. 3.00 Jan. 18, 2008 Page 595 of 1458
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Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
10
ERIE
0
Receive Error Interrupt Enable
R/W
Enables or disables the generation of a receive-error
(framing error/parity error) interrupt requested when
the ER flag in SCSSR is set to 1.
0: The receive-error interrupt disabled*
1: The receive-error interrupt enabled
Note:
9
BRIE
0
R/W
*
The receive-error interrupt request is
cleared by reading the ER flag after it has
been set to 1, then clearing the flag to 0,
or clearing the ERIE bit to 0.
Break Interrupt Enable
Enables or disables the generation of break-receive
interrupt requested when the BRK flag in SCSSR is
set to 1.
0: The break-receive interrupt disabled*
1: The break receive interrupt enabled
Note:
8
DRIE
0
R/W
*
The break-receive interrupt request is
cleared by reading the BRK flag after it
has been set to 1, then clearing the flag to
0, or clearing the BRIE bit to 0.
Receive Data Ready Interrupt Enable
Disables or enables the generation of receive-dataready interrupt when the DR flag in SCSSR is set to 1.
0: The receive-data-ready interrupt disabled
1: The receive-data-ready interrupt enabled
Note:
Rev. 3.00 Jan. 18, 2008 Page 596 of 1458
REJ09B0033-0300
*
The receive-data-ready interrupt request is
cleared by reading the DR flag after it has
been set to 1, then clearing the flag to 0,
or clearing the DRIE bit to 0.
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
7
TIE
0
Transmit Interrupt Enable
R/W
Enables or disables the transmit-FIFO-data-empty
interrupt requested when the TDFE flag of SCSSR is
set to 1.
0: Transmit-FIFO-data-empty interrupt request
disabled*
1: Transmit-FIFO-data-empty interrupt request
enabled
Note:
6
RIE
0
R/W
*
The transmit-FIFO-data empty interrupt
request can be cleared by writing the
greater number of transmit data than the
specified number of transmission triggers
to SCFTDR and by clearing TDFE to 0
after reading 1 from TDFE, or can be
cleared by clearing TIE to 0.
Receive Interrupt Enable
Enables or disables the receive-FIFO-data-full
interrupt requested when the RDF flag of SCSSR is
set to1.
0: Receive-FIFO-data-full interrupt request disabled*
1: Receive-FIFO-data-full interrupt request enabled
Note:
5
TE
0
R/W
*
The receive-FIFO-data -full interrupt
request can be cleared by reading the
RDF flag after it has been set to 1, then
clearing the flag to 0, or by clearing the
RIE bit to 0.
Transmit Enable
Enables or disables the SCIF serial transmitter.
0: Transmitter disabled
1: Transmitter enabled*
Note:
*
The serial mode register (SCSMR) and
FIFO control register (SCFCR) should be
set to select the transmit format and reset
the transmit FIFO before setting the TE bit
to 1.
Rev. 3.00 Jan. 18, 2008 Page 597 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name Initial Value R/W Description
4
RE
0
R/W Receive Enable
Enables or disables the SCIF serial receiver.
0: Receiver disabled*
1
2
1: Receiver enabled*
Notes: 1. Clearing RE to 0 does not affect the receive
flags (DR, ER, BRK, RDF, FER, PER, and
ORER). These flags retain their previous
values.
2. The serial mode register (SCSMR) and FIFO
control register (SCFCR) should be set to
select the receive format and reset the receive
FIFO before setting the RE bit to 1.
3, 2
—
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
1
CKE1
0
R/W Clock Enable 1and 0
0
CKE0
0
R/W These bits select the SCIF clock source. The bits CKE1
and CKE0 should be set before selecting the SCIF
operating mode by SCSMR.
00: Internal clock, SCK pin used for input pin (input signal
1
is ignored)*
01: Internal clock, SCK pin used for synchronous clock
output*2
10: External clock, SCK pin used for clock input*
3
3
11: External clock, SCK pin used for clock input*
Notes: 1. When the data sampling is executed using onchip baud rate generator, CKE1 and CKE0
should be set to 00.
2. In synchronous mode, a clock with a
frequency equal to the bit rate is output. When
the channel 0 is used as the IrDA interface,
CKE1 and CKE0 should be set to 01.
3. In asynchronous mode, input the clock which
is appropriate for the sampling rate. For
example, when the sampling rate is 1/16,
input the clock frequency 8 times the bit rate.
When the external clock is not input, CKE1
and CKE0 should be set to 00.
When the SCK pin is set as an I/O port pin,
CKE1 and CKE0 should be set to 00.
Rev. 3.00 Jan. 18, 2008 Page 598 of 1458
REJ09B0033-0300
Section 18
18.3.7
Serial Communication Interface with FIFO (SCIF)
FIFO Error Count Register (SCFER)
SCFER is a 16-bit read-only register that indicates the number of receive data errors (framing
error/parity error).
Bit
Bit Name
Initial value R/W
15,14

All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
13
PER5
0
R
Parity Error
12
PER4
0
R
11
PER3
0
R
10
PER2
0
R
Indicates the number of data, in which parity errors
are generated, in receive data stored in the receive
FIFO data register (SCFRDR) in asynchronous mode.
9
PER1
0
R
8
PER0
0
R
If all 64-byte receive data in SCFRDR have parity
errors, bits PER5 to PER0 indicate 0s.
7, 6

All 0
R
Reserved
Bits 13 to 8 indicate the number of data with parity
errors after the ER bit in SCSSR is set.
These bits are always read as 0. The write value
should always be 0.
5
FER5
0
R
Framing Error
4
FER4
0
R
3
FER3
0
R
2
FER2
0
R
Indicates the number of data, in which framing errors
are generated, in receive data stored in the receive
FIFO data register (SCFRDR) in asynchronous mode.
1
FER1
0
R
0
FER0
0
R
Bits 5 to 0 indicate the number of data with framing
errors after the ER bit in SCSSR is set.
If all 64-byte receive data in SCFRDR have framing
errors, bits FER5 to FER0 indicate 0s.
Rev. 3.00 Jan. 18, 2008 Page 599 of 1458
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Section 18
18.3.8
Serial Communication Interface with FIFO (SCIF)
Serial Status Register (SCSSR)
SCSSR is a 16-bit readable/writable register that indicates SCIF states. The ORER, TSF, ER,
TDFE, BRK, RDF, or DR flag cannot be set to 1. These flags can be cleared to 0 only if they have
first been read (after being set to 1). The flags TEND, FER, and PER are read-only bits and cannot
be modified.
Bit
Bit Name
15 to 10 
Initial Value R/W
All 0
R
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
9
ORER
0
R/(W)* Overrun Error Flag
Indicates that the overrun error occurred during
reception.
This bit is valid only in asynchronous mode.
0: Indicates during reception, or reception has been
1
completed without any error*
[Clearing conditions]
Power-on reset, manual reset
Writing 0 after reading ORER = 1
1: Indicates that the overrun error is generated during
reception*2
[Setting condition]
When receive FIFO is full and the next serial data
reception is completed
Notes: 1. When the RE bit in SCSCR is cleared to 0,
the ORER flag is not affected and retains
its previous state.
2. SCFRDR holds the data received before
the overrun error, and newly received data
is lost. When ORER is set to 1,
subsequent serial data reception cannot
be carried out.
Rev. 3.00 Jan. 18, 2008 Page 600 of 1458
REJ09B0033-0300
Section 18
Bit
Bit Name Initial Value R/W
8
TSF
0
Serial Communication Interface with FIFO (SCIF)
Description
R/(W)* Transmit Data Stop Flag
Indicates that the number of transmit data matches the
value set in SCTDSR.
0: Transmit data number does not match the value set
in SCTDSR
[Clearing conditions]
•
Power-on reset, manual reset
•
Writing 0 after reading TSF = 1
1: Transmit data number matches the value set in
SCTDSR
7
ER
0
R/(W)* Receive Error
Indicates that a framing error or parity error occurred
1
during reception in asynchronous mode.*
0: Receive is normally completed without any framing or
parity error
[Clearing conditions]
Power-on reset, manual reset
ER is read as 1, then written to with 0.
1: A framing error or a parity error has occurred during
receiving
[Setting conditions]
•
The stop bit is 0 after checking whether or not the
last stop bit of the received data is 1 at the end of
2
one-data receive.*
•
The total number of 1's in the received data and in
the parity bit does not match the even/odd parity
specification specified by the O/E bit in the SCSMR.
Notes: 1. Indicates clearing the RE bit to 0 in SCSCR
does not affect the ER bit, which retains its
previous value. Even if a receive error
occurs, the received data is transferred to
SCFRDR and the receive operation is
continued. Whether or not the data read
from SCRDR includes a receive error can
be detected by the FER and PER bits in
SCSSR.
2. n the stop mode, only the first stop bit is
checked; the second stop bit is not checked.
Rev. 3.00 Jan. 18, 2008 Page 601 of 1458
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Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value
R/W
Description
6
TEND
1
R
Transmit End
Indicates that when the last bit of a serial character was
transmitted, the SCFTDR did not contain valid data, so
transmission has ended.
0: Transmission is in progress
[Clearing condition]
Data is written to SCFTDR.
1: End of transmission
[Setting condition]
SCFTDR contains no transmit data when the last bit of a onebyte serial character is transmitted.
5
TDFE
1
R/(W)*
Transmit FIFO Data Empty
Indicates that data is transferred from the transmit FIFO data
register (SCFTDR) to the transmit shift register (SCTSR), the
number of data in SCFTDR becomes less than the number of
transmission triggers specified by the TTRG1 and TTRG0 bits
in the FIFO control register (SCFCR), and writing the transmit
data to SCFTDR is enabled.
0: The number of transmit data written to SCFTDR is greater
than the specified number of transmission triggers
[Clearing condition]
Data exceeding the specified number of transmission
triggers is written to SCFTDR, software reads TDFE after it
has been set to 1, then writes 0 to TDFE.
1: The number of transmission data in SCFTDR becomes less
than the specified number of transmission triggers
[Setting conditions]
•
Power-on reset, manual reset
•
The number of transmission data in SCFTDR becomes
less than the specified number of transmission triggers as
a result of transmission*
Note:
Rev. 3.00 Jan. 18, 2008 Page 602 of 1458
REJ09B0033-0300
*
Since SCFTDR is a 64-byte FIFO register, the
maximum number of data which can be written
when TDFE is 1 is "64 minus the specified
number of transmission triggers". If attempted to
write additional data, the data is ignored. The
number of data in SCFTDR is indicated by
SCFDR.
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name Initial Value
R/W
4
BRK
R/(W)* Break Detection
0
Description
Indicates that a break signal is detected in received
data in asynchronous mode.
0: No break signal is being received
[Clearing conditions]
•
Power-on reset, manual reset
•
BRK is read as 1, then written to with 0
1: A break signal is received *
[Setting conditions]
Data including a framing error is received
•
A framing error with space 0 occurs in the
subsequent received data
Note: * When a break is detected, transfer of the
received data (H'00) to SCFRDR stops
after detection. When the break ends and
the receive signal becomes mark 1, the
transfer of the received data resumes.
3
FER
0
R
Framing Error
Indicates a framing error in the data read from the
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No framing error occurred in the data read from
SCFRDR
[Clearing conditions]
•
Power-on reset, manual reset
•
No framing error is present in the data read from
SCFRDR
1: A framing error occurred in the data read from
SCFRDR
[Setting condition]
•
A framing error is present in the data read from
SCFRDR
Rev. 3.00 Jan. 18, 2008 Page 603 of 1458
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Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value
R/W
Description
2
PER
0
R
Parity Error
Indicates a parity error in the data read from the
receive FIFO data register (SCFRDR) in
asynchronous mode.
0: No parity error occurred in the data read from
SCFRDR
[Clearing conditions]
•
Power-on reset, manual reset
•
No parity error is present in the data read from
SCFRDR
1: A parity error occurred in the data read from
SCFRDR
[Setting condition]
•
Rev. 3.00 Jan. 18, 2008 Page 604 of 1458
REJ09B0033-0300
A parity error is present in the data read from
SCFRDR
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name Initial Value R/W
Description
1
RDF
Receive FIFO Data Full
0
R/(W)*
Indicates that received data is transferred to the
receive FIFO data register (SCFRDR), the number of
data in SCFRDR becomes more than the number of
receive triggers specified by the RTRG1 and RTRG0
bits in SCFCR.
0: The number of transmit data written to SCFRDR is
less than the specified number of receive triggers
[Clearing conditions]
•
Power-on reset, manual reset
•
SCFRDR is read until the number of receive data
in SCFRDR becomes less than the specified
number of receive triggers, and RDF is read as 1,
then written to with 0.
1: The number of receive data in SCFRDR is more
than the specified number of receive triggers
[Setting condition]
The number of receive data which is greater than the
specified number of receive triggers is being stored to
SCFRDR.*
Note:
*
Since SCFTDR is a 64-byte FIFO
register, the maximum number of data
which can be read when RDF is 1 is the
specified number of receive triggers. If
attempted to read after all data in
SCFRDR have been read, the data is
undefined. The number of receive data in
SCFRDR is indicated by the lower bits of
SCFTDR.
Rev. 3.00 Jan. 18, 2008 Page 605 of 1458
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Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value
R/W
Description
0
DR
0
R/(W)* Receive Data Ready
Indicates that the receive FIFO data register
(SCFRDR) stores the data which is less than the
specified number of receive triggers, and that next
data is not yet received after 15 etu has elapsed
from the last stop bit in asynchronous mode.
0: Receive is in progress, or no received data
remains in SCFRDR after the receive ended
normally.
[Clearing conditions] (Initial value)
•
Power-on reset, manual reset
•
All receive data in SCFRDR is read, and DR is
read as 1, then written to with 0.
1: Next receive data is not received
[Setting condition]
SCFRDR stores the data which is less than the
specified number of receive triggers, and that next
data is not yet received after 15 etu has elapsed
from the last stop bit.*
Note:
Note:
*
*
This is equivalent to 1.5 frames with the
8-bit 1-stop-bit format. (etu: Element
Time Unit)
The only value that can be written is 0 to clear the flag.
Rev. 3.00 Jan. 18, 2008 Page 606 of 1458
REJ09B0033-0300
Section 18
18.3.9
Serial Communication Interface with FIFO (SCIF)
Bit Rate Register (SCBRR)
SCBRR is an eight-bit readable/writable register that, together with the baud rate generator clock
source selected by the CKS1 and CKS0 bits in the serial mode register (SCSMR), determines the
serial transmit/receive bit rate.
Bit
Bit Name
Initial value
7 to 0
SCBRD7 to H'FF
SCBRD0
R/W
Description
R/W
Bit Rate Set
The SCBRR setting is calculated as follows:
Asynchronous Mode:
1. When sampling rate is 1/16
N=
Pφ
32 × 22n-1 × B
× 106 - 1
2. When sampling rate is 1/5
N=
Pφ
10 × 22n-1 × B
× 106 - 1
3. When sampling rate is 1/11
N=
Pφ
22 × 22n-1 × B
× 106 - 1
4. When sampling rate is 1/13
N=
Pφ
26 × 22n-1 × B
× 106 - 1
5. When sampling rate is 1/27
N=
Pφ
54 × 22n-1 × B
× 106 - 1
Synchronous Mode:
N=
Pφ
4 × 22n-1 × B
× 106 - 1
Rev. 3.00 Jan. 18, 2008 Page 607 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
B:
N:
Pφ:
n:
Bit rate (bits/s)
SCBRR setting for baud rate generator
Asynchronous mode: 0 ≤ N ≤ 255
Synchronous mode: 1 ≤ N ≤ 255
Peripheral module operating frequency (MHz)
Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SCSMR Settings
n
Clock Source
CKS1
0
Pφ
0
0
1
Pφ/4
0
1
2
Pφ/16
1
0
3
Pφ/64
1
1
Find the bit rate error in asynchronous mode by the following formula:
1. When sampling rate is 1/16
Error (%) =
Pφ × 106
- 1 × 100
(1+N) × B × 32 × 22n-1
2. When sampling rate is 1/5
Error (%) =
Pφ × 106
- 1 × 100
(1+N) × B × 10 × 22n-1
3. When sampling rate is 1/11
Error (%) =
Pφ × 106
(1+N) × B × 22 × 22n-1
- 1 × 100
4. When sampling rate is 1/13
Error (%) =
Pφ × 106
- 1 × 100
(1+N) × B × 26 × 22n-1
5. When sampling rate is 1/27
Error (%) =
Pφ × 106
- 1 × 100
(1+N) × B × 58 × 22n-1
Rev. 3.00 Jan. 18, 2008 Page 608 of 1458
REJ09B0033-0300
CKS0
Section 18
Serial Communication Interface with FIFO (SCIF)
18.3.10 FIFO Control Register (SCFCR)
SCFCR is a 16-bit readable/writable register that resets the number of data in the transmit and
receive FIFO registers, sets the number of trigger data, and contains an enable bit for the loop back
test.
Bit
Bit Name
Initial Value R/W
Description
15
TSE
0
Transmit Data Stop Enable
R/W
Enables or disables transmit data stop function. This
function is enabled only in asynchronous mode.
Since this function is not supported in synchronous
mode, clear this bit to 0 in synchronous mode.
0: Transmit data stop function disabled
1: Transmit data stop function enabled
14
TCRST
0
R/W
Transmit Count Reset
Clears the transmit count to 0. This bit is available
while the transmit data stop function is enabled.
0: Transmit count reset disabled*
1: Transmit count reset enabled (cleared to 0)
Note:
13 to 11 
All 0
R
*
The transmit count is reset (cleared to 0)
by a power-on reset or manual reset.
Reserved
These bits are always read as 0. The write value
should always be 0.
10
RSTRG2
0
R/W
Trigger of the RTS Output Active 2 to 0
9
RSTRG1
0
R/W
8
RSTRG0
0
R/W
The RTS signal goes to high, when the number of
receive data count stored in the receive FIFO data
register (SCFRDR) is increased more than the
number of setting triggers listed below.
000: 63
001: 1
010: 8
011: 16
100: 32
101: 48
110: 54
111: 60
Rev. 3.00 Jan. 18, 2008 Page 609 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
7
RTRG1
0
R/W
Trigger of the Number of Receive FIFO Data 1, 0
6
RTRG0
0
R/W
Set the number of receive data which sets the
receive data full (RDF) flag in the serial status
register (SCSSR). These bits set the RDF flag when
the number of receive data stored in the receive
FIFO data register (SCFRDR) is increased more
than the number of setting triggers listed below.
00: 1
01: 16
10: 32
11: 48
5
TTRG1
0
R/W
Trigger of the Number of Transmit FIFO Data 1, 0
4
TTRG0
0
R/W
Set the number of remaining transmit data which
sets the transmit FIFO data register empty (TDFE)
flag in the serial status register (SCSSR). These bits
set the TDFE flag when the number of transmit data
in the transmit FIFO data register (SCFTDR) is
decreased less than the number of setting triggers
listed below.
00: 32 (32)
01: 16 (49)
10: 2 (62)
11: 0 (64)
Note:
3
MCE
0
R/W
*
Values in brackets mean the number of
empty bytes in SCFTDR when the TDFE
is set.
Modem Control Enable
Enables the modem control signals CTS and RTS.
0: Disables the modem signal*
1: Enables the modem signal
Note:
Rev. 3.00 Jan. 18, 2008 Page 610 of 1458
REJ09B0033-0300
*
The CTS is fixed to active 0 regardless
of the input value, and the RTS is also
fixed to 0.
Section 18
Serial Communication Interface with FIFO (SCIF)
Bit
Bit Name
Initial Value R/W
Description
2
TFRST
0
Transmit FIFO Data Register Reset
R/W
Cancels the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note:
1
RFRST
0
R/W
*
The reset is executed in a power-on
reset or a manual reset.
Receive FIFO Data Register Reset
Cancels the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Disables reset operation*
1: Enables reset operation
Note:
0
LOOP
0
R/W
*
The reset is executed in a power-on
reset or a manual reset.
Loop Back Test
Internally connects the transmit output pin (TxD)
and receive input pin (RxD) and enables the loop
back test.
0: Disables the loop back test
1: Enables the loop back test
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Section 18
Serial Communication Interface with FIFO (SCIF)
18.3.11 FIFO Data Count Register (SCFDR)
SCFDR is a 16-bit register which indicates the number of data stored in the receive FIFO data
register (SCFRDR). The SCFDR is always read from the CPU.
The bits 14 to 8 of this register indicate the number of transmit data items stored in the SCFTDR
that have not yet been transmitted.
The bits 6 to 0 of this register indicate the number of receive data items stored in the SCFRDR.
Bit
Bit Name
Initial Value R/W
Description
15
—
0
Reserved
R
This bit is always read as 0. The write value should
always be 0.
14
T6
0
R
13
T5
0
R
12
T4
0
R
11
T3
0
R
10
T2
0
R
9
T1
0
R
8
T0
0
R
7
—
0
R
These bits indicate the number of non-transmitted
data stored in the SCFTDR. The H'00 means no
transmit data, and the H'40 means that the full of
transmit data are stored in the SCFTDR.
Reserved
This bit is always read as 0. The write value should
always be 0.
6
R6
0
R
5
R5
0
R
4
R4
0
R
3
R3
0
R
2
R2
0
R
1
R1
0
R
0
R0
0
R
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REJ09B0033-0300
These bits indicate the number of receive data
stored in the SCFRDR. The H'00 means no receive
data, and the H'40 means that the full of receive
data are stored in the SCFRDR.
Section 18
Serial Communication Interface with FIFO (SCIF)
18.3.12 Transmit Data Stop Register (SCTDSR)
SCTDSR is an 8-bit readable/writable register that sets the number of data to be transmitted. This
register is available when the TSE bit in the FIFO control register (SCFCR) is enabled. The
transmit operation stops after all data set by this register have been transmitted. Settable values are
H'00 (1 byte) to H'FF (256 bytes). The initial value of this register is H'FF.
18.4
Operation
For serial communication, the SCIF has asynchronous mode in which characters are synchronized
individually and synchronous mode in which synchronization is achieved with clock pulses. The
SCIF has the 64-byte FIFO buffer for both transmission and reception, reduces an overhead of the
CPU, and enables continuous high-speed communication.
18.4.1
Asynchronous Mode
Operation in asynchronous mode is described below.
The transmission and reception format is selected in the serial mode register (SCSMR), as listed in
table 18.2. The clock source of SCIF is determined by the combination of CKE1 and CKE0 bits in
the serial control register (SCSCR).
• Data length is selectable from seven or eight bits.
• Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The
combination of the preceding selections constitutes the communication format and character
length.
• In receiving, it is possible to detect framing errors, parity errors, overrun errors, receive FIFO
data full, receive data ready, and breaks.
• The number of stored data for both the transmit and receive FIFO registers is displayed.
• Clock source: Internal clock/external clock
 Internal clock: SCIF operates using the on-chip baud rate generator
 External clock: The clock appropriate for the sampling rate should be input. For example,
when the sampling rate is 1/16, input the clock frequency 8 times the bit rate. (The internal
baud rate generator should not be used.)
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Section 18
Serial Communication Interface with FIFO (SCIF)
Table 18.2 SCSMR Settings and SCIF Transmit/Receive
SCSMR Settings
Bit 6
Bit 5
SCIF Transmit/Receive
Bit 3
Data
Length
Multiprocessor
Parity Bit
Bit
CHR
PE
STOP
Mode
0
0
0
Asynchro- 8-bit data Not set
nous mode
1
1
0
Not set
0
0
Set
0
1
18.4.2
(1)
1 bit
2 bits
7-bit data
Not set
1
1
1 bit
2 bits
1
1
Stop Bit
Length
1 bit
2 bits
Set
1 bit
2 bits
Serial Operation
Transmit/Receive Formats
Table 18.3 lists eight communication formats that can be selected. The format is selected by
settings in the serial mode register (SCSMR).
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Section 18
Serial Communication Interface with FIFO (SCIF)
Table 18.3 Serial Transmit/Receive Formats
SCSMR Bits
Serial Transmit/Receive Format and Frame Length
CHR PE
STOP
0
0
0
START
8-Bit data
STOP
0
0
1
START
8-Bit data
STOP STOP
0
1
0
START
8-Bit data
P
STOP
0
1
1
START
8-Bit data
P
STOP STOP
1
0
0
START
7-Bit data
STOP
1
0
1
START
7-Bit data
STOP STOP
1
1
0
START
7-Bit data
P
STOP
1
1
1
START
7-Bit data
P
STOP STOP
(2)
1
2
3
4
5
6
7
8
9
10
11
12
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the CKE bit in the
serial control register (SCSCR).
When an external clock is input at the SCK pin, the clock appropriate for the sampling rate should
be input. For example, when the sampling rate is 1/16, the clock frequency should be 8 times the
bit rate used.
(3)
Transmitting and Receiving Data (SCIF Initialization)
Before transmitting or receiving, clear the TE and RE bits to 0 in SCSCR, then initialize the SCIF
as follows.
When changing the communication format, always clear the TE and RE bits to 0 before following
the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR).
Clearing TE and RE to 0, however, does not initialize the serial status register (SCSSR), transmit
FIFO data register (SCFTDR), or receive FIFO data register (SCFRDR), which retain their
previous contents.
Clear TE to 0 after all transmit data are transmitted and the TEND bit in the SCSSR is set. The
transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared
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Section 18
Serial Communication Interface with FIFO (SCIF)
to 0 in transmitting. Set the TFRST bit in the SCFCR to 1 and reset the SCFTDR before TE is set
again to start transmission.
When an external clock is used, the clock should not be stopped during initialization or subsequent
operation. SCIF operation becomes unreliable if the clock is stopped.
Figure 18.2 is a sample flowchart for initializing the SCIF.
Initialization
Clear TE and RE bits in SCSCR to 0
(1)
(1) Set the clock selection in SCSCR.
Be sure to clear bits RIE TIE, TE, and RE
to 0.
(2) Set the operating clock source in SCSMR.
Set TFRST and RFRST bits in
SCFCR to 1
(3) Write a value corresponding to the bit rate
into SCBRR.
(Not necessary if an external clock is used.)
Set CKE1 and CKE0
bits in SCSCR2 (leaving TE and RE
bits cleared to 0)
Set operating clock source in SCSMR (2)
(3)
Set value in SCBRR
(4) Wait at least one bit interval, then set the
TE bit or RE bit in SCSR to 1. Also set the
RIE and TIE bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used. When
transmitting, the SCIF will go to the mark
state; when receiving, it will go to the idle
state.
Wait
No
1-bit interval elapsed?
(4)
Yes
Set RTRG1, RTRG0,
TTRG1, and TTRG0 in SCFCR
Clear TFRST and RFRST bits to 0
Set TE and RE bits in
SCSCR to 1,and set RIE,
and TIE bits
End
Figure 18.2
Sample SCIF Initialization Flowchart
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Section 18
(4)
Serial Communication Interface with FIFO (SCIF)
Transmitting and Receiving Data (Serial data transmission)
Figure 18.3 shows a sample serial transmission flowchart. After SCIF transmission is enabled, use
the following procedure to perform serial data transmission.
Start transmission
(1)
Read TDFE bit in SCSSR
No
TDFE= 1?
Yes
Write transmit data (16 - transmit
trigger set number) to SCFTDR,
read 1 from TDFE bit and TEND flag
in SCSSR, then clear to 0
(2)
No
All data transmitted?
Yes
Read TEND bit in SCSSR2
No
TEND= 1?
Yes (3)
No
Break output?
(1) SCIF status check and transmit data write:
Read serial status register (SCSSR) and
check that the TDFE flag is set to 1, then
write transmit data to the transmit FIFO
data register (SCFTDR), read 1 from the
TDFE and TEND flags, then clear these
flags to 0.
The number of transmit data bytes that can
be written is 64 - (transmit trigger set
number).
(2) Serial transmission continuation procedure:
To continue serial transmission, read 1 from
the TDFE flag to confirm that writing is
possible, then write data to SCFTDR2, and
then clear the TDFE flag to 0.
(3) Break output at the end of serial
transmission:
To output a break in serial transmission, set
the port SC data register (SCPDR) and port
SC control register (SCPCR), then clear the
TE bit to 0 in the serial control register
(SCSCR).
In steps 1 and 2, it is possible to ascertain
the number of data bytes that can be
written from the number of transmit data
bytes in SCFTDR indicated by the upper 8
bits of the FIFO data count set register 2
(SCFDR).
Yes
Set SCPDR2 and SCPCR2
Clear TE bit in SCSCR2 to 0
End of transmission
Figure 18.3
Sample Serial Transmission Flowchart
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Section 18
Serial Communication Interface with FIFO (SCIF)
In serial transmission, the SCIF operates as described below.
1. When data is written into the transmit FIFO data register (SCFTDR), the SCIF transfers the
data from SCFTDR to the transmit shift register (SCTSR) and starts transmitting. Confirm that
the TDFE flag in the serial status register (SCSSR) is set to 1 before writing transmit data to
SCFTDR. The number of data bytes that can be written is (64 – transmit trigger setting).
2. When data is transferred from SCFTDR to SCTSR and transmission is started, consecutive
transmit operations are performed until there is no transmit data left in SCFTDR. When the
number of transmit data bytes in SCFTDR falls below the transmit trigger number set in the
FIFO control register (SCFCR), the TDFE flag is set. If the TIE bit in the serial control register
(SCSR) is set to 1 at this time, a transmit-FIFO-data-empty interrupt request is generated.
When the number of transmit data matches the data set in the transmit data stop register
(SCTDSR) while the transmit data stop function is used, the transmit operation is stopped and
the TSF flag in the serial status register (SCSSR) is set. When the TSIE bit in the serial control
register (SCSCR) is set to 1, transmit data stop interrupt request is generated. A common
interrupt vector is assigned to the transmit-FIFO-data-empty interrupt and the transmit-datastop interrupt.
The serial transmit data is sent from the TxD pin in the following order.
A. Start bit: One-bit 0 is output.
B. Transmit data: 8-bit or 7-bit data is output in LSB-first order.
C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is
not output can also be selected.)
D. Stop bit(s): One- or two-bit 1s (stop bits) are output.
E. Mark state: 1 is output continuously until the start bit that starts the next transmission is
sent.
3. The SCIF checks the SCFTDR transmit data at the timing for sending the stop bit. If data is
present, the data is transferred from SCFTDR to SCTSR, the stop bit is sent, and then serial
transmission of the next frame is started.
If there is no transmit data, the TEND flag in the serial status register (SCSSR) is set to 1, the
stop bit is sent, and then the line goes to the mark state in which 1 is output continuously.
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Section 18
Serial Communication Interface with FIFO (SCIF)
Figure 18.4 shows an example of the operation for transmission in asynchronous mode.
Start
bit
1
Serial
data
0
Parity Stop Start
bit
bit
bit
Data
D0
D1
D7
0/1
1
0
Parity Stop
bit
bit
Data
D0
D1
D7
0/1
1
Idle
state
(mark state)
1
TDFE
TEND
Transmit-FIFOdata-empty
interrupt request
Data written to
Transmit-FIFOSCFTDR and TDFE
data-empty
flag read as 1 then
interrupt request
cleared to 0 by TransmitFIFO-data-empty
interrupt handler
One frame
Figure 18.4 Example of Transmit Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
• Transmit data stop function
When the value of the SCTDSR register and the number of transmit data match, transmit
operation stops. Setting the TSIE bit (interrupt enable bit) allows the generation of an interrupt
and activation of DMAC.
Figure 18.5 shows an example of the operation for transmit data stop function.
Transmit data
TxD
Start
bit
0
Parity Stop
bit
bit
D0
D1
D6
D7
0/1
Start
bit
0
D0
D1
D6
D7
0/1
TSF flag
Figure 18.5
Example of Transmit Data Stop Function
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Section 18
Serial Communication Interface with FIFO (SCIF)
Figure 18.6 shows the transmit data stop function flowchart.
Start of transmission
Set transmit data stop
number in SCTDSR
1
Set TSE and TSIE bits
in SCFCR to 1
Read TSF bit in SCSSR;
if it is 1, clear to 0 after reading
1 from TSF bit
TSF = 1 ?
2
1. Set the transmit data stop number in SCTDSR, then set
the TSE bit in SCFCR to 1.When an interrupt is enabled,
also set the TSIE bit to 1.
2. If the TSF bit in SCSSR is set to 1, clear it to 0 after
reading 1. When transmit data is written to SCFTDR in
this state, transmit operation is started.
3. If the TSF bit is set to 1 (transmit data stop number is
matched with transmit data number), transmit operation
is stopped. If the TSIE bit is set to 1, an interrupt is
generated.
Serial transmission continuation procedure:
Set the TCRST bit in SCFCR to 1, clear transmit count, and
clear the TCRST bit to 0. Then follow steps 1, 2, and 3.
3
No
Yes
End of transmission
Figure 18.6
Transmit Data Stop Function Flowchart
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REJ09B0033-0300
Section 18
(5)
Serial Communication Interface with FIFO (SCIF)
Transmitting and Receiving Data (Serial data reception)
Figures 18.7 and 18.8 show sample serial reception flowcharts. After SCIF reception is enabled,
use the following procedure to perform serial data reception.
Start reception
Read PER and FER
flags in SCSSR
Yes
PER or FER = 1?
Error processing
No
Read RDF flag in SCSSR
No
(1)
(2)
RDF = 1?
Yes
Read receive data in SCFRDR,
and clear RDF flag in
SCSSR to 0
No
All data received?
Yes
(3)
(1) Receive error handling and break
detection:
Read the DR, ER, and BRK flags in
SCSSR2 to identify any error, perform
the appropriate error handling, then
clear the DR, ER, and BRK flags to 0.
In the case of a framing error, a break
can also be detected by reading the
value of the RxD2 pin.
(2) SCIF status check and receive data
read :
Read the serial status register
(SCSSR) and check that RDF = 1, then
read the receive data in the receive
FIFO data register (SCFRDR), read 1
from the RDF flag, and then clear the
RDF flag to 0.
(3) Serial reception continuation
procedure:
To continue serial reception, read at
least the receive trigger set number of
receive data bytes from SCFRDR, read
1 from the RDF flag, then clear the
RDF flag to 0. The number of receive
data bytes in SCFRDR can be
ascertained by reading the lower bits of
SCFDR.
Clear RE bit in SCSCR to 0
End reception
Figure 18.7
Sample Serial Reception Flowchart (1)
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Section 18
Serial Communication Interface with FIFO (SCIF)
1. Whether a framing error or parity error has
occurred in the receive data read from
SCFRDR can be ascertained from the FER and
PER bits in SCSSR.
Error processing
No
ER = 1?
Yes
Receive error processing
No
2. When a break signal is received, receive data
is not transferred to SCFRDR while the BRK
flag is set. However, note that the last data in
SCFRDR is H'00 and the break data in which a
framing error occurred is stored.
BRK= 1?
Break processing
No
DR= 1?
Yes
Read receive data in SCFRDR
Clear DR, ER, BRK flags in
SCSSR to 0
End
Figure 18.8
Sample Serial Reception Flowchart (2)
In serial reception, the SCIF operates as described below.
1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in SCRSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCIF carries out the following checks.
A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only
the first is checked.
B. The SCIF checks whether receive data can be transferred from the receive shift register
(SCRSR) to SCFRDR.
C. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not
set.
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Section 18
Serial Communication Interface with FIFO (SCIF)
If all the above checks are passed, the receive data is stored in SCFRDR.
Note: Even when the receive error (framing error/parity error) is generated, receive operation is
continued.
4. If the RIE bit in SCSCR is set to 1 when the RDF flag changes to 1, a receive-FIFO-data-full
interrupt request is generated.
If the ERIE bit in SCSCR is set to 1 when the ER flag changes to 1, a receive-error interrupt
request is generated.
If the BRIE bit in SCSCR is set to 1 when the BRK flag changes to 1, a break reception
interrupt request is generated.
If the DRIE bit in SCSCR is set to 1 when the DR flag changes to 1, a receive data ready
interrupt request is generated.
Note that a common vector is assigned to each interrupt source.
Figure 18.9 shows an example of the operation for reception.
1
Serial
data
Start
bit
0
Parity Stop Start
bit
bit
bit
Data
D0 D1
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7 0/1
1
1
Idle state
(mark state)
RDF
FER
Receive-FIFO-data-full
interrupt request
One frame
Data read and RDF Receive-error interrupt
flag read as 1 then
request generated
cleared to 0 by
by receive error
receive-FIFO-data-ful
interrupt handler
Figure 18.9 Example of SCIF Receive Operation
(Example with 8-Bit Data, Parity, One Stop Bit)
When modem control is enabled, transmission can be stopped and restarted in accordance with the
CTS input value. When CTS is set to 1, if transmission is in progress, the line goes to the mark
state after transmission of one frame. When CTS is set to 0, the next transmit data is output
starting from the start bit.
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Section 18
Serial Communication Interface with FIFO (SCIF)
Figure 18.10 shows an example of the operation when modem control is used.
Start
bit
Transmit data
TxD
0
Parity Stop
bit
bit
D0
D1
D6
D7
0/1
0
Transmission stops
when CTS goes high
CTS
Figure 18.10
Start
bit
D0
D1
D6
D7
0/1
Transmission starts again
when CTS goes low
Example of CTS Control Operation
When modem control is enabled, the RTS signal goes high after the number of receive FIFO
(SCFRDR) has exceeded the number of RTS output triggers.
Start
bit
Transmit data
TxD
0
Parity Stop
bit
bit
D0
D1
D6
D7
0/1
RTS
RTS goes high when receive data is
at least number of RTS output trigger
Figure 18.11
18.4.3
RTS goes low when receive data is
less than number of RTS output trigger
Example of RTS Control Operation
Synchronous Mode
Operation in synchronous mode is described below.
The SCIF has 64-stage FIFO buffers for both transmission and reception, reducing the CPU
overhead and enabling fast, continuous communication to be performed.
The operating clock source is selected using the serial mode register (SCSMR). The SCIF clock
source is determined by the CKE1 and CKE0 bits in the serial control register (SCSCR).
• Transmit/receive format: Fixed 8-bit data
• Indication of the number of data bytes stored in the transmit and receive FIFO registers
• Internal clock or external clock used as the SCIF clock source
When the internal clock is selected:
The SCIF operates on the baud rate generator clock and outputs a serial clock from SCK pin.
Rev. 3.00 Jan. 18, 2008 Page 624 of 1458
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Section 18
Serial Communication Interface with FIFO (SCIF)
When the external clock is selected:
The SCIF operates on the external clock input through the SCK pin.
18.4.4
Serial Operation in Synchronous Mode
One unit of transfer data (character or frame)
*
*
Serial clock
LSB
Serial data don't care
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
don't care
Note: * High in continuous transmission/reception
Figure 18.12
Data Format in Synchronous Communication
In synchronous serial communication, data on the communication line is output from a falling
edge of the serial clock to the next falling edge. Data is guaranteed valid at the rising edge of the
serial clock.
In serial communication, each character is output starting with the LSB and ending with the MSB.
After the MSB is output, the communication line remains in the state of the MSB.
In synchronous mode, the SCIF receives data in synchronization with the rising edge of the serial
clock.
(1)
Data Transfer Format
A fixed 8-bit data format is used. No parity or multiprocessor bits are added.
(2)
Clock
An internal clock generated by the on-chip baud rate generator or an external clock input through
the SCK pin can be selected as the serial clock for the SCIF, according to the setting of the CKE1
and CKE0 bits in SCSCR.
Eight serial clock pulses are output in the transfer of one character, and when no
transmission/reception is performed, the clock is fixed high. However, when the operation mode is
reception only, the synchronous clock output continues while the RE bit is set to 1. To fix the
clock high every time one character is transferred, write to the transmit FIFO data register
(SCFTDR) the same number of dummy data bytes as the data bytes to be received and set the TE
and RE bits to 1 at the same time to transmit the dummy data. When the specified number of data
bytes are transmitted, the clock is fixed high.
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Section 18
(3)
Serial Communication Interface with FIFO (SCIF)
Data Transfer Operations (SCIF Initialization)
Before transmitting and receiving data, it is necessary to clear the TE and RE bits in SCSCR to 0,
then initialize the SCIF as described below.
When the clock source, etc., is changed, the TE and RE bits must be cleared to 0 before making
the change using the following procedure. When the TE bit is cleared to 0, the transmit shift
register (SCTSR) is initialized. Note that clearing the TE and RE bits to 0 does not change the
contents of SCSSR, SCFTDR, or SCFRDR. The TE bit should be cleared to 0 after all transmit
data has been sent and the TEND bit in SCSSR has been set to 1. The TE bit should not be cleared
to 0 during transmission; if attempted, the TxD pin will go to the high-impedance state. Before
setting TE to 1 again to start transmission, the TFRST bit in SCFCR should first be set to 1 to reset
SCFTDR.
Figure 18.13 shows sample SCIF initialization flowcharts.
Initialization
1. Be sure to set the TFRST bit in
SCFCR to 1, to reset the FIFOs.
Clear TE and RE bits in SCSCR to 0
Set TFRST bit in SCFCR to 1
1
Set CKE1 and CKE0 bits in SCSCR
(leaving TE and RE bits cleared to 0) 2
Set C/A bit in SCSMR to 1
Set CKS1 and CKS0 bits
3
Set value in SCBRR
4
Clear TFRST bit to 0
5
2. Set the clock selection in SCSCR.
Be sure to clear bits RIE, TIE, TE,
and RE to 0.
3. Set the clock source selection in
SCSMR.
4. Write a value corresponding to the
bit rate into SCBRR.
5. Clear the TFRST bit in SCFCR to 0.
Set transmit trigger number in TTRG1
and TTRG0 in SCFCR, write transmit
data exceeding transmit trigger setting 6
number, and clear TDFE flag to 0 after
reading 1 from it
6. Set the transmit trigger number,
write transmit data exceeding the
transmit trigger setting number, and
clear the TDFE flag to 0 after reading
it.
7. Wait one bit interval.
Wait
1-bit interval elapsed?
7
No
Yes
End
Figure 18.13
Sample SCIF Initialization Flowchart (1) (Transmission)
Rev. 3.00 Jan. 18, 2008 Page 626 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Initialization
1. Be sure to set the RFRST bit in
SCFCR to 1, to reset the FIFOs.
Clear TE and RE bits in SCSCR to 0
Set RFRST bit in SCFCR to 1
1
Set CKE1 and CKE0 bits in SCSCR
(leaving TE and RE bits cleared to 0)
2
Set C/A bit in SCSMR to 1
Set CKS1 and CKS0 bits
3
Set value in SCBRR
4
Clear RFRST bit to 0
5
2. Set the clock selection in SCSCR.
Be sure to clear bits RIE, TIE, TE,
and RE to 0.
3. Set the clock source selection in
SCSMR.
4. Write a value corresponding to the
bit rate into SCBRR.
5. Clear the RFRST bit in SCFCR to 0.
6. Wait one bit interval.
Wait
1-bit interval elapsed?
6
No
Yes
End
Figure 18.13
Sample SCIF Initialization Flowchart (2) (Reception)
Rev. 3.00 Jan. 18, 2008 Page 627 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Initialization
Clear TE and RE bits in SCSCR to 0
Set TFRST and RFRST bits in
SCFCR to 1
1. Be sure to set the TFRST bit in
SCFCR to 1, to reset the FIFOs.
1
Set CKE1 and CKE0 bits in SCSCR
(leaving TE and RE bits cleared to 0) 2
Set C/A bit in SCSMR to 1
Set CKS1 and CKS0 bits
3
Set value in SCBRR
4
Clear TFRST and RFRST bits to 0
5
Set transmit trigger number in TTRG1
and TTRG0 in SCFCR, write transmit
6
data exceeding transmit trigger
setting number, and clear TDFE
flag to 0 after reading 1 from it
2. Set the clock selection in SCSCR.
Be sure to clear bits RIE, TIE, TE,
and RE to 0.
3. Set the clock source selection in
SCSMR.
4. Write a value corresponding to the
bit rate into SCBRR.
5. Clear the TFRST and RFRST bits in
SCFCR to 0.
6. Set the transmit trigger number, write
transmit data exceeding the transmit
trigger setting number, and clear the
TDFE flag to 0 after reading it.
7. Wait one bit interval.
Wait
1-bit interval elapsed?
7
No
Yes
End
Figure 18.13 Sample SCIF Initialization Flowchart (3)
(Simultaneous Transmission and Reception)
Rev. 3.00 Jan. 18, 2008 Page 628 of 1458
REJ09B0033-0300
Section 18
(4)
Serial Communication Interface with FIFO (SCIF)
Data Transfer Operations (Serial Data Transmission)
Figure 18.14 shows sample flowcharts for serial transmission.
Start of transmission
Write remaining transmit data to SCFTDR 1
Set TE bit in SCSCR
When using transmit FIFO data interrupt, 2
set TIE bit to 1
TEND =1?
1. Write the remaining transmit
data to SCFTDR.
2. Transmission is started when
the TE bit in SCSCR is set to 1.
3. After the end of transmission,
clear the TE bit to 0.
No
Yes
Clear TE bit in SCSCR to 0
3
End of transmission
Figure 18.14 Sample Serial Transmission Flowchart (1)
(First Transmission after Initialization)
Rev. 3.00 Jan. 18, 2008 Page 629 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Start of transmission
Set transmit trigger number in TTRG1 1
and TTRG0 in SCFCR
Write transmit data exceeding transmit
trigger setting number, and clear
2
TDFE flag to 0 after reading 1 from it
Wait
3
1-bit interval elapsed?
No
TEND =1?
2. Write transmit data to SCFTDR,
and clear the TDFE flag to 0 after
reading 1 from it.
3. Wait for one bit interval.
4. Transmission is started when the
TE bit in SCSCR is set to 1.
Yes
Set TE bit in SCSCR
When using transmit FIFO data
interrupt, set TIE bit to 1
1. Set the transmit trigger number
in SCFCR.
4
5. After the end of transmission, clear
the TE bit to 0.
No
Yes
Clear TE bit in SCSCR to 0
5
End of transmission
Figure 18.14 Sample Serial Transmission Flowchart (2)
(Second and Subsequent Transmission)
Rev. 3.00 Jan. 18, 2008 Page 630 of 1458
REJ09B0033-0300
Section 18
(5)
Serial Communication Interface with FIFO (SCIF)
Data Transfer Operations (Serial Data Reception)
Figure 18.15 shows sample flowcharts for serial reception.
Start of reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR
1
Set RE bit in SCSCR
When using receive FIFO data interrupt, 2
set RIE bit to 1
1. Set the receive trigger number
in SCFCR.
2. Reception is started when the
RE bit in SCSCR is set to 1.
3. Read receive data while the
RDF bit is 1.
RDF =1?
No
4. After the end of reception, clear
the RE bit to 0.
Yes
Read receive trigger number of receive 3
data bytes from SCFRDR
Clear RE bit in SCSCR to 0
4
End of reception
Figure 18.15 Sample Serial Reception Flowchart (1)
(First Reception after Initialization)
Rev. 3.00 Jan. 18, 2008 Page 631 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Start of reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR
Set RFRST bit in SCFCR to 1
1
1. Set the receive trigger number
in SCFCR.
2
2. Reset the receive FIFO.
3. Wait for one bit interval.
Clear RFRST bit in SCFCR to 0
Wait
1-bit interval elapsed?
4. Reception is started when the RE
bit in SCSCR is set to 1.
3
No
Yes
5. Read receive data while the RDF
bit is 1.
6. After the end of reception, clear the
RE bit to 0.
Set RE bit in SCSCR
When using receive FIFO data interrupt, 4
set RIE bit to 1
RDF =1?
No
Yes
Read receive trigger number of receive
5
data bytes from SCFRDR
Clear RE bit in SCSCR to 0
6
End of reception
Figure 18.15 Sample Serial Reception Flowchart (2)
(Second and Subsequent Reception)
Rev. 3.00 Jan. 18, 2008 Page 632 of 1458
REJ09B0033-0300
Section 18
(6)
Serial Communication Interface with FIFO (SCIF)
Data Transfer Operations (Simultaneous Serial Data Transmission and Reception)
Figure 18.16 shows sample flowcharts for simultaneous serial transmission and reception.
Start of simultaneous
transmission/reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR
1
1. Set the receive trigger number
in SCFCR.
Write remaining transmit data to SCFTDR 2
Read TDFE and RDF bits in SCSSR
TDFE =1?
RDF =1?
No
2. Write the remaining transmit data
to SCFTDR, and if there is receive
data in the FIFO, read receive data
until there is less than the receive
trigger setting number, read the
TDFE and RDF bits in SCSSR, and
if 1, clear to 0.
3. Transmission/reception is started
when the TE and RE bits in SCSCR
are set to 1. The TE and RE bits
must be set simultaneously.
Yes
Write 0 to TDFE and RDF bits in
SCSSR after reading 1 from them
4. After the end of transmission/reception,
clear the TE and RE bits to 0.
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data interrupt,
3
set TIE bit to 1
When using receive FIFO data interrupt,
set RIE bit to 1
TDFE =1?
RDF =1?
No
Yes
Read receive trigger number of receive
data bytes from SCFRDR
Clear TE and RE bits in SCSCR to 0
4
End of
transmission/reception
Figure 18.16
Sample Simultaneous Serial Transmission and Reception Flowchart (1)
(First Transfer after Initialization)
Rev. 3.00 Jan. 18, 2008 Page 633 of 1458
REJ09B0033-0300
Section 18
Serial Communication Interface with FIFO (SCIF)
Start of simultaneous
transmission/reception
Set receive trigger number in RTRG1
and RTRG0 in SCFCR, and set transmit 1
trigger number in TTRG1 and TTRG0
Set TFRST and RFRST bits in
SCFCR to 1
2
2. Reset the receive FIFO and transmit
FIFO.
3
3. Write transmit data to SCFTDR, and
if there is receive data in the FIFO,
read receive data until there is less
than the receive trigger setting number,
read the TDFE and RDF bits in SCSSR,
and if 1, clear to 0.
Clear TFRST and RFRST bits in
SCFCR to 0
Write transmit data to SCFTDR
4. Wait for one bit interval.
Read TDFE and RDF bits in SCSSR
TDFE =1?
RDF =1?
1. Set the receive trigger number and
transmit trigger number in SCFCR.
5. Transmission/reception is started when
the TE and RE bits in SCSCR are set
to 1. The TE and RE bits must be set
simultaneously.
No
Yes
6. After the end of transmission/reception,
clear the TE and RE bits to 0.
Write 0 to TDFE and RDF bits in
SCSSR after reading 1 from them
Wait
4
1-bit interval elapsed?
No
Yes
Set TE and RE bits in SCSCR
simultaneously
When using transmit FIFO data
interrupt, set TIE bit to 1
When using receive FIFO data
interrupt, set RIE bit to 1
TDFE =1?
RDF =1?
5
No
Yes
Read receive trigger number of
receive data bytes from SCFRDR
Clear TE and RE bits in SCSCR to 0
6
End of
transmi