LM2622
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SNVS068E – MAY 2000 – REVISED MARCH 2013
LM2622 600kHz/1.3MHz Step-up PWM DC/DC Converter
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FEATURES
DESCRIPTION
•
•
•
The LM2622 is a step-up DC/DC converter with a
1.6A, 0.2Ω internal switch and pin selectable
operating frequency. With the ability to convert 3.3V
to multiple outputs of 8V, -8V, and 23V, the LM2622
is an ideal part for biasing TFT displays. The LM2622
can be operated at switching frequencies of 600kHz
and 1.3MHz allowing for easy filtering and low noise.
An external compensation pin gives the user flexibility
in setting frequency compensation, which makes
possible the use of small, low ESR ceramic
capacitors at the output. The LM2622 is available in a
low profile 8-lead VSSOP package.
1
2
•
•
1.6A, 0.2Ω, Internal Switch
Operating Voltage as Low as 2.0V
600kHz/1.3MHz Pin Selectable Frequency
Operation
Over Temperature Protection
8-Lead VSSOP Package
APPLICATIONS
•
•
•
•
•
TFT Bias Supplies
Handheld Devices
Portable Applications
GSM/CDMA Phones
Digital Cameras
Typical Application Circuit
L
10uH
2.7V - 3.3V
D
5
6
SW
VIN
FSLCT
7
RFB!
40.2k
LM2622
Battery or
Power
Source
3
CIN
22UF
FB
SHDN
VC
2
8V
GND
1
4
RC
24k
RFB2
7.5k
COUT
22uF
CC
2.2nF
Figure 1. 600 kHz Operation
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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LM2622
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Connection Diagram
1
8
VC
NC
FB
FSLCT
2
7
3
SHDN
VIN
GND
SW
4
6
5
Figure 2. Top View
8-Lead Plastic VSSOP
See DGK Package
Pin Description
2
Pin
Name
1
VC
Compensation network connection. Connected to the output of the voltage error amplifier.
Function
2
FB
Output voltage feedback input.
3
SHDN
4
GND
Analog and power ground.
5
SW
Power switch input. Switch connected between SW pin and GND pin.
6
VIN
Analog power input.
7
FSLCT
8
NC
Shutdown control input, active low.
Switching frequency select input. VIN = 1.3MHz. Ground = 600kHz.
Connect to ground or leave open. Connect to GND pin directly beneath the device if possible. If
other traces are in the way or it is otherwise not possible to directly connect it to GND leave this pin
open and shield it from sources of EMI.
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Block Diagram
FSLCT
¦
85% Duty
Cycle Limit
Oscillator
Load Current
Measurement
SW
+
PWM
COMP
-
-
FB
BG
Set
Reset
Reset
Drive
Driver
LOGIC
ERROR
AMP
OVP
+
BG
Thermal
UVP
SD
OVP
COMP
+
BG
+
Internal
Supply
Thermal
Shutdown
Bandgap Voltage
Reference
VC
Shutdown
Comparator
SHDN
UVP
COMP
VIN
GND
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
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(1) (2)
Absolute Maximum Ratings
VIN
12V
SW Voltage
18V
FB Voltage
7V
VC Voltage
7V
SHDN Voltage
7V
FSLCT
12V
Maximum Junction Temperature
Power Dissipation
150°C
(3)
Internally Limited
Lead Temperature
300°C
Vapor Phase (60 sec.)
215°C
Infrared (15 sec.)
220°C
ESD Susceptibility
(4)
Human Body Model
2kV
Machine Model
(1)
200V
Absolute maximum ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions for which the
device is intended to be functional, but device parameter specifications may not be ensured. For ensured specifications and test
conditions, see the Electrical Characteristics.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
The maximum allowable power dissipation is a function of the maximum junction temperature, TJ(MAX), the junction-to-ambient thermal
resistance, θJA, and the ambient temperature, TA. See the Electrical Characteristics table for the thermal resistance of various layouts.
The maximum allowable power dissipation at any ambient temperature is calculated using: PD (MAX) = (TJ(MAX) − TA)/θJA. Exceeding
the maximum allowable power dissipation will cause excessive die temperature, and the regulator will go into thermal shutdown.
The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin. The machine model is a 200pF
capacitor discharged directly into each pin.
(2)
(3)
(4)
Operating Conditions
Operating Junction Temperature Range
(1)
−40°C to +125°C
−65°C to +150°C
Storage Temperature
Supply Voltage
(1)
2V to 12V
All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Electrical Characteristics
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ = −40°C to +125°C)Unless otherwise specified. VIN =2.0V and IL = 0A, unless otherwise specified.
Symbol
IQ
Parameter
Quiescent Current
Min
Typ
Max
(1)
Units
1.3
2.0
mA
5
10
µA
1.2285
1.26
1.2915
V
1.0
1.65
2.3
Conditions
(1)
(2)
FB = 0V (Not Switching)
VSHDN = 0V
VFB
ICL
Feedback Voltage
(3)
(4)
Switch Current Limit
VIN = 2.7V
ΔVO/ΔILOAD
Load Regulation
VIN = 3.3V
%VFB/ΔVIN
Feedback Voltage Line
Regulation
2.0V ≤ VIN ≤ 12.0V
IB
FB Pin Bias Current
(1)
(2)
(3)
(4)
(5)
4
(5)
6.7
A
mV/A
0.013
0.1
%/V
0.5
20
nA
All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
Typical numbers are at 25°C and represent the most likely norm.
Duty cycle affects current limit due to ramp generator.
Current limit at 0% duty cycle. See Typical Performance Characteristics section for Switch Current Limit vs. VIN
Bias current flows into FB pin.
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Electrical Characteristics (continued)
Specifications in standard type face are for TJ = 25°C and those with boldface type apply over the full Operating
Temperature Range ( TJ = −40°C to +125°C)Unless otherwise specified. VIN =2.0V and IL = 0A, unless otherwise specified.
Symbol
Parameter
VIN
Input Voltage Range
gm
Error Amp Transconductance
AV
Error Amp Voltage Gain
DMAX
Maximum Duty Cycle
fS
Switching Frequency
Conditions
Min
(1)
Typ
Max
12
V
135
290
µmho
(2)
2
ΔI = 5µA
40
78
FSLCT = Ground
(1)
Units
135
V/V
85
%
480
600
720
kHz
1
1.25
1.5
MHz
VSHDN = VIN
0.01
0.1
µA
-1
FSLCT = VIN
ISHDN
Shutdown Pin Current
VSHDN = 0V
−0.5
IL
Switch Leakage Current
VSW = 18V
0.01
3
µA
RDSON
Switch RDSON
VIN = 2.7V, ISW = 1A
0.2
0.4
Ω
ThSHDN
SHDN Threshold
Output High
0.9
Output Low
UVP
θJA
0.6
V
0.6
0.3
V
On Threshold
1.8
1.92
2.0
V
Off Threshold
1.7
1.82
1.9
V
Thermal Resistance
(6)
235
Junction to Ambient (7)
225
Junction to Ambient (8)
220
(9)
200
Junction to Ambient
Junction to Ambient
Junction to Ambient (10)
°C/W
195
(6)
Junction to ambient thermal resistance (no external heat sink) for the VSSOP package with minimal trace widths (0.010 inches) from the
pins to the circuit. See "Scenario 'A'" in the Power Dissipation section.
(7) Junction to ambient thermal resistance for the VSSOP package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.0191 sq. in. of copper heat sinking. See "Scenario 'B'" in the Power Dissipation section.
(8) Junction to ambient thermal resistance for the VSSOP package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.0465 sq. in. of copper heat sinking. See "Scenario 'C'" in the Power Dissipation section.
(9) Junction to ambient thermal resistance for the VSSOP package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.2523 sq. in. of copper heat sinking. See "Scenario 'D'" in the Power Dissipation section.
(10) Junction to ambient thermal resistance for the VSSOP package with minimal trace widths (0.010 inches) from the pins to the circuit and
approximately 0.0098 sq. in. of copper heat sinking on the top layer and 0.0760 sq. in. of copper heat sinking on the bottom layer, with
three 0.020 in. vias connecting the planes. See "Scenario 'E'" in the Power Dissipation section.
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Typical Performance Characteristics
6
Efficiency
vs.
Load Current
(VOUT = 8V, fS = 600 kHz)
Efficiency
vs.
Load Current
(VOUT = 8V, fS = 1.3 MHz)
Figure 3.
Figure 4.
Switch Current Limit
vs.
Temperature
(VIN = 3.3V, VOUT = 8V)
Switch Current Limit
vs.
VIN
Figure 5.
Figure 6.
RDSON
vs.
VIN
(ISW = 1A)
IQ
vs.
VIN
(600 kHz, not switching)
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
IQ
vs.
VIN
(600 kHz, switching)
IQ
vs.
VIN
(1.3 MHz, not switching)
Figure 9.
Figure 10.
IQ
vs.
VIN
(1.3 MHz, switching)
IQ
vs.
VIN
(In shutdown)
Figure 11.
Figure 12.
Frequency
vs.
VIN
(600 kHz)
Frequency
vs.
VIN
(1.3 MHz)
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
Load Transient Response
(600 kHz operation)
Test circuit is shown in Figure 20.
Figure 15.
8
Load Transient Response
(1.3 MHz operation)
Test circuit is shown in Figure 21
Figure 16.
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OPERATION
L
D
COUT
VIN
RLOAD
PWM
L
X
+
+
L
COUT
VIN
RLOAD
V IN
COUT
R LOAD
V OUT
V OUT
-
-
Cycle 1
(a)
Cycle 2
(b)
(a) First Cycle of Operation
(b) Second Cycle Of Operation
Figure 17. Simplified Boost Converter Diagram
CONTINUOUS CONDUCTION MODE
The LM2622 is a current-mode, PWM boost regulator. A boost regulator steps the input voltage up to a higher
output voltage. In continuous conduction mode (when the inductor current never reaches zero at steady state),
the boost regulator operates in two cycles.
In the first cycle of operation, shown in Figure 17 (a), the transistor is closed and the diode is reverse biased.
Energy is collected in the inductor and the load current is supplied by COUT.
The second cycle is shown in Figure 17 (b). During this cycle, the transistor is open and the diode is forward
biased. The energy stored in the inductor is transferred to the load and output capacitor.
The ratio of these two cycles determines the output voltage. The output voltage is defined approximately as:
VOUT =
VIN
1-D
, D' = (1-D) =
VIN
VOUT
where
•
•
D is the duty cycle of the switch
D and D′ will be required for design calculations
(1)
SETTING THE OUTPUT VOLTAGE
The output voltage is set using the feedback pin and a resistor divider connected to the output as shown in the
typical operating circuit. The feedback pin voltage is 1.26V, so the ratio of the feedback resistors sets the output
voltage according to the following equation:
VOUT - 1.26
:
RFB1 = RFB2 x
1.26
(2)
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INTRODUCTION TO COMPENSATION
IL (A)
VIN VOUT
L
VIN
L
'i L
IL_AVG
t (s)
D*Ts
Ts
(a)
ID (A)
VIN VOUT
L
ID_AVG
=IOUT_AVG
t (s)
D*Ts
Ts
(b)
(a) Inductor current
(b) Diode current
Figure 18.
The LM2622 is a current mode PWM boost converter. The signal flow of this control scheme has two feedback
loops, one that senses switch current and one that senses output voltage.
To keep a current programmed control converter stable above duty cycles of 50%, the inductor must meet
certain criteria. The inductor, along with input and output voltage, will determine the slope of the current through
the inductor (see Figure 18 (a)). If the slope of the inductor current is too great, the circuit will be unstable above
duty cycles of 50%. A 10µH inductor is recommended for most 600 kHz applications, while a 4.7µH inductor may
be used for most 1.25 MHz applications. If the duty cycle is approaching the maximum of 85%, it may be
necessary to increase the inductance by as much as 2X. See INDUCTOR AND DIODE SELECTION for more
detailed inductor sizing.
The LM2622 provides a compensation pin (VC) to customize the voltage loop feedback. It is recommended that a
series combination of RC and CC be used for the compensation network, as shown in the typical application
circuit. For any given application, there exists a unique combination of RC and CC that will optimize the
performance of the LM2622 circuit in terms of its transient response. The series combination of RC and CC
introduces a pole-zero pair according to the following equations:
10
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fZC =
fPC =
SNVS068E – MAY 2000 – REVISED MARCH 2013
1
Hz
2SRCCC
(3)
1
Hz
2S(RC + RO)CC
where
•
RO is the output impedance of the error amplifier, approximately 1MegΩ
(4)
For most applications, performance can be optimized by choosing values within the range 5kΩ ≤ RC ≤ 20kΩ (RC
can be up to 200kΩ if CC2 is used, see HIGH OUTPUT CAPACITOR ESR COMPENSATION) and 680pF ≤ CC ≤
4.7nF. Refer to the Application Information section for recommended values for specific circuits and conditions.
Refer to the COMPENSATION section for other design requirement.
COMPENSATION
This section will present a general design procedure to help insure a stable and operational circuit. The designs
in this datasheet are optimized for particular requirements. If different conversions are required, some of the
components may need to be changed to ensure stability. Below is a set of general guidelines in designing a
stable circuit for continuous conduction operation (loads greater than approximately 75mA), in most all cases this
will provide for stability during discontinuous operation as well. The power components and their effects will be
determined first, then the compensation components will be chosen to produce stability.
INDUCTOR AND DIODE SELECTION
Although the inductor sizes mentioned earlier are fine for most applications, a more exact value can be
calculated. To ensure stability at duty cycles above 50%, the inductor must have some minimum value
determined by the minimum input voltage and the maximum output voltage. This equation is:
2
L>
VINRDSON
0.144 fs
( DD') -1
( DD') +1
(in H)
where
•
•
•
fs is the switching frequency
D is the duty cycle
RDSON is the ON resistance of the internal switch taken from the graph "RDSON vs. VIN" in the Typical
Performance Characteristics section
(5)
This equation is only good for duty cycles greater than 50% (D>0.5), for duty cycles less than 50% the
recommended values may be used. The corresponding inductor current ripple as shown in Figure 18 (a) is given
by:
'iL =
VIND
2Lfs
(in Amps)
(6)
The inductor ripple current is important for a few reasons. One reason is because the peak switch current will be
the average inductor current (input current or ILOAD/D') plus ΔiL. As a side note, discontinuous operation occurs
when the inductor current falls to zero during a switching cycle, or ΔiL is greater than the average inductor
current. Therefore, continuous conduction mode occurs when ΔiL is less than the average inductor current. Care
must be taken to make sure that the switch will not reach its current limit during normal operation. The inductor
must also be sized accordingly. It should have a saturation current rating higher than the peak inductor current
expected. The output voltage ripple is also affected by the total ripple current.
The output diode for a boost regulator must be chosen correctly depending on the output voltage and the output
current. The typical current waveform for the diode in continuous conduction mode is shown in Figure 18 (b). The
diode must be rated for a reverse voltage equal to or greater than the output voltage used. The average current
rating must be greater than the maximum load current expected, and the peak current rating must be greater
than the peak inductor current. During short circuit testing, or if short circuit conditions are possible in the
application, the diode current rating must exceed the switch current limit. Using Schottky diodes with lower
forward voltage drop will decrease power dissipation and increase efficiency.
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DC GAIN AND OPEN-LOOP GAIN
Since the control stage of the converter forms a complete feedback loop with the power components, it forms a
closed-loop system that must be stabilized to avoid positive feedback and instability. A value for open-loop DC
gain will be required, from which you can calculate, or place, poles and zeros to determine the crossover
frequency and the phase margin. A high phase margin (greater than 45°) is desired for the best stability and
transient response. For the purpose of stabilizing the LM2622, choosing a crossover point well below where the
right half plane zero is located will ensure sufficient phase margin. A discussion of the right half plane zero and
checking the crossover using the DC gain will follow.
INPUT AND OUTPUT CAPACITOR SELECTION
The switching action of a boost regulator causes a triangular voltage waveform at the input. A capacitor is
required to reduce the input ripple and noise for proper operation of the regulator. The size used is dependant on
the application and board layout. If the regulator will be loaded uniformly, with very little load changes, and at
lower current outputs, the input capacitor size can often be reduced. The size can also be reduced if the input of
the regulator is very close to the source output. The size will generally need to be larger for applications where
the regulator is supplying nearly the maximum rated output or if large load steps are expected. A minimum value
of 10µF should be used for the less stressful condtions while a 22µF to 47µF capacitor may be required for
higher power and dynamic loads. Larger values and/or lower ESR may be needed if the application requires very
low ripple on the input source voltage.
The choice of output capacitors is also somewhat arbitrary and depends on the design requirements for output
voltage ripple. It is recommended that low ESR (Equivalent Series Resistance, denoted RESR) capacitors be used
such as ceramic, polymer electrolytic, or low ESR tantalum. Higher ESR capacitors may be used but will require
more compensation which will be explained later on in the section. The ESR is also important because it
determines the peak to peak output voltage ripple according to the approximate equation:
ΔVOUT ≊ 2ΔiLRESR (in Volts)
(7)
A minimum value of 10µF is recommended and may be increased to a larger value. After choosing the output
capacitor you can determine a pole-zero pair introduced into the control loop by the following equations:
fP1 =
1
(in Hz)
2S(RESR + RL)COUT
where
•
fZ1 =
RL is the minimum load resistance corresponding to the maximum load current
1
2SRESRCOUT
(8)
(in Hz)
(9)
The zero created by the ESR of the output capacitor is generally very high frequency if the ESR is small. If low
ESR capacitors are used it can be neglected. If higher ESR capacitors are used see the HIGH OUTPUT
CAPACITOR ESR COMPENSATION section.
RIGHT HALF PLANE ZERO
A current mode control boost regulator has an inherent right half plane zero (RHP zero). This zero has the effect
of a zero in the gain plot, causing an imposed +20dB/decade on the rolloff, but has the effect of a pole in the
phase, subtracting another 90° in the phase plot. This can cause undesirable effects if the control loop is
influenced by this zero. To ensure the RHP zero does not cause instability issues, the control loop should be
designed to have a bandwidth of less than ½ the frequency of the RHP zero. This zero occurs at a frequency of:
RHPzero =
VOUT(D')2
(in Hz)
2S,LOADL
where
•
12
ILOAD is the maximum load current
(10)
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SELECTING THE COMPENSATION COMPONENTS
The first step in selecting the compensation components RC and CC is to set a dominant low frequency pole in
the control loop. Simply choose values for RC and CC within the ranges given in the INTRODUCTION TO
COMPENSATION section to set this pole in the area of 10Hz to 500Hz. The frequency of the pole created is
determined by the equation:
fPC =
1
(in Hz)
2S(RC + RO)CC
where
•
RO is the output impedance of the error amplifier, approximately 1MegΩ
(11)
Since RC is generally much less than RO, it does not have much effect on the above equation and can be
neglected until a value is chosen to set the zero fZC. fZC is created to cancel out the pole created by the output
capacitor, fP1. The output capacitor pole will shift with different load currents as shown by the equation, so setting
the zero is not exact. Determine the range of fP1 over the expected loads and then set the zero fZC to a point
approximately in the middle. The frequency of this zero is determined by:
fZC =
1
(in Hz)
2SCCRC
(12)
Now RC can be chosen with the selected value for CC. Check to make sure that the pole fPC is still in the 10Hz to
500Hz range, change each value slightly if needed to ensure both component values are in the recommended
range. After checking the design at the end of this section, these values can be changed a little more to optimize
performance if desired. This is best done in the lab on a bench, checking the load step response with different
values until the ringing and overshoot on the output voltage at the edge of the load steps is minimal. This should
produce a stable, high performance circuit. For improved transient response, higher values of RC should be
chosen. This will improve the overall bandwidth which makes the regulator respond more quickly to transients. If
more detail is required, or the most optimal performance is desired, refer to a more in depth discussion of
compensating current mode DC/DC switching regulators.
HIGH OUTPUT CAPACITOR ESR COMPENSATION
When using an output capacitor with a high ESR value, or just to improve the overall phase margin of the control
loop, another pole may be introduced to cancel the zero created by the ESR. This is accomplished by adding
another capacitor, CC2, directly from the compensation pin VC to ground, in parallel with the series combination of
RC and CC. The pole should be placed at the same frequency as fZ1, the ESR zero. The equation for this pole
follows:
fPC2 =
1
(in Hz)
2SCC2(RC //RO)
(13)
To ensure this equation is valid, and that CC2 can be used without negatively impacting the effects of RC and CC,
fPC2 must be greater than 10fZC.
CHECKING THE DESIGN
The final step is to check the design. This is to ensure a bandwidth of ½ or less of the frequency of the RHP
zero. This is done by calculating the open-loop DC gain, ADC. After this value is known, you can calculate the
crossover visually by placing a −20dB/decade slope at each pole, and a +20dB/decade slope for each zero. The
point at which the gain plot crosses unity gain, or 0dB, is the crossover frequency. If the crossover frequency is
less than ½ the RHP zero, the phase margin should be high enough for stability. The phase margin can also be
improved by adding CC2 as discussed earlier in the section. The equation for ADC is given below with additional
equations required for the calculation:
ADC(DB) = 20log10
(R
RFB2
FB1 + RFB2
gmROD'
)R
{[(ZcLeff)// RL]//RL} (in dB)
DSON
where
•
•
2fs
Zc #
nD'
RL is the minimum load resistance
gm is the error amplifier transconductance found in the Electrical Characteristics table
(in rad/s)
(14)
(15)
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L
(D')2
Leff =
(16)
2mc
(no unit)
n = 1+
m1
(17)
(18)
mc ≊ 0.072fs (in V/s)
m1 #
VINRDSON
L
(in V/s)
where
•
•
VIN is the minimum input voltage
RDSON is the value chosen from the graph "RDSON vs. VIN " in the Typical Performance Characteristics
section
(19)
LAYOUT CONSIDERATIONS
The input bypass capacitor CIN, as shown in the typical operating circuit, must be placed close to the IC. This will
reduce copper trace resistance which effects input voltage ripple of the IC. For additional input voltage filtering, a
100nF bypass capacitor can be placed in parallel with CIN, close to the VIN pin, to shunt any high frequency noise
to ground. The output capacitor, COUT, should also be placed close to the IC. Any copper trace connections for
the COUT capacitor can increase the series resistance, which directly effects output voltage ripple. The feedback
network, resistors RFB1 and RFB2, should be kept close to the FB pin, and away from the inductor, to minimize
copper trace connections that can inject noise into the system. Trace connections made to the inductor and
schottky diode should be minimized to reduce power dissipation and increase overall efficiency. For more detail
on switching power supply layout considerations see Application Note AN-1149: Layout Guidelines for Switching
Power Supplies (SNVA021).
14
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Application Information
D5
D4
C5
1uF
C4
1uF
VIN = 2.7V - 3.3V
D6
L
10uH
23V
D7
C6
1uF
C7
1uF
C1
4.7uF
D1
D3
D2
-8V
C2
0.1uF
5
SW
7
6
VIN
FSLCT
CFB1
0.1uF
LM2622
RFB1
40.2k
8V
2
3
FB
SHDN
VC
GND
1
CIN
10uF
4
RC
5.1k
RFB2
7.5k
CFB2*
COUT1
10uF
COUT2
10uF
CC
3.9nF
Figure 19. Triple Output TFT Bias (600 kHz operation)
TRIPLE OUTPUT TFT BIAS
The circuit in Figure 19 shows how the LM2622 can be configured to provide outputs of 8V, −8V, and 23V,
convenient for biasing TFT displays. The 8V output is regulated, while the −8V and 23V outputs are unregulated.
The 8V output is generated by a typical boost topology. The basic operation of the boost converter is described
in the OPERATION section. The output voltage is set with RFB1 and RFB2 by:
R FB1
R FB2
VOUT 1.26
:
1.26
(20)
CFB is placed across RFB1 to act as a pseudo soft-start. The compensation network of RC and CC are chosen to
optimally stabilize the converter. The inductor also affects the stability. When operating at 600 kHz, a 10uH
inductor is recommended to insure the converter is stable at duty cycles greater than 50%. Refer to the
COMPENSATION section for more information.
The -8V output is derived from a diode inverter. During the second cycle, when the transistor is open, D2
conducts and C1 charges to 8V minus a diode drop (≊0.4V if using a Schottky). When the transistor opens in the
first cycle, D3 conducts and C1's polarity is reversed with respect to the output at C2, producing -8V.
The 23V output is realized with a series of capacitor charge pumps. It consists of four stages: the first stage
includes C4, D4, and the LM2622 switch; the second stage uses C5, D5, and D1; the third stage includes C6,
D6, and the LM2622 switch; the final stage is C7 and D7. In the first stage, C4 charges to 8V when the LM2622
switch is closed, which causes D5 to conduct when the switch is open. In the second stage, the voltage across
C5 is VC4 + VD1 - VD5 = VC4 ≊ 8V when the switch is open. However, because C5 is referenced to the 8V
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LM2622
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www.ti.com
output, the voltage at C5 is 16V when referenced to ground. In the third stage, the 16V at C5 appears across C6
when the switch is closed. When the switch opens, C6 is referenced to the 8V output minus a diode drop, which
raises the voltage at C6 with respect to ground to about 24V. Hence, in the fourth stage, C7 is charged to 24V
when the switch is open. From the first stage to the last, there are three diode drops that make the output voltage
closer to 24 - 3xVDIODE (about 22.8V if a 0.4V forward drop is assumed).
Table 1. Components For Circuits in Figure 19
Component
600 kHz
1.3 MHz
L
10µH
4.7µH
COUT1
10µF
22µF
COUT2
10µF
NOT USED
CC
3.9nF
1.5nF
CFB1
0.1µF
15nF
CFB2
NOT USED
560pF
CIN
10µF
22µF
C1
4.7µF
4.7µF
C2
0.1µF
0.1µF
C4
1µF
1µF
C5
1µF
1µF
C6
1µF
1µF
C7
1µF
1µF
RFB1
40.2kΩ
91kΩ
RFB2
7.5kΩ
18kΩ
RC
5.1kΩ
10kΩ
D1
MBRM140T3
MBRM140T3
BAT54S
BAT54S
BAT54S
BAT54S
BAT54S
BAT54S
D2
D3
D4
D5
D6
D7
16
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SNVS068E – MAY 2000 – REVISED MARCH 2013
600 KHZ OPERATION
L
10uH
2.7V - 3.3V
D
5
6
SW
VIN
FSLCT
7
RFB!
40.2k
LM2622
Battery or
Power
Source
3
FB
SHDN
VC
CIN
22UF
2
8V
GND
1
4
RC
24k
RFB2
7.5k
COUT
22uF
CC
2.2nF
Figure 20. 600 kHz operation
1.3 MHZ OPERATION
L
4.7uH
2.7V - 3.3V
D
5
6
SW
VIN
FSLCT
7
RFB!
160k
LM2622
Battery or
Power
Source
3
CIN
33UF
FB
SHDN
VC
2
8V
GND
1
4
RC
56k
RFB2
30k
COUT
22uF
CC
2.2nF
Figure 21. 1.3 MHz operation
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POWER DISSIPATION
The output power of the LM2622 is limited by its maximum power dissipation. The maximum power dissipation is
determined by the formula
PD = (Tjmax - TA)/θJA
where
•
•
•
Tjmax is the maximum specidfied junction temperature (125°C)
TA is the ambient temperature
θJA is the thermal resistance of the package
(21)
θJA is dependant on the layout of the board as shown below.
18
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19
LM2622
SNVS068E – MAY 2000 – REVISED MARCH 2013
20
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SNVS068E – MAY 2000 – REVISED MARCH 2013
REVISION HISTORY
Changes from Revision D (March 2013) to Revision E
•
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 20
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21
PACKAGE OPTION ADDENDUM
www.ti.com
7-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Device Marking
(3)
(4/5)
LM2622MM-ADJ/NOPB
ACTIVE
VSSOP
DGK
8
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S18B
LM2622MMX-ADJ/NOPB
ACTIVE
VSSOP
DGK
8
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
S18B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LM2622MM-ADJ/NOPB
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VSSOP
DGK
8
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
LM2622MMX-ADJ/NOPB VSSOP
DGK
8
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
23-Sep-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LM2622MM-ADJ/NOPB
VSSOP
DGK
8
1000
210.0
185.0
35.0
LM2622MMX-ADJ/NOPB
VSSOP
DGK
8
3500
367.0
367.0
35.0
Pack Materials-Page 2
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