Microchip MCP3901A3T-I/SS Two channel analog front end Datasheet

MCP3901
Two Channel Analog Front End
Features
Description
• Two synchronous sampling 16/24-bit resolution
Delta-Sigma A/D Converters with proprietary
multi-bit architecture
• 91 dB SINAD, -104 dBc THD (up to 35th harmonic),
109 dB SFDR for each channel
• Programmable data rate up to 64 ksps
• Ultra low power shutdown mode with <2 µA
• -133 dB Crosstalk between the two channels
• Low Drift Internal Voltage Reference: 12 ppm/°C
• Differential Voltage Reference Input Pins
• High Gain PGA on each channel (up to 32 V/V)
• Phase Delay Compensation between the two
channels with 1 µs time resolution
• Separate Modulator outputs for each channel
• High-Speed Addressable 20 MHz SPI Interface
with Mode 0,0 and 1,1 Compatibility
• Independent analog and digital power supplies
4.5V-5.5V AVDD, 2.7V-5.5V DVDD
• Low Power consumption (14 mW typical at 5V)
• Available in small 20-lead QFN and SSOP
packages
• Industrial Temperature Range -40°C to +85°C
The MCP3901 is a dual channel analog front end (AFE)
containing two synchronous sampling delta-sigma
Analog-to-Digital Converters (ADC), two PGAs, phase
delay compensation block, internal voltage reference,
modulator output block, and high-speed 20 MHz SPI
compatible serial interface. The converters contain a
proprietary dithering algorithm for reduced idle tones
and improved THD.
Package Type
AVDD
REFIN-
20-Lead
QFN
SDI
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
9
12
DR
MDAT0
MDAT1
10
11
DGND
SDO
SCK
CS
OSC2
OSC1/CLKI
SDO
Energy Metering & Power Measurement
Automotive
Portable Instrumentation
Medical and Power Monitoring
RESET
DVDD
AVDD
CH0+
CH0CH1CH1+
AGND
REFIN/OUT+
SDI
20-Lead
SSOP
DVDD
•
•
•
•
The MCP3901 is capable of interfacing to a large
variety of voltage and current sensors including shunts,
current transformers, Rogowski coils, and Hall effect
sensors.
RESET
Applications
The internal register map contains 24-bit wide ADC
data words, a modulator output byte as well as six
writable control registers to program gain,
over-sampling ratio, phase, resolution, dithering, shutdown, reset and several communication features. The
communication is largely simplified with various
continuous read modes that can be accessed by the
DMA of a MCU and with separate data ready pin that
can directly be connected to an IRQ input of a MCU.
20 19 18 17 16
CH0+ 1
© 2009 Microchip Technology Inc.
CH0-
2
15 SCK
14 CS
EP
21
CH1-
3
CH1+
4
12 OSC1/CLKI
AGND
5
11 DR
6
7
8
9
10
REFIN/OUT+
REFIN-
DGND
MDAT1
MDAT0
13 OSC2
DS22192A-page 1
MCP3901
Functional Block Diagram
REFIN/OUT+
REFIN -
AVDD
DVDD
Voltage
VREFEXT
Reference
+
VREF
-
AMCLK
DMCLK/DRCLK
VREF- VREF+ ANALOG DIGITAL
Clock
Generation
DMCLK
Xtal Oscillator
OSC1
MCLK
OSC2
OSR<1:0>
PRE<1:0>
SINC3
CH0+
+
CH0-
PGA
DATA_CH0<23:0>
DR
SDO
D -S
Modulator
Phase
Shifter
F
CH1+
+
CH1-
PGA
PHASE <7:0>
DATA_CH1<23:0>
D -S
Modulator
POR
AVDD
Monitoring
MOD<7:0>
POR
AGND
RESET
SDI
SCK
CS
SINC3
DUAL DS ADC
SDN<1:0>, RESET<1:0>, GAIN<7:0>
DS22192A-page 2
Digital SPI
Interface
MODOUT<1:0>
Modulator
Output Block
MDAT0
MDAT1
DGND
© 2009 Microchip Technology Inc.
MCP3901
1.0
ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD ...................................................................................7.0V
Digital inputs and outputs w.r.t. AGND ........ -0.6V to VDD +0.6V
Analog input w.r.t. AGND ..................................... ....-6V to +6V
VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V
Storage temperature .....................................-65°C to +150°C
Ambient temp. with power applied ................-65°C to +125°C
Soldering temperature of leads (10 seconds) ............. +300°C
ESD on the analog inputs (HBM,MM) .................7.0 kV, 400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
ESD on all other pins (HBM,MM) ........................7.0 kV, 400V
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5 V; -40°C < TA <+85°C,
MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS = 353 mVRMS @ 50/60 Hz.
Parameters
Symbol
Min
Typical
Max
Units
Conditions
VREF
-2%
2.37
+2%
V
VREFEXT = 0
TCREF
—
12
—
ppm/°C
VREFEXT = 0
7
—
kΩ
AVDD=5V,
VREFEXT = 0
—
—
10
pF
2.2
—
2.6
V
VREF = (VREF+ - VREF-),
VREFEXT = 1
VREFEXT = 1
Internal Voltage Reference
Internal Voltage Reference
Tolerance
Temperature Coefficient
Output Impedance
ZOUTREF
Voltage Reference Input
Input Capacitance
Differential Input Voltage Range
(VREF+ - VREF-)
VREF
Absolute Voltage on REFIN+ pin
VREF+
1.9
—
2.9
V
Absolute Voltage on REFIN- pin
VREF-
-0.3
—
0.3
V
24
—
—
bits
OSR = 256
(See Table 5-3)
kHz
fS = DMCLK = MCLK /
(4 x PRESCALE)
ADC Performance
Resolution (No Missing Codes)
Sampling Frequency
Note 1:
2:
3:
4:
5:
6:
7:
8:
fS
See Table 4-2
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the
maximum signal range, VIN = -0.5 dBFS @ 50/60 Hz = 353 mVRMS, VREF = 2.4V.
See terminology section for definition.
This parameter is established by characterization and not 100% tested.
For these operating currents, the following bit settings apply: SHUTDOWN<1:0>=00, RESET<1:0>=00,
VREFEXT=0, CLKEXT=0.
For these operating currents, the following configuration bit settings apply: SHUTDOWN<1:0>=11,
VREFEXT=1, CLKEXT=1.
Applies to all gains. Offset error is dependant on PGA gain setting, see Figure 2-19 for typical values.
Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied
continuously to the part with no risk for damage.
For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with
BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz.
AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to 0.
© 2009 Microchip Technology Inc.
DS22192A-page 3
MCP3901
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5 V; -40°C < TA <+85°C,
MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS = 353 mVRMS @ 50/60 Hz.
Parameters
Output Data Rate
Analog Input Absolute Voltage on
CH0+, CH0-, CH1+, CH1- pins
Analog Input Leakage Current
Differential Input Voltage Range
Offset Error (Note 2)
Symbol
fD
CHn+-
Max
See Table 4-2
-1
—
+1
Units
Conditions
ksps
fD = DRCLK= DMCLK /
OSR = MCLK / (4 x
PRESCALE x OSR)
V
All analog input
channels, measured to
AGND. (Note 7)
AIN
—
1
—
nA
(Note 4)
—
—
500 /
GAIN
mV
(Note 1)
-3
—
+3
mV
—
3
—
µV/°C
- 0.4
—
%
G=1
—
+2.5
%
All Gains
VOS
GE
-2.5
Gain Error Drift
—
Integral Non-Linearity (Note 2)
INL
Input Impedance
ZIN
SINAD
Signal-to-Noise and Distortion
Ratio (Notes 2, 3)
Typical
(CHn+CHn-)
Offset Error Drift
Gain Error (Note 2)
Min
1
—
ppm/°C
15
—
ppm
GAIN = 1,
DITHER = ON
350
—
—
kΩ
Proportional to
1/AMCLK
89
91
—
dB
OSR = 256,
DITHER = ON
78
79
—
dB
Total Harmonic Distortion
(Notes 2, 3)
THD
—
-104
-102
dB
—
-85
-84
dB
Signal-to-Noise Ratio
(Notes 2, 3)
SNR
89
91
—
dB
Spurious Free Dynamic Range
(Note 2)
Crosstalk (50 / 60 Hz) (Note 2)
Note 1:
2:
3:
4:
5:
6:
7:
8:
SFDR
CTALK
(Note 6)
From -40°C to +125°C
From -40°C to +125°C
OSR = 256,
DITHER = ON
OSR = 256,
DITHER = ON
80
81
—
dB
—
109
—
dB
OSR = 256,
DITHER = ON
—
87
—
-133
—
dB
OSR = 256,
DITHER = ON
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the
maximum signal range, VIN = -0.5 dBFS @ 50/60 Hz = 353 mVRMS, VREF = 2.4V.
See terminology section for definition.
This parameter is established by characterization and not 100% tested.
For these operating currents, the following bit settings apply: SHUTDOWN<1:0>=00, RESET<1:0>=00,
VREFEXT=0, CLKEXT=0.
For these operating currents, the following configuration bit settings apply: SHUTDOWN<1:0>=11,
VREFEXT=1, CLKEXT=1.
Applies to all gains. Offset error is dependant on PGA gain setting, see Figure 2-19 for typical values.
Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied
continuously to the part with no risk for damage.
For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with
BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz.
AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to 0.
DS22192A-page 4
© 2009 Microchip Technology Inc.
MCP3901
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, AVDD = 4.5 to 5.5V, DVDD = 2.7 to 5.5 V; -40°C < TA <+85°C,
MCLK = 4 MHz; PRESCALE = 1; OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5 dBFS = 353 mVRMS @ 50/60 Hz.
Parameters
Symbol
Min
Typical
Max
Units
Conditions
AC Power Supply Rejection
AC PSRR
—
-77
—
dB
AVDD and DVDD = 5V +
1VPP @ 50/60 Hz
DC Power Supply Rejection
DC PSRR
—
-77
—
dB
AVDD and DVDD = 4.5 to
5.5V
dB
VCM varies from -1V to
+1V
DC Common Mode Rejection
Ratio Note 2
CMRR
-72
Oscillator Input
Master Clock Frequency Range
MCLK
1
—
16.384
MHz
(Note 8)
Operating Voltage, Analog
AVDD
4.5
—
5.5
V
Operating Voltage, Digital
DVDD
2.7
3.6
5.5
V
Operating Current, Analog
(Note 4)
AIDD
—
2.1
2.8
—
3.8
5.6
mA
BOOST<1:0> = 11
Operating Current, Digital
DIDD
—
0.45
0.8
mA
DVDD = 5V,
MCLK = 4 MHz
—
0.25
0.35
mA
DVDD = 2.7V,
MCLK = 4 MHz
—
1.2
1.6
mA
DVDD = 5V,
MCLK = 8.192 MHz
Power Specifications
BOOST<1:0> = 00
Shutdown Current, Analog
IDDS,A
—
—
1
µA
AVDD pin only(Note 5)
Shutdown Current, Digital
IDDS,D
—
—
1
µA
DVDD pin only(Note 5)
Note 1:
2:
3:
4:
5:
6:
7:
8:
This specification implies that the ADC output is valid over this entire differential range and that there is no
distortion or instability across this input range. Dynamic Performance specified at -0.5 dB below the
maximum signal range, VIN = -0.5 dBFS @ 50/60 Hz = 353 mVRMS, VREF = 2.4V.
See terminology section for definition.
This parameter is established by characterization and not 100% tested.
For these operating currents, the following bit settings apply: SHUTDOWN<1:0>=00, RESET<1:0>=00,
VREFEXT=0, CLKEXT=0.
For these operating currents, the following configuration bit settings apply: SHUTDOWN<1:0>=11,
VREFEXT=1, CLKEXT=1.
Applies to all gains. Offset error is dependant on PGA gain setting, see Figure 2-19 for typical values.
Outside of this range, the ADC accuracy is not specified. An extended input range of ±6V can be applied
continuously to the part with no risk for damage.
For proper operation and to keep ADC accuracy, AMCLK should always be in the range of 1 to 5 MHz with
BOOST bits off. With BOOST bits on, AMCLK should be in the range of 1 to 8.192 MHz.
AMCLK = MCLK/PRESCALE. When using a crystal, CLKEXT bit should be equal to 0.
SERIAL INTERFACE SPECIFICATIONS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V,
DVDD = 2.7 to 5.5V, -40°C < TA <+85°C, CLOAD = 30 pF.
Parameters
Sym
Min
Typ
Max
Units
Serial Clock frequency
fSCK
—
—
—
—
20
10
MHz
MHz
4.5 ≤ DVDD ≤ 5.5
2.7 ≤ DVDD < 5.5
CS setup time
tCSS
25
50
—
—
—
—
ns
ns
4.5 ≤ DVDD ≤ 5.5
2.7 ≤ DVDD < 5.5
Note 1:
Conditions
This parameter is periodically sampled and not 100% tested.
© 2009 Microchip Technology Inc.
DS22192A-page 5
MCP3901
SERIAL INTERFACE SPECIFICATIONS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V,
DVDD = 2.7 to 5.5V, -40°C < TA <+85°C, CLOAD = 30 pF.
Parameters
Sym
Min
Typ
Max
Units
CS hold time
tCSH
50
100
—
—
—
—
ns
ns
4.5 ≤ DVDD ≤ 5.5
2.7 ≤ DVDD < 5.5
CS disable time
tCSD
50
—
—
ns
—
Data setup time
tSU
5
10
—
—
—
—
ns
ns
4.5 ≤ DVDD ≤ 5.5
2.7 ≤ DVDD < 5.5
Data hold time
tHD
10
20
—
—
—
—
ns
ns
4.5 ≤ DVDD ≤ 5.5
2.7≤ DVDD < 5.5
Serial Clock high time
tHI
25
50
—
—
—
—
ns
ns
4.5≤ DVDD ≤ 5.5
2.7 ≤ DVDD < 5.5
Serial Clock low time
tLO
25
50
—
—
—
—
ns
ns
4.5 ≤ DVDD ≤ 5.5
2.7 ≤ DVDD < 5.5
Serial Clock delay time
tCLD
50
—
—
ns
—
Serial Clock enable time
tCLE
50
—
—
ns
—
tDO
—
—
50
ns
2.7 ≤ DVDD < 5.5
tDOMDAT
—
—
1/
2*AMCLK
s
—
Output valid from SCK low
Modulator output valid from AMCLK
high
Conditions
Output hold time
tHO
0
—
—
ns
(Note 1)
Output disable time
tDIS
—
—
—
—
25
50
ns
ns
4.5 ≤ DVDD ≤ 5.5
2.7 ≤ DVDD < 5.5 (Note 1)
Reset Pulse Width (RESET)
tMCLR
100
—
—
ns
2.7 ≤ DVDD < 5.5
Data Transfer Time to DR (Data Ready)
tDODR
—
50
ns
2.7 ≤DVDD < 5.5
tDRP
1/
—
µs
2.7 ≤ DVDD < 5.5
Data Ready Pulse Low Time
DMCLK
Schmitt Trigger High-level Input voltage
VIH1
.7 DVDD
—
DVDD +1
V
Schmitt Trigger Low-level input voltage
VIL1
-0.3
—
0.2 DVDD
V
Hysteresis of Schmitt Trigger Inputs
(All digital inputs)
VHYS
300
—
Low-level output voltage, SDO pin
VOL
—
—
Low-level output voltage, DR and
MDAT pins
VOL
High-level output voltage, SDO pin
VOH
DVDD 0.5
High-level output voltage, DR and
MDAT pins
VOH
Input leakage current
Output leakage current
Internal capacitance (all inputs and
outputs)
Note 1:
mV
0.4
V
SDO pin only,
IOL = +2.0 mA, VDD = 5.0V
0.4
V
DR and MDAT pins only,
IOL = +800 mA, VDD =5.0V
—
—
V
SDO pin only,
IOH = -2.0 mA, VDD = 5.0V
DVDD 0.5
—
—
V
DR and MDAT pins only,
IOH = -800 µA, VDD=5.0V
ILI
—
—
±1
µA
CS = DVDD, VIN = DGND
or DVDD
ILO
—
—
±1
µA
CS = DVDD, VOUT = DGND
or DVDD
CINT
—
—
7
pF
TA = 25°C,
SCK = 1.0 MHz,
DVDD = 5.0V (Note 1)
This parameter is periodically sampled and not 100% tested.
DS22192A-page 6
© 2009 Microchip Technology Inc.
MCP3901
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = 4.5 to 5.5V, DVDD = 2.7 to
5.5 V.
Parameters
Sym
Min
Typ
Max
Units
Conditions
Operating Temperature Range
TA
-40
—
+85
°C
(Note 1)
Storage Temperature Range
TA
-65
—
+150
°C
Thermal Resistance, 20L SSOP
θJA
—
89.3
—
°C/W
Thermal Resistance, 20L QFN
θJA
—
43
—
°C/W
Temperature Ranges
Thermal Package Resistances
Note 1:
The internal junction temperature (TJ) must not exceed the absolute maximum specification of +150°C.
CS
fSCK
tHI
tCSH
tLO
Mode 1,1
SCK
Mode 0,0
tDO
tDIS
tHO
MSB out
SDO
LSB out
Don’t Care
SDI
FIGURE 1-1:
Serial Output Timing Diagram.
tCSD
CS
tHI
Mode 1,1
SCK
tCLE
fSCK
tCSS
tLO
tCSH
tCLD
Mode 0,0
tSU
SDI
tHD
MSB in
HI-Z
SDO
FIGURE 1-2:
LSB in
Serial Input Timing Diagram.
© 2009 Microchip Technology Inc.
DS22192A-page 7
MCP3901
1 / DRCLK
DR
tDRP
tDODR
SCK
SDO
FIGURE 1-3:
Data Ready Pulse Timing Diagram.
H
Timing Waveform for tDIS
Timing Waveform for tDO
SCK
CS
VIH
tDO
90%
SDO
SDO
tDIS
HI-Z
10%
Timing Waveform for MDAT0/1
Modulator Output
OSC1/CLKI
tDOMDAT
MDAT0/1
FIGURE 1-4:
Specific Timing Diagrams.
CLKEXT
PRESCALE<1:0>
OSR<1:0>
Digital Buffer
1
OSC1
0
OSC2
Crystal
Oscillator
FIGURE 1-5:
DS22192A-page 8
Multiplexer
1/
Prescale
MCLK
1/4
AMCLK
Clock Divider
Clock Divider
fS ADC
Sampling
Rate
fD ADC
Output
Data Rate
1 / OSR
DMCLK
DRCLK
Clock Divider
MCP3901 Clock Detail.
© 2009 Microchip Technology Inc.
MCP3901
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
fIN = -0.5dBFS @ 60 Hz
fD = 3.9 ksps
16384 Point FFT
OSR = 256
Dithering ON
0
500
1000
1500
Amplitude (dB)
Amplitude (dB)
Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5dBFS @ 60 Hz.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
2000
fIN = -60dBFS @ 60 Hz
fD = 3.9 ksps
16384 Point FFT
OSR = 256
Dithering OFF
0
500
Spectral Response.
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
FIGURE 2-4:
fIN = -60dBFS @ 60 Hz
fD = 3.9 ksps
16384 Point FFT
OSR = 256
Dithering ON
0
500
1000
1500
Amplitude (dB)
Amplitude (dB)
FIGURE 2-1:
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
2000
fIN = -0.5dBFS @ 60 Hz
fD = 15.6 ksps
16384 Point FFT
OSR = 64
Dithering OFF
0
2000
2000
4000
6000
8000
Frequency (Hz)
Spectral Response.
FIGURE 2-5:
Spectral Response.
0
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
fIN = -0.5dBFS @ 60 Hz
fD = 3.9 ksps
OSR = 256
16384 points
Dithering OFF
fIN = -60dBFS @ 60 Hz
fD = 15.6 ksps
16384 Point FFT
OSR = 64
Dithering OFF
-20
Amplitude (dB)
Amplitude (dB)
1500
Spectral Response.
Frequency (Hz)
FIGURE 2-2:
1000
Frequency (Hz)
Frequency (Hz)
-40
-60
-80
-100
-120
-140
-160
0
500
1000
1500
2000
0
FIGURE 2-3:
Spectral Response.
© 2009 Microchip Technology Inc.
2000
4000
6000
8000
Frequency (Hz)
Frequency (Hz)
FIGURE 2-6:
Spectral Response.
DS22192A-page 9
MCP3901
fIN = -0.5dBFS @ 60 Hz
fD = 15.6 ksps
16384 Point FFT
OSR = 64
Dithering ON
-160
-180
0
2000
4000
6000
120
110
100
90
80
70
60
50
40
30
20
10
0
Dithering ON
Dithering OFF
32
8000
64
Spectral Response.
Amplitude (dB)
0
-20
-40
-60
-80
-100
-120
-140
-160
-180
-200
fIN = -60dBFS @ 60 Hz
fD = 15.6 ksps
16384 Point FFT
OSR = 64
Dithering ON
0
2000
4000
6000
100
95
90
85
80
75
70
65
60
55
50
16
15
14
13
Dithering OFF
12
11
Dithering ON
10
9
8
32
8000
64
128
256
Oversampling Ratio (OSR)
Frequency (Hz)
FIGURE 2-8:
256
FIGURE 2-10:
Spurious Free Dynamic
Range vs. Oversampling Ratio.
SINAD (dB)
FIGURE 2-7:
128
Oversampling Ratio (OSR)
Frequency (Hz)
Effective Number of Bits
Amplitude (dB)
0
-20
-40
-60
-80
-100
-120
-140
Spurious Free Dynamic
Range (dB)
Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5dBFS @ 60 Hz.
Spectral Response.
FIGURE 2-11:
Signal-to-Noise and
Distortion and Effective Number of Bits vs.
Oversampling Ratio.
fIN = 60 Hz
MCLK = 4 MHz
OSR = 256
Dithering On
0
1
8
6
4
2
0
107 107.5 108 108.5 109 109.5 110 110.5 111
Spurious Free Dynamic Range (dB)
FIGURE 2-9:
Spurious Free Dynamic
Range Histogram.
DS22192A-page 10
SINAD (dB)
Frequency of Occurance
2
1
95
90
85
80
75
70
65
60
55
50
45
40
OSR = 256
OSR = 128
OSR = 32
1
2
OSR = 64
4
8
16
32
Gain (V/V)
FIGURE 2-12:
Signal-to-Noise and
Distortion vs. Gain.
© 2009 Microchip Technology Inc.
MCP3901
14
95
90
85
80
75
70
65
60
55
50
45
40
OSR = 256
Frequency of Occurance
SINAD (dB)
Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5dBFS @ 60 Hz.
12
OSR = 128
10
OSR = 64
fIN = 60 Hz
MCLK = 4 MHz
OSR = 256
Dithering On
8
6
OSR = 32
4
2
1
2
4
8
16
0
32
-105.0 -104.5 -104.0 -103.5 -103.0 -102.5 -102.0
Total Harmonic Distortion (dBc)
Gain (V/V)
FIGURE 2-16:
Total Harmonic Distortion
Histogram (Dithering On).
0
Total Harmonic Distortion
(dBc)
Total Harmonic Distortion
(dBc)
FIGURE 2-13:
Signal-to-Noise and
Distortion vs. Gain (Dithering On).
-20
-40
-60
Dithering OFF
-80
-100
Dithering ON
-120
32
64
128
0
-20
-40
-60
-80
-100
-120
-50
256
-25
0
25
Oversampling Ratio (OSR)
FIGURE 2-17:
vs. Temperature.
75
100
125 150
Total Harmonic Distortion
90
100
fD = 15.625 ksps
80
70
fD = 15.625 ksps
SINAD (dB)
Total Harmonic Distortion
(dBc)
FIGURE 2-14:
Total Harmonic Distortion
vs. Oversampling Ratio.
80
60
50
Temperature (ºC)
40
20
0
-20
60
50
40
30
20
-40
-60
-80
SINC filter notch at 15.625 Hz
10
100
1000
10000
Input Signal Frequency (Hz)
FIGURE 2-15:
Total Harmonic Distortion
vs. Input Signal Frequency.
© 2009 Microchip Technology Inc.
10
0
SINC filter notch at 15.625 Hz
10
100
1000
10000
Input Signal Frequency (Hz)
FIGURE 2-18:
Signal-to-Noise and
Distortion vs. Input Frequency.
DS22192A-page 11
MCP3901
Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5dBFS @ 60 Hz.
fIN = 60 Hz
MCLK = 4 MHz
OSR = 64
Dithering OFF
1 0
8
6
4
0.6
G=8
0.5
Offset Error (mV)
Frequency of Occurance
1 2
0.4
0.3
0.2
G=16
0.1
G=1
0
G=2
-0.1
2
G=32
G=4
-0.2
0
78.9
79
79.1 79.2 79.3 79.4 79.5 79.6 79.7 79.8
SINAD (dB)
-50
100
90
80
70
60
50
40
30
20
10
0
-50
-25
0
25
50
75
100
125
-25
0
25
50
75
Temperature (ºC)
FIGURE 2-22:
Temperature.
Offset Error (mV)
SINAD (dB)
FIGURE 2-19:
Signal-to-Noise and
Distortion Histogram.
-0.3
150
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
-0.1
-0.2
-0.3
G=8
G=1
G=16
G=32
G=2
G=4
-50
-25
0
FIGURE 2-23:
Temperature.
100
Offset Error (mV)
SINAD (dB)
80
60
40
20
0
-20
-40
- 40
- 60
Input Amplitude (dBFS)
FIGURE 2-21:
Signal-to-Noise and
Distortion vs. Input Signal Amplitude.
DS22192A-page 12
150
25
50
75
100
125
150
Temperature (°C)
FIGURE 2-20:
Signal-to-Noise and
Distortion vs. Temperature.
- 20
125
Channel 0 Offset vs.
Temperature (ºC)
0
100
- 80
0.5
0.45
0.4
0.35
0.3
0.25
0.2
0.15
0.1
0.05
0
Channel 1 Offset vs.
Channel 0
Channel 1
-50
-25
0
25
50
75
100
125
150
Temperature (°C)
FIGURE 2-24:
Channel-to-Channel Offset
Match vs. Temperature.
© 2009 Microchip Technology Inc.
MCP3901
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
G=1
G=2
G=8
G=16
G=4
G=32
-50
-25
0
25
50
75
100
125
Int. Voltage Reference (V)
Positive Gain Error (% FS)
Note: Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = +25°C, MCLK = 4 MHz; PRESCALE = 1;
OSR = 64; GAIN = 1; Dithering OFF; VIN = -0.5dBFS @ 60 Hz.
2.37165
2.3716
2.37155
2.3715
2.37145
2.3714
2.37135
2.3713
150
4.5
4.8
Temperature (°C)
Positive Gain Error vs.
0
-0.2
-0.4
-0.6
-0.8
-1
-1.2
-1.4
-1.6
-1.8
-2
G=1
G=2
G=8
G=16
G=4
G=32
-50
-25
0
25
50
75
100
125
150
3
5
Negative Gain Error vs.
Frequency of Occurence
Int. Voltage Reference (V)
2.39
2.38
2.37
2.36
2.35
FIGURE 2-27:
vs. Temperature.
0
25
50
75 100
Temperature (°C)
125
150
Internal Voltage Reference
© 2009 Microchip Technology Inc.
9
11
FIGURE 2-29:
Signal-to-Noise and
Distortion vs. Master Clock (MCLK), BOOST ON.
8000
-25
7
MCLK Frequency (MHz)
2.4
-50
5.5
100
90
80
70
60
50
40
30
20
10
0
Temperature (°C)
FIGURE 2-26:
Temperature
5.3
FIGURE 2-28:
Internal Voltage Reference
vs. Supply Voltage.
SINAD (dB)
Negative Gain Error (% FS)
FIGURE 2-25:
Temperature.
5.0
Power Supply (V)
7000
6000
5000
4000
Channel 0
VIN = 0V
TA = +25°C
16384 Consecutive
Readings
24-bit Mode
3000
2000
1000
0
-3000
-2000
-1000
0
1000
2000
3000
Output Code (LSB)
FIGURE 2-30:
Noise Histogram.
DS22192A-page 13
MCP3901
Unless otherwise indicated, AVDD = 5.0V, DVDD = 5.0 V; TA = 25°C, MCLK = 4 MHz; PRESCALE = 1; OSR
= 64; GAIN = 1; Dithering OFF; VIN = -0.5dBFS @ 60 Hz.
100
80
60
40
20
0
-20
-40
-60
-80
-100
-0.5
2.5
OSR = 256
Dithering OFF
SCK = 8 MHz
2
IDD (mA)
INL (ppm)
Note:
Channel 0
Channel 1
0
-0.25
0
0.25
0.5
INL (ppm)
1
2
3
4
5
6
FIGURE 2-33:
Operating Current vs.
Master Clock (MCLK).
OSR = 256
Dithering ON
SCK = 8 MHz
20
Channel 0
10
0
DS22192A-page 14
0
MCLK (MHz)
Integral Non-Linearity
50
40
30
FIGURE 2-32:
(Dithering On).
1
DIDD
FIGURE 2-31:
(Dithering Off).
-50
-0.5
1.5
0.5
Input Voltage (V)
-10
-20
-30
-40
AIDD BOOST OFF
Channel 1
-0.25
0
0.25
Input Voltage (V)
0.5
Integral Non-Linearity
© 2009 Microchip Technology Inc.
MCP3901
3.0
PIN DESCRIPTION
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
Pin No.
SSOP
Pin No.
QFN
Symbol
1
18
RESET
2
19
DVDD
Digital Power Supply Pin
3
20
AVDD
Analog Power Supply Pin
4
1
CH0+
Non-Inverting Analog Input Pin for Channel 0
5
2
CH0-
Inverting Analog Input Pin for Channel 0
6
3
CH1-
Inverting Analog Input Pin for Channel 1
7
4
CH1+
Non-Inverting Analog Input Pin for Channel 1
8
5
AGND
Analog Ground Pin, Return Path for internal analog circuitry
9
6
REFIN+/OUT
10
7
REFIN-
Function
Master Reset Logic Input Pin
Non-Inverting Voltage Reference Input and Internal Reference Output Pin
Inverting Voltage Reference Input Pin
Digital Ground Pin, Return Path for internal digital circuitry
11
8
DGND
12
9
MDAT1
Modulator Data Output Pin for Channel 1
13
10
MDAT0
Modulator Data Output Pin for Channel 0
14
11
DR
15
12
OSC1/CLKI
16
13
OSC2
17
14
CS
18
15
SCK
Serial Interface Clock Pin
19
16
SDO
Serial Interface Data Output Pin
20
17
SDI
Serial Interface Data Input Pin
—
21
EP
Exposed Pad - To be connected to AGND ground plane
3.1
Data Ready Signal Output Pin
Oscillator Crystal Connection Pin or External Clock Input Pin
Oscillator Crystal Connection Pin
Serial Interface Chip Select Pin
RESET
This pin is active low and places the entire chip in a
reset state when active.
When RESET=0, all registers are reset to their default
value, no communication can take place, no clock is
distributed inside the part. This state is equivalent to a
POR state.
Since the default state of the ADCs is on, the analog
power consumption when RESET=0 is equivalent to
when RESET=1. Only the digital power consumption is
largely reduced because this current consumption is
essentially dynamic and is reduced drastically when
there is no clock running.
3.2
Digital VDD (DVDD)
DVDD is the power supply pin for the digital circuitry
within the MCP3901. This pin requires appropriate
bypass capacitors and should be maintained between
2.7V and 5.5V for specified operation.
3.3
Analog VDD (AVDD)
AVDD is the power supply pin for the analog circuitry
within the MCP3901.
This pin requires appropriate bypass capacitors and
should be maintained to 5V ±10% for specified
operation.
All the analog biases are enabled during a reset so that
the part is fully operational just after a RESET rising
edge.
This input is Schmitt triggered.
© 2009 Microchip Technology Inc.
DS22192A-page 15
MCP3901
3.4
ADC Differential Analog inputs
(CHn+/CHn-)
CH0- and CH0+, and CH1- and CH1+, are the two
fully-differential analog voltage inputs for the
Delta-Sigma ADCs.
The linear and specified region of the channels are
dependent on the PGA gain. This region corresponds
to a differential voltage range of ±500 mV/GAIN with
VREF=2.4V.
The maximum absolute voltage, with respect to AGND,
for each CHn+/- input pin is +/-1V with no distortion and
+/-6V with no breaking after continuous voltage.
3.5
Analog Ground (AGND)
AGND is the ground connection to internal analog
circuitry (ADCs, PGA, voltage reference, POR). To
ensure accuracy and noise cancellation, this pin must
be connected to the same ground as DGND, preferably
with a star connection. If an analog ground plane is
available, it is recommended that this pin be tied to this
plane of the PCB. This plane should also reference all
other analog circuitry in the system.
3.6
Non-inverting Reference Input,
Internal Reference Output
(REFIN+/OUT)
This pin is the non-inverting side of the differential
voltage reference input for both ADCs or the internal
voltage reference output.
When VREFEXT=1, and an external voltage reference
source can be used, the internal voltage reference is
disabled. When using an external differential voltage
reference, it should be connected to its VREF+ pin.
When using an external single-ended reference, it
should be connected to this pin.
When VREFEXT=0, the internal voltage reference is
enabled and connected to this pin through a switch.
This voltage reference has minimal drive capability and
thus needs proper buffering and bypass capacitances
(10 µF tantalum in parallel with 0.1 µF ceramic) if used
as a voltage source.
For optimal performance, bypass capacitances should
be connected between this pin and AGND at all times
even when the internal voltage reference is used.
However, these capacitors are not mandatory to
ensure proper operation.
3.7
This pin is the inverting side of the differential voltage
reference input for both ADCs. When using an external
differential voltage reference, it should be connected to
its VREF- pin. When using an external single-ended
voltage reference, or when VREFEXT=0 (Default) and
using the internal voltage reference, this pin should be
directly connected to AGND.
3.8
Digital Ground Connection
(DGND)
DGND is the ground connection to internal digital
circuitry (SINC filters, oscillator, serial interface). To
ensure accuracy and noise cancellation, DGND must
be connected to the same ground as AGND, preferably
with a star connection. If a digital ground plane is
available, it is recommended that this pin be tied to this
plane of the Printed Circuit Board (PCB). This plane
should also reference all other digital circuitry in the
system.
3.9
Modulator Data Output Pin for
Channel 1 and Channel 0 (MDAT1/
MDAT0)
MDAT0 and MDAT1 are the output pins for the modulator serial bitstreams of ADC channels 0 and 1, respectively. These pins are high impedance by default. When
the MODOUT<1:0> are enabled, the modulator bitstream of the corresponding channel is present on the
pin and updated at the AMCLK frequency. (See
Section 5.4 “Modulator Output Block” for a complete description of the modulator outputs). These pins
can be directly connected to a MCU or DSP when a
specific digital filtering is needed.
3.10
DR (Data Ready Pin)
The data ready pin indicates if a new conversion result
is ready to be read. The default state of this pin is high
when DR_HIZN=1 and is high impedance when
DR_HIZN=0 (Default). After each conversion is
finished, a low pulse will take place on the data ready
pin to indicate the conversion result is ready as an
interrupt. This pulse is synchronous with the master
clock and has a defined and constant width.
The data ready pin is independent of the SPI interface
and acts like an interrupt output.The data ready pin
state is not latched and the pulse width (and period) are
both determined by the MCLK frequency,
over-sampling rate, and internal clock pre-scale
settings. The DR pulse width is equal to one DMCLK
period and the frequency of the pulses is equal to
DRCLK (see Figure 1-3).
Note:
DS22192A-page 16
Inverting Reference Input (REFIN-)
This pin should not be left floating when
DR_HIZN bit is low; a 1 kΩ pull-up resistor
connected to DVDD is recommended.
© 2009 Microchip Technology Inc.
MCP3901
3.11
Oscillator And Master Clock Input
Pins (OSC1/CLKI, OSC2)
OSC1/CLKI and OSC2 provide the master clock for the
device. When CLKEXT=0 (Default), a resonant crystal
or clock source with a similar sinusoidal waveform must
be placed across these pins to ensure proper
operation. The typical clock frequency specified is
4 MHz. However, the clock frequency can be 1 MHz to
5 MHz without disturbing ADC accuracy. With the current boost circuit enabled, the master clock can be
used up to 8.192 MHz without disturbing ADC
accuracy. Appropriate load capacitance should be
connected to these pins for proper operation.
Note:
3.12
When CLKEXT=1, the crystal oscillator is
disabled, as well as the OSC2 input. The
OSC1 becomes the master clock input
CLKI, direct path for an external clock
source, for example a clock source
generated by a MCU.
CS (Chip Select)
This pin is the SPI chip select that enables the serial
communication. When this pin is high, no
communication can take place. A chip select falling
edge initiates the serial communication and a chip
select rising edge terminates the communication. No
communication can take place even when CS is low
and when RESET is low.
This input is Schmitt-triggered.
3.13
SCK (Serial Data Clock)
3.14
SDO (Serial Data Output)
This is the SPI data output pin. Data is clocked out of
the device on the FALLING edge of SCK.
This pin stays high impedance during the first
command byte. It also stays high impedance during the
whole communication for write commands and when
CS pin is high or when RESET pin is low. This pin is
active only when a read command is processed. Each
read is processed by packet of 8 bits.
3.15
SDI (Serial Data Input)
This is the SPI data input pin. Data is clocked into the
device on the RISING edge of SCK.
When CS is low, this pin is used to communicate with
series of 8-bit commands.
The interface is half-duplex (inputs and outputs do not
happen at the same time).
Each communication starts with a chip select falling
edge followed by an 8-bit command word entered
through the SDI pin. Each command is either a Read or
a Write command. Toggling SDI during a Read
command has no effect.
This input is Schmitt triggered.
3.16
Exposed Thermal Pad (EP)
There is an internal electrical connection between the
Exposed Thermal Pad (EP) and the AGND pin; they
must be connected to the same potential on the Printed
Circuit Board (PCB).
This is the serial clock pin for SPI communication.
Data is clocked into the device on the RISING edge of
SCK. Data is clocked out of the device on the FALLING
edge of SCK.
The MCP3901 interface is compatible with both SPI 0,0
and 1,1 modes. SPI modes can only be changed during
a reset.
The maximum clock speed specified is 20 MHz when
DVDD>4.5V and 10 MHz otherwise.
This input is Schmitt triggered.
© 2009 Microchip Technology Inc.
DS22192A-page 17
MCP3901
NOTES:
DS22192A-page 18
© 2009 Microchip Technology Inc.
MCP3901
4.0
TERMINOLOGY AND
FORMULAS
This section defines the terms and formulas used
throughout this data sheet. The following terms are
defined:
MCLK - Master Clock
AMCLK - Analog Master Clock
4.2
AMCLK - Analog Master Clock
This is the clock frequency that is present on the analog
portion of the device, after prescaling has occurred via
the CONFIG1 PRESCALE<1:0> register bits. The analog portion includes the PGAs and the two sigma-delta
modulators.
EQUATION 4-1:
DMCLK - Digital Master Clock
MCLK AMCLK = -----------------------------PRESCALE
DRCLK - Data Rate Clock
OSR - Oversampling Ratio
Offset Error
TABLE 4-1:
Gain Error
MCP3901 OVERSAMPLING
RATIO SETTINGS
Integral Non-Linearity Error
Config
Signal-To-Noise Ratio (SNR)
PRE<1:0>
Signal-To-Noise Ratio And Distortion (SINAD)
0
0
AMCLK = MCLK/ 1 (default)
Total Harmonic Distortion (THD)
0
1
AMCLK = MCLK/ 2
Spurious-Free Dynamic Range (SFDR)
1
0
AMCLK = MCLK/ 4
MCP3901 Delta-Sigma Architecture
1
1
AMCLK = MCLK/ 8
Idle Tones
Dithering
Crosstalk
PSRR
CMRR
ADC Reset Mode
4.3
Analog Master Clock
Prescale
DMCLK - Digital Master Clock
This is the clock frequency that is present on the digital
portion of the device, after prescaling and division by 4.
This is also the sampling frequency, that is the rate at
which the modulator outputs are refreshed. Each
period of this clock corresponds to one sample and one
modulator output. See Figure 1-5.
Hard Reset Mode (RESET = 0)
ADC Shutdown Mode
EQUATION 4-2:
Full Shutdown Mode
4.1
MCLK
DMCLK = AMCLK
--------------------- = --------------------------------------4
4 × PRESCALE
MCLK - Master Clock
This is the fastest clock present in the device. This is
the frequency of the crystal placed at the OSC1/OSC2
inputs when CLKEXT=0 or the frequency of the clock
input at the OSC1/CLKI when CLKEXT=1. See
Figure 1-5.
4.4
DRCLK - Data Rate Clock
This is the output data rate i.e. the rate at which the
ADCs output new data. Each new data is signaled by a
data ready pulse on the DR pin.
This data rate is depending on the OSR and the
prescaler with the following formula:
EQUATION 4-3:
MCLK
AMCLK = ---------------------------------------------------------DRCLK = DMCLK
---------------------- = --------------------OSR
4 × OSR × PRESCALE
4 × OSR
© 2009 Microchip Technology Inc.
DS22192A-page 19
MCP3901
Since this is the output data rate, and since the
decimation filter is a SINC (or notch) filter, there is a
notch in the filter transfer function at each integer
multiple of this rate.
TABLE 4-2:
PRE
<1:0>
The following table describes the various combinations
of OSR and PRESCALE and their associated AMCLK,
DMCLK and DRCLK rates.
DEVICE DATA RATES IN FUNCTION OF MCLK, OSR, AND PRESCALE
OSR <1:0>
OSR
AMCLK
DMCLK
DRCLK
DRCLK
(ksps)
SINAD
(dB)
ENOB
(bits)
1
1
1
1
256
MCLK/8
MCLK/32
MCLK/8192
0.4882
91.4
14.89
1
1
1
0
128
MCLK/8
MCLK/32
MCLK/4096
0.976
86.6
14.10
1
1
0
1
64
MCLK/8
MCLK/32
MCLK/2048
1.95
78.7
12.78
1
1
0
0
32
MCLK/8
MCLK/32
MCLK/1024
3.9
68.2
11.04
1
0
1
1
256
MCLK/4
MCLK/16
MCLK/4096
0.976
91.4
14.89
1
0
1
0
128
MCLK/4
MCLK/16
MCLK/2048
1.95
86.6
14.10
1
0
0
1
64
MCLK/4
MCLK/16
MCLK/1024
3.9
78.7
12.78
1
0
0
0
32
MCLK/4
MCLK/16
MCLK/512
7.8125
68.2
11.04
0
1
1
1
256
MCLK/2
MCLK/8
MCLK/2048
1.95
91.4
14.89
0
1
1
0
128
MCLK/2
MCLK/8
MCLK/1024
3.9
86.6
14.10
0
1
0
1
64
MCLK/2
MCLK/8
MCLK/512
7.8125
78.7
12.78
0
1
0
0
32
MCLK/2
MCLK/8
MCLK/256
15.625
68.2
11.04
0
0
1
1
256
MCLK
MCLK/4
MCLK/1024
3.9
91.4
14.89
0
0
1
0
128
MCLK
MCLK/4
MCLK/512
7.8125
86.6
14.10
0
0
0
1
64
MCLK
MCLK/4
MCLK/256
15.625
78.7
12.78
0
0
0
0
32
MCLK
MCLK/4
MCLK/128
31.25
68.2
11.04
Note:
4.5
For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1.
OSR - Oversampling Ratio
The ratio of the sampling frequency to the output data
rate. OSR= DMCLK/DRCLK. The default OSR is 64, or
with MCLK = 4 MHz, PRESCALE = 1, AMCLK = 4
MHz, fS = 1 MHz, fD = 15.625 ksps. The following bits
in the CONFIG1 register are used to change the
oversampling ratio (OSR).
TABLE 4-3:
CONFIG
OSR<1:0>
MCP3901 OVERSAMPLING
RATIO SETTINGS
OVER SAMPLING RATIO
OSR
4.6
This is the error induced by the ADC when the inputs
are shorted together (VIN=0V). The specification
incorporates both PGA and ADC offset contributions.
This error varies with PGA and OSR settings. The
offset is different on each channel and varies from chip
to chip. This offset error can easily be calibrated out by
a MCU with a subtraction. The offset is specified in mV.
The offset on the MCP3901 has a low temperature
coefficient, see Section 2.0 “Typical Performance
Curves”.
4.7
0
0
32
0
1
64 (DEFAULT)
1
0
128
1
1
256
Offset Error
Gain Error
This is the error induced by the ADC on the slope of the
transfer function. It is the deviation expressed in%
compared to the ideal transfer function defined by
Equation 5-3. The specification incorporates both PGA
and ADC gain error contributions, but not the VREF
contribution (it is measured with an external VREF).This
error varies with PGA and OSR settings.
The gain error on the MCP3901 has a low temperature
coefficient, see the typical performance curves for
more information, Figure 2-24 and Figure 2-25.
DS22192A-page 20
© 2009 Microchip Technology Inc.
MCP3901
4.8
Integral Non-Linearity Error
Integral non-linearity error is the maximum deviation of
an ADC transition point from the corresponding point of
an ideal transfer function, with the offset and gain
errors removed, or with the end points equal to zero.
It is the maximum remaining error after calibration of
offset and gain errors for a DC input signal.
4.9
Signal-To-Noise Ratio (SNR)
For the MCP3901 ADC, the signal-to-noise ratio is a
ratio of the output fundamental signal power to the
noise power (not including the harmonics of the signal),
when the input is a sinewave at a predetermined
frequency. It is measured in dB. Usually, only the
maximum signal to noise ratio is specified. The SNR
figure depends mainly on the OSR and DITHER
settings of the device.
EQUATION 4-4:
SIGNAL-TO-NOISE RATIO
4.11
The total harmonic distortion is the ratio of the output
harmonics power to the fundamental signal power for a
sinewave input and is defined by the following
equation.
EQUATION 4-7:
HarmonicsPower
THD ( dB ) = 10 log ⎛ -----------------------------------------------------⎞
⎝ FundamentalPower⎠
The THD calculation includes the first 35 harmonics for
the MCP3901 specifications. The THD is usually only
measured with respect to the 10 first harmonics. THD
is sometimes expressed in%. For converting the THD
in %, here is the formula:
EQUATION 4-8:
SignalPower
SNR ( dB ) = 10 log ⎛⎝ ----------------------------------⎞⎠
NoisePower
4.10
Signal-To-Noise Ratio And
Distortion (SINAD)
The most important figure of merit for the analog
performance of the ADCs present on the MCP3901 is
the
Signal-to-Noise
And
Distortion
(SINAD)
specification.
Signal-to-noise and distortion ratio is similar to signalto-noise ratio, with the exception that you must include
the harmonics power in the noise power calculation.
The SINAD specification depends mainly on the OSR
and DITHER settings.
EQUATION 4-5:
SINAD EQUATION
SignalPower
SINAD ( dB ) = 10 log ⎛⎝ --------------------------------------------------------------------⎞⎠
Noise + HarmonicsPower
The calculated combination of SNR and THD per the
following formula also yields SINAD:
EQUATION 4-6:
Total Harmonic Distortion (THD)
THD ( % ) = 100 × 10
THD
( dB )
-----------------------20
This specification depends mainly on the DITHER setting.
4.12
Spurious-Free Dynamic Range
(SFDR)
The ratio between the output power of the fundamental
and the highest spur in the frequency spectrum. The
spur frequency is not necessarily a harmonic of the
fundamental even though it is usually the case. This
figure represents the dynamic range of the ADC when
a full-scale signal is used at the input. This specification
depends mainly on the DITHER setting.
EQUATION 4-9:
FundamentalPower
SFDR ( dB ) = 10 log ⎛ -----------------------------------------------------⎞
⎝ HighestSpurPower ⎠
SINAD, THD, AND SNR
RELATIONSHIP
SINAD ( dB ) = 10 log 10
⎛ SNR
-----------⎞
⎝ 10 ⎠
© 2009 Microchip Technology Inc.
+ 10
THD-⎞
⎛ –--------------⎝ 10 ⎠
DS22192A-page 21
MCP3901
4.13
MCP3901 Delta-Sigma
Architecture
The MCP3901 incorporates two Delta-Sigma ADCs
with a multi-bit architecture. A Delta-Sigma ADC is an
oversampling converter that incorporates a built-in
modulator which is digitizing the quantity of charge
integrated by the modulator loop (see Figure 5-1). The
quantizer is the block that is performing the
analog-to-digital conversion. The quantizer is typically
1-bit, or a simple comparator which helps to maintain
the linearity performance of the ADC (the DAC
structure is in this case inherently linear).
Multi-bit quantizers help to lower the quantization error
(the error fed back in the loop can be very large with
1-bit quantizers) without changing the order of the
modulator or the OSR which leads to better SNR
figures. However, typically, the linearity of such
architectures is more difficult to achieve since the DAC
is no more simple to realize and its linearity limits the
THD of such ADCs.
The MCP3901’s 5-level quantizer is a flash ADC
composed of 4 comparators arranged with equally
spaced thresholds and a thermometer coding. The
MCP3901 also includes proprietary 5-level DAC
architecture that is inherently linear for improved THD
figures.
4.14
Idle Tones
A Delta-Sigma converter is an integrating converter. It
also has a finite quantization step (LSB) which can be
detected by its quantizer. A DC input voltage that is
below the quantization step should only provide an all
zeros result since the input is not large enough to be
detected. As an integrating device, any Delta-Sigma
will show in this case idle tones. This means that the
output will have spurs in the frequency content that are
depending on the ratio between quantization step
voltage and the input voltage. These spurs are the
result of the integrated sub-quantization step inputs
that will eventually cross the quantization steps after a
long enough integration. This will induce an AC
frequency at the output of the ADC and can be shown
in the ADC output spectrum.
For power metering applications, idle tones can be very
disturbing because energy can be detected even at the
50 or 60 Hz frequency, depending on the DC offset of
the ADCs, while no power is really present at the
inputs. The only practical way to suppress or attenuate
idle tones phenomenon is to apply dithering to the
ADC. The idle tones amplitudes are function of the
order of the modulator, the OSR and the number of
levels in the quantizer of the modulator. A higher order,
a higher OSR or a higher number of levels for the
quantizer will attenuate the idle tones amplitude.
4.15
Dithering
In order to suppress or attenuate the idle tones present
in any Delta-Sigma ADCs, dithering can be applied to
the ADC. Dithering is the process of adding an error to
the ADC feedback loop in order to “decorrelate” the
outputs and “break” the idle tones behavior. Usually a
random or pseudo-random generator adds an analog
or digital error to the feedback loop of the delta-sigma
ADC in order to ensure that no tonal behavior can
happen at its outputs. This error is filter by the feedback
loop and typically has a zero average value so that the
converter static transfer function is not disturbed by the
dithering process. However, the dithering process
slightly increases the noise floor (it adds noise to the
part) while reducing its tonal behavior and thus
improving SFDR and THD. (See Figure 2-10 and
Figure 2-14). The dithering process scrambles the idle
tones into baseband white noise and ensures that
dynamic specs (SNR, SINAD, THD, SFDR) are less
signal dependent. The MCP3901 incorporates a proprietary dithering algorithm on both ADCs in order to
remove idle tones and improve THD, which is crucial
for power metering applications.
These idle tones are residues that are inherent to the
quantization process and the fact that the converter is
integrating at all times without being reset. They are
residues of the finite resolution of the conversion
process. They are very difficult to attenuate and they
are heavily signal dependent. They can degrade both
SFDR and THD of the converter, even for DC inputs.
They can be localized in the baseband of the converter
and thus difficult to filter from the actual input signal.
DS22192A-page 22
© 2009 Microchip Technology Inc.
MCP3901
4.16
Crosstalk
The crosstalk is defined as the perturbation caused by
one ADC channel on the other ADC channel. It is a
measurement of the isolation between the two ADCs
present in the chip.
This measurement is a two-step procedure:
1.
2.
Measure one ADC input with no perturbation on
the other ADC (ADC inputs shorted).
Measure the same ADC input with a
perturbation sine wave signal on the other ADC
at a certain predefined frequency.
The crosstalk is then the ratio between the output
power of the ADC when the perturbation is present and
when it is not divided by the power of the perturbation
signal.
A higher crosstalk value implies more independence
and isolation between the two channels.
The measurement of this signal is performed under the
following conditions:
•
•
•
•
GAIN = 1,
PRESCALE = 1,
OSR = 256,
MCLK = 4 MHz
Step 1
EQUATION 4-11:
Δ V OUT
PSRR ( dB ) = 20 log ⎛⎝ -------------------⎞⎠
Δ AV DD
Where VOUT is the equivalent input voltage that the
output code translates to with the ADC transfer
function. In the MCP3901 specification, AVDD varies
from 4.5V to 5.5V, and for AC PSRR a 50/60 Hz
sinewave is chosen centered around 5V with a
maximum 500 mV amplitude. The PSRR specification
is measured with AVDD = DVDD.
4.18
CMRR
This is the ratio between a change in the
common-mode input voltage and the ADC output
codes. It measures the influence of the common-mode
input voltage on the ADC outputs.
The CMRR specification can be DC (the
common-mode input voltage is taking multiple DC
values) or AC (the common-mode input voltage is a
sinewave at a certain frequency with a certain common
mode). In AC, the amplitude of the sinewave is
representing the change in the power supply.
It is defined as:
EQUATION 4-12:
Δ V OUT
CMRR ( dB ) = 20 log ⎛ -----------------⎞
⎝ Δ V CM ⎠
• CH0+=CH0-=AGND
• CH1+=CH1-=AGND
Step 2
The crosstalk is then calculated with the following
formula:
Where VCM= (CHn+ + CHn-)/2 is the common-mode
input voltage and VOUT is the equivalent input voltage
that the output code translates to with the ADC transfer
function. In the MCP3901 specification, VCM varies
from -1V to +1V, and for AC specification a 50/60 Hz
sinewave is chosen centered around 0V with a 500 mV
amplitude.
EQUATION 4-10:
4.19
• CH0+=CH0-=AGND
• CH1+ - CH1-=1VP-P @ 50/60 Hz(Full-scale sine
wave)
Δ CH0Power
CTalk ( dB ) = 10 log ⎛ ---------------------------------⎞
⎝ Δ CH1Power⎠
4.17
PSRR
This is the ratio between a change in the power supply
voltage and the ADC output codes. It measures the
influence of the power supply voltage on the ADC
outputs.
The PSRR specification can be DC (the power supply
is taking multiple DC values) or AC (the power supply
is a sinewave at a certain frequency with a certain
common mode). In AC, the amplitude of the sinewave
is representing the change in the power supply.
It is defined as:
© 2009 Microchip Technology Inc.
ADC Reset Mode
ADC Reset mode (called also soft reset mode) can only
be entered through setting high the RESET<1:0> bits in
the configuration register. This mode is defined as the
condition where the converters are active but their
output is forced to 0.
The registers are not affected in this reset mode and
retain their values.
The ADCs can immediately output meaningful codes
after leaving reset mode (and after the sinc filter settling
time of 3/DRCLK). This mode is both entered and
exited through setting of bits in the configuration
register.
Each converter can be placed in soft reset mode
independently. The configuration registers are not
modified by the soft reset mode.
DS22192A-page 23
MCP3901
A data ready pulse will not be generated by any ADC
while in reset mode.
Reset mode also effects the modulator output block,
i.e. the MDAT pin, corresponding to the channel in
reset. If enabled, it provides a bitstream corresponding
to a zero output (a series of 0011 bits continuously
repeated).
When an ADC exists ADC reset mode, any phase
delay present before reset was entered will still be
present. If one ADC was not in reset, the ADC leaving
reset mode will resynchronize automatically the phase
delay relative to the other ADC channel per the phase
delay register block and give DR pulses accordingly.
If an ADC is placed in Reset mode while the other is
converting, it is not shutting down the internal clock.
When going back out of reset, it will be resynchronized
automatically with the clock that did not stop during
reset.
If both ADCs are in soft reset or shutdown modes, the
clock is no longer distributed to the digital core for low
power operation. Once any of the ADC is back to
normal operation, the clock is automatically distributed
again.
4.20
Hard Reset Mode (RESET = 0)
This mode is only available during a POR or when the
RESET pin is pulled low. The RESET pin low state
places the device in a hard reset mode.
In this mode all internal registers are reset to their
default state.
The DC biases for the analog blocks are still active, i.e.
the MCP3901 is ready to convert. However, this pin
clears all conversion data in the ADCs. In this mode the
MDAT outputs are in high impedance. The comparators
outputs of both ADCs are forced to their reset state
(0011). The SINC filters are all reset as well as their
double output buffers. See serial timing for minimum
pulse low time, in Section 1.0 “Electrical
Characteristics”.
During a hard reset, no communication with the part is
possible. The digital interface is maintained in a reset
state.
4.21
ADC Shutdown Mode
ADC shutdown mode is defined as a state where the
converters and their biases are off, consuming only
leakage current. After this is removed, start-up delay
time (SINC filter settling time will occur before
outputting meaningful codes. The start-up delay is
needed to power-up all DC biases in the channel that
was in shutdown. This delay is the same than tPOR and
any DR pulse coming within this delay should be
discarded.
DS22192A-page 24
Each converter can be placed in shutdown mode
independently. The CONFIG registers are not modified
by the shutdown mode. This mode is only available
through programming of the SHUTDOWN<1:0> bits
the CONFIG2 register.
The output data is flushed to all zeros while in ADC
shutdown. No data ready pulses are generated by any
ADC while in ADC shutdown mode.
ADC shutdown mode also effects the modulator output
block, i.e. if MDAT of the channel in shutdown mode is
enabled, this pin will provide a bitstream corresponding
to a zero output (series of 0011 bits continuously
repeated).
When an ADC exits ADC shutdown mode, any phase
delay present before shutdown was entered will still be
present. If one ADC was not in shutdown, the ADC
leaving
shutdown
mode
will
resynchronize
automatically the phase delay relative to the other ADC
channel per the phase delay register block and give DR
pulses accordingly.
If an ADC is placed in Shutdown mode while the other
is converting, it is not shutting down the internal clock.
When going back out of shutdown, it will be
resynchronized automatically with the clock that did not
stop during reset.
If both ADCs are in ADC reset or ADC shutdown
modes, the clock is no more distributed to the digital
core for low power operation. Once any of the ADC is
back to normal operation, the clock is automatically
distributed again.
4.22
Full Shutdown Mode
The lowest power consumption can be achieved when
SHUTDOWN<1:0>=11, VREFEXT=CLKEXT=1. This
mode is called “Full shutdown mode”, and no analog
circuitry is enabled. In this mode, the POR AVDD
monitoring circuit is also disabled. When the clock is
idle (CLKI = 0 or 1 continuously), no clock is propagated throughout the chip. Both ADCs are in shutdown,
the internal voltage reference is disabled and the internal oscillator is disabled.
The only circuit that remains active is the SPI interface
but this circuit does not induce any static power
consumption. If SCK is idle, the only current
consumption comes from the leakage currents induced
by the transistors and is less than 1 µA on each power
supply.
This mode can be used to power down the chip
completely and avoid power consumption when there
is no data to convert at the analog inputs. Any SCK or
MCLK edge coming while on this mode will induce
dynamic power consumption.
Once any of the SHUTDOWN, CLKEXT and VREFEXT
bits returns to 0, the POR AVDD monitoring block is
back to operation and AVDD monitoring can take place.
© 2009 Microchip Technology Inc.
MCP3901
5.0
DEVICE OVERVIEW
5.3
5.1
Analog Inputs (CHn+/-)
5.3.1
The MCP3901 analog inputs can be connected directly
to current and voltage transducers (such as shunts,
current transformers, or Rogowski coils). Each input
pin is protected by specialized ESD structures that are
certified to pass 7 kV HBM and 400V MM contact
charge. These structures allow bipolar ±6V continuous
voltage with respect to AGND, to be present at their
inputs without the risk of permanent damage.
Both channels have fully differential voltage inputs for
better noise performance. The absolute voltage at each
pin relative to AGND should be maintained in the ±1V
range during operation in order to ensure the specified
ADC accuracy. The common-mode signals should be
adapted to respect both the previous conditions and
the differential input voltage range. For best performance, the common-mode signals should be maintained to AGND.
5.2
Programmable Gain Amplifiers
(PGA)
The two Programmable Gain Amplifiers (PGAs) reside
at the front-end of each Delta-Sigma ADC. They have
two functions : translate the common-mode of the input
from AGND to an internal level between AGND and
AVDD , and amplify the input differential signal. The
translation of the common mode does not change the
differential signal but recenters the common-mode so
that the input signal can be properly amplified.
The PGA block can be used to amplify very low signals,
but the differential input range of the delta-sigma
modulator must not be exceeded. The PGA is
controlled by the PGA_CHn<2:0> bits in the GAIN
register. The following table represents the gain
settings for the PGA:
TABLE 5-1:
Delta-Sigma Modulator
ARCHITECTURE
Both ADCs are identical in the MCP3901 and they
include a second-order modulator with a multi-bit DAC
architecture (see Figure 5-1). The quantizer is a flash
ADC composed of 4 comparators with equally spaced
thresholds and a thermometer output coding. The
proprietary 5-level architecture ensures minimum
quantization noise at the outputs of the modulators
without disturbing linearity or inducing additional
distortion. The sampling frequency is DMCLK (typically
1 MHz with MCLK=4 MHz) so the modulator outputs
are refreshed at a DMCLK rate. The modulator outputs
are available in the MOD register or serially transferred
on each MDAT pin.
Both modulators also include a dithering algorithm that
can be enabled through the DITHER<1:0> bits in the
configuration register. This dithering process improves
THD and SFDR (for high OSR settings) while
increasing slightly the noise floor of the ADCs. For
power metering applications and applications that are
distortion-sensitive, it is recommended to keep
DITHER enabled for both ADCs. In the case of power
metering applications, THD and SFDR are critical
specifications to optimize SNR (noise floor) is not really
problematic due to large averaging factor at the output
of the ADCs, therefore even for low OSR settings, the
dithering algorithm will show a positive impact on the
performance of the application.
Figure 5-1 represents a simplified block diagram of the
Delta-Sigma ADC present on MCP3901.
Loop
Filter
Output
Differential
SecondOrder
Integrator
Voltage Input
PGA CONFIGURATION
SETTING
Gain
PGA_CHn<2:0>
Gain
(V/V)
Gain
(dB)
vIN Range
(V)
0
0
0
1
0
±0.5
0
0
1
2
6
±0.25
0
1
0
4
12
±0.125
0
1
1
8
18
±0.0625
1
0
0
16
24
±0.03125
1
0
1
32
30
±0.015625
© 2009 Microchip Technology Inc.
Quantizer
Bitstream
5-level
Flash ADC
DAC
MCP3901 Sigma-Delta Modulator
FIGURE 5-1:
Block Diagram.
Simplified Delta-Sigma ADC
DS22192A-page 25
MCP3901
5.3.2
MODULATOR INPUT RANGE AND
SATURATION POINT
For a specified voltage reference value of 2.4V, the
modulators specified differential input range is
±500 mV. The input range is proportional to VREF and
scales according to the VREF voltage. This range is
guaranteeing the stability of the modulator over
amplitude and frequency. Outside of this range, the
modulator is still functional, however its stability is no
longer guaranteed and therefore it is not recommended
to exceed this limit. The saturation point for the
modulator is VREF/3 since the transfer function of the
ADC includes a gain of 3 by default (independent from
the PGA setting. See Section 5.6 “ADC OUTPUT
CODING”).
5.3.3
BOOST MODE
The Delta-Sigma modulators also include an
independent BOOST mode for each channel. If the
corresponding BOOST<1:0> bit is enabled, the power
consumption of the modulator is multiplied by 2 and its
bandwidth is increased to be able to sustain AMCLK
clock frequencies up to 8.192 MHz while keeping the
ADC accuracy. When disabled, the power consumption
is back to normal and the AMCLK clock frequencies
can only reach up to 5 MHz without affecting ADC
accuracy.
5.4
Modulator Output Block
If the user wishes to use the modulator output of the
device the appropriate bits to enable the modulator
output must be set in the configuration register.
When MODOUT<1:0> is enabled, the modulator
output of the corresponding channel is present at the
corresponding MDAT output pin as soon as the
command is placed.
Since the sigma-delta modulators have a 5-level output
given by the state of 4 comparators with thermometer
coding, their outputs can be represented on 4 bits, each
bit giving the state of the corresponding comparator
(See Table 5-2). These bits are present on the MOD
register and are updated at the DMCLK rate.
In order to output the comparators result on a separate
pin (MDAT0 and MDAT1), these comparator output bits
have been arranged to be serially output at the AMCLK
rate (See Figure 5-2).
TABLE 5-2:
DELTA-SIGMA MODULATOR
CODING
Comp<3:0>
Code
Modulator
Output Code
MDAT Serial
Stream
1111
+2
1111
0111
+1
0111
0011
0
0011
0001
-1
0001
0000
-2
0000
COMP COMP COMP COMP
<0>
<1>
<3>
<2>
AMCLK
DMCLK
MDAT+2
MDAT+1
MDAT+0
MDAT-1
MDAT-2
FIGURE 5-2:
MDAT Serial Outputs in
Function of the Modulator Output Code.
Since the reset and shutdown SPI commands are
asynchronous, the MDAT pins are resynchronized with
DMCLK after each time the part goes out of reset and
shutdown.
This means that the first output of MDAT after RESET
is always 0011 after the first DMCLK rising edge.
This 1-bit serial bitstream is the same that would be
produced by a 1-bit DAC modulator with a sampling
frequency of AMCLK. The modulator can either be
considered like a 5 level-output at DMCLK rate or 1-bit
output at AMCLK rate. These two representations are
interchangeable. The MDAT outputs can therefore be
used in any application that requires 1-bit modulator
outputs. These applications will often integrate and
filter the 1-bit output with SINC or more complex
decimation filters computed by a MCU or a DSP.
DS22192A-page 26
© 2009 Microchip Technology Inc.
MCP3901
SINC3 Filter
Both ADCs present in the MCP3901 include a
decimation filter that is a third-order sinc (or notch)
filter. This filter processes the multi-bit bitstream into 16
or 24 bits words (depending on the WIDTH
configuration bit). The settling time of the filter is 3
DMCLK periods. It is recommended to discard
unsettled data to avoid data corruption which can be
done easily by setting the DR_LTY bit high in the
STATUS/COM register.
The resolution achievable at the output of the sinc filter
(the output of the ADC) is dependant on the OSR and
is summarized with the following table:
TABLE 5-3:
The Normal-Mode Rejection Ratio (NMRR) or gain of
the transfer function is given by the following equation:
EQUATION 5-2:
OSR<1:0>
OSR
0
0
32
17
0
1
64
20
1
0
128
23
1
1
256
24
For 24 -bit output mode (WIDTH=1), the output of the
sinc filter is padded with least significant zeros for any
resolution less than 24 bits.
For 16-bit output modes, the output of the sinc filter is
rounded to the closest 16-bit number in order to
conserve only 16-bit words and to minimize truncation
error.
The gain of the transfer function of this filter is 1 at each
multiple of DMCLK (typically 1 MHz) so a proper
anti-aliasing filter must be placed at the inputs to
attenuate the frequency content around DMCLK and
keep the desired accuracy over the baseband of the
converter. This anti-aliasing filter can be a simple
first-order RC network with a sufficiently low time
constant to generate high rejection at DMCLK
frequency.
EQUATION 5-1:
3
or:
ADC RESOLUTION VS. OSR
ADC
Resolution
(bits)
No Missing
Codes
MAGNITUDE OF
FREQUENCY RESPONSE
H(f)
f
sin c ⎛⎝ π ⋅ ----------------------⎞⎠
DMCLK
NMRR ( f ) = ---------------------------------------------f
sin c ⎛ π ⋅ --------------------⎞
⎝ DRCLK⎠
f 3
sin c ⎛ π ⋅ -----⎞
⎝ f D⎠
NMRR ( f ) = ----------------------------f
sin c ⎛ π ⋅ ----⎞
⎝ f S⎠
where:
sin ( x )sin c ( x ) = -------------x
The Figure 5-3 shows the sinc filter frequency
response:
20
0
Magnitude (dB)
5.5
-20
-40
-60
-80
-100
-120
1
10
100
1000
10000
100000 1000000
Input Frequency (Hz)
FIGURE 5-3:
SINC Filter Response with
MCLK = 4 MHz, OSR = 64, PRESCALE = 1.
SINC FILTER TRANSFER
FUNCTION H(Z)
⎛ 1 – z – OSR ⎞
-⎟
H ( z ) = ⎜ -------------------------------⎝ OSR ( 1 – z –1 )⎠
3
Where:
2πfj
z = exp ⎛ ----------------------⎞
⎝ DMCLK⎠
© 2009 Microchip Technology Inc.
DS22192A-page 27
MCP3901
5.6
ADC OUTPUT CODING
In case of positive saturation (CHn+ - CHn- > VREF/3),
the output is locked to 7FFFFF for 24 bit mode (7FFF
for 16 bit mode). In case of negative saturation (CHn+
- CHn- <-VREF/3), the output code is locked to 800000
for 24-bit mode (8000 for 16 bit mode).
The second order modulator, SINC3 filter, PGA, VREF
and analog input structure all work together to produce
the device transfer function for the analog to digital conversion, Equation 5-3.
Equation 5-3 is only true for DC inputs. For AC inputs,
this transfer function needs to be multiplied by the
transfer function of the SINC3 filter (see Equation 5-1
and Equation 5-2).
The channel data is either a 16-bit or 24-bit word,
presented in 23-bit or 15-bit plus sign, two’s
complement format and is MSB (left) justified.
The ADC data is two or three bytes wide depending on
the WIDTH bit of the associated channel. The 16-bit
mode includes a round to the closest 16-bit word
(instead of truncation) in order to improve the accuracy
of the ADC data.
EQUATION 5-3:
( CH n+ – CH n- )
DATA_CHn = ⎛ -------------------------------------⎞ × 8,388,608 × G × 3
⎝ V REF+ – V REF- ⎠
(For 24-bit Mode Or WIDTH = 1)
( CH n+ – CH n- )
DATA_CHn = ⎛ -------------------------------------⎞ × 32, 768 × G × 3
⎝ V REF+ – V REF- ⎠
(For 16-bit Mode Or WIDTH = 0)
5.6.1
ADC RESOLUTION AS A FUNCTION
OF OSR
The ADC resolution is a function of the OSR
(Section 5.5 “SINC3 Filter”). The resolution is the
same for both channels. No matter what the resolution
is, the ADC output data is always presented in 24-bit
words, with added zeros at the end if the OSR is not
large enough to produce 24-bit resolution (left
justification).
TABLE 5-4:
OSR = 256 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First)
0
0
0
1
1
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
TABLE 5-5:
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
Decimal
0x7FFFFF
0x7FFFFE
0x000000
0xFFFFFF
0x800001
0x800000
+ 8,388,607
+ 8,388,606
0
-1
- 8,388,607
- 8,388,608
OSR = 128 OUTPUT CODE EXAMPLES
ADC Output Code (MSB First)
0
0
0
1
1
1
Hexadecimal
1
1
0
1
0
0
1
1
0
1
0
0
DS22192A-page 28
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
0
0
0
0
0
Hexadecimal
Decimal
23-bit Resolution
0x7FFFFE
0x7FFFFC
0x000000
0xFFFFFE
0x800002
0x800000
+ 4,194,303
+ 4,194,302
0
-1
- 4,194,303
- 4,194,304
© 2009 Microchip Technology Inc.
MCP3901
TABLE 5-6:
OSR = 64 OUTPUT CODE EXAMPLES
ADC Output code (MSB First)
0
0
0
1
1
1
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
TABLE 5-7:
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
5.7
5.7.1
1
1
0
1
0
0
1
1
0
1
0
0
Decimal
20-bit resolution
0x7FFFF0
0x7FFFE0
0x000000
0xFFFFF0
0x800010
0x800000
+ 524, 287
+ 524, 286
0
-1
- 524,287
- 524, 288
Hexadecimal
Decimal
17-bit resolution
0x7FFF80
0x7FFF00
0x000000
0xFFFF80
0x800080
0x800000
+ 65, 535
+ 65, 534
0
-1
- 65,535
- 65, 536
OSR = 32 OUTPUT CODE EXAMPLES
ADC Output code (MSB First)
0
0
0
1
1
1
Hexadecimal
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
Voltage Reference
INTERNAL VOLTAGE REFERENCE
The MCP3901 contains an internal voltage reference
source specially designed to minimize drift over
temperature. In order to enable the internal voltage
reference, the VREFEXT bit in the configuration
register must be set to 0 (default mode). This internal
VREF supplies reference voltage to both channels. The
typical value of this voltage reference is 2.37V ±2%.
The internal reference has a very low typical
temperature coefficient of ±12 ppm/°C, allowing the
output codes to have minimal variation with respect to
temperature since they are proportional to (1/VREF).
The noise of the internal voltage reference is low
enough not to significantly degrade the SNR of the
ADC if compared to a precision external low-noise
voltage reference.
The output pin for the internal voltage reference is
REFIN+/OUT.
When the internal voltage reference is enabled,
REFIN- pin should always be connected to AGND.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
These bypass capacitors are not mandatory for correct
ADC operation, but removing these capacitors may
degrade accuracy of the ADC. The bypass capacitors
also help for applications where the voltage reference
output is connected to other circuits. In this case,
additional buffering may be needed as the output drive
capability of this output is low.
5.7.2
DIFFERENTIAL EXTERNAL
VOLTAGE INPUTS
When the VREFEXT bit is high, the two reference pins
(REFIN+/OUT, REFIN-) become a differential voltage
reference input. The voltage at the REFIN+/OUT is
noted VREF+ and the voltage at the REFIN- pin is noted
VREF-. The differential voltage input value is given by
the following equation:
VREF=VREF+ - VREFThe specified VREF range is from 2.2V to 2.6V. The
REFIN- pin voltage (VREF-) should be limited to +/-0.3V.
Typically, for single-ended reference applications, the
REFIN- pin should be directly connected to AGND.
For optimal ADC accuracy, appropriate bypass
capacitors should be placed between REFIN+/OUT
and AGND. De-coupling at the sampling frequency,
around 1 MHz, is important for any noise around this
frequency will be aliased back into the conversion data.
0.1 µF ceramic and 10 µF tantalum capacitors are
recommended.
© 2009 Microchip Technology Inc.
DS22192A-page 29
MCP3901
5.8
Power-on Reset
5.9
The MCP3901 contains an internal POR circuit that
monitors analog supply voltage AVDD during operation.
The typical threshold for a power-up event detection is
4.2V +/-5%. The POR circuit has a built-in hysteresis
for improved transient spikes immunity that has a
typical value of 200 mV. Proper decoupling capacitors
(0.1 µF ceramic and 10 µF tantalum) should be
mounted as close as possible to the AVDD pin,
providing additional transient immunity.
Figure 5-4 illustrates the different conditions at
power-up and a power-down event in the typical
conditions. All internal DC biases are not settled until at
least 50 µs after system POR. Any DR pulses during
this time after system reset should be ignored. After
POR, DR pulses are present at the pin with all the
default conditions in the configuration registers.
Both AVDD and DVDD power supplies are independent.
Since AVDD is the only power supply that is monitored,
it is highly recommended to power up DVDD first as a
power-up sequence. If AVDD is powered up first, it is
highly recommended to keep RESET pin low during the
whole power-up sequence.
AVDD
When the RESET pin is low, both ADCs will be in Reset
and output code 0x0000h. The RESET pin performs a
hard reset (DC biases still on, part ready to convert)
and clears all charges contained in the sigma delta
modulators. The comparators output is 0011 for each
ADC.
The SINC filters are all reset, as well as their double
output buffers. This pin is independent of the serial
interface. It brings the CONFIG registers to the default
state. When RESET is low, any write with the SPI
interface will be disabled and will have no effect. All
output pins (SDO, DR, MDAT0/1) are high impedance,
and no clock is propagated through the chip.
5.10
Phase Delay Block
The MCP3901 incorporates a phase delay generator
which ensures that the two ADCs are converting the
inputs with a fixed delay between them. The two ADCs
are synchronously sampling but the averaging of
modulator outputs is delayed so that the SINC filter
outputs (thus the ADC outputs) show a fixed phase
delay, as determined by the PHASE register setting.
The phase register (PHASE<7:0>) is a 7 bit + sign,
MSB first, two's complement register that indicates how
much phase delay there is to be between Channel 0
and Channel 1. The reference channel for the delay is
Channel 1 (typically the voltage channel for power
metering applications). When PHASE<7:0> is positive,
Channel 0 is lagging versus Channel 1. When
PHASE<7:0> is negative, Channel 0 is leading versus
Channel 1. The amount of delay between two ADC
conversions is given by the following formula:
5V
4.2V
4V
50 µs
tPOR
Time
0V
DEVICE
MODE
RESET Effect On Delta Sigma
Modulator/SINC Filter
RESET
FIGURE 5-4:
PROPER
OPERATION
RESET
EQUATION 5-4:
Register CodeDelay = Phase
------------------------------------------------DMCLK
Power-on Reset Operation.
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration with MCLK = 4 MHz.
The data ready signals are affected by the phase delay
settings. Typically, the time difference between the data
ready pulses of channel 0 and channel 1 is equal to the
phase delay setting.
Note:
DS22192A-page 30
A detailed explanation of the data ready
pin (DR) with phase delay is present in
Section 6.10 “Data Ready Latches And
Data Ready Modes (DRMODE<1:0>)”.
© 2009 Microchip Technology Inc.
MCP3901
5.10.1
5.11
PHASE DELAY LIMITS
The Phase delay can only go from -OSR/2 to +OSR/2 - 1.
This sets the fine phase resolution. The phase register is
coded with 2's complement.
If larger delays between the two channels are needed,
they can be implemented externally to the chip with a
MCU. A FIFO in the MCU can save incoming data from
the leading channel for a number N of DRCLK clocks.
In this case, DRCLK would represent the coarse timing
resolution, and DMCLK the fine timing resolution. The
total delay will then be equal to:
Delay = N/DRCLK + PHASE/DMCLK
The Phase delay register can be programmed once
with the OSR=256 setting and will adjust to the OSR
automatically afterwards without the need to change
the value of the PHASE register.
• OSR=256: the delay can go from -128 to +127.
PHASE<7> is the sign bit. Phase<6> is the MSB
and PHASE<0> the LSB.
• OSR=128: the delay can go from -64 to +63.
PHASE<6> is the sign bit. Phase<5> is the MSB
and PHASE<0> the LSB.
• OSR=64: the delay can go from -32 to +31.
PHASE<5> is the sign bit. Phase<4> is the MSB
and PHASE<0> the LSB.
• OSR=32: the delay can go from -16 to +15.
PHASE<4> is the sign bit. Phase<3> is the MSB
and PHASE<0> the LSB.
TABLE 5-8:
PHASE VALUES WITH
MCLK = 4 MHZ, OSR = 256
Hex
Delay
(CH0 relative
to CH1)
0 1 1 1 1 1 1 1
0x7F
+ 127 µs
0 1 1 1 1 1 1 0
0x7E
+ 126 µs
0 0 0 0 0 0 0 1
0x01
+ 1 µs
Phase Register
Value
0 0 0 0 0 0 0 0
0x00
0 µs
1 1 1 1 1 1 1 1
0xFF
- 1 µs
1 0 0 0 0 0 0 1
0x81
- 127 µs
1 0 0 0 0 0 0 0
0x80
-128 µs
© 2009 Microchip Technology Inc.
Crystal Oscillator
The MCP3901 includes a Pierce type crystal oscillator
with very high stability and ensures very low tempco
and jitter for the clock generation. This oscillator can
handle up to 16.384 MHz crystal frequencies provided
that proper load capacitances and quartz quality factor
are used.
For keeping specified ADC accuracy, AMCLK should
be kept between 1 and 5 MHz with BOOST off or 1 and
8.192 MHz with BOOST on. Larger MCLK frequencies
can be used provided the prescaler clock settings allow
the AMCLK to respect these ranges.
For a proper start-up, the load capacitors of the crystal
should be connected between OSC1 and DGND and
between OSC2 and DGND. They should also respect
the following equation:
EQUATION 5-5:
2
6
f
R M < 1.6 × 10 × ⎛⎝ -----------------⎞⎠
C LOAD
where f is the crystal frequency in MHz, CLOAD, the load
capacitance in pF including parasitics from the PCB
and RM the motional resistance in ohms of the quartz
(it also defines the quality factor).
When CLKEXT=1, the crystal oscillator is bypassed by
a digital buffer to allow direct clock input for an external
clock (see Figure 1-5).
DS22192A-page 31
MCP3901
NOTES:
DS22192A-page 32
© 2009 Microchip Technology Inc.
MCP3901
6.0
6.1
SERIAL INTERFACE
DESCRIPTION
A5
A4
A3
A2
A1
A0
Overview
The MCP3901 device is compatible with SPI modes 0,0
and 1,1. Data is clocked out of the MCP3901 on the falling edge of SCK, and data is clocked into the MCP3901
on the rising edge of SCK. In these modes SCK can
idle either high, or low.
Each SPI communication starts with a CS falling edge
and stops with the CS rising edge. Each SPI
communication is independent. When CS is high, SDO
is in high impedance, transitions on SCK and SDI have
no effect. Additional controls: RESET, DR, MDAT0/1
are also provided on separate pins for advanced
communication.
The MCP3901 interface has a simple command
structure. The first byte transmitted is always the
CONTROL byte and is followed by data bytes that are
8-bit wide. Both ADCs are continuously converting data
by default and can be reset or shutdown through a
CONFIG2 register setting.
Since each ADC data is either 16 or 24 bits (depending
on the WIDTH bits), the internal registers can be
grouped together with various configurations (through
the READ bits) in order to allow easy data retrieval
within only one communication. For device reads, the
internal address counter can be automatically
incremented in order to loop through groups of data
within the register map. The SDO will then output the
data located at the ADDRESS (A<4:0>) defined in the
control byte and then ADDRESS+1 depending on the
READ<1:0> bits which select the groups of registers.
These groups are defined in the Section 7.1 “ADC
Channel Data Output Registers” (Register Map).
The data ready pin (DR) can be used as an interrupt for
a MCU and outputs pulses when new ADC channel
data is available. The RESET pin acts like a hard reset
and can reset the part to its default power-up
configuration. The MDAT0/1 pins give the modulator
outputs (see Section 5.4 “Modulator Output Block”).
6.2
A6
Control Byte
The control byte of the MCP3901 contains two device
address bits A<6:5>, 5 register address bits A<4:0>,
and a read/write bit (R/W). The first byte transmitted to
the MCP3901 is always the control byte.
The MCP3901 interface is device addressable
(through A<6:5>) so that multiple MCP3901 chips can
be present on the same SPI bus with no data bus
contention. This functionality enables three-phase
power metering systems containing three MCP3901
chips controlled by a single SPI bus (single CS, SCK,
SDI and SDO pins).
© 2009 Microchip Technology Inc.
Device
Address
Bits
FIGURE 6-1:
R/W
Read
Write Bit
Register
Address Bits
Control Byte.
The default device address bits are 00. Contact the
Microchip factory for additional device address bits. For
more information, please see the Section “Product
Identification System”.
A read on undefined addresses will give an all zeros
output on the first and all subsequent transmitted bytes.
A write on undefined address will have no effect and
will not increment the address counter either.
The register map is defined in Section 7.1 “ADC
Channel Data Output Registers”.
6.3
Reading from the Device
The first data byte read is the one defined by the
address given in the CONTROL byte. After this first
byte is transmitted, if CS pin is maintained low, the
communication continues and the address of the next
transmitted byte is determined by the status of the
READ bits in the STATUS/COM register. Multiple
looping configurations can be defined through the
READ<1:0> bits for the address increment (see
Section 6.6 “SPI MODE 0,0 - Clock Idle Low, Read/
Write Examples”).
6.4
Writing to the Device
The first data byte written is the one defined by the
address given in the control byte. The write
communication automatically increments the address
for subsequent bytes.
The address of the next transmitted byte within the
same communication (CS stays low) is the next
address defined on the register map. At the end of the
register map, the address loops to the beginning of the
register map. Writing a non-writable register has no
effect.
SDO pin stays high impedance during a write
communication.
6.5
SPI MODE 1,1 - Clock Idle High,
Read/Write Examples
In this SPI mode, the clock idles high. For the
MCP3901 this means that there will be a falling edge
before there is a rising edge.
Note:
Changing from a SPI Mode 1,1 to a SPI
Mode 0,0 is possible but needs a RESET
pulse in between to ensure correct
communication.
DS22192A-page 33
MCP3901
:
CS
Data Transitions on
the Falling Edge
MCU and MCP3901 Latch
Bits on the Rising Edge
SCK
SDI
A6 A5 A4 A3 A2 A1 A0 R/W
HI-Z
HI-Z
SDO
D0
D7 D6 D5 D4 D3 D2 D1
(ADDRESS) DATA
FIGURE 6-2:
HI-Z
D7 D6 D5 D4 D3 D2 D1
D0
(ADDRESS + 1) DATA
Device Read (SPI Mode 1,1 - Clock Idles High).
CS
Data Transitions on
the Falling Edge
MCU and MCP3901 Latch
Bits on the Rising Edge
SCK
SDI
A6 A5 A4 A3 A2 A1
A0
D7 D6 D5 D4 D3 D2 D1
R/W
(ADDRESS) DATA
HI-Z
SDO
D1
D0
(ADDRESS + 1) DATA
HI-Z
HI-Z
FIGURE 6-3:
6.6
D7 D6 D5 D4 D3 D2
D0
Device Write (SPI Mode 1,1 - Clock Idles High).
SPI MODE 0,0 - Clock Idle Low,
Read/Write Examples
In this SPI mode, the clock idles low. For the MCP3901
this means that there will be a rising edge before there
is a falling edge.
CS
Data Transitions on
the Falling Edge
MCU and MCP3901 Latch
Bits on the Rising Edge
SCK
SDI
SDO
A6 A5 A4 A3 A2 A1 A0 R/W
HI-Z
HI-Z
D7
D6 D5 D4 D3 D2 D1
D0
D7
(ADDRESS) DATA
FIGURE 6-4:
DS22192A-page 34
D6 D5 D4 D3 D2 D1 D0
D7 OF (ADDRESS + 2) DATA
HI-Z
(ADDRESS + 1) DATA
Device Read (SPI Mode 0,0 - Clock Idles Low).
© 2009 Microchip Technology Inc.
MCP3901
CS
Data Transitions on
the Falling Edge
MCU and MCP3901 Latch
Bits on the Rising Edge
SCK
SDI
A6 A5 A4 A3
A2 A1
A0 R/W
D6 D5 D4 D3 D2 D1 D0
D7
(ADDRESS) DATA
HI-Z
SDO
D6 D5 D4 D3 D2
D1 D0
D7 OF (ADDRESS + 2) DATA
(ADDRESS + 1) DATA
HI-Z
HI-Z
FIGURE 6-5:
6.7
D7
Device Write (SPI Mode 0,0 - Clock Idles Low).
Continuous Communication,
Looping On Address Sets
If the user wishes to read back either of the ADC
channels continuously, or both channels continuously,
the internal address counter of the MCP3901 can be
set to loop on specific register sets. In this case, there
is only one control byte on SDI to start the
communication. The part stays within the same loop
until CS returns high.
This internal address counter allows the following
functionality:
• Read one ADC channel data continuously
• Read both ADC channel data continuously (both
ADC data can be independent or linked with
DRMODE settings)
• Read continuously the entire register map
• Read continuously each separate register
• Read continuously all configuration registers
• Write all configuration registers in one
communication (see Figure 6-6)
The STATUS/COM register contains the loop settings
for the internal address counter (READ<1:0>). The
internal address counter can either stay constant
(READ<1:0>=00) and read continuously the same
byte, or it can auto-increment and loop through the
register groups defined below (READ<1:0>=01),
register types (READ<1:0>=10) or the entire register
map (READ<1:0>=11).
Each channel is configured independently as either a
16-bit or 24-bit data word depending on the setting of
the corresponding WIDTH bit in the CONFIG1 register.
For continuous reading, in the case of WIDTH=0
(16-bit), the lower byte of the ADC data is not accessed
and the part jumps automatically to the following
address (the user does not have to clock out the lower
byte since it becomes undefined for WIDTH=0).
The following figure represents a typical continuous
read communication with the default settings
(DRMODE<1:0>=00, READ<1:0>=10) for both WIDTH
settings. This configuration is typically used for power
metering applications.
CS
SCK
SDI
SDO
CH0 ADC
ADDR/R
CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC
Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte
CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC
Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte
DR
These bytes are not present when WIDTH=0 (16-bit mode)
FIGURE 6-6:
Typical Continuous Read Communication.
© 2009 Microchip Technology Inc.
DS22192A-page 35
MCP3901
6.7.1
CONTINUOUS WRITE
The following register sets are defined as groups:
Both ADCs are powered up with their default
configurations, and begin to output DR pulses
immediately (RESET<1:0> and SHUTDOWN<1:0>
bits are off by default).
TABLE 6-1:
REGISTER GROUPS
GROUP
The default output codes for both ADCs are all zeros.
The default modulator output for both ADCs is 0011
(corresponding to a theoretical zero voltage at the
inputs). The default phase is zero between the two
channels.
ADDRESSES
ADC DATA CH0
0x00 - 0x02
ADC DATA CH1
0x03 - 0x05
MOD, PHASE, GAIN
0x06 - 0x08
CONFIG, STATUS
0x09 - 0x0B
The following register sets are defined as types:
It is recommended to enter into ADC reset mode for
both ADCs just after power-up because the desired
MCP3901 register configuration may not be the default
one and in this case, the ADC would output undesired
data. Within the ADC reset mode (RESET<1:0>=11),
the user can configure the whole part with a single communication. The write commands increment
automatically the address so that the user can start
writing the PHASE register and finish with the
CONFIG2 register in only one communication (see
Figure 6-6). The RESET<1:0> bits are in the CONFIG2
register to allow to exit the soft reset mode and have
the whole part configured and ready to run in only one
command.
TABLE 6-2:
REGISTER TYPES
TYPE
ADDRESSES
ADC DATA
(Both Channels)
0x00 - 0x05
CONFIGURATION
0x06 - 0x0B
6.8
Situations that Reset ADC Data
Immediately after the following actions, the ADCs are
temporarily reset in order to provide proper operation:
1.
2.
3.
4.
5.
Change in PHASE register.
Change in the OSR setting.
Change in the PRESCALE setting.
Overwrite of same PHASE register value.
Change in CLKEXT bit in the CONFIG2 register
modifying internal oscillator state.
After these temporary resets, the ADCs go back to the
normal operation with no need for an additional
command. These are also the settings where the DR
position is affected. The PHASE register can be used
to serially soft reset the ADCs without using the RESET
bits in the configuration register if the same value is
written in the PHASE register.
AVDD
CS
SCK
00011000
SDI
CONFIG2 ADDR/W
11XXXXXX
CONFIG2
Optional RESET of both ADCs
FIGURE 6-7:
DS22192A-page 36
00001110
PHASE ADDR/W
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
xxxxxxxx
PHASE
GAIN
STATUS/COM
CONFIG1
CONFIG2
One command for writing complete configuration
Recommended Configuration Sequence at Power Up.
© 2009 Microchip Technology Inc.
MCP3901
6.9
Data Ready Pin (DR)
To signify when channel data is ready for transmission,
the data ready signal is available on the data ready pin
(DR) through an active low pulse at the end of a
channel conversion.
The data ready pin outputs an active low pulse with a
period is equal to DRCLK clock period and with a width
equal to one DMCLK period.
When not active low, this pin can either be in high
impedance (when DR_HIZN=0) or in a defined logic
high state (when DR_HIZN=1). This is controlled
through the configuration registers. This allows multiple
devices to share the same data ready pin (with a
pull-up resistor connected between DR and DVDD) in
3-phase energy meter designs to reduce
microcontroller pin count. A single device on the bus
does not require a pull-up resistor.
After a data ready pulse has occurred, the ADC output
data can be read through SPI communication. Two sets
of latches at the output of the ADC prevent the
communication from outputting corrupted data (see
Section 6.10 “Data Ready Latches And Data Ready
Modes (DRMODE<1:0>)”).
The CS pin has no effect on the DR pin, which means
even if CS is high, data ready pulses will be provided
(except when the configuration prevents from
outputting data ready pulses). The DR pin can be used
as an interrupt when connected to a MCU or DSP.
While RESET pin is low, the DR pin is not active.
6.10
Data Ready Latches And Data
Ready Modes (DRMODE<1:0>)
To ensure that both channel ADC data are present at
the same time for SPI read, regardless of phase delay
settings for either or both channels, there are two sets
of latches in series with both the data ready and the
‘read start’ triggers.
The first set of latches holds each output when data is
ready and latches both outputs together when
DRMODE<1:0>=00. When this mode is on, both ADCs
work together and produce one set of available data
after each data ready pulse (that corresponds to the
lagging ADC data ready). The second set of latches
ensures that when reading starts on an ADC output, the
corresponding data is latched so that no data
corruption can occur.
If an ADC read has started, in order to read the
following ADC output, the current reading needs to be
completed (all bits must be read from the ADC output
data registers).
6.10.1
DATA READY PIN (DR) CONTROL
USING DRMODE BITS
There are four modes that control the data ready
pulses, and these modes are set with the
DRMODE<1:0> bits in the STATUS/COM register. For
power metering applications, DRMODE<1:0>=00 is
recommended (default mode).
The position of DR pulses vary with respect to this
mode, to the OSR and to the PHASE settings:
• DRMODE<1:0> = 11: Both Data Ready pulses
from ADC Channel 0 and ADC Channel 1 are
output on DR pin.
• DRMODE<1:0> = 10: Data Ready pulses from
ADC Channel 1 are output on DR pin. DR from
ADC Channel 0 are not present on the pin.
• DRMODE<1:0> = 01: Data Ready pulses from
ADC Channel 0 are output on DR pin. DR from
ADC Channel 1 are not present on the pin.
• DRMODE<1:0> = 00: (Recommended, and
Default Mode). Data Ready pulses from the
lagging ADC between the two are output on DR
pin. The lagging ADC depends on the phase
register and on the OSR. In this mode the two
ADCs are linked together so their data is latched
together when the lagging ADC output is ready.
© 2009 Microchip Technology Inc.
DS22192A-page 37
MCP3901
6.10.2
DR PULSES WITH SHUTDOWN OR
RESET CONDITIONS
There will be no DR pulses if DRMODE<1:0>=00 when
either one or both of the ADCs are in reset or shutdown.
In Mode 00, a DR pulse only happens when both ADCs
are ready. Any DR pulse will correspond to one data on
both ADCs. The two ADCs are linked together and act
as if there was only on channel with the combined data
of both ADCs. This mode is very practical when both
ADC channel data retrieval and processing need to be
synchronized, as in power metering applications.
Note:
Figure 6-8 represents the behavior of the data ready
pin with the different DRMODE and DR_LTY configurations, while shutdown or resets are applied.
If DRMODE<1:0>=11, the user will still be
able to retrieve the DR pulse for the ADC
not in shutdown or reset, i.e. only 1 ADC
channel needs to be awake.
DS22192A-page 38
© 2009 Microchip Technology Inc.
MCP3901
RESET
RESET<0> or
SHUTDOWN<0>
RESET<1> or
SHUTDOWN<1>
DRMODE=00; DR
DRMODE=01; DR
DRMODE=10; DR
DRMODE=11; DR
DRMODE=00; DR
DRMODE=01; DR
DRMODE=10; DR
DRMODE=11; DR
3*DRCLK period
DRCLK period
1 DMCLK period
D6
DRCLK period
D5
D9
D4
D8
D16 D17
D3
D7
D14 D15
D2
D6
D12 D13
D6
D1
D5
D10 D11
D5
D6
D0
D4
D8 D9
D4
D5
D9
D7
D3
D7
D3
D4
D8
D6
D2
D6
D3
D7
D5
D1
D5
D6
D4
D0
D3 D4
D5
D3
D1 D2
D2
D4
D9
D2
D0
D1
D2
D3
D8
D1
D0
D1
D2
D7
D0
D0
D1
D6
D10
D7
D0
D5
D7
D4
D6
D3
D5
D2
D4
D1
D3
D0
D2
D9
D17
D1
D8
D15 D16
D0
D7
D13 D14
D7
D6
D11 D12
D6
D5
D9 D10
D5
D4
D8
D4
D3
D7
D3
D2
D5 D6
D2
D1
D3 D4
D1
D0
D1 D2
D0
D0
Data Ready pulse that appears only when DR_LTY=0
D8
D18
D8
D18
D8
D11
D9
D19
D9
D19
D9
D12
Internal reset synchronisation
(1 DMCLK period)
D11
3*DRCLK period
DRCLK period
D12
D13
D14
D17
D10
D16
D34
D9
D15
D32 D33
D8
D30 D31
D13
D7
D29
D12
D16
D16
D14
D11
D15
D16
D15
D28
D14
D15
D14
D10
D26 D27
D13
D13
D14
D13
D9
D24 D25
D12
D12
D13
D12
D8
D22 D23
D11
D11
D12
D11
D7
D11
D10
D10
D20 D21
D10
D10
D19
D14
D18
D13
D17
D12
D16
D11
D15
D10
D14
D9
D13
D8
D16
D34
D17
D15
D32 D33
D16
D14
D30 D31
D15
D29
D14
D13
D28
D13
D12
D26 D27
D12
D11
D24 D25
D11
D10
D22 D23
D10
D20 D21
DS22192A-page 39
© 2009 Microchip Technology Inc.
DRMODE=00; DR
DRMODE=01; DR
DRMODE=10; DR
DRMODE=11; DR
DRMODE=00 : Select the lagging Data Ready
DRMODE=01 : Select the Data Ready on channel 0
DRMODE=10 : Select the Data Ready on channel 1
DRMODE=11 : Select both Data ready
Data Ready Behavior.
FIGURE 6-8:
PHASE > 0
PHASE = 0
PHASE < 0
MCP3901
NOTES:
DS22192A-page 40
© 2009 Microchip Technology Inc.
MCP3901
7.0
INTERNAL REGISTERS
The addresses associated with the internal registers
are listed below. A detailed description of the registers
follows. All registers are 8-bit long and can be
addressed separately. READ modes define the groups
and types of registers for continuous read
communication or looping on address sets.
.
TABLE 7-1:
REGISTER MAP
Address
Name
Bits
R/W
Description
0x00
DATA_CH0
24
R
Channel 0 ADC Data <23:0>, MSB First
0x03
DATA_CH1
24
R
Channel 1 ADC Data <23:0>, MSB First
0x06
MOD
8
R/W Delta Sigma Modulators Output Register
0x07
PHASE
8
R/W Phase Delay Configuration Register
0x08
GAIN
8
R/W Gain Configuration Register
0x09
STATUS/COM
8
R/W Status / Communication Register
0x0A
CONFIG1
8
R/W Configuration Register 1
0x0B
CONFIG2
8
R/W Configuration Register 2
READ<1:0>
0x01
0x02
0x03
DATA_CH1
0x04
0x05
MOD
0x06
PHASE
0x07
GAIN
0x08
STATUS/
COM
0x09
CONFIG1
0x0A
CONFIG2
0x0B
GROUP
0x00
DATA_CH0
GROUP GROUP GROUP
= “01”
© 2009 Microchip Technology Inc.
= “10”
= “11”
LOOP ENTIRE REGISTER MAP
Address
TYPE
Function
REGISTER MAP GROUPING
FOR CONTINUOUS READ
MODES
TYPE
TABLE 7-2:
DS22192A-page 41
MCP3901
7.1
ADC Channel Data Output
Registers
synchronously at a DRCLK rate. The three bytes can
be accessed separately if needed but are refreshed
synchronously.
The ADC Channel data output registers always contain
the most recent A/D conversion data for each channel.
These registers are read-only. They can be accessed
independently or linked together (with READ<1:0>
bits). These registers are latched when an ADC read
communication occurs. When a data ready event
occurs during a read communication, the most current
ADC data is also latched to avoid data corruption
issues. The three bytes of each channel are updated
REGISTER 7-1:
CHANNEL OUTPUT REGISTERS: ADDRESS 0X00-0X02: CH0; 0X03-0X05: CH1
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DATA_CHn
<23>
DATA_CHn
<22>
DATA_CHn
<21>
DATA_CHn
<20>
DATA_CHn
<19>
DATA_CHn
<18>
DATA_CHn
<17>
DATA_CHn
<16>
bit 23
bit 16
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DATA_CHn
<15>
DATA_CHn
<14>
DATA_CHn
<13>
DATA_CHn
<12>
DATA_CHn
<11>
DATA_CHn
<10>
DATA_CHn
<9>
DATA_CHn
<8>
bit 15
bit 8
R-0
R-0
R-0
R-0
R-0
R-0
R-0
R-0
DATA_CHn
<7>
DATA_CHn
<6>
DATA_CHn
<5>
DATA_CHn
<4>
DATA_CHn
<3>
DATA_CHn
<2>
DATA_CHn
<1>
DATA_CHn
<0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
DS22192A-page 42
x = Bit is unknown
© 2009 Microchip Technology Inc.
MCP3901
7.2
Modulator Output Register
The MOD register contains the most recent modulator
data output. The default value corresponds to an
equivalent input of 0V on both ADCs. Each bit in this
register corresponds to one comparator output on one
of the channels.
This register should be used as a read-only register.
(Note 1).
This register is updated at the refresh rate of DMCLK
(typically 1 MHz with MCLK=4 MHz).
See Section 5.4 “Modulator Output Block” for more
details.
.
REGISTER 7-2:
MODULATOR OUTPUT REGISTER (MOD): ADDRESS 0X06
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
R/W-1
R/W-1
COMP3
_CH1
COMP2
_CH1
COMP1
_CH1
COMP0
_CH1
COMP3
_CH0
COMP2
_CH0
COMP1
_CH0
COMP0
_CH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7:4
COMPn_CH1: Comparator Outputs from Channel 1 Modulator
bit 3:0
COMPn_CH0: Comparator Outputs from Channel 0 Modulator
Note 1:
x = Bit is unknown
This register can be written in order to overwrite modulator output data but any writing here will corrupt the
ADC_DATA on the next three data ready pulses.
© 2009 Microchip Technology Inc.
DS22192A-page 43
MCP3901
7.3
PHASE Register
7.3.1
The PHASE register (PHASE<7:0>) is a 7 bits + sign
MSB first two's complement register that indicates how
much phase delay there should be between Channel 0
and Channel 1.
The reference channel for the delay is channel 1
(typically the voltage channel when used in energy
metering applications), i.e. when PHASE register code
is positive, Channel 0 is lagging channel 1.
When PHASE register code is negative, Channel 0 is
leading versus Channel 1.
The delay is give by the following formula:
EQUATION 7-1:
Register CodeDelay = Phase
------------------------------------------------DMCLK
REGISTER 7-3:
PHASE RESOLUTION FROM OSR
The timing resolution of the phase delay is 1/DMCLK or
1 µs in the default configuration (MCLK=4 MHz). The
PHASE register coding depends on the OSR setting:
• OSR=256: the delay can go from -128 to +127.
PHASE<7> is the sign bit. Phase<6> is the MSB
and PHASE<0> the LSB.
• OSR=128: the delay can go from -64 to +63.
PHASE<6> is the sign bit. Phase<5> is the MSB
and PHASE<0> the LSB.
• OSR=64: the delay can go from -32 to +31.
PHASE<5> is the sign bit. Phase<4> is the MSB
and PHASE<0> the LSB.
• OSR=32: the delay can go from -16 to +15.
PHASE<4> is the sign bit. Phase<3> is the MSB
and PHASE<0> the LSB.
PHASE REGISTER (PHASE): ADDRESS 0X07
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PHASE<7>
PHASE<6>
PHASE<5>
PHASE<4>
PHASE<3>
PHASE<2>
PHASE<1>
PHASE<0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7:0
x = Bit is unknown
CH0 relative to CH1 phase delay
Delay = PHASE Register two’s complement code / DMCLK (Default PHASE=0)
DS22192A-page 44
© 2009 Microchip Technology Inc.
MCP3901
7.4
Gain Configuration Register
This registers contains the settings for the PGA gains
for each channel as well as the BOOST options for
each channel.
REGISTER 7-4:
GAIN CONFIGURATION REGISTER (GAIN) - > ADDRESS 0X08
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
PGA_CH1
<2>
PGA_CH1
<1>
PGA_CH1
<0>
BOOST_
CH1
BOOST_
CH0
PGA_CH0
<2>
PGA_CH0
<1>
PGA_CH0
<0>
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
bit 7:5
PGA_CH1<2:0>: PGA Setting for Channel 1
111 = Reserved (Gain = 1)
110 = Reserved (Gain = 1)
101 = Gain is 32
100 = Gain is 16
011 = Gain is 8
010 = Gain is 4
001 = Gain is 2
000 = Gain is 1
bit 4:3
BOOST<1:0> Current Scaling for high speed operation
11 = Both channels have current x 2
10 = Channel 1 has current x 2
01 = Channel 0 has current x 2
00 = Neither channel have current x 2
bit 2:0
PGA_CH0<2:0>: PGA Setting for Channel 0
111 = Reserved (Gain = 1)
110 = Reserved (Gain = 1)
101 = Gain is 32
100 = Gain is 16
011 = Gain is 8
010 = Gain is 4
001 = Gain is 2
000 = Gain is 1
© 2009 Microchip Technology Inc.
x = Bit is unknown
DS22192A-page 45
MCP3901
7.5
Status and Communication
Register
This register contains all settings related to the
communication including data ready settings and
status, and read mode settings.
7.5.1
DATA READY (DR) LATENCY
CONTROL - DR_LTY
This bit determines if the first data ready pulses
correspond to settled data or unsettled data from each
SINC3 filter. Unsettled data will provide DR pulses
every DRCLK period. If this bit is set, unsettled data will
wait for 3 DRCLK periods before giving DR pulses and
will then give DR pulses every DRCLK period.
7.5.2
DATA READY (DR) PIN HIGH Z DR_HIZN
This bit defines the non-active state of the data ready
pin (logic 1 or high impedance). Using this bit, the user
can connect multiple chips with the same DR pin with a
pull up resistor (DR_HIZN=0) or a single chip with no
external component (DR_HIZN=1).
7.5.3
DATA READY MODE DRMODE<1:0>
See Section 6.9 “Data Ready Pin (DR)” for more
details about data ready pin behavior.
7.5.4
DR STATUS FLAG DRSTATUS<1:0>
These bits indicate the DR status of both channels
respectively. These flags are set to logic high after each
read of the STATUS/COM register. These bits are
cleared when a DR event has happened on its
respective ADC channel. Writing these bits has no
effect.
Note:
These bits are useful if multiple devices
share the same DR output pin
(DR_HIZN=0) in order to understand from
which device the DR event has happened.
This configuration can be used for
three-phase power metering systems
where all three phases share the same
data ready pin. In case the DRMODE=00
(Linked ADCs), these data ready status
bits will be updated synchronously upon
the same event (lagging ADC is ready).
These bits are also useful in systems
where the DR pin is not used to save MCU
I/O.
If one of the channels is in reset or shutdown, only one
of the data ready pulses is present and the situation is
similar to DRMODE = 01 or 10. In the 01,10 and 11
modes, the ADC channel data to be read is latched at
the beginning of a reading, in order to prevent the case
of erroneous data when a DR pulse happens during a
read. In these modes the two channels are independent.
When these bits are equal to 11,10 or 01, they control
which ADC’s data ready is present on the DR pin.
When DRMODE=00, the data ready pin output is synchronized with the lagging ADC channel (defined by
the PHASE register), and the ADCs are linked together.
In this mode, the output of the two ADCs are latched
synchronously at the moment of the DR event. This
prevents from having bad synchronization between the
two ADCs. The output is also latched at the beginning
of a reading in order not to be updated during a read
and not to give erroneous data.
This mode is very useful for power metering
applications because the data from both ADCs can be
retrieved using this single data ready event and
processed synchronously even in case of a large
phase difference. This mode works as if there was one
ADC channel and its data would be 48 bits long and
contain both channel data. As a consequence, if one
channel is in reset or shutdown when DRMODE=00, no
data ready pulse will be present at the outputs (if both
channels are not ready in this mode, the data is not
considered as ready).
DS22192A-page 46
© 2009 Microchip Technology Inc.
MCP3901
REGISTER 7-5:
STATUS AND COMMUNICATION REGISTER -> ADDRESS 0X09
R/W-1
R/W-0
R/W-1
R/W-0
READ<1>
READ<0>
DR_LTY
DR_HIZN
R/W-0
R/W-0
R-1
R-1
DRMODE<1> DRMODE<0> DRSTATUS_ DRSTATUS_
CH1
CH0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7:6
READ: Address Loop Setting
11 = Address counter loops on entire register map
10 = Address counter loops on register TYPES (DEFAULT)
01 = Address counter loops on register GROUPS
00 = Address not incremented, continually read same single register
bit 5
DR_LTY: Data Ready Latency Control
1 = “No Latency” Conversion, DR pulses after 3 DRCLK periods. (Default)
0 = Unsettled Data is available after every DRCLK period
bit 4
DR_HIZn: Data Ready Pin Inactive State Control
1 = The data ready pin default state is a logic high when data is NOT ready
0 = The data ready pin default state is high impedance when data is NOT ready (Default)
bit 3:2
DRMODE<1:0>: Data Ready Pin (DR) control
11 = Both Data Ready pulses from ADC0 and ADC Channel 1 are output on the DR pin.
10 = Data Ready pulses from ADC Channel 1 are output on the DR pin. DR from ADC Channel 0 are
not present on the pin.
01 = Data Ready pulses from ADC Channel 0 are output on the DR pin. DR from ADC Channel 1 are
not present on the pin.
00 = Data Ready pulses from the lagging ADC between the two are output on the DR pin. The lagging
ADC selection depends on the phase register and on the OSR (default).
bit 1:0
DRSTATUS<1:0>: Data Ready Status
11 = ADC Channel 1 and Channel 0 data not ready (Default)
10 = ADC Channel 1 data not ready, ADC Channel 0 data ready
01 = ADC Channel 0 data not ready, ADC Channel 1 data ready
00 = ADC Channel 1 and Channel 0 data ready
© 2009 Microchip Technology Inc.
DS22192A-page 47
MCP3901
7.6
Configuration Registers
The configuration registers contain settings for the
internal clock prescaler, the oversampling ratio, the
channel 0 and channel 1 width settings of 16 or 24 bits,
REGISTER 7-6:
the modulator output control settings, the state of the
channel resets and shutdowns, the dithering algorithm
control (for idle tones suppression), and the control bits
for the external VREF and external CLK.
CONFIGURATION REGISTERS:
CONFIG1: ADDRESS 0X0A, CONFIG2: ADDRESS 0X0B
R/W-0
R/W-0
R/W-0
R/W-1
R/W-0
R/W-0
R/W-0
R/W-0
PRESCALE
<1>
PRESCALE
<0>
OSR<1>
OSR<0>
WIDTH
_CH1
WIDTH
_CH0
MODOUT
_CH1
MODOUT
_CH0
bit 15
bit 8
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
R/W-1
R/W-0
R/W-0
RESET
_CH1
RESET
_CH0
SHUTDOWN
_CH1
SHUTDOWN
_CH0
DITHER
_CH1
DITHER
_CH0
VREFEXT
CLKEXT
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 15:14
PRESCALE<1:0> Internal Master Clock (AMCLK) Prescaler Value
11 = AMCLK = MCLK/ 8
10 = AMCLK = MCLK/ 4
01 = AMCLK = MCLK / 2
00 = AMCLK = MCLK (default)
bit 13-12
OSR<1:0> Oversampling Ratio for Delta-Sigma A/D Conversion (all channels, DMCLK/DRCLK)
11 = 256
10 = 128
01 = 64 (default)
00 = 32
bit 11:10
WIDTH<1:0> ADC Channel output data word width
1 = 24 bit mode
0 = 16 bit mode(default)
bit 9:8
MODOUT<1:0>: Modulator Output Setting for MDAT pins
11 = Both CH0 and CH1 Modulator Outputs present on MDAT1 and MDAT0 pins
10 = CH1 ADC Modulator Output present on MDAT1 pin
01 = CH0 ADC Modulator Output present on MDAT0 pin
00 = No modulator output is enabled (default)
bit 7:6
RESET<1:0>: RESET MODE SETTING FOR ADCs
11 = Both CH0 and CH1 ADC are in reset mode
10 = CH1 ADC in reset mode
01 = CH0 ADC in reset mode
00 = Neither Channel in reset mode(default)
bit 5:4
SHUTDOWN<1:0>: SHUTDOWN MODE SETTING FOR ADCs
11 = Both CH0 and CH1 ADC in Shutdown
10 = CH1ADC in Shutdown
01 = CH0 ADC in Shutdown
00 = Neither Channel in Shutdown(default)
bit 3:2
DITHER<1:0>: Control for dithering circuit
11 = Both CH0 and CH1 ADC have dithering circuit applied (default)
10 = Only CH1 ADC has dithering circuit applied
01 = Only CH0 ADC has dithering circuit applied
00 = Neither Channel has dithering circuit applied
DS22192A-page 48
© 2009 Microchip Technology Inc.
MCP3901
REGISTER 7-6:
CONFIGURATION REGISTERS:
CONFIG1: ADDRESS 0X0A, CONFIG2: ADDRESS 0X0B (CONTINUED)
bit 1
VREFEXT Internal Voltage Reference Shutdown Control
1 = Internal Voltage Reference Disabled, an external voltage reference must be placed between
REFIN+/OUT and REFIN-.
0 = Internal Voltage Reference Enabled (default)
bit 0
CLKEXT Clock Mode
1 = External clock mode (Internal Oscillator Disabled and bypassed - Lower Power)
0 = XT Mode - A crystal must be placed between OSC1/OSC2 (default)
© 2009 Microchip Technology Inc.
DS22192A-page 49
MCP3901
NOTES:
DS22192A-page 50
© 2009 Microchip Technology Inc.
MCP3901
8.0
PACKAGING INFORMATION
8.1
Package Marking Information
20-Lead QFN (4x4)(ML)
XXXXX
XXXXXX
YWWNNN
20-Lead SSOP (SS)
XXXXXXXX
XXXXXXXX
YYWWNNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example:
39010
e3
I/ML^^
922256
Example:
MCP3901A0
e3
I/SS^^
922256
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
© 2009 Microchip Technology Inc.
DS22192A-page 51
MCP3901
%
!" #$
2 % & %! % *" ) ' % * $% %"%
%% 133)))& &3 *
D
D2
EXPOSED
PAD
e
E2
2
E
b
2
1
1
K
N
N
NOTE 1
TOP VIEW
L
BOTTOM VIEW
A
A1
A3
4%
& 5&%
6!&( $
55, ,
6
6
67
8
%
7 9 %
:
%" $$
.
0 %%
*
./0
+
7 ;"%
,
,#
,
"";"%
7 5%
,#
""5%
,2
/0
<
:
/0
<
:
0 %%;"%
(
:
.
+
0 %%5%
5
+
.
=
>
>
0 %%% ,#
""
%
!"#$%! & '(!%&! %( %")% % % " * ) !%"
+ & "% ,-.
/01 / & %#%!
))% !%% ,21 $ & '! !)% !%% '$ $ &% !
DS22192A-page 52
) 0</
© 2009 Microchip Technology Inc.
MCP3901
%
2 % & %! % *" ) ' % * $% %"%
%% 133)))& &3 *
© 2009 Microchip Technology Inc.
DS22192A-page 53
MCP3901
%
&'() & * ) && +,
!" #&&* $
2 % & %! % *" ) ' % * $% %"%
%% 133)))& &3 *
D
N
E
E1
NOTE 1
1 2
e
b
c
A2
A
φ
A1
L1
4%
& 5&%
6!&( $
L
55, ,
6
6
67
8
%
7 9 %
>
>
<.
.
:.
%" $$
.
>
>
7 ;"%
,
:
:
""*;"%
,
.
.+
.<
7 5%
<
.
..
.
.
""*
*
2
%5%
5
2
% %
5
5"
2
*
%
5";"%
<./0
.,2
>
I
?
?
.
:?
(
>
+:
%
!"#$%! & '(!%&! %( %")% % % " & "," %!"& "$ % ! "$ % ! %#"&& "
+ & "% ,-.
/01 / & %#%!
))% !%% ,21 $ & '! !)% !%% '$ $ &% !
DS22192A-page 54
) 0/
© 2009 Microchip Technology Inc.
MCP3901
APPENDIX A:
REVISION HISTORY
Revision A (September 2009)
• Original Release of this Document.
© 2009 Microchip Technology Inc.
DS22192A-page 53
MCP3901
NOTES:
DS22192A-page 54
© 2009 Microchip Technology Inc.
MCP3901
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO.
XX
Device
Address
Options
Device:
X
X
Tape and Temperature
Reel
Range
MCP3901:
Address Options:
XX
/XX
Package
a)
MCP3901A0-I/ML:
b)
MCP3901A0T-I/ML:
c)
MCP3901A1-I/SS:
d)
MCP3901A1T-I/SS:
Two Channel ΔΣ A/D Converter
A6
A5
A0*
=
0
0
A1
=
0
1
A2
=
1
0
A3
=
1
1
* Default option. Contact Microchip factory for other
address options
Tape and Reel:
T
= Tape and Reel
Temperature Range:
I
= -40°C to +85°C
Package:
ML = Plastic Quad Flat No Lead (QFN), 20-lead
SS = Plastic Shrink Small Outline (SSOP), 20-lead
© 2009 Microchip Technology Inc.
Examples:
Two Channel ΔΣ A/D
Converter,
QFN-20 package,
Address Option = A0
Tape and Reel,
Two Channel ΔΣ A/D
Converter,
QFN-20 package,
Address Option = A0
Two Channel ΔΣ A/D
Converter,
SSOP-20 package,
Address Option = A1.
Tape and Reel,
Two Channel ΔΣ A/D
Converter,
SSOP-20 package,
Address Option = A1.
DS22192A-page 55
MCP3901
NOTES:
DS22192A-page 56
© 2009 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART,
rfPIC and UNI/O are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,
MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial
Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total
Endurance, TSHARC, UniWinDriver, WiperLock and ZENA
are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip Technology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2009, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
© 2009 Microchip Technology Inc.
Draft
DS22192A-page 57
WORLDWIDE SALES AND SERVICE
AMERICAS
ASIA/PACIFIC
ASIA/PACIFIC
EUROPE
Corporate Office
2355 West Chandler Blvd.
Chandler, AZ 85224-6199
Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
http://support.microchip.com
Web Address:
www.microchip.com
Asia Pacific Office
Suites 3707-14, 37th Floor
Tower 6, The Gateway
Harbour City, Kowloon
Hong Kong
Tel: 852-2401-1200
Fax: 852-2401-3431
India - Bangalore
Tel: 91-80-3090-4444
Fax: 91-80-3090-4080
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
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Tel: 630-285-0071
Fax: 630-285-0075
Cleveland
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Tel: 972-818-7423
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Tel: 248-538-2250
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Tel: 949-462-9523
Fax: 949-462-9608
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Santa Clara, CA
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Fax: 408-961-6445
Toronto
Mississauga, Ontario,
Canada
Tel: 905-673-0699
Fax: 905-673-6509
Australia - Sydney
Tel: 61-2-9868-6733
Fax: 61-2-9868-6755
China - Beijing
Tel: 86-10-8528-2100
Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
03/26/09
DS22192A-page 58
© 2009 Microchip Technology Inc.
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