BELLING BL6305SO Optimized pwm output stage eliminates lc output filter Datasheet

BL6305
2.6 Watt Mono Filter-Free Class-D Audio Power Amplifier
Features
Efficiency With an 8-Ω Speaker:
88% at 400 mW
80% at 100 mW
2.1mA Quiescent Current
0.4µA Shutdown Current
Optimized PWM Output Stage Eliminates LC Output Filter
Internally Generated 250-kHz Switching Frequency Eliminates Capacitor and Resistor
Improved PSRR (−75 dB) and Wide Supply Voltage (2.5 V to 5.5 V) Eliminates Need for a
Voltage Regulator
Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor
Improved CMRR Eliminates Two Input Coupling Capacitors
MSOP8, SOP8, DFN8 package
General Description
The BL6305 is a 2.6W high efficiency filter-free class-D audio power amplifier that requires
only three external components.
Features like 88% efficiency, −75dB PSRR, and improved RF-rectification immunity make
the BL6305 ideal for cellular handsets. In cellular handsets, the earpiece, speaker phone, and
melody ringer can each be driven by the BL6305.
Applications
Mobile phone、PDA
MP3/4、PMP
Portable electronic devices
Order Information
Part Number
Package
Shipping
BL6305MM
MSOP8
3000 pcs / Tape & Reel
BL6305DN
DFN8
3000 pcs / Tape & Reel
BL6305SO
SOP8
2500 pcs / Tape & Reel
Pin Diagrams
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- Page 1 of 9 -
Ver1.2
BL6305
Pin Description
Pin #
Name
1
SDB
2
Description
Shutdown terminal (low active)
NC (No internal connection)
3
IN+
Positive differential input
4
IN-
Negative differential input
5
VO+
Positive BTL output
6
VDD
Power Supply
7
PGND
Power Ground
8
VO-
Negative BTL output
Function Block Diagram
Av1 = 170k/Ri
(6)
VDD
170k
(4)
IN-
(8)
Vo-
PWM Modulator and
Power Driver
Amp1
(3)
IN+
(5)
Vo+
Av2 = 2 V/V
(7)
GND
170k
(1)
SDB
ShutDown
Control
300k
Bias &
Reference
Start up &
Protection
OSC &
RAMP
OC
Detect
Note
s: Total Voltage Gain = Av1 × Av 2 = 2 ×
170k
RI
Figure 1. Function Block Diagram
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Ver1.2
BL6305
Application Circuit
VDD
Ri
Vi-
+
Differential
Input
Vi+
+
)
p
o
Lo
TL
B
&d
e
Ms
Wo
Pl
C
(
To Battery
Cs
Vo+
Vo-
Ri
GND
Bias &
ShutDown
SDB
OSC &
RAMP
Figure 2. BL6305 Application Schematic With Differential Input
VDD
Ci
Ri
Vi-
+
Differential
Input
Vi+
Ci
+
)
p
Lo
o
T
BL
&d
Me
s
W
Po
l
C
(
To Battery
Cs
Vo+
Vo-
Ri
GND
Bias &
ShutDown
SDB
OSC &
RAMP
Figure 3. BL6305 Application Schematic With Differential Input and Input Capacitors
VDD
Ci
Sin le-ended
Input
Ri
Vi-
+
Vi+
+
)
p
Lo
o
T
BL
&d
Me
s
W
Po
l
C
(
To Battery
Cs
Vo+
Vo-
Ri
Ci
GND
SDB
Bias &
ShutDown
OSC &
RAMP
Figure 4. BL6305 Application Schematic With Single-Ended Input
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- Page 3 of 9 -
Ver1.2
BL6305
Electrical Characteristics
The following specifications apply for the circuit shown in Figure 5.
TA = 25 , unless otherwise specified.
Symbol
ISD
IQ
Parameter
Shutdown Current
Quiescent Current
Conditions
Spec
Min.
Typ.
Max.
VIN=0V, VSDB=0V, No Load
0.4
2
VDD = 2.5V, VIN = 0V, No Load
1.8
3.2
VDD = 3.6V, VIN = 0V, No Load
2.1
VDD = 5.5V, VIN = 0V, No Load
2.5
4.5
2
25
VIN = 0V, AV = 2V/V,
VOS
Output Offset Voltage
PSRR
Power Supply Rejection Ratio
VDD = 2.5V to 5.5V
VDD = 2.5V to 5.5V
Units
uA
mA
mV
-75
dB
-68
dB
VDD = 2.5V to 5.5V,
CMRR Common Mode Rejection Ratio
VIC = VDD/2 to 0.5V,
VIC = VDD/2 to VDD - 0.8V
FSW
Modulation frequency
VDD = 2.5V to 5.5V
200
250
300
kHz
AV
Voltage gain
VDD = 2.5V to 5.5V
320k
RI
340k
RI
360k
RI
V/V
RSDB
ZI
Resistance from SDB to GND
300
Input impedance
TWU
rDS(on)
160
Wake-up time from shutdown
170
VDD = 3.6V
1
VDD = 2.5V
700
Drain-Source resistance (on-state) VDD = 3.6V
500
VDD = 5.5V
400
kΩ
180
kΩ
mS
mΩ
Operating Characteristics
VDD = 5V, RI = 150kΩ, TA = 25
Symbol
PO
THD+N
SNR
Parameter
Output Power
Total Harmonic
Distortion + Noise
, unless otherwise specified.
Conditions
Spec
Min.
Typ.
Max.
Units
THD+N=10%, f=1KHz, RL = 4Ω
2.65
THD+N=1%, f=1KHz, RL = 4Ω
2.15
THD+N=10%, f=1KHz, RL = 8Ω
1.65
THD+N=1%, f=1KHz, RL = 8Ω
1.33
Po=1.0Wrms, f=1kHz, RL = 8Ω
0.21
%
95
dB
Signal-to-Noise ratio VDD=5V, Po=1.0Wrms, RL = 8Ω
W
VDD = 3.6V, RI = 150kΩ, TA = 25 , unless otherwise specified.
Symbol
PO
Parameter
Output Power
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Conditions
Spec
Min.
Typ.
THD+N=10%, f=1KHz, RL = 4Ω
1.35
THD+N=1%, f=1KHz, RL = 4Ω
1.08
THD+N=10%, f=1KHz, RL = 8Ω
0.85
THD+N=1%, f=1KHz, RL = 8Ω
0.69
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Max.
Units
W
Ver1.2
BL6305
THD+N
KSVR
Vn
CMRR
Total Harmonic
Po=0.5Wrms, f=1kHz, RL = 8Ω
Distortion + Noise
Supply ripple
VDD = 3.6V, input ac-grounded with CI = 2uF
rejection ratio
f=217Hz, V(Ripple)=200mVPP
Output voltage noise
Common Mode
%
-67
dB
VDD = 3.6V, input ac-grounded No weighting
87
with CI = 2uF, f=20~20kHz
65
A weighting
VDD = 3.6V, VIC = 1 VPP, f=217Hz
Rejection Ratio
0.21
uVRMS
-70
dB
VDD = 2.5V, RI = 150kΩ, TA = 25 , unless otherwise specified.
Symbol
PO
THD+N
Parameter
Spec
Conditions
Output Power
Total Harmonic
Distortion + Noise
Min.
Typ.
THD+N=10%, f=1KHz, RL = 4Ω
0.63
THD+N=1%, f=1KHz, RL = 4Ω
0.51
THD+N=10%, f=1KHz, RL = 8Ω
0.40
THD+N=1%, f=1KHz, RL = 8Ω
0.33
Po=0.2Wrms, f=1kHz, RL = 8Ω
0.21
Max.
Units
W
%
Test Circuit
Ci
Ri
IN+
Si nal input
from
measurement
2uF
VO+
150K
Vin
RL
BL6305
Ci
Ri
IN2uF
30
P
Output
to
measurement
VO
VO-
150K
Shutdown
si nal
SDB
VDD
GND
C1
2uF
Power +
Supply
-
Figure 5. BL6305 test set up circuit
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- Page 5 of 9 -
Ver1.2
BL6305
100
VO+
47nF
VO
100
VO-
47nF
30kHz LPF
Figure 6.
30-kHz LPF for BL6305 test
Notes: 1>. CS should be placed as close as possible to VDD/GND pad of the device
2>. Ci should be shorted for any Common-Mode input voltage measurement
3>. A 33uH inductor should be used in series with RL for efficiency measurement
4>. The 30 kHz LPF (shown in figure 5) is required even if the analyzer has an internal
LPF
Component Recommended
Due to the weak noise immunity of the single-ended input application, the differential input
application should be used whenever possible. The typical component values are listed in the table:
RI
CI
CS
150 k
3.3 nF
2 uF
(1) CI should have a tolerance of ±10% or better to reduce impedance mismatch.
(2) Use 1% tolerance resistors or better to keep the performance optimized, and place the
RI close to the device to limit noise injection on the high-impedance nodes.
Input Resistors (RI) & Capacitors (CI)
The input resistors (RI) set the total voltage gain of the amplifier according to Eq1
Gain =
2 × 170kΩ
RI
V 
 
V 
Eq1
The input resistor matching directly affects the CMRR, PSRR, and the second harmonic
distortion cancellation.
If a differential signal source is used, and the signal is biased from 0.5V ~ VDD-0.8V (shown
in Figure2), the input capacitor (CI) is not required.
If the input signal is not biased within the recommended common-mode input range in
differential input application (shown in Figure3), or in a single-ended input application (shown in
Figure4), the input coupling capacitors are required.
If the input coupling capacitors are used, the RI and CI form a high-pass filter (HPF). The
corner frequency (fC) of the HPF can be calculated by Eq2
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- Page 6 of 9 -
Ver1.2
BL6305
fC =
1
2π ⋅ R I ⋅ C I
(Hz )
Eq 2
Decoupling Capacitor (CS)
A good low equivalent-series-resistance (ESR) ceramic capacitor (CS), used as power supply
decoupling capacitor (CS), is required for high power supply rejection (PSRR), high efficiency and
low total harmonic distortion (THD). Typically CS is 2µF, placed as close as possible to the device
VDD pin.
Package Dimensions
DFN8
SYMBOL
MILLIMETER
MIN NOM
A
0.70
0.75
0.80
A1
-
0.02
0.05
b
0.25
0.30
0.35
c
0.18
0.20
0.25
D
2.90
3.00
3.10
D2
2.50REF
e
0.65BSC
Nd
1.95BSC
E
2.90
E2
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- Page 7 of 9 -
MAX
3.00
3.10
1.55REF
L
0.30
0.40
0.50
h
0.20
0.25
0.30
Ver1.2
BL6305
MSOP8
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- Page 8 of 9 -
Ver1.2
BL6305
SOP8
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- Page 9 of 9 -
Ver1.2
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