TI1 DLPR410 Configuration prom Datasheet

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DLPR410
DLPS027D – AUGUST 2012 – REVISED JANUARY 2016
DLPR410 Configuration PROM
1 Features
•
1
•
•
•
•
3 Description
®
Pre-Programmed Xilinx PROM Configures the
DLPC410ZYR
Data Transfer up to 32 Mbps
I/O Pins Compatible With 1.8 V to 3.3 V
1.8-V Core Supply Voltage
–40°C to 85°C Operating Temperature Range
2 Applications
•
•
•
Lithography
– Direct Imaging
– Flat Panel Display
– Printed Circuit Board Manufacturing
Industrial
– 3D Printing
– 3D Scanners for Machine Vision
– Quality Control
Displays
– 3D Imaging
– Intelligent and Adaptive Lighting
– Augmented Reality and Information Overlay
The DLPR410 device is a programmed PROM used
for properly configuring the DLPC410, which supports
reliable
operation
of
the
DLP7000FLP,
DLP7000UVFLP,
DLP9500FLN,
and
DLP9500UVFLN DMDs. The DLPR410 configuration
enables the DLPC410 to operate at a pixel data rate
up to 48 Gigabits per second (Gbps) with the option
for random row addressing.
The DLPR410 device is part of a multiple component
chipset in the DLP® Advanced Light Control portfolio.
A dedicated chipset provides developers easier
access to the DMD as well as high speed,
independent micromirror control.
The DLPC410 configuration program is only available
within the DLPR410. The DLPR410 requires that it be
used in conjunction with the DLPC410, the
DLP7000FLP, DLP7000UVFLP, DLP9500FLN, and
DLP9500UVFLN
DMDs,
and
the
DLPA200
components for reliable function and operation of the
chipset.
For complete electrical and mechanical specifications
of the DLPR410, see the XCF16P product
specification at www.xilinx.com.
Device Information(1)
PART NUMBER
DLPR410
PACKAGE
DSBGA (48)
BODY SIZE (NOM)
8.00 mm × 9.00 mm ×
1.20 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DLPR410
DLPS027D – AUGUST 2012 – REVISED JANUARY 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
4
6
6.1
6.2
6.3
6.4
6.5
6.6
6
6
6
6
6
Absolute Maximum Ratings .....................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
Supply Voltage Requirements for Power-On Reset
and Power-Down ......................................................
6.7 Timing Requirements ................................................
7
7
7
Detailed Description .............................................. 8
7.1 Overview ................................................................... 8
7.2 Functional Block Diagram ......................................... 8
7.3 Feature Description................................................... 9
7.4 Device Functional Modes.......................................... 9
8
Application and Implementation ........................ 11
8.1 Application Information............................................ 11
8.2 Typical Application ................................................. 11
9 Power Supply Recommendations...................... 12
10 Layout................................................................... 12
10.1 Layout Guidelines ................................................. 12
11 Device and Documentation Support ................. 13
11.1
11.2
11.3
11.4
11.5
11.6
Device Support......................................................
Documentation Support ........................................
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
13
14
14
14
14
14
12 Mechanical, Packaging, and Orderable
Information ........................................................... 14
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (April 2013) to Revision D
Page
•
Updated Features, Applications, and Description ................................................................................................................. 1
•
Deleted DLPR4101 (enhanced functionality PROM part number) throughout document ..................................................... 1
•
Added ESD Rating table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1
•
Moved Block Diagram to new Typical Application section ..................................................................................................... 1
•
Deleted 1.8 V and 3.3 V operation values from VCCO, VIL, and VIH - this implementation is 2.5 V ....................................... 6
•
Changed Device Marking Image ......................................................................................................................................... 13
•
Deleted DLP® Discovery™ 4100 Chipset Datasheet from Related Documentation .......................................................... 14
•
Added Link to XCF16P data sheet at xilinx.com ................................................................................................................. 14
Changes from Revision B (March 2013) to Revision C
Page
•
Added Top View of Device ..................................................................................................................................................... 1
•
Added DLPR4101 "Load 4" enhanced functionality to Features............................................................................................ 1
•
Added DLPR410 and DLPR4101 (enhanced functionality PROM part number) to DLPR410 throughout document .......... 1
•
Added a link to the data sheet................................................................................................................................................ 1
•
Added the Version column to the Ordering Information table ................................................................................................ 4
•
Updated DLPC and DLP7000 / DLP7000UV Embedded Example Block Diagram ............................................................. 11
•
Updated DLPC and DLP9500 / DLP9500UV Embedded Example Block Diagram ............................................................. 12
•
Added DLPR4101YVA as equivalent to TI part number 2510442-0006 ............................................................................. 13
•
Added Reference to DLPC410 data sheet ........................................................................................................................... 13
•
Added DLPR410 to Figure 4 ............................................................................................................................................... 13
•
Added Top View of Device to device marking ..................................................................................................................... 13
•
Added DLP7000UV Related Documentation........................................................................................................................ 14
•
Added DLP9500UV Related Documentation........................................................................................................................ 14
2
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Changes from Revision A (September 2012) to Revision B
•
Page
Changed the top-side marking in the Ordering Information table .......................................................................................... 4
Changes from Original (August 2012) to Revision A
•
Page
Changed the device From: Product Preview To: Production ................................................................................................. 1
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5 Pin Configuration and Functions
YVA Package
48-Pin DSBGA
Top View
1
2
3
4
5
6
A
B
C
D
E
F
G
H
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
GND
A1
G
Ground
GND
A2
G
Ground
OE/RESET
A3
I/O
Output Enable/RESET (Open-Drain I/O). When Low, this input holds the address
counter reset and the DATA and CLKOUT outputs are placed in a high-impedance state.
This is a bidirectional open-drain pin that is held Low while the PROM completes the
internal power-on reset sequence. Polarity is not programmable. Pin must be pulled
High using an external 4.7-kΩ pull-up to VCCO.
DNC1
A4
—
Do Not Connect. Leave unconnected.
D6
A5
—
Do Not Connect. Leave unconnected.
D7
A6
—
Do Not Connect. Leave unconnected.
VCCINT1
B1
P
Positive 1.8-V supply voltage for internal logic.
VCCO1
B2
P
Positive 2.5-V supply voltage connected to the output voltage drivers and internal
buffers.
CLK
B3
I
Do Not Connect. Leave unconnected.
(CE)
B4
I
Chip Enable Input. When (CE ) is High, the device is put into low-power standby mode,
the address counter is reset, and the DATA and CLKOUT outputs are placed in a high
impedance state.
D5
B5
—
Do Not Connect. Leave unconnected.
GND
B6
G
Ground
BUSY
C1
—
Do Not Connect. Leave unconnected.
(1)
4
P = Power
G = Ground
I = Input
O = Output
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Pin Functions (continued)
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
CLKOUT
C2
—
Configuration clock output. Each rising edge on the CLK input increments the internal
address counter. Pin must be pulled High and Low using an external 100-Ω pull-up
to VCCO and an external 100-Ω pull-down to Ground. Place resistors close to pin.
DNC2
C3
—
Do Not Connect. Leave unconnected.
DNC3
C4
—
Do Not Connect. Leave unconnected.
D4
C5
—
Do Not Connect. Leave unconnected.
VCCO2
C6
P
Positive 2.5-V supply voltage connected to the output voltage drivers and internal
buffers.
( CF)
D1
I
Configuration pin. The (CF) pin must be pulled High using an external 4.7-kΩ pull-up
to VCCO. Selects serial mode configuration.
(CEO)
D2
—
Do Not Connect. Leave unconnected.
DNC10
D3
—
Do Not Connect. Leave unconnected.
DNC11
D4
—
Do Not Connect. Leave unconnected.
D3
D5
—
Do Not Connect. Leave unconnected.
VCCO4
D6
P
Positive 2.5-V supply voltage connected to the output voltage drivers and internal
buffers.
VCCINT2
E1
P
Positive 1.8-V supply voltage for internal logic.
TMS
E2
I
JTAG Mode Select Input. TMS has an internal 50-kΩ resistive pull-up to VCCJ.
DNC4
E3
—
Do Not Connect. Leave unconnected.
DNC5
E4
—
Do Not Connect. Leave unconnected.
D2
E5
—
Do Not Connect. Leave unconnected.
TDO
E6
O
JTAG Serial Data Output. TDO has an internal 50-kΩ resistive pull-up to VCCJ.
GND
F1
G
Ground
DNC6
F2
—
Do Not Connect. Leave unconnected.
DNC7
F3
—
Do Not Connect. Leave unconnected.
DNC8
F4
—
Do Not Connect. Leave unconnected.
GND
F5
G
Ground
GND
F6
G
Ground
TDI
G1
I
JTAG Serial Data Input. TDI has an internal 50k-Ω resistive pull-up to VCCJ.
DNC9
G2
—
REV_SEL0
G3
I
REV_SEL1
G4
I
VCCO3
G5
P
Positive 2.5-V supply voltage connected to the output voltage drivers and internal
buffers.
VCCINT3
G6
P
Positive 1.8-V supply voltage for internal logic.
GND
H1
G
Ground
VCCJ
H2
P
Positive 2.5-V JTAG I/O supply voltage connected to the TDO output voltage driver and
TCK, TMS and TDI input buffers.
TCK
H3
I
JTAG Clock Input. This pin is the JTAG test clock. It sequences the TAP controller and
all the JTAG test and programming electronics.
(EN_EXT_SEL)
H4
I
External Selection Input. (EN_EXT_SEL) has an internal 50-kΩ resistive pull- up to
VCCO. The (EN_EXT_SEL) pin must be connected to Ground.
D1
H5
—
Do Not Connect. Leave unconnected.
D0
H6
O
DATA output pin to provide data for configuring the DLPC410 in serial mode.
Do Not Connect. Leave unconnected.
Revision Select [1:0] Inputs. When the (EN_EXT_SEL) is Low, the Revision Select pins
are used to select the design revision to be enabled. The Revision Select [1:0] inputs
have an internal 50-kΩ resistive pull-up to VCCO. The (REV_SEL0) pin must be pulled
Low using an external 10-kΩ pull-down to Ground. The (REV_SEL1) pin must be
connected to Ground.
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature (unless otherwise noted) (see
(1) (2)
)
MIN
MAX
UNIT
VCCINT Internal supply voltage
Relative to ground
–0.5
2.7
V
VCCO
Relative to ground
–0.5
4.0
V
VCCO < 2.5 V
–0.5
3.6
V
VCCO ≥ 2.5 V
–0.5
3.6
V
VCCO < 2.5 V
–0.5
3.6
V
VCCO ≥ 2.5 V
–0.5
3.6
V
125
°C
125
°C
I/O supply voltage
VIN
Input voltage with respect to ground
VTS
Voltage applied to high-impedance output
TJ
Junction temperature
Tstg
Storage temperature, ambient
(1)
(2)
–40
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
Maximum DC undershoot below GND must be limited to either 0.5 V or 10 mA. During transitions, the device pins can undershoot to –2
V or overshoot to 7 V, provided this overshoot or undershoot lasts less then 10 ns and with the forcing current being limited to 200 mA.
6.2 ESD Ratings
V(ESD)
(1)
(2)
(3)
(1)
Electrostatic discharge
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all
pins (2) (3)
VALUE
UNIT
2000
V
Electrostatic discharge (ESD) to measure device sensitivity and immunity to damage caused by assembly line electrostatic discharges in
to the device.
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC Standard JESD22-A114A (C1 = 100 pF, R1 = 1500 Ω, R2 = 500 Ω).
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
NOM
MAX
1.65
1.8
2.0
V
2.2
2.5
2.7
V
2.5-V operation
0
–
0.7
V
2.5-V operation
1.7
–
3.6
V
0
–
VCCO
V
–
–
500
ns
–40
–
85
°C
VCCINT
Internal voltage supply
VCCO
Supply voltage for output drivers
2.5-V operation
VIL
Low-level input voltage
VIH
High-level input voltage
VO
Output voltage
tIN
Input signal transition time (measured between 10% VCCO and 90% VCCO)
TA
Operating ambient temperature
UNIT
6.4 Thermal Information
Refer to the XCF16P product specifications at www.xilinx.com.
6.5 Electrical Characteristics
Refer to the XCF16P product specifications at www.xilinx.com.
6
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6.6 Supply Voltage Requirements for Power-On Reset and Power-Down
(1)
(see
)
(2)
tVCC
VCCINT rise time from 0 V to nominal voltage
VCCPOR
POR threshold for VCCINT supply
tOER
OE/RESET release delay following POR
VCCPD
Power-down threshold for VCCINT supply
tRST
Time required to trigger a device reset when the VCCINT supply drops below
the maximum VCCPD threshold
(1)
(2)
(3)
(3)
MIN
MAX
UNIT
0.2
50
0.5
–
V
0.5
30
ms
–
0.5
V
10
–
ms
ms
VCCINT, VCCO, and VCCJ supplies can be applied in any order.
At power up, the device requires the VCCINT power supply to monotonically rise to the nominal operating voltage within the specified
TVCC rise time. If the power supply cannot meet this requirement, then the device might not perform power-on-reset properly. See Figure
6, in the Xilinx XCF16P (v2.18) Product Specification for more information.
If the VCCINT and VCCO supplies do not reach their respective recommended operating conditions before the OE/RESET pin is released,
then the configuration data from the PROM is not available at the recommended threshold levels. The configuration sequence must be
delayed until both VCCINT and VCCO have reached their recommended operating conditions.
6.7 Timing Requirements
Refer to the XCF16P product specifications at www.xilinx.com.
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7 Detailed Description
7.1 Overview
The configuration bit stream stored in the DLPR410 supports reliable operation of the DLPC410 and the
DLP7000FLP, DLP7000UVFLP, DLP9500FLN, and DLP9500UVFLN DMDs. The DLPC410 digital controller
loads this configuration bit stream from the DLPR410.
7.2 Functional Block Diagram
VCCINT
VCCO
VCCJ
TCK
TDI
TMS
OE/RESET
CEO
CLK
DLPR410
CE
TDO
DO
CF
EN_EXT_SEL
REV_SEL0
REV_SEL1
GND
8
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7.3 Feature Description
7.3.1 Data Interface
7.3.1.1 Data Outputs
The DLPR410 is configured for serial mode operation, where D0 is the data output pin. D0 output pin provides a
serial connection to the DLPC410, where the configuration is read out by the DLPC410.
7.3.1.2 Configuration Clock Input
The configuration CLK is connected to the DLPC410 in master mode, where the DLPC410 provides the clock
pulses to read the configuration from the DLPR410.
7.3.1.3 Output Enable and Reset
When the OE/(RESET) input is held low, the address counter is reset and the Data and CLKOUT outputs are
placed in high-impedance state. OE/(RESET) must be pulled High using an external 4.7-kΩ pull-up to VCCO.
7.3.1.4 Chip Enable
The (CE) input is asserted by the DLPC410 to enable the Data and CLKOUT outputs. When (CE) is held high,
the DLPR410 address counter is reset, and the Data and CLKOUT outputs are placed in high-impedance states.
7.3.1.5 Configuration Pulse
The DLPR410 is configured in serial mode when the Configuration Pulse (CF) is held high and (CE) and OE are
enabled. New data is available a short time after each rising clock edge.
7.3.1.6 Revision Selection
REV_SEL_0, REV_SEL_1, and (EN_EXT_SEL) signals are used for selecting which revision to be the default.
Setting all three signals to GND will default to revision 0 for simple DLPR410 setup.
7.4 Device Functional Modes
To successfully program the DLPC410 upon power-up, the DLPR410 must be configured and connected to the
DLPC410 as shown in Figure 1.
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VCC_2P5V
VCC_1P8V
RSVD7
RSVD8
U11
V12
V11
W10
1K
1K
DLPC410
A6
A5
B5
C5
D5
E5
H5
H6
D7
D6
D5
D4
D3
D2
D1
D0
G3
G4
H4
D2
D1
REV_SEL0
REV_SEL1
EN_EXT_SEL
CEO
CF
DLPR410
DNC11
DNC10
DNC9
DNC8
DNC7
DNC6
DNC5
DNC4
DNC3
DNC2
DNC1
D4
D3
G2
F4
F3
F2
E4
E3
C4
C3
A4
TMS
TDO
TDI
TCK
E2
E6
G1
H3
0.047µF
16V
0.1µF
16V
0.047µF
16V
0.1µF
16V
0.1µF
16V
100
4.7K
4.7K
4.7K
4.7K
4.7K
TCK_JTAG
TMS_JTAG
TDO_XCF16DDC
TDO_DDC
G6
E1
B1
R18
T18
TCK_0
TMS_0
TDI_0
TDO_0
PROGB_DDC
VCCINT3
VCCINT2
VCCINT1
VREFP_0
VREFN_0
N18
J18
P18
W11
L18
D6
G5
C6
B2
H2
P14
N13
CS_B_0
PROGRAM _B_0
RWDR_B_0
D_OUT_BUSY_0
HSWAPEN_0
VCC04
VCC03
VCC02
VCC01
VCCJ
AVDD_0
AVSS_0
PROM_D0_DDC
PROM_CCK_DDC
DONE_DDC
INTB_DDC
CLK
CLKOUT
OE/RESET
CE
BUSY
GND1
GND2
GND3
GND4
GND5
GND6
GND7
M14
M13
K11
J10
K10
J11
B3
C2
A3
B4
C1
TMS_JTAG
TDO_XCF16DDC
TDI_DDC
TCK_JTAG
A1
A2
B6
F1
F5
F6
H1
DXP_0
DXN_0
D_IN_0
CCLK_0
DONE_0
INT_B_0
PROG
JTAG
MODE
NP
0
4.7K
R14
R13
DDC_M0
4.7K
VP_0
VN_0
W18
V18
Y17
JUMPER
N14
P13
M0_0
M2_0
M1_0
0-1 REV SEL = 00
1-2 REV SEL = 01
VCC_0_1
VCC_0_2
100
Y9
W12
4.7K
4.7K
Master Serial
Config Mode
Figure 1. DLPC410 and DLPR410 Connection Schematic
10
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The DLPR410 configuration PROM comes pre-programmed with configuration code for the DLPC410. Upon
power-up, the DLPC410 and the DLPR410 handshake with each other to enable configuration information to be
sent from the DLPR410 to the DLPC410, such that the DLPC410 can configure itself for proper operation within
the application. Without the DLPR410 properly connected to the DLPC410 in the application system, the
DLPC410 would not be able to boot itself and the system would remain inoperable.
8.2 Typical Application
A typical embedded system application using the DLPC410 controller programmed by the DLPR410 is shown in
Figure 2 and in Figure 3. For complete details of this typical application refer to the DLPC910 data sheet listed in
Related Documentation.
Figure 2. DLPC410 and DLP7000 / DLP7000UV Embedded Example Block Diagram
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Typical Application (continued)
OPTICAL
SENSOR
LED
DRIVERS
(CAMERA)
LEDS
OPTICS
LED
SENSORS
USER
INTERFACE
LVDS BUS (A,B,[C,D])
LVDS BUS (A,B,[C,D])
DDC_DCLK, DVALID, DDC_DIN(15:0)
DDC_DCLKOUT, DDCSCTRL, DDC_DOUT(15:0)
SCP BUS
ROW and BLOCK SIGNALS
SCPCLK, SCPDO, SCPDI, DMD_SCPENZ, A_SCPENZ, B_SCPENZ
ROWMD(1:0), ROWAD(10:0), BLKMD(1:0), BLKAD(3:0), RST2BLKZ
CONTROL SIGNALS
COMP_DATA, NS_FLIP, WDT_ENBLZ, PWR_FLOAT
CONNECTIVITY
USER - MAIN
PROCESSOR / FPGA
(USB, ETHERNET, ETC.)
DLPA200 CONTROL
A_MODE(1:0), A_SEL(1:0),
A_ADDR(3:0), OEZ, INIT
DLPC410 INFO SIGNALS
RST_ACTIVE, INIT_ACTIVE, ECP2_FINISHED,
DMD_TYPE(3:0), DDC_VERSION(2:0)
MBRST1_(15:0)
DLP9500
DLPA200
A
DLPC410
PGM SIGNALS
VOLATILE
and
NON-VOLATILE
STORAGE
DLPR410
PROM_CCK_DDC, PROGB_DDC,
PROM_DO_DDC, DONE_DDC, INTB_DDC
DLPA200 CONTROL
B_MODE(1:0), B_SEL(1:0),
B_ADDR(3:0), OEZ, INIT
JTAG
VLED0
B
VLED1
ARSTZ
CLKIN_R
DMD_RESET
OSC
50 Mhz
~
MBRST2_(15:0)
DLPA200
POWER MANAGMENT
Figure 3. DLPC410 and DLP9500 / DLP9500UV Embedded Example Block Diagram
8.2.1 Design Requirements
The DLPR410 is part of a multi-chipset solution, and it is required to be coupled with the DLPC410 for reliable
operation of the DLP7000FLP, DLP7000UVFLP, DLP9500FLN, and DLP9500UVFLN DMD. For more
information, refer to the DLPC410 datasheet listed in Related Documentation.
9 Power Supply Recommendations
The DLPR410 uses two power supply rails as shown in Table 1.
Table 1. DLPR410 Power Supply Rails
SUPPLY
POWER PINS
1.8 V
VCCINT1, VCCINT2, and VCCINT3
2.5 V
VCCO1,VCCO2,VCCO3, VCCO4, and VCCJ
COMMENTS
All VCCINT pins must be connected with a 0.1-µF
decoupling capacitor to GND.
All VCCO and VCCJ pins must be connected with a 0.1µF decoupling capacitor to GND.
10 Layout
10.1 Layout Guidelines
The DLPR410 is part of a multi-chipset solution, and it is required to be coupled with the DLPC410 for reliable
operation of the DLP7000FLP, DLP7000UVFLP, DLP9500FLN, and DLP9500UVFLN DMD. Refer to the
DLPC410 datasheet listed in Related Documentation for a layout example for this multi-chipset solution.
12
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DLPR410
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DLPS027D – AUGUST 2012 – REVISED JANUARY 2016
11 Device and Documentation Support
11.1 Device Support
11.1.1 Device Nomenclature
Table 2. Part Number Description
TI PART NUMBER
DLPR410YVA
DESCRIPTION
DLPR410 Configuration PROM
REFERENCE NUMBER
2510442-0005
11.1.2 Device Markings
25104420005 YY/WW
Pin 1
Figure 4. DLPR410 Device Markings
Where 0005 is the version number and YY/WW is the year/week the part was programmed.
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13
DLPR410
DLPS027D – AUGUST 2012 – REVISED JANUARY 2016
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11.2 Documentation Support
11.2.1 Related Documentation
For related documentation, see the following:
Table 3. Related Documentation
DOCUMENT
TI LITERATURE NUMBER
DLP7000 0.7 XGA Type-A DMD data sheet
DLPS026
DLP7000UV 0.7 XGA UV Type-A DMD data sheet
DLPS061
DLP9500 0.95 1080p Type-A DMD data sheet
DLPS025
DLP9500UV 0.95 1080p UV Type-A DMD data sheet
DLPS033
DLPA200 DMD Micromirror Driver data sheet
DLPS015
DLPC410 DMD Controller data sheet
DLPS024
XCF16P data sheet
available at www.xilinx.com
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
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E2E is a trademark of Texas Instruments.
DLP is a registered trademark of Texas Instruments.
Xilinx is a registered trademark of Xilinx, Inc.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this datasheet, refer to the left-hand navigation.
14
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
DLPR410YVA
ACTIVE
Package Type Package Pins Package
Drawing
Qty
DSBGA
YVA
48
3
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Pb-Free
(RoHS)
Call TI
Level-3-260C-168 HR
Op Temp (°C)
Device Marking
(4/5)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2014
Addendum-Page 2
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