TI1 LMV881LEE/NOPB Lmv881 23 mhz low power cmos emi hardened operational amplifier with 1.8v logic shutdown Datasheet

LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
LMV881 23 MHz Low Power CMOS EMI Hardened Operational Amplifier with 1.8V Logic
Shutdown
Check for Samples: LMV881
FEATURES
APPLICATIONS
•
•
•
•
1
2
•
•
•
•
•
•
•
•
•
•
•
•
•
Unless Otherwise Noted, Typical Values at TA
= 25°C, V+ = 3.3V
Supply Voltage 2.7V to 5.5V
Supply Current 1.65 mA
Shutdown Current 200 pA
Input Offset Voltage 1 mV Max
Input Bias Current 0.1 pA
GBW 23 MHz
EMIRR at 1.8 GHz 105 dB
Input Noise Voltage at 1 kHz 9 nV/√Hz
Slew Rate 12 V/µs
Output Voltage Swing Rail-to-Rail
Output Current Drive 70 mA
Operating Ambient Temperature Range −40°C
to 125°C
Space Saving Micro-UQFN Package 1.5 x 1.0 x
0.5 mm
Weight Scale Systems
Filters/Buffers
Medical Diagnosis Equipment
DESCRIPTION
The LMV881 is a low power CMOS input operational
amplifier that provides low input bias currents, a rail
to rail output with high output drive capability and a
wide temperature range of −40°C to +125°C.
Additionally, the LMV881 is EMI hardened to
minimize sensitivity to external interference.
The LMV881 has a maximum input offset voltage of 1
mV with an input common-mode voltage range that
includes ground. Over an operating supply range
from 2.7V to 5.5V, the LMV881 provides a typical
PSRR of 110dB and a CMRR of 110dB. This makes
the LMV881 ideal for EMI sensitive applications as
well as exceptional performance as a robust general
purpose part.
The unity gain stable LMV881 features 23 MHz of
bandwidth while consuming only 1.65 mA of current.
This device also maintains stability for capacitive
loads as large as 200 pF.
Typical Application
V
R1
+
NO RF RELATED
DISTURBANCES
PRESSURE
SENSOR
+
-
+
R2
ADC
+
EMI HARDENED
EMI HARDENED
INTERFERING
RF SOURCES
Figure 1. EMI Hardened Sensor Application
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2012–2013, Texas Instruments Incorporated
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
DESCRIPTION (CONTINUED)
LMV881 offers a shutdown pin that can be used to disable the device and reduce the supply current to subnanoamp levels. During shutdown, the output is hard-clamped to V- to provide a known output state. The
shutdown input thresholds are set for 1.8V logic, regardless of the amplifiers supply voltage. This eliminates the
need for additional logic level shifting circuitry or translators.
The LMV881 is offered in the space saving 6-Pin µUQFN package and provides excellent performance and
economy in terms of power and space usage.
Connection Diagram
IN+
1
6
V+
V+
6
1
IN+
V-
2
5
SD
SD
5
2
V-
IN -
3
4
OUT
OUT
4
3
IN -
Top View
Bottom View
6-Pad UQFN Package
See Package Number NKK0006A
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
2
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
Absolute Maximum Ratings (1)
(2)
Human Body Model
ESD Tolerance (3)
2 kV
Charge-Device Model
1 kV
Machine Model
VIN Differential
200V
± Supply Voltage
+
−
Supply Voltage (VS = V – V )
6V
Voltage at Input/Output Pins
V+ +0.4V
V− −0.4V
Storage Temperature Range
−65°C to +150°C
Junction Temperature (4)
+150°C
For soldering specifications http://www.ti.com/lit/SNOA549
(1)
(2)
(3)
(4)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see the
Electrical Characteristics Tables.
If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of
JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC).
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Operating Ratings (1)
Temperature Range (2)
−40°C to +125°C
+
−
Supply Voltage (VS = V – V )
Package Thermal Resistance (θJA
(1)
(2)
2.7V to 5.5V
(2)
)
6-Pad µUQFN
335°C/W
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For specifications and the test conditions, see the
Electrical Characteristics Tables.
The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient
temperature is PD = (TJ(MAX) - TA)/ θJA . All numbers apply for packages soldered directly onto a PC board.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
3
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
3.3V Electrical Characteristics (1)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min (2)
(4)
Typ (3)
Max (2)
Units
±273
±1000
±1260
μV
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Temperature Drift (5)
±0.7
±2.6
μV/°C
IB
Input Bias Current (5)
0.1
30
500
pA
IOS
Input Offset Current
CMRR
Common-Mode Rejection Ratio (4)
0.2V ≤ VCM ≤ V+ - 1.2V
77
76
93
PSRR
Power Supply Rejection Ratio (4)
2.7V ≤ V+ ≤ 5.5V,
VOUT = 1V
79
78
95
EMIRR
EMI Rejection Ratio, IN+ and IN−
1
(6)
VRF_PEAK = 100 mVP (−20 dBVP),
f = 400 MHz
70
VRF_PEAK = 100 mVP (−20 dBVP),
f = 900 MHz
80
VRF_PEAK = 100 mVP (−20 dBVP),
f = 1800 MHz
105
VRF_PEAK = 100 mVP (−20 dBVP),
f = 2400 MHz
110
CMVR
Input Common-Mode Voltage Range
CMRR ≥ 65 dB
AVOL
Large Signal Voltage Gain (7)
RL = 2 kΩ
VOUT = 0.15V to 1.65V,
VOUT = 3.15V to 1.65V
99
98
110
RL = 10 kΩ
VOUT = 0.1V to 1.65V,
VOUT = 3.2V to 1.65V
102
101
112
VOUT
Output Voltage Swing High
Output Voltage Swing Low
IOUT
Output Short Circuit Current
−0.2
–0.1
RL = 10 kΩ to V+/2
3
4
5
RL = 2 kΩ to V+/2
8
12
16
RL = 10 kΩ to V+/2
2
4
5
Sourcing, VOUT = VCM,
VIN = 100 mV
61
52
70
Sinking, VOUT = VCM,
VIN = −100 mV
72
58
86
VSDN = 0V
8.5
VSDN = 0V,
200Ω pullup from OUT to V+
134
(5)
(6)
(7)
4
V
dB
14
18
Shutdown Output Voltage
(4)
dB
12
Shutdown Output Resistance
(3)
dB
RL = 2 kΩ to V+/2
VOSD
(2)
dB
2.2
2.1
ROUT
(1)
pA
mV from
either rail
mA
Ohms
230
mV
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
The typical value is calculated by applying the absolute value transform to the distribution, then taking the statistical average of the
resulting distribution.
This parameter is ensured by design and/or characterization and is not tested in production.
The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
The specified limits represent the lower of the measured values for each output range condition.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
3.3V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 3.3V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
VEN
Turn-on Voltage
Test Conditions
Turn-off Voltage (8)
IS
Min (2)
(8)
Supply Current
(9)
0.3
Typ (3)
Max (2)
≥1
1.5
Units
V
≤ 0.7
Active,
VSD > 0.972 V
1.65
In Shutdown,
VSD < 0.676 V
200
AV = +1, VOUT = 1 VPP,
10% to 90%
12
2.17
2.75
mA
pA
SR
Slew Rate
GBW
Gain Bandwidth Product
23
MHz
Φm
Phase Margin
60
deg
en
Input Referred Voltage Noise Density
f = 1 kHz
f = 100 kHz
5.3
in
Input Referred Current Noise Density
CIN
Common-Mode Input Capacitance
5
Differential-Mode Input Capacitance
15
THD+N
(8)
(9)
Total Harmonic Distortion + Noise
f = 1 kHz
9
f = 1 kHz, AV = 1, BW ≥ 500 kHz
0.015
V/μs
nV/√Hz
pA/√Hz
0.02
pF
%
The shutdown logic levels are fixed to match 1.8V logic levels (referenced to V-), and do not change with the total power supply voltage.
Number specified is the slower of positive and negative slew rates.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
5
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
5V Electrical Characteristics (1)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
Test Conditions
Min (2)
(4)
Typ (3)
Max (2)
Units
±273
±1000
±1260
μV
VOS
Input Offset Voltage
TCVOS
Input Offset Voltage Temperature Drift (5)
±0.7
±2.6
μV/°C
IB
Input Bias Current (5)
0.1
30
500
pA
IOS
Input Offset Current
CMRR
Common-Mode Rejection Ratio (4)
0V ≤ VCM ≤ V+ –1.2V
79
78
94
PSRR
Power Supply Rejection Ratio (4)
2.7V ≤ V+ ≤ 5.5V,
VOUT = 1V
79
78
95
EMIRR
EMI Rejection Ratio, IN+ and IN−
1
(6)
VRF_PEAK = 100 mVP (−20 dBVP),
f = 400 MHz
70
VRF_PEAK = 100 mVP (−20 dBVP),
f = 900 MHz
80
VRF_PEAK = 100 mVP (−20 dBVP),
f = 1800 MHz
105
VRF_PEAK = 100 mVP (−20 dBVP),
f = 2400 MHz
110
CMVR
Input Common-Mode Voltage Range
CMRR ≥ 65 dB
−0.2
–0.1
AVOL
Large Signal Voltage Gain (7)
RL = 2 kΩ
VOUT = 0.15V to 2.5V,
VOUT = 4.85V to 2.5V
102
101
110
RL = 10 kΩ
VOUT = 0.1V to 2.5V,
VOUT = 4.9V to 2.5V
102
101
113
VOUT
Output Voltage Swing High
Output Voltage Swing Low
IOUT
Output Short Circuit Current
4
5
RL = 2 kΩ to V+/2
10
14
18
RL = 10 kΩ to V+/2
3
4
5
Sourcing, VOUT = VCM,
VIN = 100 mV
90
86
110
Sinking, VOUT = VCM,
VIN = −100 mV
90
86
110
VSDN = 0V,
200Ω pullup from OUT to V+
6
mV from
either rail
mA
7
169
V
dB
3
VSDN = 0V
(5)
(6)
(7)
3.9
3.8
RL = 10 kΩ to V+/2
Shutdown Output Voltage
(4)
dB
15
19
Shutdown Output Resistance
(3)
dB
13
VOSD
(2)
dB
RL = 2 kΩ to V+/2
ROUT
(1)
pA
Ohms
260
mV
Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very
limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under
conditions of internal self-heating where TJ > TA.
Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlations using
statistical quality control (SQC) method.
Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary
over time and will also depend on the application and configuration. The typical values are not tested and are not specified on shipped
production material.
The typical value is calculated by applying the absolute value transform to the distribution, then taking the statistical average of the
resulting distribution.
This parameter is ensured by design and/or characterization and is not tested in production.
The EMI Rejection Ratio is defined as EMIRR = 20log ( VRF_PEAK/ΔVOS).
The specified limits represent the lower of the measured values for each output range condition.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
5V Electrical Characteristics(1) (continued)
Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 5V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2.
Boldface limits apply at the temperature extremes.
Parameter
VEN
Turn-on Voltage
Test Conditions
Turn-off Voltage (8)
IS
Min (2)
(8)
Supply Current
(9)
0.3
Typ (3)
Max (2)
≥1
1.5
Units
V
≤ 0.7
VSD> 0.972 V
1.9
In Shutdown,
VSD< 0.676 V
200
AV = +1, VOUT = 2VPP,
10% to 90%
12
2.45
2.95
mA
pA
SR
Slew Rate
GBW
Gain Bandwidth Product
23
MHz
Φm
Phase Margin
61
deg
en
Input Referred Voltage Noise Density
f = 1 kHz
f = 100 kHz
5.5
in
Input Referred Current Noise Density
CIN
Common-Mode Input Capacitance
5
Differential-Input Capacitance
15
THD+N
(8)
(9)
Total Harmonic Distortion + Noise
f = 1 kHz
9
f = 1 kHz, AV= 1, BW ≥ 500 kHz
0.015
V/μs
nV/√Hz
pA/Hz
0.02
pF
%
The shutdown logic levels are fixed to match 1.8V logic levels (referenced to V-), and do not change with the total power supply voltage.
Number specified is the slower of positive and negative slew rates.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
7
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
Typical Performance Characteristics
At TA = 25°C, V = 5V, V− = 0V, VCM = V+/2, and RL =10 kΩ to V+/2, unless otherwise specified.
+
Input Bias Current
vs.
VCM at 25°C
Input Bias Current
vs.
VCM at 85°C
5
4
3
2
1
0
-1
-2
-3
-4
-5
TA = 85°C
5V
IBIAS (pA)
IB (pA)
TA = 25°C
3.3V
-1
0
1
2
3
4
5
50
40
30
20
10
0
-10
-20
-30
-40
-50
6
3.3V
VCM (V)
-1
2
3
VCM (V)
Figure 2.
Figure 3.
Input Bias Current
vs.
VCM at 125°C
Supply Current
vs.
Supply Voltage
1
4
+125°C
SUPPLY CURRENT (mA)
500
400
300
200
100
0
-100
-200
-300
-400
-500
0
5
6
2.2
TA = 125°C
IBIAS (pA)
5.0V
5.0V
+85°C
2.0
1.8
1.6
+25°C
1.4
-40°C
1.2
3.3V
1.0
-1
0
1
2
3
4
5
6
2.5
3.0
3.5
4.0
4.5
5.0
SUPPLY VOLTAGE (V)
VCM (V)
Figure 5.
Output Swing High
vs.
Supply Voltage RL = 2 kΩ
Output Swing High
vs.
Supply Voltage RL = 10 kΩ
5
RL = 2k
VOUT FROM RAIL HIGH (mV)
VOUT FROM RAIL HIGH (mV)
20
Figure 4.
125°C
15
85°C
10
25°C
5
0
2.5
-40°C
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
4
125°C
85°C
3
2
25°C
1
-40°C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
SUPPLY VOLTAGE (V)
Figure 6.
8
RL = 10k
0
2.5
6.0
5.5
Figure 7.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
Typical Performance Characteristics (continued)
−
+
At TA = 25°C, V = 5V, V = 0V, VCM = V+/2, and RL =10 kΩ to V+/2, unless otherwise specified.
Output Swing Low
vs.
Supply Voltage RL = 2 kΩ
5
RL = 2k
125°C
RL = 10k
125°C
VOUT FROM RAIL LOW (mV)
VOUT FROM RAIL LOW (mV)
85°C
15
10
25°C
-40°C
5
0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
4
85°C
3
25°C
2
-40°C
1
0
2.5
6.0
3.0
3.5
SUPPLY VOLTAGE (V)
SINK
VOUT FROM RAIL (V)
VOUT FROM RAIL (V)
6.0
Output Voltage Swing
vs.
Load Current at 5V
+
V = 3.3V
125°C
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
125°C
SOURCE
10
+
V = 5.0V
-40°C
125°C
SOURCE
20
30 40 50
ILOAD (mA)
60
70
80
0
10
20
30
40
50
60
70
80
ILOAD (mA)
Figure 10.
Figure 11.
Open Loop Gain
vs.
Capacitive Load at 3.3V
Open Loop Gain
vs.
Capacitive Load at 5V
60
60
135
90
GAIN
20
45
0
0
PHASE (°)
20 pF
OPEN LOOP GAIN (dB)
PHASE
PHASE
40
40
90
20 pF
GAIN
20
45
0
0
200 pF
200 pF
1M
10M
135
CL = 20, 50, 100 & 200 pF
RL=10 M:
CL = 20, 50, 100 & 200 pF
RL=10 M:
OPEN LOOP GAIN (dB)
5.5
Output Voltage Swing
vs.
Load Current at 3.3V
-40°C
-20
100k
5.0
Figure 9.
125°C
0
4.5
Figure 8.
SINK
1.0
0.8
0.6
0.4
0.2
0
-0.2
-0.4
-0.6
-0.8
-1.0
4.0
SUPPLY VOLTAGE (V)
PHASE (°)
20
Output Swing Low
vs.
Supply Voltage RL = 10 kΩ
-45
100M
-20
100k
1M
10M
-45
100M
FREQUENCY (Hz)
FREQUENCY (Hz)
Figure 12.
Figure 13.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
9
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
−
+
At TA = 25°C, V = 5V, V = 0V, VCM = V+/2, and RL =10 kΩ to V+/2, unless otherwise specified.
PSRR
vs.
Frequency
CMRR
vs.
Frequency
120
120
Vs = 3.3V and 5V
110
100
5V
-PSRR
5V
3.3V
3.3V
60
CMRR (dB)
PSRR (dB)
100
80
+PSRR
40
90
80
70
60
20
50
0
40
10
100
1k
10k 100k
FREQUENCY (Hz)
1M
10M
100
1k
10k
100k
1M
FREQUENCY (Hz)
Figure 14.
Figure 15.
Large Signal Step Response at VS = 3.3V
Large Signal Step Response at VS = 5V
0.8
0.8
RL=10K
RL=10K
CL=20pF
AV=+1
0.4
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
0.6
0.2
0.0
-0.2
-0.4
-0.6
0.0
0.6
CL=20pF
0.4
AV=+1
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-0.8
0.2
2.5
0.4
0.6
TIME ( s)
0.8
1.0
0.0
0.2
0.4
0.6
TIME ( s)
Figure 16.
Figure 17.
Turn-on Time
vs
Supply Voltage
Slew Rate
vs.
Supply Voltage
SLEW RATE (V/ s)
TURN ON TIME ( s)
1.0
RL=10K
19
CL=5pF
18
2.0
1.8
1.5
17
16
15
NEG
14
13
12
1.3
11
1.0
2.5
0.8
20
2.3
POS
10
3.0
3.5
4.0
4.5
5.0
2.5
SUPPLY VOLTAGE (V)
Figure 18.
10
10M
3.0
3.5
4.0
4.5
SUPPLY VOLTAGE (V)
5.0
Figure 19.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
Typical Performance Characteristics (continued)
−
+
At TA = 25°C, V = 5V, V = 0V, VCM = V+/2, and RL =10 kΩ to V+/2, unless otherwise specified.
Input Voltage Noise
vs.
Frequency
THD+N
vs.
Frequency
0.1
1k
RL = 10 k:
VOUT = 1VPP
BW = 500 kHz
VS = 3.3V & 5V
100
THD+N (%)
NOISE (nV/¥)
3.3V and 5V
AV = +10
0.01
10
AV = +1
1
100m
1
10k
Figure 21.
THD+N
vs.
Amplitude
EMIRR IN+
vs.
Power at 400 MHz
110
100
0.1
VS = 3.3V
0.01
0.001
90
80
125°C
85°C
70
60
50
25°C
-40°C
40
30
VS = 5V
100m
1
fRF = 400 MHz
20
-40
-30
-20
10
VOUT (Vpp)
-10
0
Figure 23.
EMIRR IN+
vs.
Power at 900 MHz
EMIRR IN+
vs.
Power at 1800 MHz
120
110
110
100
100
EMIRR V_PEAK (dB)
120
125°C
85°C
80
70
60
25°C
-40°C
50
70
60
50
40
30
0
25°C
-40°C
80
30
-10
125°C
85°C
90
40
fRF = 900 MHz
20
-40
-30
-20
10
RF INPUT PEAK VOLTAGE (dBVp)
Figure 22.
90
100k
120
Av = +1
EMIRR V_PEAK (dB)
1k
FREQUENCY (Hz)
RL = 10 k:
f = 1 kHz
BW = 20 kHz
0.0001
10m
100
Figure 20.
Av = +10
THD+N (%)
0.001
10
10 100 1k 10k 100k 1M
FREQUENCY (Hz)
EMIRR V_PEAK (dB)
10
1
fRF = 1800 MHz
20
-40
-30
-20
10
RF INPUT PEAK VOLTAGE (dBVp)
-10
0
10
RF INPUT PEAK VOLTAGE (dBVp)
Figure 24.
Figure 25.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
11
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
Typical Performance Characteristics (continued)
+
−
At TA = 25°C, V = 5V, V = 0V, VCM = V+/2, and RL =10 kΩ to V+/2, unless otherwise specified.
EMIRR IN+
vs.
Power at 2400 MHz
EMIRR IN+
vs.
Frequency
120
110
125°C
85°C
EMIRRV_PEAK (dB)
EMIRR V_PEAK (dB)
100
90
80
25°C
-40°C
70
60
50
120
110
100
90
80
70
60
50
40
30
20
125°C
85°C
25°C
-40°C
40
+
V = 3.3V, 5.0V
30
fRF = 2400 MHz
20
-40
-30
-20
VRF PEAK
== -20
dBVp
V
-20dBVp
PEAK
-10
0
10
10
1000
10000
FREQUENCY (MHz)
RF INPUT PEAK VOLTAGE (dBVp)
Figure 26.
12
100
Figure 27.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
APPLICATION INFORMATION
INTRODUCTION
The LMV881 is an operational amplifier with low offset, low noise and a high current rail-to-rail output. These
specifications make the LMV881 great choices for medical and instrumentation applications such as diagnosis
equipment and power line monitors. The low supply current and 1.8V shutdown logic is perfect for battery
powered equipment. The small package make this device a perfect choice for portable electronics.
Additionally, the EMI hardening makes the LMV881 a must for applications that are exposed to Radio Frequency
(RF) signals such as the signals transmitted by mobile phones or wireless computer peripherals. The LMV881
will effectively reduce disturbances caused by RF signals to a level that will be hardly noticeable. This again
reduces the need for additional filtering and shielding. Using this EMI resistant op amp will thus reduce the
number of components and space needed for applications that are affected by EMI, and will help applications,
not yet identified as possible EMI sensitive, to be more robust for EMI.
SHUTDOWN MODE
To conserve battery life in portable applications, the LMV881 can be disabled when the shutdown pin voltage is
pulled low. The shutdown pin is designed for 1.8V logic levels, with thresholds independent of total supply
voltage.
In shutdown mode, the amplifier is disabled and the output is hard-clamped by an internal MOSFET to V− to
provide a known output state. Care must be taken not to exceed the maximum output sinking current (specified
in the electrical table) during shutdown.
The shutdown pin input thresholds are referenced to the V- pin, and may need to be level shifted in split supply
applications. Continuous voltages between 0.9V and 1.1V on the shutdown pins should be avoided to prevent
excessive supply current draw due to internal shoot-through currents.
The shutdown pin cannot be left unconnected. In case shut down operation is not needed, the shutdown pin
should be connected to V+ for normal operation. Leaving the shutdown pin floating will result in an undefined
operation modes, either shutdown or active, or even oscillating between the two modes.
INPUT CHARACTERISTICS
The input common mode voltage range of the LMV881 includes ground, and can even sense well below ground.
The CMRR level does not degrade for input levels up to 1.2V below the positive supply voltage. For a supply
voltage of 5V, the maximum voltage that should be applied to the input for best CMRR performance is thus 3.8V.
When not configured as unity gain, this input limitation will usually not degrade the effective signal range. The
output is rail-to-rail and therefore will introduce no limitations to the signal range.
The typical offset is only 70 µV and the TCVOS is 0.7 μV/°C, placing the specifications close to that of precision
op amps.
INPUT CAPACITANCE
The LMV881's input capacitance is larger than most typical op-amps due to the internal EMIRR circuitry. The
differential mode capacitance (capacitance between the two input pins) is about 15pF. The common mode
capacitance (“stray” input capacitance) is about 5pF on each input pin to the supplies. This extra input
capacitance will cause peaking to occur with source impedances above 10KΩ. The effect of source resistance on
the peaking is shown in Figure 28 below, where the source resistance is effectively the value of RF.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
13
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
NORMALIZED BANDWIDTH (dB)
21
RL = 1 M:
18 VOUT = 200 mVPP
VS = 3.3V
15
RF = 10 k:
RF = 1 k:
12
9
RF = 100:
6
3
0
RF = 0
-3
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 28. Effect of Source Resistance on Peaking
The 15pF differential mode capacitance mostly cancels due to the feedback bootstrapping effect at lower
frequencies, but there still remains about 8pF of equivalent capacitance on each pin as seen by the circuit. The
designer should be aware of this capacitance and make the appropriate adjustments to their circuit.
OUTPUT CHARACTERISTICS
During shutdown, the output is hard-clamped to V- with a resistance of just a few ohms.
In normal operation, the output is rail-to-rail. When loading the output with a 10 kΩ resistor the maximum swing
of the output is typically 3 mV from the positive and negative rail.
The output of the LMV881 can typically drive peak currents up to 70 mA at 3.3V, and even up to 110 mA at 5V.
However, power dissipation in small packages can become an issue at high drive currents.
The LMV881 can be connected as a non-inverting unity gain amplifier (“buffer”). This configuration is the most
sensitive to capacitive loading. The combination of a capacitive load placed at the output of an amplifier along
with the amplifier’s output impedance creates a phase lag, which reduces the phase margin of the amplifier. If
the phase margin is significantly reduced, the response will be under damped which causes peaking in the
transfer and, when there is too much peaking, the op amp might start oscillating.
The LMV881 can directly drive capacitive loads up to 200 pF without any stability issues. In order to drive heavier
capacitive loads, an isolation resistor, RISO, should be used, as shown in Figure 29. By using this isolation
resistor, the capacitive load is isolated from the amplifier’s output, and hence, the pole caused by CL is no longer
in the feedback loop. The larger the value of RISO, the more stable the amplifier will be. If the value of RISO is
sufficiently large, the feedback loop will be stable, independent of the value of CL. However, larger values of RISO
result in reduced output swing and reduced output current drive.
VIN
RISO
VOUT
+
CL
Figure 29. Isolating Capacitive Load
A resistor value of around 50Ω would be sufficient. As an example some values are given in the following table,
for 5V and an open loop gain of 111 dB.
14
CLOAD
RISO
300 pF
62Ω
400 pF
55Ω
500 pF
50Ω
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
When increasing the closed-loop gain the capacitive load can be increased even further. With a closed loop gain
of 2 and a 27Ω isolation resistor, the load can be 1 nF
EMIRR
With the increase of RF transmitting devices in the world, the electromagnetic interference (EMI) between those
devices and other equipment becomes a bigger challenge. The LMV881 is a EMI hardened op amp which is
specifically designed to overcome electromagnetic interference. Along with EMI hardened op amps, the EMIRR
parameter is introduced to unambiguously specify the EMI performance of an op amp. This section presents an
overview of EMIRR. A detailed description on this specification for EMI hardened op amps can be found in
Application Note AN-1698.
The dimensions of an op amp IC are relatively small compared to the wavelength of the disturbing RF signals. As
a result, the op amp itself will hardly receive any disturbances. The RF signals interfering with the op amp are
dominantly received by the PCB and wiring connected to the op amp. The received RF signals on the pins of the
op amp can be represented by voltages and currents. This representation significantly simplifies the
unambiguous measurement and specification of the EMI performance of an op amp.
RF signals interfere with op amps via the non-linearity of the op amp circuitry. This non-linearity results in the
detection of the so called out-of-band signals. The obtained effect is that the amplitude modulation of the out-ofband signal is downconverted into the base band. This base band can easily overlap with the band of the op
amp circuit. As an example Figure 30 depicts a typical output signal of a unity-gain connected op amp in the
presence of an interfering RF signal. Clearly the output voltage varies in the rhythm of the on-off keying of the RF
carrier.
RF
RF SIGNAL
VOUT OPAMP
(AV = 1)
NO RF
VOS + VDETECTED
VOS
Figure 30. Offset Voltage Variation Due to an Interfering RF Signal
EMIRR Definition
To identify EMI hardened op amps, a parameter is needed that quantitatively describes the EMI performance of
op amps. A quantitative measure enables the comparison and the ranking of op amps on their EMI robustness.
Therefore the EMI Rejection Ratio (EMIRR) is introduced. This parameter describes the resulting input-referred
offset voltage shift of an op amp as a result of an applied RF carrier (interference) with a certain frequency and
level. The definition of EMIRR is given by:
§V
·
RF_PEAK ¸
EMIRRV RF_PEAK = 20 log ¨
¸
¨ 'V
OS ¹
©
where
•
•
VRF_PEAK is the amplitude of the applied un-modulated RF signal (V)
ΔVOS is the resulting input-referred offset voltage shift (V)
(1)
The offset voltage depends quadratically on the applied RF level, and therefore, the RF level at which the EMIRR
is determined should be specified. The standard level for the RF signal is 100 mVP. Application Note AN-1698
addresses the conversion of an EMIRR measured for an other signal level than 100 mVP. The interpretation of
the EMIRR parameter is straightforward. When two op amps have EMIRRs which differ by 20 dB, the resulting
error signals when used in identical configurations, differs by 20 dB as well. So, the higher the EMIRR, the more
robust the op amp.
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
15
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
Coupling an RF Signal to the IN+ Pin
Each of the op amp pins can be tested separately on EMIRR. In this section the measurements on the IN+ pin
(which, based on symmetry considerations, also apply to the IN- pin) are discussed. In Application Note AN-1698
the other pins of the op amp are treated as well. For testing the IN+ pin the op amp is connected in the unity gain
configuration. Applying the RF signal is straightforward as it can be connected directly to the IN+ pin. As a result
the RF signal path has a minimum of components that might affect the RF signal level at the pin. The circuit
diagram is shown in Figure 31. The PCB trace from RFIN to the IN+ pin should be a 50Ω stripline in order to
match the RF impedance of the cabling and the RF generator. On the PCB a 50Ω termination is used. This 50Ω
resistor is also used to set the bias level of the IN+ pin to ground level.
For determining the EMIRR, two measurements are needed: one is measuring the DC output level when the RF
signal is off; and the other is measuring the DC output level when the RF signal is switched on. The difference of
the two DC levels is the output voltage shift as a result of the RF signal. As the op amp is in the unity gain
configuration, the input referred offset voltage shift corresponds one-to-one to the measured output voltage shift.
C2
10 µF
+
VDD
C3
100 pF
RFin
+
R1
50:
Out
C4
100 pF
C1
22 pF
+
VSS
C5
10 µF
Figure 31. Circuit for Coupling the RF Signal to IN+
Cell Phone Call
The effect of electromagnetic interference is demonstrated in a setup where a cell phone interferes with a
pressure sensor application. The application is show in Figure 33.
This application needs two op amps. The op amp configured as a buffer and connected at the negative output of
the pressure sensor prevents the loading of the bridge by resistor R2. The buffer also prevents the resistors of
the sensor from affecting the gain of the following gain stage. The op amps are placed in a single supply
configuration.
The experiment is performed on two different op amps: a typical standard op amp and the LMV881 EMI
hardened op amp. A cell phone is placed on a fixed position a couple of centimeters from the op amps in the
sensor circuit.
When the cell phone is called, the PCB and wiring connected to the op amps receive the RF signal.
Subsequently, the op amps detect the RF voltages and currents that end up at their pins. The resulting effect on
the output of the second op amp is shown in Figure 32.
16
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
VOUT (0.5V/DIV)
www.ti.com
Typical Opamp
LMV881
TIME (0.5s/DIV)
Figure 32. Comparing EMI Robustness
The difference between the two types of op amps is clearly visible. The typical standard op amp has an output
shift (disturbed signal) larger than 1V as a result of the RF signal transmitted by the cell phone. The LMV881 EMI
hardened op amp does not show any significant disturbances. This means that the RF signal will not disturb the
signal entering the ADC when using the LMV881.
R1
2.4 k:
VDD
VDD
PRESSURE
SENSOR
+
-
R2
100:
LMV881
+
LMV881
+
ADC
VOUT
Figure 33. Pressure Sensor Application
DECOUPLING AND LAYOUT
Care must be given when creating a board layout for the op amp. For decoupling the supply lines it is suggested
that 10 nF capacitors be placed as close as possible to the op amp. For single supply, place a capacitor between
V+ and V−. For dual supplies, place one capacitor between V+ and the board ground, and a second capacitor
between ground and V−.
Even with the LMV881 inherent hardening against EMI, it is still recommended to keep the input traces short and
as far as possible from RF sources. Then the RF signals entering the chip are as low as possible and the
remaining EMI can be almost, completely eliminated in the chip by the EMI reducing features of the LMV881 .
Most of the EMI will be shunted out to the supply pins, so the supply pins should have bypassing and grounding
suitable well up into the gigahertz range. A small 100pF RF grade capacitor directly from the supply pin to the
nearest suitable RF ground is recommended.
LOAD CELL SENSOR APPLICATION
The LMV881 can be used for weight measuring system applications which use a load cell sensor. Examples of
such systems are: bathroom weight scales, industrial weight scales and weight measurement devices on moving
equipment such as forklift trucks.
The following example describes a typical load cell sensor application that can be used as a starting point for
many different types of sensors and applications. Applications in environments where EMI may appear would
especially benefit from the EMIRR performance of the LMV881 .
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
17
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
Load Cell Characteristics
The load cell used in this example is a Wheatstone bridge. The value of the resistors in the bridge changes when
pressure is applied to the sensor. This change of the resistor values will result in a differential output voltage
depending on the sensitivity of the sensor, the used supply voltage and the applied pressure. The difference
between the output at full scale pressure and the output at zero pressure is defined as the span of the load cell.
A typical value for the span is 10 mV/V.
The circuit configuration should be chosen such that loading of the sensor is prevented. Loading of the resistor
bridge due to the circuit following the sensor, could result in incorrect output voltages of the sensor.
Load Cell Example
Figure 34 shows a typical schematic for a load cell application. It uses a single supply and has an adjustment for
both positive and negative offset of the load cell. An ADC converts the amplified signal to a digital signal.
The op amps A1 and A2 are configured as buffers, and are connected at both the positive and the negative
output of the load cell. This is to prevent the loading of the resistor bridge in the sensor by the resistors
configuring the differential op amp circuit (op amp A4). The buffers also prevent the resistors of the sensor from
affecting the gain of the following gain stage. The third buffer (A3) is used to create a reference voltage, to
correct for the offset in the system.
Given the differential output voltage VSENSE of the load cell the output signal of this op amp configuration, VOUT,
equals:
R3 x V
R3
R3
x VDD
SENSE + §
+ 1 x VREF R1
© R5
R5
§
©
VOUT =
(2)
To align the pressure range with the full range of an ADC the correct gain needs to be set. To calculate the
correct gain, the power supply voltage and the span of the load cell are needed. For this example a power supply
of 5V is used and the span of the sensor, in this case a 125 kg sensor, is 100 mV. With the configuration as
shown in Figure 34, this signal is covering almost the full input range of the ADC. With no weight on the load cell,
the output of the sensor and the op amp A4 will be close to 0V. With the full weight on the load cell, the output of
the sensor is 100 mV, and will be amplified with the gain from the configuration. In the case of the configuration
of Figure 34 the gain is R3/R1 = 5 kΩ/100Ω = 50. This will result in a maximum output of 100 mV x 50 = 5V,
which covers the full range of the ADC.
For further processing the digital signal can be processed by a microprocessor following the ADC, this can be
used to display or log the weight on the load cell. To get a resolution of 0.5 kg, the LSB of the ADC should be
smaller then 0.5 kg/125 kg = 1/1000. A 12-bit ADC would be sufficient as this gives 4096 steps. A 12-bit ADC
such as the two channel 12-bit ADC122S021 can be used for this application.
18
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
LMV881
www.ti.com
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
VDD
R5
5 k:
VDD
A1
LOAD
CELL
+
R3
5 k:
R1
100:
VDD
LMV881
-
+
A4
ADC
LMV881
VSENSE
A2
-
R2
100:
+
VOUT
LMV881
+
R4
5 k:
VDD
R6
80 k:
P1
20 k:
A3
-
VREF
LMV881
+
R6
80 k:
Figure 34. Load Cell Application
EVALUATION BOARD
The LMV881 has a multi-function evaluation board available for ease of bench testing and prototyping. The
board has a separate users guide that describes the various configurations. The boards can be ordered through
the web or through your local representative.
Device
Package
Evaluation Board Part Number
LMV881
µUQFN
LMV881EVAL
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
19
LMV881
SNOSC62B – JANUARY 2012 – REVISED MAY 2013
www.ti.com
REVISION HISTORY
Changes from Revision A (May 2013) to Revision B
•
20
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 19
Submit Documentation Feedback
Copyright © 2012–2013, Texas Instruments Incorporated
Product Folder Links: LMV881
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2016
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMV881LE/NOPB
ACTIVE
USON
NKK
6
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV881LEE/NOPB
ACTIVE
USON
NKK
6
250
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
LMV881LEX/NOPB
ACTIVE
USON
NKK
6
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Jul-2016
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jul-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
LMV881LE/NOPB
USON
NKK
6
LMV881LEE/NOPB
USON
NKK
LMV881LEX/NOPB
USON
NKK
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
1000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
6
250
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
6
3000
180.0
9.5
1.15
1.6
0.75
4.0
8.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
18-Jul-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMV881LE/NOPB
USON
NKK
6
1000
184.0
184.0
19.0
LMV881LEE/NOPB
USON
NKK
6
250
184.0
184.0
19.0
LMV881LEX/NOPB
USON
NKK
6
3000
184.0
184.0
19.0
Pack Materials-Page 2
MECHANICAL DATA
NKK0006A
TOP SIDE OF PACKAGE
BOTTOM SIDE OF PACKAGE
LEH06A (Rev A)
www.ti.com
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2016, Texas Instruments Incorporated