DS90LV804 www.ti.com SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 DS90LV804 4-Channel 800 Mbps LVDS Buffer/Repeater Check for Samples: DS90LV804 FEATURES In order to maximize signal integrity, the DS90LV804 features both an internal input and output (source) termination to eliminate these extra components from the board, and to also place the terminations as close as possible to receiver inputs and driver output. This is especially significant when driving longer cables. 1 • • • 23 • • • • • • 800 Mbps Data Rate per Channel Low Output Skew and Jitter LVDS/CML/LVPECL Compatible Input, LVDS Output On-Chip 100Ω Input and Output Termination 12 kV ESD Protection on LVDS Outputs Single 3.3V Supply Very Low Power Consumption Industrial -40 to +85°C Temperature Range Small WQFN Package Footprint The DS90LV804, available in the WQFN (Leadless Leadframe Package) package, minimizes the footprint, and improves system performance. An output enable pin is provided, which allows the user to place the LVDS outputs and internal biasing generators in a TRI-STATE®, low power mode. The differential inputs interface to LVDS, and Bus LVDS signals such as those on TI's 10-, 16-, and 18bit Bus LVDS SerDes, as well as CML and LVPECL. The differential inputs are internally terminated with a 100Ω resistor to improve performance and minimize board space. This function is especially useful for boosting signals over lossy cables or point-to-point backplane configurations. DESCRIPTION The DS90LV804 is a four channel 800 Mbps LVDS buffer/repeater. In many large systems, signals are distributed across cables and signal integrity is highly dependent on the data rate, cable type, length, and the termination scheme. Block and Connection Diagrams EN IN0+ OUT0+ IN0- OUT0- IN1+ OUT1+ IN1- OUT1- IN2+ OUT2+ IN2- OUT2- IN3+ OUT3+ IN3- OUT3- Figure 1. DS90LV804 Block Diagram 1 2 3 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. TRI-STATE is a registered trademark of National Semiconductor Corporation. All other trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2005–2013, Texas Instruments Incorporated DS90LV804 GND 5 GND 6 VDD GND 7 VDD VDD 8 VDD www.ti.com EN SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 4 3 2 1 IN0+ 9 32 OUT0+ IN0- 10 31 OUT0- IN1+ 11 30 OUT1+ IN1- 12 29 OUT1- IN2+ 13 28 OUT2+ IN2- 14 27 OUT2- IN3+ 15 26 OUT3+ IN3- 16 17 18 OUT3- 21 22 VDD VDD N/C N/C 20 25 23 24 VDD 19 VDD GND GND DAP (GND) DS90LV804 WQFN Pinout (Top View) These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) −0.3V to +4.0V Supply Voltage (VDD) CMOS Input Voltage (EN) −0.3V to (VDD+0.3V) LVDS Input Voltage (2) −0.3V to (VDD+0.3V) LVDS Output Voltage −0.3V to (VDD+0.3V) LVDS Output Short Circuit Current +90 mA Junction Temperature +150°C Storage Temperature −65°C to +150°C Lead Temperature (Solder, 4sec) 260°C Max Pkg Power Capacity @ 25°C 4.16W Thermal Resistance θJA θJC Package Derating above +25°C EIAJ, 0Ω, 200pF Charged Device Model HBM, 1.5kΩ, 100pF ESD Last Passing Voltage (All other pins) EIAJ, 0Ω, 200pF Charged Device Model (1) (2) 2 3.5°C/W 33.3mW/°C HBM, 1.5kΩ, 100pF ESD Last Passing Voltage (LVDS output pins) 29.5°C/W 12 kV 250V 1000V 8 kV 250V 1000V Absolute maximum ratings are those values beyond which damage to the device may occur. The databook specifications should be met, without exception, to ensure that the system design is reliable over its power supply, temperature, and output/input loading variables. TI does not recommend operation of products outside of recommended operation conditions. VID max < 2.4V Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 DS90LV804 www.ti.com SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 Recommended Operating Conditions Supply Voltage (VCC) 3.15V to 3.45V Input Voltage (VI) (1) 0V to VDD Output Voltage (VO) 0V to VDD Operating Temperature (TA) (1) −40°C to +85°C Industrial VID max < 2.4V Electrical Characteristics Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (1) Max Units LVTTL DC SPECIFICATIONS (EN) VIH High Level Input Voltage 2.0 VDD V VIL Low Level Input Voltage GND 0.8 V IIH High Level Input Current VIN = VDD = VDDMAX −10 +10 µA IIL Low Level Input Current VIN = VSS, VDD = VDDMAX −10 +10 µA CIN1 Input Capacitance Any Digital Input Pin to VSS VCL Input Clamp Voltage ICL = −18 mA −1.5 3.5 pF −0.8 V LVDS INPUT DC SPECIFICATIONS (INn±) VTH Differential Input High Threshold (2) VCM = 0.8V to 3.4V, VDD = 3.45V VTL Differential Input Low Threshold (2) VCM = 0.8V to 3.4V, VDD = 3.45V VID Differential Input Voltage VCM = 0.8V to 3.4V, VDD = 3.45V 100 2400 mV VCMR Common Mode Voltage Range VID = 150 mV, VDD = 3.45V 0.05 3.40 V CIN2 Input Capacitance IN+ or IN− to VSS IIN Input Current 0 −100 100 0 mV mV 3.5 pF VIN = 3.45V, VDD = VDDMAX −10 +10 µA VIN = 0V, VDD = VDDMAX −10 +10 µA 600 mV 35 mV 1.475 V 35 mV −90 mA LVDS OUTPUT DC SPECIFICATIONS (OUTn±) VOD Differential Output Voltage (2) ΔVOD Change in VOD between Complementary States 250 RL = 100Ω external resistor between OUT+ and OUT− 500 −35 VOS Offset Voltage (3) ΔVOS Change in VOS between Complementary States IOS Output Short Circuit Current OUT+ or OUT− Short to GND −60 COUT2 Output Capacitance OUT+ or OUT− to GND when TRI-STATE 5.5 Total Supply Current All inputs and outputs enabled and active, terminated with external differential load of 100Ω between OUT+ and OUT-. 117 140 mA TRI-STATE Supply Current EN = 0V 2.7 6 mA 1.05 1.18 −35 pF SUPPLY CURRENT (Static) ICC ICCZ (1) (2) (3) Typical parameters are measured at VDD = 3.3V, TA = 25°C. They are for reference purposes, and are not production-tested. Differential output voltage VOD is defined as ABS(OUT+–OUT−). Differential input voltage VID is defined as ABS(IN+–IN−). Output offset voltage VOS is defined as the average of the LVDS single-ended output voltages at logic high and logic low states. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 3 DS90LV804 SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Over recommended operating supply and temperature ranges unless other specified. Symbol Parameter Conditions Min Typ (1) Max Units 210 300 ps 210 300 ps 2.0 3.2 ns 2.0 3.2 ns 25 80 ps 50 125 ps SWITCHING CHARACTERISTICS—LVDS OUTPUTS tLHT Differential Low to High Transition Time tHLT Differential High to Low Transition Time tPLHD Differential Low to High Propagation Delay tPHLD tSKD1 Use an alternating 1 and 0 pattern at 200 Mbps, measure between 20% and 80% of VOD (4) Use an alternating 1 and 0 pattern at 200 Mbps, measure at 50% VOD between input to output. Differential High to Low Propagation Delay (4) Pulse Skew |tPLHD–tPHLD| tSKCC Output Channel to Channel Skew Difference in propagation delay (tPLHD or tPHLD) among all output channels (4) tSKP Part to Part Skew Common edge, parts at same temp and VCC (4) tJIT Jitter (5) 1.1 ns RJ - Alternating 1 and 0 at 400 MHz (6) 1.1 1.5 psrms DJ - K28.5 Pattern, 800 Mbps (7) 15 35 psp-p 30 23 TJ - PRBS 2 -1 Pattern, 800 Mbps tON tOFF (4) (5) (6) (7) (8) (8) 55 psp-p LVDS Output Enable Time Time from EN to OUT± change from TRI-STATE to active. 300 ns LVDS Output Disable Time Time from EN to OUT± change from active to TRISTATE. 12 ns Not production tested. Ensured by statistical analysis on a sample basis at the time of characterization. Jitter is not production tested, but ensured through characterization on a sample basis. Random Jitter, or RJ, is measured RMS with a histogram including 1500 histogram window hits. The input voltage = VID = 500mV, 50% duty cycle at 400 MHz, tr = tf = 50ps (20% to 80%). Deterministic Jitter, or DJ, is measured to a histogram mean with a sample size of 350 hits. The input voltage = VID = 500mV, K28.5 pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). The K28.5 pattern is repeating bit streams of (0011111010 1100000101). Total Jitter, or TJ, is measured peak to peak with a histogram including 3500 window hits. Stimulus and fixture Jitter has been subtracted. The input voltage = VID = 500mV, 223-1 PRBS pattern at 800 Mbps, tr = tf = 50ps (20% to 80%). Typical Application LVDS I/O Submit Documentation Feedback FPGA or ASIC 4 Cable or Backplane LVDS I/O FPGA or ASIC DS90LV804 Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 DS90LV804 www.ti.com SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 APPLICATION INFORMATION INTERNAL TERMINATIONS The DS90LV804 has integrated termination resistors on both the input and outputs. The inputs have a 100Ω resistor across the differential pair, placing the receiver termination as close as possible to the input stage of the device. The LVDS outputs also contain an integrated 100Ω ohm termination resistor, this resistor is used to reduce the effects of Near End Crosstalk (NEXT) and does not take the place of the 100 ohm termination at the inputs to the receiving device. The integrated terminations improve signal integrity and decrease the external component count resulting in space savings. OUTPUT CHARACTERISTICS The output characteristics of the DS90LV804 have been optimized for point-to-point backplane and cable applications, and are not intended for multipoint or multidrop signaling. TRI-STATE MODE The EN input activates a hardware TRI-STATE mode. When the TRI-STATE mode is active (EN=L), all input and output buffers and internal bias circuitry are powered off and disabled. Outputs are tri-stated in TRI-STATE mode. When exiting TRI-STATE mode, there is a delay associated with turning on bandgap references and input/output buffer circuits as indicated in the LVDS Output Switching Characteristics INPUT FAILSAFE BIASING External pull up and pull down resistors may be used to provide enough of an offset to enable an input failsafe under open-circuit conditions. This configuration ties the positive LVDS input pin to VDD thru a pull up resistor and the negative LVDS input pin is tied to GND by a pull down resistor. The pull up and pull down resistors should be in the 5kΩ to 15kΩ range to minimize loading and waveform distortion to the driver. The common-mode bias point ideally should be set to approximately 1.2V (less than 1.75V) to be compatible with the internal circuitry. Please refer to application note AN-1194 “Failsafe Biasing of LVDS Interfaces” for more information. INPUT INTERFACING The DS90LV804 accepts differential signals and allow simple AC or DC coupling. With a wide common mode range, the DS90LV804 can be DC-coupled with all common differential drivers (that is, LVPECL, LVDS, CML). Figure 2, Figure 3, and Figure 4 illustrate typical DC-coupled interface to common differential drivers. Note that the DS90LV804 inputs are internally terminated with a 100Ω resistor. LVDS Driver DS90LV804 Receiver 100: Differential T-Line OUT+ IN+ 100: OUT- IN- Figure 2. Typical LVDS Driver DC-Coupled Interface to DS90LV804 Input Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 5 DS90LV804 SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com CML3.3V or CML2.5V Driver VCC 50: DS90LV804 Receiver 100: Differential T-Line 50: OUT+ IN+ 100: IN- OUT- Figure 3. Typical CML Driver DC-Coupled Interface to DS90LV804 Input LVPECL Driver OUT+ 100: Differential T-Line LVDS Receiver IN+ 100: OUT150-250: IN150-250: Figure 4. Typical LVPECL Driver DC-Coupled Interface to DS90LV804 Input OUTPUT INTERFACING The DS90LV804 outputs signals that are compliant to the LVDS standard. Their outputs can be DC-coupled to most common differential receivers. Figure 5 illustrates typical DC-coupled interface to common differential receivers and assumes that the receivers have high impedance inputs. While most differential receivers have a common mode input range that can accommodate LVDS compliant signals, it is recommended to check respective receiver's data sheet prior to implementing the suggested interface implementation. DS90LV804 Driver Differential Receiver 100: Differential T-Line OUT+ IN+ CML or LVPECL or LVDS 100: 100: IN- OUT- Figure 5. Typical DS90LV804 Output DC-Coupled Interface to an LVDS, CML or LVPECL Receiver 6 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 DS90LV804 www.ti.com SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 PIN DESCRIPTIONS Pin Name WQFN Pin Number I/O, Type Description DIFFERENTIAL INPUTS IN0+ IN0− 9 10 I, LVDS Channel 0 inverting and non-inverting differential inputs. IN1+ IN1− 11 12 I, LVDS Channel 1 inverting and non-inverting differential inputs. IN2+ IN2− 13 14 I, LVDS Channel 2 inverting and non-inverting differential inputs. IN3+ IN3− 15 16 I, LVDS Channel 3 inverting and non-inverting differential inputs. DIFFERENTIAL OUTPUTS OUT0+ OUT0− 32 31 O, LVDS Channel 0 inverting and non-inverting differential outputs (1) OUT1+ OUT1− 30 29 O, LVDS Channel 1 inverting and non-inverting differential outputs (1) OUT2+ OUT2− 28 27 O, LVDS Channel 2 inverting and non-inverting differential outputs (1) OUT3+ OUT3- 26 25 O, LVDS Channel 3 inverting and non-inverting differential outputs (1) DIGITAL CONTROL INTERFACE EN 8 I, LVTTL Enable pin. When EN is LOW, the driver is disabled and the LVDS outputs are in TRISTATE. When EN is HIGH, the driver is enabled. LVCMOS/LVTTL level input. POWER VDD 3, 4, 6, 7, 19, 20, 21, 22 I, Power VDD = 3.3V, ±5% GND 1, 2, 5, 17, 18 (2) I, Power Ground reference for LVDS and CMOS circuitry. For the WQFN package, the DAP is used as the primary GND connection to the device. The DAP is the exposed metal contact at the bottom of the WQFN-32 package. It should be connected to the ground plane with at least 4 vias for optimal AC and thermal performance. The pin numbers listed should also be tied to ground for proper biasing. N/C 23, 24 (1) (2) No Connect The LVDS outputs do not support a multidrop (BLVDS) environment. The LVDS output characteristics of the DS90LV804 device have been optimized for point-to-point backplane and cable applications. Note that for the WQFN package the GND is connected thru the DAP on the back side of the WQFN package in addition to grounding actual pins on the package as listed. Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 7 DS90LV804 SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 www.ti.com Typical Performance Characteristics POWER SUPPLY CURRENT (mA) 350 300 250 Clock 200 150 100 PRBS-23 50 0 0 0.25 0.5 0.75 1.0 BIT DATA RATE (Gbps) A. Dynamic power supply current was measured while running a clock or PRBS 223-1 pattern with all 4 channels active. VCC = 3.3V, TA = +25°C, VID = 0.5V, VCM = 1.2V Figure 6. Power Supply Current vs Bit Data Rate PACKAGING INFORMATION The Leadless Leadframe Package (WQFN) is a leadframe based chip scale package (CSP) that may enhance chip speed, reduce thermal impedance, and reduce the printed circuit board area required for mounting. The small size and very low profile make this package ideal for high density PCBs used in small-scale electronic applications such as cellular phones, pagers, and handheld PDAs. The WQFN package is offered in the no Pullback configuration. In the no Pullback configuration the standard solder pads extend and terminate at the edge of the package. This feature offers a visible solder fillet after board mounting. The WQFN has the following advantages: • Low thermal resistance • Reduced electrical parasitics • Improved board space efficiency • Reduced package height • Reduced package mass For more details about WQFN packaging technology, refer to applications note AN-1187, "Leadless Leadframe Package". 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 DS90LV804 www.ti.com SNLS195L – SEPTEMBER 2005 – REVISED APRIL 2013 REVISION HISTORY Changes from Revision K (April 2013) to Revision L • Page Changed layout of National Data Sheet to TI format ............................................................................................................ 8 Submit Documentation Feedback Copyright © 2005–2013, Texas Instruments Incorporated Product Folder Links: DS90LV804 9 PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) DS90LV804TSQ NRND WQFN RTV 32 1000 TBD Call TI Call TI -40 to 85 804TSQ DS90LV804TSQ/NOPB ACTIVE WQFN RTV 32 1000 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 804TSQ DS90LV804TSQX/NOPB ACTIVE WQFN RTV 32 4500 Green (RoHS & no Sb/Br) CU SN Level-3-260C-168 HR -40 to 85 804TSQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 8-Oct-2015 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DS90LV804TSQ WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 DS90LV804TSQ/NOPB WQFN RTV 32 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 DS90LV804TSQX/NOPB WQFN RTV 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 13-Jul-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) DS90LV804TSQ WQFN RTV 32 1000 213.0 191.0 55.0 DS90LV804TSQ/NOPB WQFN RTV 32 1000 213.0 191.0 55.0 DS90LV804TSQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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