2A Low Dropout Regulator with Enable General Description EC8320 Features The EC8320 is a high performance positive voltage ● Adjustable Output Low to 0.8V regulator designed for use in applications requiring very ● Input Voltage as Low as 1.6V and VPP Voltage 5V low Input voltage and very low dropout voltage at up to 2 ● 240mV Dropout @ 2A amps. It operates with a VIN as low as 1.6V and VPP ● Over Current and Over Temperature Protection voltage 5V with output voltage programmable as low as ● Enable Pin 0.8V. The EC8320 features ultra low dropout, ideal for ● Low Reverse Leakage (Output to Input ) applications where VOUT is very close to VIN. ● Power SOP-8(EP) Packages with Thermal Pad Additionally, the EC8320 has an enable pin to further ● ±2% Output Voltage reduce power dissipation while shutdown. The EC8320 ● VO Power OK Signal provides excellent regulation over variations in line, ● 1.2V, 1.5V, 1.8V, 2.5V Options and Adjustable load and temperature. The EC8320 provides a power OK ● Externally Using Resistors signal to indicate if the voltage level of VO reaches ● VO Pull Low Resistance when Disable 92% of its rating value. The EC8320 is available in the power SOP-8(Exposed PAD) package. It is available with 1.2V, 1.5V, 1.8V and 2.5V internally preset outputs that are also adjustable using external resistors. Applications ● Motherboards ● Peripheral Cards ● Network Cards ● Set Top Boxes ● Notebook Computers Pin Assignments E-CMOS Corp. (www.ecmos.com.tw) Page 1 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Pin Description PIN NAME Description 1 PGOOD Assert high once VO reaches 92% of its rating voltage. Open-drain output. 2 EN Enable Input. (Active High) 3 VIN Input voltage. Large bulk capacitance should be placed closely to this pin. A 10µF ceramic capacitor is recommended at this pin. 4 VDD Input voltage for controlling circuit. 5 NC Not connected. 6 VOUT The power output of the device. A pull low resistance exists when deactivate device by VEN. 7 ADJ This pin, EC8320A/B when grounded, sets the output voltage by the internal feedback resistors.If external feedback resistors are used, the output voltage will be VO = 0.8(R1+R2)/R2 Volts. 8 GND Reference ground. Ordering Information Part Number Package Marking 8320A XXLLL YYWWT EC8320AXXMHR SOP-8 (Exposed PAD) EC8320BXXMHR E-CMOS Corp. (www.ecmos.com.tw) 8320B XXLLL YYWWT Page 2 of 16 Marking Information 1.XX: Output Voltage(Ex- 12:1.2V;AJ:ADJ) 2. LLL: Last three number of Lot No 3. YYWW: Date Code 4. T: Internal Tracking Code 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Package Types Figure 1. Package Types of EC8320 Function Block Diagram Figure2:Functional Block Diagram of EC8320 E-CMOS Corp. (www.ecmos.com.tw) Page 3 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Absolute Maximum Ratings Parameter Rating Unit VCNTL Supply Voltage (VCNTL to GND) -0.3 ~ 6 V VIN Supply Voltage (VIN to GND) -0.3 ~ 6 V VOUT to GND Voltage -0.3 ~ VIN+0.3 V PGOOD to GND Voltage -0.3 ~ 7 V EN, ADJ to GND Voltage -0.3 ~ VCNTL+0.3 V Power Dissipation Internally Limited Maximum Junction Temperature 150 ℃ Storage Temperature Range -65°C ≤TJ ≤ +150 ℃ Lead Temperature (soldering, 10sec) 260 ℃ Thermal Resistance Junction to Ambient 50 ℃/W Thermal Resistance Junction to Case 20 ℃/W Operating Temperature Range -40 to +125 ℃ Storage Temperature -65 to +150 ℃ ESD Rating (Human Body Model) 2000 V Note1: Stresses greater than those listed under Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operationof the device at these or any other conditions above those indicated in the operation is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Recommended Operating Conditions Symbol Parameter Range Unit VDD VCNTL Supply Voltage 3.0 ~ 5.5 V VIN VIN Supply Voltage 1.2 ~ 5.5 V VOUT VOUT Output Voltage (when VCNTL-VOUT>1.7V) 0.8 ~ VIN – VDROP V IOUT VOUT Output Current 0~2 A R2 ADJ to GND 1K ~ 24K Ω COUT VOUT Output Capacitance IOUT = 2A at 25% nominal VOUT 8~770 IOUT = 1A at 25% nominal VOUT 8~1400 IOUT = 0.5A at 25% nominal VOUT 8~1700 uF ESRCOUT ESR of VOUT Output Capacitor 0 ~ 200 mΩ TA Ambient Temperature -40 ~ 85 ºC TJ Junction Temperature -40 ~ 125 ºC E-CMOS Corp. (www.ecmos.com.tw) Page 4 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Electrical Characteristics Note:Refer to the typical application circuits. These specifications apply over VCNTL=5V, VIN=1.8V, VOUT=1.2V, and TA= -40 ~ 85℃, unless otherwise specified.Typical values are at TJ=25℃. Symbol Parameter Test Conditions Min. Typ. Max. Unit POR Threshold 2.4 2.7 3 V POR Hysteresis 0.15 0.2 VTH_ADJ Adjustable Pin Threshold IOUT=1mA VADJ Reference Voltage IOUT=1mA ΔVOUT Fixed Output Voltage Range ΔVLINE_IN Line Regulation(VIN) V 0.2 0.4 V 0.784 0.8 0.816 V -2 0 +2 % 0.2 0.6 % 0.1 1 % VIN=VOUT+0.5V TO 5V IOUT=1mA ΔVLOAD Load Regulation VIN=VOUT+1V IOUT=1mA TO 2A VDROP Dropout Voltage IOUT= 2A 150 250 mV IQ Quiescent Current VDD=5.5V 0.6 1.2 mA ILIM Current Limit 2.8 3.2 A 0.5 1.8 A Short Circuit Current VOUT<0.2V In-rush Current COUT=10uF,Enable Start-up 0.6 A VOUT Pull-Low Resistance VEN=0V 150 Ω uA Chip Enable IEN EN Input Bias Current VEN=0V 12 ISHDN VDD Shutdown Current EC8320A 10 EC8320B VENL EN Threshold 20 uA 1 Logic-Low Voltage - - 0.2 V Logic-High Voltage 1.2 90 93 % 10 - % 0.2 0.4 V 0.5 1.5 5 mS Power Good PGOOD Rising Threshold PGOOD Hysteresis 3 PGOOD Sink Capability IPGOOD=10mA PGOOD Delay Thermal Protection TSD Thermal Shutdown Temperature - 160 - ℃ ΔTSD Thermal Shutdown Hysteresis - 30 - ℃ - 110 - ℃ Thermal Shutdown Temperature VOUT<0.4V Fold-back E-CMOS Corp. (www.ecmos.com.tw) Page 5 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Typical Operating Characteristics Short Current-Limit vs. Junction Temperature Current-Limit vs. Junction Temperature Dropout Voltage vs. Output Current E-CMOS Corp. (www.ecmos.com.tw) Dropout Voltage vs. Output Current Page 6 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Typical Operating Characteristics(Cont.) Dropout Voltage vs. Output Current Dropout Voltage vs. Output Current Reference Voltage vs. Junction Temperature Dropout Voltage vs. Output Current E-CMOS Corp. (www.ecmos.com.tw) Page 7 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Typical Operating Characteristics(Cont.) VCNTL Power Supply Rejection Ratio(PSRR) E-CMOS Corp. (www.ecmos.com.tw) VIN Power Supply Rejection Ratio(PSRR) Page 8 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Operating Waveforms Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25℃ unless otherwise specified Power On Power Off COUT=10uF, CIN=10uF, RL=0.6Ω /TIME: 5ms/Div COUT=10uF, CIN=10uF, RL=0.6Ω / TIME: 10ms/Div CH1: VCNTL, 5V/Div, DC/CH2: VIN, 1V/Div, DC CH1: VCNTL, 5V/Div, DC/CH2: VIN, 1V/Div, DC CH3: VOUT, 1V/Div, DC/CH4: VPOK, 5V/Div, DC CH3: VOUT, 1V/Div, DC/CH4: VPOK, 5V/Div, DC Load Transient Response Over Current Protection IOUT=10mA to 2A to 10mA (rise / fall time = 1us) COUT=10uF, CIN=10uF COUT=10mF, CIN=10mF, IOUT=1A to 3.4A CH1: VOUT, 50mV/Div, AC/CH4: IOUT, 1A/Div, DC/ TIME: 20us/Div CH1: VOUT, 1V/Div, DC/ CH4: IOUT, 1A/Div, DC/ TIME: 0.2ms/Div E-CMOS Corp. (www.ecmos.com.tw) Page 9 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Operating Waveforms(Cont.) Refer to the typical application circuit. The test condition is VIN=1.5V, VCNTL=5V, VOUT=1.2V, TA= 25℃ unless otherwise specified Shutdown Enable COUT=10mF, CIN=10mF, RL=0.6W/ TIME: 5us/Div COUT=10mF, CIN=10mF, RL=0.6W/ TIME: 0.5ms/Div CH1: VEN, 5V/Div, DC/CH2: VOUT, 1V/Div, DC CH1: VEN, 5V/Div, DC/CH2: VOUT, 1V/Div, DC CH3: VPOK, 5V/Div, DC/CH4: IOUT, 2A/Div, DC CH3: VPOK, 5V/Div, DC/CH4: IOUT, 2A/Div, DC E-CMOS Corp. (www.ecmos.com.tw) Page 10 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Typical Application Circuit Figure3:Fixed Voltage Regulator Application Circuit of EC8320A/B Figure4:Adjustable Voltage Regulator Application Circuit of EC8320A/B E-CMOS Corp. (www.ecmos.com.tw) Page 11 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Function Description Power-On-Reset A Power-On-Reset (POR) circuit monitors both of supply Short Current-Limit Protection voltages on VCNTL and VIN pins to prevent wrong logic controls. The POR function initiates a soft-start process The short current-limit function reduces the current-limit after both of the supply voltages exceed their rising POR level down to 0.8A (typical) when the voltage on ADJ pin voltage thresholds during powering on. The POR falls below 0.2V (typical) during current overload or function also pulls low the POK voltage regardless of the shortcircuit conditions. output status when one of the supply voltages falls below The short current-limit function is disabled for successful its falling POR voltage threshold. start-up during soft-start. Internal Soft-Start Thermal Shutdown An internal soft-start function controls rise rate of the A thermal shutdown circuit limits the junction temperature Output voltage to limit the current surge during start-up. of EC8320. When the junction temperature exceeds +170 ℃, The typical soft-start interval is about 0.6ms. a thermal sensor turns off the output NMOS, allowing the device to cool down. Output Voltage Regulation The regulator regulates the output again through initiation of a new soft-start process after the junction temperature An error amplifier working with a temperature compensated 0.8V reference and an output NMOS cools by 50℃, resulting in a pulsed output during continuous thermal overload conditions. The thermal is designed with high bandwidth and DC gain provides shutdown is designed with a 50 ℃ hysteresis to lower the average junction temperature during continuous thermal overload conditions, extending lifetime of the device. very fast transient response and less load regulation. It For normal operation, the device power dissipation compares the reference with the feedback voltage and should be externally limited so that junction temperatures amplifies the difference to drive the output NMOS which will not exceed +125 ℃. regulates output to the preset voltage. The error amplifier provides load current from VIN to VOUT. Enable Control Current-Limit Protection The EC8320A/B has a dedicated enable pin (EN). The EC8320 monitors the current flowing through the EC8320A:A logic low signal applied to this pin shuts output NMOS and limits the maximum current to prevent down the output. Following a shutdown, a logic high load and EC8320 from damages during current overload signal re-enables the output through initiation of a new conditions. soft-start cycle. When left open, this pin is pulled up by an internal current source (5uA typical) to enable normal operation. It’s not necessary to use an external transistor to Save Cost. E-CMOS Corp. (www.ecmos.com.tw) Page 12 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Function Description(Cont.) EC8320B: A logic low signal applied to this pin shuts down the output. Following a shutdown, a logic high signal re-enables the output through initiation of a new soft-start cycle. When left open, this pin is pulled up by an internal current source (5uA typical) to turn off operation. Power-OK and Delay The EC8320 indicates the status of the output voltage by monitoring the feedback voltage (VADJ) on ADJ pin. As the VADJ rises and reaches the rising Power-OK voltage threshold(VTHPOK), an internal delay function starts to work. At the end of the delay time, the IC turns off the internal NMOS of the POK to indicate the output is ok. As the VADJ falls and reaches the falling Power-OK voltage threshold, the IC turns on the NMOS of the POK ( after a debounce time of 10ms typical ). E-CMOS Corp. (www.ecmos.com.tw) Page 13 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Application Information Input Capacitor Power Sequencing The EC8320 requires proper input capacitors to supply The power sequencing of VIN and VCNTL is not necessary to be concerned. However, do not apply a voltage to VOUT for a long time when the main voltage applied at VIN is not present. The reason is the internal parasitic diode from VOUT to VIN conducts and dissipates power without protections due to the forward-voltage. current surge during stepping load transients to prevent the input voltage rail from dropping. Because the parasitic inductor from the voltage sources or other bulk capacitors to the VIN pin limit the slew rate of the surge currents, more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (such as ceramic chip capacitors) Output Capacitor and low-ESR bulk capacitors (such as solid tantalum, POSCap, The EC8320 requires a proper output capacitor to and Aluminum electrolytic capacitors can all be used as maintain stability and improve transient response. The an input capacitor of VIN. output capacitor selection is dependent upon ESR For most applications, the recommended input capacitance (equivalent series resistance) and capacitance of the of VIN is 10uF at least. However, if the drop of the input output capacitorover the operating temperature. voltage is not cared, the input capacitance can be less u than 10uF. More capacitance reduces the variations of the Ultra-low-ESR capacitors (such as ceramic chip supply voltage on VIN pin. capacitors) and low-ESR bulk capacitors (such as solid tantalum, POSCap, and Aluminum electrolytic capacitors) Setting The Output Voltage can all be used as output capacitors. During load transients, the output capacitors which is The output voltage is programmed by the resistor divider depending on the stepping amplitude and slew rate of load connected to ADJ pin. The preset output voltage is current, are used to reduce the slew rate of the current seen calculated by the following equation : by the EC8320 and help the device to minimize the variations of output voltage for good transient response. For the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. where R1 is the risistor connected from VOUT to ADJ with Decoupling ceramic capacitors must be placed at the load and Kelvin sensing connection and R2 is the risistor connected ground pins as close as possible and the impedance of the from ADJ to GND. A bypass capacitor(C1) may be connected layout must be minimized. with R1 in parallel to improve load transient response and stability. E-CMOS Corp. (www.ecmos.com.tw) Page 14 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Layout Consideration(See Figure A) 1. Please solder the Exposed Pad on the system ground pad on the top-layer of PCBs. The ground pad must have wide size to conduct heat into the ambient air through the system ground plane and PCB as a heat sink. 2. Please place the input capacitors for VIN and VCNTL pins near the pins as close as possible for decoupling Thermal Consideration Refer to the figure B, the SOP-8(EP) is a cost-effective package featuring a small size like a standard SOP-8 and a bottom exposed pad to minimize the thermal resistance of the package, being applicable to high current applications The exposed pad must be soldered to the top-layer ground high-frequency ripples. 3. Ceramic decoupling capacitors for load must be placed near the load as close as possible for decoupling plane. It is recommended to connect the top-layer ground pad to the internal ground plan by using vias. The copper of the ground plane on the top-layer conducts heat into the PCB high-frequency ripples. and ambient air. Please enlarge the area of the top-layer pad 4. To place EC8320 and output capacitors near the load reduces parasitic resistance and inductance for excellent load transient response. and the ground plane to reduce the case-to-ambient resistance (θCA). 5. The negative pins of the input and output capacitors and the GND pin must be connected to the ground plane of the load. 6. Large current paths, shown by bold lines on the figure A, must have wide tracks. 7. Place the R1, R2, and C1 (option) near the EC8320 as clos as to avoid noise coupling. 8. Connect the ground of the R2 to the GND pin by using a dedicated track. 9. Connect the one pin of the R1 to the load for Kelvin sensing. 10. Connect one pin of the C1 (option) to the VOUT pin Figure B. Figure A. E-CMOS Corp. (www.ecmos.com.tw) Page 15 of 16 3G18N-Rev.P001 2A Low Dropout Regulator with Enable EC8320 Package Information SOP-8(Exposed PAD) Package Outline Dimensions E-CMOS Corp. (www.ecmos.com.tw) Page 16 of 16 3G18N-Rev.P001