ON NLV74HCT04ADTR2G Hex inverter Datasheet

MC74HCT04A
Hex Inverter
With LSTTL−Compatible Inputs
High−Performance Silicon−Gate CMOS
The MC74HCT04A may be used as a level converter for interfacing
TTL or NMOS outputs to High−Speed CMOS inputs. The HCT04A is
identical in pinout to the LS04.
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Features
•
•
•
•
•
•
•
•
•
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS−Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 to 5.5 V
Low Input Current: 1 mA
In Compliance With the JEDEC Standard No. 7 A Requirements
Chip Complexity: 48 FETs or 12 Equivalent Gates
NLV Prefix for Automotive and Other Applications Requiring
Unique Site and Control Change Requirements; AEC−Q100
Qualified and PPAP Capable
These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS
Compliant
SOIC−14 NB
D SUFFIX
CASE 751A
TSSOP−14
DT SUFFIX
CASE 948G
PIN ASSIGNMENT
VCC A6
Y6
A5
Y5
A4
Y4
14
13
12
11
10
9
8
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3 GND
14−Lead (Top View)
LOGIC DIAGRAM
MARKING DIAGRAMS
A1
1
2
3
4
5
6
9
8
11
10
13
12
Y1
14
14
A2
A3
Y2
HCT
04A
ALYWG
G
HCT04AG
AWLYWW
1
Y3
1
TSSOP−14
SOIC−14 NB
A4
A5
A6
Y4
A
L, WL
Y, YY
W, WW
G or G
Y5
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
(Note: Microdot may be in either location)
Y6
FUNCTION TABLE
Y=A
Pin 14 = VCC
Pin 7 = GND
Inputs
Outputs
A
Y
L
H
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 3 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. 12
1
Publication Order Number:
MC74HCT04A/D
MC74HCT04A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
–0.5 to +7.0
V
DC Input Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
DC Output Voltage (Referenced to GND)
–0.5 to VCC + 0.5
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
Vout
Iin
DC Input Current, per Pin
±20
mA
Iout
DC Output Current, per Pin
±25
mA
ICC
DC Supply Current, VCC and GND Pins
±50
mA
PD
Power Dissipation in Still Air
500
450
mW
Tstg
Storage Temperature Range
–65 to +150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
SOIC or TSSOP Package
SOIC Package†
TSSOP Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of
these limits are exceeded, device functionality should not be assumed, damage may occur and
reliability may be affected.
†Derating: SOIC Package: –7 mW/_C from 65_ to 125_C
TSSOP Package: −6.1 mW/_C from 65_ to 125_C
RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
–55
+125
_C
0
500
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature Range, All Package Types
tr, tf
Input Rise/Fall Time (Figure 1)
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
DC CHARACTERISTICS (Voltages Referenced to GND)
−55 to 25°C
≤85°C
≤125°C
Unit
Vout = 0.1V
|Iout| ≤ 20mA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
Maximum Low−Level Input Voltage
Vout = VCC − 0.1V
|Iout| ≤ 20mA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
Minimum High−Level Output
Voltage
Vin = VIL
|Iout| ≤ 20mA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
4.5
3.98
3.84
3.70
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
4.5
0.26
0.33
0.40
Parameter
VIH
Minimum High−Level Input Voltage
VIL
VOH
Condition
|Iout| ≤ 4.0mA
Vin = VIL
VOL
Guaranteed Limit
VCC
V
Symbol
Maximum Low−Level Output
Voltage
Vin = VIH
|Iout| ≤ 20mA
|Iout| ≤ 4.0mA
Vin = VIH
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
±0.1
±1.0
±1.0
mA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0mA
5.5
1
10
40
mA
DICC
Additional Quiescent Supply
Current
Vin = 2.4V, Any One Input
Vin = VCC or GND, Other Inputs
Iout = 0mA
5.5
≥ −55°C
25 to 125°C
2.9
2.4
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
1. Total Supply Current = ICC + ΣDICC.
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2
MC74HCT04A
AC CHARACTERISTICS (VCC = 5.0V ±10%, CL = 50pF, Input tr = tf = 6ns)
Guaranteed Limit
Symbol
Parameter
−55 to 25°C
≤85°C
≤125°C
Unit
tPLH,
tPHL
Maximum Propagation Delay, Input A to Output Y
(Figures 1 and 2)
15
17
19
21
22
26
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
(Figures 1 and 2)
15
19
22
ns
Maximum Input Capacitance
10
10
10
pF
Cin
Typical @ 25°C, VCC = 5.0 V
CPD
22
Power Dissipation Capacitance (Per Inverter)*
pF
* Used to determine the no−load dynamic power consumption: P D = CPD VCC2 f + ICC VCC .
tf
tr
3.0V
2.7V
INPUT A
TEST
POINT
1.3V
0.3V
GND
tPLH
OUTPUT
DEVICE
UNDER
TEST
tPHL
90%
OUTPUT Y
CL*
1.3V
10%
tTLH
tTHL
*Includes all probe and jig capacitance
Figure 1. Switching Waveforms
Figure 2. Test Circuit
A
Y
Figure 3. Expanded Logic Diagram
(1/6 of the Device Shown)
ORDERING INFORMATION
Package
Shipping†
MC74HCT04ADG
SOIC−14 NB
(Pb−Free)
55 Units / Rail
MC74HCT04ADR2G
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
NLV74HCT04ADG*
SOIC−14 NB
(Pb−Free)
55 Units / Rail
NLV74HCT04ADR2G*
SOIC−14 NB
(Pb−Free)
2500 / Tape & Reel
TSSOP−14
(Pb−Free)
2500 / Tape & Reel
Device
MC74HCT04ADTR2G
NLV74HCT04ADTR2G*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*NLV Prefix for Automotive and Other Applications Requiring Unique Site and Control Change Requirements; AEC−Q100 Qualified and PPAP
Capable.
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3
MC74HCT04A
PACKAGE DIMENSIONS
TSSOP−14
CASE 948G
ISSUE B
14X K REF
0.10 (0.004)
0.15 (0.006) T U
M
T U
V
S
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL NOT
EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION SHALL
NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
S
S
N
2X
14
L/2
0.25 (0.010)
8
M
B
−U−
L
PIN 1
IDENT.
F
7
1
0.15 (0.006) T U
N
S
DETAIL E
K
A
−V−
ÉÉÉ
ÇÇÇ
ÇÇÇ
ÉÉÉ
ÇÇÇ
K1
J J1
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
SECTION N−N
−W−
C
0.10 (0.004)
−T− SEATING
PLANE
D
H
G
DETAIL E
MILLIMETERS
MIN
MAX
4.90
5.10
4.30
4.50
−−−
1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.50
0.60
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
SOLDERING FOOTPRINT*
7.06
1
0.65
PITCH
14X
0.36
14X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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4
INCHES
MIN MAX
0.193 0.200
0.169 0.177
−−− 0.047
0.002 0.006
0.020 0.030
0.026 BSC
0.020 0.024
0.004 0.008
0.004 0.006
0.007 0.012
0.007 0.010
0.252 BSC
0_
8_
MC74HCT04A
PACKAGE DIMENSIONS
D
SOIC−14 NB
CASE 751A−03
ISSUE K
A
B
14
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF AT
MAXIMUM MATERIAL CONDITION.
4. DIMENSIONS D AND E DO NOT INCLUDE
MOLD PROTRUSIONS.
5. MAXIMUM MOLD PROTRUSION 0.15 PER
SIDE.
8
A3
E
H
L
1
0.25
M
DETAIL A
7
B
13X
M
b
0.25
M
C A
S
B
S
e
DETAIL A
h
A
X 45 _
M
A1
C
SEATING
PLANE
DIM
A
A1
A3
b
D
E
e
H
h
L
M
MILLIMETERS
MIN
MAX
1.35
1.75
0.10
0.25
0.19
0.25
0.35
0.49
8.55
8.75
3.80
4.00
1.27 BSC
5.80
6.20
0.25
0.50
0.40
1.25
0_
7_
INCHES
MIN
MAX
0.054 0.068
0.004 0.010
0.008 0.010
0.014 0.019
0.337 0.344
0.150 0.157
0.050 BSC
0.228 0.244
0.010 0.019
0.016 0.049
0_
7_
SOLDERING FOOTPRINT*
6.50
14X
1.18
1
1.27
PITCH
14X
0.58
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
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MC74HCT04A/D
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