TI1 HD3SS460IRHRR 4 x 6 channels usb type-c alternate mode mux Datasheet

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HD3SS460
SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
HD3SS460 4 x 6 Channels USB Type-C™ Alternate Mode MUX
1 Features
•
1
•
•
•
•
•
•
•
•
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3 Description
TM
Provides MUX Solution for USB Type-C
Ecosystem Including Alternate Mode (AM)
Provides Wide Channel Selection Choices
Including USBSS and 2 Ch AM, 4 Ch AM
Compatible with 5 Gbps USB3.1 Gen 1 and AM
Including 5.4 Gbps DisplayPort 1.2a
Compatible for Source/Host and Sink/Device
Applications
Provides Cross-point MUX for Low Speed SBU
Pins
Bidirectional "Mux/De-Mux" Differential Switch
Supports Common Mode Voltage 0-2V
Low Power with 1-μA Shutdown and 0.6 mA
Active
Single Supply Voltage VCC of 3.3V ±10%
Industrial Temperature Range of –40 to 85°C
2 Applications
•
•
•
•
Flippable USB Type-CTM Ecosystem
Tablets, Laptops, Monitors, Phones
USB Host and Devices
Docking Stations
The HD3SS460 is a high-speed bi-directional passive
switch in mux or demux configurations. Based on
control pin POL the device provides switching to
accommodate connector flipping. The device also
provides muxing between 2Ch Data / 2Ch Video and
all 4Ch Video based on control pin AMSEL.
The device also provides cross points MUX for low
speed pins as needed in flippable connector
implementation.
The HD3SS460 is a generic analog differential
passive switch that can work for any high speed
interface applications as long as it is biased at a
common mode voltage range of 0-2V and has
differential signaling with differential amplitude up to
1800mVpp. It employs an adaptive tracking that
ensures the channel remains unchanged for entire
common mode voltage range.
Excellent dynamic characteristics of the device allow
high speed switching with minimum attenuation to the
signal eye diagram with very little added jitter. It
consumes <2 mW of power when operational and
<5µW in shutdown mode, exercisable by EN pin.
Device Information(1)
PART NUMBER
HD3SS460
PACKAGE
QFN (28)
HD3SS460I
BODY SIZE (NOM)
3.50 mm × 5.50 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
sp
sp
Simplified Schematic
sp
sp
Application
SSRX SSTX
USB Host
C_SS[RX/TX][1/2]
USB Device /
Hub
SS RX/TX
CTX1
CTX2
SS RX/TX
LnD
CRX1
High Speed
MUX
Switches
LnC
LnB
LnA
CRX2
AMSEL
EN
POL
VCC
HD3SS460
4-6
X-point
MUX
4/2 Ln DP
AUX
DP Source
USB
TypeC
SBU1/2
HD3SS460
4-6
X-point
MUX
AUX
4/2 Ln DP
DP Sink / MST
Hub
Copyright © 2016, Texas Instruments Incorporated
GND
CSBU1
CSBU2
Low Speed
MUX
Switches
SBU1
SBU2
Copyright © 2016, Texas Instruments Incorporated
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
HD3SS460
SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
www.ti.com
Table of Contents
1
2
3
4
5
6
7
8
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
5
7.1
7.2
7.3
7.4
7.5
7.6
7.7
5
5
5
5
6
6
7
Absolute Maximum Ratings ......................................
ESD Ratings ............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
High Speed Port Performance Parameters ..............
High Speed Signal Path Switching Characteristics ..
Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................. 10
8.4 Device Functional Modes........................................ 10
9
Application and Implementation ........................ 13
9.1 Application Information............................................ 13
9.2 USB SS and DP as Alternate Mode ...................... 13
10 Power Supply Recommendations ..................... 22
11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
11.2 Layout Example .................................................... 24
12 Device and Documentation Support ................. 26
12.1
12.2
12.3
12.4
12.5
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
26
26
26
26
26
13 Mechanical, Packaging, and Orderable
Information ........................................................... 26
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision A (March 2015) to Revision B
Page
•
Changed text and Figure 3, Figure 4 in the USB SS and DP as Alternate Mode section for clarity. ................................. 13
•
Added Figure 5 ..................................................................................................................................................................... 14
•
Added Figure 6 ..................................................................................................................................................................... 15
•
Deleted Table Pin Assignments for DP Source Pins and DP Sink Pins in the Detailed Design Procedure section............ 16
•
Added Table 2, Table 3, Table 4, and Table 5 .................................................................................................................... 16
•
Added Figure 8 through Figure 13 ...................................................................................................................................... 16
•
Changed Figure 16 .............................................................................................................................................................. 20
•
Changed image for Figure 19............................................................................................................................................... 22
Changes from Original (January 2015) to Revision A
•
2
Page
Added full data sheet specification complement ................................................................................................................... 5
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5 Device Comparison Table (1)
(1)
OPERATING
TEMPERATURE (°C)
PART NUMBER
PINS
TOP-SIDE MARKING
0 to 70
HD3SS460
28
3SS460
–40 to 85
HD3SS460I
28
3SS460I
For all available packages, see the orderable addendum at the end of the data sheet. Package drawings, thermal data, and
symbolization are available at www.ti.com/packaging
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SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
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6 Pin Configuration and Functions
SSTXn
26
25 24
LnDp
2
23
LnDn
POL
3
22
VCC
CTX1p
4
21
LnCp
CTX1n
5
20
LnCn
CTX2p
6
19
LnBp
CTX2n
7
18
LnBn
AMSEL
8
17
EN
CRX2p
9
16
LnAp
CRX2n
10 11
12
13
14 15
LnAn
SBU2
SSTXp
27
SBU1
SSRXn
CRX1n
28
CSBU2
1
CSBU1
CRX1p
SSRXp
RHR Package With Thermal Pad
(28-Pin WQFN)
Top View
Thermal Pad
GND
Pin Functions
PIN
NAME
NO.
TYPE (1)
DESCRIPTION
VCC
22
P
Power
GND
PAD
G
Ground
POL
3
AMSEL
8
3-Level Input Provides MUX configurations (Table 1)
EN
17
3-Level Input Enable signal; also provides MUX control (Table 1)
CRX1p, n
1, 2
I/O
High Speed Signal Port CRX1 positive, negative
CTX1p, n
4, 5
I/O
High Speed Signal Port CTX1 positive, negative
CTX2p, n
6, 7
I/O
High Speed Signal Port CTX2 positive, negative
CRX2p, n
9, 10
I/O
High Speed Signal Port CRX2 positive, negative
LnAn, p
15, 16
I/O
High Speed Signal Port LnA positive, negative
LnBn, p
18, 19
I/O
High Speed Signal Port LnB positive, negative
LnCn, p
20, 21
I/O
High Speed Signal Port LnC positive, negative
LnDn, p
23, 24
I/O
High Speed Signal Port LnD positive, negative
SSTXn, p
25, 26
I/O
High Speed Signal Port SSTX positive, negative
SSRXn, p
27, 28
I/O
High Speed Signal Port SSRX positive, negative
CSBU1, 2
11, 12
I/O
Low Speed Signal Port CSBU 1, 2
SBU1, 2
13, 14
I/O
Low Speed Signal Port SBU 1, 2
(1)
4
Input
Provides MUX control (Table 1)
High speed data ports (CRX[1/2][p/n], Ln[A-D][p,n], and SS[T/R]X[p/n]) incorporate 20kΩ pull down resistors that are switched in when a
port is not selected and switched out when the port is selected.
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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)
(1)
MIN
MAX
UNIT
Supply Voltage, VCC
–0.5
4
V
Differential High Speed I/O Voltages, C[R/T]X[1/2][p/n], Ln[A-D][p/n], SS[R/T]X[p/n]
–0.5
2.5
V
Low Speed I/O Voltages, CSBU[1/2], SBU[1/2]
–0.5
4
V
Control signal voltages, POL, AMSEL, EN
–0.5
4
V
Storage temperature, Tstg
–65
150
°C
(1)
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
7.2 ESD Ratings
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001
V(ESD)
(1)
(2)
Electrostatic discharge
VALUE
UNIT
±4000
V
±1000
V
(1)
Charged-device model (CDM), per JEDEC specification JESD22C101 (2)
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 250-V CDM is possible with the necessary precautions.
7.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
VCC
MIN
NOM
MAX
3.0
3.3
3.6
HD3SS460
0
25
70
HD3SS460I
–40
25
85
Supply voltage
TA
Operating free air temperature
Vcm
High speed port common mode voltage
0
2
Vin
Low Speed signal voltage
0
VCC
Vdiff
High speed port differential voltage
0
1.8
UNIT
V
°C
V
Vpp
7.4 Thermal Information
HD3SS460
THERMAL METRIC (1)
QFN (RGR)
UNIT
28 PINS
RθJA
Junction-to-ambient thermal resistance
44.0
°C/W
RθJC(top)
Junction-to-case (top) thermal resistance
34.8
°C/W
RθJB
Junction-to-board thermal resistance
14.7
°C/W
ψJT
Junction-to-top characterization parameter
0.7
°C/W
ψJB
Junction-to-board characterization parameter
24.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
6.9
°C/W
(1)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
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7.5 Electrical Characteristics
typical values for all parameters are at VDD = 3.3 V and TA = 25°C (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VIL
Input low voltage, control pins POL,
AMSEL, EN
VIH
Input high voltage, control pins
POL, AMSEL, EN
VIM
Input mid-level voltage, control pins
AMSEL, EN
MIN
TYP
MAX
–0.1
0.4
VCC –0.4
VCC +0.1
VCC/2 –0.3
VCC/2 VCC/2 +0.3
Leakage current on active
ILK-DIFF-ACTIVE differential IO pins, VCC=3.6V, pin
at 0 or 2.4V.
1
Leakage current on inactive
differential IO pins, VCC=3.6V, pin
at 2.4V.
150
ILK-DIFFINACTIVE
IIH
Input high current, control pins
POL, AMSEL, EN and signal pins
CSBU1/2, SBU1/2
1
IIL
Input low current, control pins POL,
AMSEL, EN and signal pins
CSBU1/2, SBU1/2
1
IIM
Input mid-level current, control pins
AMSEL, EN
1
IOFF
Device shutdown current
IDD
Device active current, EN=H or M
RON(HS)
Switch ON resistance for high
speed differential signals
1
5
0.6
0.9
VCC = 3.3 V, VCM = 0-2 V,
IO = - 8 mA
8
14
RON(LS)
Switch ON resistance for low speed VCC = 3.3 V, VCM = 0-2 V,
signals
IO = - 8 mA
12
RFLAT(ON,HS)
High speed differential signals’ ON
resistance flatness for a channel
CON(HS)
High speed differential signals’
input capacitance
(RON(MAX) – RON(MIN)) over VCM
range VCC = 3.3 V, VCM = 0-2 V,
IO = - 8 mA
UNIT
V
µA
mA
Ω
1.5
1
pF
7.6 High Speed Port Performance Parameters
under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER
MIN
100 Mhz SS Paths
RL
IL
OI
Differential return loss
Differential insertion loss
Differential off isolation
Differential cross talk, Between
CRX1/2 and CTX1/2
Xtalk
Differential cross talk, Between
CRX1 and CRX2 or CTX1 and
CTX2
6
2.5 Ghz SS Paths
TYP
UNIT
–23
–9
100 MHz AM Paths
–23
2. 7GHz AM Paths
–13
100 Mhz SS Paths
–0.7
2.5 Ghz SS Paths
–1.6
100 MHz AM Paths
–0.7
2.7 GHz AM Paths
–1.4
100 Mhz
–50
2.5 Ghz
–26
2.7 GHz
–25
100 Mhz
–80
2.5 Ghz
–30
2.7 Ghz
–28
100 Mhz
–50
2.5 Ghz
–26
2.7 Ghz
–25
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dB
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High Speed Port Performance Parameters (continued)
under recommended operating conditions; RLOAD, RSC = 50 Ω (unless otherwise noted)
PARAMETER
MIN
TYP
BWSS
Differential –3 dB BW SS Paths
4.2
BWAM
Differential –3 dB BW AM Paths
5.4
BWSBU
Low-speed switch –3 dB BW
500
MAX
UNIT
GHz
MHz
7.7 High Speed Signal Path Switching Characteristics
PARAMETER
TEST CONDITION
tPD
Switch propagation delay
tSK(O)
Inter-Pair output skew (CH-CH)
tSK(b-b)
Intra-Pair output skew (bit-bit)
tON
Control signals POL, AMSEL and
EN (H/M toggle) to switch ON time
tOFF
MIN
TYP
MAX
UNIT
100
RSC and RLOAD = 50 Ω, Figure 2
50
ps
5
Control signals POL, AMSEL and
EN (H/M toggle) to switch OFF time
3
RSC and RLOAD = 50 Ω, Figure 1
µs
1
Timing Diagrams
50%
POL, AMSEL , EN (H/M)
90%
10%
High/Low Speed Signals
Toff
Ton
Figure 1. Switch ON/OFF Time
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Vcc
50 Ω
C[R/T]X[1/2]p
HD3SS460
Ln[D-A]/SS[T/R]Xp
50 Ω
50 Ω
Ln[D-A]/SS[T/R]Xn
C[R/T]X[1/2]n
50 Ω
SEL
C[R/T]X[1/2]p
50%
50%
C[R/T]X[1/2]n
Ln[D-A]/SS[T/R]Xp
50%
50%
Ln[D-A]/SS[T/R]Xn
tP1
t1
tP2
t2
t3
t4
Ln[x]/SS[x]Xp
50%
Ln[x]/SS[x]Xn
Ln[y]/SS[y]Xp
tSK(O)
Ln[y]/SS[y]Xn
tPD = Max(tp1, tp2)
tSK(O) = Difference between t PD for any two
pairs of outputs
tSK(b-b) = 0.5 X |(t4 – t3) + (t1 – t2)|
Figure 2. Propagation Delay and Skew
8
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8 Detailed Description
8.1 Overview
The HD3SS460 is a high-speed bi-directional passive 4-6 cross-point switch in mux or demux configurations.
Based on control pin POL the device provides switching to accommodate USB Type-C plug flipping. The device
provides multiple signal switching options that allow system implementation flexibility.
The HD3SS460 is a generic analog, differential passive switch that can work for any high speed interface
applications as long as it is biased at a common mode voltage range of 0-2 V and has differential signaling with
differential amplitude up to 1800 mVpp. It employs an adaptive tracking that ensures the channel remains
unchanged for entire common mode voltage range
Excellent dynamic characteristics of the device allow high speed switching with minimum attenuation to the
signal eye diagram with very little added jitter.
8.2 Functional Block Diagram
SSRX SSTX
LnD
CRX1
CTX1
CTX2
LnC
High Speed
MUX
Switches
LnB
LnA
CRX2
AMSEL
EN
POL
VCC
GND
CSBU1
CSBU2
Low Speed
MUX
Switches
SBU1
SBU2
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8.3 Feature Description
8.3.1 High Speed Differential Signal Switching
Based on control pin AMSEL the device provides muxing options of:
1. 1 port (RX and TX) USB3.1 SS data / 2Ch video (or any other Alternate Mode data)
2. All 4Ch video (or any other Alternate Mode data)
3. 1 port (RX and TX) USB3.1 SS data
4. 1 port (RX and TX) USB3.1 SS data / 2Ch video (or any other Alternate Mode data) with option of choosing
video from two different source/sink
5. 1 port (RX and TX) USB3.1 SS data / 2Ch video (or any other Alternate Mode data) with option of choosing
video 2 Ln Video or 1 Ln Video from two different source/sink
8.3.2 Low Speed SBU Signal Switching
The device also provides cross point muxing for low speed SBU signals as needed in USB Type-C flippable
connector implementation. The device provides the option to choose the USB only implementation where SBU
ports are in tri-state.
8.3.3 Output Enable and Power Savings
The HD3SS460 has two power modes, active/normal operating mode and standby/shutdown mode. During
standby mode, the device consumes very little current to save the maximum power. To enter standby mode, the
EN control pin is pulled low and must remain low. For active/normal operation, the EN control pin should be
pulled high to VDD through a resistor or dynamically controlled to switch between H or M.
HD3SS460 consumes <2 mW of power when operational and <5 µW in shutdown mode, exercisable by the EN
pin.
8.4 Device Functional Modes
8.4.1 Device High Speed Switch Control Modes
Table 1. MUX Control for High Speed and Low Speed SBU Channels
POL
AMSEL
EN
CONFIGURATIONS
HIGH SPEED SIGNAL
FLOW (1)
SSRX
L
L
H
2CH USBSS + 2CH AM
(Normal)
H
(1)
10
L
H
2CH USBSS + 2CH AM
(Flipped)
SSTX
CRX1
LnD
CTX1
LnC
CTX2
LnB
CRX2
LnA
SSRX
SBU SIGNAL FLOW
CSBU1
SBU1
CSBU2
SBU2
CSBU1
SBU1
CSBU2
SBU2
SSTX
CRX1
LnD
CTX1
LnC
CTX2
LnB
CRX2
LnA
All positive signals connect to positive and negative to negative
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Device Functional Modes (continued)
Table 1. MUX Control for High Speed and Low Speed SBU Channels (continued)
POL
AMSEL
EN
CONFIGURATIONS
HIGH SPEED SIGNAL
FLOW (1)
SSRX
L
H
H
4CH AM (Normal)
LnD
CTX1
LnC
CTX2
LnB
CRX2
LnA
CRX1
H
H
H
4CH AM (Flipped)
CTX1
M
H
2CH USBSS (Normal)
H
M
H
2CH USBSS (Flipped)
CRX2
LnA
L
M
M
SBU1
CSBU2
SBU2
CSBU1
SBU1
CSBU2
SBU2
SSTX
CRX1
LnD
CTX1
LnC
CTX2
CRX2
LnB
All Low Speed SBU
Ports HighZ
LnA
SSTX
CRX1
LnD
CTX1
LnC
CTX2
LnB
CRX2
LnA
SSRX
2CH USBSS + 2CH AM
(Normal)
LnD
LnC
LnB
SSRX
CSBU1
SSTX
CTX2
SSRX
L
SSTX
CRX1
SSRX
SBU SIGNAL FLOW
All Low Speed SBU
Ports HighZ
SSTX
CRX1
LnD
CTX1
LnC
CTX2
CRX2
LnB
CSBU1
SBU1
CSBU2
SBU2
LnA
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Device Functional Modes (continued)
Table 1. MUX Control for High Speed and Low Speed SBU Channels (continued)
POL
AMSEL
EN
CONFIGURATIONS
HIGH SPEED SIGNAL
FLOW (1)
SSRX
H
M
M
2CH USBSS + 2CH AM
(Flipped)
L
L
M
2CH USBSS + 2CH AM from
alternate GPU (Normal)
LnD
CTX1
LnC
CTX2
LnB
CRX2
LnA
H
M
SBU1
CSBU2
SBU2
LnD
CTX1
LnC
CSBU1
SBU1
CSBU2
CTX2
LnB
SBU2
CRX2
LnA
CSBU1
SBU1
CSBU2
SBU2
SSTX
CRX1
LnD
CTX1
LnC
CTX2
LnB
CRX2
LnA
L
H
M
Reserved
Reserved
H
H
M
Reserved
Reserved
Reserved
All High Speed Ports HighZ
All Low Speed SBU
Ports HighZ
X
12
L
CSBU1
SSTX
CRX1
SSRX
2CH USBSS + 2CH AM from
alternate GPU (Flipped)
SSTX
CRX1
SSRX
SBU SIGNAL FLOW
X
L
All High Speed Ports HighZ
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
HD3SS460 can be utilized for a wide range of muxing needs. This is general purpose passive cross-point switch.
The channels have independent adaptive common mode tracking allowing flexibility. As long as recommended
electrical use conditions are met the device can be used number of ways as described in Table 1.
NOTE
HD3SS460 does not provide common mode biasing for the channel. Therefore it is
required that the device is biased from either side for all active channels.
9.2 USB SS and DP as Alternate Mode
HD3SS460 can be used USB Type-C ecosystem with DP as alternate mode in two distinct application
configurations – one is for DP Source/USB Host, the other one for the DP Sink/USB Device/Dock. Figure 3 and
Figure 4 illustrate typical application block diagrams for these two cases. Detail schematics are illustrated in
Detailed Design Procedure section. Other applications and or use cases possible where these examples can be
used as general guidelines.
Figure 3 and Figure 4 depict the AC coupling capacitor placement examples. TI recommends placing the
capacitors as shown in the illustrations for the backward compatibility and interoperability purposes as some of
the existing USB systems may present Vcm, exceeding the typical range of 0–2 V on SS differential pairs.
USB3 Host
No AC Coupling Caps
SSTX
SSRX
ML1+
ML1>
ML2+
ML2>
HD3SS460
ML3+
ML3>
TX1+
TX1>
0.1 µF
TX2+
TX2>
0.1 µF
Type C
Connector
RX1+
RX1>
No AC
Coupling Caps
DP Source
ML0+
ML0>
RX2+
RX2>
Copyright © 2016, Texas Instruments Incorporated
Figure 3. Block Diagram for a Type C Interface Using DP as Alternate Mode – Source/Host
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USB SS and DP as Alternate Mode (continued)
USB3 Upstream Port
No AC Coupling Caps
SSRX
Type C
Connector
0.1 µF
0.1 µF
SSTX
RX1+
RX1>
ML0+
ML0>
TX1+
TX1>
ML1+
ML1>
HD3SS460
TX2+
TX2>
DP Sink
ML2+
ML2>
RX2+
RX2>
ML3+
ML3>
Copyright © 2016, Texas Instruments Incorporated
Figure 4. Diagram for a Type C Interface Using DP as Alternate Mode – Sink/Device/Dock
Figure 5 and Figure 6 depict the AC coupling capacitor recommendations in case the upstream or downstream
port connected internally to the HD3SS460 presents Vcm greater than 2 V.
Vcm > 2.0 V
500 nF
100 lQ
500 nF
100 lQ
100 lQ
SSTX
DP Source
RX1+
RX1>
0.1 µF
ML1+
ML1>
HD3SS460
ML2+
ML2>
ML3+
ML3>
TX1+
TX1>
0.1 µF
TX2+
TX2>
0.1 µF
RX2+
RX2>
0.1 µF
Type C
Connector
ML0+
ML0>
100 lQ
SSRX
Copyright © 2016, Texas Instruments Incorporated
Figure 5. HD3SS460 USB Host (DP Source with SS USB Vcm)
14
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USB SS and DP as Alternate Mode (continued)
Vcm > 2.0 V
500 nF
100 lQ
100 lQ
RX1+
RX1>
Type C
Connector
0.1 µF
100 lQ
SSTX
SSRX
100 lQ
ML0+
ML0>
TX1+
TX1>
TX2+
TX2>
0.1 µF
500 nF
ML1+
ML1>
HD3SS460
DP Sink
ML2+
ML2>
RX2+
RX2>
ML3+
ML3>
Copyright © 2016, Texas Instruments Incorporated
Figure 6. HD3SS460 USB Upstream (DP Sink Implementation Example)
9.2.1 Design Requirements
DESIGN PARAMETERS
EXAMPLE VALUES
VCC
3.3 V
Decoupling capacitors
0.1 µF
AC Capacitors
75-200nF (100nF shown) USBSS TX p and n lines require AC capacotprs. Alternate
mode signals may or may not require AC capacitors
Control pins
Controls pins can be dynamically controlled or pin-strapped. The POL signal is
controlled by CC logic in the Type-C ecosystem.
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9.2.2 Detailed Design Procedure
The reference schematics shown in this document are based upon the pin assignment defined in the Alternate
mode over Type C specification as shown in Figure 7 below.
Figure 7. Pin Assignment – Alternate Mode Over Type C
Table 2 represents the example pin mapping to HD3SS460 for the DP Source pin assignments C, D, E and F,
DP Sink pin assignments C and D.
Table 2. SOURCE Pin Assignment Option C and E (AMSEL = H, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO DP SOURCE (GPU)
460 PIN MAPPING TO
TYPE C CONNECTOR
POL = L
POL = H
A11/10
CRX2
LnA(ML0)
LnD(ML3)
A2/3
CTX1
LnC(ML2)
LnB(ML1)
B11/10
CRX1
LnD(ML3)
LnA(ML0)
B2/3
CTX2
LnB(ML1)
LnC(ML2)
A8
CSBU1
SBU1(AUXP)
SBU2(AUXN)
B8
CSBU2
SBU2(AUXN)
SBU1(AUXP)
HD3SS460
A11 / A10
Video Source (GPU)
CRX2
LnA/LnD
ML0/ML3
A2 / A3
CTX1
LnC/LnB
ML2/ML1
B11 / B10
CRX1
LnD/LnA
ML3/ML0
B2 / B3
CTX2
LnB/LnC
ML1/ML2
A8 / B8
CSBU1/2
0.1 PF
0.1 PF
AUXN/N
AUXP/P
SSRX
SSTX
Type-C
Connector
SBU1/2
SBU2/1
Red text indicates POL = H
SSRX
SSTX
USB SS lines are internally
unconnected under this mode
xHCI Host
Copyright © 2016, Texas Instruments Incorporated
Figure 8. SOURCE Pin Assignment Option C and E (AMSEL = H, EN = H)
16
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Table 3. SOURCE Pin Assignment Option D and F (AMSEL = L, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO DP SOURCE (GPU)
460 PIN MAPPING TO
TYPE C CONNECTOR
POL = L
POL = H
A11/10
CRX2
LnA(ML0)
SSRX
A2/3
CTX1
SSTX
LnB(ML1)
B11/10
CRX1
SSRX
LnA(ML0)
B2/3
CTX2
LnB(ML1)
SSTX
A8
CSBU1
SBU1(AUXP)
SBU2(AUXN)
B8
CSBU2
SBU2(AUXN)
SBU1(AUXP)
Space
HD3SS460
A11 / A10
HD3SS460
Video Source (GPU)
CRX2
LnA
ML1
A11 / A10
A2 / A3
CTX1
LnC
ML3
B11 / B10
CRX1
LnD
B2 / B3
CTX2
LnB
A8 / B8
CSBU1/2
SBU1
SBU2
Video Source (GPU)
CRX2
LnA
ML0
A2 / A3
CTX1
LnC
ML2
ML2
B11 / B10
CRX1
LnD
ML3
ML0
B2 / B3
CTX2
LnB
ML1
AUXN
AUXP
A8 / B8
CSBU1/2
SBU2
SBU1
0.1 PF
0.1 PF
0.1 PF
0.1 PF
SSRX
Type-C
Connector
xHCI Host
LnC and LnD lines are internally
unconnected under this mode
SSTX
SSRX
SSTX
SSRX
LnC and LnD lines are internally
unconnected under this mode
SSTX
SSRX
SSTX
Type-C
Connector
AUXN
AUXP
xHCI Host
Copyright © 2016, Texas Instruments Incorporated
Copyright © 2016, Texas Instruments Incorporated
Figure 9. SOURCE Pin Assignment Option D and F
(AMSEL = L, EN = H, POL = L)
Figure 10. SOURCE Pin Assignment Option D and
F (AMSEL = L, EN = H, POL = H)
Table 4. SINK Pin Assignment Option C (AMSEL = H, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO DP SOURCE (GPU)
460 PIN MAPPING TO
TYPE C CONNECTOR
POL = L
POL = H
A11/10
CRX2
LnA(ML1)
LnD(ML2)
A2/3
CTX1
LnC(ML3)
LnB(ML0)
B11/10
CRX1
LnD(ML2)
LnA(ML1)
B2/3
CTX2
LnB(ML0)
LnC(ML3)
A8
CSBU1
SBU1(AUXN)
SBU2(AUXP)
B8
CSBU2
SBU2(AUXP)
SBU1(AUXN)
HD3SS460
A11 / A10
Video Sink
CRX2
LnA/LnD
ML1/ML2
A2 / A3
CTX1
LnC/LnB
ML3/ML0
B11 / B10
CRX1
LnD/LnA
ML2/ML1
B2 / B3
CTX2
LnB/LnC
ML0/ML3
A8 / B8
CSBU1/2
0.1 PF
0.1 PF
AUXN/P
AUXP/N
SSRX
SSTX
Type-C
Connector
SBU1/2
SBU2/1
Red text indicates POL = H
SSRX
SSTX
USB SS lines are internally
unconnected under this mode
SS HUB/Device
Copyright © 2016, Texas Instruments Incorporated
Figure 11. SINK Pin Assignment Option C (AMSEL = H, EN = H)
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Table 5. SINK Pin Assignment Option D (AMSEL = L, EN = H)
RECEPTACLE PIN
NUMBER
460 PIN MAPPING TO
TYPE C CONNECTOR
460 PIN MAPPING TO DP SOURCE (GPU)
POL = L
POL = H
A11/10
CRX2
LnA(ML1)
SSRX
A2/3
CTX1
SSTX
LnB(ML0)
B11/10
CRX1
SSRX
LnA(ML1)
B2/3
CTX2
LnB(ML0)
SSTX
A8
CSBU1
SBU1(AUXN)
SBU2(AUXP)
B8
CSBU2
SBU2(AUXP)
SBU1(AUXN)
Space
HD3SS460
A11 / A10
HD3SS460
Video Source (GPU)
CRX2
LnA
ML1
A11 / A10
A2 / A3
CTX1
LnC
ML3
B11 / B10
CRX1
LnD
B2 / B3
CTX2
LnB
A8 / B8
CSBU1/2
SBU1
SBU2
LnA
ML0
A2 / A3
CTX1
LnC
ML2
ML2
B11 / B10
CRX1
LnD
ML3
ML0
B2 / B3
CTX2
LnB
ML1
AUXN
AUXP
A8 / B8
CSBU1/2
SBU2
SBU1
0.1 PF
0.1 PF
0.1 PF
0.1 PF
xHCI Host
LnC and LnD lines are internally
unconnected under this mode
xHCI Host
Copyright © 2016, Texas Instruments Incorporated
Figure 12. SINK Pin Assignment Option D
(AMSEL = L, EN = H, POL=L)
18
SSTX
SSRX
SSTX
SSRX
LnC and LnD lines are internally
unconnected under this mode
SSRX
Type-C
Connector
AUXN
AUXP
SSTX
SSRX
SSTX
Type-C
Connector
Video Source (GPU)
CRX2
Copyright © 2016, Texas Instruments Incorporated
Figure 13. SINK Pin Assignment Option D
(AMSEL = L, EN = H, POL=H)
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Schematic diagrams Figure 14, Figure 15, and Figure 16 show the DP Source/USB Host implementation; and,
Figure 17, Figure 18, and Figure 19 show the DP Sink/USB Device/HUSB Hub/Dock implementation,
respectively.
VBUS
TypeC Connector and Source Pin Mapping
J2
GND
A1
B12
GND
VBUS1
VBUS2
VBUS3
VBUS4
A4
A9
B4
B9
CC1
CC2
A5
B5
CC1
CC2
SBU1
SBU2
A8
B8
CSBU1
CSBU2
DN1
DP1
A7
A6
USB2_N0
USB2_P0
DP2
DN2
B6
B7
C8
10uF
ML2P
ML1P
SSTXP1
SSTXP2
A2
B11
SSRXP1
SSRXP2
ML3P
ML0P
ML2N
ML1N
SSTXN1
SSTXN2
A3
B10
SSRXN1
SSRXN1
ML3N
ML0N
VBUS
A4
B9
VBUS
CC1
A5
B8
SBU2
DP1
A6
B7
DN2
SSTXP1
SSTXN1
A2
A3
CTX1P
CTX1N
DN1
A7
B6
DP2
SSRXP2
SSRXN2
A11
A10
CRX2P
CRX2N
SBU1
A8
B5
CC2
SSTXP2
SSTXN2
B2
B3
CTX2P
CTX2N
VBUS
A9
B4
VBUS
B11
B10
CRX1P
CRX1N
AUXP
AUXN
AUXN
AUXP
ML0N
ML3N
SSRXN2
SSRXN1
A10
B3
SSTXN2
SSTXN1
ML1N
ML2N
ML0P
ML3P
SSRXP2
SSRXP1
A11
B2
SSTXP2
SSTXP1
ML1P
ML2P
GND
A12
B1
GND
g6
g5
g4
g3
g2
g1
SSRXP1
Shield6 SSRXN1
Shield5
Shield4 GND0
Shield3 GND1
Shield2 GND2
Shield1 GND3
Note: It is
recommended to
add isolation
circuit if
voltage is to be
present on any
of the I/Os
while the
HD3SS460
device is off.
A1
A12
B1
B12
USB_TypeC_Receptacle_
CSBU1
CSBU2
R156
2MΩ
R158
2MΩ
pull-down
resistor
between 1MΩ-2MΩ
is recommended
on SBU1 and
SBU2.
Copyright © 2016, Texas Instruments Incorporated
Figure 14. Schematic Implementations for DP Source/ USB Host (1 of 3)
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ESD Components
Place in pass through manner with no stub
U8
1
2
3
4
5
CTX1N
CTX1P
CRX1N
CRX1P
NC10
D1
NC9
D1GND GND
D2+ NC7
NC6
D2TPD4E05U06
10
9
8
7
6
U9
1
2
3
4
5
CTX2P
CTX2N
CRX2P
CRX2N
10
NC10
D1
NC9 9
D18
GND GND 7
D2+ NC7 6
NC6
D2TPD4E05U06
U12
1
2
3
4
5
6
7
NC1
NC2
NC3
NC4
GND
NC5
NC6
D1+
D1D2+
D2GND
D3+
D3-
CC1
CC2
USB2_P0
USB2_N0
14
13
12
11
10
9
8
CSBU1
CSBU2
TPD6E05U06
Copyright © 2016, Texas Instruments Incorporated
Figure 15. Schematic Implementations for DP Source/ USB Host (2 of 3)
HD3SS460
3P3V
3P3V
C3
0.1uF
R188
10K
R187
10K
R6
10K
VCC
U2
Connect to
Type C SSTX/RX
pins
AC Coupling caps to
accomodate higher Vcm
on some USB devices
CRX1N
CRX1P
C490.1uF
CRX1P
CRX1N
C480.1uF
CTX1P
CTX1N
CTX1N
CTX1P
C510.1uF
CTX2N
CTX2P
C500.1uF
CRX2N
CRX2P
POL
AMSEL
EN
SSTXN
SSTXP
SSRXN
SSRXP
LNAN
LNAP
CTX2P
CTX2N
LNBN
LNBP
CRX2P
CRX2N
LNCN
LNCP
CSBU1
CSBU2
CSBU1
CSBU2
PAD
LNDN
LNDP
Connect to
Type C SBU
pins
SBU1
SBU2
Connect to control
logic to select
swtich
configuration(i.e. CC
control logic)
POL
AMSEL
EN
USB3_TX0N
USB3_TX0P
Connecto to USB
Host/Hub SS TX/RX
pairs
USB3_RX0N
USB3_RX0P
ML0P
ML0N
ML1P
ML1N
ML0..ML3:
Connecto to
DP Source
MainLink
lanes
ML2P
ML2N
ML3P
ML3N
SBU1
SBU2
Connecto to
DP Source
AUX
Channels
HD3SS460
NOTE: ALL DIFF PAIRS ARE
ROUTED 85 TO 90 OHMS
DIFFERENTIAL AND 50 OHMS
COMMON MODE. ALL OTHER
TRACES ARE 50 OHM.
Copyright © 2016, Texas Instruments Incorporated
Figure 16. Schematic Implementations for DP Source/ USB Host (3 of 3)
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VBUS
TypeC Connector and Pin Mapping
J2
GND
A1
B12
GND
ML3P
ML0P
SSTXP1
SSTXP2
A2
B11
SSRXP1
SSRXP2
ML2P
ML1P
ML3N
ML0N
SSTXN1
SSTXN2
A3
B10
SSRXN1
SSRXN1
ML2N
ML1N
A4
B9
VBUS
AUXN
AUXP
A5
B8
SBU2
DP1
A6
B7
DN1
DN1
A7
B6
DP1
SBU1
A8
B5
CC2
VBUS
A9
B4
VBUS
SBU1
SBU2
DN1
DP1
AUXP
AUXN
SSRXP2
SSRXN2
SSTXP2
SSTXN2
SSRXN2
SSRXN1
A10
B3
SSTXN2
SSTXN1
ML0N
ML3N
ML1P
ML2P
SSRXP2
SSRXP1
A11
B2
SSTXP2
SSTXP1
ML0P
ML3P
A12
B1
GND
SSRXP1
Shield6 SSRXN1
Shield5
Shield4
GND0
Shield3
GND1
Shield2
GND2
Shield1
GND3
g6
g5
g4
g3
g2
g1
C8
10uF
A5
B5
CC1
CC2
A8
B8
CSBU1
CSBU2
A7
A6
USB2_N0
USB2_P0
B6
B7
DP2
DN2
SSTXP1
SSTXN1
ML1N
ML2N
GND
CC1
CC2
VBUS
CC1
A4
A9
B4
B9
VBUS1
VBUS2
VBUS3
VBUS4
A2
A3
CTX1P
CTX1N
A11
A10
CRX2P
CRX2N
B2
B3
CTX2P
CTX2N
B11
B10
CRX1P
CRX1N
CC1
CC2
pg3
pg3
Note: It is
recommended to
add isolation
circuit if
voltage is to be
present on any
of the I/Os
while the
HD3SS460
device is off.
A1
A12
B1
B12
USB_TypeC_Receptacle_
CSBU1
CSBU2
R156
2M
R158
2M
pull-down
resistor
between 1M-2M
is
recommended
on SBU1 and
SBU2.
Copyright © 2016, Texas Instruments Incorporated
Figure 17. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (1 of 3)
ESD Components
Place in pass through manner with no stub
U8
1
2
3
4
5
CTX1N
CTX1P
CRX1N
CRX1P
D1+ NC10
D1NC9
GND GND
D2+
NC7
D2NC6
10
9
8
7
6
TPD4E05U06
U9
1
2
3
4
5
CTX2P
CTX2N
CRX2P
CRX2N
D1+ NC10
D1NC9
GND GND
D2+
NC7
D2NC6
10
9
8
7
6
TPD4E05U06
U12
1
2
3
4
5
6
7
NC1
NC2
NC3
NC4
GND
NC5
NC6
D1+
D1D2+
D2GND
D3+
D3-
14
13
12
11
10
9
8
CC1
CC2
USB2_P0
USB2_N0
CSBU1
CSBU2
TPD6E05U06
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Figure 18. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (2 of 3)
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HD3SS460
3P3V
3P3V
C3
0.1uF
R188
10K
R187
10K
R6
10K
VCC
U2
AC Coupling caps to
accomodate higher Vcm
on some USB devices
CRX1N
CRX1P
SSTXN
SSTXP
CRX1P
CRX1N
CTX1N
CTX1P
C51
0.1uF
C50
0.1uF
C49
0.1uF
C48
0.1uF
SSRXN
SSRXP
CTX1P
CTX1N
CTX2N
CTX2P
LNAN
LNAP
CTX2P
CTX2N
CRX2N
CRX2P
POL
AMSEL
EN
LNBN
LNBP
CRX2P
CRX2N
LNCN
LNCP
LNDN
LNDP
Pull-downs for Vcm bias
R300
R299
CSBU1
CSBU2
R298
100K
SBU1
SBU2
USB3_TX0N
USB3_TX0P
USB3_RX0N
USB3_RX0P
100K
100K
Connect to control
logic to select
swtich
configuration(i.e. CC
control logic)
Connecto to USB
Device/Hub
Upstream TX/RX
pairs
ML1P
ML1N
ML0P
ML0N
Connecto to DP
Sink/Branch
MainLink lanes
ML3P
ML3N
ML2P
ML2N
SBU1
SBU2
Connecto to DP Sink
AUX Channels
PAD
R301
100K
CSBU1
CSBU2
POL
AMSEL
EN
HD3SS460
Copyright © 2016, Texas Instruments Incorporated
Figure 19. Schematic Implementations for DP Sink/ USB Device/HUB/Dock (3 of 3)
10 Power Supply Recommendations
There is no power supply sequence required for HD3SS460. However it is recommended that EN is asserted low
after device supply VCC is stable and within specification. It is also recommended that ample decoupling
capacitors are placed at the device VCC near the pin.
22
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11 Layout
11.1 Layout Guidelines
High performance layout practices are paramount for board layout for high speed signals to ensure good signal
integrity. Even minor imperfection can cause impedance mismatch resulting reflection. Special care is warranted
for traces, connections to device, and connectors.
11.1.1 Critical Routing
The high speed differential signals must be routed with great care to minimize signal quality degradation between
the connector and the source or sink of the high speed signals by following the guidelines provided in this
document. Depending on the configuration schemes, the speed of each differential pair can reach a maximum
speed of 5.4 Gbps. These signals are to be routed first before other signals with highest priority.
• Each differential pair should be routed together with controlled differential impedance of 85 to 90-Ω and 50-Ω
common mode impedance. Keep away from other high speed signals. The number of vias should be kept to
minimum. Each pair should be separated from adjacent pairs by at least 3 times the signal trace width. Route
all differential pairs on the same group of layers (Outer layers or inner layers) if not on the same layer. No 90
degree turns on any of the differential pairs. If bends are used on high speed differential pairs, the angle of
the bend should be greater than 135 degrees.
• Length matching:
– Keep high speed differential pairs lengths within 5 mil of each other to keep the intra-pair skew minimum.
– The inter-pair matching of the differential pairs is not as critical as intra-pair matching. The SSTX and
SSRX pairs do not have to match while they need to be routed as short as possible.
• Keep high speed differential pair traces adjacent to ground plane.
• Do not route differential pairs over any plane split
• ESD components on the high speed differential lanes should be placed nearest to the connector in a pass
through manner without stubs on the differential path. In order to control impedance for transmission lines, a
solid ground plane should be placed next to the high- speed signal layer. This also provides an excellent lowinductance path for the return current flow.
– Placement recommendation would be: Connector – ESD Components --- HD3SS460
• For ease of routing, the P and N connection of the USB3.1 differential pairs to the HD3SS460 pins can be
swapped as long as the corresponding pairs are swapped on the other end of the switch The example is
shown in the reference EVM schematics section of this document. The P/N can be swapped on USB 3.1
connection of the switch for ease of routing purposes.
11.1.2 General Routing/Placement Rules
• Route all high-speed signals first on un-routed PCB: SSTXP/N, SSRXT/N, LNAP/N, LNB P/N, LNC P/N, LND
P/N, CTX*P/N. The stub on USB2 D+ and D- pairs should not exceed 3.5mm.
• Follow 20H rule (H is the distance to reference plane) for separation of the high-speed trace from the edge of
the plane
• Minimize parallelism of high speed clocks and other periodic signal traces to high speed lines
• All differential pairs should be routed on the top or bottom layer (microstrip traces) if possible or on the same
group of layers. Vias should only be used in the breakout region of the device to route from the top to bottom
layer when necessary. Avoid using vias in the main region of the board at all cost. Use a ground reference via
next to signal via. Distance between ground reference via and signal need to be calculated to have similar
impedance as traces.
• All differential signals should not be routed over plane split. Changing signal layers is preferable to crossing
plane splits.
• Use of and proper placement of stitching caps when split plane crossing is unavoidable to account for highfrequency return current path
• Route differential traces over a continuous plane with no interruptions.
• Do not route differential traces under power connectors or other interface connectors, crystals, oscillators, or
any magnetic source.
• Route traces away from etching areas like pads, vias, and other signal traces. Try to maintain a 20 mil keepout distance where possible.
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Layout Guidelines (continued)
•
•
•
•
•
Decoupling capacitors should be placed next to each power terminal on the HD3SS460. Care should be
taken to minimize the stub length of the trace connecting the capacitor to the power pin.
Avoid sharing vias between multiple decoupling capacitors.
Place vias as close as possible to the decoupling capacitor solder pad.
Widen VCC/GND planes to reduce effect of static and dynamic IR drop.
The VBUS traces/planes must be wide enough to carry maximum of 2 A current.
11.2 Layout Example
Figure 20, Figure 21, and Figure 22 illustrate some guidelines for layout. Actual layout should be optimized for
various factors such as board geometry, connector type, and application.
Figure 20. USB Type C Connector to HD3SS460 Signal Routing
Figure 21. Dual SMT Mid-Mount Type C Connector Layout Example Zoom-in
24
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SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
Layout Example (continued)
Figure 22. Dual-row SMT Mid-mount Type C with ESD Components
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12 Device and Documentation Support
12.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates — go to the product folder for your device on ti.com. In the
upper right-hand corner, click the Alert me button to register and receive a weekly digest of product information
that has changed (if any). For change details, check the revision history of any revised document.
12.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
12.3 Trademarks
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB-IF, Inc..
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26
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HD3SS460
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SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
PACKAGE OUTLINE
RHR0028A
WQFN - 0.8 mm max height
SCALE 2.700
PLASTIC QUAD FLATPACK - NO LEAD
3.6
3.4
A
B
PIN 1 INDEX AREA
0.5
0.3
5.6
5.4
0.3
0.2
DETAIL
OPTIONAL TERMINAL
TYPICAL
0.8 MAX
C
0.08
0.05
0.00
SEATING PLANE
2±0.1
2X 1.5
(0.2) TYP
EXPOSED
THERMAL PAD
14
11
24X 0.5
10
15
2X
4.5
4±0.1
SEE TERMINAL
DETAIL
1
PIN 1 ID
(OPTIONAL)
24
28
25
28X
28X
0.5
0.3
0.3
0.2
0.1
0.05
C A
B
4219075/A 11/2014
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
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EXAMPLE BOARD LAYOUT
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(2)
SYMM
28X (0.6)
25
28
28X (0.25)
1
24
24X (0.5)
(0.66)
TYP
SYMM
(5.3)
(4)
( 0.2) TYP
VIA
15
10
11
14
(0.75) TYP
(3.3)
LAND PATTERN EXAMPLE
SCALE:15X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219075/A 11/2014
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
www.ti.com
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SLLSEM7B – JANUARY 2015 – REVISED JUNE 2016
EXAMPLE STENCIL DESIGN
RHR0028A
WQFN - 0.8 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
SYMM
(0.55) TYP
28
28X (0.6)
25
28X (0.25)
1
24
24X (0.5)
(1.32)
TYP
SYMM
(5.3)
METAL
TYP
6X (1.12)
15
10
14
11
6X (0.89)
(3.3)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
EXPOSED PAD
75% PRINTED SOLDER COVERAGE BY AREA
SCALE:20X
4219075/A 11/2014
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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29
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
HD3SS460IRHRR
ACTIVE
WQFN
RHR
28
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3SS460I
HD3SS460IRHRT
ACTIVE
WQFN
RHR
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 85
3SS460I
HD3SS460RHRR
ACTIVE
WQFN
RHR
28
3000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
3SS460
HD3SS460RHRT
ACTIVE
WQFN
RHR
28
250
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
3SS460
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
12-Aug-2015
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
HD3SS460IRHRR
WQFN
RHR
28
HD3SS460IRHRT
WQFN
RHR
HD3SS460RHRR
WQFN
RHR
HD3SS460RHRT
WQFN
RHR
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
3000
330.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
28
250
180.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
28
3000
330.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
28
250
180.0
12.4
3.8
5.8
1.2
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Aug-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
HD3SS460IRHRR
WQFN
RHR
28
3000
367.0
367.0
35.0
HD3SS460IRHRT
WQFN
RHR
28
250
210.0
185.0
35.0
HD3SS460RHRR
WQFN
RHR
28
3000
367.0
367.0
35.0
HD3SS460RHRT
WQFN
RHR
28
250
210.0
185.0
35.0
Pack Materials-Page 2
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