STMicroelectronics M48Z58-70MH1 64 kbit 8kb x 8 zeropower sram Datasheet

M48Z58
M48Z58Y
64 Kbit (8Kb x 8) ZEROPOWER® SRAM
INTEGRATED ULTRA LOW POWER SRAM,
POWER-FAIL CONTROL CIRCUIT and
BATTERY
READ CYCLE TIME EQUALS WRITE CYCLE
TIME
AUTOMATIC POWER-FAIL CHIP DESELECT and
WRITE PROTECTION
WRITE PROTECT VOLTAGES
(VPFD = Power-fail Deselect Voltage):
– M48Z58: 4.50V ≤ VPFD ≤ 4.75V
– M48Z58Y: 4.20V ≤ VPFD ≤ 4.50V
SELF-CONTAINED BATTERY in the CAPHAT
DIP PACKAGE
PACKAGING INCLUDES a 28-LEAD SOIC
and SNAPHAT® TOP
(to be Ordered Separately)
SOIC PACKAGE PROVIDES DIRECT
CONNECTION for a SNAPHAT TOP which
CONTAINS the BATTERY and CRYSTAL
PIN and FUNCTION COMPATIBLE with
JEDEC STANDARD 8K x 8 SRAMs
DESCRIPTION
The M48Z58/58Y ZEROPOWER® RAM is an 8K x
8 non-volatile static RAM that integrates power-fail
deselect circuitry and battery control logic on a
single die. The monolithic chip is available in two
special packages to provide a highly integrated
battery backed-up memory solution.
SNAPHAT (SH)
Battery
28
28
1
1
SOH28 (MH)
Figure 1. Logic Diagram
VCC
13
W
Address Inputs
DQ0-DQ7
Data Inputs / Outputs
E
Chip Enable
G
Output Enable
W
Write Enable
VCC
Supply Voltage
VSS
Ground
March 1999
8
A0-A12
Table 1. Signal Names
A0-A12
PCDIP28 (PC)
Battery CAPHAT
DQ0-DQ7
M48Z58
M48Z58Y
E
G
VSS
AI01176B
1/17
M48Z58, M48Z58Y
Figure 2A. DIP Pin Connections
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
28
1
27
2
26
3
25
4
24
5
23
6
7
M48Z58 22
8 M48Z58Y 21
20
9
19
10
18
11
17
12
13
16
14
15
Figure 2B. SOIC Pin Connections
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
NC
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
VSS
1
28
27
2
26
3
25
4
24
5
23
6
22
7
M48Z58Y
21
8
20
9
19
10
18
11
17
12
16
13
15
14
AI01177B
VCC
W
NC
A8
A9
A11
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
AI01178B
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Table 2. Absolute Maximum Ratings (1)
Symbol
Ambient Operating Temperature
TA
TSTG
TSLD
Parameter
(2)
Value
Grade 1
Grade 6
Storage Temperature (VCC Off)
Lead Solder Temperature for 10 seconds
Unit
0 to 70
–40 to 85
°C
–40 to 85
°C
260
°C
V
VIO
Input or Output Voltages
–0.3 to 7
VCC
Supply Voltage
–0.3 to 7
IO
Output Current
20
mA
PD
Power Dissipation
1
W
V
Notes: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may
affect reliability.
2. Soldering temperature not to exceed 260°C for 10 seconds (total thermal budget not to exceed 150°C for longer than 30 seconds).
CAUTION: Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
CAUTION: Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
Table 3. Operating Modes (1)
Mode
VCC
Deselect
Write
Read
4.75V to 5.5V
or
4.5V to 5.5V
Read
Deselect
Deselect
VSO to VPFD (min)
≤ VSO
(2)
E
G
W
DQ0-DQ7
Power
VIH
X
X
High Z
Standby
VIL
X
VIL
DIN
Active
VIL
VIL
VIH
DOUT
Active
VIL
VIH
VIH
High Z
Active
X
X
X
High Z
CMOS Standby
X
X
X
High Z
Battery Back-up Mode
Notes: 1. X = VIH or VIL; VSO = Battery Back-up Switchover Voltage.
2. See Table 7 for details.
2/17
M48Z58, M48Z58Y
Figure 3. Block Diagram
A0-A12
LITHIUM
CELL
POWER
VOLTAGE SENSE
AND
SWITCHING
CIRCUITRY
DQ0-DQ7
8K x 8
SRAM ARRAY
E
VPFD
W
G
VSS
VCC
DESCRIPTION (cont’d)
The M48Z58/58Y is a non-volatile pin and function
equivalent to any JEDEC standard 8K x 8 SRAM.
It also easily fits into many ROM, EPROM, and
EEPROM sockets, providing the non-volatility of
PROMs without any requirement for special write
timing or limitations on the number of writes that
can be performed.
The 28 pin 600mil DIP CAPHAT houses the
M48Z58/58Y silicon with a long life lithium button
cell in a single package.
The 28 pin 330mil SOIC provides sockets with gold
plated contacts at both ends for direct connection
to a separate SNAPHAT housing containing the
battery. The unique design allows the SNAPHAT
battery package to be mounted on top of the SOIC
package after the completion of the surface mount
process. Insertion of the SNAPHAT housing after
reflow prevents potential battery damage due to the
high temperatures required for device surfacemounting. The SNAPHAT housing is keyed to prevent reverse insertion.
The SOIC and battery packages are shipped separately in plastic anti-static tubes or in Tape & Reel
form.
AI01394
Table 4. AC Measurement Conditions
Input Rise and Fall Times
≤ 5ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.9kΩ
DEVICE
UNDER
TEST
OUT
1kΩ
CL includes JIG capacitance
CL = 100pF or 5pF
AI01030
3/17
M48Z58, M48Z58Y
Table 5. Capacitance (1, 2)
(TA = 25 °C)
Symbol
CIN
CIO
(3)
Parameter
Test Condition
Input Capacitance
Input / Output Capacitance
Min
Max
Unit
VIN = 0V
10
pF
VOUT = 0V
10
pF
Notes: 1. Effective capacitance measured with power supply at 5V.
2. Sampled only, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
ICC
Supply Current
ICC1
Supply Current (Standby) TTL
ICC2
Supply Current (Standby) CMOS
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±5
µA
Outputs open
50
mA
E = VIH
3
mA
E = VCC – 0.2V
3
mA
VIL
Input Low Voltage
–0.3
0.8
V
VIH
Input High Voltage
2.2
VCC + 0.3
V
VOL
Output Low Voltage
IOL = 2.1mA
0.4
V
VOH
Output High Voltage
IOH = –1mA
2.4
V
Table 7. Power Down/Up Trip Points DC Characteristics (1)
(TA = 0 to 70°C or –40 to 85°C)
Symbol
Parameter
Min
Typ
Max
Unit
VPFD
Power-fail Deselect Voltage (M48Z58/58Y)
4.5
4.6
4.75
V
VPFD
Power-fail Deselect Voltage (M48Z58/58YY)
4.2
4.35
4.5
V
VSO
Battery Back-up Switchover Voltage
tDR
(2)
Expected Data Retention Time
3.0
10
V
YEARS
Notes: 1. All voltages referenced to VSS.
2. At 25 °C
DESCRIPTION (cont’d)
For the 28 lead SOIC, the battery package (i.e.
SNAPHAT) part number is "M4Z28-BR00SH1".
The M48Z58/58Y also has its own Power-fail Detect circuit. The control circuitry constantly monitors
the single 5V supply for an out of tolerance condi-
4/17
tion. When VCC is out of tolerance, the circuit write
protects the SRAM, providing a high degree of data
security in the midst of unpredictable system operation brought on by low VCC. As VCC falls below
approximately 3V, the control circuitry connects the
battery which maintains data until valid power returns.
M48Z58, M48Z58Y
Table 8. Power Down/Up Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C)
Symbol
Parameter
VPFD (max) to VPFD (min) VCC Fall Time
300
µs
VPFD (min) to VSS VCC Fall Time
10
µs
VPFD(min) to VPFD (max) VCC Rise Time
10
µs
VSS to VPFD (min) VCC Rise Time
1
µs
VPFD (max) to Inputs Recognized
40
tF (1)
tR
tRB
tREC
(3)
Unit
µs
E or W at VIH before Power Down
tFB
Max
0
tPD
(2)
Min
200
ms
Notes: 1. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200 µs after
VCC passes VPFD (min).
2. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
3. tREC (min) = 20ms for industrial temperature grade 6 device.
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tDR
tPD
INPUTS
tRB
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
HIGH-Z
OUTPUTS
VALID
(PER CONTROL INPUT)
VALID
(PER CONTROL INPUT)
AI01168C
5/17
M48Z58, M48Z58Y
Table 9. Read Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z58 / M48Z58Y
Symbol
Parameter
Min
tAVAV
Unit
-70
Read Cycle Time
Max
70
ns
tAVQV (1)
Address Valid to Output Valid
70
ns
tELQV (1)
Chip Enable Low to Output Valid
70
ns
Output Enable Low to Output Valid
35
ns
tGLQV
(1)
tELQX (2)
tGLQX
(2)
tEHQZ (2)
Chip Enable Low to Output Transition
5
ns
Output Enable Low to Output Transition
5
ns
Chip Enable High to Output Hi-Z
25
ns
tGHQZ
(2)
Output Enable High to Output Hi-Z
25
ns
tAXQX
(1)
Address Transition to Output Transition
10
ns
Notes: 1. CL = 100pF (see Figure 4).
2. CL = 5pF (see Figure 4).
Figure 6. Read Mode AC Waveforms
tAVAV
VALID
A0-A12
tAVQV
tAXQX
tELQV
tEHQZ
E
tELQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
VALID
AI01385
Note: Write Enable (W) = High.
6/17
M48Z58, M48Z58Y
Table 10. Write Mode AC Characteristics
(TA = 0 to 70°C or –40 to 85°C; VCC = 4.75V to 5.5V or 4.5V to 5.5V)
M48Z58 / M48Z58Y
Symbol
Parameter
Unit
-70
Min
Max
tAVAV
Write Cycle Time
70
ns
tAVWL
Address Valid to Write Enable Low
0
ns
tAVEL
Address Valid to Chip Enable Low
0
ns
tWLWH
Write Enable Pulse Width
50
ns
tELEH
Chip Enable Low to Chip Enable High
55
ns
tWHAX
Write Enable High to Address Transition
0
ns
tEHAX
Chip Enable High to Address Transition
0
ns
tDVWH
Input Valid to Write Enable High
30
ns
tDVEH
Input Valid to Chip Enable High
30
ns
tWHDX
Write Enable High to Input Transition
5
ns
tEHDX
Chip Enable High to Input Transition
5
ns
tWLQZ (1, 2)
Write Enable Low to Output Hi-Z
25
ns
tAVWH
Address Valid to Write Enable High
60
ns
tAVEH
Address Valid to Chip Enable High
60
ns
Write Enable High to Output Transition
5
ns
tWHQX (1, 2)
Notes: 1. CL = 5pF (see Figure 4).
2. If E goes low simultaneously with W going low, the outputs remain in the high impedance state.
READ MODE
The M48Z58/58Y is in the Read Mode whenever
W (Write Enable) is high, E (Chip Enable) is low.
Thus, the unique address specified by the 13 Address Inputs defines which one of the 8,192 bytes
of data is to be accessed. Valid data will be available at the Data I/O pins within Address Access
time (tAVQV) after the last address input signal is
stable, providing that the E and G access times are
also satisfied. If the E and G access times are not
met, valid data will be available after the latter of
the Chip Enable Access time (tELQV) or Output
Enable Access time (tGLQV).
The state of the eight three-state Data I/O signals
is controlled by E and G. If the outputs are activated
before tAVQV, the data lines will be driven to an
indeterminate state until tAVQV. If the Address Inputs are changed while E and G remain active,
output data will remain valid for Output Data Hold
time (tAXQX) but will go indeterminate until the next
Address Access.
WRITE MODE
The M48Z58/58Y is in the Write Mode whenever W
and E are low. The start of a write is referenced
from the latter occurring falling edge of W or E. A
write is terminated by the earlier rising edge of W
or E. The addresses must be held valid throughout
the cycle. E or W must return high for a minimum
of tEHAX from Chip Enable or tWHAX from Write
Enable prior to the initiation of another read or write
cycle. Data-in must be valid tDVWH prior to the end
of write and remain valid for tWHDX afterward. G
should be kept high during write cycles to avoid bus
contention; although, if the output bus has been
activated by a low on E and G, a low on W will
disable the outputs tWLQZ after W falls.
7/17
M48Z58, M48Z58Y
Figure 7. Write Enable Controlled, Write AC Waveforms
tAVAV
VALID
A0-A12
tAVWH
tWHAX
tAVEL
E
tWLWH
tAVWL
W
tWHQX
tWLQZ
tWHDX
DQ0-DQ7
DATA INPUT
tDVWH
AI01386
Figure 8. Chip Enable Controlled, Write AC Waveforms
tAVAV
A0-A12
VALID
tAVEH
tAVEL
tELEH
tEHAX
E
tAVWL
W
tEHDX
DQ0-DQ7
DATA INPUT
tDVEH
AI01387B
8/17
M48Z58, M48Z58Y
DATA RETENTION MODE
With valid VCC applied, the M48Z58/58Y operates
as a conventional BYTEWIDE static RAM.
Should the supply voltage decay, the RAM will
automatically power-fail deselect, write protecting
itself when VCC f alls within the VPFD(max),
VPFD(min) window. All outputs become high impedance, and all inputs are treated as "don’t care."
Note: A power failure during a write cycle may
corrupt data at the currently addressed location,
but does not jeopardize the rest of the RAM’s
content. At voltages below VPFD(min), the user can
be assured the memory will be in a write protected
state, provided the VCC fall time is not less than tF.
The M48Z58/58Y may respond to transient noise
spikes on VCC that reach into the deselect window
during the time the device is sampling VCC. Therefore, decoupling of the power supply lines is recommended.
When VCC drops below VSO, the control circuit
switches power to the internal battery which preserves data. The internal button cell will maintain
data in the M48Z58/58Y for an accumulated period
of at least 10 years when VCC is less than VSO.
As system power returns and VCC rises above VSO,
the battery is disconnected, and the power supply
is switched to external VCC. Write protection continues until VCC reaches VPFD(min) plus tREC(min).
Normal RAM operation can resume tREC after VCC
exceeds VPFD(max).
For more information on Battery Storage Life refer
to the Application Note AN1012.
POWER SUPPLY DECOUPLING and UNDERSHOOT PROTECTION
ICC transients, including those produced by output
switching, can produce voltage fluctuations, resulting in spikes on the VCC bus. These transients can
be reduced if capacitors are used to store energy,
which stabilizes the VCC bus. The energy stored in
the bypass capacitors will be released as low going
spikes are generated or energy will be absorbed
when overshoots occur. A ceramic bypass capacitor value of 0.1µF (as shown in Figure 9) is recommended in order to provide the needed filtering.
In addition to transients that are caused by normal
SRAM operation, power cycling can generate
negative voltage spikes on VCC that drive it to
values below VSS by as much as one Volt. These
negative spikes can cause data corruption in the
SRAM while in battery backup mode. To protect
from these voltage spikes, it is recommeded to
connect a schottky diode from VCC to VSS (cathode
connected to VCC, anode to VSS). Schottky diode
1N5817 is recommended for through hole and
MBRS120T3 is recommended for surface mount.
Figure 9. Supply Voltage Protection
VCC
VCC
0.1µF
DEVICE
VSS
AI02169
9/17
M48Z58, M48Z58Y
ORDERING INFORMATION SCHEME
Example:
M48Z58Y
Supply Voltage and Write
Protect Voltage
58 (1) VCC = 4.75V to 5.5V
VPFD = 4.5V to 4.75V
58Y
-70
Speed
-70
70ns
MH
1
TR
Package
PC
MH
PCDIP28
(2,3)
SOH28
Temp. Range
1
6
(4)
Shipping Method
for SOIC
0 to 70 °C
blank Tubes
–40 to 85°C
TR
Tape & Reel
VCC = 4.5V to 5.5V
VPFD = 4.2V to 4.5V
Notes: 1. The M48Z58 part is offered with the PCDIP28 (i.e. CAPHAT) package only.
2. The SOIC package (SOH28) requires the battery package (SNAPHAT) which is ordered separately under the part number
"M4Z28-BR00SH1" in plastic tube or "M4Z28-BR00SH1TR" in Tape & Reel form.
3. Delivery may include either the 2-pin version of the SOIC/SNAPHAT or the 4-pin version of the SOIC/SNAPHAT. Both are
functionally equivalent (see package drawing section for details).
4. Industrial temperature grade available in SOIC package (SOH28) only.
Caution: Do not place the SNAPHAT battery package "M4Z28-BR00SH1" in conductive foam since this will drain the lithium button-cell
battery.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device,
please contact the STMicroelectronics Sales Office nearest to you.
10/17
M48Z58, M48Z58Y
PCDIP28 - 28 pin Plastic DIP, battery CAPHAT
mm
Symb
Typ
inches
Min
Max
A
8.89
A1
Min
Max
9.65
0.350
0.380
0.38
0.76
0.015
0.030
A2
8.38
8.89
0.330
0.350
B
0.38
0.53
0.015
0.021
B1
1.14
1.78
0.045
0.070
C
0.20
0.31
0.008
0.012
D
39.37
39.88
1.550
1.570
E
17.83
18.34
0.702
0.722
e1
2.29
2.79
0.090
0.110
e3
29.72
36.32
1.170
1.430
eA
15.24
16.00
0.600
0.630
L
3.05
3.81
0.120
0.150
N
28
28
A2
A1
B1
B
Typ
e1
A
L
C
eA
e3
D
N
E
1
PCDIP
Drawing is not to scale.
11/17
M48Z58, M48Z58Y
SOH28 - 28 lead Plastic Small Outline, 4-socket battery SNAPHAT
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
3.05
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
CP
0.10
A2
0.004
A
C
B
eB
e
CP
D
N
E
H
A1
1
SOH-A
Drawing is not to scale.
12/17
Max
α
L
M48Z58, M48Z58Y
SOH28 - 28 lead Plastic Small Outline, 2-socket battery SNAPHAT
mm
Symb
Typ
inches
Min
Max
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.51
0.014
0.020
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
α
0°
8°
0°
8°
N
28
e
1.27
0.050
28
CP
0.10
A2
0.004
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-B
Drawing is not to scale.
13/17
M48Z58, M48Z58Y
SH - 4-pin SNAPHAT Housing for 49 mAh Battery
mm
Symb
Typ
Min
A
inches
Max
Typ
Min
Max
9.78
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
A1
eA
A2
A
A3
B
L
eB
D
E
SH
Drawing is not to scale.
14/17
M48Z58, M48Z58Y
SH - 2-pin SNAPHAT Housing for 49 mAh Battery
mm
Symb
Typ
Min
A
inches
Max
Typ
Min
Max
9.78
0.385
A1
6.73
7.24
0.265
0.285
A2
6.48
6.99
0.255
0.275
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
14.22
14.99
0.560
0.590
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
A1
A2
A
A3
B
L
eB
D
E
SHZP-A
Drawing is not to scale.
15/17
M48Z58, M48Z58Y
SH - 2-pin SNAPHAT Housing for 130 mAh Battery
mm
Symb
Typ
Min
A
inches
Max
Typ
Min
10.54
0.415
A1
8.00
8.51
0.315
0.335
A2
7.24
8.00
0.285
0.315
A3
0.38
0.015
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
0.710
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
A1
A2
A
A3
B
L
eB
D
E
SHZP-B
Drawing is not to scale.
16/17
Max
M48Z58, M48Z58Y
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by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to
change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
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17/17
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