AD AD9680-500EBZ Dual analog-to-digital converter Datasheet

FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD
SPIVDD
(1.25V) (2.5V) (3.3V)
(1.25V) (1.25V) (1.8V TO 3.3V)
(1.25V)
FD_B
Rev. C
SIGNAL
MONITOR
14
VIN+B
VIN–B
DDC
ADC
CORE
BUFFER
CONTROL
REGISTERS
V_1P0
SIGNAL
MONITOR
CLOCK
GENERATION
CLK+
CLK–
÷2
÷4
÷8
AGND
DRGND DGND
4
FAST
DETECT
JESD204B
SUBCLASS 1
CONTROL
SPI CONTROL
AD9680
SDIO SCLK CSB
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SYNCINB±
SYSREF±
PDWN/
STBY
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
3.
APPLICATIONS
Communications
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE
General-purpose software radios
Ultrawideband satellite receivers
Instrumentation
Radars
Signals intelligence (SIGINT)
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
DDC
11752-001
FD_A
ADC
CORE 14
Tx OUTPUTS
BUFFER
VIN+A
VIN–A
FAST
DETECT
JESD204B (Subclass 1) coded serial digital outputs
1.65 W total power per channel at 1 GSPS (default settings)
SFDR at 1 GSPS = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
SNR at 1 GSPS = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS),
60.5 dBFS at 1 GHz (AIN = −1.0 dBFS)
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range: 1.46 V p-p to 1.94 V p-p
AD9680-1250: 1.58 V p-p nominal
AD9680-1000 and AD9680-820: 1.70 V p-p nominal
AD9680-500: 1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
Programmable termination impedance
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
2 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors per channel
12-bit NCO, up to 4 half-band filters
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither
JESD204B
HIGH SPEED SERIALIZER
Data Sheet
14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS
JESD204B, Dual Analog-to-Digital Converter
AD9680
4.
5.
6.
Wide full power bandwidth supports IF sampling of signals
up to 2 GHz.
Buffered inputs with programmable input termination eases
filter design and implementation.
Four integrated wideband decimation filters and numerically
controlled oscillator (NCO) blocks supporting multiband
receivers.
Flexible serial port interface (SPI) controls various product
features and functions to meet specific system requirements.
Programmable fast overrange detection.
9 mm × 9 mm, 64-lead LFCSP.
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AD9680* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
REFERENCE MATERIALS
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Informational
EVALUATION KITS
Press
• AD-FMCDAQ2-EBZ Evaluation Board
• Analog Devices Introduces High-Performance RF ICs for
Multi-band Base Stations and Microwave Point-to-Point
Radios
• JESD204 Serial Interface
• AD9680/AD9234/AD9690 Evaluation Board
• ADA4961 & AD9680 Analog Signal Chain Evaluation and
AD9528 Converter Synchronization
• Analog Devices Unveils New Class of Data Converters That
Set 14-bit, GSPS Performance Standard
DOCUMENTATION
Technical Articles
Application Notes
• Clocking Wideband GSPS JESD204B ADCs
• AN-835: Understanding High Speed ADC Testing and
Evaluation
• Digital Signal Process in IF RF Data Converters
Data Sheet
• MS-2660: Understanding Spurious-Free Dynamic Range in
Wideband GSPS ADCs
• AD9680: 14-Bit, 1 GSPS/820 MSPS/500 MSPS JESD204B,
Dual Analog-to-Digital Converter Data Sheet
• MS-2672: JESD204B Subclasses - Part 1: An Introduction to
JESD204B Subclasses and Deterministic Latency
TOOLS AND SIMULATIONS
• AD9680 Delphi Models
• Visual Analog
• AD9680 / AD6674 IBIS Model
• AD9680 AMI Model
• AD9680 S-Parameters
• MS-2677: JESD204B Subclasses - Part 2: Subclass 1 vs.
Subclass 2 System Considerations
• MS-2708: GSPS Data Converters to the Rescue for
Electronics Surveillance and Warfare Systems
• MS-2714: Understanding Layers in the JESD204B
Specificaton: A High Speed ADC Perspective, Part 1
• MS-2735: Maximizing the Dynamic Range of SoftwareDefined Radio
• Powering GSPS or RF Sampling ADCs: Switcher vs LDO
DESIGN RESOURCES
• AD9680 Material Declaration
• PCN-PDN Information
• Quality And Reliability
• Symbols and Footprints
DISCUSSIONS
View all AD9680 EngineerZone Discussions.
SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
DOCUMENT FEEDBACK
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AD9680
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Frequency Translation ................................................................... 54
Applications ....................................................................................... 1
General Description ................................................................... 54
Functional Block Diagram .............................................................. 1
DDC NCO Plus Mixer Loss and SFDR ................................... 55
Product Highlights ........................................................................... 1
Numerically Controlled Oscillator .......................................... 55
Revision History ............................................................................... 3
FIR Filters ........................................................................................ 57
General Description ......................................................................... 4
General Description ................................................................... 57
Specifications..................................................................................... 5
Half-Band Filters ........................................................................ 58
DC Specifications ......................................................................... 5
DDC Gain Stage ......................................................................... 60
AC Specifications.......................................................................... 6
DDC Complex to Real Conversion ......................................... 60
Digital Specifications ................................................................... 8
DDC Example Configurations ................................................. 61
Switching Specifications .............................................................. 9
Digital Outputs ............................................................................... 64
Timing Specifications ................................................................ 10
Introduction to the JESD204B Interface ................................. 64
Absolute Maximum Ratings .......................................................... 12
JESD204B Overview .................................................................. 64
Thermal Characteristics ............................................................ 12
Functional Overview ................................................................. 65
ESD Caution ................................................................................ 12
JESD204B Link Establishment ................................................. 65
Pin Configuration and Function Descriptions ........................... 13
Physical Layer (Driver) Outputs .............................................. 67
Typical Performance Characteristics ........................................... 15
JESD204B Tx Converter Mapping ........................................... 69
AD9680-1250 .............................................................................. 15
Configuring the JESD204B Link .............................................. 71
AD9680-1000 .............................................................................. 19
Multichip Synchronization............................................................ 74
AD9680-820 ................................................................................ 24
SYSREF± Setup/Hold Window Monitor ................................. 76
AD9680-500 ................................................................................ 29
Test Modes ....................................................................................... 78
Equivalent Circuits ......................................................................... 33
ADC Test Modes ........................................................................ 78
Theory of Operation ...................................................................... 35
JESD204B Block Test Modes .................................................... 79
ADC Architecture ...................................................................... 35
Serial Port Interface ........................................................................ 81
Analog Input Considerations.................................................... 35
Configuration Using the SPI ..................................................... 81
Voltage Reference ....................................................................... 41
Hardware Interface ..................................................................... 81
Clock Input Considerations ...................................................... 42
SPI Accessible Features .............................................................. 81
ADC Overrange and Fast Detect .................................................. 44
Memory Map .................................................................................. 82
ADC Overrange .......................................................................... 44
Reading the Memory Map Register Table............................... 82
Fast Threshold Detection (FD_A and FD_B) ........................ 44
Memory Map Register Table ..................................................... 83
Signal Monitor ................................................................................ 45
Applications Information .............................................................. 96
SPORT Over JESD204B ............................................................. 46
Power Supply Recommendations............................................. 96
Digital Downconverter (DDC) ..................................................... 48
Exposed Pad Thermal Heat Slug Recommendations ............ 96
DDC I/Q Input Selection .......................................................... 48
AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) .............. 96
DDC I/Q Output Selection ....................................................... 48
Outline Dimensions ....................................................................... 97
DDC General Description ........................................................ 48
Ordering Guide .......................................................................... 97
Rev. C | Page 2 of 97
Data Sheet
AD9680
REVISION HISTORY
11/15—Rev. B to Rev. C
Added AD9680-1250 ......................................................... Universal
Changes to Features Section ............................................................ 1
Change to General Description Section ......................................... 4
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 6
Changes to Table 4 ............................................................................ 9
Changes to Table 5 ..........................................................................10
Changes to Figure 4.........................................................................11
Changes to Pin 14 Description, Table 8 .......................................14
Added AD9680-1250 Section and Figure 6 to Figure 29;
Renumbered Sequentially ..............................................................15
Changes to Figure 113 ....................................................................34
Changes to Analog Input Considerations Section ......................35
Changes to Table 9 ..........................................................................36
Changes to Input Buffer Control Registers (0x018, 0x019,
0x01A, 0x935, 0x934, 0x11A) Section ..........................................37
Added Figure 118 to Figure 120 ....................................................37
Changes to Table 10 ........................................................................40
Changes to Table 17 ........................................................................57
Changes to ADC Test Modes Section...........................................78
Changes to Table 36 ........................................................................83
Changes to Ordering Guide ...........................................................97
3/15—Rev. A to Rev. B
Added AD9680-820 ........................................................... Universal
Changes to Features Section ............................................................ 1
Changes to Table 1 ............................................................................ 5
Changes to Table 2 ............................................................................ 6
Changes to Table 3 ............................................................................ 8
Changes to Table 4 ............................................................................ 9
Added Figure 14; Renumbered Sequentially ...............................15
Added AD9680-820 Section and Figure 31 Through Figure 36 ...19
Added Figure 37 Through Figure 42 ............................................20
Added Figure 43 Through Figure 48 ............................................21
Added Figure 49 Through Figure 54 ............................................22
Added Figure 55 ..............................................................................23
Changes to Figure 69 and Figure 70 .............................................26
Changes to Input Buffer Control Registers (0x018, 0x019, 0x01A,
0x935, 0x934, 0x11A) Section, Table 9, and Figure 93....................31
Added Figure 99 Through Figure 100 ..........................................33
Changes to Table 10 ........................................................................34
Changes to Clock Jitter Considerations Section .........................37
Added Figure 112 ............................................................................37
Changes to Digital Downconverter (DDC) Section ...................42
Changes to Table 17 ........................................................................51
Changes to Table 36 ........................................................................77
Changes to Ordering Guide ...........................................................91
12/14—Rev. 0 to Rev. A
Added AD9680-500 ........................................................... Universal
Changes to Features Section and Figure 1 ..................................... 1
Changes to General Description Section ....................................... 4
Changes to Specifications Section and Table 1 ............................. 5
Changes to AC Specifications Section and Table 2....................... 6
Changes to Digital Specifications Section ..................................... 8
Changes to Switching Specifications Section and Table 4 ........... 9
Changes to Table 6, Thermal Characteristics Section, and
Table 7 ............................................................................................... 11
Change to Digital Inputs Description, Table 8 ............................ 13
Added AD9680-1000 Section, Figure 10, and Figure 11;
Renumbered Sequentially .............................................................. 14
Changes to Figure 6 to Figure 9 .................................................... 14
Added Figure 12 to Figure 14 ........................................................ 15
Changes to Figure 15 to Figure 17 ................................................ 15
Changes to Figure 18 to Figure 21 ................................................ 16
Changes to Figure 25 and Figure 29 ............................................. 17
Changes to Figure 30 ...................................................................... 18
Deleted Figure 35, Figure 36, and Figure 38 ................................ 19
Added AD9680-500 Section and Figure 31 to Figure 54 ............. 19
Changes to Analog Input Considerations Section and
Differential Input Configurations Section ................................... 25
Added Input Buffer Control Registers (0x018, 0x019, 0x01A,
0x935, 0x934, 0x11A) Section, Figure 66, Figure 68, and Table 9;
Renumbered Sequentially .............................................................. 26
Changes to Analog Input Buffer Controls and SFDR
Optimization Section and Figure 67 ............................................ 26
Added Figure 69 to Figure 72 ........................................................ 27
Added Figure 73 to Figure 75 ........................................................ 28
Changes to Table 10 ........................................................................ 28
Added Input Clock Divider ½ Period Delay Adjust Section and
Clock Fine Delay Adjust Section................................................... 30
Changes to Figure 83 and Temperature Diode Section ............. 31
Added Signal Monitor Section and Figure 86 to Figure 89 ....... 33
Changes to Table 11 ........................................................................ 39
Changes to Table 12 to Table 14 .................................................... 40
Changes to Table 16 ........................................................................ 41
Deleted Figure 65 and Figure 66 ................................................... 45
Changes to Table 17 ........................................................................ 45
Changes to Table 19 to Table 20 .................................................... 46
Changes to Table 22 ........................................................................ 47
Changes to Table 23 ........................................................................ 49
Changes to JESD204B Link Establishment Section ................... 53
Added Figure 105 to Figure 110 .................................................... 56
Changes to Example 1: Full Bandwidth Mode Section .............. 60
Added Multichip Synchronization Section, Figure 115 to
Figure 117, and Table 28................................................................. 62
Added Test Modes Section and Table 29 to Table 33 ................. 66
Changes to Reading the Memory Map Register Table Section.......70
Changes to Table 36 ........................................................................ 71
Changes to Power Supply Recommendations Section,
Figure 118, and Exposed Pad Thermal Heat Slug
Recommendations Section ............................................................ 83
Changes to Ordering Guide ........................................................... 84
5/14—Revision 0: Initial Version
Rev. C | Page 3 of 97
AD9680
Data Sheet
GENERAL DESCRIPTION
The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/
500 MSPS analog-to-digital converter (ADC). The device has
an on-chip buffer and sample-and-hold circuit designed for low
power, small size, and ease of use. This device is designed for
sampling wide bandwidth analog signals of up to 2 GHz. The
AD9680 is optimized for wide input bandwidth, high sampling
rate, excellent linearity, and low power in a small package.
function in the communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
Users can configure the Subclass 1 JESD204B-based high speed
serialized output in a variety of one-, two-, or four-lane
configurations, depending on the DDC configuration and the
acceptable lane rate of the receiving logic device. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins.
The analog input and clock signals are differential inputs. Each
ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of up to five cascaded
signal processing stages: a 12-bit frequency translator (NCO),
and four half-band decimation filters. The DDCs are bypassed
by default.
In addition to the DDC blocks, the AD9680 has several
functions that simplify the automatic gain control (AGC)
The AD9680 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.
The AD9680 is available in a Pb-free, 64-lead LFCSP and is
specified over the −40°C to +85°C industrial temperature range.
This product is protected by a U.S. patent.
Rev. C | Page 4 of 97
Data Sheet
AD9680
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity
(DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE
REFERENCE
Voltage
INPUT-REFERRED NOISE
VREF = 1.0 V
ANALOG INPUTS
Differential Input Voltage
Range (Programmable)
Common-Mode Voltage
(VCM)
Differential Input
Capacitance1
Analog Input Full Power
Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
AVDD1_SR
DVDD
DRVDD
SPIVDD
IAVDD1
IAVDD2
IAVDD3
IAVDD1_SR
IDVDD2
IDRVDD1
IDRVDD (L = 2 Mode)
ISPIVDD
Temp
Full
AD9680-500
Min Typ Max
14
AD9680-820
Min Typ
Max
14
Min
14
Full
Full
Full
Full
Full
Full
Guaranteed
−0.3 0
+0.3
0
0.3
−6
0
+6
1
5.1
−0.6 ±0.5 +0.7
Guaranteed
−0.3 0
+0.3
0
0.23
−6
0
+6
1
5.5
−0.7 ±0.5 +0.8
Full
−4.5
−3.3
±2.5
+5.0
±2.5
+4.3
AD9680-1000
Typ
Max
AD9680-1250
Min
Typ
Max
14
Unit
Bits
Guaranteed
−0.31 0
+0.31
0
0.23
−6
0
+6
1
4.5
−0.7
±0.5
+0.8
Guaranteed
−0.31 0
+0.31
0
0.3
−6
0
+6
1
4.5
−0.8
±0.5 +0.8
% FSR
% FSR
% FSR
% FSR
LSB
−5.7
−6
LSB
±2.5
+6.9
±3
+6
Full
Full
−3
±25
−10
±54
−12
±13.8
−15
92
ppm/°C
ppm/°C
Full
1.0
1.0
1.0
1.0
V
25°C
2.06
2.46
2.63
3.45
LSB rms
Full
1.46
2.06
2.06
1.46
1.70
1.94
1.46
1.70
1.94
1.46
1.58
1.94
V p-p
25°C
2.05
2.05
2.05
2.05
V
25°C
1.5
1.5
1.5
1.5
pF
25°C
2
2
2
2
GHz
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
25°C
Full
1.22
2.44
3.2
1.22
1.22
1.22
1.7
1.25
2.50
3.3
1.25
1.25
1.25
1.8
435
395
87
15
145
190
140
5
1.28
2.56
3.4
1.28
1.28
1.28
3.4
467
463
101
22
152
237
6
1.22
2.44
3.2
1.22
1.22
1.22
1.7
1.25
2.50
3.3
1.25
1.25
1.25
1.8
605
490
125
15
205
200
N/A3
5
1.28
2.56
3.4
1.28
1.28
1.28
3.4
660
545
140
18
246
240
6
Rev. C | Page 5 of 97
1.22
2.44
3.2
1.22
1.22
1.22
1.7
1.25
2.50
3.3
1.25
1.25
1.25
1.8
685
595
125
16
208
200
N/A3
5
1.28
2.56
3.4
1.28
1.28
1.28
3.4
720
680
142
18
269
225
6
1.22
2.44
3.2
1.22
1.22
1.22
1.7
1.25
2.50
3.3
1.25
1.25
1.25
1.8
785
675
125
17
250
220
N/A3
5
1.28
2.56
3.4
1.28
1.28
1.28
3.4
880
780
142
20
325
300
6
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
AD9680
Parameter
POWER CONSUMPTION
Total Power Dissipation
(Including Output
Drivers)2
Total Power Dissipation
(L = 2 Mode)
Power-Down Dissipation
Standby4
Data Sheet
Temp
AD9680-500
Min Typ Max
AD9680-820
Min Typ
Max
Min
AD9680-1000
Typ
Max
AD9680-1250
Min
Typ
Max
Unit
Full
2.2
2.9
3.3
3.7
W
25°C
2.1
N/A3
N/A3
N/A3
W
Full
Full
700
1.2
820
1.3
835
1.4
1030
1.66
mW
W
All lanes running. Power dissipation on DRVDD changes with lane rate and number of lanes used.
Default mode. No DDCs used. L = 4, M = 2, F = 1.
3
N/A means not applicable. At the maximum sample rate, it is not applicable to use L = 2 mode on the JESD204B output interface because this exceeds the maximum
lane rate of 12.5 Gbps. L = 2 mode is supported when the equation ((M × N΄ × (10/8) × fOUT)/L) results in a line rate that is ≤12.5 Gbps. fOUT is the output sample rate and
is denoted by fS/DCM, where DCM is the decimation ratio.
4
Can be controlled by the SPI.
1
2
AC SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 2.
Parameter1
ANALOG INPUT FULL SCALE
NOISE DENSITY2
SIGNAL-TO-NOISE RATIO
(SNR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
SNR AND DISTORTION RATIO
(SINAD)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
EFFECTIVE NUMBER OF BITS
(ENOB)
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
Temp
Full
Full
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
AD9680-500
Min Typ
Max
2.06
−153
67.8
67.6
10.9
69.2
69.0
68.6
68.0
64.4
63.8
60.5
69.0
68.8
68.4
67.9
64.2
63.6
60.3
11.2
11.1
11.1
11.0
10.4
10.3
9.7
AD9680-820
Min Typ
Max
1.7
−153
65.6
65.2
10.5
67.2
67.0
66.5
65.1
64.0
63.4
59.7
67.1
66.8
66.3
64.7
63.5
62.7
58.7
10.9
10.8
10.7
10.5
10.3
10.1
9.5
Rev. C | Page 6 of 97
AD9680-1000
Min Typ
Max
1.7
−154
65.1
65.0
10.5
67.2
66.6
65.3
64.0
61.5
60.5
57.0
67.1
66.4
65.2
63.8
62.1
61.1
56.0
10.8
10.7
10.5
10.3
10.0
9.8
9.0
AD9680-1250
Min Typ
Max
1.58
−151.5
61.5
61.4
9.9
Unit
V p-p
dBFS/Hz
63.6
63.2
62.8
62.2
61.1
59.2
55.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
63.5
62.8
62.6
61.8
60.8
58.2
51.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
10.3
10.1
10.1
10.0
9.8
9.4
8.3
Bits
Bits
Bits
Bits
Bits
Bits
Bits
Data Sheet
Parameter1
SPURIOUS-FREE DYNAMIC
RANGE (SFDR)3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
WORST HARMONIC,
SECOND OR THIRD3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
WORST OTHER, EXCLUDING
SECOND OR THIRD
HARMONIC3
fIN = 10 MHz
fIN = 170 MHz
fIN = 340 MHz
fIN = 450 MHz
fIN = 765 MHz
fIN = 985 MHz
fIN = 1950 MHz
TWO-TONE
INTERMODULATION
DISTORTION (IMD),
AIN1 AND AIN2 = −7 dBFS
fIN1 = 185 MHz,
fIN2 = 188 MHz
fIN1 = 338 MHz,
fIN2 = 341 MHz
CROSSTALK5
FULL POWER BANDWIDTH6
AD9680
Temp
25°C
Full
25°C
25°C
25°C
25°C
25°C
AD9680-500
Min Typ
Max
80
83
88
83
81
80
75
70
AD9680-820
Min Typ
Max
75
91
83
81
78
78
74
70
75
88
85
85
82
82
80
68
74
Unit
84
77
78
76
77
71
61
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−84
−77
−78
−76
−77
−71
−61
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
−83
−88
−83
−81
−80
−75
−70
25°C
Full
25°C
25°C
25°C
25°C
25°C
−95
−95
−93
−93
−88
−89
−84
25°C
−88
−90
−87
−82
dBFS
25°C
−88
−87
−88
−784
dBFS
25°C
25°C
95
2
95
2
95
2
95
2
dB
GHz
−82
−97
−93
−91
−90
−83
−84
−74
−75
−80
−88
−85
−85
−82
−82
−80
−68
AD9680-1250
Min Typ
Max
25°C
Full
25°C
25°C
25°C
25°C
25°C
−80
−91
−83
−81
−78
−78
−74
−70
AD9680-1000
Min Typ
Max
−95
−94
−88
−86
−81
−82
−75
−75
−81
−87
−79
−81
−79
−79
−77
−69
−74
−74
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
Noise density is measured at a low analog input frequency (30 MHz).
3
See Table 10 for the recommended settings for full-scale voltage and buffer current settings.
4
Measurement taken with 449 MHz and 452 MHz inputs for two-tone.
5
Crosstalk is measured at 170 MHz with a −1.0 dBFS analog input on one channel and no input on the adjacent channel.
6
Measured with the circuit shown in Figure 115.
1
2
Rev. C | Page 7 of 97
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
AD9680
Data Sheet
DIGITAL SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
SYSREF INPUTS (SYSREF+, SYSREF−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
LOGIC INPUTS (SDI, SCLK, CSB, PDWN/STBY)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
LOGIC OUTPUT (SDIO)
Logic Compliance
Logic 1 Voltage (IOH = 800 µA)
Logic 0 Voltage (IOL = 50 µA)
SYNCIN INPUT (SYNCINB+/SYNCINB−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC OUTPUTS (FD_A, FD_B)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 3)
Logic Compliance
Differential Output Voltage
Output Common-Mode Voltage (VCM)
AC-Coupled
Short-Circuit Current (IDSHORT)
Differential Return Loss (RLDIFF)1
Common-Mode Return Loss (RLCM)1
Differential Termination Impedance
1
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
600
Typ
LVDS/LVPECL
1200
0.85
35
Max
Unit
1800
mV p-p
V
kΩ
pF
2.5
400
0.6
LVDS/LVPECL
1200
0.85
35
1800
2.0
2.5
mV p-p
V
kΩ
pF
CMOS
0.8 × SPIVDD
0
0.5
30
V
V
kΩ
CMOS
0.8 × SPIVDD
0
400
0.6
0.5
LVDS/LVPECL/CMOS
1200
0.85
35
1800
2.0
2.5
V
V
mV p-p
V
kΩ
pF
CMOS
0.8 × SPIVDD
0
0.5
V
V
kΩ
30
Full
Full
360
770
mV p-p
25°C
25°C
25°C
25°C
Full
0
−100
8
6
80
1.8
+100
V
mA
dB
dB
Ω
Differential and common-mode return loss are measured from 100 MHz to 0.75 × baud rate.
Rev. C | Page 8 of 97
CML
100
120
Data Sheet
AD9680
SWITCHING SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified
maximum sampling rate for each speed grade, AIN = −1.0 dBFS, default SPI settings, TA = 25°C, unless otherwise noted.
Table 4.
Parameter
CLOCK
Clock Rate (at
CLK+/CLK− Pins)
Maximum Sample Rate1
Minimum Sample Rate2
Clock Pulse Width High
Clock Pulse Width Low
OUTPUT PARAMETERS
Unit Interval (UI)3
Rise Time (tR) (20% to
80% into 100 Ω Load)
Fall Time (tF) (20% to 80%
into 100 Ω Load)
PLL Lock Time
Data Rate per Channel
(NRZ)4
LATENCY5
Pipeline Latency
Fast Detect Latency
Wake-Up Time6
Standby
Power-Down
APERTURE
Aperture Delay (tA)
Aperture Uncertainty
(Jitter, tJ)
Out-of-Range Recovery
Time
Temp
AD9680-500
Min
Typ Max
Min
Full
0.3
0.3
Full
Full
Full
Full
500
300
1000
1000
Full
25°C
80
24
200
32
80
24
121.95
32
80
24
100
32
80
24
80
32
ps
ps
25°C
24
32
24
32
24
32
24
32
ps
25°C
25°C
3.125
2
5
3.125
2
8.2
3.125
2
10
3.1215
2
12.5
Full
4
AD9680-820
Typ
Max
4
820
300
609.7
609.7
12.5
55
Full
AD9680-1000
Min
Typ Max
AD9680-1250
Min
Typ Max
Unit
0.3
0.3
GHz
4
1000
300
500
500
12.5
55
28
1250
300
400
400
12.5
55
28
1
4
MSPS
MSPS
ps
ps
12.5
55
28
1
Full
Full
530
55
530
55
530
55
530
55
ps
fS rms
Full
1
1
1
1
Clock
cycles
4
The maximum sample rate is the clock rate after the divider.
The minimum sample rate operates at 300 MSPS with L = 2 or L = 1.
3
Baud rate = 1/UI. A subset of this range can be supported.
4
Default L = 4. This number can be changed based on the sample rate and decimation ratio.
5
No DDCs used. L = 4, M = 2, F = 1.
6
Wake-up time is defined as the time required to return to normal operation from power-down mode.
1
2
Rev. C | Page 9 of 97
1
Clock
cycles
Clock
cycles
25°C
25°C
4
1
28
ms
Gbps
4
4
ms
ms
AD9680
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
CLK+ to SYSREF+ TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
Test Conditions/Comments
See Figure 3
Device clock to SYSREF+ setup time
Device clock to SYSREF+ hold time
See Figure 4
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between falling edge of SCLK and output
data valid for a read operation
Time required for the SDIO pin to switch from an output to an
input relative to the SCLK rising edge (not shown in Figure 4)
tDIS_SDIO
Min
Typ
Max
Unit
117
−96
ps
ps
6
ns
ns
ns
ns
ns
ns
ns
ns
2
2
40
2
2
10
10
10
10
ns
Timing Diagrams
APERTURE
DELAY
ANALOG
INPUT
SIGNAL
SAMPLE N
N – 54
N+1
N – 55
N – 53
N–1
N – 51
N – 52
CLK–
CLK+
CLK–
CLK+
SERDOUT0–
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
CONVERTER0 MSB
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
CONVERTER0 LSB
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
CONVERTER1 MSB
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
A
B
C
D
E
F
G
H
I
J
CONVERTER1 LSB
SERDOUT0+
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SAMPLE N – 55
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
SAMPLE N – 54
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
SAMPLE N – 53
ENCODED INTO 1
8-BIT/10-BIT SYMBOL
Figure 2. Data Output Timing (Full Bandwidth Mode; L = 4; M = 2; F = 1)
Rev. C | Page 10 of 97
11752-002
SERDOUT3+
Data Sheet
AD9680
CLK–
CLK+
tSU_SR
tH_SR
11752-003
SYSREF–
SYSREF+
Figure 3. SYSREF± Setup and Hold Timing
tHIGH
tDS
tS
tCLK
tDH
tACCESS
tH
tLOW
CSB
SDIO DON’T CARE
DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D7
Figure 4. Serial Port Interface Timing Diagram
Rev. C | Page 11 of 97
D6
D3
D2
D1
D0
DON’T CARE
11752-004
SCLK DON’T CARE
AD9680
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
Table 6.
Parameter
Electrical
AVDD1 to AGND
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD to DRGND
SPIVDD to AGND
AGND to DRGND
VIN±x to AGND
SCLK, SDIO, CSB to AGND
PDWN/STBY to AGND
Operating Temperature Range
Junction Temperature Range
Storage Temperature Range (Ambient)
Rating
1.32 V
1.32 V
2.75 V
3.63 V
1.32 V
1.32 V
3.63 V
−0.3 V to +0.3 V
3.2 V
−0.3 V to SPIVDD + 0.3 V
−0.3 V to SPIVDD + 0.3 V
−40°C to +85°C
−40°C to +115°C
−65°C to +150°C
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Typical θJA, θJB, and θJC are specified vs. the number of printed
circuit board (PCB) layers in different airflow velocities (in m/sec).
Airflow increases heat dissipation effectively reducing θJA and
θJB. In addition, metal in direct contact with the package leads
and exposed pad from metal traces, through holes, ground, and
power planes, reduces θJA. Thermal performance for actual
applications requires careful inspection of the conditions in
an application. The use of appropriate thermal management
techniques is recommended to ensure that the maximum junction
temperature does not exceed the limits shown in Table 6.
Table 7. Thermal Resistance Values
PCB Type
JEDEC
2s2p Board
Airflow
Velocity
(m/sec)
0.0
1.0
2.5
θJA
17.81, 2
15.61, 2
15.01, 2
ΨJB
6.31, 3
5.91, 3
5.71, 3
θJC_TOP
4.71, 4
N/A5
N/A5
θJC_BOT
1.21, 4
Per JEDEC 51-7, plus JEDEC 51-5 2s2p test board.
Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air).
3
Per JEDEC JESD51-8 (still air).
4
Per MIL-STD 883, Method 1012.1.
5
N/A means not applicable.
1
2
ESD CAUTION
Rev. C | Page 12 of 97
Unit
°C/W
°C/W
°C/W
Data Sheet
AD9680
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
AVDD1
AVDD2
AVDD2
AVDD1
AGND
SYSREF–
SYSREF+
AVDD1_SR
AGND
AVDD1
CLK–
CLK+
AVDD1
AVDD2
AVDD2
AVDD1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
AD9680
TOP VIEW
(Not to Scale)
AVDD1
AVDD1
AVDD2
AVDD3
VIN–B
VIN+B
AVDD3
AVDD2
AVDD2
AVDD2
SPIVDD
CSB
SCLK
SDIO
DVDD
DGND
NOTES
1. EXPOSED PAD. THE EXPOSED THERMAL PAD ON THE BOTTOM OF THE
PACKAGE PROVIDES THE GROUND REFENCE FOR AVDDx. THIS EXPOSED
PAD MUST BE CONNECTED TO GROUND FOR PROPER OPERATION.
11752-005
FD_A
DRGND
DRVDD
SYNCINB–
SYNCINB+
SERDOUT0–
SERDOUT0+
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SERDOUT3+
DRVDD
DRGND
FD_B
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
AVDD1
AVDD1
AVDD2
AVDD3
VIN–A
VIN+A
AVDD3
AVDD2
AVDD2
AVDD2
AVDD2
V_1P0
SPIVDD
PDWN/STBY
DVDD
DGND
Figure 5. Pin Configuration (Top View)
Table 8. Pin Function Descriptions
Pin No.
Power Supplies
0
Mnemonic
Type
Description
EPAD
Ground
1, 2, 47, 48, 49, 52, 55, 61, 64
3, 8, 9, 10, 11, 39, 40, 41,
46, 50, 51, 62, 63
4, 7, 42, 45
13, 38
15, 34
16, 33
18, 31
19, 30
56, 60
57
Analog
5, 6
12
AVDD1
AVDD2
Supply
Supply
Exposed Pad. The exposed thermal pad on the bottom of the
package provides the ground reference for AVDDx. This
exposed pad must be connected to ground for proper
operation.
Analog Power Supply (1.25 V Nominal).
Analog Power Supply (2.5 V Nominal).
AVDD3
SPIVDD
DVDD
DGND
DRGND
DRVDD
AGND1
AVDD1_SR1
Supply
Supply
Supply
Ground
Ground
Supply
Ground
Supply
Analog Power Supply (3.3 V Nominal).
Digital Power Supply for SPI (1.8 V to 3.3 V).
Digital Power Supply (1.25 V Nominal).
Ground Reference for DVDD.
Ground Reference for DRVDD.
Digital Driver Power Supply (1.25 V Nominal).
Ground Reference for SYSREF±.
Analog Power Supply for SYSREF± (1.25 V Nominal).
VIN−A, VIN+A
V_1P0
Input
Input/DNC
44, 43
53, 54
CMOS Outputs
17, 32
VIN−B, VIN+B
CLK+, CLK−
Input
Input
ADC A Analog Input Complement/True.
1.0 V Reference Voltage Input/Do Not Connect. This pin is
configurable through the SPI as a no connect or an input. Do
not connect this pin if using the internal reference. Requires a
1.0 V reference voltage input if using an external voltage
reference source.
ADC B Analog Input Complement/True.
Clock Input True/Complement.
FD_A, FD_B
Output
Fast Detect Outputs for Channel A and Channel B.
Rev. C | Page 13 of 97
AD9680
Pin No.
Digital Inputs
20, 21
58, 59
Data Outputs
22, 23
24, 25
26, 27
28, 29
Device Under Test (DUT)
Controls
14
35
36
37
1
Data Sheet
Mnemonic
Type
Description
SYNCINB−, SYNCINB+
SYSREF+, SYSREF−
Input
Input
Active Low JESD204B LVDS Sync Input True/Complement.
Active High JESD204B LVDS System Reference Input
True/Complement.
SERDOUT0−, SERDOUT0+
SERDOUT1−, SERDOUT1+
SERDOUT2−, SERDOUT2+
SERDOUT3−, SERDOUT3+
Output
Output
Output
Output
Lane 0 Output Data Complement/True.
Lane 1 Output Data Complement/True.
Lane 2 Output Data Complement/True.
Lane 3 Output Data Complement/True.
PDWN/STBY
Input
SDIO
SCLK
CSB
Input/Output
Input
Input
Power-Down Input (Active High). The operation of this pin
depends on the SPI mode and can be configured as powerdown or standby. Requires an external 10 kΩ pull-down resistor.
SPI Serial Data Input/Output.
SPI Serial Clock.
SPI Chip Select (Active Low).
To ensure proper ADC operation, connect AVDD1_SR and AGND separately from the AVDD1 and EPAD connection. For more information, see the Applications
Information section.
Rev. C | Page 14 of 97
Data Sheet
AD9680
TYPICAL PERFORMANCE CHARACTERISTICS
AD9680-1250
AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.58 V p-p
full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted.
See Table 10 for recommended settings.
AIN = –1dBFS
SNR = 64dBFS
ENOB = 10.3 BITS
SFDR = 82dBFS
BUFFER CURRENT = 3.5×
–10
–30
AMPLITUDE (dBFS)
–50
–70
–90
–50
–70
–90
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
–130
11752-606
–130
0
AIN = –1dBFS
SNR = 60.9dBFS
ENOB = 9.8 BITS
SFDR = 74dBFS
BUFFER CURRENT = 5.5×
–10
–30
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
Figure 9. Single-Tone FFT with fIN = 450.3 MHz
AIN = –1dBFS
SNR = 63.4dBFS
ENOB = 10.2 BITS
SFDR = 79dBFS
BUFFER CURRENT = 3.5×
–30
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
Figure 6. Single-Tone FFT with fIN = 10.3 MHz
–10
78.125
11752-609
–110
–110
–50
–70
–90
–110
–50
–70
–90
–110
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
–130
11752-607
–130
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
Figure 7. Single-Tone FFT with fIN = 170.3 MHz
11752-610
AMPLITUDE (dBFS)
–30
AIN = –1dBFS
SNR = 62.5dBFS
ENOB = 9.9 BITS
SFDR = 70dBFS
BUFFER CURRENT = 3.5×
–10
Figure 10. Single-Tone FFT with fIN = 765.3 MHz
0
AIN = –1dBFS
SNR = 62.8dBFS
ENOB = 10.1 BITS
SFDR = 76dBFS
BUFFER CURRENT = 3.5×
–10
AMPLITUDE (dBFS)
–20
–50
–70
–90
–40
–60
–80
–130
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
Figure 8. Single-Tone FFT with fIN = 340.3 MHz
–120
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
Figure 11. Single-Tone FFT with fIN = 985.3 MHz
Rev. C | Page 15 of 97
11752-611
–100
–110
11752-608
AMPLITUDE (dBFS)
–30
AIN = –1dBFS
SNR = 59.7dBFS
ENOB = 9.6 BITS
SFDR = 74dBFS
BUFFER CURRENT = 5.5×
AD9680
Data Sheet
85
0
AIN = –1dBFS
SNR = 58.5dBFS
ENOB = 9.3 BITS
SFDR = 68dBFS
BUFFER CURRENT = 5.5×
80
–40
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
–20
–60
–80
SFDR
75
70
65
–100
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
60
11752-612
–120
Figure 12. Single-Tone FFT with fIN = 1205.3 MHz
1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260
SAMPLE RATE (MHz)
Figure 15. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 (0x018) = 3.5×
85
0
AIN = –1dBFS
SNR = 56.6dBFS
ENOB = 9.0 BITS
SFDR = 67dBFS
BUFFER CURRENT = 7.5×
3.5× SNR (dBFS)
3.5× SFDR (dBFS)
4.5× SNR (dBFS)
4.5× SFDR (dBFS)
80
SNR/SFDR (dBFS)
–40
–60
–80
75
70
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
60
10.3
11752-613
–120
147.3
212.3
290.3
355.3
433.3
511.3
589.3
667.3
INPUT FREQUENCY (MHz)
Figure 13. Single-Tone FFT with fIN = 1602.3 MHz
11752-616
65
–100
Figure 16. SNR/SFDR vs. fIN; fIN < 700 MHz;
Buffer Control 1 (0x018) = 3.5× and 4.5×
80
0
AIN = –1dBFS
SNR = 55.4dBFS
ENOB = 8.8 BITS
SFDR = 63dBFS
BUFFER CURRENT = 8.5×
–20
SNR 6.5×
SFDR 6.5×
75
SNR/SFDR (dBFS)
–40
–60
–80
70
65
60
–120
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
11752-614
–100
55
628.3
706.6 784.3 862.3 940.3 1018.3 1096.3 1174.3 1252.3
INPUT FREQUENCY (MHz)
Figure 17. SNR/SFDR vs. fIN; 650 MHz < fIN < 1.3 GHz;
Buffer Control 1 (0x018) = 6.5×
Figure 14. Single-Tone FFT with fIN = 1954.3 MHz
Rev. C | Page 16 of 97
11752-617
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
11752-615
SNR
Data Sheet
AD9680
0
80
SNR 8.5×
SFDR 8.5×
–20
SFDR/IMD3 (dBc AND dBFS)
70
65
60
–60
–80
1356.3
1460.3
1564.3
1668.3
177.23
1876.3
1980.3
INPUT FREQUENCY (MHz)
–120
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
11752-618
50
1252.3
0
INPUT AMPLITUDE (dBFS)
Figure 18. SNR/SFDR vs. fIN; 1.3 GHz < fIN < 2GHz;
Buffer Control 1 (0x018) = 8.5×
11752-622
–100
55
Figure 21. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 184 MHz and fIN2 = 187 MHz
0
0
AIN1 AND AIN2 = –7dBFS
SFDR = 82dBFS
IMD2 = 84dBFS
IMD3 = 82dBFS
BUFFER CURRENT = 3.5×
IMD3 (dBc)
IMD3 (dBFS)
SFDR (dBFS)
SFDR (dBc)
–20
SFDR/IMD3 (dBc AND dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–100
–120
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
11752-095
–120
0
INPUT AMPLITUDE (dBFS)
Figure 19. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz
11752-623
AMPLITUDE (dBFS)
–40
Figure 22. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with
fIN1 = 449 MHz and fIN2 = 452 MHz
0
120
AIN1 AND AIN2 = –7dBFS
SFDR = 78dBFS
IMD2 = 78dBFS
IMD3 = 78dBFS
BUFFER CURRENT = 5.5×
–20
100
80
SNR/SFDR (dB)
–40
–60
60
40
20
–80
0
–100
SNR (dBFS)
SNR (dBc)
SFDR (dBc)
SFDR (dBFS)
–120
0
78.125
156.250 234.375 312.500 390.625 468.750 546.875 625.000
FREQUENCY (MHz)
11752-096
–20
Figure 20. Two-Tone FFT; fIN1 = 449 MHz, fIN2 = 452 MHz
–40
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
0
INPUT AMPLITUDE (dBFS)
Figure 23. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz
Rev. C | Page 17 of 97
11752-624
SNR/SFDR (dBFS)
75
AMPLITUDE (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
SFDR (dBFS)
SFDR (dBc)
AD9680
Data Sheet
1200000
85
3.45 LSB rms
SFDR
1000000
NUMBER OF HITS
SNR/SFDR (dBFS)
80
75
70
65
800000
600000
400000
SNR
12 22 32 42 52 62 72 82 92 102 112
TEMPERATURE (°C)
0
11752-628
2
11752-625
55
–48 –38 –28 –18 –8
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
200000
60
CODE
Figure 24. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
Figure 27. Input-Referred Noise Histogram
4
4.00
3
3.95
3.90
2
3.85
POWER (W)
INL (LSB)
1
0
–1
3.80
3.75
3.70
–2
3.65
–3
0
2000
4000
6000
8000
10000
12000
14000
16000
OUTPUT CODE
3.55
–48 –38 –28 –18 –8
11752-626
–4
Figure 25. INL, fIN = 10.3 MHz
12
22
32
42
52
62
72
82
Figure 28. Power Dissipation vs. Temperature
0.4
4.0
0.3
3.9
POWER DISSIPATION (W)
0.2
0.1
0
–0.1
–0.2
3.8
3.7
3.6
3.5
–0.4
0
2000
4000
6000
8000
10000
12000
OUTPUT CODE
14000
16000
Figure 26. DNL, fIN = 15 MHz
3.3
1000 1020 1040 1060 1080 1100 1120 1140 1160 1180 1200 1220 1240 1260
SAMPLE RATE (MHz)
Figure 29. Power Dissipation vs. fS
Rev. C | Page 18 of 97
11752-630
3.4
–0.3
11752-627
DNL (LSB)
2
TEMPERATURE (°C)
11752-629
3.60
Data Sheet
AD9680
AD9680-1000
AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.7 V p-p
full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted.
See Table 10 for recommended settings.
AIN = –1dBFS
SNR = 67.2dBFS
ENOB = 10.8 BITS
SFDR = 88dBFS
BUFFER CONTROL 1 = 1.5×
–10
–30
AMPLITUDE (dBFS)
–50
–70
–90
–110
–50
–70
–90
0
100
200
300
400
500
FREQUENCY (MHz)
–130
11752-100
–130
0
500
AIN = –1dBFS
SNR = 61.5dBFS
ENOB = 10.1 BITS
SFDR = 82dBFS
BUFFER CONTROL 1 = 6.0×
–20
AMPLITUDE (dBFS)
–50
–70
–90
–40
–60
–80
–100
0
100
200
300
400
500
FREQUENCY (MHz)
–120
11752-101
–130
0
100
200
Figure 31. Single-Tone FFT with fIN = 170.3 MHz
0
500
AIN = –1dBFS
SNR = 60.5dBFS
ENOB = 9.9 BITS
SFDR = 80dBFS
BUFFER CONTROL 1 = 6.0×
–20
AMPLITUDE (dBFS)
–30
400
Figure 34. Single-Tone FFT with fIN = 765.3 MHz
AIN = –1dBFS
SNR = 65.3dBFS
ENOB = 10.5 BITS
SFDR = 85dBFS
BUFFER CONTROL 1 = 3.0×
–10
300
FREQUENCY (MHz)
11752-104
AMPLITUDE (dBFS)
400
0
–110
–50
–70
–90
–40
–60
–80
–100
–110
–130
0
100
200
300
400
FREQUENCY (MHz)
500
11752-102
AMPLITUDE (dBFS)
300
Figure 33. Single-Tone FFT with fIN = 450.3 MHz
AIN = –1dBFS
SNR = 66.6dBFS
ENOB = 10.7 BITS
SFDR = 85dBFS
BUFFER CONTROL 1 = 3.0×
–30
200
FREQUENCY (MHz)
Figure 30. Single-Tone FFT with fIN = 10.3 MHz
–10
100
11752-103
–110
–120
0
100
200
300
400
FREQUENCY (MHz)
Figure 35. Single-Tone FFT with fIN = 985.3 MHz
Figure 32. Single-Tone FFT with fIN = 340.3 MHz
Rev. C | Page 19 of 97
500
11752-105
AMPLITUDE (dBFS)
–30
AIN = –1dBFS
SNR = 64.0dBFS
ENOB = 10.3 BITS
SFDR = 82dBFS
BUFFER CONTROL 1 = 3.0×
–10
AD9680
0
90
AIN = –1dBFS
SNR = 59.8BFS
ENOB = 9.6 BITS
SFDR = 79dBFS
BUFFER CONTROL 1 = 8.0×
–20
85
SFDR (dBFS)
–40
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
Data Sheet
–60
–80
80
75
70
SNR (dBFS)
–100
0
100
200
300
400
500
FREQUENCY (MHz)
60
700
750
800
850
900
950
1000
1050
1100
SAMPLE RATE (MHz)
Figure 39. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 (0x018) = 3.0×
Figure 36. Single-Tone FFT with fIN = 1293.3 MHz
90
0
AIN = –1dBFS
SNR = 57.7dBFS
ENOB = 9.2 BITS
–20 SFDR = 70dBFS
BUFFER CONTROL 1 = 8.0×
85
80
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
11752-201
–120
11752-107
65
–40
–60
–80
75
70
65
55
1.5× SFDR (dBFS)
1.5× SNR (dBFS)
3.0× SFDR (dBFS)
3.0× SNR (dBFS)
0
100
200
300
400
500
FREQUENCY (MHz)
11752-108
–120
50
10.3
63.3
100.3 170.3 225.3 302.3 341.3 403.3 453.3 502.3
ANALOG INPUT FREQUENCY (MHz)
Figure 40. SNR/SFDR vs. fIN; fIN < 500 MHz;
Buffer Control 1 (0x018) = 1.5× and 3.0×
Figure 37. Single-Tone FFT with fIN = 1725.3 MHz
100
0
AIN = –1dBFS
SNR = 57.0dBFS
ENOB = 9.1 BITS
SFDR = 69dBFS
BUFFER CURRENT = 6.0×
90
SNR/SFDR (dBFS)
–20
–40
–60
–80
80
70
60
–120
0
100
200
300
FREQUENCY (MHz)
400
500
50
476.8
4.0× SFDR
4.0× SNRFS
6.0× SFDR
6.0× SNRFS
554.4
593.2
670.8
748.4
826.0
903.6
981.2
ANALOG INPUT FREQUENCY (MHz)
Figure 41. SNR/SFDR vs. fIN; 500 MHz < fIN < 1 GHz;
Buffer Control 1 (0x018) = 4.0× and 6.0×
Figure 38. Single-Tone FFT with fIN = 1950.3 MHz
Rev. C | Page 20 of 97
11752-218
–100
11752-506
AMPLITUDE (dBFS)
11752-216
60
–100
Data Sheet
AD9680
100
0
–20
AMPLITUDE (dBFS)
90
80
SFDR
70
–40
–60
–80
SNR
60
50
978.5
1142.4
1065.0
1220.0
1297.3
1452.2
1374.8
–120
ANALOG INPUT FREQUENCY (MHz)
0
100
200
300
500
Figure 45. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz
Figure 42. SNR/SFDR vs. fIN; 1 GHz < fIN < 1.5 GHz;
Buffer Control 1 (0x018) = 6.0×
20
100
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
0
SFDR/IMD3 (dBc AND dBFS)
90
80
SFDR
70
60
SNR
1607.4
1701.6
–40
–60
–80
–100
–120
11752-220
50
1513.3
–20
1889.7
1795.6
ANALOG INPUT FREQUENCY (MHz)
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
INPUT AMPLITUDE (dBFS)
Figure 46. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 184 MHz and fIN2 = 187 MHz
Figure 43. SNR/SFDR vs. fIN; 1.5 GHz < fIN < 2 GHz;
Buffer Control 1 (0x018) = 7.5×
20
0
AIN1 AND AIN2 = –7dBFS
SFDR = 87dBFS
IMD2 = 93dBFS
IMD3 = 87dBFS
BUFFER CONTROL 1 = 3.0×
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
0
SNR/SFDR (dBc AND dBFS)
–20
–40
–60
–80
–20
–40
–60
–80
–100
–100
0
100
200
300
400
FREQUENCY (MHz)
500
–140
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
INPUT AMPLITUDE (dBFS)
Figure 47. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with
fIN1 = 338 MHz and fIN2 = 341 MHz
Figure 44. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz
Rev. C | Page 21 of 97
11752-208
–120
–120
11752-205
AMPLITUDE (dBFS)
11752-207
SNR/SFDR (dBFS)
400
FREQUENCY (MHz)
11752-206
–100
11752-219
SNR/SFDR (dBFS)
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
IMD2 = 93dBFS
IMD3 = 88dBFS
BUFFER CONTROL 1 = 4.5×
AD9680
Data Sheet
3
110
100
90
2
80
1
60
INL (LSB)
SNR/SFDR (dB)
70
50
40
30
0
–1
20
10
–20
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12 –6
–3
0
INPUT AMPLITUDE (dBFS)
0
11752-209
–10
2000
4000
6000
8000
10000 12000 14000 16000
OUTPUT CODE
11752-211
–2
SFDR (dBFS)
SFDR (dBc)
SNR (dBFS)
SNR (dBc)
0
Figure 50. INL, fIN = 10.3 MHz
Figure 48. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz
0.6
100
0.4
SFDR
0.2
DNL (LSB)
80
70
0
SNR
–0.2
60
50
–50 –40 –30 –20 –10
0
10
20
30
40
50
60
70
80
TEMPERATURE (°C)
90
–0.6
0
2000
4000
6000
8000
10000 12000 14000 16000
OUTPUT CODE
Figure 51. DNL, fIN = 15 MHz
Figure 49. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
Rev. C | Page 22 of 97
11752-212
–0.4
11752-210
SNR/SFDR (dBFS)
90
Data Sheet
AD9680
3.40
25000
L = 4, M = 2, F = 1
2.63 LSB rms
3.35
3.30
POWER DISSIPATION (W)
NUMBER OF HITS
20000
15000
10000
3.25
3.20
3.15
3.10
3.05
3.00
5000
N–6 N–5 N–4 N–3 N–2 N–1
N
N+1 N+2 N+3 N+4 N+5 N+6
CODE
Figure 52. Input-Referred Noise Histogram
L=4
M=2
F=1
3.30
3.25
3.20
10
20
30
40
50
60
70
TEMPERATURE (°C)
80
90
11752-214
POWER DISSIPATION (W)
3.35
0
750
800
850
900
950
1000
SAMPLE RATE (MHz)
Figure 54. Power Dissipation vs. fS
3.40
3.15
–50 –40 –30 –20 –10
2.90
700
Figure 53. Power Dissipation vs. Temperature
Rev. C | Page 23 of 97
1050
1100
11752-215
0
11752-213
2.95
AD9680
Data Sheet
AD9680-820
AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 1.7 V p-p
full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted.
See Table 10 for recommended settings.
0
0
AIN = –1dBFS
SNR = 67.2dBFS
ENOB = 10.9BITS
SFDR = 89dBFS
BUFFER CONTROL 1 = 1.5×
AMPLITUDE (dBFS)
–40
–60
–80
–40
–60
–80
82
164
246
FREQUENCY (MHz)
328
410
0
82
164
246
328
410
FREQUENCY (MHz)
Figure 58. Single-Tone FFT with fIN = 450.3 MHz
0
0
AIN = –1dBFS
SNR = 67.0dBFS
ENOB = 10.8 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 2.0×
AIN = –1dBFS
SNR = 64.0dBFS
ENOB = 10.3 BITS
SFDR = 79dBFS
BUFFER CONTROL 1 = 6.5×
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
410
–120
Figure 55. Single-Tone FFT with fIN = 10.3 MHz
–40
–60
–80
–100
–40
–60
–80
0
82
164
246
328
410
FREQUENCY (MHz)
11752-508
–100
–120
–120
0
82
164
246
328
FREQUENCY (MHz)
Figure 56. Single-Tone FFT with fIN = 170.3 MHz
Figure 59. Single-Tone FFT with fIN = 765.3 MHz
0
0
AIN = –1dBFS
SNR = 66.5dBFS
ENOB = 10.7 BITS
SFDR = 86dBFS
BUFFER CONTROL 1 = 3.0×
AIN = –1dBFS
SNR = 63.4dBFS
ENOB = 10.1 BITS
SFDR = 74dBFS
BUFFER CONTROL 1 = 8.5×
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–100
–120
0
82
164
246
FREQUENCY (MHz)
328
410
11752-509
AMPLITUDE (dBFS)
410
11752-510
0
11752-507
–120
11752-511
–100
–100
11752-512
AMPLITUDE (dBFS)
–20
AIN = –1dBFS
SNR = 65.1dBFS
ENOB = 10.5 BITS
SFDR = 79dBFS
BUFFER CONTROL 1 = 6.5×
–20
Figure 57. Single-Tone FFT with fIN = 340.3 MHz
–120
0
82
164
246
328
FREQUENCY (MHz)
Figure 60. Single-Tone FFT with fIN = 985.3 MHz
Rev. C | Page 24 of 97
Data Sheet
AD9680
0
90
AIN = –1dBFS
SNR = 62.0dBFS
ENOB = 9.9 BITS
SFDR = 76dBFS
BUFFER CONTROL 1 = 6.5×
85
SFDR
80
–40
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
–20
–60
–80
75
70
SNR
65
60
–100
0
82
164
246
FREQUENCY (MHz)
328
410
50
500
550
Figure 61. Single-Tone FFT with fIN = 1205.3 MHz
650
700
750
SAMPLE RATE (MHz)
800
850
900
Figure 64. SNR/SFDR vs. fS, fIN = 170.3 MHz;
Buffer Control 1 (0x018) = 3.0×
0
95
AIN = –1dBFS
SNR = 60.5dBFS
ENOB = 9.5 BITS
SFDR = 68dBFS
BUFFER CONTROL 1 = 7.5×
–20
90
85
–40
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
600
11752-516
–120
11752-513
55
–60
–80
80
75
70
65
60
–100
11752-517
450.3
420.3
390.3
360.3
340.7
330.3
301.3
270.3
240.3
210.5
FREQUENCY (MHz)
50
180.3
410
170.3
328
150.3
246
95.3
164
65.5
82
10.3
0
11752-514
–120
125.4
SFDR (3.0×)
SNR (3.0×)
55
ANALOG INPUT FREQUENCY (MHz)
Figure 65. SNR/SFDR vs. fIN; fIN < 450 MHz;
Buffer Control 1 (0x018) = 3.0×
Figure 62. Single-Tone FFT with fIN = 1720.3 MHz
85
0
AIN = –1dBFS
SNR = 59.7dBFS
ENOB = 9.5 BITS
SFDR = 69dBFS
BUFFER CONTROL 1 = 8.5×
80
SNR/SFDR (dBFS)
75
–40
–60
–80
70
65
60
–100
55
–120
0
82
164
246
328
FREQUENCY (MHz)
410
50
450.3
480.3
510.3
515.3
610.3
766.3
810.3
ANALOG INPUT FREQUENCY (MHz)
Figure 66. SNR/SFDR vs. fIN; 450 MHz < fIN < 1 GHz;
Buffer Control 1 (0x018) = 6.5×
Figure 63. Single-Tone FFT with fIN = 1950.3 MHz
Rev. C | Page 25 of 97
985.3
11752-018
SFDR (6.5×)
SNR (6.5×)
11752-515
AMPLITUDE (dBFS)
–20
Data Sheet
80
0
75
–20
AMPLITUDE (dBFS)
70
65
60
AIN1 AND AIN2 = –7dBFS
SFDR = 87dBFS
IMD2 = 92dBFS
IMD3 = 87dBFS
BUFFER CURRENT = 3.0×
–40
–60
–80
SFDR (6.5×)
SNR (6.5×)
1022.3
1110.3
–120
1205.3
1315.3
1420.3
1510.3
ANALOG INPUT FREQUENCY (MHz)
11752-519
50
985.3
0
246
328
410
Figure 70. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz
75
0
–20
SFDR/IMD3 (dBc AND dBFS)
70
65
60
55
–40
–60
–80
–100
1920.3
1600.3
1720.3
1810.3
ANALOG INPUT FREQUENCY (MHz)
1950.3
11752-520
SFDR (8.5×)
SNR (8.5×)
50
1510.3
IMD3 (dBc)
IMD3 (dBFS)
SFDR (dBc)
SFDR (dBFS)
–120
–87 –81 –75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9
INPUT AMPLITUDE (dBFS)
11752-528
SNR/SFDR (dBFS)
164
FREQUENCY (MHz)
Figure 67. SNR/SFDR vs. fIN; 1 GHz < fIN < 1.5 GHz;
Buffer Control 1 (0x018) = 6.5×
Figure 71. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 184 MHz and fIN2 = 187 MHz
Figure 68. SNR/SFDR vs. fIN; 1.5 GHz < fIN < 2 GHz;
Buffer Control 1 (0x018) = 8.5×
0
0
AIN1 AND AIN2 = –7dBFS
SFDR = 90dBFS
IMD2 = 90dBFS
IMD3 = 91dBFS
BUFFER CURRENT = 3.0×
–20
SFDR/IMD3 (dBc AND dBFS)
–20
–40
–60
–80
–100
IMD3 (dBc)
IMD3 (dBFS)
SFDR (dBc)
SFDR (dBFS)
–40
–60
–80
–100
–120
0
82
164
246
FREQUENCY (MHz)
328
410
11752-529
AMPLITUDE (dBFS)
82
11752-527
–100
55
–120
–87 –81 –75 –69 –63 –57 –51 –45 –39 –33 –27 –21 –15 –9
INPUT AMPLITUDE (dBFS)
Figure 72. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with
fIN1 = 338 MHz and fIN2 = 341 MHz
Figure 69. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz
Rev. C | Page 26 of 97
11752-535
SNR/SFDR (dBFS)
AD9680
Data Sheet
AD9680
2.5
105
2.0
90
1.5
SNR/SFDR (dBc AND dBFS)
120
75
1.0
INL (LSB)
60
45
30
0.5
0
–0.5
15
–1.0
SNR (dBc)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
–1.5
0
–5
–10
–15
–20
–25
–30
–35
–40
–45
–50
–55
–60
–65
–70
–75
–80
–85
–90
–95
–30
–2.0
0
2000
4000
6000
8000 10000
OUTPUT CODE
12000
14000
16000
11752-534
–15
11752-521
0
INPUT AMPLITUDE (dBFS)
Figure 73. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz
Figure 75. INL, fIN = 10.3 MHz
90
0.25
SNR (dBFS)
SFDR (dBFS)
0.20
85
0.15
DNL (LSB)
0.05
75
0
–0.05
–0.10
70
–0.15
–0.20
65
–30
–15
–5
5
15
25
TEMPERATURE (°C)
45
65
85
–0.30
0
2000
4000
6000
8000 10000
OUTPUT CODE
12000
Figure 76. DNL, fIN = 15 MHz
Figure 74. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
Rev. C | Page 27 of 97
14000
16000
11752-530
–0.25
60
–45
11752-533
SNR/SFDR (dBFS)
0.10
80
AD9680
Data Sheet
3.1
1600000
2.46 LSB rms
1400000
3.0
2.9
POWER (W)
1000000
800000
600000
2.8
2.7
400000
11752-531
CODE
2.90
2.88
2.86
2.84
2.82
2.80
–15
–5
5
15
25
TEMPERATURE (°C)
45
65
85
11752-532
2.78
–30
900
875
850
825
800
775
750
725
700
650
675
625
600
575
550
SAMPLE RATE (MHz)
Figure 79. Power Dissipation vs. fS ; L = 4, M = 2, F = 1 for fS ≥ 625 MSPS and
L = 2, M = 2, F = 2 for fS < 625 MSPS (Default SPI)
Figure 77. Input-Referred Noise Histogram
2.76
–45
525
2.5
500
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
0
11752-522
2.6
200000
POWER (W)
NUMBER OF HITS
1200000
Figure 78. Power Dissipation vs. Temperature
Rev. C | Page 28 of 97
Data Sheet
AD9680
AD9680-500
AVDD1 = 1.25 V, AVDD1_SR = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, 2.06 V p-p
full-scale differential input, AIN = −1.0 dBFS, default SPI settings, clock divider = 2, TA = 25°C, 128k FFT sample, unless otherwise noted.
See Table 10 for recommended settings.
0
0
AIN = −1dBFS
SNR = 68.9dBFS
ENOB = 10.9 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 2.0×
–20
–40
AMPLITUDE (dBFS)
–40
–60
–80
–60
–80
–100
–100
0
25
50
75
100
125
150
175
200
225
–140
11752-132
–140
250
FREQUENCY (MHz)
0
25
175
200
225
250
–40
AMPLITUDE (dBFS)
–60
–80
–60
–80
–100
–120
–140
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
11752-133
–120
–140
0
75
100
125
150
175
200
225
250
Figure 84. Single-Tone FFT with fIN = 765.3 MHz
0
AIN = −1dBFS
SNR = 68.5dBFS
ENOB = 10.9 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 4.5×
–20
50
FREQUENCY (MHz)
Figure 81. Single-Tone FFT with fIN = 170.3 MHz
0
25
11752-136
AMPLITUDE (dBFS)
150
AIN = −1dBFS
SNR = 64.7dBFS
ENOB = 10.4 BITS
SFDR = 80dBFS
BUFFER CONTROL 1 = 5.0×
–20
–100
AIN = −1dBFS
SNR = 64.0dBFS
ENOB = 10.3 BITS
SFDR = 76dBFS
BUFFER CONTROL 1 = 5.0×
–20
–40
–40
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
125
0
–40
–60
–80
–100
–120
–60
–80
–100
–120
0
25
50
75
100
125
150
175
200
225
FREQUENCY (MHz)
250
–140
11752-134
–140
100
Figure 83. Single-Tone FFT with fIN = 450.3 MHz
AIN = −1dBFS
SNR = 68.9dBFS
ENOB = 11 BITS
SFDR = 88dBFS
BUFFER CONTROL 1 = 2.0×
–20
75
FREQUENCY (MHz)
Figure 80. Single-Tone FFT with fIN = 10.3 MHz
0
50
11752-135
–120
–120
0
25
50
75
100
125
150
175
200
225
FREQUENCY (MHz)
Figure 82. Single-Tone FFT with fIN = 340.3 MHz
Figure 85. Single-Tone FFT with fIN = 985.3 MHz
Rev. C | Page 29 of 97
250
11752-137
AMPLITUDE (dBFS)
AIN = −1dBFS
SNR = 67.8dBFS
ENOB = 10.8 BITS
SFDR = 83dBFS
BUFFER CONTROL 1 = 4.5×
–20
AD9680
Data Sheet
95
0
AIN = −1dBFS
SNR = 63.0dBFS
ENOB = 10.0 BITS
SFDR = 69dBFS
BUFFER CONTROL 1 = 8.0×
90
SNR/SFDR (dBFS)
–60
–80
80
75
–100
70
–120
65
–140
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
SNR
60
300 320 340 360 380 400 420 440 460 480 500 530 550
11752-138
AMPLITUDE (dBFS)
SFDR
85
–40
SAMPLE FREQUENCY (MHz)
Figure 86. Single-Tone FFT with fIN = 1310.3 MHz
11752-141
–20
Figure 89. SNR/SFDR vs. fS, fIN = 170.3 MHz; Buffer Control 1 = 2.0×
100
0
AIN = −1dBFS
SNR = 61.5dBFS
ENOB = 9.8 BITS
SFDR = 69dBFS
BUFFER CONTROL 1 = 8.0×
–20
90
SNR/SFDR (dBFS)
AMPLITUDE (dBFS)
–40
–60
–80
80
70
–100
60
0
25
50
75
100
125
150
175
200
225
250
FREQUENCY (MHz)
50
10.3
11752-139
–140
2.0× SNR
2.0× SFDR
4.5× SNR
4.5× SFDR
95.3
150.3
180.3
240.3
301.3
340.7
390.3
450.3
ANALOG INPUT FREQUENCY (MHz)
Figure 87. Single-Tone FFT with fIN = 1710.3 MHz
11752-142
–120
Figure 90. SNR/SFDR vs. fIN; fIN < 500 MHz;
Buffer Control 1 (0x018) = 2.0× and 4.5×
0
100
AIN = −1dBFS
SNR = 60.8dBFS
ENOB = 9.6 BITS
SFDR = 68dBFS
BUFFER CONTROL 1 = 8.0×
–20
90
SNR/SFDR (dBFS)
–60
–80
80
70
–100
60
–140
0
25
50
75
100
125
150
175
200
225
FREQUENCY (MHz)
250
50
450.3
4.0× SNR
4.0× SFDR
8.0× SNR
8.0× SFDR
480.3
510.3
515.3
610.3
765.3
810.3
985.3
ANALOG INPUT FREQUENCY (MHz)
Figure 91. SNR/SFDR vs. fIN; 500 MHz < fIN < 1 GHz;
Buffer Control 1 (0x018) = 4.0× and 8.0×
Figure 88. Single-Tone FFT with fIN = 1950.3 MHz
Rev. C | Page 30 of 97
1010.3
11752-143
–120
11752-140
AMPLITUDE (dBFS)
–40
Data Sheet
80
0
7.0× SNR
7.0× SFDR
8.0× SNR
8.0× SFDR
70
65
60
–60
–80
1950.3
–120
–90 –84 –78 –72 –66 –60 –54 –48 –42 –36 –30 –24 –18 –12
11752-148
1205.3
1810.3
1410.3
1600.3
ANALOG INPUT FREQUENCY (MHz)
11752-144
50
1010.3
INPUT AMPLITUDE (dBFS)
Figure 92. SNR/SFDR vs. fIN; 1 GHz < fIN < 2 GHz;
Buffer Control 1 (0x018) = 7.0× and 8.0×
Figure 95. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 184 MHz and fIN2 = 187 MHz
0
0
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
IMD2 = 94dBFS
IMD3 = 88dBFS
BUFFER CONTROL 1 = 2.0×
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
–20
SFDR/IMD3 (dBc AND dBFS)
–20
–40
–60
–80
–40
–60
–80
0
50
100
150
FREQUENCY (MHz)
200
250
11752-146
–120
–120
–90
–72
–63
–54
–45
–36
100
SNR/SFDR (dBc AND dBFS)
90
–40
–60
–80
–100
80
70
60
50
40
30
20
10
SFDR (dBFS)
SNR (dBFS)
SFDR (dBc)
SNR (dBc)
0
–10
200
250
–20
–90
11752-147
–120
100
150
FREQUENCY (MHz)
–9
110
AIN1 AND AIN2 = –7dBFS
SFDR = 88dBFS
IMD2 = 88dBFS
IMD3 = 89dBFS
BUFFER CONTROL 1 = 4.5×
50
–18
Figure 96. Two-Tone IMD3/SFDR vs. Input Amplitude (AIN) with
fIN1 = 338 MHz and fIN2 = 341 MHz
0
0
–27
AMPLITUDE (dBFS)
Figure 93. Two-Tone FFT; fIN1 = 184 MHz, fIN2 = 187 MHz
–20
–81
11752-149
–100
–100
–80
–70
–60
–50
–40
–30
–20
–10
INPUT AMPLITUDE (dBFS)
Figure 94. Two-Tone FFT; fIN1 = 338 MHz, fIN2 = 341 MHz
Figure 97. SNR/SFDR vs. Analog Input Level, fIN = 170.3 MHz
Rev. C | Page 31 of 97
0
11752-150
AMPLITUDE (dBFS)
–40
–100
55
AMPLITUDE (dBFS)
SFDR (dBc)
SFDR (dBFS)
IMD3 (dBc)
IMD3 (dBFS)
–20
SFDR/IMD3 (dBc AND dBFS)
75
SNR/SFDR (dBFS)
AD9680
AD9680
Data Sheet
95
900000
2.06 LSB RMS
800000
SFDR
700000
85
NUMBER OF HITS
SNR/SFDR (dBFS)
90
80
75
600000
500000
400000
300000
200000
SNR
70
35
60
85
0
N – 10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
10
TEMPERATURE (°C)
11752-151
–15
OUTPUT CODE
Figure 98. SNR/SFDR vs. Temperature, fIN = 170.3 MHz
Figure 101. Input-Referred Noise Histogram
2.32
3.0
L=4
M=2
F=1
2.5
2.30
2.0
1.5
2.28
POWER (W)
INL (LSB)
11752-154
100000
65
–40
1.0
0.5
0
2.26
2.24
–0.5
–1.0
2.22
0
2000
4000
6000
8000
10000
12000
14000
16000
OUTPUT CODE
2.20
–45
11752-152
–2.0
–35
–5
15
25
45
65
11752-155
–1.5
85
TEMPERATURE (°C)
Figure 99. INL, fIN = 10.3 MHz
Figure 102. Power Dissipation vs. Temperature
0.8
2.37
0.6
2.32
L = 4, M = 2, F = 1
L = 2, M = 2, F = 2
2.27
0.4
POWER (W)
DNL (LSB)
2.22
0.2
0
–0.2
2.17
2.12
2.07
2.02
–0.4
1.97
–0.6
2000
4000
6000
8000
10000
12000
OUTPUT CODE
14000
16000
1.87
300 320 340 360 380 400 420 440 460 480 500 520 540
11752-153
0
SAMPLE RATE (MHz)
Figure 103. Power Dissipation vs. fS
Figure 100. DNL, fIN = 15 MHz
Rev. C | Page 32 of 97
11752-156
1.92
–0.8
Data Sheet
AD9680
EQUIVALENT CIRCUITS
AVDD3
AVDD3
AVDD3
3pF 1.5pF
200Ω
EMPHASIS/SWING
CONTROL (SPI)
VCM
BUFFER
200Ω
67Ω
28Ω
10pF
200Ω
400Ω
DRVDD
AVDD3
AVDD3
DATA+
SERDOUTx+
x = 0, 1, 2, 3
VIN–x
DRGND
OUTPUT
DRIVER
DATA–
SERDOUTx–
x = 0, 1, 2, 3
11752-011
AIN
CONTROL
(SPI)
3pF 1.5pF
DRVDD
DRGND
Figure 104. Analog Inputs
11752-014
67Ω
200Ω
28Ω
VIN+x
Figure 107. Digital Outputs
DVDD
1kΩ
25Ω
CLK+
DGND
20kΩ
LEVEL
TRANSLATOR
25Ω
SYNCINB–
20kΩ
20kΩ
VCM = 0.85V
VCM
1kΩ
SYNCINB± PIN
CONTROL (SPI)
11752-012
CLK–
20kΩ
DVDD
AVDD1
VCM = 0.85V
11752-015
SYNCINB+
AVDD1
DGND
Figure 105. Clock Inputs
Figure 108. SYNCINB± Inputs
AVDD1_SR
1kΩ
SPIVDD
ESD
PROTECTED
20kΩ
LEVEL
TRANSLATOR
AVDD1_SR
SCLK
20kΩ
SPIVDD
1kΩ
30kΩ
1kΩ
ESD
PROTECTED
11752-013
SYSREF–
VCM = 0.85V
11752-016
SYSREF+
Figure 106. SYSREF± Inputs
Figure 109. SCLK Input
Rev. C | Page 33 of 97
AD9680
Data Sheet
SPIVDD
ESD
PROTECTED
30kΩ
1kΩ
CSB
1kΩ
PDWN/
STBY
ESD
PROTECTED
11752-017
ESD
PROTECTED
Figure 110. CSB Input
Figure 113. PDWN/STBY Input
SPIVDD
ESD
PROTECTED
AVDD2
SDO
ESD
PROTECTED
SPIVDD
1kΩ
SDIO
PDWN
CONTROL (SPI)
11752-020
ESD
PROTECTED
SPIVDD
SDI
V_1P0
30kΩ
11752-018
V_1P0 PIN
CONTROL (SPI)
Figure 111. SDIO Input
Figure 114. V_1P0 Input/Output
SPIVDD
ESD
PROTECTED
FD
JESD LMFC
FD_A/FD_B
JESD SYNC~
TEMPERATURE DIODE
(FD_A ONLY)
FD_x PIN CONTROL (SPI)
11752-019
ESD
PROTECTED
Figure 112. FD_A/FD_B Outputs
Rev. C | Page 34 of 97
11752-021
ESD
PROTECTED
ESD
PROTECTED
Data Sheet
AD9680
THEORY OF OPERATION
The AD9680 has two analog input channels and four JESD204B
output lane pairs. The ADC is designed to sample wide bandwidth
analog signals of up to 2 GHz. The AD9680 is optimized for wide
input bandwidth, high sampling rate, excellent linearity, and
low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The AD9680 has several functions that simplify the AGC
function in a communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
The Subclass 1 JESD204B-based high speed serialized output data
lanes can be configured in one-lane (L = 1), two-lane (L = 2),
and four-lane (L = 4) configurations, depending on the sample
rate and the decimation ratio. Multiple device synchronization
is supported through the SYSREF± and SYNCINB± input pins.
ADC ARCHITECTURE
The architecture of the AD9680 consists of an input buffered
pipelined ADC. The input buffer is designed to provide a
termination impedance to the analog input signal. This
termination impedance can be changed using the SPI to meet
the termination needs of the driver/amplifier. The default
termination value is set to 400 Ω. The equivalent circuit diagram of
the analog input termination is shown in Figure 104. The input
buffer is optimized for high linearity, low noise, and low power.
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The buffer
is optimized for high linearity, low noise, and low power. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample; at the same time, the remaining stages operate with the
preceding samples. Sampling occurs on the rising edge of the clock.
ANALOG INPUT CONSIDERATIONS
The analog input to the AD9680 is a differential buffer. The
internal common-mode voltage of the buffer is 2.05 V. The
clock signal alternately switches the input circuit between
sample mode and hold mode. When the input circuit is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within one-half of a clock cycle.
A small resistor, in series with each input, can help reduce the peak
transient current injected from the output stage of the driving
source. In addition, low Q inductors or ferrite beads can be placed
on each leg of the input to reduce high differential capacitance at
the analog inputs and, thus, achieve the maximum bandwidth of
the ADC. Such use of low Q inductors or ferrite beads is required
when driving the converter front end at high IF frequencies.
Either a differential capacitor or two single-ended capacitors
can be placed on the inputs to provide a matching passive network.
This ultimately creates a low-pass filter at the input, which limits
unwanted broadband noise. For more information, refer to the
AN-742 Application Note, the AN-827 Application Note, and
the Analog Dialogue article “Transformer-Coupled Front-End
for Wideband A/D Converters” (Volume 39, April 2005). In
general, the precise values depend on the application.
For best dynamic performance, the source impedances driving
VIN+x and VIN−x must be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
Maximum SNR performance is achieved by setting the ADC
to the largest span in a differential configuration. In the case
of the AD9680, the available span is programmable through
the SPI port from 1.46 V p-p to 2.06 V p-p differential, with
1.58 V p-p differential being the default for the AD9680-1250,
1.70 V p-p differential being the default for the AD9680-1000
and AD9680-820, and 2.06 V p-p differential being the default
for the AD9680-500.
Differential Input Configurations
There are several ways to drive the AD9680, either actively or
passively. However, optimum performance is achieved by
driving the analog input differentially.
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 115 and Table 9) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD9680.
For low to midrange frequencies, a double balun or double
transformer network (see Figure 115 and Table 9) is recommended for optimum performance of the AD9680. For higher
frequencies in the second or third Nyquist zones, it is better
to remove some of the front-end passive components to ensure
wideband operation (see Figure 115 and Table 9).
Rev. C | Page 35 of 97
AD9680
Data Sheet
0.1µF
R1
R3
R2
C1
ADC
C2
R2
R1
0.1µF
0.1µF
R3
C1
11752-168
BALUN
NOTES
1. SEE TABLE 9 FOR COMPONENT VALUES.
Figure 115. Differential Transformer-Coupled Configuration for AD9680
Table 9. Differential Transformer-Coupled Input Configuration Component Values
Device
AD9680-500
Frequency Range
DC to 250 MHz
250 MHz to 2 GHz
DC to 410 MHz
410 MHz to 2 GHz
DC to 500 MHz
500 MHz to 2 GHz
DC to 625 MHz
625 MHz to 2 GHz
AD9680-820
AD9680-1000
AD9680-1250
Transformer
ETC1-1-13
BAL-0006/BAL-0006SMG
ETC1-1-13
BAL-0006/BAL-0006SMG
ETC1-1-13/BAL-0006SMG
BAL-0006/BAL-0006SMG
BAL-0006SMG
BAL-0006SMG
Input Common Mode
The analog inputs of the AD9680 are internally biased to the
common mode as shown in Figure 116. The common-mode
buffer has a limited range in that the performance suffers greatly
if the common-mode voltage drops by more than 100 mV.
Therefore, in dc-coupled applications, set the common-mode
voltage to 2.05 V, ±100 mV to ensure proper ADC operation.
The full-scale voltage setting must be at a 1.7 V p-p differential
if running in a dc-coupled application.
Analog Input Buffer Controls and SFDR Optimization
The AD9680 input buffer offers flexible controls for the analog
inputs, such as input termination, buffer current, and input fullscale adjustment. All the available controls are shown in Figure 116.
AVDD3
AVDD3
R1 (Ω)
10
10
10
10
25
25
10
10
R2 (Ω)
50
50
50
50
25
25
50
50
R3 (Ω)
10
10
10
10
10
0
15
0
C1 (pF)
4
4
4
4
4
Open
4
Open
C2 (pF)
2
2
2
2
2
Open
2
Open
Input Buffer Control Registers (0x018, 0x019, 0x01A,
0x935, 0x934, 0x11A)
The input buffer has many registers that set the bias currents and
other settings for operation at different frequencies. These bias
currents and settings can be changed to suit the input frequency
range of operation. Register 0x018 controls the buffer bias current
to help with the kickback from the ADC core. This setting can be
scaled from a low setting of 1.0× to a high setting of 8.5×. The
default setting is 3.0× for the AD9680-1000 and AD9680-820,
and 2.0× for the AD9680-500. These settings are sufficient for
operation in the first Nyquist zone for the products. When the
input buffer current in Register 0x018 is set, the amount of
current required by the AVDD3 supply changes. This relationship
is shown in Figure 117. For a complete list of buffer current
settings, see Table 36.
300
VIN+x
VCM
BUFFER
200Ω
AD9680-1250,
AD9680-1000,
AND
AD9680-820
200
AD9680-500
150
AVDD3
AVDD3
100
VIN–x
50
1.5×
11752-169
3pF 1.5pF
AIN CONTROL
SPI REGISTERS
(0x008, 0x015,
0x016, 0x018,
0x019, 0x01A,
0x11A, 0x934,
0x935)
Figure 116. Analog Input Controls
Using the 0x018, 0x019, 0x01A, 0x11A, 0x934, and 0x935 registers,
the buffer behavior on each channel can be adjusted to optimize the
SFDR over various input frequencies and bandwidths of interest.
2.5×
3.5×
4.5×
5.5×
6.5×
7.5×
8.5×
BUFFER CONTROL 1 SETTING
11752-341
67Ω
28Ω
10pF
200Ω
400Ω
IAVDD3 (mA)
200Ω
200Ω
28Ω
67Ω
250
AVDD3
3pF 1.5pF
Figure 117. IAVDD3 vs. Buffer Control 1 Setting in Register 0x018
The 0x019, 0x01A, 0x11A, and 0x935 registers offer secondary
bias controls for the input buffer for frequencies >500 MHz.
Register 0x934 can be used to reduce input capacitance to achieve
wider signal bandwidth but may result in slightly lower linearity
Rev. C | Page 36 of 97
Data Sheet
AD9680
Figure 118, Figure 119, and Figure 120 show the SFDR vs.
analog input frequency for various buffer settings for the
AD9680-1250. The recommended settings shown in Table 10
were used to take the data while changing the contents of
Register 0x018 only.
85
250MHz
350MHz
450MHz
550MHz
80
74
72
70
68
66
64
62
650MHz
750MHz
850MHz
60
58
1304.3
1408.3
1512.3
1616.3
1720.3
11752-633
Register 0x11A is used when sampling in higher Nyquist zones
(>500 MHz for the AD9680-1000). This setting enables the ADC
sampling network to optimize the sampling and settling times
internal to the ADC for high frequency operation. For frequencies
greater than 500 MHz, it is recommended to operate the ADC core
at a 1.46 V full-scale setting irrespective of the speed grade. This
setting offers better SFDR without any significant penalty in SNR.
76
SFDR (dBFS)
and noise performance. These register settings do not impact the
AVDD3 power as much as Register 0x018 does. For frequencies
<500 MHz, it is recommended to use the default settings for
these registers. Table 10 shows the recommended values for the
buffer current control registers for various speed grades.
1928.3
1824.3
INPUT FREQUENCY (MHz)
Figure 120. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF);
1300 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115
Figure 121, Figure 122, and Figure 123 show the SFDR vs.
analog input frequency for various buffer settings for the
AD9680-1000. The recommended settings shown in Table 10
were used to take the data while changing the contents of
Register 0x018 only.
85
75
80
70
SFDR (dBFS)
147.3
212.3
290.3
355.3
433.3
511.3
589.3
667.3
INPUT FREQUENCY (MHz)
70
65
60
55
Figure 118. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF);
fIN < 500 MHz; Front-End Network Shown in Figure 115
50
10
1.5×
3.0×
4.5×
60
110
80
160
210
260
310
360
410
460
ANALOG INPUT FREQUENCY (MHz)
Figure 121. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF);
fIN < 500 MHz; Front-End Network Shown in Figure 115
75
85
4.0×
5.0×
6.0×
80
70
75
65
55
602.3
SFDR (dBFS)
60
70
350MHz
450MHz
550MHz
650MHz
680.3
758.3
65
60
55
836.3
914.3
992.3 1070.3 1148.3 1226.3
INPUT FREQUENCY (MHz)
11752-632
SFDR (dBFS)
11752-170
60
10.3
11752-631
65
75
50
45
Figure 119. Buffer Current Sweeps, AD9680-1250 (SFDR vs. IBUFF);
600 MHz < fIN < 1300 MHz; Front-End Network Shown in Figure 115
40
503.4
677.6
851.9
1026.2
1200.5
ANALOG INPUT FREQUENCY (MHz)
1374.8
11752-172
SFDR (dBFS)
90
Figure 122. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF);
500 MHz < fIN < 1500 MHz; Front-End Network Shown in Figure 115
Rev. C | Page 37 of 97
Data Sheet
80
95
75
90
70
85
65
80
SFDR (dBFS)
SFDR (dBFS)
AD9680
60
55
75
70
65
50
450.3
420.3
390.3
360.3
330.3
301.3
240.3
340.7
11752-524
1022.3
985.3
810.3
450.3
420.3
ANALOG INPUT FREQUENCY (MHz)
60
Figure 126. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF);
500 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 115
80
Figure 124. SNR/SFDR vs. Analog Input Level vs. Input Frequencies, AD9680-1000
70
SFDR (dBFS)
65
60
11752-525
1950.3
1920.3
1810.3
1720.3
50
1600.3
55
1510.3
Figure 125, Figure 126, and Figure 127 show the SFDR vs.
analog input frequency for various buffer settings for the
AD9680-820. The recommended settings shown in Table 10
were used to take the data while changing the contents of
Register 0x018 only.
6.5×
7.5×
8.5×
75
1420.3
INPUT LEVEL (dBFS)
1315.3
55
–1
1205.3
–2
1110.3
55
–3
1.52GHz
1.65GHz
1.76GHz
1.9GHz
1.95GHz
50
1022.3
60
SNR (dBc)
65
65
270.3
3.5×
4.5×
5.5×
6.5×
7.5×
55
11752-174
SFDR (dBFS)
70
210.5
65
60
70
180.3
70
766.3
75
75
610.3
75
80
80
515.3
1.65GHz
1.52GHz
1.76GHz
1.95GHz
1.9GHz
85
510.3
80
ANALOG INPUT FREQUENCY (MHz)
Figure 125. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF);
fIN < 500 MHz; Front-End Network Shown in Figure 115
SFDR (dBFS)
In certain high frequency applications, the SFDR can be improved
by reducing the full-scale setting, as shown in Table 10. At high
frequencies, the performance of the ADC core is limited by jitter.
The SFDR can be improved by backing off of the full scale level.
Figure 124 shows the SFDR and SNR vs. full-scale input level at
different high frequencies for the AD9680-1000.
170.3
Figure 123. Buffer Current Sweeps, AD9680-1000 (SFDR vs. IBUFF);
1500 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115
150.3
50
125.4
1889.8
480.3
1795.6
65.5
1701.5
ANALOG INPUT FREQUENCY (MHz)
95.3
1607.4
11752-523
55
10.3
40
1513.4
1.5×
2.0×
3.0×
4.5×
60
11752-173
45
4.5×
5.5×
6.5×
7.5×
8.5×
ANALOG INPUT FREQUENCY (MHz)
Figure 127. Buffer Current Sweeps, AD9680-820 (SFDR vs. IBUFF);
1000 MHz < fIN < 2000 MHz; Front-End Network Shown in Figure 115
Rev. C | Page 38 of 97
Data Sheet
AD9680
Figure 128, Figure 129, and Figure 130 show the SFDR vs.
analog input frequency for various buffer settings for the
AD9680-500. The recommended settings shown in Table 10
were used to take the data while changing the contents of
Register 0x018 only.
95
4.0×
5.0×
6.0×
7.0×
8.0×
90
SFDR (dBFS)
85
100
90
80
75
70
65
450.3
60
480.3
510.3
515.3
610.3
765.3
810.3
985.3
ANALOG INPUT FREQUENCY (MHz)
50
95.3
80
150.3
180.3
240.3
301.3
340.7
390.3
ANALOG INPUT FREQUENCY (MHz)
450.3
75
Figure 128. Buffer Current Sweeps, AD9680-500 (SFDR vs. IBUFF);
fIN < 500 MHz; Front-End Network Shown in Figure 115 Buffer Control 1
(0x018) = 1.0×, 1.5×, 2.0×, 3.0×, or 4.5×
70
SFDR (dBFS)
30
10.3
Figure 129. Buffer Current Sweeps, AD9680-500 (SFDR vs. IBUFF);
450 MHz < fIN < 1000 MHz; Front-End Network Shown in Figure 115
1.0×
1.5×
2.0×
3.0×
4.5×
11752-145
40
11752-175
70
65
60
55
50
45
40
1010.3
4.0×
5.0×
6.0×
7.0×
8.0×
1205.3
1410.3
1600.3
1810.3
1950.3
ANALOG INPUT FREQUENCY (MHz)
Figure 130. Buffer Current Sweeps, AD9680-500 (SFDR vs. IBUFF);
1 GHz < fIN < 2 GHz; Front-End Network Shown in Figure 115
Rev. C | Page 39 of 97
11752-176
SFDR (dBFS)
80
AD9680
Data Sheet
Table 10. Recommended Register Settings for SFDR Optimization at Different Input Frequencies
Product
AD9680500
AD9680820
AD96801000
AD96801250
1
2
3
Frequency
DC to
250 MHz
250 MHz to
500 MHz
500 MHz to
1 GHz
1 GHz to
2 GHz
DC to
200 MHz
DC to
410 MHz
500 MHz to
1 GHz
1 GHz to
2 GHz
DC to
150 MHz
DC to
500 MHz
500 MHz to
1 GHz
1 GHz to
2 GHz
DC to
625 MHz
>625 MHz
Buffer
Control 1
(0x018)—
Buffer
Current
Control
0x20
(2.0×)
0x70
(4.5×)
0x80
(5.0×)
0xF0
(8.5×)
0x10
(1.5×)
0x40
(3.0×)
0x80
(5.0×)
0xF0
(8.5×)
0x10
(1.5×)
0x40
(3.0×)
0xA0
(6.0×)
0xD0
(7.5×)
0x50
(3.5×)
0xA0
(6.0×)
Buffer
Control 2
(0x019)—
Buffer
Bias
Setting
0x60
(Setting 3)
0x60
(Setting 3)
0x40
(Setting 1)
0x40
(Setting 1)
0x40
(Setting 1)
0x40
(Setting 1)
0x40
(Setting 1)
0x40
(Setting 1)
0x50
(Setting 2)
0x50
(Setting 2)
0x60
(Setting 3)
0x70
(Setting 4)
0x50
(Setting 2)
0x50
(Setting 2)
Buffer
Control 3
(0x01A)—
Buffer
Bias
Setting
0x0A
(Setting 3)
0x0A
(Setting 3)
0x08
(Setting 1)
0x08
(Setting 1)
0x09
(Setting 2)
0x09
(Setting 2)
0x08
(Setting 1)
0x08
(Setting 1)
0x09
(Setting 2)
0x09
(Setting 2)
0x09
(Setting 2)
0x09
(Setting 2)
0x09
(Setting 2)
0x09
(Setting 2)
Buffer
Control 4
(0x11A)—
High
Frequency
Setting
0x00 (off)
Buffer
Control 5
(0x935)—
Low
Frequency
Setting
0x04 (on)
0x00 (off)
0x04 (on)
0x00 (off)
0x00 (off)
0x00 (off)
0x00 (off)
0x00 (off)
0x04 (on)
0x00 (off)
0x04 (on)
0x00 (off)
0x00 (off)
0x00 (off)
0x00 (off)
0x00 (off)
0x04 (on)
0x00 (off)
0x04 (on)
0x20 (on)
0x00 (off)
0x20 (on)
0x00 (off)
0x00 (off)
0x04 (on)
N/A3
0x00 (off)
Input
Full-Scale
Range
(0x025)
0x0C
(2.06 V p-p)
0x0C
(2.06 V p-p)
0x08
(1.46 V p-p)
0x08
(1.46 V p-p)
0x0A
(1.70 V p-p)
0x0A
(1.70 V p-p)
0x08
(1.46 V p-p)
0x08
(1.46 V p-p)
0x0A
(1.70 V p-p)
0x0A
(1.70 V p-p)
0x08
(1.46 V p-p)
0x08
(1.46 V p-p)
0x0A
(1.58 V p-p)
0x08
(1.46 V p-p)
Input
FullScale
Control
(0x030)
0x04
Input
Termination
(0x016)1
0x0C/0x1C/…
Input
Capacitance
(0x934)
0x1F
0x04
0x0C/0x1C/…
0x1F
0x18
0x0C/0x1C/…
0x1F or 0x002
0x18
0x0C/0x1C/…
0x1F or 0x001
0x14
0x0C/0x1C/…
0x1F
0x14
0x0C/0x1C/…
0x1F
0x18
0x0C/0x1C/…
0x1F or 0x002
0x18
0x0C/0x1C/…
0x1F or 0x001
0x18
0x0E/0x1E/…
0x1F
0x18
0x0E/0x1E/…
0x1F
0x18
0x0E/0x1E/…
0x1F or 0x001
0x18
0x0E/0x1E/…
0x1F or 0x001
0x18
0x0E/0x1E/…
0x1F
0x18
0x0E/0x1E/…
0x1F or 0x001
The input termination can be changed to accommodate the application with little or no impact to ac performance.
The input capacitance can be set to 1.5 pF to achieve wider input bandwidth but results in slightly lower ac performance.
N/A means not applicable.
Rev. C | Page 40 of 97
Data Sheet
AD9680
The absolute maximum input swing allowed at the inputs of the
AD9680 is 4.3 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC.
VOLTAGE REFERENCE
A stable and accurate 1.0 V voltage reference is built into the
AD9680. This internal 1.0 V reference is used to set the fullscale input range of the ADC. The full-scale input range can
be adjusted via the ADC Function Register 0x025. For more
information on adjusting the input swing, see Table 36. Figure 131
shows the block diagram of the internal 1.0 V reference controls.
the reference voltage. For more information on adjusting the
full-scale level of the AD9680, refer to the Memory Map Register
Table section.
The use of an external reference may be necessary, in some
applications, to enhance the gain accuracy of the ADC or to
improve thermal drift characteristics. Figure 132 shows the
typical drift characteristics of the internal 1.0 V reference.
1.0010
1.0009
1.0008
1.0007
V_1P0 VOLTAGE (V)
Absolute Maximum Input Swing
VIN+A/
VIN+B
VIN–A/
VIN–B
ADC
CORE
FULL-SCALE
VOLTAGE
ADJUST
1.0004
1.0003
1.0002
1.0001
1.0000
V_1P0
0.9998
–50
25
90
Figure 132. Typical V_1P0 Drift
11752-031
V_1P0 PIN
CONTROL SPI
REGISTER
(0x025, 0x02,
AND 0x024)
Figure 131. Internal Reference Configuration and Controls
The SPI Register 0x024 enables the user to either use this internal
1.0 V reference, or to provide an external 1.0 V reference. When
using an external voltage reference, provide a 1.0 V reference.
The full-scale adjustment is made using the SPI, irrespective of
The external reference must be a stable 1.0 V reference. The
ADR130 is a good option for providing the 1.0 V reference.
Figure 133 shows how the ADR130 can be used to provide the
external 1.0 V reference to the AD9680. The grayed out areas
show unused blocks within the AD9680 while using the
ADR130 to provide the external reference.
INTERNAL
V_1P0
GENERATOR
ADR130
1
NC
2
GND SET 5
3
VIN
0.1µF
0
TEMPERATURE (°C)
11752-106
0.9999
INPUT FULL-SCALE
RANGE ADJUST
SPI REGISTER
(0x025, 0x02,
AND 0x024)
INPUT
1.0005
FULL-SCALE
VOLTAGE
ADJUST
NC 6
VOUT 4
V_1P0
0.1µF
FULL-SCALE
CONTROL
Figure 133. External Reference Using ADR130
Rev. C | Page 41 of 97
11752-032
INTERNAL
V_1P0
GENERATOR
1.0006
AD9680
Data Sheet
CLOCK INPUT CONSIDERATIONS
Input Clock Divider
For optimum performance, drive the AD9680 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled to the CLK+ and CLK− pins via a
transformer or clock drivers. These pins are biased internally
and require no additional biasing.
The AD9680 contains an input clock divider with the ability to
divide the Nyquist input clock by 1, 2, 4, and 8. The divider
ratios can be selected using Register 0x10B. This is shown in
Figure 137.
Figure 134 shows a preferred method for clocking the AD9680.
The low jitter clock source is converted from a single-ended
signal to a differential signal using an RF transformer.
0.1µF
1:1Z
CLK+
100Ω
CLK+
ADC
CLK–
0.1µF
CLK–
÷2
÷4
÷8
Figure 134. Transformer-Coupled Differential Clock
Another option is to ac couple a differential CML or LVDS
signal to the sample clock input pins, as shown in Figure 135
and Figure 136.
REG 0x10B
Figure 137. Clock Divider Circuit
The AD9680 clock divider can be synchronized using the
external SYSREF± input. A valid SYSREF± causes the clock
divider to reset to a programmable state. This synchronization
feature allows multiple devices to have their clock dividers
aligned to guarantee simultaneous input sampling. See the
Multichip Synchronization section for more information.
3.3V
71Ω
10pF
33Ω
33Ω
Z0 = 50Ω
0.1µF
ADC
Z0 = 50Ω
0.1µF
11752-036
CLK+
CLK–
Input Clock Divider ½ Period Delay Adjust
The input clock divider inside the AD9680 provides phase delay
in increments of ½ the input clock cycle. Register 0x10C can be
programmed to enable this delay independently for each channel.
Changing this register does not affect the stability of the
JESD204B link.
Figure 135. Differential CML Sample Clock
0.1µF
0.1µF
LVDS
DRIVER
100Ω
50Ω1
50Ω1
ADC
Clock Fine Delay Adjust
CLK–
CLK–
CLOCK INPUT
150Ω
CLK+
CLK+
0.1µF
RESISTORS ARE OPTIONAL.
11752-037
0.1µF
CLOCK INPUT
11752-038
50Ω
11752-035
CLOCK
INPUT
The maximum frequency at the CLK± inputs is 4 GHz. This is
the limit of the divider. In applications where the clock input is
a multiple of the sample clock, care must be taken to program
the appropriate divider ratio into the clock divider before applying
the clock signal. This ensures that the current transients during
device startup are controlled.
Figure 136. Differential LVDS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a 5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. In applications where the clock duty cycle cannot
be guaranteed to be 50%, a higher multiple frequency clock can be
supplied to the device. The AD9680 can be clocked at 2 GHz with
the internal clock divider set to 2. The output of the divider offers
a 50% duty cycle, high slew rate (fast edge) clock signal to the
internal ADC. See the Memory Map section for more details on
using this feature.
The AD9680 sampling edge instant can be adjusted by writing to
Register 0x117 and Register 0x118. Setting Bit 0 of Register 0x117
enables the feature, and Bits[7:0] of Register 0x118 set the value
of the delay. This value can be programmed individually for
each channel. The clock delay can be adjusted from −151.7 ps
to +150 ps in ~1.7 ps increments. The clock delay adjust takes
effect immediately when it is enabled via SPI writes. Enabling
the clock fine delay adjust in Register 0x117 causes a datapath
reset. However, the contents of Register 0x118 can be changed
without affecting the stability of the JESD204B link.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality
of the clock input. The degradation in SNR at a given input
frequency (fA) due only to aperture jitter (tJ) can be calculated by
SNR = 20 × log 10 (2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications.
Rev. C | Page 42 of 97
Data Sheet
AD9680
IF undersampling applications are particularly sensitive to jitter
(see Figure 138).
130
12.5fS
25fS
50fS
100fS
200fS
400fS
800fS
120
110
100
The AD9680 has a PDWN/STBY pin that can be used to
configure the device in power-down or standby mode. The
default operation is PDWN. The PDWN/STBY pin is a logic
high pin. When in power-down mode, the JESD204B link is
disrupted. The power-down option can also be set via
Register 0x03F and Register 0x040.
In standby mode, the JESD204B link is not disrupted and
transmits zeros for all converter samples. This can be changed
using Register 0x571, Bit 7 to select /K/ characters.
80
70
60
Temperature Diode
50
30
10
100
1000
10000
ANALOG INPUT FREQUENCY (MHz)
11752-039
40
Figure 138. Ideal SNR vs. Input Frequency and Jitter
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9680. Separate
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
If the clock is generated from another type of source (by gating,
dividing, or other methods), retime the clock by the original clock
at the last step. Refer to the AN-501 Application Note and the
AN-756 Application Note for more in-depth information about
jitter performance as it relates to ADCs.
Figure 139 shows the estimated SNR of the AD9680-1000 across
input frequency for different clock induced jitter values. The
SNR can be estimated by using the following equation:
 − SNR JITTER  
  − SNR ADC 


SNR (dBFS) = 10log 10 10  + 10 10  




70
The AD9680 contains a diode-based temperature sensor for
measuring the temperature of the die. This diode can output a
voltage and serve as a coarse temperature sensor to monitor the
internal die temperature.
The temperature diode voltage can be output to the FD_A pin
using the SPI. Use Register 0x028, Bit 0 to enable or disable the
diode. Register 0x028 is a local register. Channel A must be
selected in the device index register (0x008) to enable the
temperature diode readout. Configure the FD_A pin to output
the diode voltage by programming Register 0x040[2:0]. See
Table 36 for more information.
The voltage response of the temperature diode (SPIVDD =
1.8 V) is shown in Figure 140.
0.90
0.85
DIODE VOLTAGE (V)
0.80
0.75
0.70
0.65
65
–55 –45 –35 –25 –15 –5
5
15 25 35 45 55 65 75 85 95 105 115 125
TEMPERATURE (°C)
55
50
45
10
Figure 140. Temperature Diode Voltage vs. Temperature
25fs
50fs
75fs
100f s
125f s
150f s
175f s
200f s
100
1K
INPUT FREQUENCY (MHz)
10K
11752-526
SNR (dBFS)
0.60
60
Figure 139. Estimated SNR Degradation for the AD9680-1000 vs.
Input Frequency and RMS Jitter
Rev. C | Page 43 of 97
11752-353
SNR (dB)
90
Power-Down/Standby Mode
AD9680
Data Sheet
ADC OVERRANGE AND FAST DETECT
The operation of the upper threshold and lower threshold
registers, along with the dwell time registers, is shown in
Figure 141.
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit in the JESD204B outputs provides
information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input
signals can have significant slew rates, the latency of this
function is of major concern. Highly pipelined converters can
have significant latency. The AD9680 contains fast detect
circuitry for individual channels to monitor the threshold and
assert the FD_A and FD_B pins.
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located at Register 0x247 and Register 0x248. The selected
threshold register is compared with the signal magnitude at the
output of the ADC. The fast upper threshold detection has a
latency of 28 clock cycles (maximum). The approximate upper
threshold magnitude is defined by
Upper Threshold Magnitude (dBFS)
= 20 log (Threshold Magnitude/213)
ADC OVERRANGE
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x249 and Register 0x24A. The fast
detect lower threshold register is a 13-bit register that is compared
with the signal magnitude at the output of the ADC. This
comparison is subject to the ADC pipeline latency, but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be embedded within the JESD204B link as a control bit (when
CSB > 0). The latency of this overrange indicator matches the
sample latency.
The AD9680 also records any overrange condition in any of the
eight virtual converters. For more information on the virtual
converters, refer to Figure 146. The overrange status of each virtual
converter is registered as a sticky bit in Register 0x563. The
contents of Register 0x563 can be cleared using Register 0x562,
by toggling the bits corresponding to the virtual converter to set
and reset position.
Lower Threshold Magnitude (dBFS)
= 20 log (Threshold Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x247 and Register 0x248. To set a lower threshold
of −10 dBFS, write 0xA1D to Register 0x249 and Register 0x24A.
FAST THRESHOLD DETECTION (FD_A AND FD_B)
The FD bit is immediately set whenever the absolute value of
the input signal exceeds the programmable upper threshold
level. The FD bit is only cleared when the absolute value of the
input signal drops below the lower threshold level for greater
than the programmable dwell time. This feature provides
hysteresis and prevents the FD bit from excessively toggling.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x24B and Register 0x24C.
See the Memory Map section (Register 0x040, and Register 0x245
to Register 0x24C in Table 36) for more details.
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
DWELL TIME
FD_A OR FD_B
Figure 141. Threshold Settings for FD_A and FD_B Signals
Rev. C | Page 44 of 97
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
11752-040
MIDSCALE
LOWER THRESHOLD
Data Sheet
AD9680
SIGNAL MONITOR
The signal monitor block provides additional information about
the signal being digitized by the ADC. The signal monitor
computes the peak magnitude of the digitized signal. This
information can be used to drive an AGC loop to optimize the
range of the ADC in the presence of real-world signals.
The results of the signal monitor block can be obtained either
by reading back the internal values from the SPI port or by
embedding the signal monitoring information into the
JESD204B interface as special control bits. A global, 24-bit
programmable period controls the duration of the
measurement. Figure 142 shows the simplified block diagram
of the signal monitor block.
FROM
MEMORY
MAP
SIGNAL MONITOR
PERIOD REGISTER
(SMPR)
0x271, 0x272, 0x273
DOWN
COUNTER
IS
COUNT = 1?
FROM
INPUT
LOAD
LOAD
SIGNAL
MONITOR
HOLDING
REGISTER
TO SPORT OVER
JESD204B AND
MEMORY MAP
11752-087
CLEAR
COMPARE
A>B
Figure 142. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 of Register 0x270 in the signal monitor
control register. The 24-bit SMPR must be programmed before
activating this mode.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
decimated clock rate. The magnitude of the input signal is
compared with the value in the internal magnitude storage
register (not accessible to the user), and the greater of the two
is updated as the current peak level. The initial value of the
magnitude storage register is set to the current ADC input signal
magnitude. This comparison continues until the monitor period
timer reaches a count of 1.
LOAD
MAGNITUDE
STORAGE
REGISTER
converter output samples. The peak magnitude can be derived
by using the following equation:
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained previously,
continues.
Rev. C | Page 45 of 97
AD9680
Data Sheet
SPORT OVER JESD204B
is to be inserted (CS = 1), only the most significant control bit is
used (see Example Configuration 1 and Example Configuration 2
in Figure 143). To select the SPORT over JESD204B option,
program Register 0x559, Register 0x55A, and Register 0x58F.
See Table 36 for more information on setting these bits.
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bits[1:0]
of Register 0x279 and Bit 1 of Register 0x27A. Figure 143 shows
two different example configurations for the signal monitor
control bit locations inside the JESD204B samples. A maximum
of three control bits can be inserted into the JESD204B samples;
however, only one control bit is required for the signal monitor.
Control bits are inserted from MSB to LSB. If only one control bit
Figure 144 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 145 shows the SPORT over JESD204B signal monitor
data with a monitor period timer set to 80 samples.
16-BIT JESD204B SAMPLE SIZE (N' = 16)
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
1-BIT
CONTROL
BIT
(CS = 1)
15-BIT CONVERTER RESOLUTION (N = 15)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S[14]
X
S[13]
X
S[12]
X
S[11]
X
S[10]
X
S[9]
X
S[8]
X
S[7]
X
S[6]
X
S[5]
X
S[4]
X
S[3]
X
S[2]
X
S[1]
X
S[0]
X
CTRL
[BIT 2]
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
16-BIT JESD204B SAMPLE SIZE (N' = 16)
15
S[13]
X
14
S[12]
X
13
S[11]
X
12
S[10]
X
11
10
S[9]
X
9
S[8]
X
8
S[7]
X
7
S[6]
X
6
S[5]
X
5
S[4]
X
4
S[3]
X
S[2]
X
3
S[1]
X
2
1
0
S[0]
X
CTRL
[BIT 2]
X
TAIL
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
Figure 143. Signal Monitor Control Bit Locations
5-BIT SUB-FRAMES
5-BIT IDLE
SUB-FRAME
(OPTIONAL)
25-BIT
FRAME
IDLE
1
IDLE
1
IDLE
1
IDLE
1
IDLE
1
5-BIT IDENTIFIER START
0
SUB-FRAME
ID[3]
0
ID[2]
0
ID[1]
0
ID[0]
1
5-BIT DATA
MSB
SUB-FRAME
START
0
P[12]
P[11]
P[10]
P[9]
5-BIT DATA
SUB-FRAME
START
0
P[8]
P[7]
P[6]
P5]
5-BIT DATA
SUB-FRAME
START
0
P[4]
P[3]
P[2]
P1]
5-BIT DATA
LSB
SUB-FRAME
START
0
P[0]
0
0
0
P[] = PEAK MAGNITUDE VALUE
11752-089
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
Figure 144. SPORT over JESD204B Signal Monitor Frame Data
Rev. C | Page 46 of 97
11752-088
1
CONTROL
BIT
1 TAIL
(CS = 1)
BIT
14-BIT CONVERTER RESOLUTION (N = 14)
Data Sheet
AD9680
SMPR = 80 SAMPLES (0x271 = 0x50; 0x272 = 0x00; 0x273 = 0x00)
80 SAMPLE PERIOD
PAYLOAD #3
25-BIT FRAME (N)
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
PAYLOAD #3
25-BIT FRAME (N + 1)
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
Figure 145. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples
Rev. C | Page 47 of 97
11752-090
PAYLOAD #3
25-BIT FRAME (N + 2)
AD9680
Data Sheet
DIGITAL DOWNCONVERTER (DDC)
The AD9680 includes four digital downconverters (DDC 0 to
DDC 3) that provide filtering and reduce the output data rate.
This digital processing section includes an NCO, a half-band
decimating filter, an FIR filter, a gain stage, and a complex-real
conversion stage. Each of these processing blocks has control lines
that allow it to be independently enabled and disabled to provide
the desired processing function. The digital downconverter can
be configured to output either real data or complex output data.
The Chip Q ignore bit (Bit 5) in the chip application mode
register (Register 0x200) controls the chip output muxing of all
the DDC channels. When all DDC channels use real outputs,
this bit must be set high to ignore all DDC Q output ports.
When any of the DDC channels are set to use complex I/Q
outputs, the user must clear this bit to use both DDC Output
Port I and DDC Output Port Q. For more information, see
Figure 154.
The DDCs output a 16-bit stream. To enable this operation, the
converter number of bits, N, is set to a default value of 16, even
though the analog core only outputs 14 bits. In full bandwidth
operation, the ADC outputs are the 14-bit word followed by
two zeros, unless the tail bits are enabled.
DDC GENERAL DESCRIPTION
DDC I/Q INPUT SELECTION
Each DDC block contains the following signal processing stages.
The AD9680 has two ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real or complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (for example, DDC Input Port I = ADC
Channel A, and Input Port Q = ADC Channel A). For complex
signals, each DDC input port must select different ADC
channels (for example, DDC Input Port I = ADC Channel A,
and Input Port Q = ADC Channel B).
The inputs to each DDC are controlled by the DDC input
selection registers (Register 0x311, Register 0x331, Register 0x351,
and Register 0x371). See Table 36 for information on how to
configure the DDCs.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real or complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit (Bit 3) in the DDC control
registers (Register 0x310, Register 0x330, Register 0x350, and
Register 0x370).
The four DDC blocks are used to extract a portion of the full
digital spectrum captured by the ADC(s). They are intended for
IF sampling or oversampled baseband radios requiring wide
bandwidth input signals.
Frequency Translation Stage (Optional)
The frequency translation stage consists of a 12-bit complex NCO
and quadrature mixers that can be used for frequency translation
of both real or complex input signals. This stage shifts a portion
of the available digital spectrum down to baseband.
Filtering Stage
After shifting down to baseband, the filtering stage decimates
the frequency spectrum using a chain of up to four half-band
low-pass filters for rate conversion. The decimation process
lowers the output data rate, which in turn reduces the output
interface rate.
Gain Stage (Optional)
Due to losses associated with mixing a real input signal down to
baseband, the gain stage compensates by adding an additional
0 dB or 6 dB of gain.
Complex to Real Conversion Stage (Optional)
When real outputs are necessary, the complex to real conversion
stage converts the complex outputs back to real by performing
an fS/4 mixing operation plus a filter to remove the complex
component of the signal.
Figure 146 shows the detailed block diagram of the DDCs
implemented in the AD9680.
Rev. C | Page 48 of 97
Data Sheet
AD9680
GAIN = 0dB
OR 6dB
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
COMPLEX TO REAL
CONVERSION
(OPTIONAL)
HB1 FIR
DCM = 2
GAIN = 0dB
OR 6dB
ADC
SAMPLING
AT fS
GAIN = 0dB
OR 6dB
REAL/I
GAIN = 0dB
OR 6dB
REAL/Q Q
HB2 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB3 FIR
DCM = BYPASS OR 2
I
HB4 FIR
DCM = BYPASS OR 2
DDC 0
REAL/I
REAL/I
CONVERTER 0
Q CONVERTER 1
SYSREF±
Q CONVERTER 3
REAL/Q Q
ADC
SAMPLING
AT fS
HB1 FIR
DCM = 2
I
HB2 FIR
DCM = BYPASS OR 2
REAL/I
HB3 FIR
DCM = BYPASS OR 2
DDC 2
REAL/I
CONVERTER 4
OUTPUT INTERFACE
HB1 FIR
DCM = 2
REAL/I
CONVERTER 2
SYSREF±
NCO
+
MIXER
(OPTIONAL)
REAL/I
HB2 FIR
DCM = BYPASS OR 2
REAL/Q Q
HB3 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB4 FIR
DCM = BYPASS OR 2
I/Q CROSSBAR MUX
I
HB4 FIR
DCM = BYPASS OR 2
DDC 1
REAL/I
Q CONVERTER 5
SYSREF±
SYSREF
SYNCHRONIZATION
CONTROL CIRCUITS
HB1 FIR
DCM = 2
REAL/I
CONVERTER 6
Q CONVERTER 7
11752-041
REAL/Q Q
HB2 FIR
DCM = BYPASS OR 2
NCO
+
MIXER
(OPTIONAL)
HB3 FIR
DCM = BYPASS OR 2
I
HB4 FIR
DCM = BYPASS OR 2
DDC 3
REAL/I
SYSREF±
Figure 146. DDC Detailed Block Diagram
Figure 147 shows an example usage of one of the four DDC
blocks with a real input signal and four half-band filters (HB4,
HB3, HB2, and HB1). It shows both complex (decimate by 16)
and real (decimate by 8) output options.
the chip decimation ratio sample rate. Whenever the NCO
frequency is set or changed, the DDC soft reset must be issued.
If the DDC soft reset is not issued, the output may potentially
show amplitude variations.
When DDCs have different decimation ratios, the chip
decimation ratio (Register 0x201) must be set to the lowest
decimation ratio of all the DDC blocks. In this scenario,
samples of higher decimation ratio DDCs are repeated to match
Table 11, Table 12, Table 13, Table 14, and Table 15 show the
DDC samples when the chip decimation ratio is set to 1, 2, 4, 8,
or 16, respectively.
Rev. C | Page 49 of 97
AD9680
Data Sheet
ADC
ADC
SAMPLING
AT fS
REAL
REAL INPUT—SAMPLED AT fS
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
REAL
BANDWIDTH OF
INTEREST
fS/32
–fS/32
DC
–fS/16
fS/16
–fS/8
FREQUENCY TRANSLATION STAGE (OPTIONAL)
DIGITAL MIXER + NCO FOR fS/3 TUNING, THE FREQUENCY
TUNING WORD = ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
fS/8
fS/4
fS/3
fS/2
I
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
cos(ωt)
REAL
12-BIT
NCO
90°
0°
–sin(ωt)
Q
DIGITAL FILTER
RESPONSE
–fS/2
–fS/3
–fS/4
fS/32
–fS/32
DC
fS/16
–fS/16
–fS/8
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
fS/8
fS/4
fS/3
fS/2
FILTERING STAGE
I
HALFBAND
FILTER
Q
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
I
HB1 FIR
HB2 FIR
HB3 FIR
HB4 FIR
HB1 FIR
HB2 FIR
HB3 FIR
HB4 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
2
Q
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
COMPLEX (I/Q) OUTPUTS
GAIN STAGE (OPTIONAL)
DIGITAL FILTER
RESPONSE
I
GAIN STAGE (OPTIONAL)
Q
0dB OR 6dB GAIN
COMPLEX TO REAL
CONVERSION STAGE (OPTIONAL)
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
–fS/32
fS/32
DC
–fS/16
fS/16
–fS/8
I
REAL (I) OUTPUTS
+6dB
+6dB
fS/8
2
+6dB
2
+6dB
I
Q
–fS/32
fS/32
DC
fS/16
–fS/16
DOWNSAMPLE BY 2
I
DECIMATE BY 8
Q
DECIMATE BY 16
0dB OR 6dB GAIN
Q
COMPLEX REAL/I
TO
REAL
–fS/8
–fS/32
fS/32
DC
–fS/16
fS/16
fS/8
Figure 147. DDC Theory of Operation Example (Real Input—Decimate by 16)
Rev. C | Page 50 of 97
11752-042
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
Data Sheet
AD9680
Table 11. DDC Samples, Chip Decimation Ratio = 1
Real (I) Output (Complex to Real Enabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 1)
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N
N
N
N
N+1
N+1
N+1
N+1
N+2
N
N
N
N+3
N+1
N+1
N+1
N+4
N+2
N
N
N+5
N+3
N+1
N+1
N+6
N+2
N
N
N+7
N+3
N+1
N+1
N+8
N+4
N+2
N
N+9
N+5
N+3
N+1
N + 10
N+4
N+2
N
N + 11
N+5
N+3
N+1
N + 12
N+6
N+2
N
N + 13
N+7
N+3
N+1
N + 14
N+6
N+2
N
N + 15
N+7
N+3
N+1
N + 16
N+8
N+4
N+2
N + 17
N+9
N+5
N+3
N + 18
N+8
N+4
N+2
N + 19
N+9
N+5
N+3
N + 20
N + 10
N+4
N+2
N + 21
N + 11
N+5
N+3
N + 22
N + 10
N+4
N+2
N + 23
N + 11
N+5
N+3
N + 24
N + 12
N+6
N+2
N + 25
N + 13
N+7
N+3
N + 26
N + 12
N+6
N+2
N + 27
N + 13
N+7
N+3
N + 28
N + 14
N+6
N+2
N + 29
N + 15
N+7
N+3
N + 30
N + 14
N+6
N+2
N + 31
N + 15
N+7
N+3
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N+1
N+1
N+1
N+1
N
N
N
N
N+1
N+1
N+1
N+1
N+2
N
N
N
N+3
N+1
N+1
N+1
N+2
N
N
N
N+3
N+1
N+1
N+1
N+4
N+2
N
N
N+5
N+3
N+1
N+1
N+4
N+2
N
N
N+5
N+3
N+1
N+1
N+6
N+2
N
N
N+7
N+3
N+1
N+1
N+6
N+2
N
N
N+7
N+3
N+1
N+1
N+8
N+4
N+2
N
N+9
N+5
N+3
N+1
N+8
N+4
N+2
N
N+9
N+5
N+3
N+1
N + 10
N+4
N+2
N
N + 11
N+5
N+3
N+1
N + 10
N+4
N+2
N
N + 11
N+5
N+3
N+1
N + 12
N+6
N+2
N
N + 13
N+7
N+3
N+1
N + 12
N+6
N+2
N
N + 13
N+7
N+3
N+1
N + 14
N+6
N+2
N
N + 15
N+7
N+3
N+1
N + 14
N+6
N+2
N
N + 15
N+7
N+3
N+1
DCM means decimation.
Rev. C | Page 51 of 97
AD9680
Data Sheet
Table 12. DDC Samples, Chip Decimation Ratio = 2
Real (I) Output (Complex to Real Enabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
N
N
N
N+1
N+1
N+1
N
N
N+2
N+1
N+1
N+3
N
+
2
N
N+4
N
+
3
N+1
N+5
N+2
N
N+6
N+3
N+1
N+7
N+4
N+2
N+8
N+5
N+3
N+9
N+4
N+2
N + 10
N+5
N+3
N + 11
N+6
N+2
N + 12
N+7
N+3
N + 13
N+6
N+2
N + 14
N+7
N+3
N + 15
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR +
HB3 FIR +
HB3 FIR +
HB2 FIR +
HB2 FIR +
HB2 FIR +
HB1 FIR
HB1 FIR
HB1 FIR
HB1 FIR
(DCM1 = 2)
(DCM1 = 4)
(DCM1 = 8)
(DCM1 = 16)
N
N
N
N
N+1
N+1
N+1
N+1
N
N
N
N+2
N+1
N+1
N+1
N+3
N
+
2
N
N
N+4
N
+
3
N
+
1
N+1
N+5
N+2
N
N
N+6
N+3
N+1
N+1
N+7
N+4
N+2
N
N+8
N+5
N+3
N+1
N+9
N+4
N+2
N
N + 10
N+5
N+3
N+1
N + 11
N+6
N+2
N
N + 12
N+7
N+3
N+1
N + 13
N+6
N+2
N
N + 14
N+7
N+3
N+1
N + 15
DCM means decimation.
Table 13. DDC Samples, Chip Decimation Ratio = 4
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR +
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
HB1 FIR (DCM1 = 4)
(DCM1 = 8)
N
N
N+1
N+1
N
N+2
N+1
N+3
N+2
N+4
N+3
N+5
N+2
N+6
N+3
N+7
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR +
HB2 FIR + HB1 FIR
HB3 FIR + HB2 FIR +
HB2 FIR + HB1 FIR
(DCM1 = 4)
HB1 FIR (DCM1 = 8)
(DCM1 = 16)
N
N
N
N+1
N+1
N+1
N
N
N+2
N+1
N+1
N+3
N+2
N
N+4
N
+
3
N+1
N+5
N
+
2
N
N+6
N
+
3
N+1
N+7
DCM means decimation.
Table 14. DDC Samples, Chip Decimation Ratio = 8
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 8)
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB3 FIR + HB2 FIR + HB1 FIR
HB4 FIR + HB3 FIR + HB2 FIR +
(DCM1 = 8)
HB1 FIR (DCM1 = 16)
N
N
N+1
N+1
N
N+2
N+1
N+3
N+2
N+4
N+3
N+5
N+2
N+6
N+3
N+7
DCM means decimation.
Rev. C | Page 52 of 97
Data Sheet
AD9680
Table 15. DDC Samples, Chip Decimation Ratio = 16
Real (I) Output (Complex to Real Enabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
Not applicable
Not applicable
Not applicable
Not applicable
1
Complex (I/Q) Outputs (Complex to Real Disabled)
HB4 FIR + HB3 FIR + HB2 FIR + HB1 FIR (DCM1 = 16)
N
N+1
N+2
N+3
DCM means decimation.
If the chip decimation ratio is set to decimate by 4, DDC 0 is set to use HB2 + HB1 filters (complex outputs decimate by 4), and DDC 1 is
set to use HB4 + HB3 + HB2 + HB1 filters (real outputs decimate by 8), then DDC 1 repeats its output data two times for every one
DDC 0 output. The resulting output samples are shown in Table 16.
Table 16. DDC Output Samples when Chip DCM1 = 4, DDC 0 DCM1 = 4 (Complex), and DDC 1 DCM1 = 8 (Real)
DDC Input Samples
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
N + 11
N + 12
N + 13
N + 14
N + 15
1
Output Port I
I0 [N]
DDC 0
Output Port Q
Q0 [N]
Output Port I
I1 [N]
DDC 1
Output Port Q
Not applicable
I0 [N + 1]
Q0 [N + 1]
I1 [N + 1]
Not applicable
I0 [N + 2]
Q0 [N + 2]
I1 [N]
Not applicable
I0 [N + 3]
Q0 [N + 3]
I1 [N + 1]
Not applicable
DCM means decimation.
Rev. C | Page 53 of 97
AD9680
Data Sheet
FREQUENCY TRANSLATION
FREQUENCY TRANSLATION GENERAL DESCRIPTION
Variable IF Mode
Frequency translation is accomplished by using a 12-bit
complex NCO along with a digital quadrature mixer. The
frequency translation translates either a real or complex input
signal from an intermediate frequency (IF) to a baseband
complex digital output (carrier frequency = 0 Hz).
NCO and mixers are enabled. NCO output frequency can be
used to digitally tune the IF frequency.
0 Hz IF (ZIF) Mode
Mixers are bypassed and the NCO is disabled.
fS/4 Hz IF Mode
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4] of
the DDC control registers (Register 0x310, Register 0x330,
Register 0x350, and Register 0x370). These IF modes are
Test Mode
Input samples are forced to 0.999 to positive full scale. NCO is
enabled. This test mode allows the NCOs to directly drive the
decimation filters.
Variable IF mode
0 Hz IF (ZIF) mode
fS/4 Hz IF mode
Test mode
Figure 148 and Figure 149 show examples of the frequency
translation stage for both real and complex inputs.
NCO FREQUENCY TUNING WORD (FTW) SELECTION
12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
I
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT fS
REAL
ADC
SAMPLING
AT fS
cos(ωt)
REAL
12-BIT
NCO
90°
0°
COMPLEX
–sin(ωt)
Q
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
–fS/8
fS/32
–fS/32
DC
–fS/16
fS/16
fS/8
fS/4
fS/3
fS/2
–6dB LOSS DUE TO
NCO + MIXER
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
POSITIVE FTW VALUES
–fS/32
DC
fS/32
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = –1365 (0xAAB)
–fS/32
NEGATIVE FTW VALUES
DC
fS/32
Figure 148. DDC NCO Frequency Tuning Word Selection—Real Inputs
Rev. C | Page 54 of 97
11752-043
•
•
•
•
Mixers and NCO are enabled in special down mixing by fS/4
mode to save power.
Data Sheet
AD9680
NCO FREQUENCY TUNING WORD (FTW) SELECTION
12-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
QUADRATURE ANALOG MIXER +
2 ADCs + QUADRATURE DIGITAL REAL
MIXER + NCO
COMPLEX INPUT—SAMPLED AT fS
QUADRATURE MIXER
ADC
SAMPLING
AT fS
I
+
I
I
Q
Q
90°
PHASE
12-BIT
NCO
90°
0°
Q
Q
ADC
SAMPLING
AT fS
Q
Q
I
I
–
–sin(ωt)
I
I
+
COMPLEX
Q
+
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–fS/3
–fS/4
–fS/32
fS/32
fS/16
–fS/16
DC
–fS/8
fS/8
fS/4
fS/3
fS/2
12-BIT NCO FTW =
ROUND ((fS/3)/fS × 4096) = +1365 (0x555)
POSITIVE FTW VALUES
–fS/32
fS/32
11752-044
–fS/2
DC
Figure 149. DDC NCO Frequency Tuning Word Selection—Complex Inputs
DDC NCO PLUS MIXER LOSS AND SFDR
Setting Up the NCO FTW and POW
When mixing a real input signal down to baseband, 6 dB of loss
is introduced in the signal due to filtering of the negative image.
An additional 0.05 dB of loss is introduced by the NCO. The
total loss of a real input signal mixed down to baseband is 6.05 dB.
For this reason, it is recommended that the user compensate for
this loss by enabling the additional 6 dB of gain in the gain stage
of the DDC to recenter the dynamic range of the signal within
the full scale of the output bits.
The NCO frequency value is given by the 12-bit twos
complement number entered in the NCO FTW. Frequencies
between −fS/2 and fS/2 (fS/2 excluded) are represented using the
following frequency words:
When mixing a complex input signal down to baseband, the
maximum value each I/Q sample can reach is 1.414 × full scale
after it passes through the complex mixer. To avoid overrange
of the I/Q samples and to keep the data bitwidths aligned with
real mixing, 3.06 dB of loss (0.707 × full scale) is introduced in
the mixer for complex signals. An additional 0.05 dB of loss is
introduced by the NCO. The total loss of a complex input signal
mixed down to baseband is −3.11 dB.
The worst case spurious signal from the NCO is greater than
102 dBc SFDR for all output frequencies.
NUMERICALLY CONTROLLED OSCILLATOR
The AD9680 has a 12-bit NCO for each DDC that enables the
frequency translation process. The NCO allows the input
spectrum to be tuned to dc, where it can be effectively filtered
by the subsequent filter blocks to prevent aliasing. The NCO
can be set up by providing a frequency tuning word (FTW) and
a phase offset word (POW).
•
•
•
0x800 represents a frequency of –fS/2.
0x000 represents dc (frequency is 0 Hz).
0x7FF represents a frequency of +fS/2 – fS/212.
The NCO frequency tuning word can be calculated using the
following equation:
 Mod( fC , f S ) 

NCO _ FTW = round 212

fS


where:
NCO_FTW is a 12-bit twos complement number representing
the NCO FTW.
fS is the AD9680 sampling frequency (clock rate) in Hz.
fC is the desired carrier frequency in Hz.
Mod( ) is a remainder function. For example, Mod(110,100) =
10, and for negative numbers, Mod(–32, 10) = –2.
round( ) is a rounding function. For example, round(3.6) = 4,
and for negative numbers, round(–3.4)= –3.
Note that this equation applies to the aliasing of signals in the
digital domain (that is, aliasing introduced when digitizing
analog signals).
Rev. C | Page 55 of 97
AD9680
Data Sheet
For example, if the ADC sampling frequency (fS) is 1250 MSPS
and the carrier frequency (fC) is 416.667 MHz,
 Mod(416.667,1250 
NCO _ FTW = round 212
 = 1365 MHz
1250


Two methods can be used to synchronize multiple PAWs within
the chip:
•
This, in turn, converts to 0x555 in the 12-bit twos complement
representation for NCO_FTW. The actual carrier frequency can
be calculated based on the following equation:
fC − actual =
NCO _ FTW × f S
= 416.56 MHz
212
•
A 12-bit POW is available for each NCO to create a known phase
relationship between multiple AD9680 chips or individual DDC
channels inside one AD9680.
The following procedure must be followed to update the FTW
and/or POW registers to ensure proper operation of the NCO:
•
•
•
Write to the FTW registers for all the DDCs.
Write to the POW registers for all the DDCs.
Synchronize the NCOs either through the DDC soft reset
bit accessible through the SPI, or through the assertion of
the SYSREF± pin.
Note that the NCOs must be synchronized either through SPI
or through the SYSREF± pin after all writes to the FTW or POW
registers have completed. This synchronization is necessary to
ensure the proper operation of the NCO.
NCO Synchronization
Each NCO contains a separate phase accumulator word (PAW)
that determines the instantaneous phase of the NCO. The initial
reset value of each PAW is determined by the POW described
in the Setting Up the NCO FTW and POW section. The phase
increment value of each PAW is determined by the FTW.
Using the SPI. The DDC NCO soft reset bit in the DDC
synchronization control register (Register 0x300, Bit 4)
can be used to reset all the PAWs in the chip. This is
accomplished by toggling the DDC NCO soft reset bit.
This method can only be used to synchronize DDC
channels within the same AD9680 chip.
Using the SYSREF± pin. When the SYSREF± pin is enabled
in the SYSREF± control registers (Register 0x120 and
Register 0x121), and the DDC synchronization is enabled
in Bits[1:0] in the DDC synchronization control register
(Register 0x300), any subsequent SYSREF± event resets all
the PAWs in the chip. This method can be used to synchronize
DDC channels within the same AD9680 chip, or DDC
channels within separate AD9680 chips.
Mixer
The NCO is accompanied by a mixer, whose operation is
similar to an analog quadrature mixer. The mixer performs the
downconversion of input signals (real or complex) by using the
NCO frequency as a local oscillator. For real input signals, this
mixer performs a real mixer operation (with two multipliers).
For complex input signals, the mixer performs a complex mixer
operation (with four multipliers and two adders). The mixer
adjusts its operation based on the input signal (real or complex)
provided to each individual channel. The selection of real or
complex inputs can be controlled individually for each DDC
block by using Bit 7 of the DDC control register (Register 0x310,
Register 0x330, Register 0x350, and Register 0x370).
Rev. C | Page 56 of 97
Data Sheet
AD9680
FIR FILTERS
FIR FILTERS GENERAL DESCRIPTION
There are four sets of decimate-by-2, low-pass, half-band, finite
impulse response (FIR) filters (HB1 FIR, HB2 FIR, HB3 FIR,
and HB4 FIR, shown in Figure 146). These filters follow the
frequency translation stage. After the carrier of interest is tuned
down to dc (carrier frequency = 0 Hz), these filters efficiently lower
the sample rate while providing sufficient alias rejection from
unwanted adjacent carriers around the bandwidth of interest.
HB1 FIR is always enabled and cannot be bypassed. The HB2,
HB3, and HB4 FIR filters are optional and can be bypassed for
higher output sample rates.
Table 17 shows the different bandwidth options by including
different half-band filters. In all cases, the DDC filtering stage of
the AD9680 provides less than −0.001 dB of pass-band ripple
and >100 dB of stop-band alias rejection.
Table 18 shows the amount of stop-band alias rejection for
multiple pass-band ripple/cutoff points. The decimation ratio
of the filtering stage of each DDC can be controlled individually
through Bits[1:0] of the DDC control registers (0x310, 0x330,
0x350, and 0x370).
Table 17. DDC Filter Characteristics
ADC
Sample
Rate
(MSPS)
1250
1000
820
500
1
Half Band
Filter
Selection
HB1
Real Output
Output
Sample
Decimation Rate
Ratio
(MSPS)
1
1250
HB1 + HB2
2
625
HB1 + HB2 +
HB3
HB1 + HB2 +
HB3 + HB4
HB1
4
312.5
8
156.25
1
1000
HB1 + HB2
2
500
HB1 + HB2 +
HB3
HB1 + HB2 +
HB3 + HB4
HB1
4
250
8
125
1
820
HB1 + HB2
2
410
HB1 + HB2 +
HB3
HB1 + HB2 +
HB3 + HB4
HB1
4
205
8
102.5
1
500
HB1 + HB2
2
250
HB1 + HB2 +
HB3
HB1 + HB2 +
HB3 + HB4
4
125
8
62.5
Complex (I/Q) Output
Output
Sample
Decimation Rate
Ratio
(MSPS)
2
625 (I) +
625 (Q)
4
312.5 (I) +
312.5 (Q)
8
156.25 (I) +
156.25 (Q)
16
78.125 (I) +
78.125 (Q)
2
500 (I) +
500 (Q)
4
250 (I) +
250 (Q)
8
125 (I) +
125 (Q)
16
62.5 (I) +
62.5 (Q)
2
410 (I) +
410 (Q)
4
205 (I) +
205 (Q)
8
102.5 (I) +
102.5 (Q)
16
51.25 (I) +
51.25 (Q)
2
250 (I) +
250 (Q)
4
125 (I) +
125 (Q)
8
62.5 (I) +
62.5 (Q)
16
31.25 (I) +
31.25 (Q)
Ideal SNR improvement due to oversampling and filtering = 10log(bandwidth/(fS/2)).
Rev. C | Page 57 of 97
Alias
Protected
Bandwidth
(MHz)
481.25
Ideal SNR
Improvement
(dB)1
1
240.62
4
120.31
7
60.15
10
385.0
1
192.5
4
96.3
7
48.1
10
315.7
1
157.8
4
78.9
7
39.4
10
192.5
1
96.3
4
48.1
7
24.1
10
PassBand
Ripple
(dB)
<−0.001
Alias
Rejection
(dB)
>100
AD9680
Data Sheet
Table 18. DDC Filter Alias Rejection
Alias
Rejection (dB)
>100
90
85
63.3
25
19.3
10.7
1
Pass-Band Ripple/
Cutoff Point (dB)
<−0.001
<−0.001
<−0.001
<−0.006
−0.5
−1.0
−3.0
Alias Protected Bandwidth for
Complex (I/Q) Outputs1
<77% × fOUT
<77.4% × fOUT
<77.8% × fOUT
<80% × fOUT
88.8% × fOUT
91.2% × fOUT
96% × fOUT
Alias Protected Bandwidth for
Real (I) Outputs1
<38.5% × fOUT
<38.7% × fOUT
<38.9% × fOUT
<40% × fOUT
44.4% × fOUT
45.6% × fOUT
48% × fOUT
fOUT is the ADC input sample rate fS/DDC decimation ratio.
HALF-BAND FILTERS
HB3 Filter
The AD9680 offers four half-band filters to enable digital signal
processing of the ADC converted data. These half-band filters
are bypassable and can be individually selected.
The second decimate-by-2, half-band, low-pass, FIR filter (HB3)
uses an 11-tap, symmetrical, fixed coefficient filter implementation,
optimized for low power consumption. The HB3 filter is only used
when complex outputs (decimate by 8 or 16) or real outputs
(decimate by 4 or 8) are enabled; otherwise, the filter is bypassed.
Table 20 and Figure 151 show the coefficients and response of
the HB3 filter.
The first decimate-by-2, half-band, low-pass FIR filter (HB4) uses
an 11-tap, symmetrical, fixed-coefficient filter implementation,
optimized for low power consumption. The HB4 filter is only used
when complex outputs (decimate by 16) or real outputs (decimate
by 8) are enabled; otherwise, the filter is bypassed. Table 19 and
Figure 150 show the coefficients and response of the HB4 filter.
Table 19. HB4 Filter Coefficients
Normalized
Coefficient
0.006042
0
−0.049316
0
0.293273
0.500000
Decimal Coefficient
(15-Bit)
99
0
−808
0
4805
8192
0
–20
–40
Normalized
Coefficient
0.006554
0
−0.050819
0
0.294266
0.500000
Decimal Coefficient
(18-Bit)
859
0
−6661
0
38,570
65,536
0
–20
–40
–60
–80
–60
–100
–80
–120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
–100
Figure 151. HB3 Filter Response
–120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
11752-045
MAGNITUDE (dB)
HB3 Coefficient
Number
C1, C11
C2, C10
C3, C9
C4, C8
C5, C7
C6
MAGNITUDE (dB)
HB4 Coefficient
Number
C1, C11
C2, C10
C3, C9
C4, C8
C5, C7
C6
Table 20. HB3 Filter Coefficients
Figure 150. HB4 Filter Response
Rev. C | Page 58 of 97
11752-046
HB4 Filter
Data Sheet
AD9680
HB2 Filter
0
Normalized
Coefficient
0.000614
0
−0.005066
0
0.022179
0
−0.073517
0
0.305786
0.500000
Decimal Coefficient
(19-Bit)
161
0
−1328
0
5814
0
−19,272
0
80,160
131,072
0
MAGNITUDE (dB)
–20
–40
–60
–80
–100
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
11752-047
–120
Figure 152. HB2 Filter Response
HB1 Filter
The fourth and final decimate-by-2, half-band, low-pass FIR
filter (HB1) uses a 55-tap, symmetrical, fixed coefficient filter
implementation, optimized for low power consumption. The
HB1 filter is always enabled and cannot be bypassed. Table 22
and Figure 153 show the coefficients and response of the HB1
filter.
–60
–80
–100
Table 21. HB2 Filter Coefficients
HB2 Coefficient
Number
C1, C19
C2, C18
C3, C17
C4, C16
C5, C15
C6, C14
C7, C13
C8, C12
C9, C11
C10
–40
–120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
NORMALIZED FREQUENCY (× π RAD/SAMPLE)
11752-048
Table 21 and Figure 152 show the coefficients and response of
the HB2 filter.
–20
MAGNITUDE (dB)
The third decimate-by-2, half-band, low-pass FIR filter (HB2)
uses a 19-tap, symmetrical, fixed coefficient filter implementation
that is optimized for low power consumption. The HB2 filter is
only used when complex outputs (decimate by 4, 8, or 16) or
real outputs (decimate by 2, 4, or 8) are enabled; otherwise, the
filter is bypassed.
Figure 153. HB1 Filter Response
Table 22. HB1 Filter Coefficients
HB1 Coefficient
Number
C1, C55
C2, C54
C3, C53
C4, C52
C5, C51
C6, C50
C7, C49
C8, C48
C9, C47
C10, C46
C11, C45
C12, C44
C13, C43
C14, C42
C15, C41
C16, C40
C17, C39
C18, C38
C19, C37
C20, C36
C21, C35
C22, C34
C23, C33
C24, C32
C25, C31
C26, C30
C27, C29
C28
Rev. C | Page 59 of 97
Normalized
Coefficient
−0.000023
0
0.000097
0
−0.000288
0
0.000696
0
−0.0014725
0
0.002827
0
−0.005039
0
0.008491
0
−0.013717
0
0.021591
0
−0.033833
0
0.054806
0
−0.100557
0
0.316421
0.500000
Decimal Coefficient
(21-Bit)
−24
0
102
0
−302
0
730
0
−1544
0
2964
0
−5284
0
8903
0
−14,383
0
22,640
0
−35,476
0
57,468
0
−105,442
0
331,792
524,288
AD9680
Data Sheet
DDC GAIN STAGE
DDC COMPLEX TO REAL CONVERSION
Each DDC contains an independently controlled gain stage.
The gain is selectable as either 0 dB or 6 dB. When mixing a real
input signal down to baseband, it is recommended that the user
enable the 6 dB of gain to recenter the dynamic range of the
signal within the full scale of the output bits.
Each DDC contains an independently controlled complex to
real conversion block. The complex to real conversion block
reuses the last filter (HB1 FIR) in the filtering stage, along with
an fS/4 complex mixer to upconvert the signal.
After up converting the signal, the Q portion of the complex
mixer is no longer needed and is dropped.
When mixing a complex input signal down to baseband, the
mixer has already recentered the dynamic range of the signal
within the full scale of the output bits and no additional gain is
necessary. However, the optional 6 dB gain can be used to
compensate for low signal strengths. The downsample by 2
portion of the HB1 FIR filter is bypassed when using the
complex to real conversion stage (see Figure 154).
HB1 FIR
Figure 154 shows a simplified block diagram of the complex to
real conversion.
GAIN STAGE
COMPLEX TO
REAL ENABLE
LOW-PASS
FILTER
I
2
0dB
OR
6dB
I
0 I/REAL
1
COMPLEX TO REAL CONVERSION
0dB
OR
6dB
I
cos(ωt)
+
REAL
90°
fS/4
0°
–
sin(ωt)
LOW-PASS
FILTER
2
Q
0dB
OR
6dB
Q
Q
11752-049
Q
0dB
OR
6dB
HB1 FIR
Figure 154. Complex to Real Conversion Block
Rev. C | Page 60 of 97
Data Sheet
AD9680
DDC EXAMPLE CONFIGURATIONS
Table 23 describes the register settings for multiple DDC example configurations.
Table 23. DDC Example Configurations
Chip
Application
Layer
One DDC
Chip
Decimation
Ratio
2
DDC
Input
Type
Complex
DDC
Output
Type
Complex
Bandwidth
per DDC1
38.5% × fS
No. of Virtual
Converters
Required
2
Two DDCs
4
Complex
Complex
19.25% × fS
4
Two DDCs
4
Complex
Real
9.63% × fS
2
Two DDCs
4
Real
Real
9.63% × fS
2
Two DDCs
4
Real
Complex
19.25% × fS
4
Rev. C | Page 61 of 97
Register Settings2
Register 0x200 = 0x01 (one DDC; I/Q selected)
Register 0x201 = 0x01 (chip decimate by 2)
Register 0x310 = 0x83 (complex mixer; 0 dB gain; variable IF;
complex outputs; HB1 filter)
Register 0x311 = 0x04 (DDC I input = ADC Channel A;
DDC Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x200 = 0x02 (two DDCs; I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x80 (complex mixer; 0 dB
gain; variable IF; complex outputs; HB2 + HB1 filters)
Register 0x311, Register 0x331 = 0x04 (DDC I input =
ADC Channel A; DDC Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x200 = 0x22 (two DDCs; I only selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x89 (complex mixer; 0 dB
gain; variable IF; real output; HB3 + HB2 + HB1 filters)
Register 0x311, Register 0x331 = 0x04 (DDC I Input = ADC
Channel A; DDC Q Input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x200 = 0x22 (two DDCs; I only selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x49 (real mixer; 6 dB gain;
variable IF; real output; HB3 + HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;
DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x200 = 0x02 (two DDCs; I/Q selected)
Register 0x201 = 0x02 (chip decimate by 4)
Register 0x310, Register 0x330 = 0x40 (real mixer; 6 dB gain;
variable IF; complex output; HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;
DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
AD9680
Data Sheet
Chip
Application
Layer
Two DDCs
Chip
Decimation
Ratio
8
DDC
Input
Type
Real
DDC
Output
Type
Real
Bandwidth
per DDC1
4.81% × fS
No. of Virtual
Converters
Required
2
Four DDCs
8
Real
Complex
9.63% × fS
8
Four DDCs
8
Real
Real
4.81% × fS
4
Rev. C | Page 62 of 97
Register Settings2
Register 0x200 = 0x22 (two DDCs; I only selected)
Register 0x201 = 0x03 (chip decimate by 8)
Register 0x310, Register 0x330 = 0x4A (real mixer; 6 dB gain;
variable IF; real output; HB4 + HB3 + HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x05 (DDC 1 I input = ADC Channel B;
DDC 1 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x200 = 0x03 (four DDCs; I/Q selected)
Register 0x201 = 0x03 (chip decimate by 8)
Register 0x310, Register 0x330, Register 0x350, Register 0x370 =
0x41 (real mixer; 6 dB gain; variable IF; complex output;
HB3+HB2+HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A;
DDC 1 Q input = ADC Channel A)
Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B;
DDC 2 Q input = ADC Channel B)
Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B;
DDC 3 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x354, Register 0x355, Register 0x360, Register 0x361 =
FTW and POW set as required by application for DDC 2
Register 0x374, Register 0x375, Register 0x380, Register 0x381 =
FTW and POW set as required by application for DDC 3
Register 0x200 = 0x23 (four DDCs; I only selected)
Register 0x201 = 0x03 (chip decimate by 8)
Register 0x310, Register 0x330, Register 0x350, Register 0x370 =
0x4A (real mixer; 6 dB gain; variable IF; real output; HB4 +
HB3 + HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A;
DDC 1 Q input = ADC Channel A)
Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B;
DDC 2 Q input = ADC Channel B)
Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B;
DDC 3 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x354, Register 0x355, Register 0x360, Register 0x361 =
FTW and POW set as required by application for DDC 2
Register 0x374, Register 0x375, Register 0x380, Register 0x381 =
FTW and POW set as required by application for DDC 3
Data Sheet
Chip
Application
Layer
Four DDCs
1
2
Chip
Decimation
Ratio
16
AD9680
DDC
Input
Type
Real
DDC
Output
Type
Complex
Bandwidth
per DDC1
4.81% × fS
No. of Virtual
Converters
Required
8
Register Settings2
Register 0x200 = 0x03 (four DDCs; I/Q selected)
Register 0x201 = 0x04 (chip decimate by 16)
Register 0x310, Register 0x330, Register 0x350, Register 0x370 =
0x42 (real mixer; 6 dB gain; variable IF; complex output;
HB4 + HB3 + HB2 + HB1 filters)
Register 0x311 = 0x00 (DDC 0 I input = ADC Channel A;
DDC 0 Q input = ADC Channel A)
Register 0x331 = 0x00 (DDC 1 I input = ADC Channel A;
DDC 1 Q input = ADC Channel A)
Register 0x351 = 0x05 (DDC 2 I input = ADC Channel B;
DDC 2 Q input = ADC Channel B)
Register 0x371 = 0x05 (DDC 3 I input = ADC Channel B;
DDC 3 Q input = ADC Channel B)
Register 0x314, Register 0x315, Register 0x320, Register 0x321 =
FTW and POW set as required by application for DDC 0
Register 0x334, Register 0x335, Register 0x340, Register 0x341 =
FTW and POW set as required by application for DDC 1
Register 0x354, Register 0x355, Register 0x360, Register 0x361 =
FTW and POW set as required by application for DDC 2
Register 0x374, Register 0x375, Register 0x380, Register 0x381 =
FTW and POW set as required by application for DDC 3
fS is the ADC sample rate. Bandwidths listed are <−0.001 dB of pass-band ripple and >100 dB of stop-band alias rejection.
The NCOs must be synchronized either through the SPI or through the SYSREF± pin after all writes to the FTW or POW registers have completed, to ensure the proper
operation of the NCO. See the NCO Synchronization section for more information.
Rev. C | Page 63 of 97
AD9680
Data Sheet
DIGITAL OUTPUTS
INTRODUCTION TO THE JESD204B INTERFACE
•
The AD9680 digital outputs are designed to the JEDEC standard
JESD204B, serial interface for data converters. JESD204B is a
protocol to link the AD9680 to a digital processing device over
a serial interface with lane rates of up to 12.5 Gbps. The benefits
of the JESD204B interface over LVDS include a reduction in
required board area for data interface routing, and an ability to
enable smaller packages for converter and logic devices.
JESD204B OVERVIEW
•
•
•
K is the number of frames per multiframe
(AD9680 value = 4, 8, 12, 16, 20, 24, 28, or 32 )
S is the samples transmitted/single converter/frame cycle
(AD9680 value = set automatically based on L, M, F, and N΄)
HD is the high density mode (AD9680 = set automatically
based on L, M, F, and N΄)
CF is the number of control words/frame clock cycle/
converter device (AD9680 value = 0)
The JESD204B data transmit block assembles the parallel data
from the ADC into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of special control
characters during the initial establishment of the link. Additional
control characters are embedded in the data stream to maintain
synchronization thereafter. A JESD204B receiver is required to
complete the serial link. For additional details on the JESD204B
interface, refer to the JESD204B standard.
Figure 155 shows a simplified block diagram of the AD9680
JESD204B link. By default, the AD9680 is configured to use
two converters and four lanes. Converter A data is output to
SERDOUT0± and/or SERDOUT1±, and Converter B is output
to SERDOUT2± and/or SERDOUT3±. The AD9680 allows
other configurations such as combining the outputs of both
converters onto a single lane, or changing the mapping of the
A and B digital output paths. These modes are set up via a quick
configuration register in the SPI register map, along with
additional customizable options.
The AD9680 JESD204B data transmit block maps up to two
physical ADCs or up to eight virtual converters (when DDCs
are enabled) over a link. A link can be configured to use one,
two, or four JESD204B lanes. The JESD204B specification refers
to a number of parameters to define the link, and these parameters
must match between the JESD204B transmitter (the AD9680
output) and the JESD204B receiver (the logic device input).
By default in the AD9680, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or a pseudorandom number
sequence. The tail bits can also be replaced with control bits
indicating overrange, SYSREF±, or fast detect output.
The JESD204B link is described according to the following
parameters:
The two resulting octets can be scrambled. Scrambling is
optional; however, it is recommended to avoid spectral peaks
when transmitting similar digital data patterns. The scrambler
uses a self-synchronizing, polynomial-based algorithm defined
by the equation 1 + x14 + x15. The descrambler in the receiver is
a self-synchronizing version of the scrambler polynomial.
•
•
•
•
•
L is the number of lanes/converter device (lanes/link)
(AD9680 value = 1, 2, or 4)
M is the number of converters/converter device (virtual
converters/link) (AD9680 value = 1, 2, 4, or 8)
F is the octets/frame (AD9680 value = 1, 2, 4, 8, or 16)
N΄ is the number of bits per sample (JESD204B word size)
(AD9680 value = 8 or 16)
N is the converter resolution (AD9680 value = 7 to 16)
CS is the number of control bits/sample
(AD9680 value = 0, 1, 2, or 3)
The two octets are then encoded with an 8-bit/10-bit encoder.
The 8-bit/10-bit encoder works by taking eight bits of data (an
octet) and encoding them into a 10-bit symbol. Figure 156
shows how the 14-bit data is taken from the ADC, how the tail
bits are added, how the two octets are scrambled, and how the
octets are encoded into two 10-bit symbols. Figure 156 illustrates
the default data format.
CONVERTER 0
CONVERTER A
INPUT
ADC
A
MUX/
FORMAT
(SPI
REG 0x561,
REG 0x564)
CONVERTER B
INPUT
JESD204B LINK
CONTROL
(L.M.F)
(SPI REG 0x570)
ADC
B
LANE MUX
AND MAPPING
(SPI
REG 0x5B0,
REG 0x5B2,
REG 0x5B3,
REG 0x5B5,
REG 0x5B6)
SERDOUT0–,
SERDOUT0+
SERDOUT1–,
SERDOUT1+
SERDOUT2–,
SERDOUT2+
SERDOUT3–,
SERDOUT3+
CONVERTER 1
11752-050
•
SYSREF±
SYNCINB±
Figure 155. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x200 = 0x00)
Rev. C | Page 64 of 97
Data Sheet
AD9680
JESD204B
INTERFACE
TEST PATTERN
(REG 0x573,
REG 0x551 TO
REG 0x558)
JESD204B
LONG TRANSPORT
TEST PATTERN
REG 0x571[5]
SERIALIZER
MSB A13
A12
A11
A10
A9
A8
A7
LSB A6
A5
A4
A3
A2
A1
A0
C2
T
MSB S7
S6
S5
S4
S3
S2
S1
LSB S0
S7
S6
S5
S4
S3
S2
S1
S0
8-BIT/10-BIT
ENCODER
a b
a b c d e f g h i j
SERDOUT0±
SERDOUT1±
i j a b
SYMBOL0
i j
SYMBOL1
a b c d e f g h i j
11752-051
TAIL BITS
0x571[6]
SCRAMBLER
1 + x14 + x15
(OPTIONAL)
OCTET 1
JESD204B SAMPLE
CONSTRUCTION
MSB A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
LSB A0
OCTET 1
OCTET 0
FRAME
CONSTRUCTION
OCTET 0
ADC TEST PATTERNS
(RE0x550,
REG 0x551 TO
REG 0x558)
ADC
JESD204B DATA
LINK LAYER TEST
PATTERNS
REG 0x574[2:0]
C2
CONTROL BITS C1
C0
Figure 156. ADC Output Data Path Showing Data Framing
TRANSPORT
LAYER
SAMPLE
CONSTRUCTION
FRAME
CONSTRUCTION
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER
CROSSBAR
MUX
SERIALIZER
Tx
OUTPUT
11752-052
PROCESSED
SAMPLES
FROM ADC
PHYSICAL
LAYER
DATA LINK
LAYER
SYSREF±
SYNCINB±
Figure 157. Data Flow
FUNCTIONAL OVERVIEW
Physical Layer
The block diagram in Figure 157 shows the flow of data through
the JESD204B hardware from the sample input to the physical
output. The processing can be divided into layers that are
derived from the open source initiative (OSI) model widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer,
and physical layer (serializer and output driver).
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data.
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. These octets are sent to the data link
layer. The transport layer mapping is controlled by rules derived
from the link parameters. Tail bits are added to fill gaps where
required. The following equation can be used to determine the
number of tail bits within a sample (JESD204B word):
T = N΄ – N – CS
Data Link Layer
The data link layer is responsible for the low level functions
of passing data across the link. These include optionally
scrambling the data, inserting control characters for multichip
synchronization/lane alignment/monitoring, and encoding
8-bit octets into 10-bit symbols. The data link layer is also
responsible for sending the initial lane alignment sequence
(ILAS), which contains the link configuration data used by the
receiver to verify the settings in the transport layer.
JESD204B LINK ESTABLISHMENT
The AD9680 JESD204B transmitter (Tx) interface operates in
Subclass 1 as defined in the JEDEC Standard 204B (July 2011
specification). The link establishment process is divided into the
following steps: code group synchronization and SYNCINB±,
initial lane alignment sequence, and user data and error correction.
Code Group Synchronization (CGS) and SYNCINB±
The CGS is the process by which the JESD204B receiver finds
the boundaries between the 10-bit symbols in the stream of
data. During the CGS phase, the JESD204B transmit block
transmits /K28.5/ characters. The receiver must locate /K28.5/
characters in its input data stream using clock and data recovery
(CDR) techniques.
The receiver issues a synchronization request by asserting the
SYNCINB± pin of the AD9680 low. The JESD204B Tx then begins
sending /K/ characters. Once the receiver has synchronized, it waits
for the correct reception of at least four consecutive /K/ symbols. It
then deasserts SYNCINB±. The AD9680 then transmits an ILAS
on the following local multiframe clock (LMFC) boundary.
For more information on the code group synchronization
phase, refer to the JEDEC Standard JESD204B, July 2011,
Section 5.3.3.1.
Rev. C | Page 65 of 97
AD9680
Data Sheet
User Data and Error Detection
The SYNCINB± pin operation can also be controlled by the
SPI. The SYNCINB± signal is a differential dc-coupled LVDS
mode signal by default, but it can also be driven single-ended.
For more information on configuring the SYNCINB± pin
operation, refer to Register 0x572.
After the initial lane alignment sequence is complete, the user
data is sent. Normally, within a frame, all characters are considered
user data. However, to monitor the frame clock and multiframe
clock synchronization, there is a mechanism for replacing
characters with /F/ or /A/ alignment characters when the data
meets certain conditions. These conditions are different for
unscrambled and scrambled data. The scrambling operation is
enabled by default, but it can be disabled using the SPI.
The SYNCINB± pins can also be configured to run in CMOS
(single-ended) mode, by setting Bit[4] in Register 0x572. When
running SYNCINB± in CMOS mode, connect the CMOS
SYNCINB signal to Pin 21 (SYNCINB+) and leave Pin 20
(SYNCINB−) floating.
For scrambled data, any 0xFC character at the end of a frame
is replaced by an /F/, and any 0x7C character at the end of a
multiframe is replaced with an /A/. The JESD204B receiver (Rx)
checks for /F/ and /A/ characters in the received data stream
and verifies that they only occur in the expected locations. If an
unexpected /F/ or /A/ character is found, the receiver handles
the situation by using dynamic realignment or asserting the
SYNCINB± signal for more than four frames to initiate a
resynchronization. For unscrambled data, if the final character
of two subsequent frames is equal, the second character is
replaced with an /F/ if it is at the end of a frame, and an /A/ if
it is at the end of a multiframe.
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary. The ILAS consists of four multiframes, with
an /R/ character marking the beginning and an /A/ character
marking the end. The ILAS begins by sending an /R/ character
followed by 0 to 255 ramp data for one multiframe. On the
second multiframe, the link configuration data is sent, starting
with the third character. The second character is a /Q/ character
to confirm that the link configuration data will follow. All
undefined data slots are filled with ramp data. The ILAS
sequence is never scrambled.
Insertion of alignment characters can be modified using SPI.
The frame alignment character insertion (FACI) is enabled by
default. More information on the link controls is available in the
Memory Map section, Register 0x571.
The ILAS sequence construction is shown in Figure 158. The
four multiframes include the following:
•
•
•
Multiframe 1. Begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 2. Begins with an /R/ character followed by a
/Q/ character (/K28.4/), followed by link configuration
parameters over 14 configuration octets (see Table 24) and
ends with an /A/ character. Many of the parameter values
are of the value – 1 notation.
Multiframe 3. Begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 4. Begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
K K
R
D
D A
R Q C
C D
D A
8-Bit/10-Bit Encoder
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols
and inserts control characters into the stream when needed.
The control characters used in JESD204B are shown in Table 24.
The 8-bit/10-bit encoding ensures that the signal is dc balanced by
using the same number of ones and zeros across multiple symbols.
The 8-bit/10-bit interface has options that can be controlled via
the SPI. These operations include bypass and invert. These options
are troubleshooting tools for the verification of the digital front
end (DFE). See the Memory Map section, Register 0x572[2:1]
for information on configuring the 8-bit/10-bit encoder.
R
D
D A
R
D
D A
D
END OF
MULTIFRAME
START OF
ILAS
START OF LINK
CONFIGURATION DATA
START OF
USER DATA
Figure 158. Initial Lane Alignment Sequence
Rev. C | Page 66 of 97
11752-053
•
Data Sheet
AD9680
Table 24. AD9680 Control Characters used in JESD204B
Abbreviation
/R/
/A/
/Q/
/K/
/F/
1
Control Symbol
/K28.0/
/K28.3/
/K28.4/
/K28.5/
/K28.7/
10-Bit Value,
RD1 = −1
001111 0100
001111 0011
001111 0100
001111 1010
001111 1000
8-Bit Value
000 11100
011 11100
100 11100
101 11100
111 11100
10-Bit Value,
RD1 = +1
110000 1011
110000 1100
110000 1101
110000 0101
110000 0111
Description
Start of multiframe
Lane alignment
Start of link configuration data
Group synchronization
Frame alignment
RD means running disparity.
PHYSICAL LAYER (DRIVER) OUTPUTS
If there is no far-end receiver termination, or if there is poor
differential trace routing, timing errors can result. To avoid such
timing errors, it is recommended that the trace length be less
than six inches, and that the differential output traces be close
together and at equal lengths.
Digital Outputs, Timing, and Controls
The AD9680 physical layer consists of drivers that are defined in
the JEDEC Standard JESD204B, July 2011. The differential digital
outputs are powered up by default. The drivers use a dynamic
100 Ω internal termination to reduce unwanted reflections.
Figure 161 to Figure 166 show an example of the digital output
data eye, time interval error (TIE) jitter histogram, and bathtub
curve for one AD9680 lane running at 10 Gbps and 6 Gbps,
respectively. The format of the output data is twos complement
by default. To change the output data format, see the Memory Map
section (Register 0x561 in Table 36).
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 300 mV p-p swing at the receiver
(see Figure 159). Alternatively, single-ended 50 Ω termination
can be used. When single-ended termination is used, the
termination voltage is DRVDD/2. Otherwise, 0.1 µF ac coupling
capacitors can be used to terminate to any single-ended voltage.
De-Emphasis
VRXCM
DRVDD
100Ω
DIFFERENTIAL
0.1µF TRACE PAIR
50Ω
50Ω
SERDOUTx+
100Ω
OR
RECEIVER
SERDOUTx–
OUTPUT SWING = 300mV p-p
11752-054
0.1µF
VCM = VRXCM
Figure 159. AC-Coupled Digital Output Termination Example
The AD9680 digital outputs can interface with custom ASICs
and FPGA receivers, providing superior switching performance
in noisy environments. Single point-to-point network topologies
are recommended with a single differential 100 Ω termination
resistor placed as close to the receiver inputs as possible. The
common mode of the digital output automatically biases itself
to half the DRVDD supply of 1.2 V (VCM = 0.6 V). See Figure 160
for dc coupling the outputs to the receiver logic.
DRVDD
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. Use the de-emphasis feature
only when the receiver is unable to recover the clock due to
excessive insertion loss. Under normal conditions, it is disabled
to conserve power. Additionally, enabling and setting too high a
de-emphasis value on a short link can cause the receiver eye
diagram to fail. Use the de-emphasis setting with caution
because it can increase electromagnetic interference (EMI). See
the Memory Map section (Register 0x5C1 to Register 0x5C5 in
Table 36) for more details.
Phase-Locked Loop
The phase-locked loop (PLL) is used to generate the serializer
clock, which operates at the JESD204B lane rate. The status of
the PLL lock can be checked in the PLL locked status bit
(Register 0x56F, Bit 7). This read only bit lets the user know if
the PLL has achieved a lock for the specific setup. The JESD204B
lane rate control, Bit 4 of Register 0x56E, must be set to
correspond with the lane rate.
100Ω
DIFFERENTIAL
TRACE PAIR
SERDOUTx+
100Ω
RECEIVER
OUTPUT SWING = 300mV p-p
VCM = DRVDD/2
11752-055
SERDOUTx–
Figure 160. DC-Coupled Digital Output Termination Example
Rev. C | Page 67 of 97
AD9680
Data Sheet
400
400
300
300
200
VOLTAGE (mV)
VOLTAGE (mV)
200
100
0
–100
Tx EYE
MASK
100
0
Tx EYE
MASK
–100
–200
–200
–300
–300
–400
–80
–60
–40
–20
0
20
40
60
80
TIME (ps)
–150
–100
–50
0
50
100
150
TIME (ps)
Figure 161. Digital Outputs Data Eye, External 100 Ω Terminations
at 10 Gbps
11752-503
–100
11752-500
–400
Figure 164. Digital Outputs Data Eye, External 100 Ω Terminations
at 6 Gbps
8000
12000
7000
10000
6000
4000
HITS
HITS
8000
6000
4000
3000
4000
2000
2000
–2
0
2
4
6
TIME (ps)
Figure 162. Digital Outputs Histogram, External 100 Ω Terminations
at 10 Gbps
1–2
1–2
1–4
1–4
1–6
1–6
BER
1
1–8
1–10
1–12
1–12
1–14
1–14
–0.3
–0.2
–0.1
0
UI
0.1
0.2
0.3
0.4
0.5
–1
1
0
2
3
4
1–8
1–10
–0.4
–2
Figure 165. Digital Outputs Histogram, External 100 Ω Terminations
at 6 Gbps
1
1–16
–0.5
–3
TIME (ps)
1–16
–0.5
11752-502
BER
0
–4
Figure 163. Digital Outputs Bathtub Curve, External 100 Ω Terminations
at 10 Gbps
–0.4
–0.3
–0.2
–0.1
0
UI
0.1
0.2
0.3
0.4
0.5
11752-505
–4
11752-501
0
11752-504
1000
Figure 166. Digital Outputs Bathtub Curve, External 100 Ω Terminations
at 6 Gbps
Rev. C | Page 68 of 97
Data Sheet
AD9680
JESD204B TX CONVERTER MAPPING
Figure 167 shows a block diagram of the two scenarios
described for I/Q transport layer mapping.
To support the different chip operating modes, the AD9680
design treats each sample stream (real or I/Q) as originating
from separate virtual converters. The I/Q samples are always
mapped in pairs with the I samples mapped to the first virtual
converter and the Q samples mapped to the second virtual
converter. With this transport layer mapping, the number of
virtual converters are the same whether
DIGITAL DOWNCONVERSION
M=2
I
CONVERTER 0
REAL
ADC
REAL
DIGITAL
DOWN
CONVERSION
JESD204B
Tx
L LANES
JESD204B
Tx
L LANES
Q
CONVERTER 1
I/Q ANALOG MIXING
M=2
I
REAL
Σ
ADC
I
CONVERTER 0
90°
PHASE
Q
ADC
Q
CONVERTER 1
Figure 167. I/Q Transport Layer Mapping
REAL/I
ADC A
SAMPLING
AT fS
REAL/I
REAL/Q
REAL/I
REAL/Q
I/Q
CROSSBAR
MUX
REAL/I
REAL/Q
REAL/Q
ADC B
SAMPLING
AT fS
REAL/I
REAL/Q
DDC 0
I
I
Q
Q
DDC 1
I
I
Q
Q
DDC 2
I
I
Q
Q
DDC 3
I
I
Q
Q
REAL/I
CONVERTER 0
Q
CONVERTER 1
REAL/I
CONVERTER 2
Q
CONVERTER 3
REAL/I
CONVERTER 4
Q
CONVERTER 5
REAL/I
CONVERTER 6
Q
CONVERTER 7
Figure 168. DDCs and Virtual Converter Mapping
Rev. C | Page 69 of 97
OUTPUT
INTERFACE
11752-059
•
A single real converter is used along with a digital
downconverter block producing I/Q outputs, or
An analog downconversion is used with two real
converters producing I/Q outputs.
11752-058
•
The JESD204B Tx block for AD9680 supports up to four DDC
blocks. Each DDC block outputs either two sample streams (I/Q)
for the complex data components (real + imaginary), or one
sample stream for real (I) data. The JESD204B interface can be
configured to use up to eight virtual converters depending on the
DDC configuration. Figure 168 shows the virtual converters and
their relationship to the DDC outputs when complex outputs
are used. Table 25 shows the virtual converter mapping for each
chip operating mode when channel swapping is disabled.
AD9680
Data Sheet
Table 25. Virtual Converter Mapping
Number of
Virtual
Converters
Supported
1 to 2
Chip
Operating
Mode (0x200,
Bits[1:0])
Full bandwidth
mode (0x0)
1
One DDC
mode
(0x1)
One DDC
mode
(0x1)
Two DDC
mode
(0x2)
Two DDC
mode
(0x2)
Four DDC
mode
(0x3)
Four DDC
mode
(0x3)
2
2
4
4
8
Chip Q
Ignore
(0x200, Bit 5)
Real or
complex
(0x0)
Real (I only)
(0x1)
Virtual Converter Mapping
0
ADC A
samples
1
ADC B
samples
2
Unused
3
Unused
4
Unused
5
Unused
6
Unused
7
Unused
DDC 0 I
samples
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Complex (I/Q)
(0x0)
DDC 0 I
samples
DDC 0 Q
samples
Unused
Unused
Unused
Unused
Unused
Unused
Real (I only)
(0x1)
DDC 0 I
samples
DDC 1 I
samples
Unused
Unused
Unused
Unused
Unused
Unused
Complex (I/Q)
(0x0)
DDC 0 I
samples
DDC 0 Q
samples
DDC 1 I
samples
DDC 1 Q
samples
Unused
Unused
Unused
Unused
Real (I only)
(0x1)
DDC 0 I
samples
DDC 1 I
samples
DDC 2 I
samples
DDC 3 I
samples
Unused
Unused
Unused
Unused
Complex (I/Q)
(0x0)
DDC 0 I
samples
DDC 0 Q
samples
DDC 1 I
samples
DDC 1 Q
samples
DDC 2 I
samples
DDC 2 Q
samples
DDC 3 I
samples
DDC 3 Q
samples
Rev. C | Page 70 of 97
Data Sheet
AD9680
CONFIGURING THE JESD204B LINK
The decimation ratio (DCM) is the parameter programmed in
Register 0x201.
The AD9680 has one JESD204B link. The device offers an easy
way to set up the JESD204B link through the JESD04B quick
configuration register (Register 0x570). The serial outputs
(SERDOUT0± to SERDOUT3±) are considered to be part of
one JESD204B link. The basic parameters that determine the
link setup are
•
•
•
The following steps can be used to configure the output:
1.
2.
3.
4.
5.
6.
Number of lanes per link (L)
Number of converters per link (M)
Number of octets per frame (F)
If the lane line rate calculated is less than 6.25 Gbps, select
the low line rate option by programming a value of 0x10 to
Register 0x56E.
If the internal DDCs are used for on-chip digital processing, M
represents the number of virtual converters. The virtual converter
mapping setup is shown in Figure 168.
Table 26 and Table 27 show the JESD204B output configurations
supported for both N΄ = 16 and N΄ = 8 for a given number of
virtual converters. Take care to ensure that the serial line rate
for a given configuration is within the supported range of
3.125 Gbps to 12.5 Gbps.
The maximum lane rate allowed by the JESD204B specification
is 12.5 Gbps. The lane line rate is related to the JESD204B
parameters using the following equation:
10
M × N '×  × f OUT
 8 
Lane Line Rate =
L
where f OUT =
Power down the link.
Select quick configuration options.
Configure detailed options.
Set output lane mapping (optional).
Set additional driver configuration options (optional).
Power up the link.
f ADC _ CLOCK
Decimation Ratio
Table 26. JESD204B Output Configurations for N΄ = 16
Number of Virtual
Converters
Supported
(Same Value as M)
1
2
4
8
JESD204B Transport Layer Settings2
JESD204B Quick
Configuration
(0x570)
0x01
0x40
0x41
0x80
0x81
0x0A
0x49
0x88
0x89
0x13
0x52
0x91
0x1C
0x5B
0x9A
JESD204B Serial
Line Rate1
20 × fOUT
10 × fOUT
10 × fOUT
5 × fOUT
5 × fOUT
40 × fOUT
20 × fOUT
10 × fOUT
10 × fOUT
80 × fOUT
40 × fOUT
20 × fOUT
160 × fOUT
80 × fOUT
40 × fOUT
L
1
2
2
4
4
1
2
4
4
1
2
4
1
2
4
M
1
1
1
1
1
2
2
2
2
4
4
4
8
8
8
F
2
1
2
1
2
4
2
1
2
8
4
2
16
8
4
S
1
1
2
2
4
1
1
1
2
1
1
1
1
1
1
HD
0
1
0
1
0
0
0
1
0
0
0
0
0
0
0
N
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
8 to 16
N΄
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
CS
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
0 to 3
K3
Only valid K
values that
are divisible
by 4 are
supported
fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3125 Mbps and ≤12,500 Mbps; when the serial line rate is
≤12.5 Gbps and ≥ 6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in 0x56E). When the serial line rate is <6.25 Gbps and ≥3.125 Gbps, the low line
rate mode must be enabled (set Bit 4 to 0x1 in 0x56E).
2
JESD204B transport layer descriptions are as described in the JESD204B Overview section.
3
For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.
1
Rev. C | Page 71 of 97
AD9680
Data Sheet
Table 27. JESD204B Output Configurations for N΄ = 8
Number of Virtual
Converters Supported
(Same Value as M)
1
2
JESD204B Quick
Configuration
(0x570)
0x00
0x01
0x40
0x41
0x42
0x80
0x81
0x09
0x48
0x49
0x88
0x89
0x8A
JESD204B Transport Layer Settings2
Serial Line Rate1
10 × fOUT
10 × fOUT
5 × fOUT
5 × fOUT
5 × fOUT
2.5 × fOUT
2.5 × fOUT
20 × fOUT
10 × fOUT
10 × fOUT
5 × fOUT
5 × fOUT
5 × fOUT
L
1
1
2
2
2
4
4
1
2
2
4
4
4
M
1
1
1
1
1
1
1
2
2
2
2
2
2
F
1
2
1
2
4
1
2
2
1
2
1
2
4
S
1
2
2
4
8
4
8
1
1
2
2
4
8
HD
0
0
0
0
0
0
0
0
0
0
0
0
0
N
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
7 to 8
N΄
8
8
8
8
8
8
8
8
8
8
8
8
8
CS
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
0 to 1
K3
Only valid K
values which
are divisible
by 4 are
supported
fOUT = output sample rate = ADC sample rate/chip decimation ratio. The JESD204B serial line rate must be ≥3125 Mbps and ≤12,500 Mbps; when the serial line rate is
≤12.5 Gbps and ≥6.25 Gbps, the low line rate mode must be disabled (set Bit 4 to 0x0 in Register 0x56E). When the serial line rate is <6.25 Gbps and ≥3.125 Gbps, the
low line rate mode must be enabled (set Bit 4 to 0x1 in Register 0x56E).
2
JESD204B transport layer descriptions are as described in the JESD204B Overview section.
3
For F = 1, K = 20, 24, 28, and 32. For F = 2, K = 12, 16, 20, 24, 28, and 32. For F = 4, K = 8, 12, 16, 20, 24, 28, and 32. For F = 8 and F = 16, K = 4, 8, 12, 16, 20, 24, 28, and 32.
1
See the Example 1: Full Bandwidth Mode section and the
Example 2: ADC with DDC Option (Two ADCs Plus Four
DDCs) section for two examples describing which JESD204B
transport layer settings are valid for a given chip mode.
CMOS
FAST
DETECTION
REAL/I
Example 1: Full Bandwidth Mode
14-BIT
AT
1Gbps
CONVERTER 0
JESD204B
TRANSMIT
INTERFACE
Chip application mode = full bandwidth mode (see Figure 169).
Two 14-bit converters at 1000 MSPS
Full bandwidth application layer mode
No decimation
REAL/Q
14-BIT
AT
1Gbps
CONVERTER 1
FAST
DETECTION
JESD204B output configuration is as follows:
•
•
CMOS
Two virtual converters required (see Table 26)
Output sample rate (fOUT) = 1000/1 = 1000 MSPS
Figure 169. Full Bandwidth Mode
Example 2: ADC with DDC Option (Two ADCs Plus Four
DDCs)
JESD204B supported output configurations (see Table 26)
include:
•
•
•
•
•
•
11752-060
•
•
•
L
JESD204B
LANES
AT UP TO
12.5Gbps
N΄ = 16 bits
N = 14 bits
L = 4, M = 2, and F = 1, or L = 4, M = 2, and F = 2 (quick
configuration = 0x88 or 0x89)
CS = 0 to 2
K = 32
Output serial line rate = 10 Gbps per lane, low line rate
mode disabled
Chip application mode = four-DDC mode. (see Figure 170).
•
•
•
•
Two 14-bit converters at 1 GSPS
Four DDC application layer mode with complex outputs
(I/Q)
Chip decimation ratio = 16
DDC decimation ratio = 16 (see Table 15).
JESD204B output configuration is as follows:
•
•
Rev. C | Page 72 of 97
Virtual converters required = 8 (see Table 26)
Output sample rate (fOUT) = 1000/16 = 62.5 MSPS
Data Sheet
AD9680
For L = 1, low line rate mode is disabled. For L = 2, low line
rate mode is enabled.
JESD204B supported output configurations (see Table 26):
•
•
•
N΄ = 16 bits
N = 14 bits
L = 1, M = 8, and F = 16, or L = 2, M = 8, and F = 8 (quick
configuration = 0x1C or 0x5B)
CS = 0 to 1
K = 32
Output serial line rate = 10 Gbps per lane (L = 1) or 5 Gbps
per lane (L = 2)
REAL
ADC A
SAMPLING
AT fS
REAL/I
REAL/Q
Example 2 shows the flexibility in the digital and lane
configurations for the AD9680. The sample rate is 1 GSPS;
however, the outputs are all combined in either one or two
lanes, depending on the I/O speed capability of the receiving
device.
DDC 0
I
CONVERTER 0
Q
CONVERTER 1
DDC 1
I
CONVERTER 2
Q
CONVERTER 3
DDC 2
I
CONVERTER 4
Q
CONVERTER 5
DDC 3
I
CONVERTER 6
Q
CONVERTER 7
I/Q
CROSSBAR
MUX
REAL/I
REAL
SYSREF
ADC B
SAMPLING
AT fS
REAL/Q
L JESD204B
LANES UP TO
12.5Gbps
L
JESD204B
LANES
AT UP TO
12.5Gbps
11752-061
•
•
•
SYNCHRONIZATION
CONTROL CIRCUITS
Figure 170. Two ADC Plus Four DDC Mode
Rev. C | Page 73 of 97
AD9680
Data Sheet
MULTICHIP SYNCHRONIZATION
The AD9680 has a SYSREF± input that provides flexible options
for synchronizing the internal blocks. The SYSREF± input is a
source synchronous system reference signal that enables multichip
synchronization. The input clock divider, DDCs, signal monitor
block, and JESD204B link can be synchronized using the SYSREF±
input. For the highest level of timing accuracy, SYSREF± must
meet setup and hold requirements relative to the CLK± input.
The flowchart in Figure 171 describes the internal mechanism
for multichip synchronization in the AD9680. The AD9680
supports several features that aid users in meeting the
requirements set out for capturing a SYSREF± signal. The
SYSREF sample event can be defined as either a synchronous
low to high transition, or a synchronous high to low transition.
Additionally, the AD9680 allows the SYSREF signal to be sampled
using either the rising edge or falling edge of the CLK± input.
The AD9680 also has the ability to ignore a programmable
number (up to 16) of SYSREF± events. The SYSREF± control
options can be selected using Register 0x120 and Register 0x121.
Rev. C | Page 74 of 97
Data Sheet
AD9680
START
INCREMENT
SYSREF± IGNORE
COUNTER
NO
NO
RESET
SYSREF± IGNORE
COUNTER
SYSREF±
ENABLED?
(0x120)
NO
NO
SYSREF±
ASSERTED?
YES
UPDATE
SETUP/HOLD
DETECTOR STATUS
(0x128)
YES
SYSREF±
IGNORE
COUNTER
EXPIRED?
(0x121)
YES
ALIGN CLOCK
DIVIDER
PHASE TO
SYSREF
INPUT
CLOCK
DIVIDER
ALIGNMENT
REQUIRED?
YES
YES
TIMESTAMP
MODE
SYSREF±
TIMESTAMP
DELAY
(0x123)
INCREMENT
SYSREF±
COUNTER
(0x12A)
CLOCK
DIVIDER
> 1?
(0x10B)
YES
NO
NO
NO
SYNCHRONIZATION
MODE?
(0x1FF)
CLOCK
DIVIDER
AUTO ADJUST
ENABLED?
(0x10D)
SYSREF±
CONTROL BITS?
(0x559, 0x55A,
0x58F)
YES
SYSREF±
INSERTED
IN JESD204B
CONTROL BITS
NO
RAMP
TEST
MODE
ENABLED?
(0x550)
NORMAL
MODE
YES
SYSREF± RESETS
RAMP TEST
MODE
GENERATOR
BACK TO START
NO
YES
ALIGN PHASE
OF ALL
INTERNAL CLOCKS
(INCLUDING LMFC)
TO SYSREF±
SEND INVALID
8-BIT/10-BIT
CHARACTERS
(ALL 0's)
SYNC~
ASSERTED
NO
SEND K28.5
CHARACTERS
NORMAL
JESD204B
INITIALIZATION
NO
NO
SIGNAL
MONITOR
ALIGNMENT
ENABLED?
(0x26F)
YES
YES
ALIGN SIGNAL
MONITOR
COUNTERS
DDC NCO
ALIGNMENT
ENABLED?
(0x300)
YES
NO
Figure 171. Multichip Synchronization
Rev. C | Page 75 of 97
ALIGN DDC
NCO PHASE
ACCUMULATOR
BACK TO START
11752-112
JESD204B
LMFC
ALIGNMENT
REQUIRED?
AD9680
Data Sheet
SYSREF± SETUP/HOLD WINDOW MONITOR
To ensure a valid SYSREF signal capture, the AD9680 has a
SYSREF± setup/hold window monitor. This feature allows the
system designer to determine the location of the SYSREF± signals
relative to the CLK± signals by reading back the amount of
setup/hold margin on the interface through the memory map.
Figure 172 and Figure 173 show the setup and hold status values
for different phases of SYSREF±. The setup detector returns the
status of the SYSREF± signal before the CLK± edge, and the
hold detector returns the status of the SYSREF signal after the
CLK± edge. Register 0x128 stores the status of SYSREF± and
lets the user know if the SYSREF± signal is captured by the ADC.
0xF
0xE
0xD
0xC
0xB
0xA
0x9
REG 0x128[3:0] 0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
CLK±
INPUT
VALID
SYSREF±
INPUT
FLIP-FLOP
HOLD (MIN)
FLIP-FLOP
HOLD (MIN)
Figure 172. SYSREF± Setup Detector
Rev. C | Page 76 of 97
11752-113
FLIP-FLOP
SETUP (MIN)
Data Sheet
AD9680
REG 0x128[7:4]
0xF
0xE
0xD
0xC
0xB
0xA
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
CLK±
INPUT
SYSREF±
INPUT
FLIP-FLOP
SETUP (MIN)
FLIP-FLOP
HOLD (MIN)
FLIP-FLOP
HOLD (MIN)
11752-114
VALID
Figure 173. SYSREF± Hold Detector
Table 28 shows the description of the contents of Register 0x128 and how to interpret them.
Table 28. SYSREF± Setup/Hold Monitor, Register 0x128
Register 0x128[7:4]
Hold Status
0x0
0x0 to 0x8
0x8
0x8
0x9 to 0xF
0x0
Register 0x128[3:0]
Setup Status
0x0 to 0x7
0x8
0x9 to 0xF
0x0
0x0
0x0
Description
Possible setup error. The smaller this number, the smaller the setup margin.
No setup or hold error (best hold margin).
No setup or hold error (best setup and hold margin).
No setup or hold error (best setup margin).
Possible hold error. The larger this number, the smaller the hold margin.
Possible setup or hold error.
Rev. C | Page 77 of 97
AD9680
Data Sheet
TEST MODES
ADC TEST MODES
The AD9680 has various test options that aid in the system level
implementation. The AD9680 has ADC test modes that are
available in Register 0x550. These test modes are described in
Table 29. When an output test mode is enabled, the analog section
of the ADC is disconnected from the digital back-end blocks,
and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and
some are not. The PN generators from the PN sequence tests
can be reset by setting Bit 4 or Bit 5 of Register 0x550. These
tests can be performed with or without an analog signal (if
present, the analog signal is ignored); however, they do require
an encode clock.
If the application mode is set to select a DDC mode of
operation, the test modes must be enabled for each DDC
enabled. The test patterns can be enabled via Bit 2 and Bit 0 of
Register 0x327, Register 0x347, and Register 0x367, depending
on which DDC(s) are selected. The (I) data uses the test
patterns selected for Channel A, and the (Q) data uses the test
patterns selected for Channel B. For DDC3 only, the (I) data
uses the test patterns from Channel A, and the (Q) data does
not output test patterns. Bit 0 of Register 0x387 selects the
Channel A test patterns to be used for the (I) data. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
Table 29. ADC Test Modes1
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
User input
Expression
N/A
00 0000 0000 0000
01 1111 1111 1111
10 0000 0000 0000
10 1010 1010 1010
X23 + X18 + 1
X9 + X5 + 1
11 1111 1111 1111
Register 0x551 to
Register 0x558
1111
Ramp Output
(X) % 214
1
Default/
Seed Value
N/A
N/A
N/A
N/A
N/A
0x3AFF
0x0092
N/A
N/A
N/A
N/A means not applicable.
Rev. C | Page 78 of 97
Sample (N, N + 1, N + 2, …)
N/A
N/A
N/A
N/A
0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555
0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6
0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697
0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000
User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
User Pattern 1[15:2] … for repeat mode
User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
0x0000 … for single mode
(X) % 214, (X +1) % 214, (X +2) % 214, (X +3) % 214
Data Sheet
AD9680
JESD204B BLOCK TEST MODES
In addition to the ADC pipeline test modes, the AD9680 also has
flexible test modes in the JESD204B block. These test modes are
listed in Register 0x573 and Register 0x574. These test patterns
can be injected at various points along the output data path. These
test injection points are shown in Figure 156. Table 30 describes
the various test modes available in the JESD204B block. For the
AD9680, a transition from test modes (Register 0x573 ≠ 0x00)
to normal mode (Register 0x573 = 0x00) requires an SPI soft
reset. This is done by writing 0x81 to Register 0x00 (self cleared).
Transport Layer Sample Test Mode
The transport layer samples are implemented in the AD9680 as
defined by Section 5.1.6.3 in the JEDEC JESD204B Specification.
These tests are shown in Register 0x571[5]. The test pattern is
equivalent to the raw samples from the ADC.
Interface Test Modes
The interface test modes are described in Register 0x573, Bits[3:0].
These test modes are also explained in Table 30. The interface tests
can be injected at various points along the data. See Figure 156
for more information on the test injection points. Register 0x573,
Bits[5:4] show where these tests are injected.
Table 31, Table 32, and Table 33 show examples of some of the
test modes when injected at the JESD sample input, PHY 10-bit
input, and scrambler 8-bit input. UP in the tables represent the
user pattern control bits from the customer register map.
Table 30. JESD204B Interface Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
1110
1111
Pattern Name
Off (default)
Alternating checker board
1/0 word toggle
31-bit PN sequence
23-bit PN sequence
15-bit PN sequence
9-bit PN sequence
7-bit PN sequence
Ramp output
Continuous/repeat user test
Single user test
Expression
Not applicable
0x5555, 0xAAAA, 0x5555, …
0x0000, 0xFFFF, 0x0000, …
X31 + X28 + 1
X23 + X18 + 1
X15 + X14 + 1
X9 + X5 + 1
X7 + X6 + 1
(X) % 216
Register 0x551 to Register 0x558
Register 0x551 to Register 0x558
Default
Not applicable
Not applicable
Not applicable
0x0003AFFF
0x003AFF
0x03AF
0x092
0x07
Ramp size depends on test injection point
User Pattern 1 to User Pattern 4, then repeat
User Pattern 1 to User Pattern 4, then zeros
Table 31. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x573[5:4] = 'b00)
Frame
Number
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
Converter
Number
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Sample
Number
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Alternating
Checkerboard
0x5555
0x5555
0x5555
0x5555
0xAAAA
0xAAAA
0xAAAA
0xAAAA
0x5555
0x5555
0x5555
0x5555
0xAAAA
0xAAAA
0xAAAA
0xAAAA
0x5555
0x5555
0x5555
0x5555
1/0 Word
Toggle
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
Ramp
(X) % 216
(X) % 216
(X) % 216
(X) % 216
(X +1) % 216
(X +1) % 216
(X +1) % 216
(X +1) % 216
(X +2) % 216
(X +2) % 216
(X +2) % 216
(X +2) % 216
(X +3) % 216
(X +3) % 216
(X +3) % 216
(X +3) % 216
(X +4) % 216
(X +4) % 216
(X +4) % 216
(X +4) % 216
Rev. C | Page 79 of 97
PN9
0x496F
0x496F
0x496F
0x496F
0xC9A9
0xC9A9
0xC9A9
0xC9A9
0x980C
0x980C
0x980C
0x980C
0x651A
0x651A
0x651A
0x651A
0x5FD1
0x5FD1
0x5FD1
0x5FD1
PN23
0xFF5C
0xFF5C
0xFF5C
0xFF5C
0x0029
0x0029
0x0029
0x0029
0xB80A
0xB80A
0xB80A
0xB80A
0x3D72
0x3D72
0x3D72
0x3D72
0x9B26
0x9B26
0x9B26
0x9B26
User Repeat
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
User Single
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
0x0000
0x0000
0x0000
0x0000
AD9680
Data Sheet
Table 32. Physical Layer 10-bit Input (Register 0x573[5:4] = 'b01)
10-Bit Symbol
Number
0
1
2
3
4
5
6
7
8
9
10
11
Alternating
Checkerboard
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
1/0 Word
Toggle
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
Ramp
(X) % 210
(X + 1) % 210
(X + 2) % 210
(X + 3) % 210
(X + 4) % 210
(X + 5) % 210
(X + 6) % 210
(X + 7) % 210
(X + 8) % 210
(X + 9) % 210
(X + 10) % 210
(X + 11) % 210
PN9
0x125
0x2FC
0x26A
0x198
0x031
0x251
0x297
0x3D1
0x18E
0x2CB
0x0F1
0x3DD
PN23
0x3FD
0x1C0
0x00A
0x1B8
0x028
0x3D7
0x0A6
0x326
0x10F
0x3FD
0x31E
0x008
User Repeat
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
User Single
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
Table 33. Scrambler 8-bit Input (Register 0x573[5:4] = 'b10)
8-Bit Octet
Number
0
1
2
3
4
5
6
7
8
9
10
11
Alternating
Checkerboard
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
1/0 Word
Toggle
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
Ramp
(X) % 28
(X + 1) % 28
(X + 2) % 28
(X + 3) % 28
(X + 4) % 28
(X + 5) % 28
(X + 6) % 28
(X + 7) % 28
(X + 8) % 28
(X + 9) % 28
(X + 10) % 28
(X + 11) % 28
Data Link Layer Test Modes
The data link layer test modes are implemented in the AD9680
as defined by section 5.3.3.8.2 in the JEDEC JESD204B
Specification. These tests are shown in Register 0x574 Bits[2:0].
PN9
0x49
0x6F
0xC9
0xA9
0x98
0x0C
0x65
0x1A
0x5F
0xD1
0x63
0xAC
PN23
0xFF
0x5C
0x00
0x29
0xB8
0x0A
0x3D
0x72
0x9B
0x26
0x43
0xFF
User Repeat
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
User Single
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Test patterns inserted at this point are useful for verifying the
functionality of the data link layer. When the data link layer
test modes are enabled, disable SYNCINB± by writing 0xC0
to Register 0x572.
Rev. C | Page 80 of 97
Data Sheet
AD9680
SERIAL PORT INTERFACE
The AD9680 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the Serial Control Interface Standard (Rev. 1.0).
CONFIGURATION USING THE SPI
Three pins define the SPI of the AD9680 ADC: the SCLK pin,
the SDIO pin, and the CSB pin (see Table 34). The SCLK (serial
clock) pin is used to synchronize the read and write data
presented from/to the ADC. The SDIO (serial data input/output)
pin is a dual-purpose pin that allows data to be sent and read
from the internal ADC memory map registers. The CSB (chip
select bar) pin is an active low control that enables or disables
the read and write cycles.
Table 34. Serial Port Interface Pins
Pin
SCLK
SDIO
CSB
Function
Serial clock. The serial shift clock input that is used to
synchronize serial interface, reads, and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active low control that gates the read
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 4 and
Table 5.
Other modes involving the CSB pin are available. The CSB pin
can be held low indefinitely, which permanently enables the
device; this is called streaming. The CSB can stall high between
bytes to allow additional external timing. When CSB is tied
high, SPI functions are placed in a high impedance mode. This
mode turns on any SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
command is issued, which allows the SDIO pin to change
direction from an input to an output.
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the SDIO pin
to change direction from an input to an output at the appropriate
point in the serial frame.
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the Serial Control Interface Standard
(Rev. 1.0).
HARDWARE INTERFACE
The pins described in Table 34 comprise the physical interface
between the user programming device and the serial port of the
AD9680. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is
used for other devices, it may be necessary to provide buffers
between this bus and the AD9680 to prevent these signals from
transitioning at the converter inputs during critical sampling
periods.
SPI ACCESSIBLE FEATURES
Table 35 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the Serial Control Interface Standard (Rev. 1.0). The AD9680
device-specific features are described in the Memory Map section.
Table 35. Features Accessible Using the SPI
Feature Name
Mode
Clock
DDC
Test Input/Output
Output Mode
SERDES Output Setup
Description
Allows the user to set either power-down mode or standby mode.
Allows the user to access the clock divider via the SPI.
Allows the user to set up decimation filters for different applications.
Allows the user to set test modes to have known data on output bits.
Allows the user to set up outputs.
Allows the user to vary SERDES settings such as swing and emphasis.
Rev. C | Page 81 of 97
AD9680
Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Logic Levels
Each row in the memory map register table has eight bit
locations. The memory map is divided into four sections: the
Analog Devices SPI registers (Register 0x000 to Register 0x00D),
the analog input buffer control registers, the ADC function
registers, the DDC function registers, and the digital outputs
and test modes registers.
An explanation of logic level terminology follows:
Table 36 (see the Memory Map Register Table section) documents
the default hexadecimal value for each hexadecimal address shown.
The column with the heading Bit 7 (MSB) is the start of the
default hexadecimal value given. For example, Address 0x561,
the output mode register, has a hexadecimal default value of
0x01, which means that Bit 0 = 1, and the remaining bits are 0s.
This setting is the default output format value, which is twos
complement. For more information on this function and others,
see Table 36.
Open and Reserved Locations
All address and bit locations that are not included in Table 36
are not currently supported for this device. Write unused bits of
a valid address location with 0s unless the default value is set
otherwise. Writing to these locations is required only when part
of an address location is unassigned (for example, Address 0x561).
If the entire address location is open (for example, Address 0x13),
do not write to this address location.
Default Values
After the AD9680 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 36.
•
•
•
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
X denotes a don’t care bit.
Channel-Specific Registers
Some channel setup functions, such as the input termination
(Register 0x016), can be programmed to a different value for
each channel. In these cases, channel address locations are
internally duplicated for each channel. These registers and bits
are designated in Table 36 as local. These local registers and bits
can be accessed by setting the appropriate Channel A or Channel B
bits in Register 0x008. If both bits are set, the subsequent write
affects the registers of both channels. In a read cycle, set only
Channel A or Channel B to read one of the two registers. If both
bits are set during an SPI read cycle, the device returns the value
for Channel A. Registers and bits designated as global in Table 36
affect the entire device and the channel features for which
independent settings are not allowed between channels. The
settings in Register 0x005 do not affect the global registers and bits.
SPI Soft Reset
After issuing a soft reset by programming 0x81 to Register 0x000,
the AD9680 requires 5 ms to recover. When programming the
AD9680 for application setup, ensure that an adequate delay is
programmed into the firmware after asserting the soft reset and
before starting the device setup.
Rev. C | Page 82 of 97
Data Sheet
AD9680
MEMORY MAP REGISTER TABLE
All address locations that are not included in Table 36 are not currently supported for this device and should not be written.
Table 36. Memory Map Registers
Reg
Addr
Register
Bit 7
(Hex)
Name
(MSB)
Analog Devices SPI Registers
INTERFACE_
Soft reset
0x000
CONFIG_A
(self
clearing)
INTERFACE_
Single
0x001
CONFIG_B
instruction
0x002
0x003
0x004
0x005
0x006
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
LSB first
0 = MSB
1 = LSB
0
Address
ascension
0
0
Address
ascension
0
0
0
0
0
0
0
Bit 1
Bit 0 (LSB)
Default
Soft reset
LSB first
(self
0 = MSB
clearing)
1 = LSB
Datapath
0
0
soft reset
(self
clearing)
00 = normal operation
0
10 = standby
11 = power-down
011 = high speed ADC
0x03
0x00
0x00
DEVICE_
CONFIG
(local)
CHIP_TYPE
0
CHIP_ID
(low byte)
CHIP_ID
(high byte)
CHIP_
GRADE
1
1
0
0
0
1
0
1
0xC5
0
0
0
0
0
0
0
0
0x00
X
X
X
X
0x008
0x00A
0x00B
0x00C
Device index
0
Scratch pad
0
SPI revision
0
Vendor ID
0
(low byte)
Vendor ID
0x00D
0
(high byte)
Analog Input Buffer Control Registers
Analog input
0x015
0
(local)
0x016
Input
termination
(local)
0x934
Input
capacitance
(local)
0
0
0
1
0
0
0
0
0
0
0
1
Channel B
0
0
1
Channel A
0
1
0
0x0
0x00
0x01
0x56
0
0
0
0
1
0
0
0x04
0
0
0
0
Analog input differential termination
0000 = 400 Ω (default)
0001 = 200 Ω
0010 = 100 Ω
0110 = 50 Ω
0
0x00
1100 = 1250 MSPS
1010 = 1000 MSPS
1000 = 820 MSPS
0101 = 500 MSPS
0
0
0
0
0
0
1
0
0
0
Input
disable
0=
normal
operation
1 = input
disabled
1110 = AD9680-1250 and AD9680-1000
1100 = AD9680-820 and AD9680-500
0
0
0x1F = 3 pF to GND (default)
0x00 = 1.5 pF to GND
Rev. C | Page 83 of 97
Notes
0x00
0x0E for
AD96801250 and
AD96801000;
0x0C for
AD9680820 and
AD9680500
0x1F
Read
only
Read
only
Read
only
Read
only
Read
only
Read
only
AD9680
Reg
Addr
(Hex)
0x018
Register
Name
Buffer
Control 1
(local)
Data Sheet
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
0000 = 1.0× buffer current
0001 = 1.5× buffer current
0010 = 2.0× buffer current (default for AD9680-500)
0011 = 2.5× buffer current
0100 = 3.0× buffer current (default for AD9680-1000
and AD9680-820)
0101 = 3.5× buffer current (default for AD9680-1250)
…
1111 = 8.5× buffer current
0100 = Setting 1 (default for AD9680-820)
0101 = Setting 2 (default for AD9680-1250 and
AD9680-1000)
0110 = Setting 3 (default for AD9680-500)
0111 = Setting 4
Bit 3
0
Bit 2
0
0
Bit 1
0
0x019
Buffer
Control 2
(local)
0x01A
Buffer
Control 3
(local)
0
0
0
0
0x11A
Buffer
Control 4
(local)
0
0
0
0
0x935
Buffer
Control 5
(local)
0
0
High
frequency
setting
0 = off
(default)
1 = on
0
0
0
0x025
Input fullscale range
(local)
0
0
0
0
0x030
Input fullscale control
(local)
0
0
0
Full-scale control
See Table 10 for recommended settings
for different frequency bands;
default values:
AD9680-1250, AD9680-1000 = 110
AD9680-820 = 101
AD9680-500 = 001
AD9680-500 = 110 (for <1.82 V)
0
0
Bit 0 (LSB)
0
0
1000 = Setting 1
1001 = Setting 2 (default for AD9680-1250,
AD9680-1000 and AD9680-820)
1010 = Setting 3 (default for AD9680-500)
0
0
Rev. C | Page 84 of 97
Notes
0x09 for
AD96801250;
0x0A for
AD96801000
and
AD9680820;
0x0C for
AD9680500
V p-p
differential;
use in
conjunction with
Reg.
0x030
0
0
0
Low
frequency
operation
0 = off
1 = on
(default)
Full-scale adjust
0000 = 1.94 V
1000 = 1.46 V
1001 = 1.58 V (default for AD9680-1250)
1010 = 1.70 V (default for AD9680-1000 and
AD9680-820)
1011 = 1.82 V
1100 = 2.06 V (default for AD9680-500)
0
Default
0x50 for
AD96801250;
0x40 for
AD96801000
and
AD9680820;
0x20 for
AD9680500
0x50 for
AD96801250 and
AD96801000;
0x40 for
AD9680820;
0x60 for
AD9680500
0x09 for
AD96801250,
AD96801000
and
AD9680820;
0x0A for
AD9680500
0
Used in
conjunction with
Reg.
0x025
Data Sheet
Reg
Addr
Register
(Hex)
Name
ADC Function Registers
V_1P0
0x024
control
AD9680
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Default
0
0
0
0
0
0
0
0x00
0
0
0
0
0
0
0
0
1.0 V
reference
select
0=
internal
1=
external
Diode
selection
0=
no diode
selected
1=
temperature
diode
selected
0
0x028
Temperature
diode
0
0x03F
PDWN/
STBY pin
control (local)
0x040
Chip pin
control
0 = PDWN/ 0
STBY
enabled
1=
disabled
PDWN/STBY function
00 = power down
01 = standby
10 = disabled
0x10B
Clock divider
0
0x10C
Clock divider
phase (local)
0
0x10D
Clock divider
and SYSREF
control
Clock
divider
auto phase
adjust
0=
disabled
1=
enabled
0x117
Clock delay
control
0
0
0
0
Fast Detect A (FD_A)
000 = Fast Detect A output
001 = JESD204B LMFC output
010 = JESD204B internal SYNC~ output
011 = temperature diode
111 = disabled
000 = divide by 1
0
001 = divide by 2
011 = divide by 4
111 = divide by 8
Independently controls Channel A and Channel B clock
divider phase offset
0000 = 0 input clock cycles delayed
0001 = ½ input clock cycles delayed
0010 = 1 input clock cycles delayed
0011 = 1½ input clock cycles delayed
0100 = 2 input clock cycles delayed
0101 = 2½ input clock cycles delayed
…
1111 = 7½ input clock cycles delayed
Clock divider positive
Clock divider negative
skew window
skew window
00 = no positive skew
00 = no negative skew
01 = 1 device clock of
01 = 1 device clock of
positive skew
negative skew
10 = 2 device clocks of
10 = 2 device clocks of
positive skew
negative skew
11 = 3 device clocks of
11 = 3 device clocks of
positive skew
negative skew
Clock fine
0
0
0
delay
adjust
enable
0=
disabled
1=
enabled
0x00
Used in
conjunction with
Reg.
0x040
0x00
Used in
conjunction with
Reg.
0x040
Fast Detect B (FD_B)
000 = Fast Detect B output
001 = JESD204B LMFC output
010 = JESD204B internal SYNC~ output
111 = disabled
0x3F
0
0
0
0x00
0
0
0
0
0
0
0
0
0
Rev. C | Page 85 of 97
Notes
0x00
0x00
0x00
Clock
divider
must be
>1
Enabling
the clock
fine delay
adjust
causes a
datapath
reset
AD9680
Reg
Addr
(Hex)
0x118
Data Sheet
Register
Name
Clock fine
delay (local)
Bit 7
(MSB)
0x11C
Clock status
0
0x120
SYSREF±
Control 1
0
0x121
SYSREF±
Control 2
0
0x123
SYSREF±
timestamp
delay control
0x128
SYSREF±
Status 1
SYSREF± and
clock divider
status
0x129
0x12A
0x1FF
Bit 6
Bit 4
Bit 3
Bit 2
Bit 1
Clock Fine Delay Adjust[7:0],
twos complement coded control to adjust the fine sample clock skew in ~1.7 ps steps
≤ −88 = −151.7 ps skew
−87 = −150 ps skew
…
0 = 0 ps skew
…
≥ +87 = +150 ps skew
0
0
0
0
0
0
SYSREF±
flag reset
0=
normal
operation
1 = flags
held in
reset
0
Bit 5
Bit 0 (LSB)
Default
0x00
Read
only
0
SYSREF±
transition
select
0 = low to
high
1 = high to
low
0 = no
input
clock
detected
1 = input
clock
detected
0
0
0
CLK±
edge
select
0 = rising
1 = falling
SYSREF± mode select
00 = disabled
01 = continuous
10 = N shot
SYSREF N-shot ignore counter select
0000 = next SYSREF± only
0001 = ignore the first SYSREF± transition
0010 = ignore the first two SYSREF± transitions
…
1111 = ignore the first 16 SYSREF± transitions
SYSREF± timestamp delay, Bits[6:0]
0x00 = no delay
0x01 = 1 clock delay
…
0x7F = 127 clocks delay
SYSREF± hold status, Register 0x128[7:4],
SYSREF± setup status, Register 0x128[3:0],
refer to Table 28
refer to Table 28
Clock divider phase when SYSREF± was captured
0
0
0
0
0000 = in-phase
0001 = SYSREF± is ½ cycle delayed from clock
0010 = SYSREF± is 1 cycle delayed from clock
0011 = 1½ input clock cycles delayed
0100 = 2 input clock cycles delayed
0101 = 2½ input clock cycles delayed
…
1111 = 7½ input clock cycles delayed
SYSREF counter, Bits[7:0] increments when a SYSREF± is captured
SYSREF±
counter
Chip sync
mode
0x200
Chip
application
mode
0
0
0x201
Chip
decimation
ratio
0
0
0x228
Customer
offset
Synchronization mode
00 = normal
01 = timestamp
Chip operating mode
Chip Q
0
0
0
00 = full bandwidth mode
ignore
01 = DDC 0 on
0 = normal
10 = DDC 0 and DDC 1 on
(I/Q)
11 = DDC 0, DDC 1,
1 = ignore
DDC 2, and DDC 3 on
(I only)
Chip decimation ratio select
0
0
0
000 = full sample rate (decimate = 1)
001 = decimate by 2
010 = decimate by 4
011 = decimate by 8
100 = decimate by 16
Offset adjust in LSBs from +127 to −128 (twos complement format)
Rev. C | Page 86 of 97
Notes
Used in
conjunction
with Reg.
0x0117
0x00
0x00
0x00
Read
only
Read
only
Read
only
0x00
0x00
0x00
0x00
Mode
select
(Reg
0x120,
Bits [2:1])
must be
N-shot
Ignored
when
Reg.
0x01FF
= 0x00
Data Sheet
Reg
Addr
(Hex)
0x245
0x247
0x248
0x249
0x24A
0x24B
0x24C
0x26F
Register
Name
Fast detect
(FD) control
(local)
FD upper
threshold
LSB (local)
FD upper
threshold
MSB (local)
FD lower
threshold
LSB (local)
FD lower
threshold
MSB (local)
FD dwell
time LSB
(local)
FD dwell
time MSB
(local)
Signal
monitor
synchronization control
0x270
Signal
monitor
control (local)
0x271
Signal
Monitor
Period
Register 0
(local)
Signal
Monitor
Period
Register 1
(local)
Signal
Monitor
Period
Register 2
(local)
Signal
monitor
result control
(local)
0x272
0x273
0x274
0x275
Signal
Monitor
Result
Register 0
(local)
AD9680
Bit 7
(MSB)
0
Bit 6
0
0
Bit 5
0
0
Bit 4
0
Bit 3
Bit 2
Force value of
Force
FD_A/FD_B
FD_A/
FD_B pins; pins if force
0 = normal pins is true,
this value is
function;
output on FD
1 = force
pins
to value
Fast detect upper threshold, Bits[7:0]
0
Bit 1
0
Bit 0 (LSB)
Enable
fast detect
output
0
Fast detect upper threshold, Bits[12:8]
0
0x00
0x00
Fast detect dwell time, Bits[7:0]
0x00
Fast detect dwell time, Bits[15:8]
0x00
0
0
0
0
0
0
0
0
0
0
0
0
0x00
Fast detect lower threshold, Bits[12:8]
0
Synchronization mode
00 = disabled
01 = continuous
11 = one shot
Peak
detector
0=
disabled
1=
enabled
0
0x00
0x80
Signal monitor period, Bits[15:8]
0x00
Signal monitor period, Bits[23:16]
0x00
0
Rev. C | Page 87 of 97
Refer to
the
Signal
Monitor
section
0x00
Signal monitor period, Bits[7:0]
Result
Result
0
0
0
selection
update
0=
1=
reserved
update
1 = peak
results
detector
(self clear)
Signal monitor result, Bits[7:0]
When Register 0x0274[0] = 1, Result Bits[19:7] = Peak Detector Absolute Value[12:0]; Result Bits[6:0] = 0
0
Notes
0x00
Fast detect lower threshold, Bits[7:0]
0
Default
0x00
In decimated
output
clock
cycles
In decimated
output
clock
cycles
In decimated
output
clock
cycles
0x01
Read
only
Updated
based on
Reg.
0x274[4]
AD9680
Reg
Addr
(Hex)
0x276
0x277
0x278
0x279
0x27A
Register
Name
Signal
Monitor
Result
Register 1
(local)
Signal
Monitor
Result
Register 1
(local)
Signal
monitor
period
counter
result (local)
Signal
monitor
SPORT over
JESD204B
control (local)
SPORT over
JESD204B
input
selection
(local)
Data Sheet
Bit 7
(MSB)
0
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Signal monitor result, Bits[15:8]
0
DDC 0 input
selection
0x314
DDC 0
frequency
LSB
DDC 0
frequency
MSB
DDC 0 phase
LSB
DDC 0 phase
MSB
0x315
0x320
0x321
Bit 0 (LSB)
Signal monitor result, Bits[19:16]
Period count result, Bits[7:0]
0
0
0
0
0
0
0
0
0
0
0
0
DDC Function Registers (See the Digital Downconverter (DDC) Section)
DDC NCO
DDC
0
0
0
0x300
soft reset
synchro0 = normal
nization
operation
control
1 = reset
IF (intermediate
Gain
DDC 0
Mixer
0x310
frequency) mode
select
control
select
00 = variable IF mode
0 = 0 dB
0 = real
(mixers and NCO
gain
mixer
enabled)
1 = 6 dB
1=
01 = 0 Hz IF mode (mixer
gain
complex
bypassed, NCO disabled)
mixer
10 = fS/4 Hz IF mode (fs/4
downmixing mode)
11 = test mode (mixer
inputs forced to +fS,
NCO enabled)
0x311
Bit 1
0
X
X
0
X
X
0
X
X
0
0
Complex
to real
enable
0=
disabled
1=
enabled
0
Q input
select
0 = Ch A
1 = Ch B
DDC 0 NCO frequency value, Bits[7:0]
twos complement
0
X
0
00 = disabled
11 = enable
Peak
detector
0=
disabled
1=
enabled
0
Synchronization mode
(triggered by SYSREF±)
00 = disabled
01 = continuous
11 = one shot
Decimation rate select
(complex to real
disabled)
11 = decimate by 2
00 = decimate by 4
01 = decimate by 8
10 = decimate by 16
(complex to real
enabled)
11 = decimate by 1
00 = decimate by 2
01 = decimate by 4
10 = decimate by 8
I input
0
select
0 = Ch A
1 = Ch B
DDC 0 NCO frequency value, Bits[11:8]
twos complement
DDC 0 NCO phase value, Bits[7:0]
twos complement
DDC 0 NCO phase value, Bits[11:8]
X
twos complement
Rev. C | Page 88 of 97
Default
Read
only
Notes
Updated
based on
Reg.
0x274[4]
Read
only
Updated
based on
Reg.
0x274[4]
Read
only
Updated
based on
Reg.
0x274[4]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Refer to
the DDC
section
Data Sheet
Reg
Addr
(Hex)
0x327
AD9680
Register
Name
DDC 0
output test
mode
selection
Bit 7
(MSB)
0
0x330
DDC 1
control
0x331
DDC 1 input
selection
0x334
DDC 1
frequency
LSB
DDC 1
frequency
MSB
DDC 1 phase
LSB
DDC 1 phase
MSB
DDC 1
output test
mode
selection
0x335
0x340
0x341
0x347
Bit 6
0
Bit 5
0
Mixer
select
0 = real
mixer
1=
complex
mixer
Gain
select
0 = 0 dB
gain
1 = 6 dB
gain
0
0
IF (intermediate
frequency) mode
00 = variable IF mode
(mixers and NCO
enabled)
01 = 0 Hz IF mode (mixer
bypassed, NCO disabled)
10 = fADC/4 Hz IF mode
(fADC/4 downmixing
mode)
11 = test mode (mixer
inputs forced to +fS,
NCO enabled)
0
0
X
X
X
X
0
0
0x350
DDC 2
control
Mixer
select
0 = real
mixer
1=
complex
mixer
Gain
select
0 = 0 dB
gain
1 = 6 dB
gain
0x351
DDC 2 input
selection
0
0
0x354
DDC 2
frequency
LSB
DDC2
frequency
MSB
0x355
X
X
Bit 4
0
Bit 3
0
Bit 2
Q output
test mode
enable
0 = disabled
1 = enabled
from
Channel B
Complex
to real
enable
0=
disabled
1=
enabled
0
Q input
select
0 = Ch A
1 = Ch B
DDC 1 NCO frequency value, Bits[7:0]
twos complement
X
X
0
Bit 1
0
Bit 0 (LSB)
I output
test mode
enable
0=
disabled
1=
enabled
from
Channel A
Decimation rate select
(complex to real
disabled)
11 = decimate by 2
00 = decimate by 4
01 = decimate by 8
10 = decimate by 16
(complex to real
enabled)
11 = decimate by 1
00 = decimate by 2
01 = decimate by 4
10 = decimate by 8
I input
0
select
0 = Ch A
1 = Ch B
DDC 1 NCO frequency value, Bits[11:8]
twos complement
DDC 1 NCO phase value, Bits[7:0]
twos complement
DDC 1 NCO phase value, Bits[11:8]
X
X
twos complement
I output
Q output
0
0
0
0
test mode
test mode
enable
enable
0=
0 = disabled
disabled
1 = enabled
1=
from Ch B
enabled
from Ch A
IF mode
Decimation rate select
Complex
0
00 = variable IF mode
(complex to real
to real
(mixers and NCO
disabled)
enable
enabled)
11 = decimate by 2
0=
01 = 0 Hz IF mode (mixer disabled
00 = decimate by 4
bypassed, NCO disabled) 1 =
01 = decimate by 8
10 = fADC/4 Hz IF mode
10 = decimate by 16
enabled
(complex to real
(fADC/4 downmixing
enabled)
mode)
11 = decimate by 1
11 = test mode (mixer
00 = decimate by 2
inputs forced to +fS,
01 = decimate by 4
NCO enabled)
10 = decimate by 8
I input
Q input
0
0
0
0
select
select
0 = Ch A
0 = Ch A
1 = Ch B
1 = Ch B
DDC 2 NCO frequency value, Bits[7:0]
twos complement
X
X
DDC 2 NCO frequency value, Bits[11:8]
twos complement
Rev. C | Page 89 of 97
Default
0x00
Notes
Refer to
the DDC
section
0x00
0x05
Refer to
the DDC
section
0x00
0x00
0x00
0x00
0x00
Refer to
the DDC
section
0x00
0x00
0x00
0x00
Refer to
the DDC
section
AD9680
Reg
Addr
(Hex)
0x360
0x361
0x367
Register
Name
DDC 2 phase
LSB
DDC 2 phase
MSB
DDC 2
output test
mode
selection
Data Sheet
Bit 7
(MSB)
Bit 6
X
X
0
0
0x370
DDC 3
control
Mixer
select
0 = real
mixer
1=
complex
mixer
Gain
select
0 = 0 db
gain
1 = 6 db
gain
0x371
DDC 3 input
selection
0
0
0x374
DDC 3
frequency
LSB
DDC 3
frequency
MSB
DDC3 phase
LSB
DDC 3 phase
MSB
DDC 3
output test
mode
selection
0x375
0x380
0x381
0x387
X
User Pattern
1 LSB
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
DDC 2 NCO phase value, Bits[7:0]
twos complement
DDC 2 NCO phase value, Bits[11:8]
X
X
twos complement
Q output
I output
0
0
0
0
test mode
test mode
enable
enable
0 = disabled
0=
1 = enabled
disabled
from Ch B
1=
enabled
from Ch A
IF mode
Decimation rate select
Complex
0
00 = variable IF mode
(complex to real
to real
(mixers and NCO
disabled)
enable
enabled)
11 = decimate by 2
0=
01 = 0 Hz IF mode(mixer
00 = decimate by 4
disabled
bypassed, NCO disabled) 1 =
01 = decimate by 8
10 = fADC/4 Hz IF mode
10 = decimate by 16
enabled
(complex to real
(fADC/4 downmixing
enabled)
mode)
11 = decimate by 1
11 = test mode (mixer
00 = decimate by 2
inputs forced to +fS,
01 = decimate by 4
NCO enabled)
10 = decimate by 8
I input
Q input
0
0
0
0
select
select
0 = Ch A
0 = Ch A
1 = Ch B
1 = Ch B
DDC 3 NCO frequency value, Bits[7:0]
twos complement
X
DDC 3 NCO frequency value, Bits[11:8]
twos complement
X
DDC 3 NCO phase value, Bits[7:0]
twos complement
DDC 3 NCO phase value, Bits[11:8]
X
twos complement
I output
0
0
0
0
test mode
enable
0=
disabled
1=
enabled
from Ch A
X
X
X
0
0
0
0
Reset PN
long gen
0 = long
PN enable
1 = long
PN reset
Reset PN
short gen
0 = short
PN enable
1 = short
PN reset
0
0
0
Digital Outputs and Test Modes
User
ADC test
0x550
pattern
modes
selection
(local)
0 = continuous
repeat
1 = single
pattern
0x551
X
Bit 5
0
0
Test mode selection
0000 = off, normal operation
0001 = midscale short
0010 = positive full scale
0011 = negative full scale
0100 = alternating checker board
0101 = PN sequence, long
0110 = PN sequence, short
0111 = 1/0 word toggle
1000 = the user pattern test mode (used with
Register 0x0550, Bit 7 and User Pattern 1 to
User Pattern 4 registers)
1111 = ramp output
0
0
0
Rev. C | Page 90 of 97
Default
0x00
Notes
0x00
0x00
Refer to
the DDC
section
0x00
0x05
Refer to
the DDC
section
0x00
0x00
0x00
0x00
0x00
Refer to
the DDC
section
0x00
0x00
Used
with Reg.
0x550
and Reg.
0x573
Data Sheet
Reg
Addr
(Hex)
0x552
AD9680
Register
Name
User Pattern
1 MSB
Bit 7
(MSB)
0
Bit 6
0
Bit 5
0
Bit 4
0
Bit 3
0
Bit 2
0
Bit 1
0
Bit 0 (LSB)
0
Default
0x00
0x553
User Pattern
2 LSB
0
0
0
0
0
0
0
0
0x00
0x554
User Pattern
2 MSB
0
0
0
0
0
0
0
0
0x00
0x555
User Pattern
3 LSB
0
0
0
0
0
0
0
0
0x00
0x556
User Pattern
3 MSB
0
0
0
0
0
0
0
0
0x00
0x557
User Pattern
4 LSB
0
0
0
0
0
0
0
0
0x00
0x558
User Pattern
4 MSB
0
0
0
0
0
0
0
0
0x00
0x559
Output Mode
Control 1
0
0
Converter Control Bit 0 selection
000 = tie low (1’b0)
001 = overrange bit
011 = fast detect (FD) bit
101 = SYSREF±
Only used when CS (Register 0x58F) = 3
0x00
0x55A
Output Mode
Control 2
0
Converter Control Bit 1 selection
000 = tie low (1’b0)
001 = overrange bit
011 = fast detect (FD) bit
101 = SYSREF±
Only used when CS (Register 0x58F)
= 2 or 3
0
0
0
0
0x01
0x561
Output
mode
0
0
0
0x562
Output
overrange
(OR) clear
0x563
Output OR
status
Converter Control Bit 2 selection
000 = tie low (1’b0)
001 = overrange bit
011 = fast detect (FD) bit
101 = SYSREF
Used when CS (Register 0x58F) = 1, 2, or 3
Data format select
Sample
00 = offset binary
invert
01 = twos complement
0 = normal
1 = sample
invert
Virtual
Virtual
Virtual
Converter 2
Converter 1 Converter
OR
OR
0 OR
0 = OR bit
0 = OR bit
0 = OR bit
enabled
enabled
enabled
1 = OR bit
1 = OR bit
1 = OR bit
cleared
cleared
cleared
Virtual
Virtual
Virtual
Converter 1 Converter
Converter 2
0 OR
OR
OR
0 = no OR
0 = no OR
0 = no OR
1 = OR
1 = OR
1 = OR
occurred
occurred
occurred
Virtual
Converter 7
OR
0 = OR bit
enabled
1 = OR bit
cleared
Virtual
Converter 7
OR
0 = no OR
1 = OR
occurred
Virtual
Converter
6 OR
0 = OR bit
enabled
1 = OR bit
cleared
Virtual
Converter
6 OR
0 = no
OR
1 = OR
occurred
0
Virtual
Converter 5
OR
0 = OR bit
enabled
1 = OR bit
cleared
Virtual
Converter 5
OR
0 = no OR
1 = OR
occurred
0
Virtual
Converter 4
OR
0 = OR bit
enabled
1 = OR bit
cleared
Virtual
Converter 4
OR
0 = no OR
1 = OR
occurred
Virtual
Converter
3 OR
0 = OR bit
enabled
1 = OR bit
cleared
Virtual
Converter
3 OR
0 = no OR
1 = OR
occurred
Rev. C | Page 91 of 97
Notes
Used
with Reg.
0x550
and Reg.
0x573
Used
with Reg.
0x550
and Reg.
0x573
Used
with Reg.
0x550
and Reg.
0x573
Used
with Reg.
0x550
and Reg.
0x573
Used
with Reg.
0x550
and Reg.
0x573
Used
with Reg.
0x550
and Reg.
0x573
Used
with Reg.
0x550
and Reg.
0x573
0x01
0x00
0x00
Read
only
AD9680
Reg
Addr
(Hex)
0x564
Data Sheet
Register
Name
Output
channel
select
Bit 7
(MSB)
0
Bit 6
0
Bit 5
0
0x56E
JESD204B
lane rate
control
0
0
0
0x56F
JESD204B
PLL lock
status
PLL lock
0 = not
locked
1 = locked
0
0
0x570
JESD204B
quick configuration
0x571
JESD204B
Link Mode
Control 1
Standby
mode
0 = all
converter
outputs 0
1 = CGS
(/K28.5/)
0x572
JESD204B
Link Mode
Control 2
SYNCINB± pin control
00 = normal
10 = ignore SYNCINB±
(force CGS)
11 = ignore SYNCINB±
(force ILAS/user data)
0x573
JESD204B
Link Mode
Control 3
CHKSUM mode
00 = sum of all 8-bit link
config registers
01 = sum of individual
link config fields
10 = checksum set to
zero
Bit 4
0
0 = serial
lane rate
≥6.25 Gbps
and
≤12.5 Gbps
1 = serial
lane rate
must be ≥
3.125 Gbps
and
≤6.25 Gbps
0
Bit 3
0
Bit 2
0
Bit 1
0
Default
0x00
0
Bit 0 (LSB)
Converter
channel
swap
0=
normal
channel
ordering
1=
channel
swap
enabled
0
0
0
0
0
0
0
0x00
Read
only
0x88 for
AD96801250,
AD96801000 and
AD9680820;
0x49 for
AD9680500
0x14
Refer to
Table 26
and
Table 27
JESD204B quick configuration
L = number of lanes = 2Register 0x570, Bits[7:6]
M = number of converters = 2Register 0x570, Bits[5:3]
F = number of octets/frame = 2 Register 0x570, Bits[2:0]
Tail bit
(t) PN
0=
disable
1=
enable
T = N΄ −
N − CS
Long
transport
layer test
0=
disable
1=
enable
SYNCINB±
pin invert
0 = active
low
1 = active
high
Lane synchronization
0 = disable
FACI uses
/K28.7/
1 = enable
FACI uses
/K28.3/ and
/K28.7/
SYNCINB±
pin type
0=
differential
1 = CMOS
Test injection point
00 = N΄ sample input
01 = 10-bit data at
8-bit/10-bit output
(for PHY testing)
10 = 8-bit data at
scrambler input
ILAS sequence mode
00 = ILAS disabled
01 = ILAS enabled
11 = ILAS always on test
mode
0
FACI
0=
enabled
1=
disabled
Link
control
0 = active
1 = power
down
8-/10-bit
0
bit invert
0=
normal
1 = invert
the abcd
efghij
symbols
JESD204B test mode patterns
0000 = normal operation (test mode disabled)
0001 = alternating checker board
0010 = 1/0 word toggle
0011 = 31-bit PN sequence—X31 + X28 + 1
0100 = 23-bit PN sequence—X23 + X18 + 1
0101 = 15-bit PN sequence—X15 + X14 + 1
0110 = 9-bit PN sequence—X9 + X5 + 1
0111 = 7-bit PN sequence—X7 + X6 + 1
1000 = ramp output
1110 = continuous/repeat user test
1111 = single user test
Rev. C | Page 92 of 97
8-bit/10-bit
bypass
0 = normal
1 = bypass
Notes
0x00 for
AD96801250,
AD96801000 and
AD9680820;
0x10 for
AD9680500
0x00
0x00
Data Sheet
Reg
Addr
(Hex)
0x574
0x578
0x580
0x581
0x583
0x584
0x585
0x586
0x58B
Register
Name
JESD204B
Link Mode
Control 4
JESD204B
LMFC offset
JESD204B
DID config
JESD204B
BID config
JESD204B LID
Config 1
JESD204B LID
Config 2
JESD204B LID
Config 3
JESD204B LID
Config 4
JESD204B
parameters
SCR/L
AD9680
Bit 7
(MSB)
Bit 6
Bit 5
Bit 4
ILAS delay
0000 = transmit ILAS on first LMFC after SYNCINB±
deasserted
0001 = transmit ILAS on second LMFC after
SYNCINB± deasserted
…
1111 = transmit ILAS on 16th LMFC after SYNCINB±
deasserted
0
0
0
Bit 2
Bit 1
Bit 0 (LSB)
Link layer test mode
000 = normal operation (link layer test
mode disabled)
001 = continuous sequence of /D21.5/
characters
100 = modified RPAT test sequence
101 = JSPAT test sequence
110 = JTSPAT test sequence
LMFC phase offset value[4:0]
Default
0x00
JESD204B Tx DID value[7:0]
0x00
0
0x00
0
0
0
0
0
Lane 0 LID value, Bits[4:0]
0x00
0
0
0
Lane 1 LID value, Bits[4:0]
0x01
0
0
0
Lane 2 LID value, Bits[4:0]
0x01
0
0
0
Lane 3 LID value, Bits[4:0]
0x03
JESD204B
scrambling
(SCR)
0=
disabled
1=
enabled
0
0
JESD204B F
config
0x58D
JESD204B K
config
JESD204B M
config
0
0x58F
JESD204B
CS/N config
0x590
JESD204B N’
config
Number of control bits
(CS) per sample
00 = no control bits
(CS = 0)
01 = 1 control bit (CS =
1); Control Bit 2 only
10 = 2 control bits
(CS = 2); Control Bit 2
and 1 only
11 = 3 control bits
(CS = 3); all control bits
(2, 1, 0)
0
0
0x591
JESD204B S
config
0
JESD204B Tx BID value, Bits[3:0]
0
0
JESD204B lanes (L)
00 = 1 lane
01 = 2 lanes
11 = 4 lanes
Read only, see
Register 0x570
Number of octets per frame, F = Register 0x58C[7:0] + 1
0
0
0
Number of frames per multiframe, K = Register 0x58D[4:0] + 1
Only values where (F × K) mod 4 = 0 are supported
Number of Converters per Link[7:0]
0x00 = link connected to one virtual converter (M = 1)
0x01 = link connected to two virtual converters (M = 2)
0x03 = link connected to four virtual converters (M = 4)
0x07 = link connected to eight virtual converters (M = 8)
ADC converter resolution (N)
0
0x06 = 7-bit resolution
0x07 = 8-bit resolution
0x08 = 9-bit resolution
0x09 = 10-bit resolution
0x0A = 11-bit resolution
0x0B = 12-bit resolution
0x0C = 13-bit resolution
0x0D = 14-bit resolution
0x0E = 15-bit resolution
0x0F = 16-bit resolution
0
Subclass
support
(Subclass V)
0=
Subclass 0
(no deterministic
latency)
1=
Subclass 1
1
0x8X
0x88
0x1F
Read
only,
see Reg.
0x570
See Reg.
0x570
Read
only
0x0F
ADC number of bits per sample (N’)
0x7 = 8 bits
0xF = 16 bits
0x2F
Samples per converter frame cycle (S)
S value = Register 0x591[4:0] + 1
0x20
Rev. C | Page 93 of 97
Notes
0x00
0
0x58C
0x58E
Bit 3
0
Read
only
AD9680
Reg
Addr
(Hex)
0x592
0x5A0
0x5A1
0x5A2
0x5A3
Register
Name
JESD204B HD
and CF
config
JESD204B
CHKSUM 0
JESD204B
CHKSUM 1
JESD204B
CHKSUM 2
JESD204B
CHKSUM 3
JESD204B
lane powerdown
Data Sheet
Bit 7
(MSB)
HD value
0=
disabled
1=
enabled
Bit 6
0
Bit 5
0
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 (LSB)
Control words per frame clock cycle per link (CF)
CF value = Register 0x592, Bits[4:0]
Default
0x80
Notes
Read
only
CHKSUM value for SERDOUT0±, Bits[7:0]
0x81
CHKSUM value for SERDOUT1±, Bits[7:0]
0x82
CHKSUM value for SERDOUT2±, Bits[7:0]
0x82
CHKSUM value for SERDOUT3±, Bits[7:0]
0x84
Read
only
Read
only
Read
only
Read
only
X
SERDOUT2±
0 = on
1 = off
X
0
0x5B2
JESD204B
lane
SERDOUT0±
assign
X
SERDOUT3±
0 = on
1 = off
X
0x5B3
JESD204B
lane
SERDOUT1±
assign
X
X
X
X
0
0x5B5
JESD204B
lane
SERDOUT2±
assign
X
X
X
X
0
0x5B6
JESD204B
lane
SERDOUT3±
assign
X
X
X
X
0
0x5BF
JESD
serializer
drive adjust
0
0
0
0
0x5C1
De-emphasis
select
0
SERDOUT3±
0=
disable
1=
enable
0
SERDOUT2±
0=
disable
1=
enable
0x5B0
1
1
1
0
Rev. C | Page 94 of 97
SERDSERD1
OUT0±
OUT1±
0 = on
0 = on
1 = off
1 = off
SERDOUT0± lane assignment
000 = Logical Lane 0
001 = Logical Lane 1
010 = Logical Lane 2
011 = Logical Lane 3
SERDOUT1± lane assignment
000 = Logical Lane 0
001 = Logical Lane 1
010 = Logical Lane 2
011 = Logical Lane 3
SERDOUT2± lane assignment
000 = Logical Lane 0
001 = Logical Lane 1
010 = Logical Lane 2
011 = Logical Lane 3
SERDOUT3± lane assignment
000 = Logical Lane 0
001 = Logical Lane 1
010 = Logical Lane 2
011 = Logical Lane 3
Swing voltage
0000 = 237.5 mV
0001 = 250 mV
0010 = 262.5 mV
0011 = 275 mV
0100 = 287.5 mV
0101 = 300 mV (default)
0110 = 312.5 mV
0111 = 325 mV
1000 = 337.5 mV
1001 = 350 mV
1010 = 362.5 mV
1011 = 375 mV
1100 = 387.5 mV
1101 = 400 mV
1110 = 412.5 mV
1111 = 425 mV
SERDSERDOUT1±
0
OUT0±
0 = disable
0 = disable
1 = enable
1 = enable
0xAA
0x00
0x11
0x22
0x33
0x05
0x00
Data Sheet
Reg
Addr
(Hex)
0x5C2
AD9680
Register
Name
De-emphasis
setting for
SERDOUT0±
Bit 7
(MSB)
0
Bit 6
0
Bit 5
0
Bit 4
0
0x5C3
De-emphasis
setting for
SERDOUT1±
0
0
0
0
0x5C4
De-emphasis
setting for
SERDOUT2±
0
0
0
0
0x5C5
De-emphasis
setting for
SERDOUT3±
0
0
0
0
Bit 3
Rev. C | Page 95 of 97
Bit 2
Bit 1
Bit 0 (LSB)
SERDOUT0± de-emphasis settings
0000 = 0 dB
0001 = 0.3 dB
0010 = 0.8 dB
0011 = 1.4 dB
0100 = 2.2 dB
0101 = 3.0 dB
0110 = 4.0 dB
0111 = 5.0 dB
SERDOUT1± de-emphasis settings
0000 = 0 dB
0001 = 0.3 dB
0010 = 0.8 dB
0011 = 1.4 dB
0100 = 2.2 dB
0101 = 3.0 dB
0110 = 4.0 dB
0111 = 5.0 dB
SERDOUT2± de-emphasis settings
0000 = 0 dB
0001 = 0.3 dB
0010 = 0.8 dB
0011 = 1.4 dB
0100 = 2.2 dB
0101 = 3.0 dB
0110 = 4.0 dB
0111 = 5.0 dB
SERDOUT3± de-emphasis settings
0000 = 0 dB
0001 = 0.3 dB
0010 = 0.8 dB
0011 = 1.4 dB
0100 = 2.2 dB
0101 = 3.0 dB
0110 = 4.0 dB
0111 = 5.0 dB
Default
0x00
0x00
0x00
0x00
Notes
AD9680
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
The AD9680 must be powered by the following seven supplies:
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR =
1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, and SPIVDD = 1.80 V.
For applications requiring an optimal high power efficiency and
low noise performance, it is recommended that the ADP2164
and ADP2370 switching regulators be used to convert the 3.3 V,
5.0 V, or 12 V input rails to an intermediate rail (1.8 V and 3.8 V).
These intermediate rails are then postregulated by very low
noise, low dropout (LDO) regulators (ADP1741, ADM7172,
and ADP125). Figure 174 shows the recommended power
supply scheme for the AD9680.
ADP1741
1.8V
AVDD1
1.25V
plane must have several vias to achieve the lowest possible
resistive thermal path for heat dissipation to flow through the
bottom of the PCB. These vias must be solder filled or plugged.
The number of vias and the fill determine the resulting θJA
measured on the board.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous copper plane by overlaying a
silkscreen on the PCB into several uniform sections. This
provides several tie points between the ADC and PCB during
the reflow process, whereas using one continuous plane with no
partitions only guarantees one tie point. See Figure 175 for a
PCB layout example. For detailed information on packaging
and the PCB layout of chip scale packages, see the AN-772
Application Note, A Design and Manufacturing Guide for the
Lead Frame Chip Scale Package (LFCSP).
AVDD1_SR
1.25V
ADP1741
DVDD
1.25V
DRVDD
1.25V
3.6V
ADP125
AVDD3
3.3V
3.3V
ADM7172
OR
ADP1741
AVDD2
2.5V
11752-063
SPIVDD
(1.8V OR 3.3V)
It is not necessary to split all of these power domains in all cases.
The recommended solution shown in Figure 174 provides the
lowest noise, highest efficiency power delivery system for the
AD9680. If only one 1.25 V supply is available, route to AVDD1
first and then tap it off and isolate it with a ferrite bead or a filter
choke, preceded by decoupling capacitors for AVDD1_SR, DVDD,
and DRVDD, in that order. This is shown as the optional path
in Figure 174. The user can employ several different decoupling
capacitors to cover both high and low frequencies. These capacitors
must be located close to the point of entry at the PCB level and
close to the devices, with minimal trace lengths.
EXPOSED PAD THERMAL HEAT SLUG
RECOMMENDATIONS
The exposed pad on the underside of the ADC must be connected
to AGND to achieve the best electrical and thermal performance
of the AD9680. Connect an exposed continuous copper plane
on the PCB to the AD9680 exposed pad, Pin 0. The copper
11752-064
Figure 174. High Efficiency, Low Noise Power Solution for the AD9680
Figure 175. Recommended PCB Layout of Exposed Pad for the AD9680
AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60)
AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) can be
used to provide a separate power supply node to the SYSREF±
circuits of AD9680. If running in Subclass 1, the AD9680 can
support periodic one-shot or gapped signals. To minimize the
coupling of this supply into the AVDD1 supply node, adequate
supply bypassing is needed.
Rev. C | Page 96 of 97
Data Sheet
AD9680
OUTLINE DIMENSIONS
9.10
9.00 SQ
8.90
0.30
0.25
0.18
PIN 1
INDICATOR
49
1
0.50
BSC
EXPOSED
PAD
7.70
7.60 SQ
7.50
33
0.80
0.75
0.70
0.45
0.40
0.35
16
32
17
BOTTOM VIEW
7.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
PKG-004396
SEATING
PLANE
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WMMD
02-12-2014-A
TOP VIEW
PIN 1
INDICATOR
64
48
Figure 176. 64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
9 mm × 9 mm Body, Very Thin Quad
(CP-64-15)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9680BCPZ-1250
AD9680BCPZ-1000
AD9680BCPZ-820
AD9680BCPZ-500
AD9680BCPZRL7-1250
AD9680BCPZRL7-1000
AD9680BCPZRL7-820
AD9680BCPZRL7-500
AD9680-1250EBZ
AD9680-1000EBZ
AD9680-LF1000EBZ
AD9680-820EBZ
AD9680-LF820EBZ
AD9680-500EBZ
AD9680-LF500EBZ
1
2
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description2
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
64-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
Evaluation Board for AD9680-1250
Evaluation Board for AD9680-1000
Evaluation Board for AD9680-1000 with 1 GHz Bandwidth
Evaluation Board for AD9680-820
Evaluation Board for AD9680-820 with 1 GHz Bandwidth
Evaluation Board for AD9680-500
Evaluation Board for AD9680-500 with 1 GHz Bandwidth
Package Option
CP-64-15
CP-64-15
CP-64-15
CP-64-15
CP-64-15
CP-64-15
CP-64-15
CP-64-15
Z = RoHS Compliant Part.
The AD9680-1250EBZ, AD9680-1000EBZ, AD9680-820EBA, and AD9680-500EBZ evaluation boards are optimized for full analog input frequency range of 2 GHz.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D11752-0-11/15(C)
Rev. C | Page 97 of 97
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