1CY74FCT162H952 T Data sheet acquired from Cypress Semiconductor Corporation. Data sheet modified to remove devices not offered. CY74FCT16952T CY74FCT162952T CY74FCT162H952T 16-Bit Registered Transceivers SCCS065C - August 1994 - Revised September 2001 Features Functional Description • Ioff supports partial-power-down mode operation • Edge-rate control circuitry for significantly improved noise characteristics • Typical output skew < 250 ps • ESD > 2000V • TSSOP (19.6-mil pitch) and SSOP (25-mil pitch) packages • Industrial temperature range of –40˚C to +85˚C • VCC = 5V ± 10% CY74FCT16952T Features: • 64 mA sink current, 32 mA source current • Typical VOLP (ground bounce) <1.0V at VCC = 5V, TA = 25˚C These 16-bit registered transceivers are high-speed, low-power devices. 16-bit operation is achieved by connecting the control lines of the two 8-bit registered transceivers together. For data flow from bus A-to-B, CEAB must be LOW to allow data to be stored when CLKAB transitions from LOW-to-HIGH. The stored data will be present on the output when OEAB is LOW. Control of data from B-to-A is similar and is controlled by using the CEBA, CLKBA, and OEBA inputs. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The CY74FCT16952T is ideally suited for driving high-capacitance loads and low-impedance backplanes. The CY74FCT162952T has 24-mA balanced output drivers with current-limiting resistors in the outputs. This reduces the need for external terminating resistors and provides for minimal undershoot and reduced ground bounce. The CY74FCT162952T is ideal for driving transmission lines. CY74FCT162952T Features: • Balanced 24 mA output drivers • Reduced system switching noise • Typical VOLP (ground bounce) <0.6V at VCC = 5V, TA= 25˚C CY74FCT162H952T Features: • Bus hold retains last active state • Eliminates the need for external pull-up or pull-down resistors The CY74FCT162H952T is a 24-mA balanced output part that has “bus hold” on the data inputs. The device retains the input’s last state whenever the input goes to high impedance. This eliminates the need for pull-up/down resistors and prevents floating inputs. Pin Configuration Logic Block Diagrams SSOP/TSSOP Top View 1 OEAB 2 CEBA 1 CEBA 1 CLKBA 2 OEAB 1 CEAB 2 CEAB 1 CLKAB 1A1 2 OEBA C CE D 1B1 C CE D 2A1 TO 7 OTHER CHANNELS 3 4 54 53 1 CEBA 5 52 1B1 1A2 VCC 6 51 1B2 7 50 VCC 1A3 8 9 49 48 1B3 47 46 45 1B5 GND 1 1A6 10 11 12 1A7 13 44 1B7 1A8 14 43 1B8 2A1 15 42 2B1 2A2 16 17 41 40 2B2 GND 2A4 18 39 GND 19 38 2B4 2A5 20 21 37 36 2B5 2A6 VCC 22 35 VCC 2A7 23 34 2B7 2A8 24 25 33 32 2B8 GND 2 CEAB 26 31 2 CEBA 2 CLKAB 27 30 2 CLKBA 2 OEAB 28 29 2 OEBA 1A4 1A5 C CE D 2B C CE D FCT16952–1 1 OEBA GND 1A1 2 CLKAB 1 OEBA 56 55 1 CEAB 2 CLKBA 1 OEAB 1 2 1 CLKAB FCT16952–2 TO 7 OTHER CHANNELS 2A3 1 CLKBA GND 1B4 GND 1B6 2B3 2B6 GND FCT16952–3 Copyright © 2001, Texas Instruments Incorporated CY74FCT16952T CY74FCT162952T CY74FCT162H952T Maximum Ratings[5, 6] Pin Description Name Description (Above which the useful life may be impaired. For user guidelines, not tested.) OEAB A-to-B Output Enable Input (Active LOW) OEBA B-to-A Output Enable Input (Active LOW) Storage Temperature ................................. –55°C to +125°C CEAB A-to-B Clock Enable Input (Active LOW) CEBA B-to-A Clock Enable Input (Active LOW) Ambient Temperature with Power Applied............................................. –55°C to +125°C CLKAB A-to-B Clock Input CLKBA B-to-A Clock Input A A-to-B Data Inputs or B-to-A Three-State Outputs[1] B B-to-A Data Inputs or A-to-B Three-State Outputs[1] DC Input Voltage ........................................... –0.5V to +7.0V DC Output Voltage......................................... –0.5V to +7.0V DC Output Current (Maximum Sink Current/Pin) ........................–60 to +120 mA Power Dissipation .......................................................... 1.0W Static Discharge Voltage............................................>2001V (per MIL-STD-883, Method 3015) Function Table[2, 3] For A-to-B (Symmetric with B-to-A) Operating Range Inputs Outputs CEAB CLKAB OEAB A B H X L X B[4] X L L X B[4] L L L L L L H H H X Z X X Range Industrial Ambient Temperature VCC –40°C to +85°C 5V ± 10% Notes: 1. On the CY74FCT162H952T these pins have bus hold. 2. A-to-B data flow is shown: B-to-A data flow is similar but uses, CEBA, CLKBA, and OEBA. 3. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care. 4. 5. 6. = LOW-to-HIGH Transition. Z = HIGH Impedance. Level of B before the indicated steady-state input conditions were established. Operation beyond the limits set forth may impair the useful life of the device. Unless otherwise noted, these limits are over the operating free-air temperature range. Unused inputs must always be connected to an appropriate logic voltage level, preferably either VCC or ground. 2 CY74FCT16952T CY74FCT162952T CY74FCT162H952T Electrical Characteristics Over the Operating Range Parameter Description VIH Input HIGH Voltage VIL Input LOW Voltage Test Conditions Min. Input Hysteresis VIK Input Clamp Diode Voltage IIH Input HIGH Current 100 VCC=Min., IIN= –18 mA Standard Input LOW Current Unit V 0.8 –0.7 VCC=Max., VI=VCC V mV –1.2 V ±1 µA ±100 Bus Hold IIL Max. 2.0 [8] VH Typ.[7] Standard VCC=Max., VI=GND Bus Hold [9] VCC=Min. ±1 µA ±100 µA VI=2.0V –50 µA VI=0.8V +50 µA IBBH IBBL Bus Hold Sustain Current on Bus Hold Input IBHHO IBHLO Bus Hold Overdrive Current on Bus Hold Input[9] VCC=Max., VI=1.5V IOZH High Impedance Output Current (Three-State Output pins) IOZL IOS TBD mA VCC=Max., VOUT=2.7V ±1 µA High Impedance Output Current (Three-State Output pins) VCC=Max., VOUT=0.5V ±1 µA Short Circuit Current[10] VCC=Max., VOUT=GND –80 –200 mA Current[10] VCC=Max., VOUT=2.5V –50 –180 mA ±1 µA Max. Unit IO Output Drive IOFF Power-Off Disable –140 VCC=0V, VOUT≤4.5V[11] Output Drive Characteristics for CY74FCT16952T Parameter VOH VOL Min. Typ.[7] VCC=Min., IOH= –3 mA 2.5 3.5 V VCC=Min., IOH= –15 mA 2.4 3.5 V VCC=Min., IOH= –32 mA 2.0 3.0 Description Output HIGH Voltage Output LOW Voltage Test Conditions VCC=Min., IOL=64 mA V 0.2 0.55 V Typ.[7] Max. Unit Output Drive Characteristics for CY74FCT162952T, CY74FCT162H952T Parameter Description Test Conditions Min. IODL Output LOW Current[10] VCC=5V, VIN=VIH or VIL, VOUT=1.5V 60 115 150 mA IODH Output HIGH Current[10] VCC=5V, VIN=VIH or VIL, VOUT=1.5V –60 –115 –150 mA VOH Output HIGH Voltage VCC=Min., IOH= –24 mA 2.4 3.3 VOL Output LOW Voltage VCC=Min., IOL=24 mA V 0.3 0.55 V Typ.[7] Max. Unit 4.5 6.0 pF Capacitance[8] (TA = +25˚C, f = 1.0 MHz) Parameter CIN Description Input Capacitance Test Conditions VIN = 0V COUT Output Capacitance VOUT = 0V 5.5 8.0 pF Note: 7. Typical values are at VCC= 5.0V, TA= +25˚C ambient. 8. This parameter is specified but not tested. 9. Pins with bus hold are described in the Pin Description. 10. Not more than one output should be shorted at a time. Duration of short should not exceed one second. The use of high-speed test apparatus and/or sample and hold techniques are preferable in order to minimize internal chip heating and more accurately reflect operational values. Otherwise prolonged shorting of a high output may raise the chip temperature well above normal and thereby cause invalid readings in other parametric tests. In any sequence of parameter tests, IOS tests should be performed last. 11. Tested at +25˚C. 3 CY74FCT16952T CY74FCT162952T CY74FCT162H952T Power Supply Characteristics Parameter Test Conditions[12] Description Typ.[7] Max. Unit 5 500 µA 0.5 1.5 mA ICC Quiescent Power Supply Current VCC=Max. VIN<0.2V VIN>VCC–0.2V ∆ICC Quiescent Power Supply Current VCC=Max. (TTL inputs HIGH) VIN=3.4V[13] ICCD Dynamic Power Supply Current[14] VCC=Max., One Input Toggling, VIN=VCC or 50% Duty Cycle, Outputs Open, VIN=GND OEAB or OEBA=GND 75 120 µA/MHz IC Total Power Supply Current[15] VCC=Max., F1=5 MHz, F0 = 10 MHz (CLKAB) OEAB = CEAB = GND OEBA = VCC 50% Duty Cycle, Outputs Open, One Bit Toggling VIN=VCC or VIN=GND 0.8 1.7 mA VIN=3.4V or VIN=GND 1.3 3.2 VIN=VCC or VIN=GND 3.8 6.5[16] VIN=3.4V or VIN=GND 8.3 20.0[16] VCC=Max., f0=10 MHz (CLKAB) f1=2.5 MHz, OEAB = CEAB = GND OEBA = VCC 50% Duty Cycle, Outputs Open, Sixteen Bit Toggling Notes: 12. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 13. Per TTL driven input (VIN=3.4V); all other inputs at VCC or GND. 14. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. = IQUIESCENT + IINPUTS + IDYNAMIC 15. IC IC = ICC+∆ICCDHNT+ICCD(f0/2 + f1N1) ICC = Quiescent Current with CMOS input levels ∆ICC = Power Supply Current for a TTL HIGH input (VIN=3.4V) DH = Duty Cycle for TTL inputs HIGH NT = Number of TTL inputs at DH ICCD = Dynamic Current caused by an input transition pair (HLH or LHL) = Clock frequency for registered devices, otherwise zero f0 = Input signal frequency f1 N1 = Number of inputs changing at f1 All currents are in milliamps and all frequencies are in megahertz. 16. Values for these conditions are examples of the ICC formula. These limits are specified but not tested. 4 CY74FCT16952T CY74FCT162952T CY74FCT162H952T Switching Characteristics Over the Operating Range[17] CY74FCT16952AT CY74FCT162952AT CY74FCT162H952AT Parameter Description CY74FCT162952BT Min. Max. Min. Max. Unit Fig. No.[18] tPLH tPHL Propagation Delay CLKAB, CLKBA to B, A 2.0 10.0 2.0 7.5 ns 1, 5 tPZH tPZL Output Enable Time OEBA, OEAB to A, B 1.5 10.5 1.5 8.0 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEBA, OEAB to A, B 1.5 10.0 1.5 7.5 ns 1, 7, 8 tSU Set-Up Time, HIGH or LOW A, B to CLKAB, CLKBA 2.5 — 2.5 — ns 4 tH Hold Time, HIGH or LOW A, B to CLKAB, CLKBA 2.0 — 1.5 — ns 4 tSU Set-Up Time, HIGH or LOW CEAB, CEBA to CLKAB, CLKBA 3.0 — 3.0 — ns 4 tH Hold Time, HIGH or LOW CEAB, CEBA to CLKAB, CLKBA 2.0 — 2.0 — ns 4 tW Pulse Width HIGH or LOW CLKAB or CLKBA[19] 3.0 — 3.0 — ns 5 tSK(O) Output Skew[20] — 0.5 — 0.5 ns — CY74FCT16952CT CY74FCT162H952CT Parameter Description Min. Max. Unit Fig. No.[18] tPLH tPHL Propagation Delay CLKAB, CLKBA to B, A 2.0 6.3 ns 1, 5 tPZH tPZL Output Enable Time OEBA, OEAB to A, B 1.5 7.0 ns 1, 7, 8 tPHZ tPLZ Output Disable Time OEBA, OEAB to A, B 1.5 6.5 ns 1, 7, 8 tSU Set-Up Time, HIGH or LOW A, B to CLKAB, CLKBA 2.5 — ns 4 tH Hold Time, HIGH or LOW A, B to CLKAB, CLKBA 1.5 — ns 4 tSU Set-Up Time, HIGH or LOW CEAB, CEBA to CLKAB, CLKBA 3.0 — ns 4 tH Hold Time, HIGH or LOW CEAB, CEBA to CLKAB, CLKBA 2.0 — ns 4 tW Pulse Width HIGH or LOW CLKAB or CLKBA[19] 3.0 — ns 5 tSK(O) Output Skew[20] — 0.5 ns — Notes: 17. Minimum limits are specified but not tested on Propagation Delays. 18. See “Parameter Measurement Information” in the General Information section. 19. This parameter is specified but not tested. 20. Skew between any two outputs of the same package switching in the same direction. This parameter is ensured by design. 5 CY74FCT16952T CY74FCT162952T CY74FCT162H952T Ordering Information CY74FCT16952 Speed (ns) Ordering Code Package Name Package Type Operating Range 6.3 CY74FCT16952CTPACT Z56 56-Lead (240-Mil) TSSOP Industrial 10.0 CY74FCT16952ATPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial Ordering Information CY74FCT162952 Speed (ns) 7.5 10.0 Ordering Code Package Name Package Type CY74FCT162952BTPVC O56 56-Lead (300-Mil) SSOP 74FCT162952BTPVCT O56 56-Lead (300-Mil) SSOP 74FCT162952ATPACT Z56 56-Lead (240-Mil) TSSOP Operating Range Industrial Industrial Ordering Information CY74FCT162H952 Speed (ns) Ordering Code Package Name Package Type Operating Range 6.3 74FCT162H952CTPVC/PVCT O56 56-Lead (300-Mil) SSOP Industrial 10.0 74FCT162H952ATPACT Z56 56-Lead (240-Mil) TSSOP Industrial 6 CY74FCT16952T CY74FCT162952T CY74FCT162H952T Package Diagrams 56-Lead Shrunk Small Outline Package O56 56-Lead Thin Shrunk Small Outline Package Z56 7 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty 74FCT162952BTPVCG4 ACTIVE SSOP DL 56 74FCT162952ETPACT OBSOLETE TSSOP DGG 74FCT162952ETPVCT OBSOLETE SSOP DL 74FCT162H952ETPAC OBSOLETE TSSOP 74FCT162H952ETPACT OBSOLETE 74FCT16952ATPVCG4 ACTIVE 74FCT16952CTPACTE4 20 Lead/Ball Finish MSL Peak Temp (3) Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 56 TBD Call TI Call TI 56 TBD Call TI Call TI DGG 56 TBD Call TI Call TI TSSOP DGG 56 Call TI SSOP DL 56 ACTIVE TSSOP DGG 74FCT16952CTPACTG4 ACTIVE TSSOP CY74FCT162952BTPVC ACTIVE CY74FCT162952ETPAC TBD Call TI Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM SSOP DL 56 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM OBSOLETE TSSOP DGG 56 TBD Call TI Call TI CY74FCT162952ETPVC OBSOLETE SSOP DL 56 Call TI CY74FCT16952ATPVC ACTIVE SSOP DL 56 CY74FCT16952CTPACT ACTIVE TSSOP DGG 56 CY74FCT16952ETPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI CY74FCT16952ETPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI 20 20 TBD Call TI Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 20 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 11-Nov-2009 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device CY74FCT16952CTPACT Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CY74FCT16952CTPACT TSSOP DGG 56 2000 346.0 346.0 41.0 Pack Materials-Page 2 MECHANICAL DATA MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001 DL (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0.025 (0,635) 0.0135 (0,343) 0.008 (0,203) 48 0.005 (0,13) M 25 0.010 (0,25) 0.005 (0,13) 0.299 (7,59) 0.291 (7,39) 0.420 (10,67) 0.395 (10,03) Gage Plane 0.010 (0,25) 1 0°–ā8° 24 0.040 (1,02) A 0.020 (0,51) Seating Plane 0.110 (2,79) MAX 0.004 (0,10) 0.008 (0,20) MIN PINS ** 28 48 56 A MAX 0.380 (9,65) 0.630 (16,00) 0.730 (18,54) A MIN 0.370 (9,40) 0.620 (15,75) 0.720 (18,29) DIM 4040048 / E 12/01 NOTES: A. B. C. D. All linear dimensions are in inches (millimeters). This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15). Falls within JEDEC MO-118 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 MECHANICAL DATA MTSS003D – JANUARY 1995 – REVISED JANUARY 1998 DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 48 PINS SHOWN 0,27 0,17 0,50 48 0,08 M 25 6,20 6,00 8,30 7,90 0,15 NOM Gage Plane 1 0,25 24 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 48 56 64 A MAX 12,60 14,10 17,10 A MIN 12,40 13,90 16,90 DIM 4040078 / F 12/97 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold protrusion not to exceed 0,15. Falls within JEDEC MO-153 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PACKAGE OPTION ADDENDUM www.ti.com 24-Apr-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) 74FCT162952ETPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 74FCT162952ETPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 74FCT162H952ETPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 74FCT162H952ETPACT OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 74FCT16952ATPVCG4 ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT16952A CY74FCT162952BTPVC ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT162952B CY74FCT162952ETPAC OBSOLETE TSSOP DGG 56 TBD Call TI Call TI -40 to 85 CY74FCT162952ETPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 CY74FCT16952ATPVC ACTIVE SSOP DL 56 20 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT16952A CY74FCT16952CTPACT ACTIVE TSSOP DGG 56 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 FCT16952C CY74FCT16952ETPVC OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 CY74FCT16952ETPVCT OBSOLETE SSOP DL 56 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com (4) 24-Apr-2015 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CY74FCT16952CTPACT Package Package Pins Type Drawing TSSOP DGG 56 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 8.6 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.6 1.8 12.0 24.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CY74FCT16952CTPACT TSSOP DGG 56 2000 367.0 367.0 45.0 Pack Materials-Page 2 PACKAGE OUTLINE DGG0056A TSSOP - 1.2 mm max height SCALE 1.200 SMALL OUTLINE PACKAGE C 8.3 TYP 7.9 SEATING PLANE PIN 1 ID AREA A 0.1 C 54X 0.5 56 1 14.1 13.9 NOTE 3 2X 13.5 28 B 6.2 6.0 29 56X 0.27 0.17 0.08 1.2 MAX C A B (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4222167/A 07/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 28 29 (7.5) LAND PATTERN EXAMPLE SCALE:6X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS 4222167/A 07/2015 NOTES: (continued) 5. Publication IPC-7351 may have alternate designs. 6. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN DGG0056A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 56X (1.5) SYMM 1 56 56X (0.3) 54X (0.5) (R0.05) TYP SYMM 29 28 (7.5) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:6X 4222167/A 07/2015 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 8. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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