256K X 36, 512K X 18 3.3V Synchronous SRAMs AS8C803600 3.3V I/O, Burst Counter AS8C801800 Pipelined Outputs, Single Cycle Deselect Features ◆ ◆ 256K x 36 / 512K x 18. The SRAMs contain write, data, address and control registers. Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the AS8C803600/801800 can provide four cycles of data for a single address presented to the SRAM. An internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. The first cycle of output data will be pipelined for one cycle before it is available on the next rising clock edge. If burst mode operation is selected (ADV=LOW), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. The order of these three addresses are defined by the internal burst counter and the LBO input pin. The AS8C803600/801800 SRAMs utilize the latest high-performance CMOS process and are packaged in a JEDEC standard 14mm x 20mm 100pin thin plastic quad flatpack (TQFP), 256K x 36, 512K x 18 memory configurations Supports high system speed: – 150MHz 3.8ns clock access time ◆ ◆ ◆ ◆ ◆ ◆ LBO input selects interleaved or linear burst mode Self-timed write cycle with global write control (GW), byte write enable (BWE), and byte writes (BWx) 3.3V core power supply Power down controlled by ZZ input 3.3V I/O supply (VDDQ) Packaged in a JEDEC Standard 100-pin thin plastic quad flatpack (TQFP) Description The AS8C803600/801800 are high-speed SRAMs organized as Pin Description Summary A0-A 18 Address Inputs Input Synchronous CE Chip Enable Input Synchronous CS0, CS1 Chip Selects Input Synchronous OE Output Enable Input Asynchronous GW Global Write Enable Input Synchronous BWE Byte Write Enable Input Synchronous BW1, BW2, BW3, BW4(1) Individual Byte Write Selects Input Synchronous CLK Clock Input N/A ADV Burst Address Advance Input Synchronous ADSC Address Status (Cache Controller) Input Synchronous ADSP Address Status (Processor) Input Synchronous LBO Linear / Interleaved Burst Order Input DC ZZ Sleep Mode Input Asynchronous I/O0-I/O31, I/OP1-I/OP4 Data Input / Output I/O Synchronous VDD, V DDQ Core Power, I/O Power Supply N/A VSS Ground Supply N/A NOTE: 1. BW3 and BW4 are not applicable for other devices 5310 tbl 01 September 2010 1 . AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range Pin Definitions(1) Symbol Pin Function I/O Active Description A0-A18 Address Inputs I N/A Synchronous Address inputs. The address register is triggered by a combination of the rising edge of CLK and ADSC Low or ADSP Low and CE Low. ADSC Address Status (Cache Controller) I LOW Synchronous Address Status from Cache Controller. ADSC is an active LOW input that is used to load the address registers with new addresses. ADSP Address Status (Processor) I LOW Synchronous Address Status from Processor. ADSP is an active LOW input that is used to load the address registers with new addresses. ADSP is gated by CE. ADV Burst Address Advance I LOW Synchronous Address Advance. ADV is an active LOW input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. When the input is HIGH the burst counter is not incremented; that is, there is no address advance. BWE Byte Write Enable I LOW Synchronous byte write enable gates the byte write inputs BW1-BW4. If BWE is LOW at the rising edge of CLK then BWx inputs are passed to the next stage in the circuit. If BWE is HIGH then the byte write inputs are blocked and only GW can initiate a write cycle. BW1-BW4 Individual Byte Write Enables I LOW Synchronous byte write enables. BW1 controls I/O0-7, I/OP1, BW2 controls I/O8-15, I/OP2, etc. Any active byte write causes all outputs to be disabled. CE Chip Enable I LOW Synchronous chip enable. CE is used with CS 0 and CS1 to enable the IDT71V67603/7803. CE also gates ADSP. CLK Clock I N/A This is the clock input. All timing references for the device are made with respect to this input. CS 0 Chip Select 0 I HIGH Synchrono us active HIGH chip select. CS0 is used with CE and CS1 to enable the chip. CS1 Chip Select 1 I LOW Synchronous active LOW chip select. CS1 is used with CE and CS0 to enable the chip. GW Global Write Enable I LOW Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on the rising edge of CLK. GW supersedes individual byte write enables. I/O0-I/O31 I/OP1-I/OP4 Data Input/Output I/O N/A Synchronous data input/output (I/O) pins. Both the data input path and data output path are registered and triggered by the rising edge of CLK. LBO Linear Burst Order I LOW Asynchronous burst order selection input. When LBO is HIGH, the interleaved burst sequence is selected. When LBO is LOW the Line ar burst sequence is selected. LBO is a static input and must not change state while the device is operating. OE Output Enable I LOW Asynchronous output enable. When OE is LOW the data output drivers are enabled on the I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a highimpedance state. VDD Power Supply N/A N/A 3.3V core power supply. VDDQ Power Supply N/A N/A 3.3V I/O Supply. VSS Ground N/A N/A Ground. NC No Connect N/A N/A NC pins are not electrically connected to the device. ZZ Sleep Mode I HIGH Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the AS8C803600/1800 to its lowest power consumption level. Data retention is guaranteed in Sleep Mode. NOTE: 1. All synchronous inputs must meet specified setup and hold times with respect to CLK. 6.42 2 5310 tbl 02 AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range Functional Block Diagram LBO ADV CLK 2 Binary Counter ADSC Burst Logic Q0 CLR ADSP Q1 ADDRESS REGISTER 18/19 A0* A1* 256K x 36/ 512K x 18BIT MEMORY ARRAY 2 CLK EN A0–A17/18 GW BWE INTERNAL ADDRESS Burst Sequence CEN A0,A1 A2–A18 36/18 18/19 Byte 1 Write Register 36/18 Byte 1 Write Driver BW1 9 Byte 2 Write Register Byte 2 Write Driver BW2 9 Byte 3 Write Register Byte 3 Write Driver BW3 9 Byte 4 Write Register Byte 4 Write Driver BW4 9 OUTPUT REGISTER CE CS0 CS1 D Q Enable Register DATA INPUT REGISTER CLK EN ZZ Powerdown D Q Enable Delay Register OE OE I/O0–I/O31 I/OP1–I/OP4 OUTPUT BUFFER 36/18 5301 drw 01 6.42 3 , AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Absolute Maximum Ratings(1) Symbol (2) Rating Commercial Unit Commercial Temperature Range Recommended Operating Temperature and Supply Voltage Grade Temperature(1) VSS VDD V DDQ Commercial 0°C to +70°C 0V 3.3V±5% 3.3V±5% Industrial -40°C to +85°C 0V 3.3V±5% 3.3V±5% VTERM Terminal Voltage with Respect to GND -0.5 to +4.6 V VTERM(3,6) Terminal Voltage with Respect to GND -0.5 to VDD V VTERM(4,6) Terminal Voltage with Respect to GND -0.5 to VDD +0.5 V NOTE: 1. TA is the "instant on" case temperature. VTERM(5,6) Terminal Voltage with Respect to GND -0.5 to VDDQ +0.5 V Recommended DC Operating Conditions TA(7) Operating Temperature -0 to +70 o C C TBIAS Temperature Under Bias -55 to +125 o TSTG Storage Temperature -55 to +125 o Power Dissipation PT 2.0 DC Output Current IOUT Symbol C W 50 5310 tbl 03 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VDD terminals only. 3. VDDQ terminals only. 4. Input terminals only. 5. I/O terminals only. 6. This is a steady-state DC parameter that applies after the power supplies have ramped up. Power supply sequencing is not necessary; however, the voltage on any input or I/O pin cannot exceed V DDQ during power supply ramp up. 7. TA is the "instant on" case temperature. Parameter CIN Input Capacitance CI/O I/O Capacitance Input Capacitance CI/O I/O Capacitance 3.135 3.3 3.465 V VDDQ I/O Supply Voltage 3.135 3.3 3.465 V V SS Supply Voltage 0 0 0 V V IH Input High Voltage - Inputs 2.0 ____ VDD +0.3 V V IH Input High Voltage - I/O 2.0 ____ V DDQ +0.3 V ____ 0.8 V Input Low Voltage Parameter(1) Conditions Max. Unit Symbol VIN = 3dV 5 pF CIN Input Capacitance VOUT = 3dV 7 pF CI/O I/O Capacitance (TA = +25°C, f = 1.0MHz) CIN Core Supply Voltage (1) -0.3 5310 tbl 05 119 BGA Capacitance Parameter(1) Unit NOTE: 1. VIL (min) = -1.0V for pulse width less than tCYC/2, once per cycle. 5310 tbl 07 Symbol Max. (TA = +25°C, f = 1.0MHz) (TA = +25°C, f = 1.0MHz) Symbol Typ. 165 fBGA Capacitance 100 Pin TQFP Ca pacitance (1) Min. V DD V IL mA Parameter 5310 tbl 04 Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 7 pF 5310 tbl 07a NOTE: 1. This parameter is guaranteed by device characterization, but not production tested. 6.42 4 Conditions Max. Unit VIN = 3dV 7 pF VOUT = 3dV 7 pF 5310 tbl 07b IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges A6 A7 CE CS0 BW4 BW3 BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 Pin Configuration – 256K x 36, 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 I/OP3 I/O16 I/O17 VDDQ VSS I/O18 I/O19 I/O20 I/O21 VSS VDDQ I/O22 I/O23 VDD / NC(1) VDD NC VSS I/O24 I/O25 VDDQ VSS I/O26 I/O27 I/O28 I/O29 VSS VDDQ I/O30 I/O31 I/OP4 1 80 2 79 3 78 4 77 5 76 6 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 19 63 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 54 28 53 29 52 51 30 I/OP2 I/O15 I/O14 VDDQ VSS I/O13 I/O12 I/O11 I/O10 VSS VDDQ I/O9 I/O8 VSS NC VDD ZZ(2) I/O7 I/O6 VDDQ VSS I/O5 I/O4 I/O3 I/O2 VSS VDDQ I/O1 I/O0 I/OP1 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC VSS VDD NC A17 A10 A11 A12 A13 A14 A15 A16 LBO A5 A4 A3 A2 A1 A0 5301 drw 02 Top View NOTES: 1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected. 2. Pin 64 can be left unconnected and the device will always remain in active mode. 6.42 5 , IDT71V67603, IDT71V67803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial and Industrial Temperature Ranges A6 A7 CE CS0 NC NC BW2 BW1 CS1 VDD VSS CLK GW BWE OE ADSC ADSP ADV A8 A9 Pin Configuration – 512K x 18, 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 NC NC NC 1 80 2 79 3 78 VDDQ VSS NC NC I/O8 I/O9 VSS VDDQ I/O10 I/O11 VDD / NC(1) VDD NC VSS I/O12 I/O13 VDDQ VSS I/O14 I/O15 I/OP2 NC VSS VDDQ NC NC NC 4 77 5 76 6 75 7 74 8 73 9 72 71 10 11 70 12 69 13 68 14 67 15 66 16 65 17 64 18 63 19 62 20 61 21 60 22 59 23 58 24 57 25 56 26 55 27 28 54 53 29 52 51 30 A10 NC NC VDDQ VSS NC I/OP1 I/O7 I/O6 VSS VDDQ I/O5 I/O4 VSS NC VDD ZZ(2) I/O3 I/O2 VDDQ VSS I/O1 I/O0 NC NC VSS VDDQ NC NC NC 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 LBO A5 A4 A3 A2 A1 A0 NC NC VSS VDD NC A18 A11 A12 A13 A14 A15 A16 A17 5310 drw 03 Top View NOTES: 1. Pin 14 can either be directly connected to VDD, or connected to an input voltage ≥ VIH, or left unconnected. 2. Pin 64 can be left unconnected and the device will always remain in active mode. 6.42 6 , AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range (VDD = 3.3V ± 5%) Symbol Parameter Test Conditions Min. Max. Unit |ILI| Input Leakage Current VDD = Max., VIN = 0V to V DD ___ 5 µA |ILZZ| ZZ and LBO Input Leakage Current(1) VDD = Max., VIN = 0V to V DD ___ 30 µA |ILO| Output Leakage Current VOUT = 0V to V DDQ, Device Deselected ___ 5 µA 0.4 V ___ V VOL Output Low Voltage IOL = +8mA, VDD = Min. ___ VOH Output High Voltage IOH = -8mA, VDD = Min. 2.4 5310 tbl 08 NOTE: 1. The LBO pin will be internally pulled to VDD if it is not actively driven in the application and the ZZ pin will be internally pulled to VSS if not actively driven. DC Electrical Characteristics Over the Operating Temperature and Supply Voltage Range(1) 166MHz Symbol Parameter 150MHz 133MHz Unit Test Conditions Com'l only Com'l Ind Com'l Ind IDD Operating Power Supply Current Device Selected, Outputs Open, VDD = Max., VDDQ = Max., VIN > VIH or < VIL, f = fMAX(2) 340 305 325 260 280 ISB1 CMOS Standby Power Supply Current Device Deselected, Outputs Open, V DD = Max., VDDQ = Max., VIN > VHD or < VLD, f = 0(2,3) 50 50 70 50 70 ISB2 Clock Running Power Supply Current Device Deselected, Outputs Open, V DD = Max., VDDQ = Max., VIN > VHD or < VLD, f = fMAX(2,3) 160 155 175 150 170 IZZ Full Sleep Mode Supply Current ZZ > VHD, VDD = Max. 50 50 70 50 70 mA mA mA mA 5310 tbl 09 NOTES: 1. All values are maximum guaranteed values. 2. At f = fMAX, inputs are cycling at the maximum frequency of read cycles of 1/tCYC while ADSC = LOW; f=0 means no input lines are changing. 3. For I/Os VHD = VDDQ - 0.2V, VLD = 0.2V. For other inputs VHD = V DD - 0.2V, VLD = 0.2V. AC Test Conditions AC Test Load (VDDQ = 3.3V) Input Pulse Levels 50Ω 0 to 3V Input Rise/Fall Times 2ns Input Timing Reference Levels 1.5V Output Timing Reference Levels AC Test Load VDDQ/2 I/O Z0 = 50Ω 5310 drw 06 , Figure 1. AC Test Load 1.5V 6 See Figure 1 5 5310 tbl 10 4 ∆tCD 3 (Typical, ns) 2 1 20 30 50 80 100 Capacitance (pF) 200 5310 drw 07 Figure 2. Lumped Capacitive Load, Typical Derating 6.427 , AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range Synchronous Truth Table(1,3) Address Used CE CS0 CS 1 ADSP ADSC ADV GW BWE BWx OE (2) CLK I/O Deselected Cycle, Power Down None H X X X L X X X X X - HI-Z Deselected Cycle, Power Down None L X H L X X X X X X - HI-Z Deselected Cycle, Power Down None L L X L X X X X X X - HI-Z Deselected Cycle, Power Down None L X H X L X X X X X - HI-Z Deselected Cycle, Power Down None L L X X L X X X X X - HI-Z Read Cycle, Begin Burst External L H L L X X X X X L - DOUT Read Cycle, Begin Burst External L H L L X X X X X H - HI-Z Read Cycle, Begin Burst External L H L H L X H H X L - DOUT Read Cycle, Begin Burst External L H L H L X H L H L - DOUT Read Cycle, Begin Burst External L H L H L X H L H H - HI-Z Write Cycle, Begin Burst External L H L H L X H L L X - DIN Write Cycle, Begin Burst External L H L H L X L X X X - DIN Read Cycle, Continue Burst Next X X X H H L H H X L - DOUT Read Cycle, Continue Burst Next X X X H H L H H X H - HI-Z Read Cycle, Continue Burst Next X X X H H L H X H L - DOUT Read Cycle, Continue Burst Next X X X H H L H X H H - HI-Z Read Cycle, Continue Burst Next H X X X H L H H X L - DOUT Read Cycle, Continue Burst Next H X X X H L H H X H - HI-Z Read Cycle, Continue Burst Next H X X X H L H X H L - DOUT Read Cycle, Continue Burst Next H X X X H L H X H H - HI-Z Write Cycle, Continue Burst Next X X X H H L H L L X - DIN Write Cycle, Continue Burst Next X X X H H L L X X X - DIN Write Cycle, Continue Burst Next H X X X H L H L L X - DIN Write Cycle, Continue Burst Next H X X X H L L X X X - DIN Read Cycle, Suspend Burst Current X X X H H H H H X L - DOUT Read Cycle, Suspend Burst Current X X X H H H H H X H - HI-Z Read Cycle, Suspend Burst Current X X X H H H H X H L - DOUT Read Cycle, Suspend Burst Current X X X H H H H X H H - HI-Z Read Cycle, Suspend Burst Current H X X X H H H H X L - DOUT Read Cycle, Suspend Burst Current H X X X H H H H X H - HI-Z Read Cycle, Suspend Burst Current H X X X H H H X H L - DOUT Read Cycle, Suspend Burst Current H X X X H H H X H H - HI-Z Write Cycle, Suspend Burst Current X X X H H H H L L X - DIN Write Cycle, Suspend Burst Current X X X H H H L X X X - DIN Write Cycle, Suspend Burst Current H X X X H H H L L X - DIN Write Cycle, Suspend Burst Current H X X X H H L X X X - Operation DIN 5310 tbl 11 NOTES: 1. L = VIL, H = VIH, X = Don’t Care. 2. OE is an asynchronous input. 3. ZZ = low for this table. 6.428 AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Synchronous Write Function T ruth Table Commercial Temperature Range (1, 2) Operation GW BWE BW1 BW2 BW3 BW4 Read H H X X X X Read H L H H H H Write all Bytes L X X X X X Write all Bytes H L L L L L (3) H L L H H H (3) H L H L H H (3) H L H H L H (3) H L H H H L Write Byte 1 Write Byte 2 Write Byte 3 Write Byte 4 5310 tbl 12 NOTES: 1. L = VIL, H = V IH, X = Don’t Care. 2. BW3 and BW4 are not applicable other devices 3. Multiple bytes may be selected during the same cycle. Asynchronous Truth Table(1) Operation(2) OE ZZ I/O Status Power Read L L Data Out Active Read H L High-Z Active Write X L High-Z – Data In Active Deselected X L High-Z Standby Sleep Mode X H High-Z Sleep 5310 tbl 13 NOTES: 1. L = VIL, H = V IH, X = Don’t Care. 2. Synchronous function pins must be biased appropriately to satisfy operation requirements. Interleaved Burst SequenceTable (LBO=VDD) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 0 0 1 1 1 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 1 1 1 0 0 1 0 0 5310 tbl 14 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. Linear Burst Sequence Table (LBO=VSS) Sequence 1 Sequence 2 Sequence 3 Sequence 4 A1 A0 A1 A0 A1 A0 A1 A0 First Address 0 0 0 1 1 0 1 1 Second Address 0 1 1 0 1 1 0 0 Third Address 1 0 1 1 0 0 0 1 Fourth Address (1) 1 1 0 0 0 1 1 0 NOTE: 1. Upon completion of the Burst sequence the counter wraps around to its initial state. 9 5310 tbl 15 AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range AC Electrical Characteristics (VDD = 3.3V ±5%, Commercial and Industrial Temperature Ranges) 166MHz Symbol Parameter 150MHz 133MHz Min. Max. Min. Max. Min. Max. Unit 6 ____ 6.7 ____ 7.5 ____ ns tCYC Clock Cycle Time tCH(1) Clock High Pulse Width 2.4 ____ 2.6 ____ 3 ____ ns tCL(1) Clock Low Pulse Width 2.4 ____ 2.6 ____ 3 ____ ns Output Parameters tCD Clock High to Valid Data ____ 3.5 ____ 3.8 ____ 4.2 ns tCDC Clock High to Data Change 1.5 ____ 1.5 ____ 1.5 ____ ns tCLZ(2) Clock High to Output Active 0 ____ 0 ____ 0 ____ ns tCHZ(2) Clock High to Data High-Z 1.5 3.5 1.5 3.8 1.5 4.2 ns tOE Output Enable Access Time ____ 3.5 ____ 3.8 ____ 4.2 ns 0 ____ 0 ____ 0 ____ ns ____ 3.5 ____ 3.8 ____ 4.2 ns (2) tOLZ Output Enable Low to Output Active tOHZ(2) Output Enable High to Output High-Z Set Up Times tSA Address Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns tSS Address Status Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns 1.5 ____ 1.5 ____ ns tSD Data In Setup Time 1.5 ____ tSW Write Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns tSAV Address Advance Setup Time 1.5 ____ 1.5 ____ 1.5 ____ ns 1.5 ____ 1.5 ____ 1.5 ____ ns tSC Chip Enable/Select Setup Time Hold Times tHA Address Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHS Address Status Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ ns tHD Data In Hold Time 0.5 ____ tHW Write Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns tHAV Address Advance Hold Time 0.5 ____ 0.5 ____ 0.5 ____ ns 0.5 ____ 0.5 ____ 0.5 ____ ns tHC Chip Enable/Select Hold Time Sleep Mode and Configuration Parameters tZZPW ZZ Pulse Width 100 ____ 100 ____ 100 ____ ns tZZR(3) ZZ Recovery Time 100 ____ 100 ____ 100 ____ ns tCFG (4) Configuration Set-up Time 24 ____ 27 ____ 30 ____ ns 5310 tbl 16 NOTES: 1. Measured as HIGH above VIH and LOW below VIL. 2. Transition is measured ±200mV from steady-state. 3. Device must be deselected when powered-up from sleep mode. 4. tCFG is the minimum time required to configure the device based on the LBO input. LBO is a static input and must not change during normal operation. 6.42 10 AS8C803600, AS8C801800, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with 3.3V I/O, Pipelined Outputs, Single Cycle Deselect Commercial Temperature Range 100-Pin Plastic Thin Quad Flatpack (TQFP) Package Diagram Outline 17 6.17 ORDERING INFORMATION Alliance Organization VCC Range AS8C803600-QC150N 256K x 36 3.1 - 3.4V 100 pin TQFP Comercial: 0 - 70C 150 AS8C801800-QC150N 512K x 18 3.1 - 3.4V 100 pin TQFP Comercial: 0 - 70C 150 Package Speed Mhz Operating Temp 1. EMLSI Memory 2. Device Type 3. Density 4. Function 5. Technology 6. Operating Voltage 11. Power 10. Speed 9. Package 8. Version 7. Organization PART NUMBERING SYSTEM AS8C Sync. SRAM prefix 'HYLFH &RQI 80 = 8M 18= x18 36 = x36 0RGH3DFNDJH2SHUDWLQJ7HPS1 Speed Q = 100 Pin TQFP 01= ZBT 00 = Pipelined 25 = Flow- Thru 0 ~ 70C 150MHz N= Leadfree ORDERING INFORMATION Alliance VCC Range Organization AS6C8016A -55ZIN 512K x 16 AS6C8016A -55BIN Package 2.7 - 5.5V 512K x 16 2.7 - 5.5V Speed ns Operating Temp 44pin TSOP II Industrial ~ -40 C - 85 C 55 48ball FBGA Industrial ~ -40 C - 85 C 55 PART NUMBERING SYSTEM AS6C 8016 -55 Device Number low power SRAM prefix ® Alliance Memory, Inc. 551 Taylor way, suite#1, San Carlos, CA 94070 Tel: 650-610-6800 Fax: 650-620-9211 Copyright © Alliance Memory All Rights Reserved 19 www.alliancememory.com Part Number: AS8C803600/801800 Document Version: v. 1.0 © Copyright 2003 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their respective companies. Alliance reserves the right to make changes to this document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right to change or correct this data at any time, without notice. If the product described herein is under development, significant changes to these specifications are possible. The information in this product data sheet is intended to be general descriptive information for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of the application or use of any product described herein, and disclaims any express or implied warranties related to the sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such use and agrees to indemnify Alliance against all claims arising from such use. 618.42 80 = 8M 16 = x16 Access Time X X Package Option Temperature Range Z - 44pin TSOP I = Industrial B = 48ball TFBGA (-40 to + 85 C) N N = Lead Free RoHS compliant part