TI1 LMR33630ADDA Simple switcher 3.8-v to 36-v, 3-a synchronous step-down voltage converter Datasheet

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LMR33630
SNVSAN3B – AUGUST 2017 – REVISED APRIL 2018
LMR33630 SIMPLE SWITCHER® 3.8-V to 36-V, 3-A
Synchronous Step-Down Voltage Converter
1 Features
3 Description
•
The LMR33630 SIMPLE SWITCHER® regulator is an
easy-to-use,
synchronous,
step-down
DC/DC
converter that delivers best-in-class efficiency for
rugged industrial applications. The LMR33630 is
capable of driving up to 3 A of load current from an
input of up to 36 V. The LMR33630 provides high
light load efficiency and output accuracy in a very
small solution size. Features such as a power-good
flag and precision enable provide both flexible and
easy-to-use solutions for a wide range of applications.
The LMR33630 automatically folds back frequency at
light load to improve efficiency. Integration eliminates
most external components and provides a pinout
designed for simple PCB layout. Protection features
include thermal shutdown, input undervoltage lockout,
cycle-by-cycle current limit, and hiccup short-circuit
protection. The LMR33630 is available in an 8-pin
HSOIC package and in a 12-pin 3 mm × 2 mm VQFN
package with wettable flanks.
1
•
•
•
Configured for Rugged Industrial Applications
– Input Voltage Range: 3.8 V to 36 V
– Output Voltage Range: 1 V to 24 V
– Output Current: 3 A
– 75 mΩ/50 mΩ Low RDS-ON Power MOSFETs
– Peak-Current-Mode Control
– Short Minimum On-Time of 68 ns
– Frequency: 400 kHz, 1.4 MHz, 2.1 MHz
– Junction Temperature Range –40°C to +125°C
– Integrated Synchronous Rectification
– Integrated Compensation Network
High Efficiency Solution
– Peak Efficiency > 95%
– Low Shutdown Quiescent Current of 5 µA
– Low Operating Quiescent Current of 25 µA
Flexible System Interface
– Power-Good Flag and Precision Enable
Create a Custom Design Using the LMR33630
with the WEBENCH® Power Designer
•
•
PART NUMBER
PACKAGE
BODY SIZE (NOM)
LMR33630
HSOIC (8)
5.00 mm × 4.00 mm
LMR33630
VQFN (12)
3.00 mm × 2.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
2 Applications
•
Device Information(1)
Motor Drive Systems: Drones, AC Inverters,
VF Drives, Servos
Factory and Building Automation Systems:
PLC CPU, HVAC Control, Elevator Control
General Purpose Wide VIN Power Supplies
space
space
space
space
space
Simplified Schematic
Efficiency vs Output Current
VOUT = 5 V, 400 kHz, VQFN
BOOT
VIN
CIN
100
CBOOT
EN
SW
L1
90
COUT
PGND
VCC
95
VOUT
PG
RFBT
CVCC
Efficiency (%)
VIN
85
80
75
8V
70
FB
AGND
RFBB
12V
65
24V
60
36V
55
0.01
0.1
Output Current (A)
1
10
C021
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LMR33630
SNVSAN3B – AUGUST 2017 – REVISED APRIL 2018
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Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Device Comparison Table.....................................
Pin Configuration and Functions .........................
Specifications.........................................................
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
8
1
1
1
2
3
3
5
Absolute Maximum Ratings ...................................... 5
ESD Ratings.............................................................. 5
Recommended Operating Conditions ...................... 5
Thermal Information .................................................. 6
Electrical Characteristics........................................... 6
Timing Characteristics............................................... 8
System Characteristics ............................................. 9
Typical Characteristics ............................................ 10
Detailed Description ............................................ 11
8.1 Overview ................................................................. 11
8.2 Functional Block Diagram ....................................... 11
8.3 Feature Description................................................. 12
8.4 Device Functional Modes........................................ 16
9
Application and Implementation ........................ 19
9.1 Application Information............................................ 19
9.2 Typical Application .................................................. 19
9.3 Do's and Don'ts ....................................................... 31
10 Power Supply Recommendations ..................... 32
11 Layout................................................................... 33
11.1 Layout Guidelines ................................................. 33
11.2 Layout Example .................................................... 35
12 Device and Documentation Support ................. 37
12.1
12.2
12.3
12.4
12.5
12.6
12.7
Device Support ....................................................
Documentation Support ........................................
Receiving Notification of Documentation Updates
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
37
37
37
37
38
38
38
13 Mechanical, Packaging, and Orderable
Information ........................................................... 38
4 Revision History
Changes from Revision A (February 2018) to Revision B
•
Added WSON information throughout data sheet .................................................................................................................. 1
Changes from Original (August 2017) to Revision A
•
2
Page
Page
First release of production-data data sheet ........................................................................................................................... 1
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5 Device Comparison Table
DEVICE NUMBER
PACKAGE
FREQUENCY
RATED CURRENT
400 kHz
3A
1400 kHz
3A
LMR33630CDDA
2100 kHz
3A
LMR33630ARNX
400 kHz
3A
1400 kHz
3A
2100 kHz
3A
LMR33630ADDA
LMR33630BDDA
LMR33630BRNX
DDA (8-pin HSOIC)
5.0 × 4.0 mm
RNX (12-pin VQFN)
3.0 × 2.0 × 0.85 mm
LMR33630CRNX
OUTPUT VOLTAGE
Adjustable
Adjustable
6 Pin Configuration and Functions
DDA Package
8-Pin HSOIC With PowerPAD™
Top View
PGND
1
VIN
2
8
SW
7
BOOT
THERMAL PAD
EN
3
6
VCC
PG
4
5
FB
Not to scale
RNX Package
12-Pin VQFN
Top View
SW
12
PGND 1
11 PGND
VIN
2
10 VIN
NC
3
9 EN
BOOT
4
8 PG
5
VCC
6
7
AGND
FB
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Pin Functions
PIN
HSOIC
TYPE
DESCRIPTION
VQFN
NAME
1
1,11
PGND
G
Power ground terminal. Connect to system ground and AGND. Connect to CIN with
short wide traces.
2
2,10
VIN
P
Input supply to regulator. Connect a high-quality bypass capacitor(s) directly to this
pin and PGND.
3
9
EN
A
Enable input to regulator. High = ON, low = OFF. Can be connected directly to VIN;
DO NOT FLOAT.
4
8
PG
A
Open drain power-good flag output. Connect to suitable voltage supply through a
current limiting resistor. High = power OK, low = power bad. Flag pulls low when EN =
Low. Can be open or grounded when not used.
5
7
FB
A
Feedback input to regulator. Connect to tap point of feedback voltage divider. DO
NOT FLOAT. DO NOT GROUND.
6
5
VCC
P
Internal 5-V LDO output. Used as supply to internal control circuits. Do not connect to
external loads. Can be used as logic supply for power-good flag. Connect a high
quality 1-µF capacitor from this pin to GND.
7
4
BOOT
P
Boot-strap supply voltage for internal high-side driver. Connect a high-quality 100-nF
capacitor from this pin to the SW pin. On the VQFN package connect the SW pin to
NC on the PCB. This simplifies the connection from the CBOOT capacitor to the SW
pin.
8
12
SW
P
Regulator switch node. Connect to power inductor. On the VQFN package connect
the SW pin to NC on the PCB. This simplifies the connection from the CBOOT
capacitor to the SW pin.
THERMAL
PAD
6
AGND
G
Analog ground for regulator and system. Ground reference for internal references and
logic. All electrical parameters are measured with respect to this pin. Connect to
system ground on PCB. For the HSOIC package, the pad on the bottom of the device
serves as both the AGND connection and a thermal connection to the heat sink
ground plane. This pad must be soldered to a ground plane to achieve good electrical
and thermal performance.
—
3
NC
—
On the VQFN package the SW pin must be connected to NC on the PCB. This
simplifies the connection from the CBOOT capacitor to the SW pin. This pin has no
internal connection to the regulator.
A = Analog, P = Power, G = Ground
4
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7 Specifications
7.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range (1)
MIN
MAX
VIN to PGND
PARAMETER
–0.3
38
EN to AGND (2)
–0.3
VIN + 0.3
FB to AGND
–0.3
5.5
PG to AGND (2)
0
22
AGND to PGND
–0.3
0.3
SW to PGND
–0.3
VIN + 0.3
SW to PGND less than 100-ns transients
–3.5
38
BOOT to SW
–0.3
5.5
VCC to AGND (3)
–0.3
5.5
TJ
Junction temperature (4)
–40
150
°C
Tstg
Storage temperature
–55
150
°C
Voltages
(1)
(2)
(3)
(4)
UNIT
V
V
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V
Under some operating conditions the VCC LDO voltage may increase beyond 5.5V.
Operating at junction temperatures greater than 125°C, although possible, degrades the lifetime of the device.
7.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Electrostatic discharge
Human-body model (HBM)
(1)
UNIT
±2500
Charged-device model (CDM) (2)
V
±750
JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40 °C to 125 °C (unless otherwise noted)
VIN to PGND
Input voltage
EN
(2)
PG (2)
(3)
Adjustable output voltage
VOUT
Output current
IOUT
Temperature
Operating junction temperature, TJ
(1)
(2)
(3)
(4)
(4)
(1)
MIN
MAX
3.8
36
UNIT
0
VIN
0
18
1
24
0
3
A
–40
125
°C
V
V
Recommended operating conditions indicate conditions for which the device is intended to be functional, but do not ensure specific
performance limits. For ensured specifications, see Electrical Characteristics.
The voltage on this pin must not exceed the voltage on the VIN pin by more than 0.3 V.
The maximum output voltage can be extended to 95% of VIN; contact TI for details. Under no conditions should the output voltage be
allowed to fall below zero volts.
Operating at junction temperatures greater than 125℃, although possible, degrades the lifetime of the device.
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7.4 Thermal Information
LMR336x0
THERMAL METRIC (1)
(2)
DDA (HSOIC)
RNX (VQFN)
8 PINS
12 PINS
UNIT
42.9
72.5
°C/W
RθJA
Junction-to-ambient thermal resistance
RθJC(top)
Junction-to-case (top) thermal resistance
54
35.9
°C/W
RθJB
Junction-to-board thermal resistance
13.6
23.3
°C/W
ψJT
Junction-to-top characterization parameter
4.3
0.8
°C/W
ψJB
Junction-to-board characterization parameter
13.8
23.5
°C/W
RθJC(bot)
Junction-to-case (bottom) thermal resistance
4.3
N/A
°C/W
(1)
(2)
For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
The value of RθJA given in this table is only valid for comparison with other packages and can not be used for design purposes. These
values were calculated in accordance with JESD 51-7, and simulated on a 4-layer JEDEC board. They do not represent the
performance obtained in an actual application. For design information see Maximum Ambient Temperature.
7.5 Electrical Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY VOLTAGE
VIN
Minimum operating input
voltage
IQ
Non-switching input
current; measured at VIN
pin (1)
VFB = 1.2 V
ISD
Shutdown quiescent
current; measured at VIN
pin
EN = 0
VEN-VCC-H
EN input level required to
turn on internal LDO
Rising threshold
VEN-VCC-L
EN input level required to
turn off internal LDO
Falling threshold
0.3
VEN-H
EN input level required to
start switching
Rising threshold
1.2
VEN-HYS
Hysteresis below VEN-H
Hysteresis below VEN-H; falling
100
mV
ILKG-EN
Enable input leakage
current
VEN = 3.3 V
0.2
nA
3.8
V
24
34
µA
5
10
µA
1
V
ENABLE
V
1.231
1.26
V
INTERNAL SUPPLIES
VCC
Internal LDO output
voltage appearing at the
VCC pin
VBOOT-UVLO
Bootstrap voltage
undervoltage lock-out
threshold (2)
6 V ≤ VIN ≤ 36 V
4.75
5
5.25
2.2
V
V
VOLTAGE REFERENCE (FB PIN)
VFB
Feedback voltage
IFB
Current into FB pin
0.985
FB = 1 V
1
1.015
V
0.2
50
nA
4.5
5.05
A
CURRENT LIMITS (3)
ISC
(1)
(2)
(3)
6
High-side current limit
LMR33630
3.85
This is the current used by the device open loop. It does not represent the total input current of the system when in regulation.
When the voltage across the CBOOT capacitor falls below this voltage, the low side MOSFET is turned on to recharge CBOOT.
The current limit values in this table are tested, open loop, in production. They may differ from those found in a closed loop application.
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
ILIMIT
Low-side current limit
LMR33630
IPEAK-MIN
Minimum peak inductor
current
LMR33630
IZC
Zero current detector
threshold
MIN
TYP
MAX
2.9
3.5
4.1
UNIT
A
0.8
A
0.01
A
SOFT START
tSS
Internal soft-start time
2.9
4
6
ms
POWER GOOD (PG PIN)
VPG-HIGH-UP
Power-good upper
threshold - rising
% of FB voltage
105%
107%
110%
VPG-HIGH-DN
Power-good upper
threshold - falling
% of FB voltage
103%
105%
108%
VPG-LOW-UP
Power-good lower
threshold - rising
% of FB voltage
92%
94%
97%
VPG-LOW-DN
Power-good lower
threshold - falling
% of FB voltage
90%
92%
95%
tPG
Power-good glitch filter
delay (4)
RPG
Power-good flag RDSON
VIN-PG
Minimum input voltage for
proper PG function
50-µA, EN = 0 V
VPG
PG logic low output
50-µA, EN = 0 V, VIN = 2V
ƒSW
Switching frequency
"A" Version
340
400
460
kHz
ƒSW
Switching frequency
"B" Version
1.2
1.4
1.6
MHz
ƒSW
Switching frequency
"C" Version, DDA package
1.8
2.1
2.4
MHz
ƒSW
Switching frequency
"C" Version, RNX package
1.8
2.1
2.3
MHz
60
170
VIN = 12 V, VEN = 4 V
76
150
VEN = 0 V
35
60
µs
Ω
2
V
0.2
V
OSCILLATOR
(4)
See Power-Good Flag Output for details.
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Electrical Characteristics (continued)
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VEN = 4 V.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
MOSFETS
RDS-ON-HS
High-side MOSFET ONresistance
RNX package
75
145
mΩ
RDS-ON-HS
High-side MOSFET ONresistance
DDA package
95
160
mΩ
RDS-ON-LS
Low-side MOSFET ONresistance
RNX package
50
95
mΩ
RDS-ON-LS
Low-side MOSFET ONresistance
DDA package
66
110
mΩ
7.6 Timing Characteristics
Limits apply over the recommended operating junction temperature (TJ) range of –40°C to +125°C, unless otherwise stated.
Minimum and maximum limits are specified through test, design or statistical correlation. Typical values represent the most
likely parametric norm at TJ = 25°C, and are provided for reference purposes only. Unless otherwise stated, the following
conditions apply: VIN = 12 V, VEN = 4 V.
NOM
MAX
tON-MIN
Minimum switch on-time
RNX package
MIN
68
80
ns
tON-MIN
Minimum switch on-time
DDA package
75
108
ns
tOFF-MIN
Minimum switch off-time
RNX package
52
70
ns
tOFF-MIN
Minimum switch off-time
DDA package
50
85
ns
tON-MAX
Maximum switch on-time
7
9
µs
8
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7.7 System Characteristics
The following specifications apply to a typical applications circuit, with nominal component values. Specifications in the typical
(TYP) column apply to TJ = 25°C only. Specifications in the minimum (MIN) and maximum (MAX) columns apply to the case
of typical components over the temperature range of TJ = –40°C to 125°C. These specifications are not ensured by
production testing.
PARAMETER
VIN
Operating input voltage range
Output voltage regulation for VOUT =
5 V (1)
VOUT
Output voltage regulation for VOUT =
3.3 V (1)
TEST CONDITIONS
VOUT = 3.3 V, IOUT= 0 A
MIN
TYP
MAX
3.8
36
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 0 A
to max. load
–1.5%
2.5%
VOUT = 5 V, VIN = 7 V to 36 V, IOUT = 1 A
to max. load
–1.5%
1.5%
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT =
0 A to max. load
–1.5%
2.5%
VOUT = 3.3 V, VIN = 3.8 V to 36 V, IOUT =
1 A to max. load
–1.5%
1.5%
UNIT
V
ISUPPLY
Input supply current when in
regulation
VIN = 12 V, VOUT = 3.3 V, IOUT = 0 A,
RFBT = 1 MΩ
VDROP
Dropout voltage; (VIN – VOUT)
DMAX
Maximum switch duty cycle (2)
VHC
FB pin voltage required to trip shortcircuit hiccup mode
0.4
V
tHC
Time between current-limit hiccup
burst
94
ms
tD
Switch voltage dead time
TSD
(1)
(2)
Thermal shutdown temperature
25
µA
VOUT = 5 V, IOUT = 1A
Dropout at –1% of regulation,
ƒSW = 140 kHz
150
mV
VIN = VOUT = 12 V, IOUT = 1 A
98%
2
ns
Shutdown temperature
165
°C
Recovery temperature
148
°C
Deviation is with respect to VIN =12 V, IOUT = 1 A.
In dropout the switching frequency drops to increase the effective duty cycle. The lowest frequency is clamped at approximately: ƒMIN =
1 / (tON-MAX + tOFF-MIN). DMAX = tON-MAX /(tON-MAX + tOFF-MIN).
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7.8 Typical Characteristics
Unless otherwise specified the following conditions apply: TA = 25°C and VIN = 12 V
36
12
11
10
Shutdown Current (µA)
Quiescent Current (µA)
34
32
30
28
26
-40C
24
25C
22
5
10
15
20
25
30
35
8
7
6
5
4
3
-40C
2
25C
1
125C
20
0
9
0
0
40
Input Voltage (V)
10
15
20
25
30
35
40
Input Voltage (V)
C005
VFB = 1.2 V
C003
EN = 0 V
Figure 1. Non-Switching Input Supply Current
Figure 2. Shutdown Supply Current
1.35
1000
Short Circuit Output Current (mA)
125C
5
EN Threshold Voltage (V)
1.30
900
800
700
-40C
600
500
0
5
10
15
20
25
30
ƒS = 400 kHz
1.20
1.15
1.10
25C
1.05
125C
1.00
35
UP
DN
±40
40
±20
0
20
40
60
80
100
120
140
Temperature (C)
Input Voltage (V)
VOUT = 0 V
1.25
C006
C004
See Figure 47
Figure 4. Precision Enable Thresholds
Figure 3. Short-Circuit Output Current
1,200
DN
Peak Inductor Current (mA)
OUTPUT VOLTAGE (0.8V/Div)
1,100
UP
1,000
900
800
700
-40C
600
25C
500
125C
400
0
5
INPUT VOLTAGE (1V/Div)
IOUT = 1 mA
15
20
25
Input Voltage (V)
See Figure 47
IOUT = 0 A
ƒSW = 400 kHz
VOUT = 5 V
30
35
40
C006
See Figure 47
Figure 6. IPEAK-MIN
Figure 5. UVLO Thresholds
10
10
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8 Detailed Description
8.1 Overview
The LMR33630 is a synchronous peak-current-mode buck regulator designed for a wide variety of industrial
applications. The regulator automatically switches modes between PFM and PWM depending on load. At heavy
load, the device operates in PWM at a constant switching frequency. At light loads the mode changes to PFM,
with diode emulation allowing DCM. This reduces the input supply current and keeps efficiency high. The device
features internal loop compensation which reduces design time and requires fewer external components than
externally compensated regulators.
8.2 Functional Block Diagram
VIN
VCC
INT. REG.
BIAS
OSCILLATOR
EN
ENABLE
LOGIC
BOOT
HS CURRENT
SENSE
1.0V
Reference
PWM
COMP.
ERROR
AMPLIFIER
FB
+
-
+
-
PG
CONTROL
LOGIC
PFM MODE
CONTROL
SW
DRIVER
LS CURRENT
SENSE
POWER GOOD
CONTROL
AGND
PGND
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8.3 Feature Description
8.3.1 Power-Good Flag Output
The power-good flag function (PG output pin) of the LMR33630 can be used to reset a system microprocessor
whenever the output voltage is out of regulation. This open-drain output goes low under fault conditions, such as
current limit and thermal shutdown, as well as during normal start-up. A glitch filter prevents false flag operation
for short excursions of the output voltage, such as during line and load transients. The timing parameters of the
glitch filter are found in the Electrical Characteristics table. Output voltage excursions lasting less than tPG do not
trip the power-good flag. Power-good operation can best be understood by reference to Figure 7 and Figure 8.
Note that during initial power-up a delay of about 4 ms (typical) is inserted from the time that EN is asserted to
the time that the power-good flag goes high. This delay only occurs during start-up and is not encountered during
normal operation of the power-good function.
The power-good output consists of an open drain NMOS; requiring an external pull up resistor to a suitable logic
supply. It can also be pulled up to either VCC or VOUT, through a 100-kΩ resistor, as desired. If this function is
not needed, the PG pin should be left floating. When EN is pulled low, the flag output is also forced low. With EN
low, power good remains valid as long as the input voltage is ≥ 2 V (typical). Limit the current into the powergood flag pin to less than 5 mA D.C. The maximum current is internally limited to about 35 mA when the device
is enabled and about 65 mA when the device is disabled. The internal current limit protects the device from any
transient currents that may occur when discharging a filter capacitor connected to this output.
VOUT
VPG-HIGH_UP (107%)
VPG-HIGH-DN (105%)
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
PG
High = Power Good
Low = Fault
Figure 7. Static Power-Good Operation
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Feature Description (continued)
Glitches do not cause false operation nor reset timer
VOUT
VPG-LOW-UP (95%)
VPG-LOW-DN (93%)
< tPG
PG
tPG
tPG
tPG
Figure 8. Power-Good-Timing Behavior
8.3.2 Enable and Start-up
Start-up and shutdown are controlled by the EN input. This input features precision thresholds, allowing the use
of an external voltage divider to provide an adjustable input UVLO (see the External UVLO section). Applying a
voltage of ≥ VEN-VCC_H causes the device to enter standby mode, powering the internal VCC, but not producing
an output voltage. Increasing the EN voltage to VEN-H fully enables the device, allowing it to enter start-up mode
and beginning the soft-start period. When the EN input is brought below VEN-H by VEN-HYS, the regulator stops
running and enters standby mode. Further decrease in the EN voltage to below VEN-VCC-L completely shuts down
the device. This behavior is shown in Figure 9. The EN input may be connected directly to VIN if this feature is
not needed. This input must not be allowed to float. The values for the various EN thresholds can be found in the
Electrical Characteristics table.
The LMR33630 utilizes a reference-based soft start that prevents output voltage overshoots and large inrush
currents as the regulator is starting up. A typical start-up waveform is shown in Figure 10 along with typical
timings. The rise time of the output voltage is about 4 ms (see Electrical Characteristics).
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Feature Description (continued)
EN
VEN-H
VEN-H ± VEN-HYS
VEN-VCC-H
VEN-VCC-L
VCC
5V
0
VOUT
VOUT
0
Figure 9. Precision Enable Behavior
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Feature Description (continued)
EN, 3V/Div
VOUT, 2V/Div
PG, 5V/Div
Inductor Current, 3A/Div
2ms/Div
Figure 10. Typical Start-up Behavior
VIN = 12 V, VOUT = 5 V, IOUT = 3 A
8.3.3 Current Limit and Short Circuit
The LMR33630 incorporates valley current limit for normal overloads and for short-circuit protection. In addition
the high-side power MOSFET is protected from excessive current by a peak current limit circuit. Cycle-by-cycle
current limit is used for overloads, while hiccup mode is used for short circuits. Finally, a zero current detector is
used on the low-side power MOSFET to implement DEM at light loads (see Glossary). The typical value of this
current limit is found under IZC in the Electrical Characteristics.
During overloads the low-side current limit, ILIMIT, (see Electrical Characteristics table) determines the maximum
load current that the LMR33630 can supply. When the low-side switch turns on, the inductor current begins to
ramp down. If the current does not fall below ILIMIT before the next turn-on cycle, then that cycle is skipped, and
the low-side MOSFET is left on until the current falls below ILIMIT. This is somewhat different than the more typical
peak current limit and results in Equation 1 for the maximum load current.
IOUT
max
ILIMIT
VIN VOUT VOUT
˜
2 ˜ fSW ˜ L
VIN
where
•
•
fSW = Switching frequency
L = Inductor value
(1)
If, during current limit, the voltage on the FB input falls below about 0.4 V, due to a short circuit, the device enters
into hiccup mode. In this mode the device stops switching for tHC (see System Characteristics), or about 94 ms
and then goes through a normal re-start with soft start. If the short-circuit condition remains, the device runs in
current limit for about 20 ms (typical) and then shuts down again. This cycle repeats, as shown in Figure 11 as
long as the short-circuit-condition persists. This mode of operation helps to reduce the temperature rise of the
device during a hard short on the output. The output current is greatly reduced during hiccup mode (see Typical
Characteristics). Once the output short is removed, and the hiccup delay is passed, the output voltage recovers
normally as shown in Figure 12
The high-side-current limit trips when the peak inductor current reaches ISC (see Electrical Characteristics table).
This is a cycle-by-cycle current limit and does not produce any frequency or load current fold back. It is meant to
protect the high-side MOSFET from excessive current. Under some conditions, such as high input voltages, this
current limit may trip before the low-side protection. Under this condition, ISC determines the maximum output
current. Note that ISC varies with duty cycle.
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Feature Description (continued)
Short Applied
Short Removed
VOUT, 2V/Div
Inductor Current, 1A/Div
50ms/Div
Inductor Current,
1A/Div
50ms/Div
Figure 11. Inductor Current Burst in Short-Circuit Mode
Figure 12. Short-Circuit Transient and Recovery
8.3.4 Undervoltage Lockout and Thermal Shutdown
The LMR33630 incorporates an undervoltage-lockout feature on the output of the internal LDO (at the VCC pin).
When VCC reaches about 3.7 V the device is ready to receive an EN signal and start up. When VCC falls below
about 3 V the device shuts down, regardless of EN status. Since the LDO is in dropout during these transitions,
the above values roughly represent the input voltage levels during the transitions.
Thermal shutdown is provided to protect the regulator from excessive junction temperature. When the junction
temperature reaches about 165°C the device shuts down; re-start occurs when the temperature falls to about
148°C .
8.4 Device Functional Modes
8.4.1 Auto Mode
In auto mode the device moves between PWM and PFM as the load changes. At light loads the regulator
operates in PFM. At higher loads the mode changes to PWM. The load current for which the device moves from
PFM to PWM can be found in the Application Curves. The output current at which the device changes modes
depends somewhat on the input voltage, inductor value and the nominal switching frequency. For output currents
above the curve, the device is in PWM mode. For currents below the curve, the device is in PFM. The curves
apply for a nominal switching frequency of 400 kHz and the BOM shown in Table 4. At higher switching
frequencies the load at which the mode change occurs will be greater. For applications where the switching
frequency must be known for a given condition, the above mentioned effects must be carefully tested before the
design is finalized.
In PWM the regulator operates as a constant frequency, current mode, full synchronous converter using PWM to
regulate the output voltage. While operating in this mode the output voltage is regulated by switching at a
constant frequency and modulating the duty cycle to control the power to the load. This provides excellent line
and load regulation and low output voltage ripple.
In PFM the high-side MOSFET is turned on in a burst of one or more pulses to provide energy to the load. The
duration of the burst depends on how long it takes the inductor current to reach IPEAK-MIN. The frequency of these
bursts is adjusted to regulate the output, while diode emulation (DEM) is used to maximize efficiency (see
Glossary). This mode provides high light-load efficiency by reducing the amount of input supply current required
to regulate the output voltage at small loads. This trades off very good light-load efficiency for larger output
voltage ripple and variable switching frequency. Also, a small increase in output voltage occurs at light loads. The
actual switching frequency and output voltage ripple depends on the input voltage, output voltage, and load.
Typical switching waveforms in PFM and PWM are shown in Figure 13 and Figure 14. See the Application
Curves for output voltage variation with load in auto mode.
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Device Functional Modes (continued)
SW,
5V/Div
SW,
5V/Div
VOUT,
10mV/Div
VOUT,
10mV/Div
Inductor
Current,
0.5A/Div
Inductor
Current,
2A/Div
2µs/Div
50µs/Div
Figure 14. Typical PWM Switching Waveforms
VIN = 12 V, VOUT = 5 V, IOUT = 3 A, ƒS = 400 kHz
Figure 13. Typical PFM Switching Waveforms
VIN = 12 V, VOUT = 5 V, IOUT = 10 mA
8.4.2 Dropout
The dropout performance of any buck regulator is affected by the RDSON of the power MOSFETs, the DC
resistance of the inductor, and the maximum duty cycle that the controller can achieve. As the input voltage is
reduced to near the output voltage, the off-time of the high side MOSFET starts to approach the minimum value
(see Timing Characteristics). Beyond this point the switching may become erratic, and/or the output voltage falls
out of regulation. To avoid this problem the LMR33630 automatically reduces the switching frequency to increase
the effective duty cycle and maintain regulation. In this data sheet the dropout voltage is defined as the
difference between the input and output voltage when the output has dropped by 1% of its nominal value. Under
this condition the switching frequency has dropped to its minimum value of about 140 kHz. Note that the 0.4 V
short circuit detection threshold is not activated when in dropout mode. Typical drop-out characteristics can be
found in Figure 15 and Figure 16.
6
0.45
0.4
Drop-Out Voltage (V)
Output Voltage (V)
5.5
5
4.5
1A
4
2A
3.5
0.35
0.3
0.25
0.2
0.15
0.1
3A
5V
0.05
0A
3.3V
3
0
4
4.5
5
5.5
6
6.5
Input Voltage (V)
7
0
1
1.5
2
2.5
3
Output Current (A)
C017
Figure 15. Overall Dropout Characteristic
VOUT = 5 V
0.5
3.5
C011
Figure 16. Typical Dropout Voltage vs Output Current
ƒSW = 140 kHz
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Device Functional Modes (continued)
8.4.3 Minimum Switch On-Time
Every switching regulator has a minimum controllable on-time dictated by the inherent delays and blanking times
associated with the control circuits. This imposes a minimum switch duty cycle and therefore a minimum
conversion ratio. The constraint is encountered at high input voltages and low output voltages. To help extend
the minimum controllable duty cycle, the LMR33630 automatically reduces the switching frequency when the
minimum on-time limit is reached. In this way the converter can regulate the lowest programmable output voltage
at the maximum input voltage. An estimate for the approximate input voltage, for a given output voltage, before
frequency fold-back occurs is found in Equation 2. The values of tON and fSW can be found in the Electrical
Characteristics table. As the input voltage is increased, the switch on-time (duty-cycle) reduces to regulate the
output voltage. When the on-time reaches the limit, the switching frequency drops, while the on-time remains
fixed. This relationship is highlighted in Figure 17 for a nominal switching frequency of 2.1 MHz.
VOUT
VIN d
t ON ˜ fSW
(2)
Switching Frequency (MHz)
2.4
2.2
2
1.8
1.6
1.4
1.2
3.3V
1
10
15
20
25
30
Input Voltage (V)
35
40
C017
Figure 17. Switching Frequency vs Input Voltage
VOUT = 3.3 V, IOUT = 1 A
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
NOTE
In this data sheet the effective value of capacitance is defined as the actual capacitance
under D.C. bias and temperature; not the rated or nameplate values. Use high-quality,
low-ESR, ceramic capacitors with an X5R or better dielectric throughout. All high value
ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. Under D.C. bias the capacitance drops considerably. Large case
sizes and/or higher voltage ratings are better in this regard. To help mitigate these effects,
multiple capacitors can be used in parallel to bring the minimum effective capacitance up
to the required value. This can also ease the RMS current requirements on a single
capacitor. A careful study of bias and temperature variation of any capacitor bank should
be made in order to ensure that the minimum value of effective capacitance is provided.
9.1 Application Information
The LMR33630 step-down DC-to-DC converter is typically used to convert a higher DC voltage to a lower DC
voltage with a maximum output current of 3 A. The following design procedure can be used to select components
for the LMR33630. Alternately, the WEBENCH® Design Tool may be used to generate a complete design. This
tool utilizes an iterative design procedure and has access to a comprehensive database of components. This
allows the tool to create an optimized design and allows the user to experiment with various options.
9.2 Typical Application
Figure 18 shows a typical application circuit for the LMR33630. This device is designed to function over a wide
range of external components and system parameters. However, the internal compensation is optimized for a
certain range of external inductance and output capacitance. As a quick start guide, Table 2 provides typical
component values for a range of the most common output voltages. The values given in the table are typical.
Other values may be used to enhance certain performance criterion as required by the application.
L
VIN
6 V to 36 V
CIN
10 µF
VOUT
SW
VIN
5V
3A
8 µH
CHF
CBOOT
220 nF
COUT
BOOT
EN
4x 22 µF
0.1 µF
RFBT
CFF
PG
100 NŸ
PG
100 NŸ
VCC
CVCC
1 µF
FB
PGND
AGND
RFBB
24.9 NŸ
Figure 18. Example Application Circuit (400 kHz)
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Typical Application (continued)
9.2.1 Design Requirements
Table 1 provides the parameters for our detailed design procedure example:
Table 1. Detailed Design Parameters
DESIGN PARAMETER
EXAMPLE VALUE
Input voltage
12 V (6 V to 36 V)
Output voltage
5V
Maximum output current
0 A to 3 A
Switching frequency
400 kHz
Table 2. Typical External Component Values
ƒSW
(kHz)
VOUT (V)
L (µH)
COUT (rated
capacitance)
RFBT (Ω)
RFBB (Ω)
CIN + CHF
CBOOT
CVCC
CFF
400
3.3
6.8
4 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
open
1400
3.3
2.2
2 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
open
2100
3.3
1.2
2 × 22 µF
100 k
43.2 k
10 µF + 220 nF
100 nF
1 µF
open
400
5
8
4 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
open
1400
5
2.2
2 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
open
2100
5
1.5
2 × 22 µF
100 k
24.9 k
10 µF + 220 nF
100 nF
1 µF
open
400
12
15
4 × 22 µF
100 k
9.09 k
10 µF + 220 nF
100 nF
1 µF
open
1400
12
4.7
4 × 10 µF
100 k
9.09 k
10 µF + 220 nF
100 nF
1 µF
open
2100
12
3.3
4 × 10 µF
100 k
9.09 k
10 µF + 220 nF
100 nF
1 µF
open
9.2.2 Detailed Design Procedure
The following design procedure applies to Figure 18 and Table 1.
9.2.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LMR33630 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
9.2.2.2 Choosing the Switching Frequency
The choice of switching frequency is a compromise between conversion efficiency and overall solution size.
Lower switching frequency implies reduced switching losses and usually results in higher system efficiency.
However, higher switching frequency allows the use of smaller inductors and output capacitors, and hence a
more compact design. For this example we choose 400 kHz.
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9.2.2.3 Setting the Output Voltage
The output voltage of LMR33630 is externally adjustable using a resistor divider network. The range of
recommended output voltage is found in the Recommended Operating Conditions table. The divider network is
comprised of RFBT and RFBB, and closes the loop between the output voltage and the converter. The converter
regulates the output voltage by holding the voltage on the FB pin equal to the internal reference voltage, VREF.
The resistance of the divider is a compromise between excessive noise pick-up and excessive loading of the
output. Smaller values of resistance reduce noise sensitivity but also reduce the light-load efficiency. The
recommended value for RFBT is 100 kΩ; with a maximum value of 1 MΩ. If a 1 MΩ is selected for RFBT, then a
feed-forward capacitor must be used across this resistor to provide adequate loop phase margin (see CFF
Selection). Once RFBT is selected, Equation 3 is used to select RFBB. VREF is nominally 1 V (see Electrical
Characteristics for limits).
RFBT
RFBB
ª VOUT
º
1»
«
¬ VREF
¼
(3)
For this 5-V example, RFBT = 100 kΩ and RFBB = 24.9 kΩ are chosen.
9.2.2.4 Inductor Selection
The parameters for selecting the inductor are the inductance and saturation current. The inductance is based on
the desired peak-to-peak ripple current and is normally chosen to be in the range of 20% to 40% of the maximum
output current. Experience shows that the best value for inductor ripple current is 30% of the maximum load
current. Note that when selecting the ripple current for applications with much smaller maximum load than the
maximum available from the device, the maximum device current should be used. Equation 4 can be used to
determine the value of inductance. The constant K is the percentage of inductor current ripple. For this example
we choose K = 0.3 and find an inductance L = 8.1 µH; we select the next standard value of 8 µH.
L
VIN VOUT
V
˜ OUT
fSW ˜ K ˜ IOUT max VIN
(4)
Ideally, the saturation current rating of the inductor should be at least as large as the high-side switch current
limit, ISC (see Electrical Characteristics ). This ensures that the inductor does not saturate even during a short
circuit on the output. When the inductor core material saturates, the inductance falls to a very low value, causing
the inductor current to rise very rapidly. Although the valley current limit, ILIMIT, is designed to reduce the risk of
current run-away, a saturated inductor can cause the current to rise to high values very rapidly. This may lead to
component damage; do not allow the inductor to saturate! Inductors with a ferrite core material have very hard
saturation characteristics, but usually have lower core losses than powdered iron cores. Powered iron cores
exhibit a soft saturation, allowing some relaxation in the current rating of the inductor. However, they have more
core losses at frequencies above about 1 MHz. In any case the inductor saturation current should not be less
than the device low-side current limit, ILIMIT (see Electrical Characteristics). In order to avoid sub-harmonic
oscillation, the inductance value should not be less than that given in Equation 5 The maximum inductance is
limited by the minimum current ripple required for the current mode control to perform correctly. As a rule-ofthumb, the minimum inductor ripple current should be no less than about 10% of the device maximum rated
current under nominal conditions.
LMIN t 0.28 ˜
VOUT
fSW
(5)
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9.2.2.5 Output Capacitor Selection
The value of the output capacitor, and its ESR, determine the output voltage ripple and load transient
performance. The output capacitor bank is usually limited by the load transient requirements, rather than the
output voltage ripple. Equation 6 can be used to estimate a lower bound on the total output capacitance, and an
upper bound on the ESR, required to meet a specified load transient.
º
ª
'IOUT
K2
COUT t
˜«1 D ˜ 1 K
˜ 2 D»
12
fSW ˜ 'VOUT ˜ K ¬«
¼»
ESR d
D
2 K ˜ 'VOUT
ª
2 ˜ 'IOUT «1 K
¬«
K2
12
§
1 ·º
¸¸»
˜ ¨¨1
© (1 D) ¹¼»
VOUT
VIN
where
•
•
•
ΔVOUT = output voltage transient
ΔIOUT = output current transient
K = Ripple factor from Inductor Selection
(6)
Once the output capacitor and ESR have been calculated, Equation 7 can be used to check the peak-to-peak
output voltage ripple; Vr.
Vr # 'IL ˜ ESR 2
1
8 ˜ fSW ˜ COUT
2
(7)
The output capacitor and ESR can then be adjusted to meet both the load transient and output ripple
requirements.
For this example we require a ΔVOUT of ≤ 250 mV for an output current step of ΔIOUT = 2 A. Equation 6 gives a
minimum value of 52 µF and a maximum ESR of 0.11 Ω. Assuming a 20% tolerance and a 10% bias de-rating,
we arrive at a minimum capacitance of 72 µF. This can be achieved with a bank of 4 × 22-µF, 16-V, ceramic
capacitors in the 1210 case size. More output capacitance can be used to improve the load transient response.
Ceramic capacitors can easily meet the minimum ESR requirements. In some cases an aluminum electrolytic
capacitor can be placed in parallel with the ceramics to help build up the required value of capacitance. In
general use a capacitor of at least 10 V for output voltages of 3.3 V or less, while a capacitor of 16 V or more
should be used for output voltages of 5 V and above.
In practice the output capacitor has the most influence on the transient response and loop phase margin. Load
transient testing and Bode plots are the best way to validate any given design and should always be completed
before the application goes into production. In addition to the required output capacitance, a small ceramic
placed on the output can help to reduce high frequency noise. Small case size ceramic capacitors in the range of
1 nF to 100 nF can be very helpful in reducing spikes on the output caused by inductor and board parasitics.
The maximum value of total output capacitance should be limited to about 10 times the design value, or 1000 µF,
whichever is smaller. Large values of output capacitance can adversely affect the start-up behavior of the
regulator as well as the loop stability. If values larger than noted here must be used, then a careful study of startup at full load and loop stability must be performed.
9.2.2.6 Input Capacitor Selection
The ceramic input capacitors provide a low impedance source to the regulator in addition to supplying the ripple
current and isolating switching noise from other circuits. A minimum of 10 µF of ceramic capacitance is required
on the input of the LMR33630. This must be rated for at least the maximum input voltage that the application
requires; preferably twice the maximum input voltage. This capacitance can be increased to help reduce input
voltage ripple and/or maintain the input voltage during load transients. In addition a small case size 220-nF
ceramic capacitor must be used at the input, as close a possible to the regulator. This provides a high frequency
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bypass for the control circuits internal to the device. For this example a 10-µF, 50-V, X7R (or better) ceramic
capacitor is chosen. The 220 nF must also be rated at 50 V with an X7R dielectric. The VQFN (RNX) package
provides two input voltage pins and two power ground pins on opposite sides of the package. This allows the
input capacitors to be split, and placed optimally with respect to the internal power MOSFETs, thus improving the
effectiveness of the input bypassing. In this example, place two 4.7-µF and two 100-nF ceramic capacitors at
each VIN/PGND location. A single 10-µF can also be used on one side of the package.
Many times it is desirable to use an electrolytic capacitor on the input in parallel with the ceramics. This is
especially true if long leads/traces are used to connect the input supply to the regulator. The moderate ESR of
this capacitor can help damp any ringing on the input supply caused by the long power leads. The use of this
additional capacitor also helps with voltage dips caused by input supplies with unusually high impedance.
Most of the input switching current passes through the ceramic input capacitor(s). The approximate RMS value of
this current can be calculated from Equation 8 and should be checked against the manufacturers' maximum
ratings.
I
IRMS # OUT
2
(8)
9.2.2.7 CBOOT
The LMR33630 requires a boot-strap capacitor connected between the BOOT pin and the SW pin. This capacitor
stores energy that is used to supply the gate drivers for the power MOSFETs. A high-quality ceramic capacitor of
100 nF and at least 10 V is required.
9.2.2.8 VCC
The VCC pin is the output of the internal LDO used to supply the control circuits of the regulator. This output
requires a 1-µF, 16-V ceramic capacitor connected from VCC to GND for proper operation. In general avoid
loading this output with any external circuitry. However, this output can be used to supply the pullup for the
power-good function (see Power-Good Flag Output). A value of 100 kΩ is a good choice in this case. The
nominal output voltage on VCC is 5 V; see Electrical Characteristics for limits. Do not short this output to ground
or any other external voltage.
9.2.2.9 CFF Selection
In some cases a feed-forward capacitor can be used across RFBT to improve the load transient response or
improve the loop-phase margin. This is especially true when values of RFBT > 100 kΩ are used. Large values of
RFBT, in combination with the parasitic capacitance at the FB pin, can create a small signal pole that interferes
with the loop stability. A CFF can help to mitigate this effect. Equation 9 can be used to estimate the value of CFF.
The value found with Equation 9 is a starting point; use lower values to determine if any advantage is gained by
the use of a CFF capacitor. The application report Optimizing Transient Response of Internally Compensated DCDC Converters with Feed-forward Capacitor is helpful when experimenting with a feed-forward capacitor.
VOUT ˜ COUT
CFF
VREF
120 ˜ RFBT ˜
VOUT
(9)
9.2.2.10 External UVLO
In some cases an input UVLO level different than that provided internal to the device is needed. This can be
accomplished by using the circuit shown in Figure 19. The input voltage at which the device turns on is
designated VON; while the turnoff voltage is VOFF. First a value for RENB is chosen in the range of 10 kΩ to 100
kΩ and then Equation 10 is used to calculate RENT and VOFF.
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VIN
RENT
EN
RENB
Figure 19. Set-Up for External UVLO Application
RENT
§ VON
¨¨
© VEN H
VOFF
§
VEN HYS
VON ˜ ¨¨1
VEN
©
·
1¸¸ ˜ RENB
¹
·
¸¸
¹
where
•
•
VON = VIN turnon voltage
VOFF = VIN turnoff voltage
(10)
9.2.2.11 Maximum Ambient Temperature
As with any power conversion device, the LMR33630 dissipates internal power while operating. The effect of this
power dissipation is to raise the internal temperature of the converter above ambient. The internal die
temperature (TJ) is a function of the ambient temperature, the power loss and the effective thermal resistance,
RθJA of the device and PCB combination. The maximum internal die temperature for the LMR33630 must be
limited to 125°C. This establishes a limit on the maximum device power dissipation and therefore the load
current. Equation 11 shows the relationships between the important parameters. It is easy to see that larger
ambient temperatures (TA) and larger values of RθJA reduce the maximum available output current. The converter
efficiency can be estimated by using the curves provided in this data sheet. If the desired operating conditions
can not be found in one of the curves, then interpolation can be used to estimate the efficiency. Alternatively, the
EVM can be adjusted to match the desired application requirements and the efficiency can be measured directly.
The correct value of RθJA is more difficult to estimate. As stated in Semiconductor and IC Package Thermal
Metrics, the value of RθJA given in the Thermal Information table is not valid for design purposes and must not be
used to estimate the thermal performance of the application. The values reported in that table were measured
under a specific set of conditions that are rarely obtained in an actual application.
IOUT
MAX
TJ TA
1
K
˜
˜
R TJA
1 K VOUT
where
•
η = Efficiency
(11)
The effective RθJA is a critical parameter and depends on many factors such as power dissipation, air
temperature/flow, PCB area, copper heat-sink area, number of thermal vias under the package, and adjacent
component placement; to mention just a few. The HSOIC (DDA) package utilizes a die attach paddle, or thermal
pad (PAD) to provide a place to solder down to the PCB heat-sinking copper. This provides a good heat
conduction path from the regulator junction to the heat sink and must be properly soldered to the PCB heat sink
copper. Due to the ultra-miniature size of the VQFN (RNX) package, a DAP is not available. This means that this
package exhibits a somewhat large value RθJA. Typical examples of RθJA vs copper board area can be found in
Figure 20 and Figure 21. The copper area given in the graph is for each layer; the top and bottom layers are 2
oz. copper each, while the inner layers are 1 oz. A typical curve of maximum output current vs. ambient
temperature is shown in Figure 22. This data was taken with a device/PCB combination giving an RθJA of about
30°C/W. It must be remembered that the data given in these graphs are for illustration purposes only, and the
actual performance in any given application depends on all of the previously mentioned factors.
24
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44
42
40
38
(ƒC/W)
36
34
R
JA
32
30
28
26
24
22
DDA, 4L
20
0
10
20
30
40
50
60
70
Copper Area (cm2)
C003
Figure 20. Typical RθJA vs Copper Area for a Four-Layer Board and the HSOIC (DDA) Package
70
60
55
R
JA (ƒC/w)
65
50
45
RNX, 4L
40
0
10
20
30
40
50
60
70
Copper Area (cm2)
C005
Figure 21. RθJA vs Copper Board Area for the VQFN (RNX) Package
Maximum Output Current (A)
3.5
3
2.5
2
1.5
1
0.5
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140
Ambient Temperature (ƒC)
C002
Figure 22. Maximum Output Current vs Ambient Temperature
VIN = 12 V, VOUT = 5 V, ƒSW = 400 kHz, RθJA = 30°C/W
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The resources below can be used as a guide to optimal thermal PCB design and estimating RθJA for a given
application environment:
• Thermal Design by Insight not Hindsight
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
• Semiconductor and IC Package Thermal Metrics
• Thermal Design Made Simple with LM43603 and LM43602
• SLMA002 PowerPADTM Thermally Enhanced Package
• PowerPADTM Made Easy
• SBVA025 Using New Thermal Metrics
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9.2.3 Application Curves
Unless otherwise specified the following conditions apply: VIN = 12 V, TA = 25°C. The circuit is shown in
Figure 47, with the appropriate BOM from Table 3 or Table 4.
100
95
85
Efficiency (%)
Efficiency (%)
90
80
75
8V
70
12V
65
24V
60
36V
55
0.001
0.01
0.1
1
10
Output Current (A)
VOUT = 5 V
100
95
90
85
80
75
70
65
60
55
50
45
40
35
30
0.001
24V
36V
0.01
400 kHz
0.1
1
10
Output Current (A)
DDA Package
VOUT = 3.3 V
C011
400 kHz
DDA Package
Figure 24. Efficiency
100
100
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
12V
C009
Figure 23. Efficiency
75
70
65
8V
60
75
70
65
5V
60
55
12V
55
12V
50
24V
50
24V
45
45
36V
40
0.001
0.01
0.1
1
VOUT = 5 V
40
0.001
10
Output Current (A)
36V
0.01
1.4 MHz
0.1
1
10
Output Current (A)
C013
VOUT = 3.3 V
DDA Package
C012
1.4 MHz
DDA Package
Figure 26. Efficiency
Figure 25. Efficiency
100
100
95
95
90
90
85
85
80
80
Efficiency (%)
Efficiency (%)
5V
75
70
65
8V
60
75
70
65
5V
60
55
12V
55
12V
50
24V
50
24V
45
45
36V
40
0.001
0.01
0.1
Output Current (A)
VOUT = 5 V
2.1 MHz
1
10
40
0.001
0.01
0.1
1
10
Output Current (A)
C014
DDA Package
36V
VOUT = 3.3 V
Figure 27. Efficiency
2.1 MHz
C015
DDA Package
Figure 28. Efficiency
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100
100
95
95
90
90
85
85
Efficiency (%)
Efficiency (%)
SNVSAN3B – AUGUST 2017 – REVISED APRIL 2018
80
75
70
8V
65
0.01
0.1
1
VOUT = 5 V
12V
24V
36V
50
0.001
10
Output Current (A)
8V
55
36V
50
0.001
70
60
24V
55
75
65
12V
60
80
0.01
400 kHz
RNX Package
VOUT = 3.3 V
100
100
95
95
90
90
85
85
80
75
70
8V
65
55
1
75
70
1.4 MHz
RNX Package
90
90
85
85
Efficiency (%)
Efficiency (%)
95
80
75
70
8V
65
60
55
10
C020
1.4 MHz
RNX Package
75
70
8V
12V
24V
55
36V
1
80
10
50
0.001
RNX Package
36V
0.01
0.1
Output Current (A)
C010
VOUT = 3.3 V
Figure 33. Efficiency
28
1
60
24V
2.1 MHz
0.1
65
12V
VOUT = 5 V
0.01
Figure 32. Efficiency
100
0.1
36V
VOUT = 3.3 V
95
Output Current (A)
24V
Output Current (A)
100
0.01
12V
C019
Figure 31. Efficiency
50
0.001
5V
50
0.001
10
Output Current (A)
80
55
36V
VOUT = 5 V
RNX Package
60
24V
0.1
10
C008
400 kHz
65
12V
60
0.01
1
Figure 30. Efficiency
Efficiency (%)
Efficiency (%)
Figure 29. Efficiency
50
0.001
0.1
Output Current (A)
C007
2.1 MHz
1
10
C009
RNX Package
Figure 34. Efficiency
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5.06
32
8V
5.055
Output Voltage (V)
Input Supply Current (µA)
12V
5.05
24V
5.045
36V
5.04
5.035
5.03
5.025
5.02
30
28
26
24
22
5.015
5V
5.01
0
0.5
1
1.5
2
2.5
3
20
0
3.5
Output Current (A)
10
15
VOUT = 5 V
Figure 35. Line and Load Regulation
0.5
1000000
Switching Frequency (Hz)
10000000
0.4
9
PWM
0.2
PFM
;
0.1
25
30
35
C017
IOUT = 0 A
RFBT = 1 MΩ
100000
10000
1000
8V
100
12V
10
24V
36V
5V
0
0
5
10
15
20
25
30
35
Input Voltage (V)
VOUT = 5 V
40
Figure 36. Input Supply Current
0.6
0.3
20
Input Voltage (V)
VOUT = 5 V
Output Current (A)
5
C011
1
0.00001
40
0.0001
0.001
0.01
0.1
1
10
Output Current (A)
C012
ƒSW = 400 kHz
VOUT = 5 V
Figure 37. Mode Change Thresholds
C014
ƒSW = 400 kHz
Figure 38. Switching Frequency vs Output Current
VOUT,
300mV/Div
VOUT,
300mV/Div
Output Current,
1A/Div
Output Current,
1A/Div
100µs/Div
0
100µs/Div
0
VIN = 12 V
tf = tr = 2 µs
VOUT = 5 V
IOUT = 0 A to 3 A
VIN = 12 V
tf = tr = 2 µs
Figure 39. Load Transient
VOUT = 5 V
IOUT = 1 A to 3 A
Figure 40. Load Transient
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32
3.35
5V
12V
3.34
24V
3.335
36V
Input Supply Current (µA)
Output Voltage (V)
3.345
3.33
3.325
3.32
3.315
30
28
26
24
22
3.3V
3.31
0
0.5
1
1.5
2
2.5
3
20
0
3.5
Output Current (A)
VOUT = 3.3 V
10000000
0.7
1000000
Switching Frequency (Hz)
Output Current (A)
15
0.6
0.5
0.4
9
PWM
0.3
0.2
PFM
;
0.1
10
15
IOUT = 0 A
35
20
25
30
40
C016
RFBT = 1 MΩ
100000
10000
1000
5V
100
12V
10
24V
36V
3.3V
35
Input Voltage (V)
VOUT = 3.3V
20
25
30
Input Voltage (V)
Figure 42. Input Supply Current
0.8
5
10
VOUT = 3.3 V
Figure 41. Line and Load Regulation
0
0
5
C011
1
0.00001
40
0.0001
0.001
0.01
0.1
1
10
Output Current (A)
C012
ƒSW = 400 kHz
VOUT = 3.3 V
Figure 43. Mode Change Thresholds
C015
ƒSW = 400 kHz
Figure 44. Switching Frequency vs Output Current
VOUT,
300mV/Div
VOUT,
300mV/Div
Output Current,
1A/Div
Output Current,
1A/Div
100µs/Div
0
100µs/Div
0
VIN = 12 V
tf = tr = 2 µs
VOUT = 3.3 V
IOUT = 0 A to 3 A
VIN = 12 V
tf = tr = 2 µs
Figure 45. Load Transient
30
VOUT = 3.3V
IOUT = 1 A to 3 A
Figure 46. Load Transient
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L
VIN
VIN
VOUT
SW
U1
CBOOT
CIN
CHF
COUT
BOOT
EN
0.1 µF
RFBT
PG
100 NŸ
PG
100 NŸ
VCC
CVCC
1 µF
FB
PGND
AGND
RFBB
Figure 47. Circuit for Application Curves
Table 3. BOM for Typical Application Curves DDA Package (1)
(1)
VOUT
FREQUENCY
RFBB
COUT
CIN + CHF
L
U1
3.3 V
400 kHz
43.3 kΩ
4 × 22 µF
1 × 10 µF + 1 × 220 nF
6.8 µH, 14 mΩ
LMR33630ADDA
3.3 V
1400 KHz
43.3 kΩ
4 × 22 µF
1 × 10 µF + 1 × 220 nF
2.2 µH, 11.4 mΩ
LMR33630BDDA
3.3 V
2100 kHz
43.3 kΩ
4 × 22 µF
1 × 10 µF + 1 × 220 nF
1.2 µH, 16 mΩ
LMR33630CDDA
5V
400 kHz
24.9 kΩ
4 × 22 µF
1 × 10 µF + 1 × 220 nF
8 µH, 14 mΩ
LMR33630ADDA
5V
1400 KHz
24.9 kΩ
4 × 22 µF
1 × 10 µF + 1 × 220 nF
2.2 µH, 11.4 mΩ
LMR33630BDDA
5V
2100 kHz
24.9 kΩ
4 × 22 µF
1 × 10 µF + 1 × 220 nF
1.5 µH, 8.2 mΩ
LMR33630CDDA
The values in this table were selected to enhance certain performance criteria and may not represent typical values.
Table 4. BOM for Typical Application Curves RNX Package (1)
(1)
VOUT
FREQUENCY
RFBB
COUT
CIN + CHF
L
U1
3.3 V
400 kHz
43.3 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
6.8 µH, 14 mΩ
LMR33630ARNX
3.3 V
1400 KHz
43.3 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
2.2 µH, 11.4 mΩ
LMR33630BRNX
3.3 V
2100 kHz
43.3 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
1.2 µH, 7 mΩ
LMR33630CRNX
5V
400 kHz
24.9 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
8 µH, 25 mΩ
LMR33630ARNX
5V
1400 KHz
24.9 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
2.2 µH, 11.4 mΩ
LMR33630BRNX
5V
2100 kHz
24.9 kΩ
4 × 22 µF
2 × 4.7 µF + 2 × 100 nF
1.5 µH, 8.2 mΩ
LMR33630CRNX
The values in this table were selected to enhance certain performance criteria and may not represent typical values.
9.3 Do's and Don'ts
•
•
•
•
•
•
•
Don't: Exceed the Absolute Maximum Ratings
Don't: Exceed the ESD Ratings
Don't: Exceed the Recommended Operating Conditions
Don't: Allow the EN input to float.
Don't: Allow the output voltage to exceed the input voltage, nor go below ground.
Don't: Use the value of RθJA given in the Thermal Information table to design your application.
Do: Follow all the guidelines and/or suggestions found in this data sheet before committing the design to
production. TI application engineers are ready to help critique your design and PCB layout to help make your
project a success (see Community Resources).
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10 Power Supply Recommendations
The characteristics of the input supply must be compatible with the Absolute Maximum Ratings and
Recommended Operating Conditions found in this data sheet. In addition, the input supply must be capable of
delivering the required input current to the loaded regulator. The average input current can be estimated with
Equation 12, where η is the efficiency.
VOUT ˜ IOUT
IIN
VIN ˜ K
(12)
If the regulator is connected to the input supply through long wires or PCB traces, special care is required to
achieve good performance. The parasitic inductance and resistance of the input cables can have an adverse
effect on the operation of the regulator. The parasitic inductance, in combination with the low-ESR, ceramic input
capacitors, can form an under damped resonant circuit, resulting in overvoltage transients at the input to the
regulator. The parasitic resistance can cause the voltage at the VIN pin to dip whenever a load transient is
applied to the output. If the application is operating close to the minimum input voltage, this dip may cause the
regulator to momentarily shutdown and/or reset. The best way to solve these kind of issues is to reduce the
distance from the input supply to the regulator and/or use an aluminum or tantalum input capacitor in parallel with
the ceramics. The moderate ESR of these types of capacitors help to damp the input resonant circuit and reduce
any overshoots. A value in the range of 20 µF to 100 µF is usually sufficient to provide input damping and help to
hold the input voltage steady during large load transients.
Sometimes, for other system considerations, an input filter is used in front of the regulator. This can lead to
instability, as well as some of the effects mentioned above, unless it is designed carefully. The user guide AN2162 Simple Success With Conducted EMI From DCDC Converters provides helpful suggestions when
designing an input filter for any switching regulator.
In some cases a transient voltage suppressor (TVS) is used on the input of regulators. One class of this device
has a snap-back characteristic (thyristor type). The use of a device with this type of characteristic is not
recommended. When the TVS fires, the clamping voltage falls to a very low value. If this voltage is less than the
output voltage of the regulator, the output capacitors discharge through the device back to the input. This
uncontrolled current flow may damage the device.
The input voltage should not be allowed to fall below the output voltage. In this scenario, such as a shorted input
test, the output capacitors will discharge through the internal parasitic diode found between the VIN and SW pins
of the device. During this condition, the current can become uncontrolled, possibly causing damage to the
device. If this scenario is considered likely, then a Schottky diode between the input supply and the output should
be used.
32
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11 Layout
11.1 Layout Guidelines
The PCB layout of any DC/DC converter is critical to the optimal performance of the design. Bad PCB layout can
disrupt the operation of an otherwise good schematic design. Even if the converter regulates correctly, bad PCB
layout can mean the difference between a robust design and one that cannot be mass produced. Furthermore,
the EMI performance of the regulator is dependent on the PCB layout, to a great extent. In a buck converter the
most critical PCB feature is the loop formed by the input capacitor(s) and power ground, as shown in Figure 48.
This loop carries large transient currents that can cause large transient voltages when reacting with the trace
inductance. These unwanted transient voltages will disrupt the proper operation of the converter. Because of this,
the traces in this loop should be wide and short, and the loop area as small as possible to reduce the parasitic
inductance. Figure 49 and Figure 50 show recommended layouts for the critical components of the LMR33630 .
1. Place the input capacitor(s) as close as possible to the VIN and GND terminals. VIN and GND pins are
adjacent, simplifying the input capacitor placement.
2. Place bypass capacitor for VCC close to the VCC pin. This capacitor must be placed close to the device
and routed with short, wide traces to the VCC and GND pins.
3. Use wide traces for the CBOOT capacitor. Place CBOOT close to the device with short/wide traces to the
BOOT and SW pins. For the VQFN package, it is important to route the SW connection under the device to
the NC pin, and use this path to connect the BOOT capacitor to SW.
4. Place the feedback divider as close as possible to the FB pin of the device. Place RFBB, RFBT, and CFF,
if used, physically close to the device. The connections to FB and GND must be short and close to those
pins on the device. The connection to VOUT can be somewhat longer. However, this latter trace must not be
routed near any noise source (such as the SW node) that can capacitively couple into the feedback path of
the regulator.
5. Use at least one ground plane in one of the middle layers. This plane acts as a noise shield and also act
as a heat dissipation path.
6. Connect the thermal pad to the ground plane. The SOIC package has a thermal pad (PAD) connection
that must be soldered down to the PCB ground plane. This pad acts as a heat-sink connection and an
electrical ground connection for the regulator. The integrity of this solder connection has a direct bearing on
the total effective RθJA of the application.
7. Provide wide paths for VIN, VOUT, and GND. Making these paths as wide and direct as possible reduces
any voltage drops on the input or output paths of the converter and maximizes efficiency.
8. Provide enough PCB area for proper heat sinking. As stated in the Maximum Ambient Temperature
section, enough copper area must be used to ensure a low RθJA, commensurate with the maximum load
current and ambient temperature. Make the top and bottom PCB layers with two-ounce copper; and no less
than one ounce. With the SOIC package, use an array of heat-sinking vias to connect the thermal pad (PAD)
to the ground plane on the bottom PCB layer. If the PCB design uses multiple copper layers (recommended),
thermal vias can also be connected to the inner layer heat-spreading ground planes.
9. Keep switch area small. Keep the copper area connecting the SW pin to the inductor as short and wide as
possible. At the same time the total area of this node should be minimized to help reduce radiated EMI.
See the following PCB layout resources for additional important guidelines:
• Layout Guidelines for Switching Power Supplies
• Simple Switcher PCB Layout Guidelines
• Construction Your Power Supply- Layout Considerations
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
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Layout Guidelines (continued)
VIN
CIN
SW
GND
Figure 48. Current Loops with Fast Edges
11.1.1 Ground and Thermal Considerations
As mentioned above, TI recommends using one of the middle layers as a solid ground plane. A ground plane
provides shielding for sensitive circuits and traces. It also provides a quiet reference potential for the control
circuitry. The AGND and PGND pins should be connected to the ground planes using vias next to the bypass
capacitors. PGND pins are connected directly to the source of the low side MOSFET switch, and also connected
directly to the grounds of the input and output capacitors. The PGND net contains noise at the switching
frequency and may bounce due to load variations. The PGND trace, as well as the VIN and SW traces, must be
constrained to one side of the ground planes. The other side of the ground plane contains much less noise and
must be used for sensitive routes.
TI recommends providing adequate device heat sinking by utilizing the thermal pad (PAD) of the device as the
primary thermal path. Use a minimum 4 × 3 array of 10 mil thermal vias to connect the PAD to the system
ground plane heat sink. The vias must be evenly distributed under the PAD. Use as much copper as possible, for
system ground plane, on the top and bottom layers for the best heat dissipation. Use a four-layer board with the
copper thickness for the four layers, starting from the top as: 2 oz / 1 oz / 1 oz / 2 oz. A four-layer board with
enough copper thickness, and proper layout, provides low current conduction impedance, proper shielding and
lower thermal resistance.
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11.2 Layout Example
GND
HEATSINK
INDUCTOR
VOUT
COUT
COUT
CBOOT
COUT
CHF
GND
CIN
VIN
EN
CVCC
PGOOD
RFBT
RFBB
GND
GND
HEATSINK
Top Trace
Bottom Trace
VIA
Ground Plane
VIA
Bottom
Figure 49. Example Layout for HSOIC (DDA) Package
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Layout Example (continued)
VOUT
VOUT
INDUCTOR
COUT
COUT
COUT
COUT
GND
GND
CIN
CIN
CHF
12
11
2
10
3
9
4
8
5
6
VIN
EN
PGOOD
7
RFBT
CBOOT
1
VIN
CHF
CVCC
RFBB
GND
HEATSINK
GND
HEATSINK
INNER GND PLANE
Top Trace/Plane
Inner GND Plane
VIN Strap on Inner Layer
Top
VIA to Signal Layer
Inner GND Plane
VIA to GND Planes
VIN Strap and
GND Plane
Signal traces
and GND Plane
VIA to VIN Strap
Trace on Signal Layer
Figure 50. Example Layout for VQFN Package
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12 Device and Documentation Support
12.1 Device Support
12.1.1 Development Support
12.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM33630 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
12.2 Documentation Support
12.2.1 Related Documentation
For related documentation see the following:
• Thermal Design by Insight not Hindsight
• A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages
• Semiconductor and IC Package Thermal Metrics
• Thermal Design Made Simple with LM43603 and LM43602
• SLMA002 PowerPADTM Thermally Enhanced Package
• PowerPADTM Made Easy
• SBVA025 Using New Thermal Metrics
• Layout Guidelines for Switching Power Supplies
• Simple Switcher PCB Layout Guidelines
• Construction Your Power Supply- Layout Considerations
• Low Radiated EMI Layout Made Simple with LM4360x and LM4600x
12.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
12.4 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
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12.5 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
SIMPLE SWITCHER, WEBENCH are registered trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
12.6 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.7 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OUTLINE
DDA0008J
PowerPADTM SOIC - 1.7 mm max height
SCALE 2.400
PLASTIC SMALL OUTLINE
C
6.2
TYP
5.8
SEATING PLANE
PIN 1 ID
AREA
A
0.1 C
6X 1.27
8
1
2X
3.81
5.0
4.8
NOTE 3
4
5
8X
B
4.0
3.8
NOTE 4
0.51
0.31
0.1
C A
1.7 MAX
B
0.25
TYP
0.10
SEE DETAIL A
5
4
EXPOSED
THERMAL PAD
0.25
GAGE PLANE
3.1
2.5
8
1
0 -8
0.15
0.00
1.27
0.40
DETAIL A
2.6
2.0
TYPICAL
4221637/B 03/2016
PowerPAD is a trademark of Texas Instruments.
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MS-012, variation BA.
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EXAMPLE BOARD LAYOUT
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.95)
NOTE 9
SOLDER MASK
DEFINED PAD
(2.6)
SOLDER MASK
OPENING
SEE DETAILS
8X (1.55)
1
8
8X (0.6)
SYMM
(1.3)
TYP
(3.1)
SOLDER MASK
OPENING
(4.9)
NOTE 9
6X (1.27)
5
4
( 0.2) TYP
VIA
METAL COVERED
BY SOLDER MASK
SYMM
(1.3) TYP
(5.4)
LAND PATTERN EXAMPLE
SCALE:10X
0.07 MIN
ALL AROUND
0.07 MAX
ALL AROUND
SOLDER MASK
OPENING
METAL
METAL UNDER
SOLDER MASK
SOLDER MASK
OPENING
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4221637/B 03/2016
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
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EXAMPLE STENCIL DESIGN
DDA0008J
PowerPAD TM SOIC - 1.7 mm max height
PLASTIC SMALL OUTLINE
(2.6)
BASED ON
0.125 THICK
STENCIL
8X (1.55)
1
8
8X (0.6)
(3.1)
BASED ON
0.127 THICK
STENCIL
SYMM
6X (1.27)
5
4
METAL COVERED
BY SOLDER MASK
SYMM
(5.4)
SEE TABLE FOR
DIFFERENT OPENINGS
FOR OTHER STENCIL
THICKNESSES
SOLDER PASTE EXAMPLE
EXPOSED PAD
100% PRINTED SOLDER COVERAGE BY AREA
SCALE:10X
STENCIL
THICKNESS
SOLDER STENCIL
OPENING
0.1
0.125
0.150
0.175
2.91 X 3.47
2.6 X 3.1 (SHOWN)
2.37 X 2.83
2.20 X 2.62
4221637/B 03/2016
NOTES: (continued)
10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
11. Board assembly site may have different recommendations for stencil design.
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PACKAGE OUTLINE
RNX0012B
VQFN-HR - 1 mm max height
SCALE 4.500
PLASTIC QUAD FLATPACK - NO LEAD
2.1
1.9
B
A
PIN 1 INDEX AREA
3.1
2.9
0.1 MIN
(0.05)
SECTION A-A
A-A 40.000
TYPICAL
1 MAX
C
SEATING PLANE
0.05
0.00
0.08 C
1
SYMM
(0.2) TYP
7
5
2X
0.675
2X
1.125
4X 0.5
8
4
PKG
1.725
1.525
2X
0.65
A
1
11
A
12
PIN 1 ID
11X
0.3
0.2
11X
0.5
0.3
0.3
0.2
0.1
0.05
C B A
C
4223969/B 03/2018
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
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SNVSAN3B – AUGUST 2017 – REVISED APRIL 2018
EXAMPLE BOARD LAYOUT
RNX0012B
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
(0.25)
12
11X (0.6)
1
11
2X (0.65)
11X
(0.25)
(1.825)
2X
(1.125)
(0.788)
PKG
2X
(0.675)
4X (0.5)
8
4
(1.4)
(R0.05) TYP
5
SYMM
7
(1.8)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:25X
0.07 MAX
ALL AROUND
0.07 MIN
ALL AROUND
SOLDER MASK
OPENING
METAL EDGE
EXPOSED
METAL
SOLDER MASK
OPENING
EXPOSED
METAL
NON SOLDER MASK
DEFINED
(PREFERRED)
METAL
SOLDER MASK
DEFINED
PADS 1, 2, 10-12
SOLDER MASK DETAILS
4223969/B 03/2018
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
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EXAMPLE STENCIL DESIGN
RNX0012B
VQFN-HR - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
2X (0.25)
2X (0.812)
12
11X (0.6)
11X (0.25)
1
11
2X
(0.65)
EXPOSED METAL
(1.294)
2X
(1.125)
PKG
(0.282)
2X (0.675)
4X (0.5)
8
4
(1.4)
(R0.05) TYP
5
SYMM
7
(1.8)
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
FOR PAD 12
87.7% PRINTED SOLDER COVERAGE BY AREA
SCALE:25X
4223969/B 03/2018
NOTES: (continued)
5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2018
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LMR33630ADDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33630A
LMR33630ADDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33630A
LMR33630ARNXR
ACTIVE
VQFN-HR
RNX
12
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
33630A
LMR33630ARNXT
ACTIVE
VQFN-HR
RNX
12
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
33630A
LMR33630BDDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33630B
LMR33630BDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33630B
LMR33630BRNXR
ACTIVE
VQFN-HR
RNX
12
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
33630B
LMR33630BRNXT
ACTIVE
VQFN-HR
RNX
12
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
33630B
LMR33630CDDA
ACTIVE SO PowerPAD
DDA
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33630C
LMR33630CDDAR
ACTIVE SO PowerPAD
DDA
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAUAG
Level-2-260C-1 YEAR
-40 to 125
33630C
LMR33630CRNXR
ACTIVE
VQFN-HR
RNX
12
3000
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
33630C
LMR33630CRNXT
ACTIVE
VQFN-HR
RNX
12
250
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
33630C
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2018
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Feb-2018
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
LMR33630ADDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
LMR33630BDDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
LMR33630CDDAR
SO
Power
PAD
DDA
8
2500
330.0
12.8
6.4
5.2
2.1
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Feb-2018
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LMR33630ADDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
LMR33630BDDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
LMR33630CDDAR
SO PowerPAD
DDA
8
2500
366.0
364.0
50.0
Pack Materials-Page 2
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support, pacemakers, defibrillators, heart pumps, neurostimulators, and implantables). Such equipment includes, without limitation, all
medical devices identified by the U.S. Food and Drug Administration as Class III devices and equivalent classifications outside the U.S.
TI may expressly designate certain products as completing a particular qualification (e.g., Q100, Military Grade, or Enhanced Product).
Designers agree that it has the necessary expertise to select the product with the appropriate qualification designation for their applications
and that proper product selection is at Designers’ own risk. Designers are solely responsible for compliance with all legal and regulatory
requirements in connection with such selection.
Designer will fully indemnify TI and its representatives against any damages, costs, losses, and/or liabilities arising out of Designer’s noncompliance with the terms and provisions of this Notice.
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