NSC LM27965SQ Dual display white led driver with i2c compatible brightness control Datasheet

LM27965
Dual Display White LED Driver with I2C Compatible
Brightness Control
General Description
Features
The LM27965 is a highly integrated charge-pump-based
dual-display LED driver. The device can drive up to 9 LEDs
in parallel with a total output current of 180mA. Regulated
internal current sinks deliver excellent current and brightness
matching in all LEDs.
The LED driver current sinks are split into three independently controlled groups. The primary group can beconfigurabled with 4 or 5 LEDs, for backlighting a larger main
display and the second group can be configured with 2 or 3
LEDs, for backlighing a smaller secondary display. An additional, independently controlled led driver is provided for
driving an indicator or general purpose LED. The LM27965
has an I2C compatible interface that allows the user to
independently control the brightness on each bank of LEDs.
The device provides excellent efficiency without the use of
an inductor by operating the charge pump in a gain of 3/2, or
in Pass-Mode. The proper gain for maintaining current regulation is chosen based on LED forward voltage, so that
efficiency is maximized over the input voltage range.
The LM27965 is available in National’s small 24-pin Leadless Leadframe Package (LLP-24).
91% Peak LED Drive Efficiency
No Inductor Required
0.3% Current Matching
Drives LEDs with up to 30mA per LED
180mA of total drive current
I2C Compatible Brightness Control Interface
Adaptive 1x - 3/2x Charge Pump
Resistor-Programmable Current Settings
External Chip RESET Pin
Extended Li-Ion Input: 2.7V to 5.5V
Small low profile industry standard leadless package,
LLP 24 : (4mm x 4mm x 0.8mm)
n 25mm2 total solution size
n
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Applications
n Mobile Phone Display Lighting
n PDA Backlighting
n General LED Lighting
Typical Application Circuit
20155001
© 2006 National Semiconductor Corporation
DS201550
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LM27965 -Dual Display White LED Driver System with I2C Compatible Brightness Control
May 2006
LM27965
Connection Diagram
24 Pin Quad LLP Package
NS Package Number SQA24A
20155002
Pin Descriptions
Pin #s
Pin Names
24
VIN
Pin Descriptions
Input voltage. Input range: 2.7V to 5.5V.
23
POUT
Charge Pump Output Voltage
19, 22 (C1)
20, 21 (C2)
C1, C2
Flying Capacitor Connections
12, 13, 14, 15,
16
D5A, D4A, D3A,
D2A, D1A
LED Drivers - GroupA
4, 5, 6
D1B, D2B, D3B
LED Drivers - GroupB
3
D1C
LED Driver - Indicator LED
17
ISET
Placing a resistor (RSET) between this pin and GND sets the full-scale LED
current for DxA , DxB, and D1C LEDs.
Full-Scale LED Current = 200 x (1.25V ÷ RSET)
1
SCL
Serial Clock Pin
2
SDIO
Serial Data Input/Output Pin
7
VIO
Serial Bus Voltage Level Pin
10
RESET
9, 18, DAP
GND
8, 11
NC
Harware Reset Pin. High = Normal Operation, Low = RESET
Ground
No Connect
Ordering Information
Order Information
LM27965SQ
LM27965SQX
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Package
SQA24 LLP
2
Supplied As
1000 Units, Tape & Reel
4500 Units, Tape & Reel
Operating Rating
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
VIN pin voltage
-0.3V to
(VPOUT+0.3V)
w/ 6.0V max
Continuous Power Dissipation
(Note 3)
Internally Limited
Junction Temperature (TJ-MAX)
150oC
Storage Temperature Range
-65oC to +150o C
Maximum Lead Temperature
(Soldering)
(Note 4)
ESD Rating(Note 5)
Human Body Model
2.0V to 4.0V
-30˚C to +100˚C
-30˚C to +85˚C
Thermal Properties
41.3˚C/W
Junction-to-Ambient Thermal
Resistance (θJA), SQA24A Package
(Note 7)
ESD Caution Notice National Semiconductor recommends that all integrated circuits be handled with
appropriate ESD precautions. Failure to observe proper
ESD handling techniques can result in damage to the
device.
2.0kV
Electrical Characteristics
2.7V to 5.5V
LED Voltage Range
Ambient Temperature (TA)
Range(Note 6)
-0.3V to (VIN+0.3V)
w/ 6.0V max
IDxx Pin Voltages
Input Voltage Range
Junction Temperature (TJ) Range
-0.3V to 6.0V
SCL, SDIO, VIO, RESET pin
voltages
(Notes 1, 2)
(Notes 2, 8)
Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = 3.6V; VRESET = VIN; VIO = 1.8V VDxA = VDxB = VDxC = 0.4V; RSET = 12.7kΩ; BankA = BankB =
BankC = Fullscale Current; ENA, ENB, ENC, EN5A, EN3B Bits = “1”; C1 = C2 = CIN= COUT= 1.0µF; Specifications related to
output current(s) and current setting pins (IDxx and ISET) apply to BankA and BankB. (Note 9)
Symbol
IDxx
Typ
Max
Units
Output Current Regulation
BankA or BankB Enabled
Parameter
3.0V ≤ VIN ≤ 5.5V
ENA = ’1’ or ENB = ’1’ and ENC= ’0’
18.2
(-9.5%)
20.1
22.0
(+9.5%)
mA
(%)
Output Current Regulation
BankC Enabled
3.0V ≤ VIN ≤ 5.5V
ENC = ’1’ and ENA = ENB= ’0’
19.2
(-7.7%)
20.8
22.4
(+7.7%)
mA
(%)
Maximum Diode Current per Dxx
Output(Note 10)
RSET = 8.33kΩ
Output Current Regulation
BankA, BankB, and BankC
Enabled
(Note 10)
IDxx-MATCH LED Current Matching(Note 11)
ROUT
Condition
Min
30
3.2V ≤ VIN ≤ 5.5V
VLED = 3.6V
mA
20
DxA
20
DxB
mA
20
DxC
3.0V ≤ VIN ≤ 5.5V
BankA
0.3
1.7
BankB
0.3
1.4
Gain = 3/2
2.75
%
Open-Loop Charge Pump Output
Resistance
Gain = 1
VDxTH
VDxx 1x to 3/2x Gain Transition
Threshold
VDxA and/or VDxB Falling
RSET = 16.9kΩ
175
mV
VHR
Current sink Headroom Voltage
Requirement
(Note 12)
IDxx = 95% xIDxx (nom.)
(IDxx (nom) ≈ 15mA)
RSET = 16.9kΩ
110
mV
IQ
Quiescent Supply Current
Gain = 1.5x, No Load
2.90
3.32
mA
5.4
µA
Ω
1
ISD
Shutdown Supply Current
All ENx bits = "0"
3.4
VSET
ISET Pin Voltage
2.7V ≤ VIN ≤ 5.5V
1.25
IDxA-B-C /
ISET
Output Current to Current Set
Ratio BankA, BankB, BankC
fSW
Switching Frequency
tSTART
Start-up Time
V
200
0.89
POUT = 90% steady state
3
1.27
250
1.57
MHz
µs
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LM27965
Absolute Maximum Ratings (Notes 1, 2)
LM27965
Electrical Characteristics (Notes 2, 8)
(Continued)
Limits in standard typeface are for TJ = 25˚C, and limits in boldface type apply over the full operating temperature range. Unless otherwise specified: VIN = 3.6V; VRESET = VIN; VIO = 1.8V VDxA = VDxB = VDxC = 0.4V; RSET = 12.7kΩ; BankA = BankB =
BankC = Fullscale Current; ENA, ENB, ENC, EN5A, EN3B Bits = “1”; C1 = C2 = CIN= COUT= 1.0µF; Specifications related to
output current(s) and current setting pins (IDxx and ISET) apply to BankA and BankB. (Note 9)
Symbol
Parameter
fPWM
Internal Diode Current PWM
Frequency
VRESET
Reset Voltage Thresholds
Condition
Min
Typ
Max
20
2.7V ≤ VIN ≤ 5.5V
Reset
Normal
Operation
Units
kHz
0
0.45
1.2
VIN
V
I2C Compatible Interface Voltage Specifications (SCL, SDIO, VIO)
VIO
Serial Bus Voltage Level
2.7V ≤ VIN ≤ 5.5V (Note 13)
1.4
VIN
V
VIL
Input Logic Low "0"
2.7V ≤ VIN ≤ 5.5V, VIO= 3.0V
0
0.3 x
VIO
V
VIH
Input Logic High "1"
2.7V ≤ VIN ≤ 5.5V, VIO= 3.0V
0.7 x
VIO
VIO
VOL
Output Logic Low "0"
ILOAD = 3mA
400
V
mV
I2C Compatible Interface Timing Specifications (SCL, SDIO, VIO)(Note 14)
t1
SCL (Clock Period)
2.5
µs
100
ns
0
ns
t2
Data In Setup Time to SCL High
t3
Data Out stable After SCL Low
t4
SDIO Low Setup Time to SCL Low
(Start)
100
ns
t5
SDIO High Hold Time After SCL
High (Stop)
100
ns
20155013
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of
the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the
Electrical Characteristics tables.
Note 2: All voltages are with respect to the potential at the GND pins.
Note 3: Internal thermal shutdown circuitry protects the device from permanent damage. Thermal shutdown engages at TJ = 170˚C (typ.) and disengages at TJ =
165˚C (typ.).
Note 4: For detailed soldering specifications and information, please refer to National Semiconductor Application Note 1187: Leadless Leadframe Package
(AN-1187).
Note 5: The human body model is a 100pF capacitor discharged through 1.5kΩ resistor into each pin. (MIL-STD-883 3015.7)
Note 6: In applications where high power dissipation and/or poor package thermal resistance is present, the maximum ambient temperature may have to be
derated. Maximum ambient temperature (TA-MAX) is dependent on the maximum operating junction temperature (TJ-MAX-OP = 100˚C), the maximum power
dissipation of the device in the application (PD-MAX), and the junction-to ambient thermal resistance of the part/package in the application (θJA), as given by the
following equation: TA-MAX = TJ-MAX-OP – (θJA x PD-MAX).
Note 7: Junction-to-ambient thermal resistance is highly dependent on application and board layout. In applications where high maximum power dissipation exists,
special care must be paid to thermal dissipation issues in board design. For more information, please refer to National Semiconductor Application Note 1187:
Leadless Leadframe Package (AN-1187).
Note 8: Min and Max limits are guaranteed by design, test, or statistical analysis. Typical numbers are not guaranteed, but do represent the most likely norm.
Note 9: CIN, CPOUT, C1, and C2 : Low-ESR Surface-Mount Ceramic Capacitors (MLCCs) used in setting electrical characteristics
Note 10: The maximum total output current for the LM27965 should be limited to 180mA. The total output current can be split among any of the three banks (IDxA
= IDxB = IDxC = 30mA Max.). Under maximum output current conditions, special attention must be given to input voltage and LED forward voltage to ensure proper
current regulation. See the Maximum Output Current section of the datasheet for more information.
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4
(Continued)
Note 11: For the two groups of current sinks on a part (BankA and BankB), the following are determined: the maximum sink current in the group (MAX), the minimum
sink current in the group (MIN), and the average sink current of the group (AVG). For each group, two matching numbers are calculated: (MAX-AVG)/AVG and
(AVG-MIN)/AVG. The largest number of the two (worst case) is considered the matching figure for the bank. The matching figure for a given part is considered to
be the highest matching figure of the two banks. The typical specification provided is the most likely norm of the matching figure for all parts.
Note 12: For each Dxx pin, headroom voltage is the voltage across the internal current sink connected to that pin. For Group A, B, and C current sinks, VHRx = VOUT
-VLED. If headroom voltage requirement is not met, LED current regulation will be compromised.
Note 13: SCL and SDIO signals are referenced to VIO and GND for minimum VIO voltage testing.
Note 14: SCL and SDIO should be glitch-free in order for proper brightness control to be realized.
Block Diagram
20155003
5
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LM27965
Electrical Characteristics (Notes 2, 8)
LM27965
Typical Performance Characteristics
Unless otherwise specified: TA = 25˚C; VIN = 3.6V; VRESET =
VIN; VLEDxA = VLEDxB = VLED1C = 3.6V; RSET = 16.9kΩ; C1=C2= CIN = CPOUT = 1µF; ENA = ENB = ENC =EN5A = EN3B =
’1’.
LED Drive Efficiency vs Input Voltage
Input Current vs Input Voltage
20155033
20155034
BankA Current Regulation vs Input Voltage
BankB Current Regulation vs Input Voltage
20155030
20155029
BankC Current Regulation vs Input Voltage
BankA Current Matching vs Input Voltage
20155028
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20155031
6
VIN; VLEDxA = VLEDxB = VLED1C = 3.6V; RSET = 16.9kΩ; C1=C2= CIN = CPOUT = 1µF; ENA = ENB = ENC =EN5A = EN3B =
’1’. (Continued)
BankB Current Matching vs Input Voltage
BankA Diode Current vs Brightness Register Code
20155032
20155026
BankB Diode Current vs Brightness Register Code
20155027
CIRCUIT COMPONENTS
Circuit Description
Charge Pump
The input to the 3/2x - 1x charge pump is connected to the
VIN pin, and the regulated output of the charge pump is
connected to the VOUT pin. The recommended input voltage
range of the LM27965 is 3.0V to 5.5V. The device’s regulated charge pump has both open loop and closed loop
modes of operation. When the device is in open loop, the
voltage at VOUT is equal to the gain times the voltage at the
input. When the device is in closed loop, the voltage at VOUT
is regulated to 4.6V (typ.). The charge pump gain transitions
are actively selected to maintain regulation based on LED
forward voltage and load requirements.
OVERVIEW
The LM27965 is a white LED driver system based upon an
adaptive 3/2x - 1x CMOS charge pump capable of supplying
up to 180mA of total output current. With three separately
controlled banks of constant current sinks, the LM27965 is
an ideal solution for platforms requiring a single white LED
driver for main display, sub display, and indicator lighting.
The tightly matched current sinks ensure uniform brightness
from the LEDs across the entire small-format display.
Each LED is configured in a common anode configuration,
with the peak drive current being programmed through the
use of an external RSET resistor. An I2C compatible interface
is used to enable the device and vary the brightness within
the individual current sink banks. For BankA and BankB, 32
levels of brightness control are available. The brightness
control is achieved through a mix of analog and pulse width
modulated (PWM) methods. BankC has 4 analog brightness
levels available.
LED Forward Voltage Monitoring
The LM27965 has the ability to switch converter gains (1x or
3/2x) based on the forward voltage of the LED load. This
ability to switch gains maximizes efficiency for a given load.
Forward voltage monitoring occurs on all diode pins within
BankA and BankB. At higher input voltages, the LM27965
7
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LM27965
Typical Performance Characteristics Unless otherwise specified: TA = 25˚C; VIN = 3.6V; VRESET =
LM27965
Circuit Description
(Continued)
A pull-up resistor between VIO and SDIO must be greater
than [ (VIO-VOL) / 3mA] to meet the VOL requirement on
SDIO. Using a larger pull-up resistor results in lower switching current with slower edges, while using a smaller pull-up
results in higher switching currents with faster edges.
will operate in pass mode, allowing the POUT voltage to track
the input voltage. As the input voltage drops, the voltage on
the DXX pins will also drop (VDXX = VPOUT – VLEDx). Once
any of the active Dxx pins reaches a voltage approximately
equal to 175mV, the charge pump will switch to the gain of
3/2. This switch-over ensures that the current through the
LEDs never becomes pinched off due to a lack of headroom
across the current sinks.
START AND STOP CONDITIONS
START and STOP conditions classify the beginning and the
end of the I2C session. A START condition is defined as
SDIO signal transitioning from HIGH to LOW while SCL line
is HIGH. A STOP condition is defined as the SDIO transitioning from LOW to HIGH while SCL is HIGH. The I2C master
always generates START and STOP conditions. The I2C bus
is considered to be busy after a START condition and free
after a STOP condition. During data transmission, the I2C
master can generate repeated START conditions. First
START and repeated START conditions are equivalent,
function-wise.
Only active Dxx pins will be monitored. For example, if only
BankA is enabled, the LEDs in BankB will not affect the gain
transition point. If both banks are enabled, all diodes will be
monitored, and the gain transition will be based upon the
diode with the highest forward voltage. Diode pins D5A and
D3B can have the diode sensing circuity disabled through
the general purpose register if those drivers are not going to
be used.
BankC (D1C) is not a monitored LED current sink.
RESETPin
The LM27965 has a hardware reset pin (RESET) that allows
the device to be disabled by an external controller without
requiring an I2C write command. Under normal operation,
the RESET pin should be held high (logic ’1’) to prevent an
unwanted reset. When the RESET is driven low (logic ’0’), all
internal control registers reset to the default states and the
part becomes disabled. Please see the Electrical Characteristics section of the datasheet for required voltage thresholds.
20155011
FIGURE 2. Start and Stop Conditions
TRANSFERING DATA
I2C Compatible Interface
Every byte put on the SDIO line must be eight bits long, with
the most significant bit (MSB) transferred first. Each byte of
data has to be followed by an acknowledge bit. The acknowledge related clock pulse is generated by the master. The
master releases the SDIO line (HIGH) during the acknowledge clock pulse. The LM27965 pulls down the SDIO line
during the 9th clock pulse, signifying an acknowledge. The
LM27965 generates an acknowledge after each byte is received.
After the START condition, the I2C master sends a chip
address. This address is seven bits long followed by an
eighth bit which is a data direction bit (R/W). The LM27965
address is 36h. For the eighth bit, a “0” indicates a WRITE
and a “1” indicates a READ. The second byte selects the
register to which the data will be written. The third byte
contains data to write to the selected register.
DATA VALIDITY
The data on SDIO line must be stable during the HIGH
period of the clock signal (SCL). In other words, state of the
data line can only be changed when CLK is LOW.
20155025
FIGURE 1. Data Validity Diagram
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8
LM27965
Circuit Description
(Continued)
20155012
FIGURE 3. Write Cycle
w = write (SDIO = "0")
r = read (SDIO = "1")
ack = acknowledge (SDIO pulled down by either master or slave)
id = chip address, 36h for LM27965
I2C COMPATIBLE CHIP ADDRESS
The chip address for LM27965 is 0110110, or 36h.
Note: ENA: Enables DxA LED drivers (Main Display)
ENB: Enables DxB LED drivers (Aux Lighting)
ENC: Enables D1C LED driver (Indicator Lighting)
EN5A: Enables D5A LED voltage sense
EN3B: Enables D3B LED driver and voltage sense
20155009
20155005
FIGURE 4. Chip Address
INTERNAL REGISTERS OF LM27965
Internal Hex
Address
Power On
Value
10h
0010 0000
Bank A Brightness A0h
Control Register
1110 0000
Bank B
B0h
Brightness Control
Register
1110 0000
Bank C
C0h
Brightness Control
Register
1111 1100
Register
General Purpose
Register
20155006
20155007
FIGURE 6. Brightness Control Register Description
Internal Hex Address: 0xA0 (BankA), 0xB0 (BankB),
0xC0 (BankC)
Note: DxA4-DxA0: Sets Brightness for DxA pins (BankA). 11111=Fullscale
DxB4-DxB0: Sets Brightness for DxB pins (BankB). 11111=Fullscale
Bit7 to Bit 5: Not Used
DxC1-DxC0: Sets Brightness for DxC pin. 11 = Fullscale
Bit7 to Bit2:Not Used
Full-Scale Current set externally by the following equation:
20155008
IDxx = 200 x 1.25V / RSET
FIGURE 5. General Purpose Register Description
Internal Hex Address: 10h
9
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LM27965
Circuit Description
(Continued)
Brightness Level Control Table (BankA and BankB)
Brightness Code (hex)
Analog Current (% of
Full-Scale)
Duty Cycle (%)
Perceived Brightness
Level (%)
00
20
1/16
1.25
01
20
2/16
2.5
02
20
3/16
3.75
03
20
4/16
5
04
20
5/16
6.25
05
20
6/16
7.5
06
20
7/16
8.75
07
20
8/16
10
08
20
9/16
11.25
09
20
10/16
12.5
0A
20
11/16
13.75
0B
20
12/16
15
0C
20
13/16
16.25
0D
20
14/16
17.5
0E
20
15/16
18.75
0F
20
16/16
20
10
40
10/16
25
11
40
11/16
27.5
12
40
12/16
30
13
40
13/16
32.5
14
40
14/16
35
15
40
15/16
37.5
16
40
16/16
40
17
70
11/16
48.125
18
70
12/16
52.5
19
70
13/16
56.875
1A
70
14/16
61.25
65.625
1B
70
15/16
1C
70
16/16
70
1D
100
13/16
81.25
1E
100
15/16
93.75
1F
100
16/16
100
BankC Brightness Levels (%of Full-Scale) = 20%, 40%,
70%, 100%
Once the desired RSET value has been chosen, the
LM27965 has the ability to internally dim the LEDs using a
mix of Pulse Width Modulation (PWM) and analog current
scaling. The PWM duty cycle is set through the I2C compatible interface. LEDs connected to BankA and BankB current
sinks (DxA and DxB) can be dimmed to 32 different levels/
duty-cycles. The internal PWM frequency for BankA and
BankB is fixed at 20kHz. BankC(D1C) has 4 analog current
levels.
Please refer to the I2C Compatible Interface section of this
datasheet for detailed instructions on how to adjust the
brightness control registers.
Application Information
SETTING LED CURRENT
The current through the LEDs connected to DxA and DxB
can be set to a desired level simply by connecting an appropriately sized resistor (RSET) between the ISET pin of the
LM27965 and GND. The DxA and DxB LED currents are
proportional to the current that flows out of the ISET pin and
are a factor of 200 times greater than the ISET current. The
feedback loops of the internal amplifiers set the voltage of
the ISET pin to 1.25V (typ.). The statements above are simplified in the equations below:
IDxA/B/C (A)= 200 x (VISET / RSET)
RSET (Ω)= 200 x (1.25V / IDxA/B/C)
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PARALLEL CONNECTED AND UNUSED OUTPUTS
Outputs D1A-5A or D1B-D3B may be connected together to
drive one or two LEDs at higher currents. In such a configuration, all five parallel current sinks (BankA) of equal value
can drive a single LED. The LED current programmed for
BankA should be chosen so that the current through each of
the outputs is programmed to 20% of the total desired LED
current. For example, if 60mA is the desired drive current for
a single LED, RSET should be selected such that the current
through each of the current sink inputs is 12mA.
(Continued)
MAXIMUM OUTPUT CURRENT, MAXIMUM LED
VOLTAGE, MINIMUM INPUT VOLTAGE
The LM27965 can drive 8 LEDs at 22.5mA each (BankA and
BankB) from an input voltage as low as 3.2V, so long as the
LEDs have a forward voltage of 3.6V or less (room temperature).
The statement above is a simple example of the LED drive
capabilities of the LM27965. The statement contains the key
application parameters that are required to validate an LEDdrive design using the LM27965: LED current (ILEDx), number of active LEDs (Nx), LED forward voltage (VLED), and
minimum input voltage (VIN-MIN).
Connecting the outputs in parallel does not affect internal
operation of the LM27965 and has no impact on the Electrical Characteristics and limits previously presented. The
available diode output current, maximum diode voltage, and
all other specifications provided in the Electrical Characteristics table apply to this parallel output configuration, just as
they do to the standard 5-LED application circuit.
Both BankA and BankB utilize LED forward voltage sensing
circuitry on each Dxx pin to optimize the charge-pump gain
for maximum efficiency. Due to the nature of the sensing
circuitry, it is not recommended to leave any of the DxA
(D1A-D4A) or DxB (D1B-D2B) pins open if either diode bank
is going to be used during normal operation. Leaving DxA
and/or DxB pins unconnected will force the charge-pump
into 3/2x mode over the entire VIN range negating any efficiency gain that could have been achieved by switching to 1x
mode at higher input voltages.
If D5A is not used, it is recommended that the driver pin be
grounded and the general purpose register bit EN5A be set
to 0 to ensure proper gain transitions.
The D3B driver can be completely turned on or off on the fly
using the general purpose register. The diode monitoring
circuity is enabled and disabled with the driver. If D3B is not
used, it is recommended that the driver pin be grounded and
the general purpose register bit EN3B be set to 0 to ensure
proper gain transitions.
Care must be taken when selecting the proper RSET value.
The current on any Dxx pin must not exceed the maximum
current rating for any given current sink pin.
The equation below can be used to estimate the maximum
output current capability of the LM27965:
ILED_MAX = [(1.5 x VIN) - VLED - (IADDITIONAL x ROUT)] /
[(Nx x ROUT) + kHRx] (eq. 1)
ILED_MAX = [(1.5 x VIN ) - VLED - (IADDITIONAL x 2.75Ω)] /
[(Nx x 2.75Ω) + kHRx]
IADDITIONAL is the additional current that could be delivered
to the other LED banks.
ROUT – Output resistance. This parameter models the internal losses of the charge pump that result in voltage droop at
the pump output POUT. Since the magnitude of the voltage
droop is proportional to the total output current of the charge
pump, the loss parameter is modeled as a resistance. The
output resistance of the LM27965 is typically 2.75Ω (VIN =
3.6V, TA = 25˚C). In equation form:
VPOUT = (1.5 x VIN) – [(NAx ILEDA + NB x ILEDB ) x
(eq. 2)
ROUT]
kHR – Headroom constant. This parameter models the minimum voltage required to be present across the current sinks
for them to regulate properly. This minimum voltage is proportional to the programmed LED current, so the constant
has units of mV/mA. The typical kHR of the LM27965 is
8mV/mA. In equation form:
(eq. 3)
(VPOUT – VLEDx) > kHRx x ILEDx
Typical Headroom Constant Values
kHRA = 8mV/mA
kHRB = 8mV/mA
The "ILED-MAX" equation (eq. 1) is obtained from combining
the ROUT equation (eq. 2) with the kHRx equation (eq. 3) and
solving for ILEDx. Maximum LED current is highly dependent
on minimum input voltage and LED forward voltage. Output
current capability can be increased by raising the minimum
input voltage of the application, or by selecting an LED with
a lower forward voltage. Excessive power dissipation may
also limit output current capability of an application.
POWER EFFICIENCY
Efficiency of LED drivers is commonly taken to be the ratio of
power consumed by the LEDs (PLED) to the power drawn at
the input of the part (PIN). With a 3/2x - 1x charge pump, the
input current is equal to the charge pump gain times the
output current (total LED current). The efficiency of the
LM27965 can be predicted as follows:
PLEDTOTAL = (VLEDA x NA x ILEDA) +
(VLEDB x NB x ILEDB) + (VLEDC x ILEDC)
PIN = VIN x IIN
PIN = VIN x (GAIN x ILEDTOTAL + IQ)
E = (PLEDTOTAL ÷ PIN)
Total Output Current Capability
The maximum output current that can be drawn from the
LM27965 is 180mA. Each driver bank has a maximum allotted current per Dxx sink that must not be exceeded.
DRIVER TYPE
MAXIMUM Dxx CURRENT
DxA
30mA per DxA Pin
DxB
30mA per DxB Pin
DxC
30mA per DxB Pin
The LED voltage is the main contributor to the charge-pump
gain selection process. Use of low forward-voltage LEDs
(3.0V- to 3.5V) will allow the LM27965 to stay in the gain of
1x for a higher percentage of the lithium-ion battery voltage
range when compared to the use of higher forward voltage
LEDs (3.5V to 4.0V). See the LED Forward Voltage Monitoring section of this datasheet for a more detailed description
of the gain selection and transition process.
For an advanced analysis, it is recommended that power
consumed by the circuit (VIN x IIN) for a given load be
evaluated rather than power efficiency.
The 180mA load can be distributed in many different configurations. Special care must be taken when running the
LM27965 at the maximum output current to ensure proper
functionality.
11
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LM27965
Application Information
LM27965
Application Information
series resistance (ESR < 20mΩ typ.). Tantalum capacitors,
OS-CON capacitors, and aluminum electrolytic capacitors
are not recommended for use with the LM27965 due to their
high ESR, as compared to ceramic capacitors.
For most applications, ceramic capacitors with X7R or X5R
temperature characteristic are preferred for use with the
LM27965. These capacitors have tight capacitance tolerance (as good as ± 10%) and hold their value over temperature (X7R: ± 15% over -55˚C to 125˚C; X5R: ± 15% over
-55˚C to 85˚C).
(Continued)
POWER DISSIPATION
The power dissipation (PDISS) and junction temperature (TJ)
can be approximated with the equations below. PIN is the
power generated by the 3/2x - 1x charge pump, PLED is the
power consumed by the LEDs, TA is the ambient temperature, and θJA is the junction-to-ambient thermal resistance
for the LLP-24 package. VIN is the input voltage to the
LM27965, VLED is the nominal LED forward voltage, N is the
number of LEDs and ILED is the programmed LED current.
PDISS = PIN - PLEDA - PLEDB - PLEDC
Capacitors with Y5V or Z5U temperature characteristic are
generally not recommended for use with the LM27965. Capacitors with these temperature characteristics typically
have wide capacitance tolerance (+80%, -20%) and vary
significantly over temperature (Y5V: +22%, -82% over -30˚C
to +85˚C range; Z5U: +22%, -56% over +10˚C to +85˚C
range). Under some conditions, a nominal 1µF Y5V or Z5U
capacitor could have a capacitance of only 0.1µF. Such
detrimental deviation is likely to cause Y5V and Z5U capacitors to fail to meet the minimum capacitance requirements of
the LM27965.
The minimum voltage rating acceptable for all capacitors is 6.3V. The recommended voltage rating for the
capacitors is 10V to account for DC bias capacitance
losses.
PDISS= (GAIN x VIN x IBANKA + BANKB + BANKC ) - (VLEDA x
NA x ILEDA) - (VLEDB x NB x ILEDB) - (VLEDC x ILEDC)
TJ = TA + (PDISS x θJA)
The junction temperature rating takes precedence over the
ambient temperature rating. The LM27965 may be operated
outside the ambient temperature rating, so long as the junction temperature of the device does not exceed the maximum operating rating of 100˚C. The maximum ambient temperature rating must be derated in applications where high
power dissipation and/or poor thermal resistance causes the
junction temperature to exceed 100˚C.
THERMAL PROTECTION
Internal thermal protection circuitry disables the LM27965
when the junction temperature exceeds 170˚C (typ.). This
feature protects the device from being damaged by high die
temperatures that might otherwise result from excessive
power dissipation. The device will recover and operate normally when the junction temperature falls below 165˚C (typ.).
It is important that the board layout provide good thermal
conduction to keep the junction temperature within the specified operating ratings.
PCB LAYOUT CONSIDERATIONS
The LLP is a leadframe based Chip Scale Package (CSP)
with very good thermal properties. This package has an
exposed DAP (die attach pad) at the center of the package
measuring 2.6mm x 2.5mm. The main advantage of this
exposed DAP is to offer lower thermal resistance when it is
soldered to the thermal land on the PCB. For PCB layout,
National highly recommends a 1:1 ratio between the package and the PCB thermal land. To further enhance thermal
conductivity, the PCB thermal land may include vias to a
ground plane. For more detailed instructions on mounting
LLP packages, please refer to National Semiconductor Application Note AN-1187.
CAPACITOR SELECTION
The LM27965 requires 4 external capacitors for proper operation (C1 = C2 = CIN = COUT = 1µF). Surface-mount
multi-layer ceramic capacitors are recommended. These capacitors are small, inexpensive and have very low equivalent
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12
inches (millimeters) unless otherwise noted
SQA24: 24 Lead LLP
X1 = 4.0mm
X2 = 4.0mm
X3 = 0.8mm
National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves
the right at any time without notice to change said circuitry and specifications.
For the most current product information visit us at www.national.com.
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WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR
CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body, or
(b) support or sustain life, and whose failure to perform when
properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result
in a significant injury to the user.
2. A critical component is any component of a life support
device or system whose failure to perform can be reasonably
expected to cause the failure of the life support device or
system, or to affect its safety or effectiveness.
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LM27965 -Dual Display White LED Driver System with I2C Compatible Brightness Control
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