STMicroelectronics L6995STR Lossless current limit Datasheet

L6995S
STEP DOWN CONTROLLER FOR HIGH DIFFERENTIAL
INPUT-OUTPUT CONVERSION
1
Figure 1. Package
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FEATURES
CONSTANT ON TIME TOPOLOGY ALLOWS
OPERATION WITH LOWER DUTY THAN
PWM TOPOLOGY
VERY FAST LOAD TRANSIENTS
5V Vcc SUPPLY
1.5V TO 35V INPUT VOLTAGE RANGE
0.9V ±1% VREF
MINIMUM OUTPUT VOLTAGE AS LOW AS 0.9V
SELECTABLE SINKING MODE
LOSSLESS CURRENT LIMIT
REMOTE SENSING
OVP,UVP LATCHED PROTECTIONS
600µA TYP QUIESCENT CURRENT
POWER GOOD AND OVP SIGNALS
PULSE SKIPPING AT LIGHT LOADS
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2
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APPLICATIONS
I/O BUS FOR CPU CORE SUPPLY
NOTEBOOK COMPUTERS
NETWORKING DC-DC
DISTRIBUTED POWER
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TSSOP20
Table 1. Order Codes
Part Number
Package
L6995S
TSSOP20
L6995STR
Tape & Reel
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DESCRIPTION
The device is a step-down controller specifically designed to provide extremely high efficiency conversion, with losses current sensing tecnique.
The "constant on-time" topology assures fast load
transient response. The embedded "voltage feed-forward" provides nearly constant switching frequency
operation.
An integrator can be introduced in the control loop to
reduce the static output voltage error.
The available remote sensing improve the static and
dynamic regulation recovering the wires voltage
drop. Pulse skipping technique reduces power consumption at light load. Drivers current capability allows output current in excess of 20A.
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Figure 2. Minimum Component Count Application
Rin1
5V
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VDR
CIN
SHDN
VCC
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35V
Rin2
OSC
bs
5V
BOOT
HGATE
C
HS
PHASE
O
LGATE
D
BOOT
BOOT
Vo
L
LS
RILIM
DS
0.9V
COUT
PGND
ILIM
L6995S
GND
NOSKIP
VSENSE
SS
CSS
INT
VFB
VREF
CVREF
April 2004
REV. 1
1/26
L6995S
Table 2. Absolute Maximum Ratings
Symbol
Value
Unit
VCC
VCC to GND
Parameter
-0.3 to 6
V
VDR
VDR to GND
-0.3 to 6
V
HGATE and BOOT, to PHASE
-0.3 to 6
V
VPHASE
BOOT, HGATE
and PHASE
PINS
HGATE and BOOT, to PGND
-0.3 to 42
V
PHASE
-0.3-to 36
V
LGATE to PGND
-0.3 to VDR+0.3
V
ILIM, VFB, VSENSE, NOSKIP, SHDN, PGOOD, OVP, VREF,
INT, GNDSENSE to GND
-0.3 to VCC+0.3
V
±750
V
Maximum Withstanding Voltage Range
Test Condition:CDF-AEC-Q100-002 “Human Body Model”
Accepatance Criteria: “Normal Performance”
OTHER PINS
Ptot
Power dissipation at Tamb = 25°C
Tstg
Storage temperature range
±2000
V
1
W
-40 to 150
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Table 3. Thermal Data
Symbol
Rth j-amb
Parameter
Thermal Resistance Junction to Ambient
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Junction operating temperature range
Tj
Figure 3. Pin Connection (Top View)
NOSKIP
1
GNDSENSE
2
(s)
INT
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BOOT
19
HGATE
18
PHASE
17
VDR
VCC
5
16
LGATE
GND
6
15
PGND
VREF
7
14
PGOOD
VFB
8
13
OVP
OSC
9
12
SHDN
10
11
ILIM
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20
4
SS
Value
Unit
125
°C/W
0 to 125
°C
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VSENSE
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°C
TSSOP20
Table 4. Pin Function
N°
2/26
Name
Description
1
NOSKIP Connect to VCC to force continuous conduction mode and sink mode.
2
GNDSE
NSE
3
INT
4
VSENS
E
Remote ground sensing pin
Integrator output. Short this pin to VFB pin and connect it via a capacitor to VOUT to insert the
integrator in the control loop. If the integrator is not used, short this pin to VREF.
This pin must be connected to the remote output voltage to detect overvoltage and undervoltage
conditions and to provide integrator feedback input.
L6995S
Table 4. Pin Function (continued)
N°
Name
5
VCC
Description
IC Supply Voltage.
6
GND
Signal ground
7
VREF
0.9 V voltage reference. Connect max. a 10nF ceramic capacitor between this pin and ground.
This pin is capable to source or sink up to 250uA
8
VFB
PWM comparator feedback input. Short this pin to INT pin when using the integrator function, or
to VSENSE pin without integrator.
9
OSC
Connect this pin to the input voltage through a voltage divider in order to provide the feedforward function. It cannot be left floating.
10
SS
Soft start pin. A 5µA constant current charges an external capacitor which value sets the softstart time.
11
ILIM
12
SHDN
An external resistor connected between this pin and GND sets the current limit threshold.
Shutdown. When connected to GND the device and the drivers are OFF. It cannot be left floating.
13
OVP
14
PGOOD
Open drain output. During the over voltage condition it is pulled up by an external resistor.
15
PGND
Low Side driver ground.
16
LGATE
Low Side driver output.
17
VDR
Low Side driver supply.
18
PHASE
Return path of the High Side driver.
19
HGATE
High side MOSFETS driver output.
20
BOOT
Bootstrap capacitor pin. High Side driver is supplied through this pin.
Open drain output. During the soft start and in case of output voltage fault it is low. It is pulled up
by external resistor.
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Table 5. Electrical Characteristics
(VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified)
Symbol
Parameter
)
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SUPPLY SECTION
Vin
Input voltage range
VCC,
VDR
VCC
Turn-onvoltage
Vout=Vref Fsw=110Khz Iout=1A
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Turn-off voltage
Test Condition
Min.
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IqVcc
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Max.
1.5
35
V
5.5
V
4.2
4.4
V
4.1
4.3
V
100
Quiescent Current Drivers
VFB > VREF
Device Quiescent current
VFB > VREF
Unit
4.5
Hysteresis
IqVDR
Typ.
400
mV
20
µA
600
µA
SHUTDOWN SECTION
SHDN
Device On
1.2
V
Device Off
ISHVDR
Drivers shutdown current
SHDN to GND
ISHVCC
Devices shutdown current
SHDN to GND
10
0.6
V
5
µA
15
µA
6
µA
500
mV
SOFT START SECTION
ISS
Soft Start current
VSS = 0.8V
4
SS Clamp Voltage
Soft start active range
4
400
450
V
3/26
L6995S
Table 5. Electrical Characteristics (continued)
(VCC = VDR = 5V; Tamb = 0°C to 85°C unless otherwise specified)
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
4.9
5
5.1
µA
2
mV
CURRENT LIMIT AND ZERO CURRENT COMPARATOR
ILIM input bias current
RILIM = 2KΩ to 400KΩ
Zero Crossing Comparator Offset
Phase-gnd
-2
ON TIME
Ton
On time duration
VREF=VSENSE OSC=250mV
850
950
1050
ns
VREF=VSENSE OSC=500mV
470
520
570
ns
VREF=VSENSE OSC=1V
250
285
320
ns
VREF=VSENSE OSC=2V
130
160
190
ns
580
ns
OFF TIME
TOFFMIN
Minimum off time
KOSC/TOFFMIN
OSC=250mV
0.30
0µA < IREF < 100µA
0.891
0.60
VOLTAGE REFERENCE
VREF
Voltage Accuracy
0.9
Input voltage offset
IFB
-2
Input Bias Current
INT
Over Voltage Clamp
VSENSE = VCC
Under Voltage Clamp
VSENSE = GND
Integrator Input Offset Voltage
VSENSE-VREF
IVSENSE
Input Bias Current
GATE DRIVERS
High side rise time
High side fall time
Low side rise time
Low side fall time
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mV
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0.1
INTEGRATOR
INT
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PWM COMPARATOR
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0.909
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µA
1.04
1.07
1.1
0.82
0.84
0.86
V
5
mV
-5
V
µA
0.1
VDR=3.3V; C=7nF
HGATE - PHASE from 1 to 3V
50
70
ns
50
70
ns
VDR=3.3V; C=14nF
LGATE from 1 to 3V
50
70
ns
50
70
ns
112
115
118
%
66
69
72
%
PGOOD UVP/OVP PROTECTIONS
OVP
Over voltage threshold
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UVP
PGOOD
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PGOOD
VPGOOD
4/26
with respect to VREF
Under voltage threshold
Upper threshold
(VSENSE-VREF)
VSENSE rising
107
110
113
%
Lower threshold
(VSENSE-VREF)
VSENSE falling
86
89
92
%
0.14
0.2
V
ISink=2mA
V IN
5 uA
VREF
0.9V
power management
1.416
VREF
1.236V
bandgap
HS control
pwm comparator
Reference chain
+
+
-
-
+
+
IC enable
soft-start
control
S
R
NOSKIP
1.15 VREF
-
VSENSE
0.69 VREF
-
+
-
+
0.89 VREF
VSENSE
VSENSE
1.10 VREF
pgood comparators
+
-
undervoltage comparator
VSENSE
+
overvoltage comparator
one-shot
Ton
Ton min
one-shot
Toff min
delay
LS control
Q
GND
zero-cross comparator
-
+
no-skip
mode
Ton= Kosc V(VSENSE)/V(OSC)
PHASE
S
R
VCC
no-skip
mode
R
S
Q
V(PHASE)<0.2V
comp
V(LGATE)<0.5V
comp
LS and HS anti-cross-conduction comparators
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-
OSC
SENSEGND
Gm
VREF
0.2
+
positive current limit
comparator
PHASE
VREF
VSENSE
INT
FB
ILIM
SS
OVP
VSENSE
PGOOD
OSC
one-shot
Ton
Q
OSC
LS driver
HS driver
Ton= Kosc V(VSENSE)/V(OSC)
S
R
level shifter
VCC
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VSENSE
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SHDN
PGND
LGATE
VDR
PHASE
HGATE
BOOT
5V
V IN
V OUT
L6995S
Figure 4. Functional & Block Diagram
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L6995S
4
DEVICE DESCRIPTION
4.1 Constant On Time PWM topology
Figure 5. Loop block schematic diagram
Vin
R1
One-shot generator
OSC
R2
FFSR
R Q
Vsense
HS
Vout
HGATE
S
Vref
Q
LS
+
-
DS
LGATE
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PWM comparator
FB
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The device implements a Constant On Time control scheme, where the Ton is the high side MOSFET on time
duration forced by the one-shot generator. The on time is directly proportional to VSENSE pin voltage and inverse to OSC pin voltage as in Eq1:
V SENSE
T ON = K OSC ---------------------- + τ
V OSC
Eq 1
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where KOSC = 250ns and τ is the internal propagation delay time (typ. 70ns). The system imposes in steady
state a minimum on time corresponding to VOSC = 2V. In fact if the VOSC voltage increases above 2V the corresponding Ton will not decrease. Connecting the OSC pin to a voltage partition from VIN to GND, it allows a
steady-state switching frequency FSW independent of VIN. It results:
Eq 2
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Eq 4
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V OUT 1
α OSC 1
f SW = --------------- ----------- = --------------- --------------- → α OSC = f SW K OSC α OUT
V IN T ON
α OUT K OSC
V OSC
R2
- = -------------------α OSC = -------------V IN
R2 + R 1
R4
V FB
α OUT = -------------- = -------------------V OUT
R 3 + R4
The above equations allow setting the frequency divider ratio αOSC once output voltage has been set; note that
such equations hold only if VOSC<2V. Further the Eq2 shows how the system has a switching frequency ideally
independent from the input voltage. The delay introduces a light dependence from VIN. A minimum off-time constrain of about 580ns is introduced in order to assure the boot capacitor charge and to limit the switching fre6/26
L6995S
quency after a load transient as well as to mask PWM comparator output against noise and spikes.
The system has not an internal clock, because this is a hysteretic controller, so the turn on pulse will start if three
conditions are met contemporarily: the FB pin voltage is lower than the reference voltage, the minimum off time
is passed and the current limit comparator is not triggered (i.e. the inductor current is below the current limit
value). The voltage on the OSC pin must range between 50mV and 2V to ensure the system linearity.
4.2 Closing the loop
The loop is closed connecting the output voltage (or the output divider middle point) to the FB pin. The FB pin
is linked internally to the comparator negative pin and the positive pin is connected to the reference voltage
(0.9V Typ.) as in Figure 2. When the FB goes lower than the reference voltage, the PWM comparator output
goes high and sets the flip-flop output, turning on the high side MOSFET. This condition is latched to avoid noise
spike. After the on-time (calculated as described in the previous section) the system resets the flip-flop and then
turns off the high side MOSFET and turns on the low side MOSFET. Internally the device has more complex
logic than a flip-flop to manage the transition in correct way. For more details refers to the Figure 3.
The voltage drop along ground and supply metals connecting output capacitor to the load is a source of DC
error. Further the system regulates the output voltage valley value not the average, as in the Figure 5 is shown.
So the voltage ripple on the output capacitor is a source of DC static error (as the PCB traces). To compensate
the DC errors, an integrator network must be introduced in the control loop, by connecting the output voltage to
the INT pin through a capacitor and the FB pin to the INT pin directly as in Figure 6. The internal integrator amplifier with the external capacitor CINT1 introduces a DC pole in the control loop. CINT1 also provides an AC path
for output ripple.
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Figure 6. Valley regulation
Vout
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DC Error Offset
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<Vout>
Vref
Time
The integrator amplifier generates a current, proportional to the DC errors, that increases the output capacitance
voltage in order to compensate the total static errors. A voltage clamper within the device forces INT pin voltage
ranges from VREF-50mV, VREF+150mV. This is useful to avoid or smooth output voltage overshoot during a load
transient. Also, this means that the integrator is capable of recovering output error due to ripple when its peakto-peak amplitude is less than 150mV in steady state.
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In case of the ripple amplitude is larger than 150mV, a capacitor CINT2 can be connected between INT pin and
ground to reduce ripple amplitude at INT pin, otherwise the integrator can operate out of its linear range. Choose
CINT1 according to the following equation:
Eq 5
g INT ⋅ α OUT
C INT1 = -----------------------------2 ⋅ π ⋅ Fu
where GINT=50 µs is the integrator transconductance, αOUT is the output divider ratio given from Eq4 and FU
is the close loop bandwidth. This equation also holds if CINT2 is connected between INT pin and ground. CINT2
is given by:
7/26
L6995S
C INT2
∆V OUT
---------------- = -----------------C INT1
V INT
Eq 6
Where ∆VOUT is the output ripple and ∆VINT is the ripple wanted at the INT pin (100mV typ).
Figure 7. Integrator loop block diagram
Vin
R1
One-shot generator
PCB TRACES
OSC
FFSR
R Q
R2
HS
From Vsense
S
Vref
Q
LS
FB
Vout
HGATE
+
-
LOAD
DS
LGATE
PWM comparator
+
INT
+
Cint2
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Vref
Vsense
Gndsense
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Integrator amplifier
Cint1
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Respect to a traditional PWM controller, that has an internal oscillator setting the switching frequency, in a hysteretic system the frequency can change with some parameters (input voltage, output current). In L6995S is implemented the voltage feed-forward circuit that allows constant switching frequency during steady-sate
operation with the input voltage variation. There are many factors affecting switching frequency accuracy in
steady-state operation. Some of these are internal as dead times, which depend on high side MOSFET driver.
Others related to the external components as high side MOSFET gate charge and gate resistance, voltage
drops on supply and ground rails, low side and high side RDSON and inductor parasitic resistance.
)
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During a positive load transient, (the output current increases), the converter switches at its maximum frequency
(the period is TON+TOFFmin) to recover the output voltage drop. During a negative load transient, (the output
current decreases), the device stops to switch (high side MOSFET remains off).
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4.3 Transition from PWM to PFM/PSK
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To achieve high efficiency at light load conditions, PFM mode is provided. The PFM mode differs from the PWM
mode essentially for the off section; the on section is the same. In PFM after a turn-on cycle the system turnson the low side MOSFET, until the inductor current reaches the zero A value, when the zero-crossing comparator turns off the low side MOSFET. In this way the energy stored in the output capacitor will not flow to ground,
through the low side MOSFET, but it will flow to the load. In PWM mode, after a turn on cycle, the system keeps
the low side MOSFET on until the next turn-on cycle, so the energy stored in the output capacitor will flow
through the low side MOSFET to ground. The PFM mode is naturally implemented in hysteretic controller, in
fact in PFM mode the system reads the output voltage with a comparator and then turns on the high side MOSFET when the output voltage goes down a reference value. The device works in discontinuous mode at light
load and in continuous mode at high load. The transition from PFM to PWM occurs when load current is around
half the inductor current ripple. This threshold value depends on VIN, L, and VOUT. Note that the higher the in-
8/26
L6995S
ductor value is, the smaller the threshold is. On the other hand, the bigger the inductor value is, the slower the
transient response is. In PFM mode the frequency changes, with the output current changing, more than in
PWM mode; in fact if the output current increase, the output voltage decreases more quickly; so the successive
turn-on arrives before, increasing the switching frequency. The PFM waveforms may appear more noisy and
asynchronous than normal operation, but this is normal behaviour mainly due to the very low load. If the PFM
is not compatible with the application it can be disabled connecting to VCC the NOSKIP pin.
4.4 Softstart
If the supply voltages are already applied, the SHDN pin gives the start-up. The system starts with the high side
MOSFET off and the low side MOSFET on. After the SHDN pin is turned on the SS pin voltage begins to increase and the system starts to switch. The softstart is realized by gradually increasing the current limit threshold to avoid output overvoltage. The active soft start range for the VSS voltage (where the output current limit
increase linearly) starts from 0.6V to 1.5V. In this range an internal current source (5µA Typ) charges the capacitor on the SS pin; the reference current (for the current limit comparator) forced through ILIM pin is proportional to SS pin voltage and it saturates at 5µA (Typ.) when SS voltage is close to 1.5V and the maximum current
limit is active. Undervoltage protection is disabled until SS pin voltage reaches 1.5V; instead the overvoltage is
always present (see figure 7).
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Once the SS pin voltage reaches the 1.5V value, the voltage on SS pin doesn't impact the system operation
anymore. If the SHDN pin is turned on before the supplies, the correct start-up sequence is the following: first
turn-on the power section and after the logic section (VCC pin).
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Figure 8. Soft -Start Diagram
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4.1V
1.5V
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Soft-start active range
0.6V
(s)
Ilim current
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5µA
od
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Time
Maximum current limit
Time
Because the system implements the soft start controlling the inductor current, the soft start capacitor selection
is function of the output capacitance, the current limit and the soft start active range (∆VSS).
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In order to select the softstart capacitor it must be imposed that the output voltage reaches the final value before
the soft start voltage reaches the under voltage value (1.5V). In other words the output voltage charging time
has to be lower than the uvp time.
The UVP time is given by:
Eq 7
V uvp
T uvp ( C SS ) = ------------ ⋅ C SS
Iss
In order to calculate the output volatge chargin time it should be calculated, before, the output volatrge function
versus time. This function can be calculated from the inductor current function; the inductor current function can
9/26
L6995S
be supposed linear function of the time.
( R ilim /R dson ⋅ K C ⋅ I SS ⋅ t )
I L ( t,C SS ) = ------------------------------------------------------------------( ∆V SS ⋅ C SS )
Eq 8
so the output voltage is given by:
2
( R ilim /R dson ⋅ K C ⋅ I SS ⋅ t )
Q ( t,C SS )
V out ( t,C SS ) = ------------------------ = ---------------------------------------------------------------------C out
( C out ⋅ ∆V SS ⋅ C SS ⋅ 2 )
Eq 9
calling Vout as the Vout final value, the output charging time can be estimated as:
( V out ⋅ C out ⋅ ∆V SS ⋅ C SS ⋅ 2 ) 0.5
I out ( C SS ) = ---------------------------------------------------------------------------( R ilim /R dson ⋅ K C ⋅ I SS )
Eq 10
the minimum CSS value is given imposing this condition:
Eq 11
Tout =Tuvp
4.5 Current limit
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The current limit comparator senses the inductor current through the low side MOSFET RDSON drop and compares this value with the ILIM pin voltage value. While the current is above the current limit value, the control
inhibits the one-shot start.
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To properly set the current limit threshold, it should be noted that this is a valley current limit. Average current
depends on the inductor value, VIN VOUT and switching frequency.
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The average output current in current limit is given by:
Eq 12
I OUT
∆I
= I max valley + ----2
CL
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Thus, to set the current threshold, choose RILIM according to the following equation:
)
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R ILim I Lim
I max valley = ----------------- ⋅ ---------Rds on 5.2
Eq 13
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In current limit the system keeps the current constant until the output voltage meets the undervolatge threshold.
The system is capable to sink current, but it has not a negative current limit.
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The system accuracy is function of the exactness of the resistance connected to ILIM pin and the low side MOSFET RDSON accuracy. Moreover the voltage on ILIM pin must range between 10mV and 2V to ensure the system linearity.
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Figure 9. Current limit schematic
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To inductor
O
LS
RILIM
PHASE
PGN
D
Current
Comparator
5µA
Positive current limit
10/26
To
logic
L6995S
4.6 Protection and fault
Sensing VSENSE pin voltage performs output protection. The nature of the fault (that is, latched OV or latched
UV) is given by the PGOOD and OVP pins. If the output voltage is between the 89% (typ.) and 110% (typ) of
the regulated value, PGOOD is high. If a hard overvoltage or an undervoltage occurs, the device is latched: low
side MOSFET is turned on, high side MOSFET is turned off and PGOOD goes low. In case the system detects
an overvoltage the OVP pin goes high.
To recover the functionality the device must be shut down and restarted thought the SHDN pin, or the supply
has to be removed, and restart with the correct sequence.
These features are useful to protect against short-circuit (UV fault) as well as high side MOSFET short (OV
fault).
4.7 Drivers
The integrated high-current drivers allow using different size of power MOSFET, maintaining fast switching transition. The driver for the high side MOSFET uses the BOOT pin for supply and PHASE pin for return (floating
driver). The driver for the low side MOSFET uses the VDR pin for the supply and PGND pin for the return. The
main feature is the adaptive anti-cross-conduction protection, which prevents from both high side and low side
MOSFET to be on at the same time, avoiding a high current to flow from VIN to GND. When high side MOSFET
is turned off the voltage on the pin PHASE begins to fall; the low side MOSFET is turned on only when the voltage on PHASE pin reaches 250mV. When low side is turned off, high side remains off until LGATE pin voltage
reaches 500mV. This is important since the driver can work properly with a large range of external power MOSFETS.
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The current necessary to switch the external MOSFETS flows through the device, and it is proportional to the
MOSFET gate charge and the switching frequency. So the power dissipation of the device is function of the external power MOSFET gate charge and switching frequency.
P driver = V cc ⋅ Q gTOT ⋅ F SW
Eq 14
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The maximum gate charge values for the low side and high side are given from:
Eq 15
f SW0
Q MAXHS = ------------- ⋅ 75nC
f SW
Eq 16
f SW0
Q MAXLS = ------------- ⋅ 125nC
f SW
)
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Where fSW0 = 500Khz. The equations above are valid for TJ = 150°C. If the system temperature is lower the QG
can be higher.
For the Low Side driver the max output gate charge meets another limit due to the internal traces degradation;
in this case the maximum value is QMAXLS = 125nC.
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The low side driver has been designed to have a low resistance pull-down transistor, around 0.5 ohms. This
prevents the voltage on LGATE pin raises during the fast rise-time of the pin PHASE, due to the Miller effect.
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5
APPLICATION INFORMATION
5.1 20A Demo board description
The demoboard shows the device operation in general purpose applications. The evaluation board allows using
only one supply because the on board linear regulator LM317LD; the linear regulator supplies the device
through the J1. Output current in excess of 20A can be reached dependently on the MOSFET type. The SW1
is used to start the device (when the supplies are already present) and to select the PFM/PWM mode.
11/26
L6995S
Figure 10. Demoboard Schematic Diagram
5V
J1
VIN
LM317LD
R1
C1
R2
C5
R5
R3
C2
C13,14,15,16,17,18
VCC
VDR
R4
C3
OSC
BOOT
D1
HGATE
C22
R6
Q1,2,3,
C19
Vout
R7
PHASE
L
R9
PGOOD
LOAD
LGATE
OVP
Q4,5,6
L6995S
5V
NOSKIP
VSENSE
GNDSENSE
SS
R11
VFB
VREF
SHDN
Without Int.
Rn
5.2 Jumper Connection
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Table 6. Jumper connection with integrator
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Rn
Component
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Connection
C4
Mounted
C7
Mounted *
INT
Close
NOINT
Open
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With Int
With Int.
C6 C7
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C24
C23
INT
R12
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R13
Without Int.
C4
C20
* This component is not necessary, depends from the output ESR capacitor. See the integrator section.
Table 7. Jumper connection without integrator
12/26
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R10
GND
R8
5V
C7,8,9,10,11,12
PGND
ILIM
C21
D2
Component
Connection
C4
Not mounted
C7
Not Mounted
INT
Open
NOINT
Close
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L6995S
5.3 NOTE
There is a linear regulator on board, it allows to use one generator (only for the power section, in fact the IC
section is powered by the linear regulator); if the regulator is used close the J1, other wise it has to keep open.
Be careful measuring the efficiency with the linear regulator asserted.
At high current in the integrator configuration (around 20A), it can be seen an oscillation in the switching frequency due to the noise interaction, to reduce this oscillation put a noise filter RN, CN like in the figure 9. Note
the RN resistor is in the place of the INT jumper near C4. RN, CN, should be selected with a pole frequency
around 1Mhz, but anyway higher than switching frequency (five times).
5.4 DEMOBOARD LAYOUT
Real dimensions: 5,7 cm X 7,7 cm (2,28inch X 3, 08inch)
Figure 11. PCB layout: bottom side
Figure 13. Internal ground plane
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Figure 12. PCB Layout: Top side
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Figure 14. Power & signal plane
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13/26
L6995S
Table 8. PCB Layout guidelines
Goal
Suggestion
Low radiation and low magnetic coupling
with the adjacent circuitry.
1) Small switching current loop areas. (For example placing CIN, High
Side and Low side MOSFETS, Shottky diode as close as possible).
2) Controller placed as close as possible to the power MOSFET.
3) Group the gate drive component (Boot cap and diode together near
the IC.
Don’t penalty the efficiency.
Keep power traces and load connections short and wide.
Ensure high accuracy in the current sense
system.
Phase pin and PGND pin must be made with Kelvin connection and as
close as possible to the Low Side MOSFETS.
Reduce the noise effect on IC.
1) Put the feedback component (like output divider, integrator network,
etc) as close as possible to the IC.
2) The feedback traces must be parallel and as close as possible.
Moreover they must be routed as far as possible from the switching
current loops.
3) Make the controller ground connection like the figure 19.
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Table 9. Component list
)
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The component list is shared in two sections: the first for the general-purpose component, the second for power
section:
GENERAL-PURPOSE SECTION
Part name
Value
Dimension
R1
100Ω
0603
R2
300Ω
R3
560kΩ
R4
33kΩ
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RESISTOR
R5
47Ω
R6, R7, R11, R12
33kΩ
47kΩ
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R9
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R10
R13
Notes
Output resistor divider for the
linear regulator.
0603
0603
(s)
ct
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R8
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Input resistor divider
(To set switching frequency)
0603
0603
0603
0603
Current limit resistor
(To set current limit)
390Ω
0603
Output resistor divider
(To set output voltage)
1KΩ
0603
220Ω
0603
CAPACITOR
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14/26
C1
220nF
0805
C2
47µF
KEMET-16V
C3
220nF
0805
C4
330pF
0603
C5
47pF
0603
C6
10nF
0603
C7
N.M.
0603
C19
220nF
0805
C20
220nF
0603
First integrator capacitor
Second integrator capacitor
Softstart capacitor
L6995S
Part name
Value
Dimension
C21
47pF
0603
C22
220nF
0805
C23
Notes
0603
C24
1nF
0603
C25
1uF
Tantalum
D1
BAT54
N.M.
DIODES
25V
POWER SECTION
OUTPUT CAPACITORS
C10-C11-C12
3X330uF
EEFUE0D331R
PANASONIC
Output capacitor C8, C9 N.M.
10uF
C34Y5U1E106Z
TOKIN
Input capacitor
10uF
C3225Y5V1E106Z
TDK
INPUT CAPACITORS
C13, C14, C16, C17,
C15 C18
Part name
Value
Dimension
10uF
ECJ4XF1E106Z
PANASONIC
10uF
TMK325F106ZH
TAIYO YUDEN
0.6µH
ETQP6F0R6BFA
PANASONIC
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INDUCTOR
L1
0.6µH
Q1,Q2
0.6µH
DXM1306-R60-T COEV
0.6µH
CEP12D38H0R6 SUMIDA
)
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Q5,Q6
STS11NF3LL
STMicroelectronics
Q3 N.M.
STSJ25NF3LL
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STMicroelectronics
Q3 N.M.
STS25NH3LL
STMicroelectronics
Q4 N.M.
STPS3L40U
STMicroelectronics
25V
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DIODES
D2
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A959ASR60N
TOKO
POWER MOS
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Notes
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INTEGRATED CIRCUIT
U1
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U2
LM317LD
Linear regulator
L6995S
Switcher
Notes: 1. N.M.=Not Mounted
2. The demoboard with this component list is set to give: VOUT = 1.25V, FSW = 270kHz with an input voltage around VIN = 20V with
the integrator feature, and with 20A continuos output current.
3. All capacitors are intended ceramic type otherwise specified.
15/26
L6995S
6
STEP BY STEP DESIGN
VIN = 20V VOUT = 1.25V IOUT = 20A FSW = 270kHz
In this design it is considered a low profile demoboard, so a great attention is given to the components height.
6.1 Input capacitor.
A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC component of this current is quite high and dissipates a considerable amount of power on the ESR capacitor:
2 Vin ⋅ ( Vin – Vout )
P CIN = ESR CIN ⋅ Iout ⋅ -----------------------------------------------2
Vin
Eq 17
The IRMS current is given by:
Icin rms =
Eq 18
2
2
δ
Iout δ ( 1 – δ ) + ------ ( ∆I L )
12
Neglecting the last term, the equation reduces to:
Icin rms = Iout δ ( 1 – δ )
Eq 19
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which maximum value corresponds to δ = 1/2.
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ICINRMS, has a maximum equal to δ = 1/2 (@ VIN = 2×VOUT, that is, 50% duty cycle). The input capacitor,
therefore, should be selected with an RMS rated current higher than ICINRMS. Electrolytic capacitors are the
most used because are the cheapest ones and are available with a wide range of RMS current ratings. The only
drawback is that, considering a requested ripple current rating, they are physically larger than other capacitors.
Very good tantalum capacitors are coming available, with very low ESR and small size. The only problem is that
they occasionally can burn out if subjected to very high current during the charge. So, it is better avoid this type
of capacitors for the input filter of the device. In fact, they can be subjected to high surge current when connected
to the power supply. If available for the requested value and voltage rating, the ceramic capacitors have usually
a higher RMS current rating for a given physical size (due to the very low ESR). From the equation 18 it is found:
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Icinrms = 4.8A
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Considering 10µF capacitors ceramic, that have ICINRMS =1.5A, 6 pzs. are needed.
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6.2 Inductor
In order to determine the inductor value is necessary considering the maximum output current to decide the inductor current saturation. Once the inductor current saturation it is found automatically is found the inductor value. In our design it is considered a very low profile inductor.
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bs
L = 0.6µH
O
The saturation current for this choke is around 25A
6.3 Output capacitor
The output capacitor is chosen by the output voltage static and dynamic accuracy. The static accuracy is related
to the output voltage ripple value, while the dynamic accuracy is related to the output current load step.
If the static precision is around ± 2% for the 1.25V output, the output accuracy is ±25mV.
To determine the ESR value from the output precision is necessary before calculate the ripple current:
16/26
L6995S
Vin – Vo Vo
∆I = ----------------------- ⋅ --------- ⋅ T sw
L
Vin
Eq 20
Considering a switching frequency around 270kHz from the equation above the ripple current is around 7A.
So the maximum ESR should be:
∆V ripple
ESR = -------------------- = 7mΩ
∆
-----I
2
Eq 21
The dynamic specifications are sometimes more relaxed than the static requirements so the ESR value around
7mΩ should be enough.
The current ripple flows through the output capacitor, so the output capacitors should be calculated also to sustain this ripple: the RMS current value is given from Eq22.
1
Icout rms = ----------- ∆I L
2 3
Eq 22
But this is usually a negligible constrain when choosing output capacitor.
)
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To allow the device control loop to work properly output capacitor zero should be at the least ten times smaller
than switching frequency. The output capacitor value (COUT) and the output capacitor ESR (ESROUT) should be
large enough and small enough, to keep the output voltage ripple within the specification and to give to the device a minimum signal to noise ratio.
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6.4 Power MOSFETS and Schottky Diodes
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Since a 5V bus powers the gate drivers of the device, the use of logic-level MOSFETS is highly recommended,
especially for high current applications. The breakdown voltage VBRDSS must be greater than VINMAX with a
certain margin.
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The RDSON can be selected once the allowable power dissipation has been established. By selecting identical
Power MOSFET for the main switch and the synchronous rectifier, the total power they dissipate does not depend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required
RDSON (@ 25 °C) can be derived from:
)
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P ON
RDS ON = -----------------------------------------------2
Iout ⋅ ( 1 + α ⋅ ∆T )
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Eq 23
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α is the temperature coefficient of RDSON (typically, α = 510-3 °C-1 for these low-voltage classes) and ∆T the
admitted temperature rise. It is worth noticing, however, that generally the lower RDSON, the higher is the gate
charge QG, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge QG moves
from the input source to ground, resulting in an equivalent drive current:
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Eq 24
Iq = Qg ⋅ FSW
O
For application with low Duty Cycle, where the input voltage is high (around 20V) it is very important to select
the high side MOSFET with low gate charge, to reduce the switching losses as STS11NF3LL. For the low side
section should be selected a low RDSON as STS25NH3LL.
A SCHOTTKY diode can be added to increase the system efficiency at high switching frequency (where the
dead times could be an important part of total switching period).
This optional diode must be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM
greater than VINMAX. The current size of the diode must be selected in order to keep it in safe operating conditions.
17/26
L6995S
6.5 Output voltage setting
To select the output divider network there isn't a specific criteria, but a low divider network value (around 100Ω)
reduces the efficiency at low current; instead a high value divider network (500KΩ) increase the noise effects.
A network divider values from 1K to 50K is right. From the Eq4:
R10 = 1KΩ
R9 = 390Ω
The device output voltage is adjustable by connecting a voltage divider from output to VSENSE pin. Minimum
output voltage is VOUT = VREF = 0.9V. Once output divider and frequency divider have been designed as to obtain the required output voltage and switching frequency, the following equation gives the smallest input voltage,
which allows L6995S to regulate (which corresponds to TOFF = TOFF, MIN):
α OSC
1
δ < 1 – --------------- ⋅ -----------------------------α OUT  K
OSC 
 ------------------------
 T OFFMIN
Eq 25
where the KOSC/TOFFMIN ratio worst-case is given in electrical characteristic table (pag. 4).
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6.6 Voltage Feed Forward
)
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Choosing the switching frequency around 270KHz from the Eq1. It can be selected the input divider. For example:
R3=560KΩ
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R4=28KΩ
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In order to compensate the comparator delay R4 resistor should be increased around 20%.
R4=33KΩ
6.7 Current limit resistor
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From the Eq13 can be set the valley current limit, knowing the low side RDSON. To set the exact current limit it
must be considered the temperature effect. So two STS25NH3LL have 2.75mΩ @ 25°C, at 100°C can be considered 3.85mΩ.
)
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R8 = 47KΩ
6.8 Integrator capacitor
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Let it be FU = 15kHz.
Since VREF = 0.9V, from Eq4, it follows αOUT = 0.72 and, from Eq5 it follows CINT1 = 330pF. Because the ripple
is lower than 150mV the system doesn't need the second integrator capacitor.
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6.9 Soft start capacitor
Considering the soft start equations (Eq. 11) at page 10, it can be found:
CSS = 200pF
These equations are valid whitout load. When an active load is present the equantions result more complex;
further some active loads have unexpected effect, as higher current than the expected one during the start up,
that can change the start up time.
In this case the capacitor value can be selected on the application; anyway the Eq11 gives an idea about the
CSS value.
18/26
L6995S
6.9.1 Efficiency
VIN = 20V VOUT = 1.25V FSW = 270KHz
Figure 15. Efficiency vs output current
Ef f [ %]
85
80
75
70
65
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60
0,0
4,0
8,0
1 2,0
16 ,0
20 ,0
Cu r r e n t [A]
V in=20 V V o u t=1.25 V Fsw =22 0Khz PFM
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R7
C8
(s)
R4
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R5
R10
TP1
VDR
ct
VCC
C11 C10
du
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R6
Vcc
J1
C7,C13
VIin
GNDin
OSC
BOOT
C4
HGATE
D1
Q1
L1
VOUT
PHASE
R3
PGOOD
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ILIM
R8
C12
Q2
LGATE
OVP
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TP2
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V in=20 V V o ut=1 .25 V Fs w =22 0K hz PW M
6.10 5A demo Board
Figure 16. Schematic Diagram
24 ,0
)
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D2
C14,C15
R1
L6995S
U1
R2
PGND
GND
GNDOUT
NOSKIP
VSENSE
GNDSENSE
SS
NOINT
C9
C3
INT
INT
R9
VFB
SHDN
C1
VREF
C6
NOINT
SD
TP3
C5
INT
C2
NS
Cn
Rn
19/26
L6995S
6.11 DEMOBOARD LAYOUT
Real dimensions: 4.7 cm X 2.7 cm (1.85inch X1.063inch)
Figure 17. Top side components placement
Figure 19. Top side layout
Figure 18. Bottom side Jumpers distribution
Figure 20. Bottom side layout
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Table 10. Component list
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GENERAL-PURPOSE SECTION
Part name
RESISTOR
R1, R5, R9, R10
R2
R3
R4
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R6
R7
R8
CAPACITOR
C1
C2
C3
C4
C5
C6
C8, C12
C9
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20/26
Value
Dimension
Notes
du
0603
0603
Pull-up resistor
Output resistor divider
(To set output voltage)
10kΩ
21kΩ
0603
0603
470kΩ
47Ω
120kΩ
0603
0603
0603
330pF
N.M.
N.M.
100nF
1µF
10nF
47pF
22nF
0603
0603
0603
0603
Tantalum
0603
0603
0603
33kΩ
10kΩ
Input resistor divider
(To set switching frequency)
Current limit resistor
First integrator capacitor
Second integrator capacitor
N.M.
Softstart capacitor
L6995S
Part name
C10
C11
DIODE
D1
Value
100nF
100nF
Dimension
0603
0603
Notes
BAR18
POWER SECTION
INPUT CAPACITORS
C7, C13
OUTPUT CAPACITORS
C14, C15
10µF
C34Y5U1E106ZTE12 TOKIN
330µF
EEFUE0D331R
PANASONIC
INDUCTOR
L1
2.7µH
DO3316P-272HC
COILCRAFT
ETQP6H2R2GF
PANASONIC
DQ7545
COEV
2.2µH
3.3µH
POWER MOS
Q1,Q2
DIODE
D2
)
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STS8DNF3LL
STMicroelectronics
Dual MOSFETS in single package
STPS3L40U
STMicroelectronics
3
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Notes: 1. N.M.=Not Mounted
2. The demoboard with this component list is set to give: VOUT = 1.8V, FSW = 250kHz with an input voltage around VIN = 20V and
with the integrator feature.
3. The diode efficiency impact is very low; it is not a necessary component.
4. All capacitors are intended ceramic type otherwise specified.
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6.11.1Efficiency
Vin = 20V Vout = 1.8V Fsw = 270kHz
Figure 21. Efficiency vs output current
)
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Ef f [ %]
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-
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90
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80
s
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70
60
50
40
30
0,0
0,5
1 ,0
1,5
2,0
2,5
3,0
3,5
4,0
4,5
5,0
5 ,5
6,0
Cu r r e n t [A]
V in=20V V ou t=1.8V Fs w =270K hz PW M
V in=2 0V V out=1 .8V Fs w =2 70Khz PFM
21/26
L6995S
7
TYPICAL OPERATING WAVEFORMS
The measurements refer to the part list in table 4. Vin = 20V Vout = 1.25V Fsw = 270kHz Tamb = 25°C.
Figure 22. Soft Start with no load.
Figure 24. Normal functionality in PSK mode.
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Ch1-> Inductor current
Ch2-> Output voltage
Ch1-> Inductor current
Ch2-> Output voltage
Ch3-> Phase voltage
Figure 23. Soft Start with 20A load.
Figure 25. Normal functionality in PWM mode.
)
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Ch1-> Inductor current
Ch2-> Output voltage
Ch3-> Soft Start voltage
22/26
Ch1-> Inductor current
Ch2-> Output voltage
Ch3-> Phase voltage
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L6995S
Figure 26. Load transient from 0 to 18A.
Figure 28. Switching Frequency Vs Output
current
Fsw
[ Khz]
350
300
250
200
P SK/P FM
150
P WM
100
50
0
5
10
15
20
25
V in [ V ]
Ch1-> Output current
Ch2-> Output voltage
Ch3->Phase voltage
Figure 27. Load transient from 18A to 0A..
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Figure 29. Switching Frequency Vs Input
Voltage
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Fsw
[ K h z]
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3 50
3 00
)
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Ch1-> Output current
Ch2-> Output voltage
Ch3->Phase voltage
s
b
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2 50
2 00
150
PFM
100
PW M
50
0
0 ,0
5 ,0
10,0
15 ,0
2 0,0
25 ,0
C u rre n t [ A ]
23/26
L6995S
Figure 30. TSSOP20 Mechanical Data & Package Dimensions
mm
inch
DIM.
MIN.
TYP.
A
MAX.
MIN.
TYP.
1.20
A1
0.050
A2
0.800
b
MAX.
0.047
0.150
0.002
1.050
0.031
0.190
0.300
0.007
0.012
c
0.090
0.200
0.004
0.008
D (1)
6.400
6.500
6.600
0.252
0.256
0.260
E
6.200
6.400
6.600
0.244
0.252
0.260
E1 (1) 4.300
4.400
4.500
0.170
0.173
0.177
e
L
1.000
0.650
0.450
L1
0.600
0.006
0.039
0.041
0.026
0.750
0.018
1.000
k
OUTLINE AND
MECHANICAL DATA
0.024
c
u
d
0.030
0.039
aaa
0˚ (min.) 8˚ (max.)
0.100
0.004
Note: 1. D and E1 does not include mold flash or protrusions.
Mold flash or potrusions shall not exceed 0.15mm
(.006inch) per side.
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Thin Shrink Small Outline Package
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0087225 (Jedec MO-153-AC)
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Table 11. Revision History
Date
Revision
April 2004
1
Description of Changes
First Issue
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