IRF IR3827MPBF 6a highly integrated supirbuck single-input voltage, synchronous buck regulator Datasheet

6A Highly Integrated SupIRBuckTM SingleInput Voltage, Synchronous Buck Regulator
FEATURES
IR3827
DESCRIPTION
• Single input voltage range from 5V to 21V
• Wide input voltage range from 1.0V to 21V with
external VCC bias voltage
• Output voltage range from 0.6V to 0.86% PVin
The IR3827 SupIRBuckTM is an easy-to-use, fully
integrated and highly efficient DC/DC regulator.
The onboard PWM controller and MOSFETs make
IR3827 a space-efficient solution, providing accurate
power delivery for low output voltage applications.
• Enhanced line/load regulation with feedforward
IR3827 is a versatile regulator which offers
programmable switching frequency and internally set
current limit while operating in wide range of input and
output voltage conditions.
• Programmable switching frequency up to
1.2MHz
• Three user selectable soft-start time
• User selectable LDO output voltage
• Enable input with voltage monitoring capability
• Thermally compensated current limit with robust
hiccup mode over current protection
• Synchronization to an external clock
• Enhanced Pre-bias start-up
• Precise reference voltage (0.6V+/-0.6%)
The switching frequency is programmable from 300kHz
to 1.2MHz for an optimum solution. It also features
important protection functions, such as Pre-Bias
startup, thermally compensated current limit, over
voltage protection and thermal shutdown to give
required system level security in the event of fault
conditions.
APPLICATIONS
• Open-drain PGood indication
• Optional power up sequencing
• Computing Applications
• Integrated MOSFET drivers and bootstrap diode
• Set Top Box Applications
• Thermal Shut Down
• Storage Applications
• Monotonic Start-Up
• Data Center Applications
• Operating temp: -40°C < Tj < 125°C
• Distributed Point of Load Power Architectures
• Package size: 4mm x 5mm PQFN
• Lead-free, Halogen-free and RoHS6 Compliant
ORDERING INFORMATION
Base Part Number
Package Type
IR3827
IR3827
PQFN 4 mm x 5 mm
PQFN 4 mm x 5 mm
Standard Pack
Form
Quantity
Tape and Reel
750
Tape and Reel
4000
Orderable Part Number
IR3827MTR1PBF
IR3827MTRPBF
IR3827      
PBF – Lead Free
TR/TR1 – Tape and Reel
M – PQFN Package
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© 2013 International Rectifier
July 18, 2013
IR3827
BASIC APPLICATION
Vin
SS_Select Vin
Vcc/
LDO_out
PGood
PGood
Seq
Enable
Rt/Sync
PVin
Boot
Vo
SW
IR3827
Fb
Comp
LDO_Select Gnd PGnd
Figure 1 IR3827 Basic Application Circuit
Figure 2 IR3827 Efficiency
PINOUT DIAGRAM
IR3827
PVin
SW
13
12
PGnd
11
Boot 14
10 Vcc/LDO_Out
GND
Enable 15
9
17
Vin
8 LDO_Select
d
7
PG
oo
t
ele
c
c
6
SS_
S
Syn
Gn
d
5
Rt/
4
mp
N/
3
Co
2
C
1
Fb
Seq 16
Figure 3 4mm x 5mm PQFN (Top View)
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© 2013 International Rectifier
July 18, 2013
IR3827
BLOCK DIAGRAM
5.1V/6.9V
Internal LDO
Vin
VCC
Vcc/ LDO_Out
THERMAL
TSD
SHUT DOWN
LDO_Select
OC
FAULT
POR
CONTROL
UVcc
Gnd
UVcc
Boot
OV
Comp
Seq
+
+
E/A
+
-
VREF
+
0.6V 0.15V
FAULT
POR VCC
PVin
Vin
Fb
Fb
HDrv
POR
INTL_SS
VREF
OV
OVER
VOLTAGE
HDin
SW
GATE
DRIVE
LDin
SS_Select
SOFT
START
POR
SSOK
LDrv
CONTROL
VREF
FAULT
PGnd
SEQ
Enable
LOGIC
UVEN
UVEN
OC
Over Current
Protection
POR
UVcc
POR
Rt/Sync PGood
Figure 4 Simplified Block Diagram
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© 2013 International Rectifier
July 18, 2013
IR3827
PIN DESCRIPTIONS
PIN #
PIN NAME
PIN DESCRIPTION
1
Fb
Inverting input to the error amplifier. This pin is connected directly to the output of the
regulator via a resistor divider to set the output voltage and to provide the feedback signal
to the error amplifier.
2
N/C
3
Comp
4, 17
Gnd
5
Rt/Sync
Multi-function pin to set the switching frequency. The internal oscillator frequency is set
with a resistor between this pin and Gnd. Or synchronization to an external clock by
connecting this pin to the external clock signal through a diode.
6
SS_Select
Soft start selection pin. Three user selectable soft start time is available: 1.5ms
(SS_Select=Vcc), 3ms (SS_Select=Float), 6ms (SS_Select=Gnd)
7
PGood
8
LDO_Select
Should not be connected to other signals on PCB layout. It is internally connected for
testing purpose.
Output of error amplifier. An external resistor and capacitor network is typically connected
from this pin to Fb pin to form a loop compensator.
Signal ground for internal reference and control circuitry.
Open-drain power good indication pin. Connect a pull-up resistor from this pin to Vcc.
LDO output voltage selection pin. Float gives 5.1V and low 0V (Gnd) gives 6.9V
Input for internal LDO. A 1.0µF capacitor should be connected between this pin and
PGnd. If external supply is connected to Vcc/LDO_out pin, this pin should be shorted to
Vcc/LDO_out pin. Connecting this pin to PVin can also implement the input voltage
feedforward.
9
Vin
10
Vcc/LDO_Out
11
PGnd
12
SW
Switch node. Connected this pin to the output inductor.
13
PVin
Input voltage for power stage.
14
Boot
Supply voltage for high side driver, a 100nF capacitor should be connected between this
pin and SW pin.
15
Enable
Enable pin to turn on and off the device. Input voltage monitoring (input UVLO) can also
be implemented by connecting this pin to PVin pin through a resistor divider.
16
Seq
Sequence pin to do simultaneous and ratiometric sequencing operation. A resistor divider
can be connected from master output to this pin for sequencing mode of operation. If not
used, leave it open.
17
Gnd
Signal ground for internal reference and control circuitry.
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Output of the internal LDO and optional input of an external biased supply voltage.
minimum 2.2µF ceramic capacitor is recommended between this pin and PGnd.
A
Power Ground. This pin serves as a separated ground for the MOSFET drivers and
should be connected to the system’s power ground plane.
© 2013 International Rectifier
July 18, 2013
IR3827
ABSOLUTE MAXIMUM RATINGS
Stresses beyond these listed under “Absolute Maximum Ratings” may cause permanent damage to the device.
These are stress ratings only and functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications are not implied.
PVin, Vin to PGnd (Note 4)
-0.3V to 25V
Vcc/LDO_Out to PGnd (Note 4)
-0.3V to 8V (Note 1)
Boot to PGnd (Note 4)
-0.3V to 33V
SW to PGnd (Note 4)
-0.3V to 25V (DC), -4V to 25V (AC, 100ns)
Boot to SW
-0.3V to VCC + 0.3V (Note 2)
PGood, SS_Select to Gnd (Note 4)
-0.3V to VCC + 0.3V (Note 2)
Other Input/Output Pins to Gnd (Note 4)
-0.3V to +3.9V
PGnd to Gnd
-0.3V to +0.3V
THERMAL INFORMATION
Junction to Ambient Thermal Resistance ƟjA
32 °C/W (Note 3)
Junction to PCB Thermal Resistance Ɵj-PCB
2 °C/W
Storage Temperature Range
-55°C to 150°C
Junction Temperature Range
-40°C to 150°C
Note 1: Vcc must not exceed 7.5V for Junction Temperature between -10°C and -40°C
Note 2: Must not exceed 8V
Note 3: Based on IRDC3827 demo board - 2.6”x2.2”, 4-layer PCB board using 2 oz. copper on each layer.
Note 4: PGnd pin and Gnd pin are connected together.
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IR3827
ELECTRICAL SPECIFICATIONS
RECOMMENDED OPERATING CONDITIONS
SYMBOL
MIN
MAX
UNITS
Input Voltage Range with External Vcc Note 5, Note 7
PVin
1.0
21
Input Voltage Range with Internal LDO Note 6, Note 7
Vin, PVin
5.5
21
Supply Voltage Range (Note 6)
VCC
4.5
7.5
Supply Voltage Range (Note 6)
Boot to SW
4.5
7.5
Output Voltage Range
V0
0.6
0.86 x PVin
Output Current Range
I0
0
6
A
Switching Frequency
FS
300
1200
kHz
Operating Junction Temperature
TJ
-40
125
°C
V
Note 5: Vin is connected to Vcc to bypass the internal LDO.
Note 6: Vin is connected to PVin. For single-rail applications with PVin=Vin= 4.5V-5.5V, please refer to the application information in the
section of User Selectable Internal LDO and the section of Over Current Protection.
Note 7: Maximum SW node voltage should not exceed 25V.
ELECTRICAL CHARACTERISTICS
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Stage
PVin=Vin = 12V, Vo=1.2V,
Io = 6A, Fs=600kHz,L=1.0uH,
LDO_Select=Gnd. Note 8
Power Losses
Top Switch RDS(ON)
Bottom Switch RDS(ON)
Bootstrap Diode Forward
Voltage
PLOSS
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W
PVin=Vin =12V, Vo=1.2V,
Io=6A, Fs=600kHz, L=1.0uH,
LDO_Select=Float. Note 8
1.3
VBOOT -Vsw=5.1V,Io = 6A,
Tj = 25°C
21
29
VBOOT -Vsw=6.9V,Io = 6A,
Tj = 25°C
16
22
Vcc = 5.1V, Io = 6A, Tj = 25°C
21.4
30
Vcc = 6.9V, Io = 6A, Tj = 25°C
16.8
23
260
470
mV
VSW = 0V, Enable = 0V
1
µA
VSW = 0V, Enable = High,
VSEQ=0V
1
µA
RDS(on)-T
RDS(on)-B
VD
SW Leakage Current
Dead Band Time
1.1
TD
I(Boot) = 10mA
Note 8
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180
10
mΩ
ns
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
200
µA
Supply Current
Vin Supply Current (standby)
Vin Supply Current
(dynamic)
Iin(Standby)
EN = Low, No Switching
EN = High, Fs = 600kHz,
Vin = PVin = 21V,
LDO_Select=Gnd
Iin(Dyn)
10
13
mA
EN = High, Fs = 600kHz,
Vin = PVin = 21V,
LDO_Select=Float
8
11
5.1
5.4
VCC/LDO_Out
Vin(min) = 5.5V, Io = 0-30mA,
Cload =2.2uF,
LDO_Select=Float
Output Voltage
4.75
V
Vcc
Vin(min) = 7.3V, Io = 0-30mA,
Cload = 2.2uF,
LDO_Select=Gnd
LDO_Select Input bias
Current
6.5
LDO_Select=Gnd
6.9
7.2
30
60
Vin=6.5V,Io=30mA,
Cload=2.2uF,
LDO_Select=Gnd
LDO Dropout Voltage
0.7
Vcc_drop
V
Vin=4.7V,Io=25mA,
Cload=2.2uF,
LDO_Select=Float
Short Circuit Current
Ishort
uA
0.7
LDO_Select=Gnd
70
mA
1.0
V
Oscillator
Rt Voltage
Frequency Range
Ramp Amplitude
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VRt
Fs
Rt = 80.6kΩ
270
300
330
Rt = 39.2kΩ
540
600
660
Rt = 19.1kΩ
1080
1200
1320
Vin = 7.3V, Vin slew rate max
= 1V/µs, Note 8
1.095
Vin = 12V, Vin slew rate max
= 1V/µs, Note 8
1.80
Vin = 21V, Vin slew rate max
= 1V/µs, Note 8
3.15
Vin=Vcc=5V, For external Vcc
operation, Note 8
0.75
Vramp
kHz
Vp-p
© 2013 International Rectifier
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
Ramp Offset
CONDITIONS
MIN
Note 8
Minimum Pulse Width
Tmin(ctrl)
Maximum Duty Cycle
Dmax
Fixed Off Time
Toff
TYP
0.16
Note 8
Fs = 300kHz, Vin =PVin= 12V
MAX
V
60
86
Note 8
Fsync
270
Sync Pulse Duration
Tsync
100
High
3
ns
%
200
Sync Frequency Range
UNITS
250
ns
1320
kHz
200
ns
Sync Level Threshold
V
Low
0.6
Error Amplifier
Input Offset Voltage
VFB – VSEQ, VSEQ=0.3V
-3
+3
%
Input Bias Current (VFB)
IFB(E/A)
-1
+1
Input Bias Current (VSEQ)
ISEQ(E/A)
0
+4
Sink Current
Isink(E/A)
0.4
0.85
1.2
mA
Isource(E/A)
4
7.5
11
mA
µA
Source Current
Slew Rate
Gain-Bandwidth Product
DC Gain
SR
Note 8
7
12
20
V/µs
GBWP
Note 8
20
30
40
MHz
Gain
Note 8
100
110
120
dB
1.7
2.0
2.3
V
100
mV
1.2
V
Maximum Output Voltage
Vmax(E/A)
Minimum Output Voltage
Vmin(E/A)
Common Mode Input Voltage
0
Reference Voltage (VREF)
Feedback Voltage
LDO_Select= Gnd
0.6
LDO_Select= Float
0.6
VFB
V
0°C < Tj < 70°C
-0.6
+0.6
-40°C < Tj < 125°C ; Note 9
-1.2
+1.2
SS_Select=High
0.34
0.4
0.46
SS_Select=Float
0.17
0.2
0.23
SS_Select=Gnd
0.085
0.1
0.115
40
80
%
Accuracy
Soft Start
Soft Start Ramp Rate
SS_Select Input Bias Current
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LDO_Select=Gnd
SS_Select=Gnd
© 2013 International Rectifier
mV/µs
uA
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=Float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Good
Power Good Turn on
Threshold
VPG (on)
VFB rising
85
90
95
% VREF
Power Good Lower Turn off
Threshold
VPG(lower)
VFB falling
80
85
90
% VREF
Power Good Turn on Delay
TPG(ON)_D
VFB rising, see VPG(on)
Power Good Upper Turn off
Threshold
VPG(upper)
VFB rising
PGood Comparator Delay
PGood Voltage Low
VFB < VPG(lower) or
VFB > VPG(upper)
PG(voltage)
2.56
ms
115
120
125
% VREF
1
2
3.5
µs
0.5
V
IPGood = -5mA
Under-Voltage Lockout
Vcc-Start Threshold
VCC UVLO
Start
Vcc rising trip Level
3.9
4.1
4.3
V
Vcc-Stop Threshold
VCC UVLO
Stop
Vcc falling trip Level
3.6
3.8
4.0
V
Enable-Start-Threshold
Enable
UVLO Start
ramping up
1.14
1.2
1.26
V
Enable-Stop-Threshold
Enable
UVLO Stop
ramping down
0.95
1
1.05
Enable Leakage Current
IEN_LK
Enable = 3.3V
1
µA
Over-Voltage Protection
OVP Trip Threshold
OVP Comparator Delay
OVP_Vth
VFB rising
115
120
125
% VREF
1
2
3.5
µs
Tj = 25°C, LDO_Select=Float
6.2
7.3
8.5
Tj = 25°C, LDO_Select=Gnd
7.9
9.3
10.8
TOVP_D
Over-Current Protection
Current Limit
Hiccup Blanking Time
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A
ILIMIT
TBLK_Hiccup
SS_Select = Vcc, Note 8
10
SS_Select = Float, Note 8
20
SS_Select = Gnd, Note 8
40
© 2013 International Rectifier
ms
July 18, 2013
IR3827
ELECTRICAL CHARACTERISTICS (CONTINUED)
Unless otherwise specified, these specifications apply over, 5.5V < Vin = PVin < 21V, 0°C < TJ < 125°C, LDO_Select=Gnd,
SS_Select=float. Typical values are specified at Ta = 25°C.
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Upper Gate Driver
Source Resistance
VBOOT-VSW = 5.1V, Note 8
3
Sink Resistance
VBOOT-VSW = 5.1V, Note 8
4
Source Resistance
VCC = 5.1V, Note 8
2
Sink Resistance
VCC = 5.1V, Note 8
0.8
Thermal Shutdown Threshold
Note 8
145
Hysteresis
Note8
20
Ω
Lower Gate Driver
Ω
Over-Temperature Protection
°C
Note 8: Guaranteed by design, but not tested in production.
Note 9: Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
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IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, VCC= Internal LDO, LDO_Select = Float, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include the losses of IR3827, the inductor losses and the losses of the input and output
capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement.
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VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.82
SPM6550T-R82M (TDK)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
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IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, VCC= Internal LDO, LDO_Select = Gnd, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the
efficiency and power loss curves include the losses of IR3827, the inductor losses and the losses of the input and output
capacitors. The table below shows the inductors used for each of the output voltages in the efficiency measurement.
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VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.82
SPM6550T-R82M (TDK)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
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IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = 12V, VCC= External 5V, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and power
loss curves include the losses of IR3827, the inductor losses and the losses of the input and output capacitors. The table
below shows the inductors used for each of the output voltages in the efficiency measurement.
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VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.82
SPM6550T-R82M (TDK)
4.2
1.2
1.0
SPM6550T-1R0M (TDK)
4.7
1.8
1.0
SPM6550T-1R0M (TDK)
4.7
3.3
2.2
7443340220(Wurth Elektronik)
4.4
5
2.2
7443340220(Wurth Elektronik)
4.4
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July 18, 2013
IR3827
TYPICAL EFFICIENCY AND POWER LOSS CURVES
PVin = Vin = VCC = 5V, IO = 0A-6A, FS = 600 kHz, Room Temperature, No Air Flow. Note that the efficiency and power loss
curves include the losses of IR3827, the inductor losses and the losses of the input and output capacitors. The table below
shows the inductors used for each of the output voltages in the efficiency measurement.
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VOUT (V)
LOUT (µH)
P/N
DCR (mΩ)
1.0
0.68
PCMB065T- R68MS (Cyntec)
3.9
1.2
0.82
SPM6550T-R82M(TDK)
4.2
1.8
0.82
SPM6550T-R82M(TDK)
4.7
3.3
1.0
SPM6550T-1R0M(TDK)
4.7
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IR3827
RDS(ON) OF MOSFETS OVER TEMPERATURE AT VCC=6.9V
RDS(ON) OF MOSFETS OVER TEMPERATURE AT VCC=5.1V
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IR3827
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
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IR3827
TYPICAL OPERATING CHARACTERISTICS (-40°C TO +125°C)
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IR3827
THEORY OF OPERATION
DESCRIPTION
The IR3827 SupIRBuckTM is a 6A easy-to-use, fully
integrated and highly efficient synchronous Buck
regulator intended for Point-Of-Load (POL)
applications. It includes two IR HEXFETs with low
RDS(on). The bottom FET has an integrated
monolithic schottky diode in place of a conventional
body diode.
The IR3827 provides precisely regulated output
voltage programmed via two external resistors from
0.6V to 0.86×Vin. It uses voltage mode control
employing a proprietary PWM modulator with input
voltage feedforward. That provides excellent noise
immunity, easy loop compensation design, and good
line transient response.
The IR3827 has a user-selectable internal Low
Dropout (LDO) Regulator, allowing single supply
operation without resorting to an external bias
supply voltage. To further improve the efficiency, the
internal LDO can be bypassed. Instead an external
bias supply can be used. This feature allows the
input bus voltage range extended to 1.0V.
A RC network has to be connected between the FB
pin and the COMP pin to form a feedback
compensator. The goal of the compensator design
is to achieve a high control bandwidth with a phase
margin of 45° or above. The high control bandwidth
is beneficial for the loop dynamic response, which
helps to reduce the number of output capacitors,
PCB size and the cost. A phase margin of 45° or
higher is desired to ensure the system stability. For
most applications, a gain margin of -10dB or higher
is preferred to accommodate component variations
and to eliminate jittering/noise. The proprietary PWM
modulator in IR3827 significantly reduces the PWM
jittering, allowing the control bandwidth in the range
th
th
of 1/10 to 1/5 of the switching frequency.
Two types of compensators are commonly used:
Type II (PI) and Type III (PID), as shown in Figure 5.
The selection of the compensation type is
dependent on the ESR of the output capacitors.
Electrolytic capacitors have relatively higher ESR. If
the ESR pole is located at the frequency lower than
the cross-over frequency, FC, the ESR pole will help
to boost the phase margin. Thus a type II
compensator can be used. For the output capacitors
with lower ESR such as ceramic capacitors, type III
compensation is often desired.
The IR3827 features programmable switching
frequency from 300kHz to 1.2MHz, three selectable
soft-start time, and smooth synchronization to an
external clock. The other important functions include
thermally compensated over current protection,
output over voltage protection and thermal shutdown, etc.
CC2
Vout
CC1
RC1
Rf1
-
Fb
Rf2
E/A
Comp
+
VREF
VOLTAGE LOOP COMPESNATION DESIGN
The IR3827 uses PWM voltage mode control. The
output voltage of the POL, sensed by a resistor
divider, is fed into an internal Error Amplifier (E/A).
The output of the E/R is then compared to an
internal ramp voltage to determine the pulse width of
the gate signal for the control FET. The amplitude of
the ramp voltage is proportional to Vin so that the
bandwidth of the voltage loop remains almost
constant for different input voltages. This feature is
called input voltage feedfoward. It allows the
feedback loop design independent of the input
voltage. Please refer to the next section for more
information.
(a)
Vout
Rf3
CC2
Rf1
RC1
Fb
-
Rf2
+
CC1
Cf3
E/A
Comp
VREF
(b)
Figure 5 Loop Compensator (a) Type II, (b) Type III
18
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© 2013 International Rectifier
July 18, 2013
IR3827
Table 1 lists the compensation selection for different
types of output capacitors.
For more detailed design guideline of voltage loop
compensation, please refer to the application note
AN-1162, “Compensation Design Procedure for
Buck Converter with Voltage-Mode Error-Amplifier”.
SupBuck design tool is also available at www.irf.com
providing the reference design based on user’s
design requirements.
function can also minimize impact on output voltage
from fast Vin change. The maximum Vin slew rate is
within 1V/µs.
If an external bias voltage is used as Vcc, Vin pin
should be connected to Vcc/LDO_out pin instead of
PVin pin. Then the feedforward function is disabled.
The control loop compensation might need to be
adjusted.
16V
12V
TABLE 1 RECOMMENDED COMPENSATION TYPE
LOCATION OF
CROSS-OVER
FREQUENCY
TYPE OF
OUTPUT
CAPACITORS
Type II (PI)
FLC<FESR<F0<FS/2
Type III-A (PID)
FLC<F0<FESR<FS/2
Type III-B (PID)
FLC<F0<FS/2<FESR
Electrolytic,
POS-CAP, SPCAP
POS-CAP, SPCAP
Ceramic
COMPENSATOR
12V
7.3V
0
PWM Ramp
PWM Ramp
Amplitude = 1.8V
PWM Ramp Amplitude
= 2.4V
PWM Ramp Amplitude
= 1.095V
Ramp Offset
0
Figure 6 Timing Diagram for Input Feedforward
FLC is the resonant frequency of the output LC filter.
It is often referred to as double pole.
FLC
1
=
2 × π Lo × Co
FESR is the ESR zero of the output capacitor.
FESR =
1
2π × ESR × Co
F0 is the cross-over frequency of the closed voltage
loop and FS is the switching frequency.
INPUT VOLTAGE FEEDFORWARD
Input voltage feedforward is an important feature,
because it can keep the converter stable and
preserve its load transient performance when Vin
varies in a large range. In IR3827, feedforward
function is enabled when Vin pin is connected to PVin
pin and Vin>5.5V. In this case, the internal low
dropout (LDO) regulator is used. The PWM ramp
amplitude (Vramp) is proportionally changed with Vin
to maintain the ratio Vin/Vramp almost constant
throughout Vin variation range (as shown in Figure
6). Thus, the control loop bandwidth and phase
margin can be maintained constant. Feed-forward
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© 2013 International Rectifier
UNDER-VOLTAGE LOCKOUT AND POR
The Under-Voltage Lockout (UVLO) circuit monitors
the voltage of VCC/LDO_Output pin and the Enable
pin. It assures that the MOSFET driver outputs
remain off whenever either of these two signals is
below the set thresholds. Normal operation resumes
once both VCC/LDO_Output and En voltages rise
above their thresholds.
The POR (Power On Ready) signal is generated
when all these signals reach the valid logic level
(see system block diagram). When the POR is
asserted, the soft start sequence starts (see soft
start section).
ENABLE/EXTERNAL PVIN MONITOR
The IR3827 has an Enable function providing
another level of flexibility for start-up. The Enable pin
has a precise threshold which is internally monitored
by Under-Voltage Lockout (UVLO) circuit. If the
voltage at Enable pin is below its UVLO threshold,
both high-side and low-side FETs are off. When
Enable pin is below its UVLO, Over-Voltage
Protection (OVP) is disabled, and PGood stays low.
July 18, 2013
IR3827
The Enable pin should not be left floating. A pulldown resistor in the range of several kilo ohms is
recommended to connect between the Enable Pin
and Gnd.
In addition to logical inputs, the Enable pin can be
used to implement precise input voltage UVLO. As
shown in Figure 7, the input of the Enable pin is
derived from the PVin voltage by a set of resistive
divider, R1 and R2. By selecting different divider
ratios, users can program the UVLO threshold
voltage. The bus voltage UVLO is a very desirable
feature. It prevents the IR3827 from regulating at
PVin lower than the desired voltage level. Figure 8
shows the start-up waveform with the input UVLO
voltage set at 10V.
Vin
R1
IR3827
Enable
R2
Figure 7 Implementation of Input Under-Voltage
Lockout (UVLO) using Enable Pin
USER SELECTABLE INTERNAL LDO
The IR3827 has an internal Low Dropout Regulator
(LDO), offering two LDO voltage options – 5.1V and
6.9V. 5.1V VCC voltage results in higher light load
efficiency due to the lower gate charge loss, while
6.9 VCC voltage results in higher full load efficiency
due to less conduction loss. User can select the
desired VCC voltage based on the design target. The
selection of the LDO voltage is achieved with
LDO_Select pin, as shown in Table 2. It should be
noted that 6.9V VCC voltage results in faster
switching speed and may cause higher voltage spike
at the SW node than 5.1V VCC voltage.
TABLE 2 CONFIGURATION OF INTERNAL LDO
LDO_SELECT
VCC/LDO_OUT
Float
5.1V
Gnd
6.9V
The internal LDO is beneficial for single rail (supply)
applications, where no external bias supplies will be
needed. For these applications, Vin pin should be
connected to PVin and VCC/LDO_Out pin is left
floating as shown in Figure 9. 1.0μF and 2.2μF
ceramic bypass capacitors should be placed close to
Vin pin and VCC/LDO_Out pin respectively.
Input =5V-21V
1.0uF
PVin (12V)
10V
VCC/
LDO_OUT
2.2uF
Figure 8 Illustration of start-up with PVin UVLO
threshold voltage of 10V. The internal soft-start is
used in this case.
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PGnd
Enable
Intl_SS
Vout
20
PVin
IR3827
Vcc
Enable threshold
voltage1.2V
Vin
© 2013 International Rectifier
Figure 9 Internally Biased Single-Rail Configuration
When Vin drops below 5.5V (LDO_Select = Float), or
7.3V (LDO_Select = Gnd), the internal LDO enters
the dropout mode. Figure 10 shows the
VCC/LDO_Out voltage for Vin=PVin=5V with switching
frequency of 600kHz and 1200kHz respectively.
Alternatively, if the input bus voltage, PVin, is in the
range of 4.5V to 7.5V, VCC/LDO_Out pin can be
July 18, 2013
IR3827
Ext VCC
4.5V-7.5V
directly connected to the PVin pin to bypass the
internal LDO and therefore to avoid the voltage drop
on the internal LDO. This configuration is illustrated
in Figure 11.
Vin
PVin
IR3827
Figure 12 shows the configuration using an external
VCC voltage. With this configuration, the input voltage
range can be extended down to 1.0V. Please note
that the input feedforward function is disabled for
this configuration. The feedback compensation
needs to be adjusted accordingly.
It should be noted as the VCC voltage decreases, the
efficiency and the over current limit will decrease
due to the increase of RDS(ON). Please refer to the
section of the over current protection for more
information.
Input =1.0V-21V
VCC/
LDO_OUT
2.2uF
PGnd
Figure 12 Use External Bias Voltage
.
SOFT-START
The IR3827 has an internal digital soft-start circuit to
control the output voltage rise time, and to limit the
current surge at the start-up. To ensure correct startup, the soft-start sequence initiates when the Enable
and Vcc voltages rise above their UVLO thresholds
and generate the Power On Ready (POR) signal.
The slew rate of the internal soft-start can be
adjusted externally with SS_Select pin, as shown in
Table 3.
Table 3 User Selectable Soft-Start Time
Figure 10 LDO Dropout Voltage at Vin=PVin=5V
Input =4.5V-7.5V
1.0uF
Vin
PVin
IR3827
VCC/
LDO_OUT
2.2uF
SS_Select
Slew Rate
(mV/ µs)
Soft-Start Time
( ms )
Vcc
Float
Gnd
0.4
0.2
0.1
1.5
3
6
Figure 13 shows the waveforms during the soft start.
The corresponding soft-start time can be calculated
as follows.
Tss =
0.75V − 0.15V
SlewRate
PGnd
It should be noted that during the soft-start the overcurrent protection (OCP) and over-voltage protection
(OVP) is enabled to protect the device for any short
circuit or over voltage condition.
Figure 11 Single-Rail Configuration for 4.5V-7V inputs
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© 2013 International Rectifier
July 18, 2013
IR3827
POR
3.0V
1.5V
0.75V
be used. Table 4 summarizes the configurations to
achieve
simultaneous/ratiometric
sequencing
operations and normal start-up using the internal
soft-start. Figure 15 shows the typical waveforms for
sequencing operations.
Vin
0.15V
Intl_SS
SS_Select Vin
Vcc/
LDO_out
Vout
PGood
t1 t 2
t3
Vo1
(Master)
RE
RF
Figure 13 Theoretical start-up waveforms using
internal soft-start
POWER UP SEQUENCING
The IR3827 provides the simultaneous or ratiometric
sequencing function with Seq pin. As shown in the
block diagram, the Error-Amplifier (E/A) has three
positive inputs. The input with the lowest voltage is
used for regulating the output voltage and the other
two inputs are ignored. In practice, the voltage of the
other two inputs should be about 200mV greater
than the low-voltage input so that their effects can
completely be ignored. Seq pin is internally biased to
3.3V via a high impedance path. For normal
operation, Seq pin is left floating.
PGood
Seq
Enable
Rt/Sync
PVin
Boot
SW
IR3827
RC
Fb
Comp
RD
LDO_Select Gnd PGnd
Figure 14 Application circuit for Simultaneous and
Ratiometric sequencing operation
Table 4 Start-Up Configurations
Operating Mode
VSEQ
Configuration
Internal soft-start
Simultaneous
Sequencing
Ratiometric
Sequencing
Floating
Ramp up
from 0V
Ramp up
from 0V
―
RE/RF=RC/RD
RE/RF>RC/RD
Vcc
VREF=0.6V
In sequencing operation, the voltage at Seq pin,
VSEQ, should be kept to zero until the internal softstart is finished. Then VSEQ is ramped up and the
feedback voltage, VFB, follows VSEQ. When VSEQ is
above 0.6V, the Error-Amplifier switches to VREF and
VFB starts to follow VREF. The final VSEQ voltage after
sequencing startup should be between 0.7V ~ 3.3V.
Figure 14 shows the typical application circuit for
sequencing operation. VSEQ is derived from the
output of another voltage regulator (Master) through
a resistor divider composed of RE and RF. If the ratio
of this resistor divider is equal to that of the feedback
resistor divider i.e. RE/RF =RC/RD, simultaneous
start-up is achieved. That is, the output voltage of
the slave follows that of the master until the voltage
at the Seq pin of the slave reaches 0.6 V. After VSEQ
of the slave exceeds 0.6V, the internal 0.6V
reference voltage of the slave dictates its output. To
achieve ratiometric operation, RE/RF >RC/RD should
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© 2013 International Rectifier
Enable (slave)
1.2V
Soft Start (slave)
Vo1 (master)
(a)
Vo2 (slave)
Vo1 (master)
(b)
Vo2 (slave)
Figure 15 Typical waveforms for sequencing
operation: (a) Simultaneous; (b) Ratiometric
PRE-BIAS START-UP
IR3827 is able to start up into a pre-charged output
smoothly,
which
prevents
oscillations
and
disturbances of the output voltage.
July 18, 2013
IR3827
The output starts in an asynchronous fashion and
keeps the synchronous MOSFET (Sync FET) off
until the first gate signal for control MOSFET (Ctrl
FET) is generated. Figure 16 shows a typical PreBias condition at start up. The gate signal of the
control FET is determined by the loop compensator.
The sync FET always starts with a narrow pulse
width (12.5% of a switching period) and gradually
increases its duty cycle with a step of 12.5% until it
reaches the steady state value. The number of these
startup pulses for each step is 16 and it’s internally
programmed. Figure 17 shows the series of 16x8
startup pulses.
It should be noted that PGood is not active until the
first gate signal for control FET is generated. Please
refer to Power Good Section for more information.
Vo
Pre-Bias Voltage
Figure 16 Pre-Bias start-up
...
12.5%
...
25%
...
LDRv
...
...
16
...
87.5%
...
...
16
...
...
End of
PB
Figure 17 Pre-Bias startup pulses
SHUTDOWN
IR3827 can be shut down by pulling the Enable pin
below its 1.0V threshold. Both the high side and the
low side drivers are pulled low.
OPERATING FREQUENCY
The switching frequency can be programmed
between 300kHz – 1200kHz by connecting an
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Fs = 19954 × Rt
−0.953
Where FS is in kHz, and Rt is in kΩ.
Table 5 shows the different oscillator frequency and
its corresponding Rt for easy reference.
Table 5 Switching Frequency vs. Rt
Rt (kΩ)
FS (kHz)
80.6
60.4
48.7
39.2
34
29.4
26.1
23.2
21
19.1
300
400
500
600
700
800
900
1000
1100
1200
OVER CURRENT PROTECTION
t
HDRv
external resistor from Rt pin to Gnd. Rt can be
calculated as follows.
© 2013 International Rectifier
The over current (OC) protection is performed by
sensing current through the RDS(on) of the
Synchronous MOSFET. This method enhances the
converter’s efficiency, reduces cost by eliminating a
current sense resistor and any layout related noise
issues. The current limit is pre-set internally and is
compensated according to the IC temperature. So at
different ambient temperature, the over-current trip
threshold remains almost constant.
Detailed operation of OCP is explained as follows.
Over Current Protection circuit senses the inductor
current flowing through the Synchronous MOSFET
closer to the valley point. OCP circuit samples this
current for 40nsec typically after the rising edge of
the PWM set pulse which has a width of 12.5% of
the switching period. The PWM pulse starts at the
falling edge of the PWM set pulse. This makes valley
current sense more robust as current is sensed
close to the bottom of the inductor downward slope
where transient and switching noise are lower and
helps to prevent false tripping due to noise and
transient. An OC condition is detected if the load
current exceeds the threshold, the converter enters
into hiccup mode. PGood will go low and the internal
July 18, 2013
IR3827
soft start signal will be pulled low. The converter
goes into hiccup mode with some hiccup blanking
time as shown in Figure 18. The convertor stays in
this mode until the over load or short circuit is
removed. With different SS_Select configurations,
the hiccup blanking time is different. Please refer to
the electrical table for details. The actual DC output
current limit point will be greater than the valley point
by an amount equal to approximately half of peak to
peak inductor ripple current.
I OCP = I LIMIT +
∆i
2
IOCP= DC current limit hiccup point
ILIMIT= Over current limit (Valley of Inductor Current)
Δi= Peak-to-peak inductor ripple current
Over Current Limit
Hiccup Blanking Time
IL
0
HDrv
...
0
LDrv
...
0
PGood
0
Figure 18 Timing Diagram for Hiccup Over Current
Protection
Over current limit is affected by the VCC voltage. For
some single rail operations where Vin is 5V or less,
the OCP limit will de-rated due to the drop of VCC
voltage. Figure 19 and Figure 20 show the over
current limit for two single rail applications with
Vin=PVin=5V and Vin=PVin=VCC=4.5V respectively.
Figure 20 OCP Limit at Vin=PVin=VCC=4.5V
OVER-VOLTAGE PROTECTION (OVP)
Over-voltage protection in IR3827 is achieved by
comparing FB pin voltage to a pre-set threshold.
OVP threshold is set at 1.2×Vref. When FB pin
voltage exceeds the over voltage threshold, an over
voltage trip signal asserts after 2us (typ.) delay.
Then the high side drive signal HDrv is turned off
immediately, PGood flags low. The sync FET
remains on to discharge the output capacitor. When
the VFB voltage drops below the threshold, the sync
FET turns off to prevent the complete depletion of
the output capacitor. After that, HDrv remains off
until a reset is performed by cycling either Vcc or
Enable. Figure 21 shows the timing diagram for over
voltage protection. Please note that OVP
comparator becomes active only when the IR3827 is
enabled.
POWER GOOD OUTPUT
IR3827 continually monitors the output voltage via
FB voltage. The FB voltage is an input to the window
comparator with upper and lower threshold of 120%
and 85% of the reference voltage respectively.
PGood signal is high whenever FB voltage is within
the PGood comparator window thresholds. For prebiased start-up, PGood is not active until the first
gate signal of the control FET is generated.
The PGood pin is open drain and it needs to be
externally pulled high. High state indicates that
output is in regulation.
Figure 19 OCP Limit at Vin=PVin=5V using Internal LDO
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© 2013 International Rectifier
In addition, PGood is also gated by other faults
including over current and over temperature. When
July 18, 2013
IR3827
either of the faults occurs, PGood pin will be pulled
low.
1.2*Vref
FB
0.6V
0
HDrv
0
LDrv
0
running frequency, a transition from the free-running
frequency to the external clock frequency will
happen. This transition is to gradually make the
actual switching frequency equal to the external
clock frequency, no matter which one is higher. On
the contrary, when the external clock signal is
removed from Rt/Sync pin, the switching frequency
is also changed to free-running gradually. In order to
minimize the impact from these transitions to output
voltage, a diode is recommended to add between
the external clock and Rt/Sync pin, as shown in
Figure 22. Figure 23 shows the timing diagram of
these transitions.
PGood
0
Figure 21 Timing Diagram for Over Voltage Protection
THERMAL SHUTDOWN
Temperature sensing is provided inside IR3827. The
trip threshold is typically set to 145ºC. When trip
threshold is exceeded, thermal shutdown turns off
both MOSFETs and resets the internal soft start.
An internal compensation circuit is used to change
the PWM ramp slope according to the clock
frequency applied on Rt/Sync pin. Thus, the
effective amplitude of the PWM ramp (Vramp), which
is used in compensation loop calculation, has minor
impact from the variation of the external
synchronization signal.
IR3827
Automatic restart is initiated when the sensed
temperature drops within the operating range. There
is a 20°C hysteresis in the thermal shutdown
threshold.
Rt/Sync
Gnd
EXTERNAL SYNCHRONIZATION
IR3827 incorporates an internal phase lock loop
(PLL) circuit which enables synchronization of the
internal oscillator to an external clock. This function
is important to avoid sub-harmonic oscillations due
to beat frequency for embedded systems when
multiple point-of-load (POL) regulators are used. A
multi-function pin, Rt/Sync, is used to connect the
external clock. If the external clock is present before
the converter turns on, Rt/Sync pin can be
connected to the external clock signal solely and no
other resistor is needed. If the external clock is
applied after the converter turns on, or the converter
switching frequency needs to toggle between the
external clock frequency and the internal freerunning frequency, an external resistor from Rt/Sync
pin to Gnd is required to set the free-running
frequency.
Figure 22 Configuration of External Synchronization
Synchronize to the
external clock
Free Running
Frequency
Return to freerunning freq
...
SW
Gradually change
Gradually change
...
Fs1
SYNC
Fs1
Fs2
Figure 23 Timing Diagram for Synchronization
to the External Clock (Fs1<Fs2 or Fs1>Fs2)
When an external clock is applied to Rt/Sync pin
after the converter runs in steady state with its free25
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© 2013 International Rectifier
July 18, 2013
IR3827
MINIMUM ON TIME CONSIDERATIONS
The minimum ON time is the shortest amount of time
for which Ctrl FET may be reliably turned on, and
this depends on the internal timing delays. For
IR3827, the worst case minimum on-time is specified
as 60 ns.
range this ratio increases, thus the lower the
maximum duty ratio at which IR3827 can operate.
Figure 24 shows a plot of the maximum duty ratio vs.
the switching frequency.
Any design or application using IR3827 must ensure
operation with a pulse width that is higher than this
minimum on-time and preferably higher than 60ns.
This is necessary for the circuit to operate without
jitter and pulse-skipping, which can cause high
inductor current ripple and high output voltage ripple.
t on =
Vout
D
=
Fs Vin × Fs
Figure 24 Maximum duty cycle vs. switching
frequency.
In any application that uses IR3827, the following
condition must be satisfied:
t on (min) ≤ t on
t on (min) ≤
Vout
Vout
, therefore, Vin × Fs ≤
t on (min)
Vin × Fs
The minimum output voltage is limited by the
reference voltage and hence Vout(min) = 0.6 V.
Therefore,
Vin × Fs ≤
Vout (min)
ton (min)
=
0.6V
= 10V / µs
60ns
Therefore, at the maximum recommended input
voltage 21V and minimum output voltage, the
converter should be designed at a switching
frequency that does not exceed 476 kHz.
Conversely, for operation at the maximum
recommended operating frequency (1.32 MHz) and
minimum output voltage (0.6V). The input voltage
(PVin) should not exceed 7.57V, otherwise pulse
skipping will happen.
MAXIMUM DUTY RATIO
A certain off-time is specified for IR3827. This
provides an upper limit on the operating duty ratio at
any given switching frequency. The off-time remains
at a relatively fixed ratio to switching period in low
and mid frequency range, while in high frequency
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© 2013 International Rectifier
July 18, 2013
IR3827
DESIGN EXAMPLE
Vo = VREF × (1 +
The following example is a typical application for
IR3827. The application circuit is shown in Figure 28.
PVin = Vin = 12V (±10%)
RF 1
)
RF 2
RF1 and RF2 are the feedback resistor divider, as
shown in Figure 25. For the selection of RF1 and RF2,
please see feedback compensation section.
Vo = 1.2V
Vout
Io = 6A
Peak-to-Peak Ripple Voltage = ±1% of Vo
ΔVo = ± 4% of Vo (for 30% Load Transient)
IR3827
Rf1
FB
Rf2
Fs = 600 kHz
EXTERNAL PVIN MONITOR (INPUT UVLO)
As explained in the section of Enable/External PVin
monitor, the input voltage, PVin, can be monitored by
connecting the Enable pin to PVin through a set of
resistor divider. When PVin exceeds the desired
voltage level such that the voltage at the Enable pin
exceeds the Enable threshold, 1.2V, the IR3827 is
turned on. The implementation of this function is
shown in Figure 7.
For a typical Enable threshold of VEN = 1.2 V
PVin (min) ×
R2
= VEN = 1.2
R1 + R2
R2 = R1 ×
VEN
PVin (min) − VEN
For the minimum input voltage PVin (min) = 9.2V,
select R1=49.9kΩ, and R2=7.5kΩ.
SWITCHING FREQUENCY
For FS = 600 kHz, select Rt = 39.2 KΩ, from Table 5.
Figure 25 The output voltage is programmed through
a set of feedback resistor divider
BOOTSTRAP CAPACITOR SELECTION
To drive the Control FET, it is necessary to supply a
gate voltage at least 4V greater than the voltage at
the SW pin, which is connected to the source of the
Control FET. This is achieved by using a bootstrap
configuration, which comprises the internal bootstrap
diode and an external bootstrap capacitor, C1, as
shown in Figure 26. The operation of the circuit is as
follows: When the sync FET is turned on, the
capacitor node connected to SW is pulled low. VCC
starts to charge C1 through the internal bootstrap
didoe. The voltage, Vc, across the bootstrap
capacitor C1 can be calculated as
VC = VCC − VD
where VD is the forward voltage drop of the
bootstrap diode.
When the control FET turns on in the next cycle, the
SW node voltage rises to the bus voltage, PVin. The
voltage at the Boot pin becomes:
OUTPUT VOLTAGE SETTING
Output voltage is set by the reference voltage and
the external voltage divider connected to the FB pin.
The FB pin is the inverting input of the error
amplifier, which is internally referenced to 0.6V. The
divider ratio is set to provide 0.6V at the FB pin
when the output is at its desired value. The output
voltage is defined by using the following equation:
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© 2013 International Rectifier
VBOOT = PVin + VCC − VD
A good quality ceramic capacitor of 0.1μF with
voltage rating of at least 25V is recommended for
most applications.
July 18, 2013
IR3827
Cvin
+ VD -
INDUCTOR SELECTION
VIN
Boot
Vcc
C1
SW
+
Vc
L
PGnd
Figure 26 Bootstrap circuit to generate the supply
voltage for the high-side driver voltage
INPUT CAPACITOR SELECTION
Good quality input capacitors are necessary to
minimize the input ripple voltage and to supply the
switch current during the on-time. The input
capacitors should be selected based on the RMS
value of the input ripple current and requirement of
the input ripple voltage.
The RMS value of the input ripple current can be
calculated as follows:
I RMS = I o × D × (1 − D)
The inductor is selected based on output power,
operating frequency and efficiency requirements. A
low inductor value causes large ripple current,
resulting in the smaller size, faster response to a
load transient but poor efficiency and high output
noise. Generally, the selection of the inductor value
can be reduced to the desired maximum ripple
current in the inductor (Δi). The optimum point is
usually found between 20% and 50% ripple of the
output current.
The saturation current of the inductor is desired to
be higher than the over current limit plus the inductor
ripple current. An inductor with soft-saturation
characteristic is recommended.
For the buck converter, the inductor value for the
desired operating ripple current can be determined
using the following relation:
PVin max − Vo = L ×
D
∆iL max
; ∆t =
Fs
∆t
L = ( PVin max − Vo ) ×
Vo
Vin × ∆iL max × Fs
The input voltage ripple is the result of the charging
of the input capacitors and the voltage induced by
ESR and ESL of the input capacitors.
Where:
PVinmax = Maximum input voltage
V0 = Output Voltage
ΔiLmax = Maximum Inductor Peak-to-Peak Ripple
Current
Fs = Switching Frequency
Δt = On time
D = Duty Cycle
Ceramic capacitors are recommended due to their
high ripple current capabilities. They also feature low
ESR and ESL at higher frequency which enables
better efficiency.
Select ΔiLmax ≈ 30%×Io, then the output inductor is
calculated to be 1.0μH. Select L=1.0μH, SPM6550T1R0M, from TDK which provides a compact, low
profile inductor suitable for this application.
For this application, it is suggested to use three
10μF/25V ceramic capacitors, C3216X5R1E106M,
from TDK. In addition, although not mandatory, a
1x330uF, 25V SMD capacitor EEV-FK1E331P from
Panasonic may also be used as a bulk capacitor and
is recommended if the input power supply is not
located close to the converter.
OUTPUT CAPACITOR SELECTION
Where D is the duty cycle and Io is the output
current. For Io=6A and D=0.1, IRMS= 1.8A
28
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© 2013 International Rectifier
Output capacitors are usually selected to meet two
specific requirements: (1) Output ripple voltage and
(2) load transient response. The load transient
response is also greatly affected by the control
bandwidth. So it is common practice to select the
output capacitors to meet the requirements of the
July 18, 2013
IR3827
output ripple voltage first, and then design the
control bandwidth to meet the transient load
response. For some cases, even with the highest
allowable control bandwidth, the resulting load
transient response still cannot meet the requirement.
The number of output capacitors then need to be
increased.
FLC =
The voltage ripple is attributed by the ripple current
charging the output capacitors, and the voltage drop
due to the Equivalent Series Resistance (ESR) and
the Equivalent Series Inductance (ESL. Following
lists the respective peak-to-peak ripple voltages:
The equivalent ESR zero of the output capacitors,
FESR, is.
∆Vo ( C ) =
∆iL max
8 × Co × Fs
∆Vo ( ESR ) = ∆iL max × ESR
∆Vo ( ESL ) = (
PVin − Vo
) × ESL
L
Where ΔiLmax is maximum inductor peak-to-peak
ripple current.
Good quality ceramic capacitors are recommended
due to their low ESR, ESL and the small package
size. It should be noted that the capacitance of
ceramic capacitors are usually de-rated with the DC
and AC biased voltage. It is important to use the derated capacitance value for the calculation of output
ripple voltage as well as the voltage loop
compensation design. The de-rated capacitance
value may be obtained from the manufacturer’s
datasheets.
1
2 × π Lo × Co
1
=
2 × π 1.0 × 10 −6 × 3 × 18 × 10 −6
= 21.6kHz
1
ESR
× 3 × Co
2π ×
3
1
=
−3
2π × 3 × 10 × 18 × 10 −6
= 2.95 × 103 kHz
FESR =
Select crossover frequency F0=100kHz
According to Table 1, Type III B compensation is
selected for FLC<F0<FS/2<FESR. Type III compensator
is shown below for easy reference.
Vout
Rf3
CC2
Rf1
RC1
Fb
-
Rf2
+
CC1
Cf3
E/A
Comp
VREF
In this case, three 22uF ceramic capacitors,
C2012X5R0J226M, from TDK are used to achieve
±12mV peak-to-peak ripple voltage requirement. The
de-rated capacitance value with 1.2VDC bias and
10mVAC voltage is around 18uF each.
Gain
(dB)
|H(s)|
FEEDBACK COMPENSATION
For this design, the resonant frequency of the output
LC filter, FLC, is
FZ1
FZ2
FP2
FP3
Figure 27 Type III compensation and its asymptotic
gain plot
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© 2013 International Rectifier
July 18, 2013
IR3827
FZ 1 =
1
2π × RC1 × CC1
FZ 2 =
1
2π × C F 3 × ( RF 3 + RF 1 )
FP 2 = F0
FP1 = 0
FP 2 =
FP 3
1 + sin θ
1 + sin 70
= 100 ×10 3
= 568kHz
1 − sin θ
1 − sin 70
FZ1 is selected to provide extra phase boost.
FZ 1 = FZ 2 / 2 = 8.8kHz
FP3 is set at one half of the switching frequency to
damp the switching noise.
1
FP 3 = FS / 2 = 300kHz
2π × RF 3 × C F 3
The selected compensation parameters are:
RF1=3.32kΩ, RF2=3.32kΩ, RF3=100Ω, CF3=2200pF,
RC1=2kΩ, CC1=10nF, CC2=180pF.
1
=
2π × RC1 × CC 2
FZ2 and FP2 are selected to achieve phase boost
Ɵ=70º.
FZ 2 = F0
30
1 − sin 70
1 − sin θ
= 17.6kHz
= 100 × 10 3
1 + sin 70
1 + sin θ
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© 2013 International Rectifier
July 18, 2013
IR3827
APPLICATION DIAGRAM
12V
R18
49.9k
C7
0.1uF
C32
1.0uF
Cin
3x10uF
R19
7.5k
Enable
PGood
Vin
PGood
R17
49.9k
Vcc/LDO_out
C23
2.2uF
Seq
R9
39.2k
PVin
Boot
C24
0.1uF 1.0uH
L1
SW
IR3827
Fb
SS_Select
Rt/Sync
Comp
LDO_Select Gnd PGnd
R1
C26
2.0k
10nF
1.2V
R2
3.32k
C8
2200pF
R4
100Ω
Cout
3x22uF
C14
0.1uF
R3
3.32k
C11 180pF
Figure 28 Single Rail 6A POL Application Circuit: PVin=Vin=12V, Vo=1.2V, Io=6A, fsw=600kHz
SUGGESTED BILL OF MATERIALS
QTY
PART
REFERENCE
VALUE
DESCRIPTION
MANUFACTURER
PART NUMBER
3
3
1
1
3
1
1
1
1
1
2
1
1
2
Cin
C7 C14 C24
C8
C11
Cout
C23
C26
C32
L1
R1
R2,R3
R4
R9
R17 R18
10uF
0.1uF
2200pF
180pF
22uF
2.2uF
10nF
1.0uF
1.0uH
2K
3.32K
100
39.2K
49.9K
1206, 25V, X5R, 20%
0603, 25V, X7R, 10%
0603,50V,X7R
0603, 50V, NP0, 5%
0805, 6.3V, X5R, 20%
0603, 16V, X5R, 20%
0603, 25V, X7R, 10%
0603, 25V, X5R, 10%
SMD 7.1x6.5x5mm,4.7mΩ
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
Thick Film, 0603,1/10W,1%
TDK
Murata
Murata
Murata
TDK
TDK
Murata
Murata
TDK
Panasonic
Panasonic
Panasonic
Panasonic
Panasonic
C3216X5R1E106M
GRM188R71E104KA01B
GRM188R71H222KA01B
GRM1885C1H181JA01D
C2012X5R0J226M
C1608X5R1C225M
GRM188R71E103KA01J
GRM188R61E105KA12D
SPM6550T-1R0
ERJ-3EKF2001V
ERJ-3EKF3321V
ERJ-3EKF1000V
ERJ-3EKF3922V
ERJ-3EKF4992V
1
R19
7.5K
Thick Film, 0603,1/10W,1%
Panasonic
ERJ-3EKF7501V
1
U1
IR3827
PQFN 4x5mm
IR
IR3827MPBF
31
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© 2012 International Rectifier
July 18, 2013
IR3827
APPLICATION DIAGRAM
12V
R18
49.9k
C7
0.1uF
C32
1.0uF
Cin
3x10uF
R19
7.5k
Vin
Enable
PGood
PGood
PVin
Boot
R17
49.9k
Ext Vcc=5V
IR3827
Seq
R9
39.2k
L1
SW
Vcc/LDO_out
C23
2.2uF
C24
0.1uF 1.0uH
Fb
SS_Select
Rt/Sync
Comp
R1
C26
806Ω
22nF
LDO_Select Gnd PGnd
1.2V
R2
3.32k
C8
2200pF
R4
100Ω
Cout
3x22uF
C14
0.1uF
R3
3.32k
C11 180pF
Figure 29 6A POL Application Circuit with external 5V VCC: PVin=Vin=12V, Vo=1.2V, Io=6A, fsw=600kHz. Please note that
loop compensation is adjusted to consider the absence of the input voltage feedforward.
5V
C7
0.1uF
Enable
C32
1.0uF
PGood
Enable
Vin
PGood
PVin
Boot
R17
49.9k
Seq
R9
39.2k
SS_Select
Rt/Sync
C24
0.1uF 0.68uH
L1
SW
Vcc/LDO_out
C23
2.2uF
Cin
4x10uF
IR3827
Fb
Comp
LDO_Select Gnd PGnd
R1
C26
2k
4.7nF
1V
R2
3.32k
C8
2200pF
R4
100Ω
Cout
4x22uF
C14
0.1uF
R3
4.99k
C11 100pF
Figure 30 Single Rail 6A POL Application Circuit: PVin=Vin=5V, Vo=1.0V, Io=6A, fsw=600kHz
32
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© 2012 International Rectifier
July 18, 2013
IR3827
TYPICAL OPERATING WAVEFORMS
Vin = 12V, V0 = 1.2V, I0 = 0-6A, Unless otherwise Specified, LDO_Select = Float. Room Temperature, No Air Flow
Figure 31 Start up at 6A Load with SS_Select pin
floating. Ch1:Vin, Ch2:Enable, Ch3:Vo ,Ch4: PGood
Figure 33 Start up with 1.06V Pre Bias, 0A Load
Ch3: Vo, Ch4: PGood
Figure 35 Inductor node at 6A load,
LDO_Select = Float Ch3:LX
33
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© 2013 International Rectifier
Figure 32 Start up at 6A Load with SS_Select pin
floating. Ch1:Vin, Ch2:Enable, Ch3:Vo ,Ch4:Vcc
Figure 34 Output Voltage Ripple, 6A load Ch2: Vout
Figure 36 Short circuit (Hiccup) Recovery,
SS_Select = Float, Ch3:Vout , Ch4:Iout
July 18, 2013
IR3827
TYPICAL OPERATING WAVEFORMS
Vin = 12V, V0 = 1.2V, I0 = 0-6A, Unless otherwise Specified, LDO_Select = Float. Room Temperature, No Air Flow
Figure 37 Transient Response, 4.2A to 6A
Step load Ch2:Vout Ch4-Iout
Figure 38 Feed Forward for Vin change
from 6.8 to 15V and back to 6.8V. Ch2-Vout, Ch4-Vin
Figure 39 Bode Plot at 6A load, bandwidth = 105 kHz, and phase margin = 53 degrees and gain margin = -12dB
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© 2013 International Rectifier
July 18, 2013
IR3827
TYPICAL OPERATING WAVEFORMS
Vin = 12V, V0 = 1.2V, I0 = 0-6A, Unless otherwise Specified, LDO_Select = Float. Room Temperature, No Air Flow
Figure 40 Efficiency vs. Load Current, LDO_Select = Gnd and Float
Figure 41 Power Loss vs. Load Current, LDO_Select = Gnd and Float
35
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© 2013 International Rectifier
July 18, 2013
IR3827
TYPICAL OPERATING WAVEFORMS
Vin = 12V, V0 = 1.2V, I0 = 0-6A, Unless otherwise Specified, LDO_Select = Float. Room Temperature, No Air Flow
Figure 42 Thermal Image of the board at 6A load, LDO_Select= Float (VCC=5.1V)
IR3827=70°C, Inductor=40°C
Figure 43 Thermal Image of the board at 6A load, LDO_Select= GND (VCC=6.9V)
IR3827=60°C, Inductor=38°C
36
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© 2013 International Rectifier
July 18, 2013
IR3827
LAYOUT RECOMMENDATIONS
The layout is very important when designing high
frequency switching converters. Layout will affect
noise pickup and can cause a good design to
perform with worse than expected results.
Make the connections for the power components in
the top layer with wide, copper filled areas or
polygons. In general, it is desirable to make proper
use of power planes and polygons for power
distribution and heat dissipation.
The inductor, output capacitors and the IR3827
should be as close to each other as possible. This
helps to reduce the EMI radiated by the power
traces due to the high switching currents through
them. Place the input capacitor directly at the PVin
pin of IR3827.
The feedback part of the system should be kept
away from the inductor and other noise sources.
pins. It is important to place the feedback
components including feedback resistors and
compensation components close to Fb and Comp
pins.
In a multilayer PCB use one layer as a power
ground plane and have a control circuit ground
(analog ground), to which all signals are referenced.
The goal is to localize the high current path to a
separate loop that does not interfere with the more
sensitive analog control function. These two grounds
must be connected together on the PC board layout
at a single point. It is recommended to place all
the compensation parts over the analog ground
plane in top layer.
The Power QFN is a thermally enhanced package.
Based on thermal performance it is recommended to
use at least a 4-layers PCB. To effectively remove
heat from the device the exposed pad should be
connected to the ground plane using via holes.
Figure 44-Figure 47 illustrates the implementation of
the layout guidelines outlined above, on the
IRDC3827 4-layer demo board.
The critical bypass components such as capacitors
for Vin and VCC should be close to their respective
PGnd
Vout
PVin
Compensation parts
should be placed
as close as possible
to the Comp pin
Resistor Rt should be
placed as close as
possible to their pins
Enough copper &
minimum ground length
path between Input and
Output
SW node copper is
kept only at the top
layer to minimize
the switching noise
AGnd
All bypass caps
should be placed
as close as possible
to their connecting pins
Figure 44 IRDC3827 Demo Board – Top Layer
37
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© 2013 International Rectifier
July 18, 2013
IR3827
PVin
PGnd
Vout
Single point connection
between AGND & PGND,
should be close to the
SupIRBuck kept away from
noise sources
Figure 45 IRDC3827 Demo Board – Bottom Layer
PGnd
Feedback and Vsns trace
routing should be kept
away from noise sources
AGnd
Figure 46 IRDC3827 Demo Board – Middle Layer 1
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© 2013 International Rectifier
July 18, 2013
IR3827
PGnd
Figure 47 IRDC3827 Demo Board – Middle Layer 2
39
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© 2013 International Rectifier
July 18, 2013
IR3827
PCB METAL AND COMPONENT
PLACEMENT
dependent on solders and processes, and
experiments should be run to confirm the limits of
self-centering on specific processes.
Evaluations have shown that the best overall
performance is achieved using the substrate/PCB
layout as shown in following figures. PQFN devices
should be placed to an accuracy of 0.050mm on
both X and Y axes. Self-centering behavior is highly
For further information, please refer to “SupIRBuck™
Multi-Chip Module (MCM) Power Quad Flat No-Lead
(PQFN) Board Mounting Application Note.”
(AN1132)
Figure 48 PCB Metal Pad Spacing (all dimensions in mm)
* Contact International Rectifier to receive an electronic PCB Library file in your preferred format
40
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© 2013 International Rectifier
July 18, 2013
IR3827
SOLDER RESIST
IR recommends that the larger Power or Land Area
pads are Solder Mask Defined (SMD.) This allows
the underlying Copper traces to be as large as
possible, which helps in terms of current carrying
capability and device cooling capability.
When using SMD pads, the underlying copper
traces should be at least 0.05mm larger (on each
edge) than the Solder Mask window, in order to
accommodate any layer to layer misalignment. (i.e.
0.1mm in X & Y.)
are Non Solder Mask Defined (NSMD) or Copper
Defined.
When using NSMD pads, the Solder Resist Window
should be larger than the Copper Pad by at least
0.025mm on each edge, (i.e. 0.05mm in X&Y,) in
order to accommodate any layer to layer
misalignment.
Ensure that the solder resist in-between the smaller
signal lead areas are at least 0.15mm wide, due to
the high x/y aspect ratio of the solder mask strip.
However, for the smaller Signal type leads around
the edge of the device, IR recommends that these
Figure 49 Solder Resist
41
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© 2013 International Rectifier
July 18, 2013
IR3827
STENCIL DESIGN
Stencils for PQFN can be used with thicknesses of
0.100-0.250mm (0.004-0.010"). Stencils thinner than
0.100mm are unsuitable because they deposit
insufficient solder paste to make good solder joints
with the ground pad; high reductions sometimes
create similar problems. Stencils in the range of
0.125mm-0.200mm (0.005-0.008"), with suitable
reductions, give the best results.
Evaluations have shown that the best overall
performance is achieved using the stencil design
shown in following figure. This design is for a stencil
thickness of 0.127mm (0.005"). The reduction
should
be
adjusted
for
stencils
of other thicknesses.
Figure 50 Stencil Pad Spacing (all dimensions in mm)
42
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© 2013 International Rectifier
July 18, 2013
IR3827
MARKING INFORMATION
PACKAGE INFORMATION
43
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© 2013 International Rectifier
July 18, 2013
IR3827
ENVIRONMENTAL QUALIFICATIONS
Industrial
Qualification Level
Moisture Sensitivity Level
4mm x 5mm PQFN
Machine Model
(JESD22-A115A)
ESD
Human Body Model
(JESD22-A114F)
Charged Device Model
(JESD22-C101D)
JEDEC Level 2 @ 260°C
Class B
≥200V to <400V
Class 2
≥2000V to <4000V
Class III
≥500V to ≤1000V
RoHS6 Compliant
Yes
† Qualification standards can be found at International Rectifier web site: http://www.irf.com
†† Exceptions to AEC-Q101 requirements are noted in the qualification report.
Data and specifications subject to change without notice.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information.
www.irf.com
44
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July 18, 2013
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