TI DAC104S085CISDX/NOPB 10-bit micro power quad digital-to-analog converter with rail-to-rail output Datasheet

DAC104S085
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SNAS362E – MAY 2006 – REVISED OCTOBER 2012
DAC104S085/DAC104S085-Q1 10-Bit Micro Power QUAD Digital-to-Analog Converter with
Rail-to-Rail Output
Check for Samples: DAC104S085
FEATURES
1
•
•
•
•
•
•
•
2
Guaranteed Monotonicity
Low Power Operation
Rail-to-Rail Voltage Output
Power-on Reset to 0V
Simultaneous Output Updating
Wide power supply range (+2.7V to +5.5V)
Industry's Smallest Package
•
•
Power Down Modes
AEC-Q100 Grade 1 Qualified
APPLICATIONS
•
•
•
•
•
Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage & Current Sources
Programmable Attenuators
Automotive
DESCRIPTION
The DAC104S085 is a full-featured, general purpose QUAD 10-bit voltage-output digital-to-analog converter
(DAC) that can operate from a single +2.7V to 5.5V supply and consumes 1.1 mW at 3V and 2.5 mW at 5V. The
DAC104S085 is packaged in 10-lead SON and VSSOP packages. The 10-lead SON package makes the
DAC104S085 the smallest QUAD DAC in its class. The on-chip output amplifier allows rail-to-rail output swing
and the three wire serial interface operates at clock rates up to 40 MHz over the entire supply voltage range.
Competitive devices are limited to 25 MHz clock rates at supply voltages in the 2.7V to 3.6V range. The serial
interface is compatible with standard SPI, QSPI, MICROWIRE and DSP interfaces.
The reference for the DAC104S085 serves all four channels and can vary in voltage between 1V and VA,
providing the widest possible output dynamic range. The DAC104S085 has a 16-bit input shift register that
controls the outputs to be updated, the mode of operation, the powerdown condition, and the binary input data.
All four outputs can be updated simultaneously or individually depending on the setting of the two mode of
operation bits.
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a
valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three
different termination options.
The low power consumption and small packages of the DAC104S085 make it an excellent choice for use in
battery operated equipment.
The DAC104S085 is one of a family of pin compatible DACs, including the 8-bit DAC084S085 and the 12-bit
DAC124S085. The DAC104S085 operates over the extended industrial temperature range of −40°C to +125°C.
Table 1. Key Specifications
VALUE
UNIT
Resolution
10
bits
INL
±2
LSB (max)
DNL
+0.35 / −0.25
LSB (max)
Settling Time
6
µs (max)
Zero Code Error
+15
mV (max)
Full-Scale Error
−0.75
%FS (max)
1.1
mW (3V)
2.5
mW (5V) typ
0.3
µW (3V)
0.8
µW (5V) typ
Supply Power
Normal
Power Down
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006–2012, Texas Instruments Incorporated
DAC104S085
SNAS362E – MAY 2006 – REVISED OCTOBER 2012
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Pin Configuration
VA 1
VOUTA 2
VOUTB 3
VOUTC 4
VOUTD 5
VA
1
VOUTA
2
VOUTB
VOUTC
VOUTD
10 SCLK
9 SYNC
SON 8 DIN
7 VREFIN
6 GND
10
SCLK
9
3 VSSOP 8
4
7
5
6
SYNC
DIN
VREFIN
GND
Block Diagram
VREFIN
DAC104S085
REF
POWER-ON
RESET
10 BIT DAC
VOUTA
BUFFER
10
2.5k
100k
REF
10 BIT DAC
VOUTB
BUFFER
10
DAC
REGISTER
2.5k
100k
REF
10 BIT DAC
VOUTC
BUFFER
10
2.5k
100k
10
REF
10 BIT DAC
VOUTD
BUFFER
10
2.5k
INPUT
CONTROL
LOGIC
SYNC
2
SCLK
100k
POWER-DOWN
CONTROL
LOGIC
DIN
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PIN DESCRIPTIONS
SON
VSSOP
Pin No.
Symbol
Type
Description
1
VA
Supply
2
VOUTA
Analog Output
Power supply input. Must be decoupled to GND.
Channel A Analog Output Voltage.
3
VOUTB
Analog Output
Channel B Analog Output Voltage.
4
VOUTC
Analog Output
Channel C Analog Output Voltage.
5
VOUTD
Analog Output
Channel D Analog Output Voltage.
6
GND
Ground
7
VREFIN
Analog Input
Unbuffered reference voltage shared by all channels. Must be decoupled
to GND.
8
DIN
Digital Input
Serial Data Input. Data is clocked into the 16-bit shift register on the
falling edges of SCLK after the fall of SYNC.
Ground reference for all on-chip circuitry.
9
SYNC
Digital Input
Frame synchronization input for the data input. When this pin goes low, it
enables the input shift register and data is transferred on the falling edges
of SCLK. The DAC is updated on the 16th clock cycle unless SYNC is
brought high before the 16th clock, in which case the rising edge of
SYNC acts as an interrupt and the write sequence is ignored by the DAC.
10
SCLK
Digital Input
Serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
11
PAD
(SON only)
Ground
Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance and
enhances package self-alignment during reflow.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings
(1) (2) (3)
Supply Voltage, VA
6.5V
−0.3V to 6.5V
Voltage on any Input Pin
Input Current at Any Pin (4)
10 mA
Package Input Current (4)
20 mA
Power Consumption at TA = 25°C
See
ESD Susceptibility (6)
Human Body Model
(5)
2500V
Machine Model
250V
Junction Temperature
+150°C
Storage Temperature
−65°C to +150°C
(1)
(2)
(3)
(4)
(5)
(6)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited to 10 mA. The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10
mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe
fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through ZERO
Ohms.
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(1) (2)
Operating Ratings
−40°C ≤ TA ≤ +125°C
Operating Temperature Range
Supply Voltage, VA
+2.7V to 5.5V
Reference Voltage, VREFIN
+1.0V to VA
Digital Input Voltage (3)
0.0V to 5.5V
Output Load
0 to 1500 pF
SCLK Frequency
(1)
(2)
(3)
Up to 40 MHz
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not guarantee specific performance limits. For guaranteed specifications and test conditions, see
the Electrical Characteristics. The guaranteed specifications apply only for the test conditions listed. Some performance characteristics
may degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating
Ratings is not recommended.
All voltages are measured with respect to GND = 0V, unless otherwise specified.
The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion
result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device.
I/O
TO INTERNAL
CIRCUITRY
GND
Package Thermal Resistances (1)
(1)
Package
θJA
10-Lead VSSOP
240°C/W
10-Lead SON
250°C/W
Soldering process must comply with National Semiconductor's Reflow Temperature Profile specifications. Refer to
www.national.com/packaging
Reflow temperature profiles are different for lead-free packages.
Electrical Characteristics
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code
range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise
specified.
Symbol
Parameter
Conditions
Typical (1)
Limits (1)
Units
(Limits)
10
Bits (min)
STATIC PERFORMANCE
Resolution
Monotonicity
LSB (max)
+0.08
+0.35
LSB (max)
−0.03
−0.25
LSB (min)
+5
+15
mV (max)
IOUT = 0
−0.1
−0.75
%FSR (max)
All ones Loaded to DAC register
−0.2
−1.0
%FSR
−20
µV/°C
VA = 3V
−0.7
ppm/°C
VA = 5V
−1.0
ppm/°C
DNL
Differential Non-Linearity
VA = 2.7V to 5.5V
ZE
Zero Code Error
IOUT = 0
FSE
Full-Scale Error
GE
Gain Error
TC GE
4
Bits (min)
±2
Integral Non-Linearity
ZCED
(1)
10
±0.7
INL
Zero Code Error Drift
Gain Error Tempco
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average
Outgoing Quality Level).
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Electrical Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code
range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise
specified.
Symbol
Parameter
Conditions
Typical (1)
Limits (1)
Units
(Limits)
0
VREFIN
V (min)
V (max)
±1
µA (max)
OUTPUT CHARACTERISTICS
Output Voltage Range
IOZ
ZCO
FSO
IOS
IOS
(2)
High-Impedance Output
Leakage Current (2)
Zero Code Output
Full Scale Output
Output Short Circuit Current
(source)
Output Short Circuit Current (sink)
IO
Continuous Output
Current (2)
CL
Maximum Load Capacitance
ZOUT
See
VA = 3V, IOUT = 200 µA
1.3
mV
VA = 3V, IOUT = 1 mA
6.0
mV
VA = 5V, IOUT = 200 µA
7.0
mV
VA = 5V, IOUT = 1 mA
10.0
mV
VA = 3V, IOUT = 200 µA
2.984
V
VA = 3V, IOUT = 1 mA
2.934
V
VA = 5V, IOUT = 200 µA
4.989
V
VA = 5V, IOUT = 1 mA
4.958
V
VA = 3V, VOUT = 0V,
Input Code = 3FFh
-56
mA
VA = 5V, VOUT = 0V,
Input Code = 3FFh
-69
mA
VA = 3V, VOUT = 3V,
Input Code = 000h
52
mA
VA = 5V, VOUT = 5V,
Input Code = 000h
75
mA
Available on each DAC output
11
mA (max)
RL = ∞
1500
pF
RL = 2kΩ
1500
pF
7.5
Ω
DC Output Impedance
REFERENCE INPUT CHARACTERISTICS
Input Range Minimum
VREFIN
0.2
Input Range Maximum
Input Impedance
1.0
V (min)
VA
V (max)
30
kΩ
LOGIC INPUT CHARACTERISTICS
IIN
Input Current (2)
VIL
Input Low Voltage (2)
±1
µA (max)
VA = 3V
0.9
0.6
V (max)
VA = 5V
1.5
0.8
V (max)
VA = 3V
1.4
2.1
V (min)
VA = 5V
2.1
2.4
V (min)
3
pF (max)
Supply Voltage Minimum
2.7
V (min)
Supply Voltage Maximum
5.5
V (max)
VIH
Input High Voltage (2)
CIN
(2)
Input Capacitance
POWER REQUIREMENTS
VA (3)
(2)
(3)
This parameter is guaranteed by design and/or characterization and is not tested in production.
To guarantee accuracy, it is required that VA and VREFIN be well bypassed.
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Electrical Characteristics (continued)
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code
range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise
specified.
Symbol
Parameter
fSCLK = 30 MHz
Normal Supply Current (output
unloaded)
IN
fSCLK = 0
IPD
Power Down Supply Current
(output unloaded, SYNC = DIN =
0V after PD mode loaded)
All PD Modes, (2)
fSCLK = 30 MHz
Normal Supply Power (output
unloaded)
PN
fSCLK = 0
PPD
Power Down Supply Power (output
unloaded, SYNC = DIN = 0V after
PD mode loaded)
Typical (1)
Limits (1)
Units
(Limits)
VA = 2.7V
to 3.6V
350
485
µA (max)
VA = 4.5V
to 5.5V
500
650
µA (max)
VA = 2.7V
to 3.6V
330
µA
VA = 4.5V
to 5.5V
460
µA
VA = 2.7V
to 3.6V
0.10
1.0
µA (max)
VA = 4.5V
to 5.5V
0.15
1.0
µA (max)
VA = 2.7V
to 3.6V
1.1
1.7
mW (max)
VA = 4.5V
to 5.5V
2.5
3.6
mW (max)
VA = 2.7V
to 3.6V
1.0
mW
VA = 4.5V
to 5.5V
2.3
mW
VA = 2.7V
to 3.6V
0.3
3.6
µW (max)
VA = 4.5V
to 5.5V
0.8
5.5
µW (max)
Conditions
All PD Modes,
(2)
A.C. and Timing Characteristics
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code
range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise
specified.
Symbol
fSCLK
Parameter
Conductions
SCLK Frequency
Typical (1)
Limits (1)
Units
(Limits)
40
30
MHz (max)
100h to 300h code change
RL = 2 kΩ, CL = 200 pF
4.5
6
µs (max)
1
V/µs
Code change from 200h to 1FFh
12
nV-sec
0.5
nV-sec
Digital Crosstalk
1
nV-sec
DAC-to-DAC Crosstalk
3
nV-sec
ts
Output Voltage Settling Time (2)
SR
Output Slew Rate
Glitch Impulse
Digital Feedthrough
Multiplying Bandwidth
VREFIN = 2.5V ± 0.1Vpp
160
kHz
Total Harmonic Distortion
VREFIN = 2.5V ± 0.1Vpp
input frequency = 10kHz
70
dB
VA = 3V
6
µsec
VA = 5V
39
µsec
tWU
Wake-Up Time
1/fSCLK
SCLK Cycle Time
25
33
ns (min)
tCH
SCLK High time
7
10
ns (min)
(1)
(2)
6
Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are guaranteed to National's AOQL (Average
Outgoing Quality Level).
This parameter is guaranteed by design and/or characterization and is not tested in production.
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A.C. and Timing Characteristics (continued)
Values shown in this table are design targets and are subject to change before product release.
The following specifications apply for VA = +2.7V to +5.5V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, input code
range 12 to 1011. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are at TA = 25°C, unless otherwise
specified.
Symbol
Parameter
Conductions
Typical (1)
Limits (1)
Units
(Limits)
tCL
SCLK Low Time
7
10
ns (min)
tSS
SYNC Set-up Time prior to SCLK
Falling Edge
4
10
ns (min)
tDS
Data Set-Up Time prior to SCLK Falling
Edge
1.5
3.5
ns (min)
tDH
Data Hold Time after SCLK Falling
Edge
1.5
3.5
ns (min)
tCFSR
SCLK fall prior to rise of SYNC
0
3
ns (min)
tSYNC
SYNC High Time
6
10
ns (min)
Specification Definitions
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB, which is VREF / 1024 = VA / 1024.
DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change
in the output of another DAC.
DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale
change in the input register of another DAC.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data
bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (3FFh) loaded
into the DAC and the value of VA x 1023 / 1024.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE - ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is
measured from the center of that code value. The end point method is used. INL for this product is
specified over a limited range, per the Electrical Tables.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n
where
•
where VREF is the supply voltage for this product, and "n" is the DAC resolution in bits, which is 10 for
the DAC104S085.
(1)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3dB below the input sine wave
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on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed by the
device without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the falling edge of the
16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.
Transfer Characteristic
FSE
1023 x VREFIN
1024
GE = FSE - ZE
FSE = GE + ZE
OUTPUT
VOLTAGE
ZE
0
0
1024
DIGITAL INPUT CODE
Figure 1. Input / Output Transfer Characteristic
Timing Diagrams
|
1 / fSCLK
SCLK
1
2
13
tSS
tSYNC
tCL
14
15
16
tCH
tCFSR
|
SYNC
DIN
| |
tDH
DB15
DB0
tDS
Figure 2. Serial Timing Diagram
8
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Typical Performance Characteristics
VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated
10
INL at VA = 3.0V
INL at VA = 5.0V
Figure 3.
Figure 4.
DNL at VA = 3.0V
DNL at VA = 5.0V
Figure 5.
Figure 6.
INL/DNL
vs
VREFIN at VA = 3.0V
INL/DNL
vs
VREFIN at VA = 5.0V
Figure 7.
Figure 8.
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Typical Performance Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated
INL/DNL
vs
fSCLK at VA = 2.7V
INL/DNL
vs
VA
Figure 9.
Figure 10.
INL/DNL
vs
Clock Duty Cycle at VA = 3.0V
INL/DNL
vs
Clock Duty Cycle at VA = 5.0V
Figure 11.
Figure 12.
INL/DNL
vs
Temperature at VA = 3.0V
INL/DNL
vs
Temperature at VA = 5.0V
Figure 13.
Figure 14.
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Typical Performance Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated
12
Zero Code Error
vs.
VA
Zero Code Error
vs.
VREFIN
Figure 15.
Figure 16.
Zero Code Error
vs.
fSCLK
Zero Code Error
vs.
Clock Duty Cycle
Figure 17.
Figure 18.
Zero Code Error
vs.
Temperature
Full-Scale Error
vs.
VA
Figure 19.
Figure 20.
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Typical Performance Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated
Full-Scale Error
vs.
VREFIN
Full-Scale Error
vs.
fSCLK
Figure 21.
Figure 22.
Full-Scale Error
vs.
Clock Duty Cycle
Full-Scale Error
vs.
Temperature
Figure 23.
Figure 24.
Supply Current
vs.
VA
Supply Current
vs.
Temperature
Figure 25.
Figure 26.
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Typical Performance Characteristics (continued)
VREF = VA, fSCLK = 30 MHz, TA = 25C, Input Code Range 12 to 1011, unless otherwise stated
14
5V Glitch Response
Power-On Reset
Figure 27.
Figure 28.
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FUNCTIONAL DESCRIPTION
DAC SECTION
The DAC104S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared
by all four DACs.
For simplicity, a single resistor string is shown in Figure 29. This string consists of 1024 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage of:
VOUTA,B,C,D = VREFIN x (D / 1024)
(2)
where D is the decimal equivalent of the binary code that is loaded into the DAC register. D can take on any
value between 0 and 1023. This configuration guarantees that the DAC is monotonic.
VA
R
R
R
To Output Amplifier
R
R
Figure 29. DAC Resistor String
OUTPUT AMPLIFIERS
The output amplifiers are rail-to-rail, providing an output voltage range of 0V to VA when the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the
amplifier are described in the Electrical Tables.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zerocode and full-scale outputs for given load currents are available in the Electrical Characteristics Table.
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REFERENCE VOLTAGE
The DAC104S085 uses a single external reference that is shared by all four channels. The reference pin, VREFIN,
is not buffered and has an input impedance of 30 kΩ. It is recommended that VREFIN be driven by a voltage
source with low output impedance. The reference voltage range is 1.0V to VA, providing the widest possible
output dynamic range.
SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and MICROWIRE, as well as most DSPs and operates at
clock rates up to 40 MHz. See the Timing Diagram for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register,
it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Serial Timing Diagram,
Figure 2). On the 16th falling clock edge, the last data bit is clocked in and the programmed function (a change in
the DAC channel address, mode of operation and/or register contents) is executed. At this point the SYNC line
may be kept low or brought high. Any data and clock pusles after the 16th falling clock edge will be ignored. In
either case, SYNC must be brought high for the minimum specified time before the next write sequence is
initiated with a falling edge of SYNC.
Since the SYNC and DIN buffers draw more current when they are high, they should be idled low between write
sequences to minimize power consumption.
INPUT SHIFT REGISTER
The input shift register, Figure 30, has sixteen bits. The first two bits are address bits. They determine whether
the register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that
determine the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing
to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating
their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The
data format is straight binary (MSB first, LSB last), with all 0's corresponding to an output of 0V and all 1's
corresponding to a full-scale output of VREFIN - 1 LSB. The contents of the serial input register are transferred to
the DAC register on the sixteenth falling edge of SCLK. See Timing Diagram, Figure 2.
LSB
MSB
A1
A0
OP1 OP0 D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DATA BITS
0
0
1
1
0
1
0
1
DAC A
DAC B
DAC C
DAC D
0
0
1
1
0
1
0
1
Write to specified register but do not update outputs.
Write to specified register and update outputs.
Write to all registers and update outputs.
Power-down outputs.
Figure 30. Input Register Contents
Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift
register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and
there is no change in the mode of operation or in the DAC output voltages.
POWER-ON RESET
The power-on reset circuit controls the output voltages of the four DACs during power-up. Upon application of
power, the DAC registers are filled with zeros and the output voltages are 0V. The outputs remain at 0V until a
valid write sequence is made to the DAC.
16
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POWER-DOWN MODES
The DAC104S085 has four power-down modes, two of which are identical. In power-down mode, the supply
current drops to 20 µA at 3V and 30 µA at 5V. The DAC104S085 is set in power-down mode by setting OP1 and
OP0 to 11. Since this mode powers down all four DACs, the address bits, A1 and A0, are used to select different
output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tri-stated (a high
impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by 2.5 kΩ or 100 kΩ
to ground respectively (see Table 2).
Table 2. Power-Down Modes
A1
A0
OP1
OP0
0
0
1
1
Operating Mode
High-Z outputs
0
1
1
1
2.5 kΩ to GND
1
0
1
1
100 kΩ to GND
1
1
1
1
High-Z outputs
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the
power-down modes. However, the contents of the DAC registers are unaffected when in power-down. Each DAC
register maintains its value prior to the DAC104S085 being powered down unless it is changed during the write
sequence which instructed it to recover from power down. Minimum power consumption is achieved in the
power-down mode with SYNC and DIN idled low and SCLK disabled. The time to exit power-down (Wake-Up
Time) is typically tWU µsec as stated in the A.C. and Timing Characteristics table.
Applications Information
USING REFERENCES AS POWER SUPPLIES
While the simplicity of the DAC104S085 implies ease of use, it is important to recognize that the path from the
reference input (VREFIN) to the VOUTs will have essentially zero Power Supply Rejection Ratio (PSRR).
Therefore, it is necessary to provide a noise-free supply voltage to VREFIN. In order to utilize the full dynamic
range of the DAC104S085, the supply pin (VA) and VREFIN can be connected together and share the same supply
voltage. Since the DAC104S085 consumes very little power, a reference source may be used as the reference
input and/or the supply voltage. The advantages of using a reference source over a voltage regulator are
accuracy and stability. Some low noise regulators can also be used. Listed below are a few reference and power
supply options for the DAC104S085.
LM4130
The LM4130, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC104S085. The 4.096V version is useful if a 0 to 4.095V output range is desirable or acceptable. Bypassing
the LM4130 VIN pin with a 0.1µF capacitor and the VOUT pin with a 2.2µF capacitor will improve stability and
reduce output noise. The LM4130 comes in a space-saving 5-pin SOT23.
Input
Voltage
LM4132-4.1
C1
0.1 PF
C2
2.2 PF
C3
0.1 PF
VA VREFIN
DAC104S085
VOUT = 0V to 4.092V
SYNC
DIN
SCLK
Figure 31. The LM4130 as a power supply
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LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC104S085. It is available in 4.096V and 5V versions and comes in a space-saving 3-pin SOT23.
Input
Voltage
R
VZ
IDAC
IZ
0.1 PF
0.47 PF
LM4050-4.1
or
LM4050-5.0
VA VREFIN
DAC104S085
VOUT = 0V to 5V
SYNC
DIN
SCLK
Figure 32. The LM4050 as a power supply
The minimum resistor value in the circuit of Figure 32 must be chosen such that the maximum current through
the LM4050 does not exceed its 15 mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, and the DAC104S085 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC104S085 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC104S085 draws its maximum current. These conditions can be summarized as
R(min) = ( VIN(max) − VZ(min) ) /IZ(max)
(3)
and
R(max) = ( VIN(min) − VZ(max) ) / ( (IDAC(max) + IZ(min) )
where
•
•
•
•
VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature
IZ(max) is the maximum allowable current through the LM4050
IZ(min) is the minimum current required by the LM4050 for proper regulation
IDAC(max) is the maximum DAC104S085 supply current.
(4)
LP3985
The LP3985 is a low noise, ultra low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC104S085. It comes in 3.0V, 3.3V and
5V versions, among others, and sports a low 30 µV noise specification at low frequencies. Since low frequency
noise is relatively difficult to filter, this specification could be important for some applications. The LP3985 comes
in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
18
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Input
Voltage
LP3985
0.1 PF
1 PF
0.01 PF
0.1 PF
VA VREFIN
DAC104S085
VOUT = 0V to 5V
SYNC
DIN
SCLK
Figure 33. Using the LP3985 regulator
An input capacitance of 1.0µF without any ESR requirement is required at the LP3985 input, while a 1.0µF
ceramic capacitor with an ESR requirement of 5mΩ to 500mΩ is required at the output. Careful interpretation
and understanding of the capacitor specification is required to ensure correct device operation.
LP2980
The LP2980 is an ultra low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon
grade. It is available in 3.0V, 3.3V and 5V versions, among others.
Input
Voltage
VIN
VOUT
LP2980
ON /OFF
1 PF
0.1 PF
VA VREFIN
DAC104S085
VOUT = 0V to 5V
SYNC
DIN
SCLK
Figure 34. Using the LP2980 regulator
Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1.0µF over temperature, but values of 2.2µF or more will provide even better performance. The
ESR of this capacitor should be within the range specified in the LP2980 data sheet. Surface-mount solid
tantalum capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to
their small size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic
capacitors are typically not a good choice due to their large size and have ESR values that may be too high at
low temperatures.
BIPOLAR OPERATION
The DAC104S085 is designed for single supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 35. This circuit will provide an output voltage range of ±5 Volts.
A rail-to-rail amplifier should be used if the amplifier supplies are limited to ±5V.
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10 pF
R2
+5V
R1
+5V
10 PF
+
-
0.1 PF
±5V
+
DAC104S085
-5V
SYNC
DIN
VOUT
SCLK
Figure 35. Bipolar Operation
The output voltage of this circuit for any code is found to be
VO = (VA x (D / 1024) x ((R1 + R2) / R1) - VA x R2 / R1)
where
• D is the input code in decimal form
• With VA = 5V and R1 = R2
VO = (10 x D / 1024) - 5V
(5)
(6)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 3.
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Table 3. Some Rail-to-Rail Amplifiers
AMP
PKGS
LMC7111
DIP-8
SOT23-5
Typ VOS
Typ ISUPPLY
0.9 mV
25 µA
LM7301
SO-8
SOT23-5
0.03 mV
620 µA
LM8261
SOT23-5
0.7 mV
1 mA
DSP/MICROPROCESSOR INTERFACING
Interfacing the DAC104S085 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.
ADSP-2101/ADSP2103 Interfacing
Figure 36 shows a serial interface between the DAC104S085 and the ADSP-2101/ADSP2103. The DSP should
be set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and should be configured for Internal Clock Operation, Active Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.
ADSP-2101/
ADSP2103
TFS
DT
SCLK
DAC104S085
SYNC
DIN
SCLK
Figure 36. ADSP-2101/2103 Interface
80C51/80L51 Interface
A serial interface between the DAC104S085 and the 80C51/80L51 microcontroller is shown in Figure 37. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is transmitted to the DAC104S085. Since the 80C51/80L51 transmits 8-bit
bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must be
left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC104S085 requires data with the MSB first.
80C51/80L51
DAC104S085
P3.3
SYNC
TXD
SCLK
RXD
DIN
Figure 37. 80C51/80L51 Interface
68HC11 Interface
A serial interface between the DAC104S085 and the 68HC11 microcontroller is shown in Figure 38. The SYNC
line of the DAC104S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.
The 68HC11 should be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 should be raised to end the write sequence.
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68HC11
DAC104S085
PC7
SYNC
SCK
SCLK
MOSI
DIN
Figure 38. 68HC11 Interface
Microwire Interface
Figure 39 shows an interface between a Microwire compatible device and the DAC104S085. Data is clocked out
on the rising edges of the SK signal. As a result, the SK of the Microwire device needs to be inverted before
driving the SCLK of the DAC104S085.
MICROWIRE
DEVICE
CS
SYNC
SK
SCLK
SO
DIN
DAC104S085
Figure 39. Microwire Interface
LAYOUT, GROUNDING, AND BYPASSING
For best accuracy and minimum noise, the printed circuit board containing the DAC104S085 should have
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.
Both of these planes should be located in the same board layer. There should be a single ground plane. A single
ground plane is preferred if digital return current does not flow through the analog ground area. Frequently a
single ground plane design will utilize a "fencing" technique to prevent the mixing of analog and digital ground
current. Separate ground planes should only be utilized when the fencing technique is inadequate. The separate
ground planes must be connected in one place, preferably near the DAC104S085. Special care is required to
guarantee that digital signals with fast edge rates do not pass over split ground planes. They must always have a
continuous return path below their traces.
The DAC104S085 power supply should be bypassed with a 10µF and a 0.1µF capacitor as close as possible to
the device with the 0.1µF right at the device supply pin. The 10µF capacitor should be a tantalum type and the
0.1µF capacitor should be a low ESL, low ESR type. The power supply for the DAC104S085 should only be
used for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines should have controlled impedances.
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PACKAGE OPTION ADDENDUM
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9-Mar-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package Qty
Drawing
Eco Plan
Lead/Ball Finish
(2)
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
(3)
(4)
DAC104S085CIMM
ACTIVE
VSSOP
DGS
10
1000
TBD
Call TI
Call TI
-40 to 105
X68C
DAC104S085CIMM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X68C
DAC104S085CIMMX
ACTIVE
VSSOP
DGS
10
3500
TBD
Call TI
Call TI
-40 to 105
X68C
DAC104S085CIMMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X68C
DAC104S085CISD
ACTIVE
WSON
DSC
10
1000
TBD
Call TI
Call TI
-40 to 105
X69C
DAC104S085CISD/NOPB
ACTIVE
WSON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X69C
DAC104S085CISDX
ACTIVE
WSON
DSC
10
4500
TBD
Call TI
Call TI
-40 to 105
X69C
DAC104S085CISDX/NOPB
ACTIVE
WSON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 105
X69C
DAC104S085QIMM/NOPB
ACTIVE
VSSOP
DGS
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
DAC104S085QIMMX/NOPB
ACTIVE
VSSOP
DGS
10
3500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
9-Mar-2013
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Only one of markings shown within the brackets will appear on the physical device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF DAC104S085, DAC104S085-Q1 :
• Catalog: DAC104S085
• Automotive: DAC104S085-Q1
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
DAC104S085CIMM
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC104S085CIMM/NOPB VSSOP
DGS
10
1000
178.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
VSSOP
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC104S085CIMMX/NOP VSSOP
B
DGS
10
3500
330.0
12.4
5.3
3.4
1.4
8.0
12.0
Q1
DAC104S085CIMMX
DAC104S085CISD
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
DAC104S085CISD/NOPB
SON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
DAC104S085CISDX
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
SON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
DAC104S085CISDX/NOP
B
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Nov-2012
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
DAC104S085CIMM
VSSOP
DGS
10
1000
203.0
190.0
41.0
DAC104S085CIMM/NOPB
VSSOP
DGS
10
1000
203.0
190.0
41.0
DAC104S085CIMMX
VSSOP
DGS
10
3500
349.0
337.0
45.0
VSSOP
DGS
10
3500
349.0
337.0
45.0
DAC104S085CIMMX/NOP
B
DAC104S085CISD
SON
DSC
10
1000
203.0
190.0
41.0
DAC104S085CISD/NOPB
SON
DSC
10
1000
203.0
190.0
41.0
DAC104S085CISDX
SON
DSC
10
4500
349.0
337.0
45.0
SON
DSC
10
4500
349.0
337.0
45.0
DAC104S085CISDX/NOP
B
Pack Materials-Page 2
MECHANICAL DATA
DSC0010A
SDA10A (Rev A)
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