EM48BM1684LBC Revision History Revision 0.1 (Jun. 2012) First release. Jun. 2012 www.eorex.com 1/20 EM48BM1684LBC 512Mb (8M4Bank16) Mobile Synchronous DRAM Features Description • Fully Synchronous to Positive Clock Edge The EM48BM1684LBC is Mobile Synchronous • VDD= 1.7 ~1.95V for 133/166MHz Power Supply Dynamic Random Access Memory (SDRAM) • LVCMOS Compatible with Multiplexed Address organized as 8Meg words x 4 banks by 16 bits. All • Programmable Burst Length (B/L) - 1, 2, 4, 8 inputs and outputs are synchronized with the positive edge of the clock. or Full Page • Programmable CAS Latency (C/L) - 3 The 512Mb Mobile SDRAM uses synchronized • Data Mask (DQM) for Read / Write Masking pipelined architecture to achieve high speed data • Programmable Wrap Sequence transfer rates and is designed to operate at 1.8V – Sequential (B/L = 1/2/4/8/full Page) low power memory system. It also provides auto – Interleave (B/L = 1/2/4/8) refresh with power saving / down mode. All inputs • Burst Read with Single-bit Write Operation and outputs voltage levels are compatible with • All Inputs are sampled at the Rising Edge of the LVCMOS. Available packages: System Clock • Auto Refresh and Self Refresh FBGA-54B (8mm x 9mm) • 8,192 Refresh Cycles / 64ms (7.8us) • Driver strength: normal/weak Ordering Information Part No Organization Max. Freq Package Grade Pb EM48BM1684LBC-75F 32M X 16 133MHz @CL3 FBGA-54B Commercial Free EM48BM1684LBC-75FE 32M X 16 133MHz @CL3 FBGA-54B Extended Free EM48BM1684LBC-6F 32M X 16 166MHz @CL3 FBGA-54B Commercial Free EM48BM1684LBC-6FE 32M X 16 166MHz @CL3 FBGA-54B Extended Free Jun. 2012 www.eorex.com 2/20 EM48BM1684LBC Parts Naming Rule * EOREX reserves the right to change products or specification without notice. Jun. 2012 www.eorex.com 3/20 EM48BM1684LBC Pin Assignment: FBGA 54Ball 54Ball FBGA (8mm x 10mm) Jun. 2012 www.eorex.com 4/20 EM48BM1684LBC Pin Description (Simplified) Pin Name F2 CLK G9 /CS F3 CKE H7,H8,J8,J7,J3, J2,H3,H2,H1,G3, H9,G2,G1 A0~A12 G7,G8 BA0, BA1 F8 /RAS F7 /CAS F9 /WE F1, E8 UDQM, LDQM A8,B9,B8,C9,C8, D9,D8,E9,E1,D2, D1,C2,C1,B2,B1, A2 A9,E7,J9/ A1,E3,J1 A7,B3,C7,D3/ A3,B7,C3,D7 E2 DQ0~DQ15 VDD/VSS VDDQ/VSSQ NC Function (System Clock) Master clock input (Active on the positive rising edge) (Chip Select) Selects chip when active (Clock Enable) Activates the CLK when “H” and deactivates when “L”. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. (Address) Row address (A0 to A12) is determined by A0 to A12 level at the bank active command cycle CLK rising edge. CA (CA0 to CA9) is determined by A0 to A9 level at the read or write command cycle CLK rising edge. And this column address becomes burst access start address. A10 defines the pre-charge mode. When A10= High at the pre-charge command cycle, all banks are pre-charged. But when A10= Low at the pre-charge command cycle, only the bank that is selected by BA0/BA1 is pre-charged. (Bank Address) Selects which bank is to be active. (Row Address Strobe) Latches Row Addresses on the positive rising edge of the CLK with /RAS “L”. Enables row access & pre-charge. (Column Address Strobe) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Write Enable) Latches Column Addresses on the positive rising edge of the CLK with /CAS low. Enables column access. (Data Input/Output Mask) DQM controls I/O buffers. (Data Input/Output) DQ pins have the same function as I/O pins on a conventional DRAM. (Power Supply/Ground) VDD and VSS are power supply pins for internal circuits. (Power Supply/Ground) VDDQ and VSSQ are power supply pins for the output buffers. (No Connection) This pin is recommended to be left No Connection on the device. Jun. 2012 www.eorex.com 5/20 EM48BM1684LBC Absolute Maximum Rating Symbol Item Rating Units VIN, VOUT Input, Output Voltage -0.3 ~ +2.7 V VDD, VDDQ Power Supply Voltage -0.3 ~ +2.7 V TOP Operating Temperature Range TSTG Storage Temperature Range Commercial 0 ~ +70 Extended -25 ~ +85 °C -55 ~ +125 °C PD Power Dissipation 1 W IOS Short Circuit Current 50 mA Note: Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Capacitance (VCC=1.7~1.95V, f=1MHz, TA=25°C) Symbol Parameter Min. Typ. Max. Units CCLK Clock Capacitance Input Capacitance for CLK, CKE, Address, /CS, /RAS, /CAS, /WE, DQML, DQMU Input/Output Capacitance 1.5 - 3.5 pF 1.5 - 3.0 pF 3.0 - 5.0 pF Min. Typ. Max. Units CI CO Recommended DC Operating Conditions Symbol Parameter VDD Power Supply Voltage 1.7 1.8 1.95 V VDDQ Power Supply Voltage (for I/O Buffer) 1.7 1.8 1.95 V 0.8*VDDQ - VDDQ+0.3 V -0.3 - 0.3 V VIH Input Logic High Voltage Input Logic Low Voltage VIL Note: * All voltages referred to VSS. Jun. 2012 www.eorex.com 6/20 EM48BM1684LBC Recommended DC Operating Conditions (VDD=1.8V) Symbol Speed -6 Speed -75 Units Burst length=1, tRC=tRC(min.), IOL=0mA, One bank active 38 35 mA Parameter Test Conditions (Note 1) IDD1 Operating Current IDD2P Precharge Standby Current in Power Down Mode CKE≦VIL(max), tCK=15ns 0.8 0.8 mA IDD3P Active Standby Current in Power Down Mode CKE≦VIL(max), tCK=15ns 5 5 mA Operating Current (Burst Mode) tCCD≧2tCK, IOL=0mA 75 70 mA CKE, /CS=high, tRFC≧tRFC (MIN) 75 75 mA CKE≦0.2V, Full Array 1 1 mA ICC4 (Note 2) ICC5 Auto Refresh Current ICC6 Self Refresh Current (Note 3) *All voltages referenced to VSS. Note 1: ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 2: ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. Input signals are changed only one time during tCK (min.) Note 3: Input signals are changed only one time during tCK (min.) Recommended DC Operating Conditions (Continued) Symbol Parameter Test Conditions Min. Typ. Max. Units -1 - +1 uA -5 - +5 uA IIL Input Leakage Current IOL Output Leakage Current 0≦VI≦VDDQ, VDDQ=VDD All other pins not under test=0V 0≦VO≦VDDQ, DOUT is disabled VOH High Level Output Voltage IO=-0.1mA 0.9*VDDQ - - V VOL Low Level Output Voltage IO=+0.1mA - - 0.2 V Jun. 2012 www.eorex.com 7/20 EM48BM1684LBC Block Diagram Auto/Self Refresh Counter A0 A1 DQM A2 A3 A4 Memory Array A5 A6 Write DQM Control A7 A8 Data In A9 DOi S/A & I/O Gating A10 A11 Data Out Col. Decoder A12 BA0 BA1 Col. Add. Buffer Read DQM Control Mode Register Set Col. Add. Counter Burst Counter Timing Register CLK CKE /CS /RAS /CAS Jun. 2012 /WE DQM www.eorex.com 8/20 EM48BM1684LBC AC Operating Test Conditions (VDD=1.8V) Item Conditions Output Reference Level 0.5*VDDQ Output Load See diagram as below Input Signal Level 0.9*VDDQ/0.2 Transition Time of Input Signals 1ns/1ns Input Reference Level 0.5*VDDQ AC Operating Test Characteristics (VDD=1.8V) -6 Symbol Parameter -75 Min Max Min Max Units tCK Clock Cycle Time CL=3 6 - 7.5 - ns tAC Access Time form CLK CL=3 - 5.4 - 5.4 ns tCH CLK High Level Width 2 - 2.5 - ns tCL CLK Low Level Width 2 - 2.5 - ns tOH Data-out Hold Time 2.5 - 2.5 - ns - 5.4 - 5.4 ns tHZ Data-out High Impedance Time (Note 5) CL=3 CL=3 tLZ Data-out Low Impedance Time 1 - 1 - ns tIH Input Hold Time 1 - 1 - ns tIS Input Setup Time 1.5 - 1.5 - ns * All voltages referenced to VSS. Note 5: tHZ defines the time at which the output achieve the open circuit condition and is not referenced to output voltage levels. Jun. 2012 www.eorex.com 9/20 EM48BM1684LBC AC Operating Test Characteristics (Continued) (VDD=1.8V) Symbol tRC tRAS tRP tRCD tRRD -6 Parameter ACTIVE to ACTIVE Command Period (Note 6) ACTIVE to PRECHARGE Command Period (Note 6) PRECHARGE to ACTIVE Command Period (Note 6) ACTIVE to READ/WRITE Delay Time (Note 6) ACTIVE(one) to ACTIVE(another) Command (Note 6) -75 Max. Units Min. Max. Min. 60 - 72.5 - ns 42 100k 50 100k ns 18 - 18 - ns 18 - 18 - ns 12 - 15 - ns tCCD READ/WRITE Command to READ/WRITE Command 1 - 1 - tCLK tDPL Date-in to PRECHARGE Command 2 - 2 - tCLK tBDL Date-in to BURST Stop Command 1 - 1 - tCLK tROH Data-out to High Impedance from PRECHARGE Command 3 - 3 - tCLK tREF Refresh Time (8,192 cycle) - 64 - 64 ms CL=3 Refresh to Refresh/ACTIVE command period 72 72 ns tRFC * All voltages referenced to VSS. Note 6: These parameters account for the number of clock cycles and depend on the operating frequency of the clock, as follows: The number of clock cycles = Specified value of timing/clock period (Count Fractions as a whole number) Recommended Power On and Initialization The following power on and initialization sequence guarantees the device is preconditioned to each user’s specific needs. (Like a conventional DRAM) During power on, all VDD and VDDQ pins must be built up simultaneously to the specified voltage when the input signals are held in the “NOP” state. The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. (CLK signal started at same time) After power on, an initial pause of 200 µs is required followed by a precharge of all banks using the precharge command. To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial pause period. Once all banks have been precharged, the Mode Register Set Command must be issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required, and these may be done before or after programming the Mode Register. Jun. 2012 www.eorex.com 10/20 EM48BM1684LBC Simplified State Diagram Self Refresh LF SE Mode Register Set MRS Ex LF SE REF IDLE CBR Refresh it CK CK ACT E Power Down E CKE Row Active adBS Write wit WRITE Suspend CKE WRITE Wr hRead Read Re ad R wit Write CKE Active Power Down CKE e CKE READ T CKE READ Suspend h WRITEA Suspend CKE CKE WRITEA CKE PR READA PR CKE READA Suspend E E POWER ON Precharge ite Precharge Manual Input Automatic Sequence Jun. 2012 www.eorex.com 11/20 EM48BM1684LBC Address Input for Mode Register Set BA1 BA0 A12/A11 A10 A9 A8 A7 A6 Operation Mode A5 A4 A3 CAS Latency A2 BT A1 A0 Burst Length Burst Length Sequential Interleave A2 A1 A0 1 1 0 0 0 2 2 0 0 1 4 4 0 1 0 8 8 0 1 1 Reserved Reserved 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Full Page Reserved 1 1 1 Burst Type A3 Interleave 1 Sequential 0 CAS Latency A6 A5 A4 Reserved 0 0 0 Reserved 0 0 1 Reserved 0 1 0 3 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 BA1 BA0 A12/A11 A10 A9 A8 A7 Operation Mode 0 0 0 0 0 0 0 Normal 0 0 0 0 1 0 0 Burst Read with Single-bit Write Jun. 2012 www.eorex.com 12/20 EM48BM1684LBC Burst Type (A3) Burst Length 2 4 8 A2 A1 A0 Sequential Addressing Interleave Addressing X X 0 01 01 X X 0 10 10 X 0 0 0123 0123 X 0 1 1230 1032 X 1 0 2301 2301 X 1 1 3012 3210 0 0 0 01234567 01234567 0 0 1 12345670 10325476 0 1 0 23456701 23016745 0 1 1 34567012 32107654 1 0 0 45670123 45670123 1 0 1 56701234 54761032 1 1 0 67012345 67452301 1 1 1 70123456 76543210 Full Page* n n n Cn Cn+1 Cn+2…… * Page length is a function of I/O organization and column addressing 16 (CA0 ~ CA8): - Full page = 1024bits Jun. 2012 www.eorex.com 13/20 EM48BM1684LBC 1. Command Truth Table Command Symbol CKE n-1 n H X /CS /RAS /CAS /WE BA0, BA1 A10 A11, A9~A10 H X X X X X X H X X X Ignore Command DESL No Operation NOP H X L H H Burst Stop BSTH H X L H H L X X X Read READ H X L H L H V L V READA H X L H L H V H V Write WRIT H X L H L L V L V Write with Auto Pre-charge WRITA H X L H L L V H V Bank Activate ACT H X L L H H V V V Pre-charge Select Bank PRE H X L L H L V L X Pre-charge All Banks PALL H X L L H L X H X Mode Register Set MRS H X L L L L L L V Read with Auto Pre-charge H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input Jun. 2012 www.eorex.com 14/20 EM48BM1684LBC 2. DQM Truth Table Command CKE Symbol n-1 /CS n Data Write/Output Enable ENB H X H Data Mask/Output Disable MASK H X L Upper Byte Write Enable/Output Enable BSTH H X L Read READ H X L READA H X L WRIT H X L Read with Auto Pre-charge Write Write with Auto Pre-charge WRITA H X L Bank Activate ACT H X L Pre-charge Select Bank PRE H X L Pre-charge All Banks PALL H X L Mode Register Set MRS H X L H = High level, L = Low level, X = High or Low level (Don't care), V = Valid data input 3. CKE Truth Table Item Command Activating Any Clock Suspend Idle Clock Suspend Mode Entry Clock Suspend Mode CBR Refresh Command Idle Self Refresh Entry Self Refresh Symbol Clock Suspend Mode Exit CKE n-1 n H L L L /CS /RAS /CAS /WE Addr. X X X X X X X X X X L H X X X X X REF H H L L L H X SELF H L L L L L H X H L H H H X L H H X X X X Self Refresh Exit Idle Power Down Entry H L X X X X X Power Down Power Down Exit L H X X X X X Remark H = High level, L = Low level, X = High or Low level (Don't care) Jun. 2012 www.eorex.com 15/20 EM48BM1684LBC 4. Operative Command Table (Note 7) Current State Idle Row Active /CS /R /C /W Addr. Command Action H X X X X DESL Nop or power down L H H X X NOP or BST Nop or power down L H L H BA/CA/A10 READ/READA ILLEGAL L L L H L L L H H L H L BA/CA/A10 BA/RA BA, A10 WRIT/WRITA ACT PRE/PALL L L L H X REF/SELF ILLEGAL Row activating Nop Refresh or self refresh L H L L L X H H L X H L L X X H Op-Code X X BA/CA/A10 MRS DESL NOP or BST READ/READA Mode register accessing Nop Nop (Note 11) Begin read: Determine AP L H L L BA/CA/A10 WRIT/WRITA Begin write: Determine AP L L H H BA/RA ACT L L H L BA, A10 PRE/PALL Pre-charge L L H L L L L X H H L L X H H H L X H L X Op-Code X X X REF/SELF MRS DESL NOP BST L H L H BA/CA/A10 READ/READA ILLEGAL ILLEGAL Continue burst to end → Row active Continue burst to end → Row active Burst stop → Row active Terminate burst, new read: L L L L BA/CA/A10 WRIT/WRITA (Note 9) (Note 10) ILLEGAL L H H BA/RA ACT L L H L BA, A10 PRE/PALL L L L L L L H L X Op-Code REF/SELF MRS H X X X X DESL L H H H X NOP L H H L X BST L H L H BA/CA/A10 READ/READA (Note 12) (Note 10) (Note 13) Terminate burst, start write: ILLEGAL (Note 13, 14) (Note 9) Terminate burst, pre-charging (Note 10) ILLEGAL ILLEGAL Continue burst to end → Write recovering Continue burst to end → Write recovering Burst stop → Row active Terminate burst, start read: Determine AP 7, 8 Write L L L L BA/CA/A10 WRIT/WRITA L H H BA/RA ACT L L H L BA, A10 PRE/PALL (Note 13, 14) Terminate burst, new write: Determine AP 7 L (Note 11) (Note 9) Determine AP L (Note 8) (Note 9) Determine AP Read (Note 8) ILLEGAL (Note 13) (Note 9) Terminate burst, pre-charging (Note 15) ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care) L L L L L L H L X Op-Code REF/SELF MRS Jun. 2012 www.eorex.com 16/20 EM48BM1684LBC 4. Operative Command Table (Continued) Current State Read with AP Write with AP Pre-charging Row Activating (Note 7) /CS /R /C /W Addr. Command Action H X X X X DESL L H H H X NOP L L H H H L L H X BA/CA/A10 BST READ/READA Continue burst to end → Pre-charging Continue burst to end → Pre-charging ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L L L L H L L L H L BA, A10 X Op-Code PRE/PALL REF/SELF MRS H X X X X DESL L H H H X NOP L L H H H L L H X BA/CA/A10 BST READ/READA ILLEGAL ILLEGAL ILLEGAL Burst to end → Write recovering with auto pre-charge Continue burst to end → Write recovering with auto pre-charge ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L H L L L L L L X H H H H L L X H H L L H L X H L H BA, A10 X Op-Code X X X BA/CA/A10 PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRP Nop → Enter idle after tRP ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT L L L H L L L L L L X H H H H L L X H H L L H L X H L H BA, A10 X Op-Code X X X BA/CA/A10 PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL Nop → Enter idle after tRP ILLEGAL ILLEGAL Nop → Enter idle after tRCD Nop → Enter idle after tRCD ILLEGAL (Note 9) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L H H BA/RA ACT ILLEGAL L L L L L L H L L L H L BA, A10 X Op-Code PRE/PALL REF/SELF MRS (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9) (Note 9, 16) (Note 9) ILLEGAL ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Jun. 2012 www.eorex.com 17/20 EM48BM1684LBC 4. Operative Command Table (Continued) Current State Write Recovering Write Recovering with AP Refreshing Mode Register Accessing (Note 7) /CS /R /C /W Addr. Command Action H L L L L X H H H H X H H L L X H L H L X X X BA/CA/A10 BA/CA/A10 DESL NOP BST READ/READA WRIT/WRITA Nop → Enter row active after tDPL Nop → Enter row active after tDPL Nop → Enter row active after tDPL Start read, Determine AP (Note 14) New write, Determine AP L L H H BA/RA ACT L L L H L L L L L L X H H H H L L X H H L L H L X H L H BA, A10 X Op-Code X X X BA/CA/A10 PRE/PALL REF/SELF MRS DESL NOP BST READ/READA ILLEGAL ILLEGAL ILLEGAL Nop → Enter pre-charge after tDPL Nop → Enter pre-charge after tDPL Nop → Enter pre-charge after tDPL (Note 9, 14) ILLEGAL L H L L BA/CA/A10 WRIT/WRITA ILLEGAL L L L L H L L L L H L L L L L L L X H H L L X H H H H H L L X H L H L X H H L H L H L X X X X X X H L X BA/RA BA, A10 X Op-Code X X X X X X X X X L L X X X ACT PRE/PALL REF/SELF MRS DESL NOP/BST READ/WRIT ACT/PRE/PALL REF/SELF/MRS DESL NOP BST READ/WRIT ACT/PRE/PALL/ REF/SELF/MRS ILLEGAL (Note 9) (Note 9) (Note 9) (Note 9) ILLEGAL ILLEGAL ILLEGAL ILLEGAL Nop → Enter idle after tRC Nop → Enter idle after tRC ILLEGAL ILLEGAL ILLEGAL Nop Nop ILLEGAL ILLEGAL ILLEGAL Remark H = High level, L = Low level, X = High or Low level (Don't care), AP = Auto Pre-charge Note 7: All entries assume that CKE was active (High level) during the preceding clock cycle. Note 8: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Power down mode. All input buffers except CKE will be disabled. Note 9: Illegal to bank in specified states; Function may be legal in the bank indicated by Bank Address (BA), depending on the state of that bank. Note 10: If all banks are idle, and CKE is inactive (Low level), SDRAM will enter Self refresh mode. All input buffers except CKE will be disabled. Note 11: Illegal if tRCD is not satisfied. Note 12: Illegal if tRAS is not satisfied. Note 13: Must satisfy burst interrupt condition. Note 14: Must satisfy bus contention, bus turn around, and/or write recovery requirements. Note 15: Must mask preceding data which don't satisfy tDPL. Note 16: Illegal if tRRD is not satisfied. Jun. 2012 www.eorex.com 18/20 EM48BM1684LBC 5. Command Truth Table for CKE Current State Self Refresh Self Refresh Recovery Power Down Both Banks Idle CKE n-1 n Any State Other than Listed above /R /C /W Addr. H X X X X X X L L L L L H H H H H H H H H H H H L H H H H L L L L H L L L X H L L L H L L L X H H L X X H H L X H H L X H L X X X H L X X H L X X X X X X X X X X X X X X X X X X X X X X X X X X X H X X X X X X L L H H H H H H H H H H L H H H H H L L L L X X H L L L L H L L L X X X H L L L X H L L X X X X H L L X X H L X X X X X H L X X X H X X L L L L Op-Code H Row Active /CS L Action INVALID, CLK(n-1) would exit self refresh Self refresh recovery Self refresh recovery ILLEGAL ILLEGAL Maintain self refresh Idle after tRC Idle after tRC ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL ILLEGAL INVALID, CLK(n-1) would exit power down Exit power down → Idle Maintain power down mode Refer to operations in Operative Command Table X Op-Code Refresh Refer to operations in Operative Command Table X L X X X X X X H X X X X X X L X X X X X X H H X X X X H L X X X X X (Note 17) Self refresh Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table (Note 17) Power down Refer to operations in Operative Command Table Begin clock suspend next cycle (Note 18) Exit clock suspend next cycle Maintain clock suspend Remark: H = High level, L = Low level, X = High or Low level (Don't care) Notes 17: Self refresh can be entered only from the both banks idle state. Power down can be entered only from both banks idle or row active state. Notes 18: Must be legal command as defined in Operative Command Table L L H L X X X X X X X X Jun. 2012 X X www.eorex.com 19/20 EM48BM1684LBC Package Description Package: FBGA-54B Unit: mm 6.40 A1 9 8 7 6 5 4 3 2 1 A 0.80 B C D 6.4 ± 0.1 10.0 ± 0.1 E F 3.2 ± 0.05 G 5.0 ± 0.05 H J 3.2 ± 0.05 4.0 ± 0.05 8.0 ± 0.1 0.66 ± 0.05 1.025 MAX 0.45 ± 0.05 Jun. 2012 0.1 MAX www.eorex.com 20/20