–28 V, −200 mA, Low Noise,
Linear Regulator
ADP7182
Data Sheet
FEATURES
TYPICAL APPLICATION CIRCUITS
CIN
2.2µF
COUT
2.2µF
GND
VIN = –8V
ON
–2V
ADP7182
2V
NC
EN
0V
OFF
VOUT = –5V
VOUT
VIN
10703-001
ON
Figure 1. ADP7182 with Fixed Output Voltage, VOUT = −5 V
CIN
2.2µF
COUT
2.2µF
GND
VIN = –8V
ON
OFF
–2V
VIN
2V
0V
VOUT
13kΩ
40.2kΩ
VOUT = –5V
ADP7182
EN
ADJ
ON
10703-002
Low noise: 18 µV rms
Power supply rejection ratio (PSRR): 66 dB at 10 kHz at VOUT = −3 V
Positive or negative enable logic
Stable with small 2.2 µF ceramic output capacitor
Input voltage range: −2.7 V to −28 V
Maximum output current: −200 mA
Low dropout voltage: −185 mV at −200 mA load
Initial accuracy: ±1%
Accuracy over line, load, and temperature
+2% maximum/−3% minimum
Low quiescent current, IGND = −650 µA with −200 mA load
Low shutdown current: −2 µA
Adjustable output from −1.22 V to −VIN + VDO
Current-limit and thermal overload protection
6- and 8-lead LFCSP and 5-lead TSOT
Supported by ADIsimPower tool
Figure 2. ADP7182 with Adjustable Output Voltage, VOUT = −5 V
APPLICATIONS
Regulation to noise sensitive applications
Analog-to-digital converter (ADC) and digital-to-analog
converter (DAC) circuits, precision amplifiers
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7182 is a CMOS, low dropout (LDO) linear regulator
that operates from −2.7 V to −28 V and provides up to −200 mA
of output current. This high input voltage LDO is ideal for
regulation of high performance analog and mixed signal circuits
operating from −27 V down to −1.2 V rails. Using an advanced
proprietary architecture, it provides high power supply rejection
and low noise, and achieves excellent line and load transient
response with a small 2.2 µF ceramic output capacitor.
The ADP7182 is available in fixed output voltage and an
adjustable version that allows the output voltage to range from
−1.22 V to −VIN + VDO via an external feedback divider.
Rev. I
The following fixed output voltages are available from stock: −5 V
(3 mm × 3 mm LFCSP), −1.8 V, −2.5 V, −3 V, −5 V (TSOT), −1.2 V,
−1.5 V, −2.5 V, −5 V (2 mm × 2 mm LFCSP). Additional voltages
are available by special order.
The ADP7182 regulator output noise is 18 µV rms independent
of the output voltage. The enable logic is capable of interfacing
with positive or negative logic levels for maximum flexibility.
The ADP7182 is available in 5-lead TSOT, 6- and 8-lead LFCSP
packages for a small, low profile footprint.
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ADP7182
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 21
Applications ....................................................................................... 1
Adjustable Mode Operation ..................................................... 21
Typical Application Circuits............................................................ 1
Applications Information .............................................................. 22
General Description ......................................................................... 1
ADIsimPower Design Tool ....................................................... 22
Revision History ............................................................................... 2
Capacitor Selection .................................................................... 22
Specifications..................................................................................... 3
Enable Pin Operation ................................................................ 23
Input and Output Capacitance, Recommended Specifications
......................................................................................................... 4
Soft Start ...................................................................................... 23
Absolute Maximum Ratings ............................................................ 5
Current-Limit and Thermal Overload Protection ................. 24
Thermal Data ................................................................................ 5
Thermal Considerations............................................................ 25
Thermal Resistance ...................................................................... 5
PCB Layout Considerations ...................................................... 28
ESD Caution .................................................................................. 5
Outline Dimensions ....................................................................... 30
Pin Configurations and Function Descriptions ........................... 6
Ordering Guide .......................................................................... 31
Noise Reduction of the Adjustable ADP7182 ............................ 24
Typical Performance Characteristics ............................................. 9
REVISION HISTORY
12/2016—Rev. H to Rev. I
Changes to Figure 77 ................................................................................. 21
Moved Theory of Operation/Enable Pin Operation Section.... 23
Changes to Enable Pin Operation Section .................................. 23
11/2016—Rev. G to Rev. H
Change to Thermal Considerations Section ............................... 25
Updated Outline Dimensions ....................................................... 30
Changes to Ordering Guide .......................................................... 31
6/2016—Rev. F to Rev. G
Changes to Figure 101 .................................................................... 28
3/2016—Rev. E to Rev. F
Changes to Figure 62 ...................................................................... 17
9/2014—Rev. D to Rev. E
Changes to Features and General Description Sections.............. 1
Changes to Figure 101 .................................................................... 28
Added Table 11 ............................................................................... 29
Changes to Ordering Guide .......................................................... 31
7/2014—Rev. C to Rev. D
Added 6-Lead LFCSP (Throughout) ............................................. 1
Added 6-Lead LFCSP Thermal Resistance Parameters............... 5
Added Figure 7, Figure 8, and Table 7 ........................................... 8
Added 6-Lead LFCSP θJA Values to Table 8; Added 6-Lead
LFCSP ΨJB Value to Table 10 ......................................................... 25
Added Figure 92, Figure 93, and Figure 94 ................................. 26
Changes to Thermal Characterization Parameter, ΨJB Section
and Added Figure 99 ...................................................................... 27
Added Figure 101 ........................................................................... 28
Added Figure 104, Outline Dimensions ...................................... 29
Changes to Ordering Guide .......................................................... 30
9/2013—Rev. B to Rev. C
Changes to Ordering Guide .......................................................... 28
6/2013—Rev. A to Rev. B
Changes to General Description .....................................................1
Updated Outline Dimensions ....................................................... 27
Changes to Ordering Guide .......................................................... 28
5/2013—Rev. 0 to Rev. A
Changed Start-Up Time VOUT = −5 V from 450 µs to 550 µs ......3
Changes to Figure 9 and Figure 12..................................................8
Changes to Figure 13.........................................................................9
Changes to Figure 19 and Figure 22 ............................................ 10
Changes to Figure 28...................................................................... 11
Changes to Figure 31 and Figure 34 ............................................ 12
Changes to Figure 37 and Figure 40 ............................................ 13
Changes to Figure 43...................................................................... 14
Added ADIsimPower Design Tool Section................................. 21
4/2013—Revision 0: Initial Version
Rev. I | Page 2 of 31
Data Sheet
ADP7182
SPECIFICATIONS
VIN = (VOUT − 0.5 V) or −2.7 V (whichever is greater), EN = VIN, IOUT = −10 mA, CIN = COUT = 2.2 µF, TJ = −40°C to +125°C for
minimum/maximum specifications, TA = 25°C for typical specifications, unless otherwise noted.
Table 1.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Symbol
VIN
IGND
SHUTDOWN CURRENT
IGND-SD
OUTPUT VOLTAGE ACCURACY
Fixed Output Voltage Accuracy
Adjustable Output Voltage
Accuracy
VOUT
VADJ
LINE REGULATION
LOAD REGULATION1
ADJ INPUT BIAS CURRENT
DROPOUT VOLTAGE2
∆VOUT/∆VIN
∆VOUT/∆IOUT
ADJI-BIAS
VDO
START-UP TIME3
tSTART-UP
CURRENT-LIMIT THRESHOLD4
THERMAL SHUTDOWN
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
EN THRESHOLD
Positive Rise
Negative Rise
Positive Fall
Negative Fall
INPUT VOLTAGE LOCKOUT
Start Threshold
Shutdown Threshold
Hysteresis
OUTPUT NOISE
ILIMIT
Test Conditions/Comments
IOUT = 0 µA
IOUT = −10 mA
IOUT = −200 mA
EN = GND
EN = GND, VIN = −2.7 V to −28 V
–1
–3
−1.208
−1 mA < IOUT < −200 mA, VIN = (VOUT − 0.5 V) to −28 V
VIN = (VOUT − 0.5 V) to −28 V
IOUT = −1 mA to −200 mA
−1 mA < IOUT < −200 mA, VIN = (VOUT − 0.5 V) to −28 V
IOUT = −10 mA
IOUT = −50 mA
IOUT = −200 mA
VOUT = −5 V
VOUT = −2.8 V
−1.184
−0.01
−230
TJ rising
VEN-POS-RISE
VEN-NEG-RISE
VEN-POS-FALL
VEN-NEG-FALL
VOUT = off to on (positive)
VOUT = off to on (negative)
VOUT = on to off (positive)
VOUT = on to off (negative)
Typ
−33
−100
−650
−2
IOUT = −10 mA, TA = 25°C
−1 mA < IOUT < −200 mA, VIN = (VOUT − 0.5 V) to −28 V
IOUT = −10 mA
TSSD
TSSD-HYS
−1.22
0.001
10
−25
−46
−185
550
375
−350
Max
−28
−53
−150
−850
−8
Unit
V
µA
µA
µA
µA
µA
+1
+2
−1.232
%
%
V
−1.244
+0.01
0.006
V
%/V
%/mA
nA
mV
mV
mV
µs
µs
mA
−70
−90
−360
−500
150
15
VSTART
VSHUTDOWN
OUTNOISE
Min
−2.7
1.2
−2.0
0.3
−0.55
−2.695
10 Hz to 100 kHz, VOUT = −1.5 V, VOUT = −3 V, and
VOUT = −5 V
10 Hz to 100 kHz, VOUT = −5 V, adjustable mode,
CNR = open, RNR = open, RFB1 = 147 kΩ, RFB2 = 13 kΩ
10 Hz to 100 kHz, VOUT = −5 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 147 kΩ, RFB2 = 13 kΩ
Rev. I | Page 3 of 31
°C
°C
−2.49
−2.34
150
18
−2.1
V
V
V
V
V
V
mV
µV rms
150
µV rms
33
µV rms
ADP7182
Parameter
POWER SUPPLY REJECTION RATIO
Data Sheet
Symbol
PSRR
Test Conditions/Comments
1 MHz, VIN = −4.3 V, VOUT = −3 V
1 MHz, VIN = −6 V, VOUT = −5 V
100 kHz, VIN = −4.3 V, VOUT = −3 V
100 kHz, VIN = −6 V, VOUT = −5 V
10 kHz, VIN = −4.3 V, VOUT = −3 V
10 kHz, VIN = −6 V, VOUT = −5 V
1 MHz, VIN = −16 V, VOUT = −15 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 13 kΩ, RFB2 = 147 kΩ
100 kHz, VIN = −16 V, VOUT = −15 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 13 kΩ, RFB2 = 147 kΩ
10 kHz, VIN = −16 V, VOUT = −15 V, adjustable mode,
CNR = 100 nF, RNR = 13 kΩ, RFB1 = 13 kΩ, RFB2 = 147 kΩ
Min
Typ
45
32
45
45
66
66
45
Max
Unit
dB
dB
dB
dB
dB
dB
dB
45
dB
66
dB
Based on an endpoint calculation using −1 mA and −200 mA loads. See Figure 10 for the typical load regulation performance for loads less than 1 mA.
Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only for output
voltages below −3 V.
3
Start-up time is defined as the time between the rising edge of EN to VOUT being at 90% of the nominal value.
4
Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a −5 V
output voltage is defined as the current that causes the output voltage to drop to 90% of −5 V, or −4.5 V.
1
2
INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
INPUT AND OUTPUT CAPACITANCE
Minimum Capacitance1
Capacitor Effective Series Resistance (ESR)
1
Symbol
Test Conditions/Comments
Min
Typ
CMIN
RESR
TA = −40°C to +125°C
TA = −40°C to +125°C
1.5
0.001
2.2
Max
Unit
0.2
µF
Ω
The minimum input and output capacitance must be greater than 1.5 µF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended;
Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. I | Page 4 of 31
Data Sheet
ADP7182
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
EN to VIN
ADJ to GND
Storage Temperature Range
Operating Junction Temperature Range
Operating Ambient Temperature Range
Soldering Conditions
Rating
+0.3 V to −30 V
0.3 V to VIN
5 V to VIN
+30 V to −0.3 V
+0.3 V to VOUT
−65°C to +150°C
−40°C to +125°C
−40°C to +85°C
JEDEC J-STD-020
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP7182 can be damaged when the junction
temperature limits are exceeded. Monitoring ambient temperature
does not guarantee that junction temperature (TJ) is within the
specified temperature limits. In applications with high power
dissipation and poor thermal resistance, the maximum ambient
temperature may have to be derated.
In applications with moderate power dissipation and low printed
circuit board (PCB) thermal resistance, the maximum ambient
temperature can exceed the maximum limit as long as the junction
temperature is within specification limits. The TJ of the device is
dependent on the ambient temperature (TA), the power dissipation
of the device (PD), and the junction-to-ambient thermal resistance
of the package (θJA).
Maximum TJ is calculated from the TA and PD using the formula
In applications where high maximum power dissipation exists,
close attention to thermal board design is required. The value of
θJA can vary, depending on PCB material, layout, and
environmental conditions. The specified values of θJA are based
on a 4-layer, 4 in. × 3 in. circuit board. See JESD51-7 and
JESD51-9 for detailed information on the board construction. For
additional information, see the AN-617 Application Note,
MicroCSP™ Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
with units of °C/W. ΨJB of the package is based on modeling and
calculation using a 4-layer board. The JESD51-12, Guidelines for
Reporting and Using Electronic Package Thermal Information, states
that thermal characterization parameters are not the same as
thermal resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation from
the package, factors that make ΨJB more useful in real-world
applications. Maximum junction temperature is calculated from
the board temperature (TB) and power dissipation using the
formula
TJ = TB + (PD × ΨJB)
See JESD51-8 and JESD51-12 for more detailed information
about ΨJB.
THERMAL RESISTANCE
θJA, θJC, and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
8-Lead LFCSP
6-Lead LFCSP
5-Lead TSOT
ESD CAUTION
TJ = TA + (PD × θJA)
Junction-to-ambient thermal resistance (θJA) of the package is
based on modeling and calculation using a 4-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout.
Rev. I | Page 5 of 31
θJA
50.2
68.9
170
θJC
31.7
42.29
Not applicable
ΨJB
18.2
44.1
43
Unit
°C/W
°C/W
°C/W
ADP7182
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
5
GND 1
VOUT
VIN 2
TOP VIEW
(Not to Scale)
EN 3
4
EN 3
NC
NOTES
1. NC = NO CONNECT. DO NOT
CONNECT TO THIS PIN.
VOUT
4
ADJ
TOP VIEW
(Not to Scale)
10703-003
VIN 2
5
ADP7182
ADP7182
10703-004
GND 1
Figure 4. 5-Lead TSOT Pin Configuration, Adjustable Output Voltage
Figure 3. 5-Lead TSOT Pin Configuration, Fixed Output Voltage
Table 5. 5-Lead TSOT Pin Function Descriptions
TSOT Pin No.
Fixed Output Voltage Adjustable Output Voltage
1
1
2
2
Mnemonic
GND
VIN
3
3
EN
4
Not applicable
5
Not applicable
4
5
NC
ADJ
VOUT
Description
Ground.
Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater
capacitor.
Drive EN 2 V above or below ground to enable the regulator, or
drive EN to ground to turn off the regulator. For automatic startup,
connect EN to VIN.
No Connect. Do not connect to this pin.
Adjustable Input. An external resistor divider sets the output voltage.
Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or
greater capacitor.
Rev. I | Page 6 of 31
Data Sheet
ADP7182
ADP7182
VOUT 2
NC 3
EN 4
TOP VIEW
(Not to Scale)
EXPOSED PAD
8 VIN
VOUT 1
7 VIN
VOUT 2
6 GND
ADJ 3
5 NC
EN 4
10703-005
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
Figure 5. 8-Lead LFCSP Pin Configuration, Fixed Output Voltage
8 VIN
ADP7182
7 VIN
TOP VIEW
(Not to Scale)
6 GND
EXPOSED PAD
5 NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
10703-006
VOUT 1
Figure 6. 8-Lead LFCSP Pin Configuration, Adjustable Output Voltage
Table 6. 8-Lead LFCSP Pin Function Descriptions
LFCSP Pin No.
Fixed Output Voltage Adjustable Output Voltage
1, 2
1, 2
Mnemonic
VOUT
Not applicable
3
4
3
Not applicable
4
ADJ
NC
EN
5
6
7, 8
5
6
7, 8
NC
GND
VIN
9
9
EPAD
Description
Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or
greater capacitor.
Adjustable Input. An external resistor divider sets the output voltage.
No Connect. Do not connect to this pin.
Drive EN 2 V above or below ground to enable the regulator, or drive
EN to ground to turn off the regulator. For automatic startup,
connect EN to VIN.
No Connect. Do not connect to this pin.
Ground.
Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater
capacitor.
Exposed pad. The exposed pad on the bottom of the LFCSP package
enhances thermal performance and is electrically connected to VIN
inside the package. The exposed pad must be connected to the VIN
plane on the board for proper operation. Because this is a negative
voltage regulator, VIN is the most negative potential in the circuit.
Rev. I | Page 7 of 31
ADP7182
Data Sheet
TOP VIEW
(Not to Scale)
NC 2
EXPOSED PAD
EN 3
VOUT 1
6 VIN
ADJ 2
5 GND
EN 3
4 NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
Figure 7. 6-Lead LFCSP Pin Configuration, Fixed Output Voltage
ADP7182
TOP VIEW
(Not to Scale)
EXPOSED PAD
6 VIN
5 GND
4 NC
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
2. THE EXPOSED PAD ON THE BOTTOM OF THE LFCSP PACKAGE ENHANCES
THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN
INSIDE THE PACKAGE. THE EXPOSED PAD MUST BE CONNECTED TO THE
VIN PLANE ON THE BOARD FOR PROPER OPERATION. BECAUSE THIS IS A
NEGATIVE VOLTAGE REGULATOR, VIN IS THE MOST NEGATIVE POTENTIAL
IN THE CIRCUIT.
10703-106
ADP7182
10703-107
VOUT 1
Figure 8. 6-Lead LFCSP Pin Configuration, Adjustable Output Voltage
Table 7. 6-Lead LFCSP Pin Function Descriptions
LFCSP Pin No.
Fixed Output Voltage Adjustable Output Voltage
1
1
Mnemonic
VOUT
Not applicable
3
2
3
ADJ
EN
2, 4
5
6
4
5
6
NC
GND
VIN
7
7
EPAD
Description
Regulated Output Voltage. Bypass VOUT to GND with a 2.2 µF or
greater capacitor.
Adjustable Input. An external resistor divider sets the output voltage.
Drive EN 2 V above or below ground to enable the regulator, or drive
EN to ground to turn off the regulator. For automatic startup,
connect EN to VIN.
No Connect. Do not connect to this pin.
Ground.
Regulator Input Supply. Bypass VIN to GND with a 2.2 µF or greater
capacitor.
Exposed pad. The exposed pad on the bottom of the LFCSP package
enhances thermal performance and is electrically connected to VIN
inside the package. The exposed pad must be connected to the VIN
plane on the board for proper operation. Because this is a negative
voltage regulator, VIN is the most negative potential in the circuit.
Rev. I | Page 8 of 31
Data Sheet
ADP7182
TYPICAL PERFORMANCE CHARACTERISTICS
VIN = −3.5 V, VOUT = −3 V, IOUT = −10 mA, CIN = COUT = 2.2 µF, TA = 25°C, unless otherwise noted.
–2.980
VOUT (V)
–2.985
0
= –100µA
= –1mA
= –10mA
= –50mA
= –100mA
= –200mA
–100
–2.990
–2.995
–3.000
–3.005
–200
–300
–400
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
–500
–600
–3.010
= –100µA
= –1mA
= –10mA
= –50mA
= –100mA
= –200mA
–700
–3.015
–40
–5
25
85
–800
10703-007
–3.020
125
JUNCTION TEMPERATURE (°C)
–40
–5
25
85
10703-010
–2.975
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
GROUND CURRENT (µA)
–2.970
125
JUNCTION TEMPERATURE (°C)
Figure 9. Output Voltage (VOUT) vs. Junction Temperature (TJ)
Figure 12. Ground Current vs. Junction Temperature (TJ)
–2.95
0
–2.96
–100
GROUND CURRENT (µA)
–2.97
VOUT (V)
–2.98
–2.99
–3.00
–3.01
–3.02
–200
–300
–400
–500
–600
–3.03
–150
–100
–50
0
–800
–250
10703-008
50
ILOAD (mA)
–50
0
50
0
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
GROUND CURRENT (µA)
–100
–3.00
–3.05
–200
–300
–400
–500
–600
–700
–25
–20
–15
–10
–5
VIN (V)
0
10703-009
VOUT (V)
–100
Figure 13. Ground Current vs. Load Current (ILOAD)
–2.90
–3.10
–30
–150
ILOAD (mA)
Figure 10. Output Voltage (VOUT) vs. Load Current (ILOAD)
–2.95
–200
Figure 11. Output Voltage (VOUT) vs. Input Voltage (VIN)
–800
–30
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–25
–20
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–15
–10
–5
VIN (V)
Figure 14. Ground Current vs. Input Voltage (VIN)
Rev. I | Page 9 of 31
0
10703-012
–3.05
–200
10703-011
–700
–3.04
ADP7182
Data Sheet
0
0
–0.5
–200
GROUND CURRENT (µA)
–2.0
–2.5
–3.0
–3.5
–4.0
–4.5
–5.0
–50
VIN = –2.7V
VIN = –3.0V
VIN = –4.0V
VIN = –5.0V
VIN = –8.0V
VIN = –28.0V
–25
0
–400
–600
–800
–1000
25
50
75
100
125
–1200
–3.4
TEMPERATURE (°C)
–3.2
–3.0
–2.8
Figure 18. Ground Current vs. Input Voltage (VIN) in Dropout
–4.90
0
–4.92
–20
–4.94
–40
–4.96
–60
–4.98
–100
–5.00
–5.02
–120
–5.04
–140
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–5.06
–160
–5.08
–180
–5.10
10
100
1000
ILOAD (mA)
–2.60
–2.65
–2.70
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
25
85
125
–5.000
= –5mA
= –10mA
= –25mA
= –50mA
= –100mA
= –200mA
–5.005
–5.010
–5.015
VOUT (V)
–2.75
–2.80
–2.85
–5.020
–5.025
–5.030
–5.035
–2.95
–5.040
–3.00
–5.045
–3.2
–3.0
–2.8
VIN (V)
10703-015
–2.90
–3.05
–3.4
–5
JUNCTION TEMPERATURE (°C)
Figure 19. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −5 V
Figure 16. Dropout Voltage vs. Load Current (ILOAD)
–2.55
–40
–5.050
–200
–150
–100
–50
0
ILOAD (mA)
Figure 20. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −5 V
Figure 17. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout
Rev. I | Page 10 of 31
10703-018
1
10703-014
–200
10703-017
–80
VOUT (V)
DROPOUT VOLTAGE (mV)
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
VIN (V)
Figure 15. Shutdown Current vs. Temperature at Various Input Voltages
VOUT (V)
ILOAD = –5mA
ILOAD = –10mA
ILOAD = –25mA
10703-016
–1.5
10703-013
SHUTDOWN CURRENT (µA)
–1.0
Data Sheet
ADP7182
0
–4.97
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–5.01
–300
–400
–500
–600
–5.02
–700
–25
–20
–15
–10
–5
0
VIN (V)
–800
–30
10703-019
–5.03
–30
–100
–20
–200
–40
DROPOUT VOLTAGE (mV)
–300
–400
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–10
–5
0
–60
–80
–100
–120
–140
–700
–40
–5
25
85
–160
10703-020
–800
125
JUNCTION TEMPERATURE (°C)
1
10
100
1000
ILOAD (mA)
Figure 25. Dropout Voltage vs. Load Current (ILOAD), VOUT = −5 V
Figure 22. Ground Current vs. Junction Temperature (TJ), VOUT = −5 V
0
–4.60
–100
–4.65
–4.70
–200
ILOAD = –5mA
ILOAD = –10mA
ILOAD = –25mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–4.75
VOUT (V)
–300
–400
–500
–600
–4.85
–4.95
–700
–800
–200
–4.80
–4.90
–5.00
–150
–100
–50
0
ILOAD (mA)
Figure 23. Ground Current vs. Load Current (ILOAD), VOUT = −5 V
–5.05
–5.4
10703-021
GROUND CURRENT (µA)
–15
10703-023
GROUND CURRENT (µA)
0
–600
–20
Figure 24. Ground Current vs. Input Voltage (VIN), VOUT = −5 V
0
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–25
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
VIN (V)
Figure 21. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −5 V
–500
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
10703-022
–5.00
–200
–5.2
–5.0
VIN (V)
–4.8
10703-024
VOUT (V)
–4.99
–100
GROUND CURRENT (µA)
–4.98
Figure 26. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout, VOUT = −5 V
Rev. I | Page 11 of 31
ADP7182
Data Sheet
0
–1.780
–200
–1.790
VOUT (V)
–600
–800
–1.805
–5.2
–4.8
–5.0
VIN (V)
–1.810
–30
–20
–15
0
–5
–10
Figure 30. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.8 V
–1.770
0
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= –100µA
= –1mA
= –10mA
= –50mA
= –100mA
= –200mA
–100
GROUND CURRENT (µA)
–1.780
–25
VIN (V)
Figure 27. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = −5 V
–1.775
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
10703-028
–1600
–5.4
–1.800
ILOAD = –5mA
ILOAD = –10mA
ILOAD = –25mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–1.785
–1.790
–1.795
–1.800
–200
–300
–400
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–500
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–600
–1.805
–40
–5
25
85
–700
10703-026
–1.810
125
JUNCTION TEMPERATURE (°C)
Figure 28. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −1.8 V
–40
–5
25
85
10703-029
–1200
–1400
VOUT (V)
–1.795
–1000
10703-025
GROUND CURRENT (µA)
–1.785
–400
125
JUNCTION TEMPERATURE (°C)
Figure 31. Ground Current vs. Junction Temperature (TJ), VOUT = −1.8 V
0
–1.790
–100
GROUND CURRENT (µA)
VOUT (V)
–1.795
–1.800
–1.805
–200
–300
–400
–500
–150
–100
ILOAD (mA)
–50
0
Figure 29. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −1.8 V
Rev. I | Page 12 of 31
–700
–200
–150
–100
–50
0
ILOAD (mA)
Figure 32. Ground Current vs. Load Current (ILOAD), VOUT = −1.8 V
10703-030
–1.810
–200
10703-027
–600
Data Sheet
ADP7182
0
–1.20
–100
–400
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–500
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–1.22
–1.23
–1.24
–600
–25
–20
–15
–10
–5
0
VIN (V)
–1.25
–30
10703-031
–700
–30
Figure 33. Ground Current vs. Input Voltage (VIN), VOUT = −1.8 V
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–20
–25
–15
–10
0
–5
VIN (V)
10703-034
–300
VOUT (V)
GROUND CURRENT (µA)
–1.21
–200
Figure 36. Output Voltage (VOUT) vs. Input Voltage (VIN), VOUT = −1.22 V
0
–1.20
–100
GROUND CURRENT (µA)
–1.22
–1.23
–1.25
–40
= –100µA
= –1mA
= –10mA
= –50mA
= –100mA
= –200mA
–5
–200
–300
–400
–500
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–600
25
85
125
–700
JUNCTION TEMPERATURE (°C)
Figure 34. Output Voltage (VOUT) vs. Junction Temperature (TJ), VOUT = −1.22 V
–40
–5
25
85
10703-035
–1.24
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
10703-032
VOUT (V)
–1.21
125
JUNCTION TEMPERATURE (°C)
Figure 37. Ground Current vs. Junction Temperature (TJ), VOUT = −1.22 V
0
–1.20
–100
GROUND CURRENT (µA)
VOUT (V)
–1.21
–1.22
–1.23
–200
–300
–400
–500
–1.24
–150
–100
ILOAD (mA)
–50
0
Figure 35. Output Voltage (VOUT) vs. Load Current (ILOAD), VOUT = −1.22 V
Rev. I | Page 13 of 31
–700
–200
–150
–100
–50
0
ILOAD (mA)
Figure 38. Ground Current vs. Load Current (ILOAD), VOUT = −1.22 V
10703-036
–1.25
–200
10703-033
–600
ADP7182
Data Sheet
0
–14.80
–14.85
–100
–14.95
–400
–15.00
–15.05
–15.10
–15.15
–500
–15.20
–700
–30
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–20
–25
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–15
–15.25
0
–5
–10
VIN (V)
–15.30
–30
10703-037
–600
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–25
–20
10703-040
–300
VOUT (V)
GROUND CURRENT (µA)
–14.90
–200
–15
VIN (V)
Figure 39. Ground Current vs. Input Voltage (VIN), VOUT = −1.22 V
Figure 42. Output Voltage (VOUT) vs. Input Voltage (VIN),
Adjustable Output Voltage, VOUT = −15 V
–14.80
0
–14.85
–100
GROUND CURRENT (µA)
–14.90
–15.00
–15.05
–15.10
–15.20
–15.25
–15.30
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
= –100µA
= –1mA
= –10mA
= –50mA
= –100mA
= –200mA
–40
–5
–200
–300
–400
–500
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–600
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
–700
25
85
125
–800
JUNCTION TEMPERATURE (°C)
–40
–5
25
85
10703-041
–15.15
10703-038
VOUT (V)
–14.95
125
JUNCTION TEMPERATURE (°C)
Figure 40. Output Voltage (VOUT) vs. Junction Temperature (TJ),
Adjustable Output Voltage, VOUT = −15 V
Figure 43. Ground Current vs. Junction Temperature (TJ),
Adjustable Output Voltage, VOUT = −15 V
0
–14.80
–14.85
–100
GROUND CURRENT (µA)
–14.90
–15.00
–15.05
–15.10
–15.15
–200
–300
–400
–500
–600
–15.20
–15.30
–200
–150
–100
–50
ILOAD (mA)
0
Figure 41. Output Voltage (VOUT) vs. Load Current (ILOAD),
Adjustable Output Voltage, VOUT = −15 V
–800
–200
–150
–100
–50
ILOAD (mA)
Figure 44. Ground Current vs. Load Current (ILOAD),
Adjustable Output Voltage, VOUT = −15 V
Rev. I | Page 14 of 31
0
10703-042
–700
–15.25
10703-039
VOUT (V)
–14.95
ADP7182
0
–100
–200
–200
–400
GROUND CURRENT (µA)
0
–300
–400
–500
ILOAD = –100µA
ILOAD = –1mA
ILOAD = –10mA
–600
–700
ILOAD = –50mA
ILOAD = –100mA
ILOAD = –200mA
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
–600
–800
–1000
–1200
–25
–20
–15
VIN (V)
–1600
–15.0
Figure 45. Ground Current vs. Input Voltage (VIN),
Adjustable Output Voltage, VOUT = −15 V
–14.8
–14.6
–14.4
–14.2
10703-046
–800
–30
–14.0
VIN (V)
Figure 48. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = −15 V
0
0
–10
–20
–20
–40
ILOAD
ILOAD
ILOAD
ILOAD
= –200mA
= –100mA
= –10mA
= –1mA
100
1k
–30
PSRR (dB)
DROPOUT VOLTAGE (mV)
= –5mA
= –10mA
= –25mA
= –50mA
= –100mA
= –200mA
–1400
10703-043
GROUND CURRENT (µA)
Data Sheet
–60
–80
–40
–50
–60
–70
–100
–80
–120
10
100
1000
ILOAD (mA)
–100
10703-044
1
10
–14.70
=
=
=
=
=
=
0
–10mA
–10mA
–25mA
–50mA
–100mA
–200mA
–10
–20
PSRR (dB)
–14.85
–14.90
–14.95
ILOAD
ILOAD
ILOAD
ILOAD
= –200mA
= –100mA
= –10mA
= –1mA
100
1k
–40
–50
–60
–70
–15.00
–80
–15.05
–15.10
–15.0
10M
–30
–14.80
–90
–14.9
–14.8
–14.7
–14.6
–14.5
VIN (V)
10703-045
VOUT (V)
–14.75
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
ILOAD
1M
Figure 47. Output Voltage (VOUT) vs. Input Voltage (VIN) in Dropout,
Adjustable Output Voltage, VOUT = −15 V
–100
10
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 50. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.22 V vs. Different Load Currents (ILOAD), VIN = −5.7 V
Rev. I | Page 15 of 31
10703-048
–14.60
100k
Figure 49. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.22 V vs. Different Load Currents (ILOAD), VIN = −2.7 V
Figure 46. Dropout Voltage vs. Load Current (ILOAD),
Adjustable Output Voltage, VOUT = −15 V
–14.65
10k
FREQUENCY (Hz)
10703-047
–90
–140
ADP7182
–10
–20
PSRR (dB)
–30
–40
–50
–70
2.0
2.5
3.0
3.5
4.0
4.5
5.0
Figure 51. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = −1.22 V, Load Current (ILOAD) = −200 mA
0
–10
–20
ILOAD
ILOAD
ILOAD
ILOAD
–80
1.0
0
= –200mA
= –100mA
= –10mA
= –1mA
–10
–20
–40
–40
PSRR (dB)
–30
–50
–60
–70
–80
–90
–90
–100
–100
10k
100k
1M
10M
FREQUENCY (Hz)
10
0
–20
ILOAD
ILOAD
ILOAD
ILOAD
3.5
4.0
ILOAD
ILOAD
ILOAD
ILOAD
= –200mA
= –100mA
= –10mA
= –1mA
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 52. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.8 V vs. Different Load Currents (ILOAD), VIN = −2.8 V
–10
3.0
–60
–80
1k
2.5
–50
–70
100
2.0
Figure 54. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = −1.8 V, Load Current (ILOAD) = −200 mA
–30
10
1.5
HEADROOM VOLTAGE (V)
10703-050
Figure 55. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −3 V vs. Different Load Currents (ILOAD), VIN = −4.0 V
0
= –200mA
= –100mA
= –10mA
= –1mA
–10
–20
–30
ILOAD = –200mA
ILOAD = –100mA
ILOAD = –10mA
ILOAD = –1mA
–30
PSRR (dB)
–40
–50
–60
–70
–40
–50
–60
–70
–80
–80
–90
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
10703-051
–90
–100
Figure 53. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −1.8 V vs. Different Load Currents (ILOAD), VIN = −5.5 V
–100
10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 56. Power Supply Rejection Ratio (PSRR) vs. Frequency,
VOUT = −3 V vs. Different Load Currents (ILOAD), VIN = −5.5 V
Rev. I | Page 16 of 31
10703-054
PSRR (dB)
–50
–70
HEADROOM VOLTAGE (V)
PSRR (dB)
–40
–60
1.5
= 100Hz
= 1kHz
= 10kHz
= 100kHz
= 1MHz
= 10MHz
–30
–60
–80
1.0
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
–10
10703-049
PSRR (dB)
–20
0
= 100Hz
= 1kHz
= 10kHz
= 100kHz
= 1MHz
= 10MHz
10703-052
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
10703-053
0
Data Sheet
Data Sheet
0
ADP7182
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
–10
–20
0
= 100Hz
= 1kHz
= 10kHz
= 100kHz
= 1MHz
= 10MHz
–20
PSRR (dB)
–40
–50
–60
= 100Hz
= 1kHz
= 10kHz
= 100kHz
= 1MHz
= 10MHz
–30
–40
–50
–60
–70
–70
–80
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
HEADROOM VOLTAGE (V)
0
ILOAD
ILOAD
ILOAD
ILOAD
–20
0
0.25
0.50
0.75
1.00
1.25
1.50
1.75
2.00
HEADROOM VOLTAGE (V)
Figure 60. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
Adjustable Output Voltage, VOUT = −15 V with Noise Reduction Network,
Load Current (ILOAD) = −200 mA
Figure 57. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = −3 V, Load Current (ILOAD) = −200 mA
–10
–80
10703-055
–90
10703-058
PSRR (dB)
–30
1000
= –200mA
= –100mA
= –10mA
= –1mA
NOISE (µV rms)
–30
PSRR (dB)
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
FREQUENCY
–10
–40
–50
–60
–70
VOUT = –5V
VOUT = –1.8V
VOUT = –15V ADJ NR
VOUT = –3V
VOUT = –1.2V
VOUT = –15V ADJ
100
10
–80
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 58. Power Supply Rejection Ratio (PSRR) vs. Frequency,
Adjustable Output Voltage, VOUT = −15 V vs. Different Load Currents (ILOAD),
VIN = −15.5 V with Noise Reduction Network
–20
ILOAD
ILOAD
ILOAD
ILOAD
0.1
–40
–50
–60
–70
–80
1
10
100
1000
Figure 61. RMS Noise vs. Load Current (ILOAD), Various Output Voltages
100k
= –200mA
= –100mA
= –10mA
= –1mA
–30
PSRR (dB)
0.01
LOAD CURRENT (mA)
NOISE SPECTRAL DENSITY (nV Hz)
0
–10
1
0.001
10703-056
10
10703-059
–90
–100
VOUT = –5V
VOUT = –1.8V
VOUT = –15V ADJ NR
VOUT = –3V
VOUT = –1.2V
VOUT = –15V ADJ
10k
1k
100
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
Figure 59. Power Supply Rejection Ratio (PSRR) vs. Frequency,
Adjustable Output Voltage, VOUT = −15 V vs. Different Load Currents (ILOAD),
VIN = −16.5 V with Noise Reduction Network
Rev. I | Page 17 of 31
1
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 62. Noise Spectral Density, Various Output Voltages
10703-060
10
10703-057
–90
–100
ADP7182
Data Sheet
1
1
T
T
VOUT
2
VOUT
2
VIN
CH2 2mV
B
W
M10µs
A CH3
T 10.00%
2.52V
CH1 500mV BW
Figure 63. Line Transient Response, 500 mV Step, VOUT = −1.22 V, ILOAD = −200 mA
CH2 5mV
B
W
M2µs
A CH3
T 10.00%
1.60V
10703-064
CH1 500mV BW
10703-061
VIN
Figure 66. Line Transient Response, 500 mV Step, VOUT = −1.8 V, ILOAD = −10 mA
1
1
T
T
VOUT
2
VIN
VIN
VOUT
CH2 1mV
B
W
M10µs
A CH3
T 10.00%
2.52V
CH1 1V BW
Figure 64. Line Transient Response, 500 mV Step, VOUT = −1.22 V, ILOAD = −10 mA
CH2 5mV
B
W
M4µs
A CH3
T 10.00%
1.60V
10703-065
CH1 500mV BW
10703-062
2
Figure 67. Line Transient Response, 500 mV Step, VOUT = −3 V, ILOAD = −200 mA
1
1
T
T
VOUT
2
VIN
VIN
CH2 5mV
B
W
A CH3
M2µs
T 10.00%
1.60V
10703-063
CH1 500mV BW
CH1 1V BW
Figure 65. Line Transient Response, 500 mV Step, VOUT = −1.8 V, ILOAD = −200 mA
CH2 5mV
B
W
M4µs
A CH3
T 10.00%
1.60V
10703-066
VOUT
2
Figure 68. Line Transient Response, 500 mV Step, VOUT = −3 V, ILOAD = −10 mA
Rev. I | Page 18 of 31
Data Sheet
ADP7182
1
T
T
1
VIN
VOUT
VIN
VOUT
CH1 1V BW
CH2 10mV
B
W
M2µs
A CH3
T 10.00%
2.02V
10703-067
2
CH1 1V BW
CH2 2mV
B
M10µs
A CH3
T 10.00%
W
2.52V
10703-070
2
Figure 72. Line Transient Response, 500 mV Step, VOUT = −15 V,
Noise Reduction Network, ILOAD = −10 mA
Figure 69. Line Transient Response, 500 mV Step, VOUT = −5 V, ILOAD = −200 mA
1
T
T
VOUT
2
VOUT
2
1
VIN
CH2 5mV
B
W
M2µs
A CH3
T 10.00%
2.02V
CH1 100mA BW CH2 50mV
Figure 70. Line Transient Response, 500 mV Step, VOUT = −5 V, ILOAD = −10 mA
W
M40µs A CH1
T 10.40%
–122mA
Figure 73. Load Transient Response, VOUT = −1.22 V, ILOAD = −1 mA to −200 mA,
Load Step = 1 A/µs
T
T
1
B
10703-071
CH1 1V BW
10703-068
LOAD CURRENT
VIN
VOUT
2
1
VOUT
2
CH2 2mV
B
W
A CH3
M4µs
T 10.00%
2.52V
Figure 71. Line Transient Response, 500 mV Step, VOUT = −15 V,
Noise Reduction Network, ILOAD = −200 mA
CH1 100mA BW
CH2 50mV
B
W
M40µs A CH1
T 10.60%
–122mA
10703-072
CH1 1V BW
10703-069
LOAD CURRENT
Figure 74. Load Transient Response, VOUT = −3 V, ILOAD = −1 mA to −200 mA,
Load Step = 1 A/µs
Rev. I | Page 19 of 31
ADP7182
Data Sheet
T
T
VOUT
VOUT
2
2
1
1
LOAD CURRENT
B
W M10µs A CH1
T 10.00%
–122mA
CH1 100mA BW
Figure 75. Load Transient Response, VOUT = −5 V, ILOAD = −1 mA to −200 mA,
Load Step = 1 A/µs
CH2 50mV
B
W
M40µs A CH1
T 10.00%
–122mA
10703-074
CH2 50mV
10703-073
CH1 100mA BW
LOAD CURRENT
Figure 76. Load Transient Response, VOUT = −15 V, ILOAD = −1 mA to −200 mA,
Load Step = 1 A/µs, Noise Reduction Network
Rev. I | Page 20 of 31
Data Sheet
ADP7182
THEORY OF OPERATION
The ADP7182 is a low quiescent current, LDO linear regulator
that operates from −2.7 V to −28 V and can provide up to −200 mA
of output current. Drawing a low −650 μA of quiescent current
(typical) at full load makes the ADP7182 ideal for battery-powered
portable equipment. Maximum shutdown current consumption
is −8 μA at room temperature.
Optimized for use with small 2.2 μF ceramic capacitors, the
ADP7182 provides excellent transient performance.
EN
SHORT
CIRCUIT
THERMAL
PROTECT
The ADP7182 is available in a fixed output voltage and an
adjustable mode version with an output voltage that can be set
to between −1.22 V and −27 V by an external voltage divider. The
output voltage can be set according to
−VOUT = −1.22 V (1 + RFB1/RFB2)
RFB2 must be less than 120 kΩ to minimize the output voltage errors
due to the leakage current of the ADJ pin. The error voltage caused
by the ADJ pin leakage current is the parallel combination of RFB1
and RFB2 times the ADJ pin leakage current.
GND
VREG
ADJUSTABLE MODE OPERATION
REFERENCE
For example, when RFB1 = RFB2 = 120 kΩ, the output voltage is
−2.44 V and the error due to the typical ADJ pin leakage current
(10 nA) is 60 kΩ times 10 nA, or 6 mV. This example results in
an output voltage error of 0.245%.
VOUT
VIN
10703-075
SHUTDOWN
Figure 77. Fixed Output Voltage Internal Block Diagram
The addition of a small capacitor (~100 pF) in parallel with
RFB1 can improve the stability of the ADP7182. Larger values of
capacitance also reduce the noise and improve PSRR (see the
Noise Reduction of the Adjustable section).
GND
SHORT
CIRCUIT
THERMAL
PROTECT
–1.22V
REFERENCE
CIN
2.2µF
COUT
2.2µF
GND
EN
SHUTDOWN
ADJ
VIN = –3V
VOUT
10703-076
ON
VIN
OFF
–2V
Figure 78. Adjustable Output Voltage Internal Block Diagram
VIN
2V
0V
VOUT
RFB2
120kΩ
RFB1
120kΩ
VOUT = –2.44V
ADP7182
EN
ADJ
ON
Figure 79. Setting Adjustable Output Voltage
Internally, the ADP7182 consists of a reference, an error amplifier,
a feedback voltage divider, and an NMOS pass transistor. Output
current is delivered via the NMOS pass transistor, which is
controlled by the error amplifier. The error amplifier compares
the reference voltage with the feedback voltage from the output
and amplifies the difference. If the feedback voltage is more positive
than the reference voltage, the gate of the NMOS transistor is
pulled toward GND, allowing more current to pass and increasing
the output voltage. If the feedback voltage is more negative than
the reference voltage, the gate of the NMOS transistor is pulled
toward −VIN, allowing less current to pass and decreasing the
output voltage.
The ESD protection devices are shown in the block diagram as
Zener diodes (see Figure 77 and Figure 78).
Rev. I | Page 21 of 31
10703-077
VREG
ADP7182
Data Sheet
APPLICATIONS INFORMATION
CAPACITOR SELECTION
Output Capacitor
The ADP7182 is designed for operation with small space-saving
ceramic capacitors; however, it functions with most commonly
used capacitors as long as care is taken with regard to the ESR
value. The ESR of the output capacitor affects the stability of the
LDO control loop. A minimum of 2.2 µF capacitance with an
ESR of 0.2 Ω or less is recommended to ensure the stability of
the ADP7182. Transient response to changes in load current is
also affected by output capacitance. Using a larger value of output
capacitance improves the transient response of the ADP7182
to large changes in load current. Figure 80 shows the transient
responses for an output capacitance value of 2.2 µF.
Figure 81 depicts the capacitance vs. voltage bias characteristics
of an 0805, 2.2 µF, 25 V, X5R capacitor. The voltage stability of a
capacitor is strongly influenced by the capacitor size and voltage
rating. In general, a capacitor in a larger package or higher voltage
rating exhibits better stability. The temperature variation of the
X5R dielectric is ~ ±15% over the −40°C to +85°C temperature
range and is not a function of package or voltage rating.
2.5
2.0
1.5
1.0
0.5
0
T
0
5
10
15
20
25
DC BIAS (V)
30
10703-079
The ADP7182 is supported by the ADIsimPower™ design tool set.
ADIsimPower is a collection of tools that produce complete power
designs optimized for a specific design goal. The tools enable
the user to generate a full schematic, bill of materials, and calculate
performance in minutes. ADIsimPower can optimize designs for
cost, area, efficiency, and devices count taking into consideration
the operating conditions and limitations of the IC and all real
external components. For more information about, and to obtain
ADIsimPower design tools, visit www.analog.com/ADIsimPower.
Capacitors must have a dielectric adequate to ensure the minimum
capacitance over the necessary temperature range and dc bias
conditions. X5R or X7R dielectrics with a voltage rating of 25 V
or 50 V are recommended. Due to their poor temperature and dc
bias characteristics, Y5V and Z5U dielectrics are not
recommended.
CAPACITANCE (µF)
ADIsimPower DESIGN TOOL
Figure 81. Capacitance vs. DC Bias Characteristics
VOUT
Use Equation 1 to determine the worst-case capacitance accounting
for capacitor variation over temperature, component tolerance,
and voltage.
2
CEFF = CBIAS × (1 − TEMPCO) × (1 − TOL)
1
where:
CBIAS is the effective capacitance at the operating voltage, which
is −3 V for this example.
TEMPCO is the worst-case capacitor temperature coefficient.
TOL is the worst-case component tolerance.
CH2 50mV
B
W
M40µs A CH1
T 10.60%
–122mA
10703-078
LOAD CURRENT
CH1 100mA BW
(1)
Figure 80. Output Transient Response, COUT = 2.2 µF
Input Bypass Capacitor
Connecting a 2.2 µF capacitor from VIN to GND reduces the
circuit sensitivity to PCB layout, especially when long input
traces or high source impedance are encountered. When more
than 2.2 µF of output capacitance is required, increase the input
capacitance to match it.
Input and Output Capacitor Properties
As long as they meet the minimum capacitance and maximum
ESR requirements, any good quality ceramic capacitors can be
used with the ADP7182. Ceramic capacitors are manufactured
with a variety of dielectrics, each with different behavior over
temperature and applied voltage.
In this example, the worst-case temperature coefficient (TEMPCO)
over −40°C to +85°C is 15% for an X5R dielectric. The tolerance
of the capacitor (TOL) is 10%, and the CBIAS is 2.08 µF at a 3 V bias,
as shown in Figure 81.
Substituting these values in Equation 1 yields
CEFF = 2.08 μF × (1 − 0.15) × (1 − 0.1) = 1.59 µF
Therefore, the capacitor chosen in this example meets the
minimum capacitance requirement of the LDO over temperature
and tolerance at the chosen output voltage of −3 V.
To guarantee the performance of the ADP7182, it is imperative
that the effects of dc bias, temperature, and tolerances on the
behavior of the capacitors be evaluated for each application.
Rev. I | Page 22 of 31
Data Sheet
ADP7182
ENABLE PIN OPERATION
T
EN
The ADP7182 uses the EN pin to enable and disable the VOUT
pin under normal operating conditions. When EN is at ±2 V with
respect to GND, VOUT turns on, and when EN is at 0 V, VOUT
turns off. For automatic startup, EN can be connected to VIN.
When the device is disabled, a ~220 kΩ resistor connects to the
VOUT pin, which pulls the VOUT pin up to GND.
1
VOUT
2
The ADP7182 provides a dual polarity enable pin (EN) that turns
on the LDO when |VEN| ≥ 2 V. The enable voltage can be positive or
negative with respect to ground.
CH1 500mV BW
VOUT (V)
–0.5
CH2 500mV BW
M40µs A CH1
T 10.20%
10703-082
0
590mV
Figure 84. Typical Start-Up Behavior, Positive Going Enable
T
1
–1.0
–1.5
EN
VOUT WITH RISING VEN
VOUT WITH FALLING VEN
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
ENABLE VOLTAGE (V)
VOUT
2
10703-080
–2.0
–2.0
Figure 82 shows the typical hysteresis of the EN pin. This prevents
on/off oscillations that can occur due to noise on the EN pin as
it passes through the threshold points.
Figure 83 shows typical EN thresholds when the input voltage
varies from −2.7 V to −28 V.
1.0
M40µs A CH1
T 10.20%
–580mV
Figure 85. Typical Start-Up Behavior, Negative Going Enable
SOFT START
2
–1.0
1
–26
–22
–18
–14
–10
–6
INPUT VOLTAGE (V)
–2
Figure 83. Typical EN Pin Thresholds vs. Input Voltage
Figure 84 and Figure 85 show the start-up behavior for a −5 V
output with positive and negative going enable signals.
0
–1
–2
–3
–4
VEN
VOUT = –1.22V
VOUT = –3V
VOUT = –5V
–5
–6
0
100
200
300
400
500
600
700
800
900
1000
TIME (µs)
Figure 86. Typical Start-Up Behavior, Different Output Voltages
Rev. I | Page 23 of 31
10703-084
–2.0
–30
10703-081
–1.5
OUTPUT VOLTAGES (V)
ENABLE THRESHOLD (V)
ENABLE+
DISABLE+
ENABLE–
DISABLE–
–0.5
CH2 500mV BW
The ADP7182 uses an internal soft start to limit the inrush current
when the output is enabled. The start-up time for the −5 V option
is approximately 450 μs from the time the EN active threshold is
crossed to when the output reaches 90% of the final value. As
shown in Figure 86, the start-up time is dependent on the output
voltage setting.
0.5
0
CH1 500mV BW
10703-083
Figure 82. Typical EN Pin Operation
ADP7182
Data Sheet
The adjustable LDO circuit can be modified slightly to reduce
the output voltage noise to levels close to that of the fixed output of
the ADP7182. The circuit shown in Figure 87 adds two additional
components to the output voltage setting resistor divider. CNR
and RNR are added in parallel with RFB1 to reduce the ac gain of
the error amplifier. RNR is chosen to be nearly equal to RFB2; this
limits the ac gain of the error amplifier to approximately 6 dB.
The actual gain is the parallel combination of RNR and RFB1 divided
by RFB2. This resistance ensures that the error amplifier always
operates at greater than unity gain.
1
/13 kΩ
18 μV × 1
1/13 kΩ 1/147 kΩ
Figure 88 shows the difference in noise spectral density for the
adjustable ADP7182 set to −15 V with and without the noise
reduction network. In the 100 Hz to 30 kHz frequency range,
the reduction in noise is significant.
100k
CNR is chosen by setting the reactance of CNR equal to RFB1 − RNR
at a frequency between 10 Hz and 100 Hz. This capacitance sets
the frequency where the ac gain of the error amplifier is 3 dB down
from the dc gain.
COUT
2.2µF
CIN
2.2µF
GND
ON
OFF
–2V
VIN
2V
0V
VOUT
RFB1
147kΩ
RNR
13kΩ
VOUT = –15V
ADP7182
EN
ADJ
ON
Figure 87. Noise Reduction Modification to Adjustable LDO
The noise of the LDO is approximately the noise of the fixed output
LDO (typically 18 μV rms) times RFB2, divided by the parallel
combination of RNR and RFB1. Based on the component values
shown in Figure 87, the ADP7182 has the following
characteristics:
–15V ADJ
–15V ADJ NR
10k
1k
100
10
1
1
10
100
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
Figure 88. −15 V Adjustable ADP7182 with and without the
Noise Reduction Network (CNR and RNR)
CURRENT-LIMIT AND THERMAL OVERLOAD
PROTECTION
CNR
100nF
10703-085
VIN = –16V
RFB2
13kΩ
(2)
10703-086
The ultralow output noise of the fixed output ADP7182 is achieved
by keeping the LDO error amplifier in unity gain and setting the
reference voltage equal to the output voltage. This architecture does
not work for an adjustable output voltage LDO. The adjustable
output ADP7182 uses the more conventional architecture where
the reference voltage is fixed and the error amplifier gain is a function
of the output voltage. The disadvantage of the conventional LDO
architecture is that the output voltage noise is proportional to
the output voltage.
The following equation shows the calculation with the values
shown in Figure 87.
NOISE SPECTRAL DENSITY (nV Hz)
NOISE REDUCTION OF THE ADJUSTABLE ADP7182
DC gain of 12.3 (21.8 dB)
3 dB roll-off frequency of 10.8 Hz
High frequency ac gain of 1.92 (5.67 dB)
Noise reduction factor of 6.41 (16.13 dB)
Measured rms noise of the adjustable LDO at −200 mA
without noise reduction of 220 μV rms
Measured rms noise of the adjustable LDO at −200 mA
with noise reduction circuit of 35 μV rms
Calculated rms noise of the adjustable LDO with noise
reduction (assuming 18 μV rms for fixed voltage option) of
34.5 μV rms
The noise of the LDO is approximately the noise of the fixed output
LDO (typically 18 μV rms) times the high frequency ac gain.
The ADP7182 is protected against damage due to excessive power
dissipation by current-limit and thermal overload protection
circuits. The ADP7182 is designed to limit current when the
output load reaches −350 mA (typical). When the output load
exceeds −350 mA, the output voltage is reduced to maintain a
constant current limit.
Thermal overload protection is included, which limits the junction
temperature to a maximum of 150°C (typical). Under extreme
conditions (that is, high ambient temperature and power
dissipation) when the junction temperature starts to rise above
150°C, the output is turned off, reducing the output current to
0 mA. When the junction temperature falls below 135°C, the
output is turned on again, and the output current is restored to
the nominal value.
Consider the case where a hard short from VOUT to ground
occurs. At first, the ADP7182 limits current so that only −350 mA
is conducted into the short. If self-heating of the junction is great
enough to cause the temperature to rise above 150°C, thermal
shutdown is activated, turning off the output and reducing the
output current to 0 mA. As the junction temperature cools and
falls below 135°C, the output turns on and conducts −350 mA
into the short, again causing the junction temperature to rise
above 150°C. This thermal oscillation between 135°C and 150°C
causes a current oscillation between −350 mA and 0 mA that
continues as long as the short remains at the output.
Rev. I | Page 24 of 31
Data Sheet
ADP7182
Current-limit and thermal overload protections are intended to
protect the device against accidental overload conditions. For
reliable operation, device power dissipation must be externally
limited so that the junction temperatures do not exceed 125°C.
THERMAL CONSIDERATIONS
In most applications, the ADP7182 does not dissipate much heat
due to the high efficiency. However, in applications with high
ambient temperature, and high supply voltage to output voltage
differential, the heat dissipated in the package is large enough that
it can cause the junction temperature of the die to exceed the
maximum junction temperature of 125°C.
When the junction temperature exceeds 150°C, the converter
enters thermal shutdown. It recovers only after the junction
temperature has decreased below 135°C to prevent any permanent
damage. Therefore, thermal analysis for the chosen application
is important to guarantee reliable performance over all conditions.
The junction temperature of the die is the sum of the ambient
temperature of the environment and the temperature rise of the
package due to the power dissipation, as shown in Equation 3.
To guarantee reliable operation, the junction temperature of the
ADP7182 must not exceed 125°C. To ensure that the junction
temperature stays below this maximum value, the user must be
aware of the parameters that contribute to junction temperature
changes. These parameters include ambient temperature, power
dissipation in the power device, and thermal resistances between
the junction and ambient air (θJA). The θJA number is dependent
on the package assembly compounds that are used, and the amount
of copper that solders the package VIN pins to the PCB.
Table 8 and Table 9 show typical θJA values of the 6- and 8-lead
and 5-lead TSOT packages for various PCB copper sizes.
Table 10 shows the typical ΨJB values of the 6- and 8-lead and
and 5-lead TSOT.
Model
6-lead LFCSP
8-lead LFCSP
5-lead TSOT
The junction temperature of the ADP7182 can be calculated by
TJ = TA + (PD × θJA)
PD = [(VIN − VOUT) × ILOAD] + (VIN × IGND)
6-Lead LFCSP
177.8
138.2
79.8
67.8
53.5
Device soldered to minimum size pin traces.
Table 9. Typical θJA Values of the 5-Lead TSOT
Copper Size (mm2)
01
50
100
300
500
1
θJA (°C/W)
170
152
146
134
131
(4)
where:
VIN and VOUT are the input and output voltages, respectively.
ILOAD is the load current.
IGND is the ground current.
Power dissipation due to ground current is quite small and can be
ignored. Therefore, the junction temperature equation simplifies to
TJ = TA + {[(VIN − VOUT) × ILOAD] × θJA}
(5)
As shown in Equation 5, for a given ambient temperature, input-tooutput voltage differential, and continuous load current, there
exists a minimum copper size requirement for the PCB to ensure
that the junction temperature does not rise above 125°C. Figure 89
to Figure 97 show junction temperature calculations for different
ambient temperatures, power dissipation, and areas of PCB copper.
Heat dissipation from the package can be improved by increasing
the amount of copper attached to the pins of the ADP7182.
Adding thermal planes under the package also improves thermal
performance. However, as listed in Table 8 and Table 9, a point
of diminishing returns is reached eventually, beyond which an
increase in the copper area does not yield significant reduction
in the junction-to-ambient thermal resistance.
140
JUNCTION TEMPERATURE, TJ (°C)
1
8-Lead LFCSP
175
135.6
77.3
65.2
51
(3)
where:
TA is the ambient temperature.
PD is the power dissipation in the die, given by
θJA (°C/W)
Copper Size (mm2)
251
100
500
1000
6400
ΨJB (°C/W)
44.1
18.2
43
120
100
80
60
6400mm 2
1000mm 2
500mm 2
100mm 2
25mm 2
JEDEC
TJ MAX
40
20
0
0
0.2
0.4
0.6
0.8
1.0
1.2
TOTAL POWER DISSIPATION (W)
Figure 89. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 25°C
Device soldered to minimum size pin traces.
Rev. I | Page 25 of 31
10703-087
Table 8. Typical θJA Values of the LFCSP
Table 10. Typical ΨJB Values
ADP7182
Data Sheet
140
130
100
80
60
6400mm 2
1000mm 2
500mm 2
100mm 2
25mm 2
JEDEC
TJ MAX
40
20
0
0
0.2
0.4
0.6
0.8
1.0
1.2
90
80
6400 mm 2
500 mm 2
25 mm2
TJ MAX
70
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
TOTAL POWER DISSIPATION (W)
Figure 93. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 50°C
145
140
135
100
80
60
6400mm 2
1000mm 2
500mm 2
100mm 2
25mm 2
JEDEC
TJ MAX
40
20
0
0
0.2
0.4
0.6
0.8
1.0
125
115
105
95
85
6400 mm 2
500 mm 2
25 mm2
TJ MAX
75
1.2
TOTAL POWER DISSIPATION (W)
65
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
10703-193
JUNCTION TEMPERATURE (°C)
120
10703-089
0.9
0.8
1.0
TOTAL POWER DISSIPATION (W)
Figure 94. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 85°C
Figure 91. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 85°C
140
145
JUNCTION TEMPERATURE, TJ (°C)
135
125
115
105
95
85
75
65
55
45
35
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
TOTAL POWER DISSIPATION (W)
1.8
10703-191
6400 mm 2
500 mm 2
25 mm2
TJ MAX
120
100
80
60
500mm 2
40
300mm 2
100mm 2
20
25mm 2
JEDEC
TJ MAX
0
0
2.0
0.2
0.4
0.6
0.8
1.0
1.2
TOTAL POWER DISSIPATION (W)
Figure 95. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 25°C
Figure 92. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 25°C
Rev. I | Page 26 of 31
10703-090
JUNCTION TEMPERATURE, TJ (°C)
100
50
Figure 90. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 50°C
JUNCTION TEMPERATURE (°C)
110
60
TOTAL POWER DISSIPATION (W)
25
120
10703-192
JUNCTION TEMPERATURE (°C)
120
10703-088
JUNCTION TEMPERATURE, TJ (°C)
140
ADP7182
140
120
120
100
80
60
500mm 2
40
300mm 2
100mm 2
20
25mm 2
JEDEC
TJ MAX
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
TOTAL POWER DISSIPATION (W)
100
80
60
40
TB = 25°C
TB = 50°C
TB = 85°C
TJ MAX
20
0
0
1
2
3
4
5
6
10703-093
JUNCTION TEMPERATURE, TJ (°C)
140
10703-091
JUNCTION TEMPERATURE, TJ (°C)
Data Sheet
7
TOTAL POWER DISSIPATION (W)
Figure 98. Junction Temperature vs. Total Power Dissipation for the
8-Lead LFCSP, TA = 85°C
Figure 96. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 50°C
140
140
80
60
500mm 2
300mm 2
40
100mm 2
20
0
0
0.05
0.10
0.15
0.20
0.25
0.30
100
80
60
25mm 2
JEDEC
20
TJ MAX
0
0.35
0.40
TOTAL POWER DISSIPATION (W)
TB = 25°C
TB = 50°C
TB = 65°C
TB = 85°C
TJ MAX
40
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
TOTAL POWER DISSIPATION (W)
10703-198
JUNCTION TEMPERATURE (°C)
100
10703-092
JUNCTION TEMPERATURE, TJ (°C)
120
120
4.0
4.5
Figure 99. Junction Temperature vs. Total Power Dissipation for the
6-Lead LFCSP, TA = 85°C
Figure 97. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 85°C
140
TJ = TB + (PD × ΨJB)
(6)
The typical value of ΨJB is 18.2°C/W for the 8-lead LFCSP package,
44.1°C/W for the 6-lead LFCSP package and 43°C/W for the 5-lead
TSOT package.
120
100
80
60
40
TB = 25°C
TB = 50°C
TB = 85°C
TJ MAX
20
0
0
1
2
3
4
5
6
7
TOTAL POWER DISSIPATION (W)
Figure 100. Junction Temperature vs. Total Power Dissipation for the
5-Lead TSOT, TA = 85°C
Rev. I | Page 27 of 31
10703-094
When the board temperature is known, use the thermal
characterization parameter, ΨJB, to estimate the junction
temperature rise (see Figure 98 and Figure 100). Maximum
junction temperature (TJ) is calculated from the board temperature
(TB) and power dissipation (PD) using the following formula:
JUNCTION TEMPERATURE, TJ (°C)
Thermal Characterization Parameter, ΨJB
ADP7182
Data Sheet
PCB LAYOUT CONSIDERATIONS
10703-095
Place the input capacitor as close as possible to the VIN and GND
pins. Place the output capacitor as close as possible to the VOUT
and GND pins. Use of 1206 or 0805 size capacitors and resistors
achieves the smallest possible footprint solution on boards where
area is limited.
10703-100
Figure 102. Example of the 8-Lead LFCSP PCB Layout
10703-096
Figure 101. Example of the 6-Lead LFCSP PCB Layout
Figure 103. Example of the 5-Lead TSOT PCB Layout
Rev. I | Page 28 of 31
Data Sheet
ADP7182
Table 11. Recommended LDOs for Very Low Noise Operation
IOUT
(mA)
300
IQ at
IOUT
(µA)
750
IGND-SD
Max
(µA)
75
Soft
Start
No
PGOOD
Yes
Noise
(Fixed)
10 Hz to
100 kHz
(µV rms)
15
1.22 to
19
500
900
75
No
Yes
15
60
40
1.8, 3.3, 5
1.22 to
19
500
900
75
Yes
Yes
15
60
40
2.7 to 20
1.2 to 5
1.2 to 19
200
160
10
Yes
No
11
68
50
ADP7142
2.7 to 40
1.2 to 5
1.2 to 39
200
160
10
Yes
No
11
68
50
ADP7182
−2.7 to
−28
−1.8 to
−5
−1.22 to
−27
−200
−650
−8
No
No
18
45
45
Device
Number
ADP7102
VIN
Range (V)
3.3 to 20
VOUT
Fixed (V)
1.5 to 9
ADP7104
3.3 to 20
1.5 to 9
ADP7105
3.3 to 20
ADP7118
VOUT
Adjust
(V)
1.22 to
19
Rev. I | Page 29 of 31
PSRR
100 kHz
(dB)
60
PSRR
1 MHz
(dB)
40
Package
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
3 mm × 3 mm
8-lead LFCSP,
8-lead SOIC
2 mm × 2 mm
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
2 mm × 2 mm
6-lead LFCSP,
8-lead SOIC,
5-lead TSOT
2 mm × 2 mm
6-lead LFCSP,
3 mm × 3 mm
8-lead LFCSP,
5-lead TSOT
ADP7182
Data Sheet
OUTLINE DIMENSIONS
1.70
1.60
1.50
2.10
2.00 SQ
1.90
0.65 BSC
6
4
1.10
1.00
0.90
EXPOSED
PAD
0.425
0.350
0.275
1
3
TOP VIEW
0.60
0.55
0.50
SEATING
PLANE
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
0.35
0.30
0.25
0.20 MIN
PIN 1
INDICATOR
(R 0.15)
BOTTOM VIEW
0.20 REF
02-06-2013-D
PIN 1 INDEX
AREA
0.15 REF
Figure 104. 6-Lead Lead Frame Chip Scale Package [LFCSP]
2.00 mm × 2.00 mm Body and 0.55 Package Height
(CP-6-3)
Dimensions shown in millimeters
1.84
1.74
1.64
PIN 1 INDEX
AREA
SIDE VIEW
0.30
0.25
0.20
1
4
BOTTOM VIEW
TOP VIEW
SEATING
PLANE
1.55
1.45
1.35
EXPOSED
PAD
0.50
0.40
0.30
0.80
0.75
0.70
0.50 BSC
8
5
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-229-WEED-4
Figure 105. 8-Lead Lead Frame Chip Scale Package [LFCSP]
3 mm × 3 mm Body and 0.75 Package Height
(CP-8-13)
Dimensions shown in millimeters
Rev. I | Page 30 of 31
PIN 1
INDICATOR
(R 0.15)
05-11-2016-A
3.10
3.00 SQ
2.90
Data Sheet
ADP7182
2.90 BSC
4
5
2.80 BSC
1.60 BSC
1
2
3
0.95 BSC
1.90
BSC
*1.00 MAX
0.10 MAX
0.50
0.30
0.20
0.08
SEATING
PLANE
8°
4°
0°
0.60
0.45
0.30
*COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH
THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS.
100708-A
*0.90 MAX
0.70 MIN
Figure 106. 5-Lead Thin Small Outline Transistor Package [TSOT]
(UJ-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP7182ACPZ-R7
ADP7182ACPZ-5.0-R7
ADP7182AUJZ-R7
ADP7182AUJZ-1.8-R7
ADP7182AUJZ-2.5-R7
ADP7182AUJZ-3.0-R7
ADP7182AUJZ-5.0-R7
ADP7182ACPZN-R7
ADP7182ACPZN-5.0R7
ADP7182ACPZN-2.5R7
ADP7182ACPZN-1.5R7
ADP7182ACPZN-1.2R7
ADP7182UJ-EVALZ
ADP7182CP-EVALZ
1
2
Temperature Range
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
−40°C to +125°C
Output Voltage (V)2
Adjustable
−5
Adjustable
−1.8
−2.5
−3
−5
Adjustable
−5
−2.5
−1.5
−1.2
Package Description
8-Lead LFCSP
8-Lead LFCSP
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
5-Lead TSOT
6-Lead LFCSP
6-Lead LFCSP
6-Lead LFCSP
6-Lead LFCSP
6-Lead LFCSP
Evaluation Board, TSOT
Evaluation Board, LFCSP
Z = RoHS Compliant Part.
For additional voltage options, contact a local Analog Devices, Inc., sales or distribution representative.
©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10703-0-12/16(I)
Rev. I | Page 31 of 31
Package Option
CP-8-13
CP-8-13
UJ-5
UJ-5
UJ-5
UJ-5
UJ-5
CP-6-3
CP-6-3
CP-6-3
CP-6-3
CP-6-3
Branding
LN6
LN9
LN6
LN1
LN7
LN2
LN9
LN6
LN9
LN7
LQK
LRE