TI1 MSP430A095IPN Mixed-signal microcontroller Datasheet

MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
MSP430FG43x Mixed-Signal Microcontrollers
1 Device Overview
1.1
Features
1
• Low Supply-Voltage Range, 1.8 V to 3.6 V
• Ultra-Low Power Consumption
– Active Mode: 300 µA at 1 MHz, 2.2 V
– Standby Mode: 1.1 µA
– Off Mode (RAM Retention): 0.1 µA
• Five Power-Saving Modes
• Wakeup From Standby Mode in Less Than 6 µs
• 16-Bit RISC Architecture, 125-ns Instruction Cycle
Time
• Single-Channel Internal DMA
• 12-Bit Analog-to-Digital Converter (ADC) With
Internal Reference, Sample-and-Hold and
Autoscan Feature
• Three Configurable Operational Amplifiers
• Dual 12-Bit Digital-to-Analog Converters (DACs)
With Synchronization
• 16-Bit Timer_A With Three Capture/Compare
Registers
• 16-Bit Timer_B With Three Capture/CompareWith-Shadow Registers
1.2
•
•
•
Applications
Analog and Digital Sensor Systems
Digital Motor Control
Remote Controls
1.3
• On-Chip Comparator
• Serial Communication Interface (USART),
Select Asynchronous UART or Synchronous SPI
by Software
• Brownout Detector
• Supply-Voltage Supervisor and Monitor With
Programmable Level Detection
• Bootstrap Loader (BSL)
• Serial Onboard Programming, No External
Programming Voltage Needed, Programmable
Code Protection by Security Fuse
• Integrated Liquid Crystal Display (LCD) Driver for
up to 128 Segments
• Available in 113-Ball BGA (ZCA) and 80-Pin QFP
(PN) Packages
• Section 3 Summarizes the Available Family
Members
• For Complete Module Descriptions, See the
MSP430x4xx Family User's Guide (SLAU056)
•
•
•
Thermostats
Digital Timers
Hand-Held Meters
Description
The Texas Instruments MSP430™ family of ultra-low-power microcontrollers consists of several devices
featuring different sets of peripherals targeted for various applications. The architecture, combined with
five low-power modes, is optimized to achieve extended battery life in portable measurement applications.
The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute
to maximum code efficiency. The digitally controlled oscillator (DCO) allows the device to wake up from
low-power modes to active mode in less than 6 µs.
The MSP430FG43x devices are microcontrollers with two 16-bit timers, a high-performance 12-bit ADC,
dual 12-bit DACs, three configurable operational amplifiers, one universal synchronous/asynchronous
communication interface, DMA, 48 I/O pins, and an LCD driver.
Table 1-1. Device Information (1)
PACKAGE
BODY SIZE (2)
MSP430FG439PN
LQFP (80)
12 mm x 12 mm
MSP430FG439ZCA
BGA (113)
7 mm x 7 mm
PART NUMBER
(1)
(2)
For the most current device, package, and ordering information, see the Package Option Addendum in Section 8, or see the TI web site
at www.ti.com.
The sizes shown here are approximations. For the package dimensions with tolerances, see the Mechanical Data in Section 8.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
1.4
www.ti.com
Functional Block Diagram
Figure 1-1 shows the functional block diagram.
XIN
XT2IN
XT2OUT
DV CC1/2 DV SS1/2
XOUT
AV CC
AV SS
P1
P2
P4
P3
8
8
P6
P5
8
8
8
8
ACLK
Oscillator
FLL+
Flash
SMCLK
60KB
48KB
32KB
MCLK
8 MHz
CPU
incl. 16
Registers
Emulation
Module
ADC12
DAC12
Port 1
Port 2
2KB
1KB
12-Biit
12 Channels
<10µs Conv.
12-Bit
2 Channels
Voltage Out
8 I/O
Interrupt
Capability
8 I/O
Interrupt
Capability
DMA
Controller
Watchdog
Timer
WDT
RAM
Port 3
Port 4
Port 5
Port 6
8 I/O
8 I/O
8 I/O
8 I/O
LCD
128
Segments
1,2,3,4 MUX
USART0
OA0, OA1
OA2
UART Mode
SPI Mode
MAB
MDB
POR/
SVS/
Brownout
JTAG
Interface
1 Channel
15/16-Bit
Timer_B3
Timer_A3
3 CC Reg
Shadow
Reg
3 CC Reg
Comparator_
A
Basic
Timer 1
1 Interrupt
Vector
3 Op Amps
fLCD
RST/NMI
Figure 1-1. Functional Block Diagram
2
Device Overview
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Table of Contents
1
2
3
4
5
Device Overview ......................................... 1
5.24
12-Bit ADC, Built-In Reference...................... 28
1.1
Features .............................................. 1
5.25
12-Bit ADC, Timing Parameters
1.2
Applications ........................................... 1
5.26
12-Bit ADC, Linearity Parameters................... 30
1.3
Description ............................................ 1
5.27
12-Bit ADC, Temperature Sensor and Built-In VMID
1.4
Functional Block Diagram ............................ 2
5.28
12-Bit DAC, Supply Specifications .................. 31
Revision History ......................................... 4
Device Comparison ..................................... 5
Terminal Configuration and Functions .............. 6
5.29
12-Bit DAC, Linearity Specifications ................ 32
5.30
12-Bit DAC, Output Specifications .................. 34
5.31
12-Bit DAC, Reference Input Specifications ........ 35
4.1
Pin Diagrams ......................................... 6
5.32
12-Bit DAC, Dynamic Specifications ................ 35
4.2
Signal Descriptions ................................... 8
5.33
12-Bit DAC, Dynamic Specifications (Continued) ... 36
Specifications ........................................... 12
5.34
5.35
Operational Amplifier (OA), Supply Specifications .. 37
Operational Amplifier (OA), Input/Output
Specifications........................................ 37
12
5.36
Operational Amplifier (OA), Dynamic Specifications 38
Supply Current Into AVCC + DVCC Excluding
External Current .................................... 14
Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI,
JTAG (TCK, TMS, TDI/TCLK, TDO/TDI) ........... 15
5.37
OA Dynamic Specifications Typical Characteristics
5.38
Flash Memory ....................................... 39
5.39
JTAG Interface ...................................... 39
5.40
JTAG Fuse
5.1
5.2
5.3
5.4
5.5
........................
Handling Ratings ....................................
Recommended Operating Conditions ...............
Absolute Maximum Ratings
12
12
5.6
Inputs Px.y, TAx, TBx ............................... 15
5.7
.................
...........................
Output Frequency ...................................
Typical Characteristics – Outputs ...................
Wake-Up From LPM3 ...............................
RAM .................................................
LCD..................................................
Comparator_A ......................................
Comparator_A Typical Characteristics ..............
5.8
5.9
5.10
5.11
5.12
5.13
5.14
5.15
5.16
6
....................
.........................................
30
31
38
39
Detailed Description ................................... 40
Leakage Current – Ports P1 to P6
15
6.1
CPU
Outputs – Ports P1 to P6
16
6.2
Instruction Set ....................................... 41
.................................................
40
16
6.3
Operating Modes .................................... 42
17
6.4
Interrupt Vector Addresses.......................... 43
18
6.5
Special Function Registers (SFRs)
18
6.6
Memory Organization ............................... 46
.................
44
18
6.7
Bootstrap Loader (BSL) ............................. 47
19
6.8
Flash Memory ....................................... 47
19
6.9
Peripherals
6.10
Input/Output Schematics ............................ 55
Power-On Reset (POR) and Brownout Reset (BOR)
..........................................
48
5.17
...................................................... 21
Supply Voltage Supervisor (SVS) and Supply
Voltage Monitor (SVM) ............................. 22
7.1
Device Support ...................................... 78
5.18
DCO ................................................. 24
7.2
Documentation Support ............................. 80
5.19
Crystal Oscillator, XT1 Oscillator
...................
Crystal Oscillator, XT2 Oscillator ...................
USART0 ............................................
26
7.3
Trademarks.......................................... 80
26
7.4
Electrostatic Discharge Caution ..................... 80
26
12-Bit ADC, Power Supply and Input Range
Conditions .......................................... 27
7.5
Glossary ............................................. 80
5.20
5.21
5.22
5.23
12-Bit ADC, External Reference
...................
27
7
8
Device and Documentation Support ............... 78
Mechanical Packaging and Orderable
Information .............................................. 81
8.1
Packaging Information
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..............................
Table of Contents
81
3
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
www.ti.com
2 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision C (March 2011) to Revision D
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
4
Page
Document format and organization changes throughout, including addition of section numbering........................ 1
Added Section 1.2 ................................................................................................................... 1
Added Device Information table .................................................................................................... 1
Added Section 3 ...................................................................................................................... 5
Added ZCA package pinout ......................................................................................................... 7
Added ZCA package to Table 4-1 .................................................................................................. 8
Added Section 5 and moved all electrical specifications to it ................................................................. 12
Added Section 5.2 and moved Tstg to it .......................................................................................... 12
Added ZCA package to BSL table ................................................................................................ 47
Added ZCA package to Timer_A3 table.......................................................................................... 49
Added ZCA package to Timer_B3 table ......................................................................................... 50
Moved Section 6.10 ................................................................................................................. 55
Changed the values in the Port/LCD column ................................................................................... 59
Changed the input signals (LCDPx[0:2]) in the top left of the figure ......................................................... 60
Changed the input signal (LCDPx[2]) in the top left of the figure ............................................................. 61
Changed the values in the DEVICE, PORT FUNCTION, and LCD SEGMENT FUNCTION columns................... 62
Changed the input "1, If LCDPx ≥ 01h" near the top left of the figure ....................................................... 63
Changed the values in the DEVICE, PORT FUNCTION, and LCD SEGMENT FUNCTION columns................... 63
Changed the input "1, If LCDPx ≥ 01h" near the top left of the figure ....................................................... 64
Changed the values in the DEVICE, PORT FUNCTION, and LCD SEGMENT FUNCTION columns................... 64
Changed the input "1, If LCDPx ≥ 01h" near the top left of the figure ....................................................... 65
Changed the values in the DEVICE, PORT FUNCTION, and LCD SEGMENT FUNCTION columns................... 65
Changed the input "1, If LCDPx ≥ 01h" near the top left of the figure ....................................................... 66
Changed the LCDPx column heading and values .............................................................................. 66
Changed the value in the Port/LCD column ..................................................................................... 66
Added Section 7 ..................................................................................................................... 78
Added Section 8 .................................................................................................................... 81
Revision History
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
3 Device Comparison
The following table summarizes the available family members.
Table 3-1. Device Comparison (1) (2)
Device
FLASH
(KB)
SRAM
(KB)
ADC12
DAC12
Comp_A
Timer_A (3)
Timer_B (4)
USART
LCD
I/Os
Package
Type
MSP430FG439
60
2
12
channels
2 channels
16
channels
3
3
Yes
Yes
48
80 PN
113 ZCA
MSP430FG438
48
2
12
channels
2 channels
16
channels
3
3
Yes
Yes
48
80 PN
113 ZCA
MSP430FG437
32
1
12
channels
2 channels
16
channels
3
3
Yes
Yes
48
80 PN
113 ZCA
(1)
(2)
(3)
(4)
For the most current package and ordering information, see the Package Option Addendum in Section 8, or see the TI web site at
www.ti.com.
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM
output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first
instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
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Device Comparison
5
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
www.ti.com
4 Terminal Configuration and Functions
4.1
Pin Diagrams
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1.6/CA0
P6.2/A2/OA0I1
P6.1/A1/OA0O
P6.0/A0/OA0I0
RST/NMI
TCK
TMS
TDI/TCLK
TDO/TDI
XT2IN
XT2OUT
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
AV CC
DV SS1
AV SS
Figure 4-1 shows the pin assignments for the 80-pin PN package.
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
1
60
2
59
3
58
4
57
5
56
6
55
7
54
8
53
9
52
10
51
11
50
12
49
13
48
14
47
15
46
16
45
17
44
18
43
19
42
20
41
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
P1.7/CA1
P2.0/TA2
P2.1/TB0
P2.2/TB1
P2.3/TB2
P2.4/UTXD0
P2.5/URXD0
DV SS2
DV CC2
P5.7/R33
P5.6/R23
P5.5/R13
R03
P5.4/COM3
P5.3/COM2
P5.2/COM1
COM0
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P4.0/S9
S10
S11
S12
S13
S14
S15
S16
S17
P2.7/ADC12CLK/S18
P2.6/CAOUT/S19
S20
S21
S22
S23
P3.7/S24
P3.6/S25/DMAE0
P3.5/S26
P3.4/S27
P3.3/UCLK0/S28
DV CC1
P6.3/A3/OA1I1/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2I1/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VREF+
XIN
XOUT
Ve REF+/DAC0
VREF- /VeREFP5.1/S0/A12/DAC1
P5.0/S1/A13
P4.7/S2/A14
P4.6/S3/A15
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
Figure 4-1. 80-Pin PN Package (Top View)
6
Terminal Configuration and Functions
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Figure 4-2 shows the pin assignments for the 113-pin ZCA package.
ZCA PACKAGE
(TOP VIEW)
P6.1
P6.0
RST
P1.3
P1.6
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
DVCC
DVSS
AVCC
P6.2
P6.3
DVSS
DVSS
DVSS
P1.2
P1.5
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
DVSS
AVSS AVCC
VREF+ DVCC
XT2IN XT2OUT DVSS
A12
P1.7
B11
B12
P2.0 P2.4/TX
DVSS
C1
C2
AVSS
P6.7
P6.5
P6.4
TMS
TDO
P1.0
P1.1
D1
D2
D4
D5
D6
D7
D8
D9
D11
D12
XIN
AVSS
P6.6
TCK
TDI
E1
E2
E4
E6
E7
XOUT
AVSS
P5.1
F1
F2
F4
AVSS
AVSS
P5.0
G1
G2
G4
C3
VeREF+ AVSS
H1
VREF- AVSS
J2
P4.5
P4.4
E5
F5
G5
P1.4
P2.2
DVSS2
E9
E11
E12
P2.3
DVCC2
F8
F9
F11
F12
G8
G9
COM3
R33
G11
G12
COM2
R23
H4
H5
H6
H7
H8
H9
H11
H12
P4.6
S13
S16
S21
S22
S23
COM1
R13
J4
J5
J6
J7
J8
J9
J11
J12
COM0
R03
K1
K2
P4.1
P4.2
P4.3
S11
S14
S17
S20
L1
L2
L3
L4
L5
L6
L7
P4.0
S10
S12
S15
M2
M3
M4
M5
M1
C12
E8
P4.7
H2
J1
C11
P2.1 P2.5/RX
K11
P3.6/S25 P3.5/S26 P3.4/S27
L8
L9
L10
K12
P3.0/S31
L11
L12
P2.7/S18 P2.6/S19 P3.7/S24 P3.3/S28 P3.2/S29 P3.1/S30
M6
M7
M8
M9
M10
M11
M12
Figure 4-2. 113-Pin ZCA Package (Top View)
Terminal Configuration and Functions
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4.2
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Signal Descriptions
Table 4-1 describes the signals for all device variants and package options.
Table 4-1. Signal Descriptions
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PN
ZCA
1
B1, C2
2
B5
I/O
General-purpose digital I/O
Analog input a3—12-bit ADC
OA1 output and/or input multiplexer on +terminal and −terminal
3
D5
I/O
General-purpose digital I/O
Analog input a4—12-bit ADC
OA1 input multiplexer on +terminal and −terminal
4
D4
I/O
General-purpose digital I/O
Analog input a5—12-bit ADC
OA2 output and/or input multiplexer on +terminal and −terminal
5
E4
I/O
General-purpose digital I/O
Analog input a6—12-bit ADC
DAC12.0 output
OA2 input multiplexer on +terminal and −terminal
6
D2
I/O
General-purpose digital I/O
Analog input a7—12-bit ADC
DAC12.1 output/analog input to supply voltage supervisor
VREF+
7
C1
O
Positive output terminal of the reference voltage in the ADC
XIN
8
E1
I
Input terminal of crystal oscillator XT1
XOUT
9
F1
O
Output terminal of crystal oscillator XT1
10
H1
I/O
Positive input terminal for an external reference voltage to the 12-bit
ADC/DAC12.0 output
11
J1
I
12
F4
I/O
General-purpose digital I/O
LCD segment output 0
Analog input a12—12-bit ADC
DAC12.1 output
13
G4
I/O
General-purpose digital I/O
LCD segment output 1
Analog input a13—12-bit ADC
14
H4
I/O
General-purpose digital I/O
LCD segment output 2
Analog input a14—12-bit ADC
15
J4
I/O
General-purpose digital I/O
LCD segment output 3
Analog input a15—12-bit ADC
16
K1
I/O
General-purpose digital I/O
LCD segment output 4
17
K2
I/O
General-purpose digital I/O
LCD segment output 5
18
L3
I/O
General-purpose digital I/O
LCD segment output 6
19
L2
I/O
General-purpose digital I/O
LCD segment output 7
20
L1
I/O
General-purpose digital I/O
LCD segment output 8
21
M2
I/O
General-purpose digital I/O
LCD segment output 9
22
M3
O
LCD segment output 10
DVCC1
Digital supply voltage, positive terminal.
P6.3/A3/OA1I1/OA1O
P6.4/A4/OA1I0
P6.5/A5/OA2I1/OA2O
P6.6/A6/DAC0/OA2I0
P6.7/A7/DAC1/SVSIN
VeREF+/DAC0
VREF−/VeREF−
P5.1/S0/A12/DAC1
P5.0/S1/A13
P4.7/S2/A14
P4.6/S3/A15
P4.5/S4
P4.4/S5
P4.3/S6
P4.2/S7
P4.1/S8
P4.0/S9
S10
8
Terminal Configuration and Functions
Negative terminal for the 12-bit ADC's reference voltage for both sources, the
internal reference voltage or an external applied reference voltage to the 12-bit
ADC.
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
PN
I/O
DESCRIPTION
ZCA
S11
23
L4
O
LCD segment output 11
S12
24
M4
O
LCD segment output 12
S13
25
J5
O
LCD segment output 13
S14
26
L5
O
LCD segment output 14
S15
27
M5
O
LCD segment output 15
S16
28
J6
O
LCD segment output 16
S17
29
L6
O
LCD segment output 17
30
M6
I/O
General-purpose digital I/O
Conversion clock—12-bit ADC
LCD segment output 18
31
M7
I/O
General-purpose digital I/O
Comparator_A output / LCD segment output 19
S20
32
L7
O
LCD segment output 20
S21
33
J7
O
LCD segment output 21
S22
34
J8
O
LCD segment output 22
S23
35
J9
O
LCD segment output 23
36
M8
I/O
General-purpose digital I/O
LCD segment output 24
37
L8
I/O
General-purpose digital I/O
LCD segment output 25/DMA Channel 0 external trigger
38
L9
I/O
General-purpose digital I/O
LCD segment output 26
39
L10
I/O
General-purpose digital I/O
LCD segment output 27
40
M9
I/O
General-purpose digital I/O
External clock input—USART0/UART or SPI mode, clock output—USART0/SPI
mode
LCD segment output 28
41
M10
I/O
General-purpose digital I/O
Slave out/master in of USART0/SPI mode
LCD segment output 29
42
M11
I/O
General-purpose digital I/O
Slave in/master out of USART0/SPI mode
LCD segment output 30
43
L12
I/O
General-purpose digital I/O
Slave transmit enable-USART0/SPI mode
LCD segment output 31
44
K11
O
Common output, COM0−3 are used for LCD backplanes.
45
J11
I/O
General-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
46
H11
I/O
General-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
47
G11
I/O
General-purpose digital I/O
Common output, COM0−3 are used for LCD backplanes.
48
K12
I
Input port of fourth positive (lowest) analog LCD level (V5)
49
J12
I/O
General-purpose digital I/O
input port of third most positive analog LCD level (V4 or V3)
50
H12
I/O
General-purpose digital I/O
Input port of second most positive analog LCD level (V2)
51
G12
I/O
General-purpose digital I/O
Output port of most positive analog LCD level (V1)
52
F12
P2.7/ADC12CLK/S18
P2.6/CAOUT/S19
P3.7/S24
P3.6/S25/DMAE0
P3.5/S26
P3.4/S27
P3.3/UCLK0/S28
P3.2/SOMI0/S29
P3.1/SIMO0/S30
P3.0/STE0/S31
COM0
P5.2/COM1
P5.3/COM2
P5.4/COM3
R03
P5.5/R13
P5.6/R23
P5.7/R33
DVCC2
Digital supply voltage, positive terminal
Terminal Configuration and Functions
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Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O
DESCRIPTION
PN
ZCA
53
E12
54
D12
I/O
General-purpose digital I/O
Receive data in—USART0/UART mode
55
C12
I/O
General-purpose digital I/O
Transmit data out—USART0/UART mode
56
F11
I/O
General-purpose digital I/O
Timer_B3 CCR2. Capture: CCI2A/CCI2B input, compare: Out2 output
57
E11
I/O
General-purpose digital I/O
Timer_B3 CCR1. Capture: CCI1A/CCI1B input, compare: Out1 output
58
D11
I/O
General-purpose digital I/O
Timer_B3 CCR0. Capture: CCI0A/CCI0B input, compare: Out0 output
59
C11
I/O
General-purpose digital I/O
Timer_A Capture: CCI2A input, compare: Out2 output
60
B12
I/O
General-purpose digital I/O
Comparator_A input
61
A11
I/O
General-purpose digital I/O
Comparator_A input
62
B10
I/O
General-purpose digital I/O
Timer_A, clock signal TACLK input
ACLK output (divided by 1, 2, 4, or 8)
63
E9
I/O
General-purpose digital I/O
Input clock TBCLK—Timer_B3
Submain system clock SMCLK output
64
A10
I/O
General-purpose digital I/O
Switch all PWM digital output ports to high impedance—Timer_B3 TB0 to TB2
SVS: output of SVS comparator
65
B9
I/O
General-purpose digital I/O
Timer_A, Capture: CCI1A, compare: Out1 output
66
D9
I/O
General-purpose digital I/O
Timer_A. Capture: CCI0B / MCLK output. Note: TA0 is only an input on this pin
BSL receive
67
D8
I/O
General-purpose digital I/O
Timer_A. Capture: CCI0A input, compare: Out0 output
BSL transmit
XT2OUT
68
A8
O
Output terminal of crystal oscillator XT2
XT2IN
69
A7
I
Input port for crystal oscillator XT2. Only standard crystals can be connected.
TDO/TDI
70
D7
I/O
71
E7
I
Test data input or test clock input. The device protection fuse is connected to
TDI/TCLK.
TMS
72
D6
I
Test mode select. TMS is used as an input port for device programming and test.
TCK
73
E6
I
Test clock. TCK is the clock input port for device programming and test.
RST/NMI
74
A6
I
Reset or nonmaskable interrupt input
75
A5
I/O
General-purpose digital I/O
Analog input a0 − 12-bit ADC
OA0 input multiplexer on +terminal and −terminal
76
A4
I/O
General-purpose digital I/O
Analog input a1 − 12-bit ADC
OA0 output
77
B4
I/O
General-purpose digital I/O
Analog input a2 − 12-bit ADC
OA0 input multiplexer on + terminal and − terminal
DVSS2
P2.5/URXD0
P2.4/UTXD0
P2.3/TB2
P2.2/TB1
P2.1/TB0
P2.0/TA2
P1.7/CA1
P1.6/CA0
Digital supply voltage, negative terminal
P1.5/TACLK/ACLK
P1.4/TBCLK/SMCLK
P1.3/TBOUTH/SVSOUT
P1.2/TA1
P1.1/TA0/MCLK
P1.0/TA0
TDI/TCLK
P6.0/A0/OA0I0
P6.1/A1/OA0O
P6.2/A2/OA0I1
10
Terminal Configuration and Functions
Test data output port. TDO/TDI data output or programming data input terminal
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
Table 4-1. Signal Descriptions (continued)
TERMINAL
NAME
NO.
I/O
PN
ZCA
78
A2, D1,
E2, F2,
G2, G1,
H2, J2
Analog supply voltage, negative terminal. Supplies SVS, brownout, oscillator,
comparator_A, port 1, and LCD resistive divider circuitry.
A1, B2,
C3, B6,
B7, B8,
A9
Digital supply voltage, negative terminal
79
80
A3, B3
AVSS
DVSS1
AVCC
Reserved
(1)
DESCRIPTION
(1)
Analog supply voltage, positive terminal. Supplies SVS, brownout, oscillator,
comparator_A, port 1, and LCD resistive divider circuitry; must not power up prior
to DVCC1/DVCC2.
Reserved
A12, B11, E5, E8, F5, F8, F9, G5, G8, G9, H5, H6, H7, H8, H9, L11, M1, M12 are reserved and should be connected to ground.
Terminal Configuration and Functions
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5 Specifications
Absolute Maximum Ratings (1)
5.1
over operating free-air temperature range (unless otherwise noted)
Voltage applied at VCC to VSS
Voltage applied to any pin
(2)
MIN
MAX
UNIT
–0.3
4.1
V
–0.3
VCC + 0.3
V
±2
mA
Diode current at any device terminal
(1)
(2)
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltages referenced to VSS.The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is
applied to the TDI/TCLK pin when blowing the JTAG fuse.
5.2
Handling Ratings
Tstg
Storage temperature range
5.3
MIN
MAX
Unprogrammed device
-55
150
Programmed device
-40
85
UNIT
°C
Recommended Operating Conditions
MIN
During program execution
Supply voltage (1)
(AVCC = DVCC1 = DVCC2 = VCC)
VCC
NOM MAX UNIT
1.8
3.6
2
3.6
2.7
3.6
0
0
V
–40
85
°C
450
8000
kHz
1000
8000
450
8000
1000
8000
VCC = 1.8 V
dc
4.15
VCC = 3.6 V
dc
8
During program execution,
SVS enabled and PORON = 1 (2)
During flash memory programming
V
(1)
VSS
Supply voltage
(AVSS = DVSS1 = DVSS2 = VSS)
TA
Operating free-air temperature range
f(LFXT1)
XT1 crystal frequency (3)
XT2 crystal frequency
f(System)
Processor frequency (signal MCLK)
(2)
(3)
12
Watch crystal
XT1 selected, XTS_FLL = 1
Ceramic resonator
XT1 selected, XTS_FLL = 1
Crystal
Ceramic resonator
f(XT2)
(1)
LF selected, XTS_FLL = 0
Crystal
32.768
kHz
MHz
It is recommended to power AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be
tolerated during power up and operation.
The minimum operating supply voltage is defined according to the trip point where POR is going active by decreasing the supply
voltage. POR is going inactive when the supply voltage is raised above the minimum supply voltage plus the hysteresis of the SVS
circuitry.
In LF mode, the LFXT1 oscillator requires a watch crystal. In XT1 mode, LFXT1 accepts a ceramic resonator or a crystal.
Specifications
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f(System) – MHz
8
Supply voltage range,
MSP430FG43x, during
program execution
Supply voltage range, MSP430FG43x,
during flash memory programming
4.15
1.8
2.7
3
Supply Voltage - V
3.6
Figure 5-1. Frequency vs Supply Voltage, Typical Characteristic
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Specifications
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5.4
www.ti.com
Supply Current Into AVCC + DVCC Excluding External Current
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TA
TYP
MAX
2.2 V
300
370
3V
470
570
2.2 V
55
70
3V
95
110
2.2 V
11
14
3V
17
22
–40°C
1
2
25°C
1.1
2
2
3
(1)
I(AM)
Active mode
f(MCLK) = f(SMCLK) = 1 MHz,
f(ACLK) = 32768 Hz,
XTS_FLL = 0, SELM = (0,1)
I(LPM0)
Low-power mode (LPM0) (1)
I(LPM2)
Low-power mode (LPM2),
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 0 (3)
–40°C to 85°C
(2)
–40°C to 85°C
(2)
–40°C to 85°C
60°C
I(LPM3)
Low-power mode (LPM3)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 32768 Hz, SCG0 = 1 (3)
(4) (2)
3.5
6
–40°C
1.8
2.8
1.6
2.7
60°C
2.5
3.5
4.2
7.5
–40°C
0.1
0.5
0.1
0.5
0.7
1.1
85°C
1.7
3
–40°C
0.1
0.8
0.1
0.8
0.8
1.2
1.9
3.5
60°C
(2)
3V
85°C
25°C
I(LPM4)
2.2 V
25°C
60°C
2.2 V
3V
85°C
(1)
(2)
(3)
(4)
MIN
85°C
25°C
Low-power mode (LPM4)
f(MCLK) = f(SMCLK) = 0 MHz,
f(ACLK) = 0 Hz, SCG0 = 1 (3)
VCC
UNIT
µA
µA
µA
µA
µA
Timer_B is clocked by f(DCOCLK) = f(DCO) = 1 MHz. All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
Current for brownout included.
All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
The current consumption in LPM3 is measured with active Basic Timer1 and LCD (ACLK selected). The current consumption of the
Comparator_A and the SVS module are specified in the respective sections. The LPM3 currents are characterized with a KDS
Daishinku DT−38 (6 pF) crystal and OSCCAPx = 01h.
Current consumption of active mode versus system frequency:
I(AM) = I(AM) [1 MHz] × f(System) [MHz]
Current consumption of active mode versus supply voltage:
I(AM) = I(AM) [3 V] + 175 µA/V × (VCC – 3 V)
14
Specifications
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5.5
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
Schmitt-Trigger Inputs – Ports P1 to P6, RST/NMI, JTAG (TCK, TMS, TDI/TCLK, TDO/TDI)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VIT+
Positive-going input threshold voltage
VIT–
Negative-going input threshold voltage
Vhys
Input voltage hysteresis (VIT+ – VIT– )
5.6
VCC
MIN
MAX
2.2 V
1.1
1.55
3V
1.5
1.98
2.2 V
0.4
0.9
3V
0.9
1.3
2.2 V
0.3
1.1
3V
0.5
1
MIN
MAX
UNIT
V
V
V
Inputs Px.y, TAx, TBx
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
2.2 V
62
3V
50
2.2 V
62
3V
50
t(int)
External interrupt timing
Port P1, P2: P1.x to P2.x, external trigger signal
for the interrupt flag (1)
t(cap)
Timer_A or Timer_B capture timing
TA0, TA1, TA2
TB0, TB1, TB2
f(TAext)
Timer_A or Timer_B clock
frequency externally applied to pin
TACLK, TBCLK, INCLK: t(H) = t(L)
Timer_A or Timer_B clock
frequency
SMCLK or ACLK signal selected
f(TBext)
f(TAint)
f(TBint)
(1)
UNIT
ns
ns
2.2 V
8
3V
10
2.2 V
8
3V
10
MHz
MHz
The external signal sets the interrupt flag every time the minimum t(int) parameters are met. It might be set with trigger signals shorter
than t(int).
Leakage Current – Ports P1 to P6 (1)
5.7
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Ilkg(Px.y)
(1)
(2)
Leakage current, Port Px
TEST CONDITIONS
V(Px.y) (2)
VCC = 2.2 V, 3 V
MIN
MAX
UNIT
±50
nA
The leakage current is measured with VSS or VCC applied to the corresponding pins, unless otherwise noted.
The port pin must be selected as input.
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5.8
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Outputs – Ports P1 to P6
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
IOH(max) = –1.5 mA, VCC = 2.2 V
VOH
High-level output voltage
(1)
VCC – 0.25
VCC
VCC – 0.6
VCC
IOH(max) = –1.5 mA, VCC = 3 V (1)
VCC – 0.25
VCC
VCC – 0.6
VCC
IOL(max) = 1.5 mA, VCC = 2.2 V
(1)
(2)
Low-level output voltage
MAX
IOH(max) = –6 mA, VCC = 2.2 V (2)
IOH(max) = –6 mA, VCC = 3 V (2)
VOL
MIN
(1)
UNIT
V
VSS VSS + 0.25
IOL(max) = 6 mA, VCC = 2.2 V (2)
VSS
IOL(max) = 1.5 mA, VCC = 3 V (1)
VSS VSS + 0.25
IOL(max) = 6 mA, VCC = 3 V (2)
VSS
VSS + 0.6
V
VSS + 0.6
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±12 mA to satisfy the maximum specified
voltage drop.
The maximum total current, IOH(max) and IOL(max), for all outputs combined, should not exceed ±48 mA to satisfy the maximum specified
voltage drop.
5.9
Output Frequency
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
f(Px.y)
(1 ≤ × ≤ 6, 0 ≤ y ≤ 7)
f(MCLK)
P1.1/TA0/MCLK
f(SMCLK)
P1.4/TBCLK/SMCLK
f(ACLK)
P1.5/TACLK/ACLK
TEST CONDITIONS
CL = 20 F,
IL = ±1.5 mA
16
Duty cycle of output frequency
Specifications
VCC = 2.2 V, 3 V
TYP
dc
CL = 20 pF
P1.5/TACLK/ACLK,
CL = 20 pF,
VCC = 2.2 V, 3 V
t(Xdc)
MIN
f(ACLK) = f(LFXT1) = f(XT1)
40%
f(ACLK) = f(LFXT1) = f(LF)
30%
f(ACLK) = f(LFXT1)
P1.1/TA0/MCLK,
CL = 20 pF,
VCC = 2.2 V, 3 V
f(MCLK) = f(XT1)
P1.4/TBCLK/SMCLK,
CL = 20 pF,
VCC = 2.2 V, 3 V
f(SMCLK) = f(XT2)
MAX
UNIT
f(System)
MHz
f(System)
MHz
60%
70%
50%
40%
50% –
15 ns
f(MCLK) = f(DCOCLK)
60%
50%
40%
f(SMCLK) = f(DCOCLK)
50% –
15 ns
50%+
15 ns
60%
50%
50%+
15 ns
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5.10 Typical Characteristics – Outputs
over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
25
TA = 25°C
VCC = 2.2 V
P2.7
14
12
I OL - Typical Low-level Output Current - m A
I OL - Typical Low-level Output Current - m A
16
TA = 85°C
10
8
6
4
2
0
0.0
0.5
1.0
1.5
2.0
2.5
VOL - L ow-Level Output Voltage - V
Figure 5-2. Typical Low-Level Output Current vs Typical LowLevel Output Current
I OL - Typical High-level Output Current - m A
I OL - Typical High-level Output Current - m A
-4
-6
-8
TA = 85°C
-12
TA = 25°C
-14
0.0
20
TA = 85°C
15
10
5
0
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
0
VCC = 2.2 V
P2.7
-10
TA = 25°C
VOL - L ow-Level Output Voltage - V
Figure 5-3. Typical Low-Level Output Current vs Typical LowLevel Output Current
0
-2
VCC = 3 V
P2.7
0.5
1.0
1.5
2.0
2.5
VOH - H igh-Level Output Voltage - V
Figure 5-4. Typical High-Level Output Current vs Typical HighLevel Output Current
VCC = 3 V
P2.7
-5
-10
-15
TA = 85°C
-20
-25
TA = 25°C
-30
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
VOH - High-Level Output Voltage - V
Figure 5-5. Typical High-Level Output Current vs Typical HighLevel Output Current
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Specifications
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5.11
www.ti.com
Wake-Up From LPM3
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
MAX
f = 1 MHz
td(LPM3)
Delay time
6
f = 2 MHz
VCC = 2.2 V, 3 V
6
f = 3 MHz
5.12
UNIT
µs
6
RAM
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
(1)
MIN
CPU halted (1)
VRAMh
MAX
1.6
UNIT
V
This parameter defines the minimum supply voltage when the data in program memory RAM remain unchanged. No program execution
should take place during this supply voltage condition.
5.13
LCD
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
V(33)
TEST CONDITIONS
Voltage at P5.7/R33
V(23)
Analog voltage
V(13)
Voltage at P5.6/R23
Voltage at P5.5/R13
V(33)-V(03)
Voltage at R33 to R03
I(R03)
R03 = VSS
I(R13)
Input leakage
I(R23)
P5.5/R13 = VCC/3
P5.6/R23 = 2 × VCC/3
V(Sxx0)
V(Sxx1)
V(Sxx2)
Segment line
voltage
V(Sxx3)
18
Specifications
I(Sxx) = −3 µA, VCC = 3 V
MIN
TYP
2.5
MAX
[V(33)−V(03)] × 2/3 + V(03)
VCC = 3 V
UNIT
VCC + 0.2
V
[V(33)−V(03)] × 1/3 + V(03)
2.5
VCC + 0.2
No load at all
segment and
common lines,
VCC = 3 V
±20
±20
nA
±20
V(03)
V(03) - 1
V(13)
V(13) - 1
V(23)
V(23) - 1
V(33)
V(33) - 1
V
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5.14 Comparator_A (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
I(CC)
CAON = 1, CARSEL = 0, CAREF = 0
I(Refladder/RefDiode)
CAON = 1, CARSEL = 0, CAREF = (1,2,3),
No load at P1.6/CA0 and P1.7/CA1
MIN
TYP
MAX
2.2 V
25
40
3V
45
60
2.2 V
30
50
3V
45
71
V(Ref025)
(Voltage at 0.25 VCC node) /
VCC
PCA0 = 1, CARSEL = 1, CAREF = 1,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V
0.23
0.24
0.25
V(Ref050)
(Voltage at 0.55 VCC node) /
VCC
PCA0 = 1, CARSEL = 1, CAREF = 2,
No load at P1.6/CA0 and P1.7/CA1
2.2 V, 3 V
0.47
0.48
0.5
2.2 V
390
480
540
3V
400
490
550
V(RefVT)
PCA0 = 1, CARSEL = 1, CAREF = 3,
See Figure 5-6 and Figure 5-7 No load at P1.6/CA0 and P1.7/CA1,
TA = 85°C
VIC
Common-mode input
voltage range
CAON = 1
(2)
Vp – VS
Offset voltage
See
Vhys
Input hysteresis
CAON = 1
(1)
(2)
µA
µA
mV
VCC
–1
2.2 V, 3 V
0
2.2 V, 3 V
–30
30
mV
2.2 V, 3 V
0
0.7
1.4
mV
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V
160
210
300
3V
80
150
240
TA = 25°C,
Overdrive 10 mV, with filter: CAF = 1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
TA = 25°C,
Overdrive 10 mV, without filter: CAF = 0
2.2 V
130
210
300
3V
80
150
240
TA = 25°C,
Overdrive 10 mV, with filter: CAF = 1
2.2 V
1.4
1.9
3.4
3V
0.9
1.5
2.6
t(response LH)
t(response HL)
UNIT
V
ns
µs
ns
µs
The leakage current for the Comparator_A terminals is identical to Ilkg(Px.y) specification.
The input offset voltage can be cancelled by using the CAEX bit to invert the Comparator_A inputs on successive measurements. The
two successive measurements are then summed together.
5.15 Comparator_A Typical Characteristics
650
650
VCC = 2.2 V
VREF - Reference Voltage - mV
VREF - Reference Voltage - mV
VCC = 3 V
600
Typical
550
500
450
400
-45
-25
-5
15
35
55
75
95
TA - Free-Air Temperature - °C
Figure 5-6. Reference Voltage vs Free-Air Temperature
600
Typical
550
500
450
400
-45
-25
-5
15
35
55
75
95
TA - Free-Air Temperature - °C
Figure 5-7. Reference Voltage vs Free-Air Temperature
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19
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
0V
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VCC
0
1
CAF
CAON
To Internal
Modules
Low-Pass Filter
V+
V-
+
_
0
0
1
1
CAOUT
Set CAIFG
Flag
t » 2 µs
Figure 5-8. Block Diagram of Comparator_A Module
VCAOUT
Overdrive
V-
400 mV
V+
t(response)
Figure 5-9. Overdrive Definition
20
Specifications
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.16 Power-On Reset (POR) and Brownout Reset (BOR) (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
td(BOR)
VCC(start)
dVCC/dt ≤ 3 V/s (see Figure 5-10)
V(B_IT–)
dVCC/dt ≤ 3 V/s (see Figure 5-10 through
Figure 5-12)
Brownout (2)
dVCC/dt ≤ 3 V/s (see Figure 5-10)
t(reset)
Pulse length needed at RST/NMI pin to accepted
reset internally, VCC = 2.2 V, 3 V
(2)
UNIT
2000
µs
0.7 × V(B_IT– )
Vhys(B_IT–)
(1)
MAX
70
130
V
1.71
V
210
mV
2
µs
The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–) +
Vhys(B_IT–) is ≤ 1.8 V.
During power up, the CPU begins code execution following a period of td(BOR) after VCC = V(B_IT–) + Vhys(B_IT–). The default FLL+ settings
must not be changed until VCC ≥ VCC(min), where VCC(min) is the minimum supply voltage for the desired operating frequency. See the
MSP430x4xx Family User's Guide (SLAU056) for more information on the brownout/SVS circuit.
VCC
Vhys(B_IT-)
V(B_IT-)
VCC(start)
1
0
td(BOR)
Figure 5-10. POR and BOR vs Supply Voltage
V CC
2
tpw
3V
VCC = 3 V
Typical Conditions
VCC(drop) - V
1.5
1
V CC(drop)
0.5
0
0.001
1
1000
1 ns
tpw - Pulse Width - m s
1 ns
tpw - Pulse Width - ms
Figure 5-11. VCC(drop) Level with a Square Voltage Drop to Generate a POR or BOR Signal
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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V CC
2
tpw
3V
VCC = 3 V
V C C (drop) - V
1.5
Typical Conditions
1
V CC(drop)
0.5
tf = tr
0
0.001
1
1000
tf
tr
tpw - Pulse Width - ms
tpw - Pulse Width - m s
Figure 5-12. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR or BOR Signal
5.17 Supply Voltage Supervisor (SVS) and Supply Voltage Monitor (SVM)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
dVCC/dt > 30 V/ms (see Figure 5-13)
t(SVSR)
SVS on, switch from VLD = 0 to VLD ≠ 0, VCC = 3 V
tsettle
VLD ≠ 0 (1)
V(SVSstart)
VLD ≠ 0, VCC/dt ≤ 3 V/s (see Figure 5-13)
2000
150
1.55
VLD = 1
VCC/dt ≤ 3 V/s (see Figure 5-13)
Vhys(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 5-13),
external voltage applied on A7
VCC/dt ≤ 3 V/s (see Figure 5-13)
V(SVS_IT–)
VCC/dt ≤ 3 V/s (see Figure 5-13),
external voltage applied on A7
ICC(SVS) (3)
(2)
(3)
22
MAX
150
dVCC/dt ≤ 30 V/ms
td(SVSon)
(1)
TYP
5
VLD = 2 to 14
VLD = 15
70
120
µs
12
µs
1.7
V
155
mV
V(SVS_IT–)
× 0.016
4.4
20
VLD = 1
1.8
1.9
2.05
VLD = 2
1.94
2.1
2.23
VLD = 3
2.05
2.2
2.35
VLD = 4
2.14
2.3
2.46
VLD = 5
2.24
2.4
2.58
VLD = 6
2.33
2.5
2.69
VLD = 7
2.46
2.65
2.84
VLD = 8
2.58
2.8
2.97
VLD = 9
2.69
2.9
3.10
VLD = 10
2.83
3.05
3.26
VLD = 11
2.94
3.2
3.39
VLD = 12
3.11
3.35
3.58 (2)
VLD = 13
3.24
3.5
3.73 (2)
VLD = 14
3.43
(2)
3.96 (2)
VLD = 15
1.1
1.2
1.3
10
15
VLD ≠ 0, VCC = 2.2 V, 3 V
µs
300
V(SVS_IT–)
× 0.001
3.7
UNIT
mV
V
µA
tsettle is the settling time that the comparator output needs to have a stable level after VLD is switched from VLD ≠ 0 to a different VLD
value somewhere between 2 and 15. The overdrive is assumed to be > 50 mV.
The recommended operating voltage range is limited to 3.6 V.
The current consumption of the SVS module is not included in the ICC current consumption data.
Specifications
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
VCC
V(SVS_IT-)
V(SVSstart)
Software Sets VLD>0:
SVS is Active
Vhys(SVS_IT-)
Vhys(B_IT-)
V(B_IT-)
VCC(start)
Brown
Out
Region
Brownout
Region
Brownout
1
0
SVSOut
t d(BOR)
t d(BOR)
SVS Circuit is Active From VLD > to VCC < V(B_IT-)
1
0
td(SVSon)
Set POR
1
td(SVSR)
undefined
0
Figure 5-13. SVS Reset (SVSR) vs Supply Voltage
V CC
tpw
3V
2
Rectangular Drop
V CC(drop)
V C C (drop) - V
1.5
Triangular Drop
1
1 ns
1 ns
0.5
V CC
t pw
3V
0
1
10
100
1000
tpw - Pulse Width - m s
V CC(drop)
tf = tr
tf
tr
t - Pulse Width - ms
Figure 5-14. VCC(drop) With a Square Voltage Drop and a Triangle Voltage Drop to Generate an SVS Signal
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23
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.18
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DCO
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
f(DCOCLK)
N(DCO) = 01Eh, FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2,
DCOPLUS = 0, fCrystal = 32.738 kHz
f(DCO=2)
FN_8=FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1
f(DCO=27)
FN_8 = FN_4 = FN_3 = FN_2 = 0, DCOPLUS = 1
f(DCO=2)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1
f(DCO=27)
FN_8 = FN_4 = FN_3 = FN_2 = 1, DCOPLUS = 1
f(DCO=2)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
f(DCO=27)
FN_8 = FN_4 = 0, FN_3 = 1, FN_2 = x, DCOPLUS = 1
f(DCO=2)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO=27)
FN_8 = 0, FN_4 = 1, FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO=2)
FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1
f(DCO=27)
FN_8 = 1, FN_4 = FN_3 = FN_2 = x, DCOPLUS = 1
Sn
Step size between adjacent DCO taps:
Sn = fDCO(Tap n+1) / fDCO(Tap n) (see Figure 5-16 for taps 21 to
27)
Dt
Temperature drift, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
DV
Drift with VCC variation, N(DCO) = 01Eh,
FN_8 = FN_4 = FN_3 = FN_2 = 0, D = 2, DCOPLUS = 0
MIN
TYP
2.2 V, 3 V
f(DCO)
f(DCO20°C)
MHz
2.2 V
0.3
0.65
1.25
3V
0.3
0.7
1.3
2.2 V
2.5
5.6
10.5
3V
2.7
6.1
11.3
2.2 V
0.7
1.3
2.3
3V
0.8
1.5
2.5
2.2 V
5.7
10.8
18
3V
6.5
12.1
20
2.2 V
1.2
2
3
3V
1.3
2.2
3.5
9
15.5
25
3V
10.3
17.9
28.5
2.2 V
1.8
2.8
4.2
3V
2.1
3.4
5.2
2.2 V
13.5
21.5
33
3V
16
26.6
41
2.2 V
2.8
4.2
6.2
3V
4.2
6.3
9.2
2.2 V
21
32
46
3V
30
46
70
1 < TAP ≤ 20
1.06
1.11
TAP = 27
1.07
1.17
2.2 V
–0.2
–0.3
–0.4
3V
–0.2
–0.3
–0.4
0
5
15
2.2 V, 3 V
f(DCO)
1.0
UNIT
1
2.2 V
f(DCO3V)
MAX
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
%/°C
%/V
1.0
0
1.8
2.4
3.0
3.6
-40
-20
0
20
40
60
85
TA - ° C
VCC - V
Figure 5-15. DCO Frequency vs Supply Voltage VCC and vs Ambient Temperature
24
Specifications
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S n - S tepsize R atio betw een D C O Taps
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1.17
Max
1.11
1.07
1.06
Min
1
20
27
DCO Tap
Figure 5-16. DCO Tap Step Size
Legend
f(DCO)
Tolerance at Tap 27
DCO Frequency
Adjusted by Bits
9
5
2 to 2 in SCFI1 {N{DCO}}
Tolerance at Tap 2
Overlapping DCO Ranges:
Uninterrupted Frequency Range
FN_2=0
FN_3=0
FN_4=0
FN_8=0
FN_2=1
FN_3=0
FN_4=0
FN_8=0
FN_2=x
FN_3=1
FN_4=0
FN_8=0
FN_2=x
FN_3=x
FN_4=1
FN_8=0
FN_2=x
FN_3=x
FN_4=x
FN_8=1
Figure 5-17. Five Overlapping DCO Ranges Controlled by FN_x Bits
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25
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.19
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Crystal Oscillator, XT1 Oscillator (1)
(2)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CXIN
CXOUT
TEST CONDITIONS
Integrated input capacitance (3)
Integrated output capacitance (3)
MIN
TYP
OSCCAPx = 0h, VCC = 2.2 V, 3 V
0
OSCCAPx = 1h, VCC = 2.2 V, 3 V
10
OSCCAPx = 2h, VCC = 2.2 V, 3 V
14
OSCCAPx = 3h, VCC = 2.2 V, 3 V
18
OSCCAPx = 0h, VCC = 2.2 V, 3 V
0
OSCCAPx = 1h, VCC = 2.2 V, 3 V
10
OSCCAPx = 2h, VCC = 2.2 V, 3 V
14
OSCCAPx = 3h, VCC = 2.2 V, 3 V
VIL
(1)
(2)
(3)
(4)
UNIT
pF
pF
18
VCC = 2.2 V, 3 V (4)
Input levels at XIN
VIH
MAX
VSS
0.2 × VCC
0.8 × VCC
VCC
V
The parasitic capacitance from the package and board may be estimated to be 2 pF. The effective load capacitor for the crystal is (CXIN
× CXOUT) / (CXIN+ CXOUT). This is independent of XTS_FLL.
To improve EMI on the low-power LFXT1 oscillator, particularly in the LF mode (32 kHz), the following guidelines should be observed.
• Keep the trace between the device and the crystal as short as possible.
• Design a good ground plane around the oscillator pins.
• Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT.
• Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.
• Use assembly materials and processes that avoid any parasitic load on the oscillator XIN and XOUT pins.
• If conformal coating is used, make sure that it does not induce capacitive or resistive leakage between the oscillator pins.
• Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This
signal is no longer required for the serial programming adapter.
External capacitance is recommended for precision real-time clock applications, OSCCAPx = 0h.
Applies only when using an external logic-level clock source. XTS_FLL must be set. Not applicable when using a crystal or resonator.
5.20
Crystal Oscillator, XT2 Oscillator (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
CXT2IN
TEST CONDITIONS
Integrated input capacitance
CXT2OUT Integrated output capacitance
VIL
Input levels at XT2IN
VIH
(1)
(2)
MIN
TYP
VCC = 2.2 V, 3 V
2
VCC = 2.2 V, 3 V
2
VCC = 2.2 V, 3 V (2)
MAX
UNIT
pF
pF
VSS
0.2 × VCC
V
0.8 × VCC
VCC
V
The oscillator needs capacitors at both terminals, with values specified by the crystal manufacturer.
Applies only when using an external logic-level clock source. Not applicable when using a crystal or resonator.
5.21
USART0 (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
t(τ)
(1)
26
USART0 deglitch time
TEST CONDITIONS
MIN
TYP
MAX
VCC = 2.2 V, SYNC = 0, UART mode
200
430
800
VCC = 3 V, SYNC = 0, UART mode
150
280
500
UNIT
ns
The signal applied to the USART0 receive signal/terminal (URXD0) should meet the timing requirements of t(τ) to ensure that the URXS
flip-flop is set. The URXS flip-flop is set with negative pulses meeting the minimum timing condition of t(τ). The operating conditions to
set the flag must be met independently from this timing constraint. The deglitch circuitry is active only on negative transitions on the
URXD0 line.
Specifications
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5.22
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
12-Bit ADC, Power Supply and Input Range Conditions (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
AVCC
Analog supply voltage
AVCC and DVCC are connected together,
AVSS and DVSS are connected together,
V(AVSS) = V(DVSS) = 0 V
V(P6.x/Ax)
Analog input voltage range (2)
All external Ax terminals, Analog inputs selected in
ADC12MCTLx register and P6Sel.x = 1,
V(AVSS) ≤ VAx ≤ V(AVCC)
IADC12
Operating supply current into the
AVCC terminal (3)
fADC12CLK = 5.0 MHz,
ADC12ON = 1, REFON = 0,
SHT0 = 0, SHT1 = 0, ADC12DIV = 0
IREF+
Operating supply current into the
AVCC terminal (4)
fADC12CLK = 5.0 MHz,
ADC12ON = 0,
REFON = 1, REF2_5V = 1
fADC12CLK = 5.0 MHz,
ADC12ON = 0
REFON = 1, REF2_5V = 0
MAX
3.6
V
0
VAVCC
V
0.65
1.3
VCC = 3 V
0.8
1.6
VCC = 3 V
0.5
0.8
VCC = 2.2 V
0.5
0.8
VCC = 3 V
0.5
0.8
Input capacitance
Only one terminal can be selected at one
VCC = 2.2 V
time, Ax
RI
Input MUX ON resistance
0 V ≤ VAx ≤ VAVCC
UNIT
2.2
VCC = 2.2 V
CI
(1)
(2)
(3)
(4)
TYP
VCC = 3 V
mA
mA
mA
40
pF
2000
Ω
The leakage current is defined in the leakage current table with Ax parameter.
The analog input voltage range must be within the selected reference voltage range VR+ to VR– for valid conversion results.
The internal reference supply current is not included in current consumption parameter IADC12.
The internal reference current is supplied via terminal AVCC. Consumption is independent of the ADC12ON control bit, unless a
conversion is active. The REFON bit enables to settle the built-in reference before starting an A/D conversion.
5.23
12-Bit ADC, External Reference (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VeREF+
Positive external reference
voltage input
VeREF+ > VREF–/VeREF–
(2)
1.4
VAVCC
V
VREF–/VeREF–
Negative external reference
voltage input
VeREF+ > VREF–/VeREF–
(3)
0
1.2
V
(VeREF+ –
VREF–/VeREF–)
Differential external reference
voltage input
VeREF+ > VREF–/VeREF–
(4)
1.4
VAVCC
V
IVeREF+
Static input current
0 V ≤ VeREF+ ≤ VAVCC
VCC = 2.2 V, 3 V
±1
µA
IVREF–/VeREF–
Static input current
0 V ≤ VeREF– ≤ VAVCC
VCC = 2.2 V, 3 V
±1
µA
(1)
(2)
(3)
(4)
The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the
dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the
recommendations on analog-source impedance to allow the charge to settle for 12-bit accuracy.
The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced
accuracy requirements.
The accuracy limits minimum external differential reference voltage. Lower differential reference voltage levels may be applied with
reduced accuracy requirements.
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.24
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12-Bit ADC, Built-In Reference
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
Positive built in reference
voltage output
VREF+
TEST CONDITIONS
VCC
MIN
TYP
MAX
REF2_5V = 1 for 2.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
3V
2.4
2.5
2.6
REF2_5V = 0 for 1.5 V,
IVREF+max ≤ IVREF+ ≤ IVREF+min
2.2 V, 3 V
1.44
1.5
1.56
V
REF2_5V = 0,
IVREF+max ≤ IVREF+ ≤ IVREF+min
AVCC(min)
2.2
AVCC minimum voltage,
REF2_5V = 1,
Positive built in reference active IVREF+min ≥ IVREF+ ≥ –0.5 mA
2.8
REF2_5V = 1,
IVREF+min ≥ IVREF+ ≥ – 1 mA
IL(VREF)+
Load-current regulation, VREF+
terminal
IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 0.75 V,
REF2_5V = 0
–0.5
3V
0.01
–1
mA
3V
±2
IVREF+ = 500 µA ± 100 µA,
Analog input voltage ≈ 1.25 V,
REF2_5V = 1
3V
±2
LSB
IVREF+ = 100 µA → 900 µA,
CVREF+ = 5 µF, ax ≈ 0.5 × VREF+,
Error of conversion result ≤ 1 LSB
3V
20
ns
CVREF+
Capacitance at pin VREF+
TREF+
Temperature coefficient of built- IVREF+ is a constant in the range of
in reference
0 mA ≤ IVREF+ ≤ 1 mA
tREFON
Settle time of internal reference IVREF+ = 0.5 mA, CVREF+ = 10 µF,
voltage (see Figure 5-18 ) (2)
VREF+ = 1.5 V, VAVCC = 2.2 V
(2)
0.01
±2
Load current regulation, VREF+
terminal
(1)
2.2 V
2.2 V
IDL(VREF)+
(1)
V
2.9
Load current out of VREF+
terminal
IVREF+
UNIT
REFON =1,
0 mA ≤ IVREF+ ≤ IVREF+max
2.2 V, 3 V
5
10
2.2 V, 3 V
LSB
µF
±100 ppm/°C
17
ms
The internal buffer operational amplifier and the accuracy specifications require an external capacitor. All INL and DNL tests uses two
capacitors between pins VREF+ and AVSS and VREF-–/VeREF– and AVSS: 10 µF tantalum and 100 nF ceramic.
The condition is that the error in a conversion started after tREFON is less than ±0.5 LSB. The settling time depends on the external
capacitive load.
CVREF+
100 mF
tREFON » .66 x CVREF+ [ms] with CVREF+ in mF
10 mF
1 mF
0
1 ms
10 ms
100 ms
tREFON
Figure 5-18. Typical Settling Time of Internal Reference tREFON vs External Capacitor on VREF+
28
Specifications
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DV CC1/2
+
-
From Power Supply
DV SS1/2
10µF
100 nF
AVCC
+
-
MSP430FG43x
AVSS
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
10µF
100 nF
VREF+ or V eREF+
+
10µF
100 nF
Apply External Reference
VREF -/V eREF-
+
10µF
100 nF
Figure 5-19. Supply Voltage and Reference Voltage Design VREF–/VeREF– External Supply
DV CC1/2
From Power Supply
+
DV SS1/2
10µF
100 nF
AVCC
+
-
MSP430FG43x
AVSS
Apply External Reference [VeREF+]
or Use Internal Reference [VREF+]
Reference Is Internally
Switched to AVSS
10µ F
100 nF
VREF+ or VeREF+
+
10µF
100 nF
VREF- /VeREF-
Figure 5-20. Supply Voltage and Reference Voltage Design VREF–/VeREF– = AVSS, Internally Connected
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29
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5.25
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12-Bit ADC, Timing Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
TYP
MAX
UNIT
fADC12CLK
ADC12 clock frequency
For specified performance of ADC12
linearity parameters
2.2 V, 3 V
0.45
5
6.3
MHz
fADC12OSC
Internal ADC12 oscillator
ADC12DIV = 0, fADC12CLK = fADC12OSC
2.2 V, 3 V
3.7
5
6.3
MHz
CVREF+ ≥ 5 µF, Internal oscillator,
fADC12OSC = 3.7 MHz to 6.3 MHz
2.2 V, 3 V
2.06
3.51
µs
tCONVERT
Conversion time
tADC12ON
Turn on settling time of
the ADC
See
tSample
Sampling time
RS = 400 Ω,RI = 1000 Ω,
CI = 30 pF, τ = [RS +RI] × CI
(1)
(2)
13 ×
ADC12DIV ×
1/fADC12CLK
External fADC12CLK from ACLK, MCLK, or
SMCLK, ADC12SSEL ≠ 0
(1)
µs
100
(2)
3V
1220
2.2 V
1400
ns
ns
The condition is that the error in a conversion started after tADC12ON is less than ±0.5 LSB. The reference and input signal are already
settled.
Approximately ten Tau (τ) are needed to get an error of less than ±0.5 LSB:
tSample = ln(2n+1) × (RS + RI) x CI + 800 ns, where n = ADC resolution = 12, RS = external source resistance.
5.26
12-Bit ADC, Linearity Parameters
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
1.4 V ≤ (VeREF+ – VREF–/VeREF–) min ≤ 1.6 V
VCC
EI
Integral linearity error
ED
Differential linearity error
(VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EO
Offset error
(VeREF+ – VREF–/VeREF–) min ≤ (VeREF+ – VREF–/VeREF–),
Internal impedance of source RS < 100 Ω,
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
2.2 V, 3 V
EG
Gain error
(VeREF+ – VREF–/VeREF–)min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ =10 µF (tantalum) and 100 nF (ceramic)
ET
Total unadjusted error
(VeREF+ – VREF–/VeREF– )min ≤ (VeREF+ – VREF–/VeREF–),
CVREF+ = 10 µF (tantalum) and 100 nF (ceramic)
30
Specifications
1.6 V < (VeREF+ – VREF–/VeREF–) min ≤ VAVCC
MIN
TYP
MAX
±2
2.2 V, 3 V
±1.7
UNIT
LSB
±1
LSB
±2
±4
LSB
2.2 V, 3 V
±1.1
±2
LSB
2.2 V, 3 V
±2
±5
LSB
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.27 12-Bit ADC, Temperature Sensor and Built-In VMID
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TYP
MAX
2.2 V
40
120
3V
60
160
ADC12ON = 1, INCH = 0Ah,
TA = 0°C
2.2 V,
3V
986
ADC12ON = 1, INCH = 0Ah
2.2 V,
3V
3.55 ± 3%
ISENSOR
Operating supply current into REFON = 0, INCH = 0Ah,
AVCC terminal (1)
ADC12ON = NA, TA = 25°C
VSENSOR
See
(2)
TCSENSOR
tSENSOR(sample)
Sample time required if
channel 10 is selected (3)
ADC12ON = 1, INCH = 0Ah,
Error of conversion result ≤ 1 LSB
IVMID
Current into divider at
channel 11 (4)
ADC12ON = 1, INCH = 0Bh
AVCC divider at channel 11
ADC12ON = 1, INCH = 0Bh,
VMID ≈ 0.5 × VAVCC
VMID
tVMID(sample)
(1)
(2)
(3)
(4)
(5)
Sample time required if
channel 11 is selected (5)
ADC12ON = 1, INCH = 0Bh,
Error of conversion result ≤ 1 LSB
VCC
MIN
2.2 V
30
3V
30
mV/°C
µs
NA
3V
NA
2.2 V
1.1
1.10 ±
0.04
3V
1.5
1.50 ±
0.04
1400
3V
1220
µA
mV
2.2 V
2.2 V
UNIT
µA
V
ns
The sensor current ISENSOR is consumed if (ADC12ON = 1 and REFON = 1), or (ADC12ON = 1 AND INCH = 0Ah and sample signal is
high). When REFON = 1, ISENSOR is already included in IREF+.
The temperature sensor offset can be as much as ±20°C. A single-point calibration is recommended in order to minimize the offset error
of the built-in temperature sensor.
The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on)
No additional current is needed. The VMID is used during sampling.
The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.
5.28 12-Bit DAC, Supply Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
AVCC
TEST CONDITIONS
Analog supply voltage
VCC
AVCC = DVCC, AVSS = DVSS = 0 V
IDD
DAC12AMPx = 2, DAC12IR = 1,
DAC12_xDAT = 0800h , VeREF+ = VREF+ = AVCC
DAC12AMPx = 5, DAC12IR = 1,
DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC
2.2 V,
3V
DAC12AMPx = 7, DAC12IR = 1,
DAC12_xDAT = 0800h, VeREF+ = VREF+ = AVCC
PSRR Power-supply rejection ratio (3)
(1)
(2)
(3)
(4)
(4)
DAC12_xDAT = 0800h, VREF = 1.5 V,
ΔAVCC = 100 mV
DAC12_xDAT = 0800h, VREF = 1.5 V or 2.5 V,
ΔAVCC = 100 mV
TYP
2.2
DAC12AMPx = 2, DAC12IR = 0,
DAC12_xDAT = 0800h
Supply current, single DAC
channel (1) (2)
MIN
MAX
3.6
50
110
50
110
200
440
700
1500
UNIT
V
µA
2.2 V
70
dB
3V
No load at the output pin, DAC0 or DAC1, assuming that the control bits for the shared pins are set properly.
Current into reference terminals not included. If DAC12IR = 1, current flows through the input divider (see Reference Input
specifications).
PSRR = 20 × log(ΔAVCC / ΔVDAC12_xOUT).
VREF is applied externally. The internal reference is not used.
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5.29 12-Bit DAC, Linearity Specifications
over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5-21)
PARAMETER
TEST CONDITIONS
Resolution
DNL
MIN
12-bit monotonic
Integral nonlinearity (1)
INL
VCC
Differential nonlinearity
(1)
Offset voltage without calibration
(1) (2)
EO
Offset voltage with calibration (1)
(2)
dE(O)/dT
Offset error temperature coefficient (1)
EG
Gain error (1)
dE(G)/dT
Gain temperature coefficient (1)
tOffset Cal
Time for offset calibration (3)
TYP
12
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
Vref = 1.5 V,
DAC12AMPx = 7, DAC12IR = 1
2.2 V
Vref = 2.5 V,
DAC12AMPx = 7, DAC12IR = 1
3V
±2.0
±8.0
LSB
±0.4
±1.0
LSB
±21
mV
±2.5
2.2 V, 3 V
VREF = 1.5 V
2.2 V
VREF = 2.5 V
3V
±30
µV/°C
±3.5
2.2 V, 3 V
%FSR
ppm of
FSR/°C
10
100
DAC12AMPx = 3, 5
2.2 V, 3 V
32
DAC12AMPx = 4, 6, 7
(2)
(3)
UNIT
bits
DAC12AMPx = 2
(1)
MAX
ms
6
Parameters calculated from the best-fit curve from 0x0A to 0xFFF. The best-fit curve method is used to deliver coefficients "a" and "b" of
the first-order equation: y = a + b × x. VDAC12_xOUT = EO + (1 + EG) × (VeREF+ / 4095) × DAC12_xDAT, DAC12IR = 1.
The offset calibration works on the output operational amplifier. Offset Calibration is triggered setting bit DAC12CALON.
The offset calibration can be done if DAC12AMPx = {2, 3, 4, 5, 6, 7}. The output operational amplifier is switched off with DAC12AMPx =
{0, 1}. It is recommended that the DAC12 module be configured prior to initiating calibration. Port activity during calibration may affect
accuracy and is not recommended.
DAC VOUT
DAC Output
V R+
R Load =
Ideal transfer
function
AVCC
2
Offset Error
C Load = 100pF
Gain Error
Positive
Negative
DAC Code
Figure 5-21. Linearity Test Load Conditions and Gain/Offset Definition
32
Specifications
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INL - Integral Nonlinearity Error - LSB
4
VCC = 2.2 V, V REF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
3
2
1
0
-1
-2
-3
-4
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT - Digital Code
Figure 5-22. Typical INL Error vs Digital Input Data
DNL - Differential Nonlinearity Error - LSB
2.0
VCC = 2.2 V, V REF = 1.5V
DAC12AMPx = 7
DAC12IR = 1
1.5
1.0
0.5
0.0
-0.5
-1.0
-1.5
-2.0
0
512
1024
1536
2048
2560
3072
3584
4095
DAC12_xDAT - Digital Code
Figure 5-23. Typical DNL Error vs Digital Input Data
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5.30 12-Bit DAC, Output Specifications
over recommended operating free-air temperature (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
Output voltage range (1)
(see Figure 5-24)
VO
No Load, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
2.2 V,
3V
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0h, DAC12IR = 1,
DAC12AMPx = 7
RLoad = 3 kΩ, VeREF+ = AVCC,
DAC12_xDAT = 0FFFh, DAC12IR = 1,
DAC12AMPx = 7
TYP
MAX
0
0.005
AVCC –
0.05
AVCC
V
0
0.1
AVCC –
0.13
AVCC
CL(DAC12)
Maximum DAC12 load
capacitance
2.2 V,
3V
IL(DAC12)
Maximum DAC12 load
current
2.2 V
–0.5
+0.5
3V
–1.0
+1.0
RLoad = 3 kΩ, VO/P(DAC12) < 0.3 V,
DAC12AMPx = 7, DAC12_xDAT = 0h
RO/P(DAC12)
Output resistance (see
Figure 5-24)
RLoad = 3 kΩ,
VO/P(DAC12) > AVCC – 0.3 V,
DAC12AMPx = 7, DAC12_xDAT = 0FFFh
2.2 V,
3V
RLoad = 3 kΩ,
0.3 V ≤ VO/P(DAC12) ≤ AVCC – 0.3 V
DAC12AMPx = 7
(1)
UNIT
100
150
250
150
250
1
4
pF
mA
Ω
Data is valid after the offset calibration of the output amplifier.
R O/P(DAC12_x)
I Load
Max
R Load
AVCC
DAC12
2
O/P(DAC12_x)
C Load = 100pF
Min
0.3
AVCC -0.3V
V OUT
AVCC
Figure 5-24. DAC12_x Output Resistance Tests
34
Specifications
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
5.31 12-Bit DAC, Reference Input Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VCC
MIN
(1) (2)
Reference input voltage DAC12IR = 0
range
DAC12IR = 1 (3)
VeREF+
Ri(VREF+),
(Ri(VeREF+)
Reference input
resistance
2.2 V, 3 V
(4)
MAX
AVCC / 3
AVCC + 0.2
AVCC
AVCC + 0.2
DAC12_0 IR = DAC12_1 IR = 0
20
DAC12_0 IR = 1, DAC12_1 IR = 0
40
48
56
40
48
56
20
24
28
2.2 V, 3 V
DAC12_0 IR = 0, DAC12_1 IR = 1
DAC12_0 IR = DAC12_1 IR =1,
DAC12_0 SREFx = DAC12_1 SREFx (5)
(1)
(2)
(3)
(4)
(5)
TYP
UNIT
V
MΩ
kΩ
For a full-scale output, the reference input voltage can be as high as 1/3 of the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / [3 × (1 + EG)].
For a full-scale output, the reference input voltage can be as high as the maximum output voltage swing (AVCC).
The maximum voltage applied at reference input voltage terminal VeREF+ = [AVCC – VE(O)] / (1 + EG).
When DAC12IR = 1 and DAC12SREFx = 0 or 1 for both channels, the reference input resistive dividers for each DAC are in parallel,
reducing the reference input resistance.
5.32 12-Bit DAC, Dynamic Specifications
Vref = VCC, DAC12IR = 1, over recommended operating free-air temperature range (unless otherwise noted) (see Figure 5-25
and Figure 5-26)
PARAMETER
tON
TEST CONDITIONS
DAC12_xDAT = 800h,
ErrorV(O) < ±0.5 LSB (1)
(see Figure 5-25)
DAC12 on time
VCC
MIN
DAC12AMPx = 0 → {2, 3, 4}
DAC12AMPx = 0 → {5, 6}
2.2 V, 3 V
DAC12AMPx = 0 → 7
DAC12AMPx = 2
tS(FS)
Settling time,
full scale
DAC12_xDAT =
80h→F7Fh→80h
DAC12AMPx = 3, 5
2.2 V, 3 V
DAC12AMPx = 4, 6, 7
tS(C–C)
DAC12AMPx = 2
DAC12_xDAT =
3F8h→408h→3F8h
BF8h→C08h→BF8h
Settling time,
code to code
2.2 V, 3 V
DAC12AMPx = 3, 5
2.2 V, 3 V
12
200
40
80
15
30
0.12
0.35
0.7
1.5
2.7
µs
µs
µs
V/µs
10
DAC12AMPx = 3, 5
2.2 V, 3 V
10
DAC12AMPx = 4, 6, 7
(1)
(2)
6
100
0.05
DAC12AMPx = 2
DAC12_xDAT =
80h→ F7Fh→ 80h
30
1
DAC12AMPx = 4, 6, 7
Glitch energy,
full scale
120
15
2
DAC12AMPx = 4, 6, 7
DAC12_xDAT =
80h→ F7Fh→ 80h (2)
Slew rate
60
5
DAC12AMPx = 3, 5
DAC12AMPx = 2
SR
TYP MAX UNIT
nV-s
10
RLoad and CLoad connected to AVSS (not AVCC/2) in Figure 5-25.
Slew rate applies to output voltage steps ≥ 200 mV.
Conversion 1
V OUT
DAC Output
I Load
R Load = 3 k W
Glitch
Energy
Conversion 2
Conversion 3
+/- 1/2 LSB
AVCC
2
R O/P(DAC12.x)
+/- 1/2 LSB
C Load = 100pF
t settleLH
t settleHL
Figure 5-25. Settling Time and Glitch Energy Testing
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Conversion 1
Conversion 2
Conversion 3
V OUT
90%
90%
10%
10%
t SRLH
t SRHL
Figure 5-26. Slew Rate Testing
5.33 12-Bit DAC, Dynamic Specifications (Continued)
TA = 25°C unless otherwise noted
PARAMETER
TEST CONDITIONS
VCC
MIN
DAC12AMPx = {2, 3, 4}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
3-dB bandwidth,
VDC = 1.5 V, VAC = 0.1 VPP
(see Figure 5-27)
BW–3dB
2.2 V, 3 V
180
DAC12AMPx = 7, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
(1)
MAX
UNIT
40
DAC12AMPx = {5, 6}, DAC12SREFx = 2,
DAC12IR = 1, DAC12_xDAT = 800h
kHz
550
DAC12_0DAT = 800h, No Load,
DAC12_1DAT = 80h↔F7Fh, RLoad = 3 kΩ
fDAC12_1OUT = 10 kHz with 50/50 duty cycle
Channel-to-channel
crosstalk (1)
(see Figure 5-28)
TYP
–80
2.2 V, 3 V
DAC12_0DAT = 80h↔F7Fh, RLoad = 3 kΩ,
DAC12_1DAT = 800h, No Load,
fDAC12_0OUT = 10 kHz with 50/50 duty cycle
dB
–80
RLOAD = 3 kΩ, CLOAD = 100 pF
I Load
VeREF+
R Load = 3 k W
AVCC
DAC12_x
2
DACx
AC
C Load = 100pF
DC
Figure 5-27. Test Conditions for 3-dB Bandwidth Specification
I Load
R Load
AVCC
2
DAC12_0
DAC0
DAC12_xDAT
080h
7F7h
080h
7F7h
080h
V OUT
C Load = 100pF
VREF+
I Load
V DAC12_yOUT
R Load
AVCC
2
DAC12_1
DAC1
V DAC12_xOUT
f Toggle
C Load = 100pF
Figure 5-28. Crosstalk Test Conditions
36
Specifications
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5.34 Operational Amplifier (OA), Supply Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC
TEST CONDITIONS
VCC
MIN
TYP
MAX
Fast Mode, RRIP OFF
180
290
Medium Mode, RRIP OFF
110
190
50
80
300
490
190
350
90
190
Supply voltage
2.2
Slow Mode, RRIP OFF
Supply current (1)
ICC
2.2 V, 3 V
Fast Mode, RRIP ON
Medium Mode, RRIP ON
Slow Mode, RRIP ON
PSRR Power supply rejection ratio
(1)
Non-inverting
2.2 V, 3 V
UNIT
3.6
V
µA
70
dB
P6SEL.x = 1 for each corresponding pin when used in OA input or OA output mode.
5.35 Operational Amplifier (OA), Input/Output Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
VI/P
Voltage supply, I/P
IIkg
Input leakage current,
I/P (1) (2)
VCC
MIN
VCC – 1.2
RRIP ON
–0.1
VCC + 0.1
TA = –40°C to +55°C
–5
±0.5
5
TA = +55°C to +85°C
–20
±5
20
Medium Mode
Voltage noise density, I/P
140
Fast Mode
30
fV(I/P) = 10 kHz
Offset voltage, I/P
nV/√Hz
65
±10
Offset temperature drift,
I/P
See
Offset voltage drift with
supply, I/P
0.3 V ≤ VIN ≤ VCC – 0.3 V
ΔVCC ≤ ±10%, TA = 25°C
VOH
High-level output voltage,
O/P
Fast Mode, ISOURCE ≤ –500 µA
2.2 V
VCC – 0.2
VCC
Slow Mode, ISOURCE ≤ –150 µA
3V
VCC – 0.1
VCC
VOL
Low-level output voltage,
O/P
Fast Mode, ISOURCE ≤ +500 µA
2.2 V
VSS
0.2
Slow Mode, ISOURCE ≤ +150 µA
3V
VSS
0.1
(3)
2.2 V, 3 V
±10
2.2 V, 3 V
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
VO/P(OAx) > AVCC – 0.2 V
2.2 V, 3 V
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
0.2 V ≤ VO/P(OAx) ≤ AVCC – 0.2 V
(1)
(2)
(3)
(4)
Common-mode rejection
ratio
Non-inverting
2.2 V, 3 V
mV
µV/°C
±1.5
RLoad = 3 kΩ,CLoad = 50 pF, RRIP ON,
VO/P(OAx) < 0.2 V
CMRR
nA
50
2.2 V, 3 V
Output resistance (4) (see
Figure 5-29)
V
80
fV(I/P) = 1 kHz
Slow Mode
RO/P (OAx)
UNIT
50
Slow Mode
Medium Mode
VIO
MAX
–0.1
Fast Mode
Vn
TYP
RRIP OFF
150
250
150
250
0.1
4
mV/V
70
V
V
Ω
dB
ESD damage can degrade input current leakage.
The input bias current is overridden by the input leakage current.
Calculated using the box method.
Specification valid for voltage-follower OAx configuration.
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R O/P(OAx)
Max
R Load
I Load
AVCC
2
OAx
C Load
O/P(OAx)
Min
0.2V
AVCC -0.2V AV
V OUT
CC
Figure 5-29. OAx Output Resistance Tests
5.36 Operational Amplifier (OA), Dynamic Specifications
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
SR
TEST CONDITIONS
Slew rate
VCC
MIN
Fast Mode
1.2
Medium Mode
0.8
Slow Mode
0.3
Open-loop voltage gain
φm
GBW
TYP
MAX
UNIT
V/µs
100
dB
Phase margin
CL = 50 pF
60
deg
Gain margin
CL = 50 pF
20
dB
Non-inverting, Fast Mode,
RL = 47 kΩ,CL = 50 pF
2.2
Gain-bandwidth product
(see Figure 5-30 and Figure 5-31)
1.4
Non-inverting, Medium Mode,
RL = 300 kΩ, CL = 50 pF
2.2 V, 3 V
MHz
0.5
Non-inverting, Slow Mode,
RL = 300 kΩ, CL = 50 pF
ten(on)
Enable time on
ten(off)
Enable time off
ton, non-inverting, Gain = 1
2.2 V, 3 V
10
2.2 V, 3 V
20
µs
1
µs
5.37 OA Dynamic Specifications Typical Characteristics
0
140
120
Fast Mode
100
-50
80
Phase - degrees
Medium Mode
Gain = dB
60
40
20
0
Slow Mode
Fast Mode
-100
Medium Mode
-150
Slow Mode
-20
-200
-40
-60
-80
0.001
0.01
0.1
1
10
100
1000 10000
Input Frequency - kHz
Figure 5-30. Typical Open-Loop Gain vs Frequency
38
Specifications
-250
1
10
100
1000
10000
Input Frequency - kHz
Figure 5-31. Typical Phase vs Frequency
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5.38
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
Flash Memory
over recommended operating free-air temperature range (unless otherwise noted)
TEST
CONDITIONS
PARAMETER
VCC
MIN
TYP
MAX
UNIT
VCC(PGM/ ERASE)
Program and erase supply voltage
2.7
3.6
V
fFTG
Flash timing generator frequency
257
476
kHz
IPGM
Supply current from DVCC during program
5
mA
IERASE
Supply current from DVCC during erase
7
mA
tCPT
Cumulative program time
See
(1)
2.7 V, 3.6 V
10
ms
tCMErase
Cumulative mass erase time
See
(2)
2.7 V, 3.6 V
2.7 V, 3.6 V
3
2.7 V, 3.6 V
3
200
4
Program and erase endurance
10
10
tRetention
Data retention duration
tWord
Word or byte program time
35
Block program time for first byte or word
30
tBlock,
0
TJ = 25°C
ms
5
years
tBlock, 1-63
Block program time for each additional byte or
word
tBlock, End
Block program end-sequence wait time
tMass Erase
Mass erase time
5297
tSeg Erase
Segment erase time
4819
(1)
(2)
(3)
See
cycles
100
21
(3)
tFTG
6
The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming
methods: individual word or byte write and block write modes.
The mass erase duration generated by the flash timing generator is at least 11.1 ms ( = 5297 × 1/fFTG,max = 5297 × 1 / 476 kHz). To
achieve the required cumulative mass erase time the Flash Controller's mass erase operation can be repeated until this time is met. (A
worst case minimum of 19 cycles are required).
These values are hard-wired into the flash controller's state machine (tFTG = 1 / fFTG).
5.39 JTAG Interface
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
TEST CONDITIONS
fTCK
TCK input frequency
See
(1)
RInternal
Internal pullup resistance on TMS, TCK, TDI/TCLK
See
(2)
(1)
(2)
MAX
UNIT
2.2 V
VCC
MIN
0
TYP
5
MHz
3V
0
10
MHz
2.2 V, 3 V
25
90
kΩ
60
fTCK may be restricted to meet the timing requirements of the module selected.
TMS, TDI/TCLK, and TCK pullup resistors are implemented in all versions.
5.40 JTAG Fuse (1)
over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER
VCC(FB)
Supply voltage during fuse-blow condition
VFB
Voltage level on TDI/TCLK for fuse-blow
IFB
Supply current into TDI/TCLK during fuse blow
tFB
Time to blow fuse
(1)
TEST CONDITIONS
TA = 25°C
MIN
MAX
2.5
6
UNIT
V
7
V
100
mA
1
ms
After the fuse is blown, no further access to the MSP430 JTAG/Test and emulation features is possible. The JTAG block is switched to
bypass mode.
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6 Detailed Description
6.1
CPU
The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All
operations, other than program-flow instructions, are performed as register operations in conjunction with
seven addressing modes for source operand and four addressing modes for destination operand.
The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-toregister operation execution time is one cycle of the CPU clock.
Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and
constant generator respectively. The remaining registers are general-purpose registers.
Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all
instructions.
Program Counter
PC/R0
Stack Pointer
SP/R1
Status Register
Constant Generator
40
Detailed Description
SR/CG1/R2
CG2/R3
General-Purpose Register
R4
General-Purpose Register
R5
General-Purpose Register
R6
General-Purpose Register
R7
General-Purpose Register
R8
General-Purpose Register
R9
General-Purpose Register
R10
General-Purpose Register
R11
General-Purpose Register
R12
General-Purpose Register
R13
General-Purpose Register
R14
General-Purpose Register
R15
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6.2
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
Instruction Set
The instruction set consists of the original 51 instructions with three formats and seven address modes
and additional instructions for the expanded address range. Each instruction can operate on word and
byte data. Table 6-1 shows examples of the three types of instruction formats; Table 6-2 lists the address
modes.
Table 6-1. Instruction Word Formats
INSTRUCTION FORMAT
EXAMPLE
OPERATION
Dual operands, source-destination
ADD R4,R5
R4 + R5 → R5
Single operands, destination only
CALL R8
PC→(TOS), R8 →PC
Relative jump, un/conditional
JNE
Jump-on-equal bit = 0
Table 6-2. Address Mode Descriptions
(1)
ADDRESS MODE
S (1)
D (1)
SYNTAX
EXAMPLE
Register
✓
✓
MOV Rs,Rd
MOV R10,R11
R10 → R11
Indexed
✓
✓
MOV X(Rn),Y(Rm)
MOV 2(R5),6(R6)
M(2+R5)→ M(6+R6)
Symbolic (PC relative)
✓
✓
MOV EDE,TONI
Absolute
✓
✓
MOV & MEM, & TCDAT
Indirect
✓
MOV @Rn,Y(Rm)
MOV @R10,Tab(R6)
M(R10) → M(Tab+R6)
Indirect autoincrement
✓
MOV @Rn+,Rm
MOV @R10+,R11
M(R10) → R11
R10 + 2→ R10
Immediate
✓
MOV #X,TONI
MOV #45,TONI
#45 → M(TONI)
OPERATION
M(EDE) → M(TONI)
M(MEM) → M(TCDAT)
S = source D = destination
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Operating Modes
The MSP430 has one active mode and five software-selectable low-power modes of operation. An
interrupt event can wake up the device from any of the five low-power modes, service the request, and
restore back to the low-power mode on return from the interrupt program.
The following six operating modes can be configured by software:
• Active mode (AM)
– All clocks are active
• Low-power mode 0 (LPM0)
– CPU is disabled
– ACLK and SMCLK remain active. MCLK is disabled
– FLL+ loop control remains active
• Low-power mode 1 (LPM1)
– CPU is disabled
– FLL+ loop control is disabled
– ACLK and SMCLK remain active. MCLK is disabled
• Low-power mode 2 (LPM2)
– CPU is disabled
– MCLK, FLL+ loop control and DCOCLK are disabled
– DCO's dc-generator remains enabled
– ACLK remains active
• Low-power mode 3 (LPM3)
– CPU is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– ACLK remains active
• Low-power mode 4 (LPM4)
– CPU is disabled
– ACLK is disabled
– MCLK, FLL+ loop control, and DCOCLK are disabled
– DCO's dc-generator is disabled
– Crystal oscillator is stopped
42
Detailed Description
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6.4
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
Interrupt Vector Addresses
The interrupt vectors and the power-up start address are located in the address range 0FFFFh to 0FFC0h.
The vector contains the 16-bit address of the appropriate interrupt-handler instruction sequence.
Table 6-3. Interrupt Sources, Flags, and Vectors of MSP430FG43x Configurations
INTERRUPT SOURCE
INTERRUPT FLAG
SYSTEM
INTERRUPT
WORD
ADDRESS
PRIORITY
Power-Up
External Reset
Watchdog
Flash Memory
WDTIFG
KEYV (1)
Reset
0FFFEh
15, highest
NMI
Oscillator Fault
Flash Memory Access Violation
NMIIFG (1)
OFIFG (1)
ACCVIFG (1)
(Non)maskable (2)
(Non)maskable
(Non)maskable
0FFFCh
14
Timer_B3
TBCCR0 CCIFG0 (3)
Maskable
0FFFAh
13
Timer_B3
TBCCR1 CCIFG1 and TBCCR2 CCIFG2,
TBIFG (1) (3)
Maskable
0FFF8h
12
Comparator_A
CAIFG
Maskable
0FFF6h
11
Watchdog Timer
WDTIFG
Maskable
0FFF4h
10
USART0 Receive
URXIFG0
Maskable
0FFF2h
9
USART0 Transmit
UTXIFG0
Maskable
0FFF0h
8
Maskable
0FFEEh
7
Maskable
0FFECh
6
Maskable
0FFEAh
5
Maskable
0FFE8h
4
Maskable
0FFE6h
3
0FFE4h
2
Maskable
0FFE2h
1
Maskable
0FFE0h
0, lowest
ADC12
ADC12IFG
Timer_A3
Timer_A3
I/O Port P1 (Eight Flags)
DAC12 DMA
I/O Port P2 (Eight Flags)
TACCR0 CCIFG0
(3)
TACCR1 CCIFG1 and TACCR2 CCIFG2,
TAIFG (1) (3)
P1IFG.0 to P1IFG.7 (1)
(3)
DAC12.0IFG, DAC12.1IFG, DMA0IFG
P2IFG.0 to P2IFG.7
Basic Timer1
(1)
(2)
(3)
(1) (3)
BTIFG
(1) (3)
(1) (3)
Multiple source flags
(Non)maskable: the individual interrupt-enable bit can disable an interrupt event, but the general-interrupt enable cannot disable it.
Interrupt flags are located in the module.
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Special Function Registers (SFRs)
The MSP430 SFRs are located in the lowest address space and are organized as byte-mode registers.
SFRs should be accessed with byte instructions.
Legend
rw
Bit can be read and written.
rw-0, rw-1
Bit can be read and written. It is Reset or Set by PUC.
rw-(0), rw-1
Bit can be read and written. It is Reset or Set by POR.
SFR bit is not present in device.
6.5.1
Interrupt Enable Registers 1 and 2
Figure 6-1. Interrupt Enable Register 1 (Address = 0h)
7
UTXIE0
rw–0
6
URXIE0
rw–0
5
ACCVIE
rw–0
4
NMIIE
rw–0
3
2
1
OFIE
rw–0
0
WDTIE
rw–0
Table 6-4. Interrupt Enable Register 1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
UTXIE0
RW
0h
USART0: UART and SPI transmit-interrupt enable
6
URXIE0
RW
0h
USART0: UART and SPI receive-interrupt enable
5
ACCVIE
RW
0h
Flash access violation interrupt enable
4
NMIIE
RW
0h
Nonmaskable-interrupt enable
1
OFIE
RW
0h
Oscillator-fault-interrupt enable
0
WDTIE
RW
0h
Watchdog-timer interrupt enable. Inactive if watchdog mode is selected.
Active if watchdog timer is configured as a general-purpose timer.
Figure 6-2. Interrupt Enable Register 2 (Address = 1h)
7
BTIE
rw–0
6
5
4
3
2
1
0
Table 6-5. Interrupt Enable Register 2 Field Descriptions
BIT
7
44
FIELD
TYPE
RESET
DESCRIPTION
BTIE
RW
0h
Basic timer interrupt enable
Detailed Description
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6.5.2
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
Interrupt Flag Registers 1 and 2
Figure 6-3. Interrupt Flag Register 1 (Address = 2h)
7
UTXIFG0
rw–1
6
URXIFG0
rw–0
5
4
NMIIFG
rw–0
3
2
1
OFIFG
rw–1
0
WDTIFG
rw–(0)
Table 6-6. Interrupt Flag Register 1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
UTXIFG0
RW
1h
USART0: UART and SPI transmit flag
6
URXIFG0
RW
0h
USART0: UART and SPI receive flag
4
NMIIFG
RW
0h
Set by RST/NMI pin
1
OFIFG
RW
1h
Flag set on oscillator fault
0
WDTIFG
RW
0h
Set on watchdog timer overflow (in watchdog mode) or security key violation
Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode
Figure 6-4. Interrupt Flag Register 2 (Address = 3h)
7
BTIFG
rw–0
6
5
4
3
2
1
0
1
0
1
0
Table 6-7. Interrupt Flag Register 2 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
BTIFG
RW
0h
Basic timer flag
6.5.3
Module Enable Registers 1 and 2
Figure 6-5. Module Enable Register 1 (Address = 4h)
7
UTXE0
rw–0
6
URXE0
USPIE0
rw–0
5
4
3
2
Table 6-8. Module Enable Register 1 Field Descriptions
BIT
FIELD
TYPE
RESET
DESCRIPTION
7
UTXE0
RW
0h
USART0: UART mode transmit enable
URXE0
RW
0h
USART0: UART mode receive enable
USPIE0
RW
0h
USART0: SPI mode transmit and receive enable
6
Figure 6-6. Module Enable Register 2 (Address = 5h)
7
6
5
4
3
2
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Memory Organization
Table 6-9 shows the memory organization for all device variants.
Table 6-9. Memory Organization
MSP430FG437
MSP430FG438
Size
32KB
48KB
60KB
Main: interrupt vector
Flash
0FFFFh-0FFE0h
0FFFFh-0FFE0h
0FFFFh-0FFE0h
Main: code memory
Flash
0FFFFh-08000h
0FFFFh-04000h
0FFFFh-01100h
Information memory
Size
256 Byte
256 Byte
256 Byte
Flash
010FFh-01000h
010FFh-01000h
010FFh-01000h
Memory
Boot memory
RAM
Size
1KB
1KB
1KB
ROM
0FFFh-0C00h
0FFFh-0C00h
0FFFh-0C00h
Size
Peripherals
1KB
2KB
2KB
05FFh-0200h
09FFh-0200h
09FFh-0200h
16-bit
01FFh-0100h
01FFh-0100h
01FFh-0100h
8-bit
0FFh-010h
0FFh-010h
0FFh-010h
0Fh-00h
0Fh-00h
0Fh-00h
8-bit SFR
46
Detailed Description
MSP430FG439
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6.7
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
Bootstrap Loader (BSL)
The MSP430 bootstrap loader (BSL) enables users to program the flash memory or RAM using a UART
serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For
complete description of the features of the BSL and its implementation, see MSP430 Programming Via the
Bootstrap Loader (BSL) (SLAU319).
6.8
BSL FUNCTION
PN PACKAGE PINS
ZCA PACKAGE PINS
Data Transmit
67 – P1.0
D8 – P1.0
Data Receiver
66 – P1.1
D9 – P1.1
Flash Memory
The flash memory can be programmed via the JTAG port, the bootstrap loader, or in system by the CPU.
The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash
memory include:
• Flash memory has n segments of main memory and two segments of information memory (A and B) of
128 bytes each. Each segment in main memory is 512 bytes in size.
• Segments 0 to n may be erased in one step, or each segment may be individually erased.
• Segments A and B can be erased individually, or as a group with segments 0 to n. Segments A and B
are also called information memory.
• New devices may have some bytes programmed in the information memory (needed for test during
manufacturing). The user should perform an erase of the information memory prior to the first use.
32KB
48KB
60KB
0FFFFh
0FFFFh
0FFFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FE00h
0FDFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FC00h
0FBFFh
0FA00h
0F9FFh
0FA00h
0F9FFh
0FA00h
0F9FFh
Segment 0
with Interrupt Vectors
Segment 1
Segment 2
Main
Memory
08400h
083FFh
04400h
043FFh
01400h
013FFh
08200h
081FFh
04200h
041FFh
01200h
011FFh
08000h
010FFh
04000h
010FFh
01100h
010FFh
01080h
0107Fh
01080h
0107Fh
01080h
0107Fh
01000h
01000h
01000h
Segment n-1
Segment n
(see Note A)
Segment A
Information
Memory
Segment B
A.
MSP430FG43x flash segment n = 256 bytes.
Figure 6-7. Flash Memory Segments
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Peripherals
Peripherals are connected to the CPU through data, address, and control buses and can be handled using
all instructions. For complete module descriptions, see the MSP430x4xx Family User's Guide (SLAU056).
6.9.1
DMA Controller
The DMA controller allows movement of data from one memory address to another without CPU
intervention. For example, the DMA controller can be used to move data from the ADC12 conversion
memory to RAM. Using the DMA controller can increase the throughput of peripheral modules. The DMA
controller reduces system power consumption by allowing the CPU to remain in sleep mode without
having to awaken to move data to or from a peripheral.
6.9.2
Oscillator and System Clock
The clock system in the MSP430FG43x family of devices is supported by the FLL+ module, which
includes support for a 32768-Hz watch crystal oscillator, an internal digitally-controlled oscillator (DCO),
and a high frequency crystal oscillator. The FLL+ clock module is designed to meet the requirements of
both low system cost and low power consumption. The FLL+ features digital frequency locked loop (FLL)
hardware that, in conjunction with a digital modulator, stabilizes the DCO frequency to a programmable
multiple of the watch crystal frequency. The internal DCO provides a fast turn-on clock source and
stabilizes in less than 6 µs. The FLL+ module provides the following clock signals:
• Auxiliary clock (ACLK), sourced from a 32768-Hz watch crystal or a high-frequency crystal
• Main clock (MCLK), the system clock used by the CPU
• Sub-Main clock (SMCLK), the subsystem clock used by the peripheral modules
• ACLK/n, the buffered output of ACLK, ACLK/2, ACLK/4, or ACLK/8
6.9.3
Brownout, Supply Voltage Supervisor
The brownout circuit is implemented to provide the proper internal reset signal to the device during poweron and power-off. The supply voltage supervisor (SVS) circuitry detects if the supply voltage drops below
a user selectable level and supports both supply voltage supervision (the device is automatically reset)
and supply voltage monitoring (the device is not automatically reset).
The CPU begins code execution after the brownout circuit releases the device reset. However, VCC may
not have ramped to VCC(min) at that time. The user must make sure that the default FLL+ settings are not
changed until VCC reaches VCC(min). If desired, the SVS circuit can be used to determine when VCC
reaches VCC(min).
6.9.4
Digital I/O
There are six 8-bit I/O ports implemented—ports P1 through P6:
• All individual I/O bits are independently programmable.
• Any combination of input, output, and interrupt conditions is possible.
• Edge-selectable interrupt input capability for all the eight bits of ports P1 and P2.
• Read and write access to port-control registers is supported by all instructions
6.9.5
Basic Timer1
The Basic Timer1 has two independent 8-bit timers that can be cascaded to form a 16-bit timer/counter.
Both timers can be read and written by software. The Basic Timer1 can be used to generate periodic
interrupts and clock for the LCD module.
48
Detailed Description
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6.9.6
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
LCD Drive
The LCD driver generates the segment and common signals required to drive an LCD display. The LCD
controller has dedicated data memory to hold segment drive information. Common and segment signals
are generated as defined by the mode. Static, 2-MUX, 3-MUX, and 4-MUX LCDs are supported by this
peripheral.
6.9.7
OA
The MSP430FG43x has three configurable low-current general-purpose operational amplifiers. Each OA
input and output terminal is software-selectable and offers a flexible choice of connections for various
applications. The OA op amps primarily support front-end analog signal conditioning prior to analog-todigital conversion.
6.9.8
Watchdog Timer (WDT)
The primary function of the WDT module is to perform a controlled system restart after a software problem
occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not
needed in an application, the module can be configured as an interval timer and can generate interrupts at
selected time intervals.
6.9.9
USART0
The MSP430FG43x has one hardware universal synchronous/asynchronous receive transmit (USART)
peripheral module that is used for serial data communication. The USART supports synchronous SPI (3 or
4 pin) and asynchronous UART communication protocols, using double-buffered transmit and receive
channels.
6.9.10 Timer_A3
Timer_A3 is a 16-bit timer/counter with three capture/compare registers. Timer_A3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-10. Timer_A3 Signal Connections
INPUT PIN NUMBER
ZCA
PN
DEVICE INPUT
SIGNAL
MODULE
INPUT NAME
B10 - P1.5
62 - P1.5
TACLK
TACLK
ACLK
ACLK
SMCLK
SMCLK
B10 - P1.5
62 - P1.5
TACLK
INCLK
D8 - P1.0
67 - P1.0
TA0
CCI0A
D9 - P1.1
66 - P1.1
TA0
CCI0B
B9 - P1.2
C11 - P2.0
65 - P1.2
59 - P2.0
DVSS
GND
DVCC
VCC
TA1
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
CCR0
OUTPUT PIN NUMBER
PN
ZCA
67 - P1.0
D8 - P1.0
B9 - P1.2
TA0
CCI1A
65 - P1.2
CAOUT
(internal)
CCI1B
ADC12
(internal)
DVSS
GND
DVCC
VCC
TA2
CCI2A
ACLK (internal)
CCI2B
DVSS
GND
DVCC
VCC
CCR1
TA1
59 - P2.0
CCR2
C11 - P2.0
TA2
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6.9.11 Timer_B3
Timer_B3 is a 16-bit timer/counter with three capture/compare registers. Timer_B3 can support multiple
capture/compares, PWM outputs, and interval timing. Timer_B3 also has extensive interrupt capabilities.
Interrupts may be generated from the counter on overflow conditions and from each of the
capture/compare registers.
Table 6-11. Timer_B3 Signal Connections
INPUT PIN NUMBER
ZCA
PN
DEVICE INPUT
SIGNAL
E9 - P1.4
63 - P1.4
TBCLK
MODULE
INPUT NAME
TBCLK
ACLK
ACLK
SMCLK
SMCLK
MODULE
BLOCK
MODULE
OUTPUT
SIGNAL
Timer
NA
OUTPUT PIN NUMBER
PN
ZCA
D11 - P2.1
E9 - P1.4
63 - P1.4
TBCLK
INCLK
D11 - P2.1
58 - P2.1
TB0
CCI0A
58 - P2.1
TB0
CCI0B
ADC12
(internal)
D11 - P2.1
58 - P2.1
DVSS
GND
DVCC
VCC
CCR0
TB0
E11 - P2.2
57 - P2.2
TB1
CCI1A
57 - P2.2
E11 - P2.2
57 - P2.2
TB1
CCI1B
ADC12
(internal)
DVSS
GND
DVCC
VCC
F11 - P2.3
56 - P2.3
TB2
CCI2A
F11 - P2.3
56 - P2.3
TB2
CCI2B
DVSS
GND
DVCC
VCC
CCR1
TB1
56 - P2.3
CCR2
E11 - P2.2
F11 - P2.3
TB2
6.9.12 Comparator_A
The primary function of the comparator_A module is to support precision slope analog-to-digital
conversions, battery-voltage supervision, and monitoring of external analog signals.
6.9.13 ADC12
The ADC12 module supports fast, 12-bit analog-to-digital conversions. The module implements a 12-bit
SAR core, sample select control, reference generator and a 16 word conversion-and-control buffer. The
conversion-and-control buffer allows up to 16 independent ADC samples to be converted and stored
without any CPU intervention.
6.9.14 DAC12
The DAC12 module is a 12-bit, R-ladder, voltage output DAC. The DAC12 may be used in 8- or 12-bit
mode, and may be used in conjunction with the DMA controller. When multiple DAC12 modules are
present, they may be grouped together for synchronous operation.
50
Detailed Description
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6.9.15 Peripheral File Map
Table 6-12 shows peripherals with word-access registers, and Table 6-13 shows peripherals with byteaccess registers.
Table 6-12. Peripherals With Word Access
PERIPHERAL
REGISTER NAME
ACRONYM
OFFSET
Watchdog
Watchdog timer control
WDTCTL
0120h
Timer_B3
Capture/compare register 2
TBCCR2
0196h
Capture/compare register 1
TBCCR1
0194h
Capture/compare register 0
TBCCR0
0192h
Timer_B register
TBR
0190h
Capture/compare control 2
TBCCTL2
0186h
Capture/compare control 1
TBCCTL1
0184h
Capture/compare control 0
TBCCTL0
0182h
Timer_B control
TBCTL
0180h
Timer_B interrupt vector
TBIV
011Eh
Capture/compare register 2
TACCR2
0176h
Capture/compare register 1
TACCR1
0174h
Capture/compare register 0
TACCR0
0172h
Timer_A register
TAR
0170h
Capture/compare control 2
TACCTL2
0166h
Capture/compare control 1
TACCTL1
0164h
Capture/compare control 0
TACCTL0
0162h
Timer_A control
TACTL
0160h
Timer_A interrupt vector
TAIV
012Eh
Flash control 3
FCTL3
012Ch
Flash control 2
FCTL2
012Ah
Flash control 1
FCTL1
0128h
DMA module control 0
DMACTL0
0122h
DMA module control 1
DMACTL1
0124h
DMA channel 0 control
DMA0CTL
01E0h
DMA channel 0 source address
DMA0SA
01E2h
DMA channel 0 destination address
DMA0DA
01E4h
DMA channel 0 transfer size
DMA0SZ
01E6h
Timer_A3
Flash
DMA
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Table 6-12. Peripherals With Word Access (continued)
PERIPHERAL
ADC12
(See also Table 6-13)
DAC12
REGISTER NAME
ACRONYM
OFFSET
Conversion memory 15
ADC12MEM15
015Eh
Conversion memory 14
ADC12MEM14
015Ch
Conversion memory 13
ADC12MEM13
015Ah
Conversion memory 12
ADC12MEM12
0158h
Conversion memory 11
ADC12MEM11
0156h
Conversion memory 10
ADC12MEM10
0154h
Conversion memory 9
ADC12MEM9
0152h
Conversion memory 8
ADC12MEM8
0150h
Conversion memory 7
ADC12MEM7
014Eh
Conversion memory 6
ADC12MEM6
014Ch
Conversion memory 5
ADC12MEM5
014Ah
Conversion memory 4
ADC12MEM4
0148h
Conversion memory 3
ADC12MEM3
0146h
Conversion memory 2
ADC12MEM2
0144h
Conversion memory 1
ADC12MEM1
0142h
Conversion memory 0
ADC12MEM0
0140h
Interrupt-vector-word register
ADC12IV
01A8h
Interrupt-enable register
ADC12IE
01A6h
Interrupt-flag register
ADC12IFG
01A4h
Control register 1
ADC12CTL1
01A2h
Control register 0
ADC12CTL0
01A0h
DAC12_1 data
DAC12_1DAT
01CAh
DAC12_1 control
DAC12_1CTL
01C2h
DAC12_0 data
DAC12_0DAT
01C8h
DAC12_0 control
DAC12_0CTL
01C0h
Table 6-13. Peripherals With Byte Access
PERIPHERAL
OA2
OA1
OA0
LCD
REGISTER NAME
OFFSET
OA2CTL1
0C5h
Operational Amplifier 2 control register 0
OA2CTL0
0C4h
Operational Amplifier 1 control register 1
OA1CTL1
0C3h
Operational Amplifier 1 control register 0
OA1CTL0
0C2h
Operational Amplifier 0 control register 1
OA0CTL1
0C1h
Operational Amplifier 0 control register 0
OA0CTL0
0C0h
LCD memory 20
LCDM20
0A4h
⋮
⋮
⋮
LCD memory 16
LCDM16
0A0h
LCD memory 15
LCDM15
09Fh
⋮
52
ACRONYM
Operational Amplifier 2 control register 1
⋮
⋮
LCD memory 1
LCDM1
091h
LCD control and mode
LCDCTL
090h
Detailed Description
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Table 6-13. Peripherals With Byte Access (continued)
PERIPHERAL
ADC12
(Memory control
registers require byte
access)
REGISTER NAME
ACRONYM
OFFSET
ADC memory-control register 15
ADC12MCTL15
08Fh
ADC memory-control register 14
ADC12MCTL14
08Eh
ADC memory-control register 13
ADC12MCTL13
08Dh
ADC memory-control register 12
ADC12MCTL12
08Ch
ADC memory-control register 11
ADC12MCTL11
08Bh
ADC memory-control register 10
ADC12MCTL10
08Ah
ADC memory-control register 9
ADC12MCTL9
089h
ADC memory-control register 8
ADC12MCTL8
088h
ADC memory-control register 7
ADC12MCTL7
087h
ADC memory-control register 6
ADC12MCTL6
086h
ADC memory-control register 5
ADC12MCTL5
085h
ADC memory-control register 4
ADC12MCTL4
084h
ADC memory-control register 3
ADC12MCTL3
083h
ADC memory-control register 2
ADC12MCTL2
082h
ADC memory-control register 1
ADC12MCTL1
081h
ADC memory-control register 0
ADC12MCTL0
080h
Transmit buffer
U0TXBUF
077h
Receive buffer
U0RXBUF
076h
Baud rate
U0BR1
075h
Baud rate
U0BR0
074h
Modulation control
U0MCTL
073h
Receive control
U0RCTL
072h
Transmit control
U0TCTL
071h
USART control
U0CTL
070h
Comparator_A port disable
CAPD
05Bh
Comparator_A control 2
CACTL2
05Ah
Comparator_A control 1
CACTL1
059h
BrownOUT, SVS
SVS control register (Reset by brownout signal)
SVSCTL
056h
FLL+ Clock
FLL+ Control 1
FLL_CTL1
054h
FLL+ Control 0
FLL_CTL0
053h
System clock frequency control
SCFQCTL
052h
System clock frequency integrator
SCFI1
051h
System clock frequency integrator
SCFI0
050h
BT counter 2
BTCNT2
047h
BT counter 1
BTCNT1
046h
BT control
BTCTL
040h
Port P6 selection
P6SEL
037h
Port P6 direction
P6DIR
036h
Port P6 output
P6OUT
035h
Port P6 input
P6IN
034h
Port P5 selection
P5SEL
033h
Port P5 direction
P5DIR
032h
Port P5 output
P5OUT
031h
Port P5 input
P5IN
030h
USART0
(UART or SPI mode)
Comparator_A
Basic Timer1
Port P6
Port P5
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Table 6-13. Peripherals With Byte Access (continued)
PERIPHERAL
Port P4
Port P3
Port P2
Port P1
Special functions
54
REGISTER NAME
ACRONYM
OFFSET
Port P4 selection
P4SEL
01Fh
Port P4 direction
P4DIR
01Eh
Port P4 output
P4OUT
01Dh
Port P4 input
P4IN
01Ch
Port P3 selection
P3SEL
01Bh
Port P3 direction
P3DIR
01Ah
Port P3 output
P3OUT
019h
Port P3 input
P3IN
018h
Port P2 selection
P2SEL
02Eh
Port P2 interrupt enable
P2IE
02Dh
Port P2 interrupt-edge select
P2IES
02Ch
Port P2 interrupt flag
P2IFG
02Bh
Port P2 direction
P2DIR
02Ah
Port P2 output
P2OUT
029h
Port P2 input
P2IN
028h
Port P1 selection
P1SEL
026h
Port P1 interrupt enable
P1IE
025h
Port P1 interrupt-edge select
P1IES
024h
Port P1 interrupt flag
P1IFG
023h
Port P1 direction
P1DIR
022h
Port P1 output
P1OUT
021h
Port P1 input
P1IN
020h
SFR module enable 2
ME2
005h
SFR module enable 1
ME1
004h
SFR interrupt flag 2
IFG2
003h
SFR interrupt flag 1
IFG1
002h
SFR interrupt enable 2
IE2
001h
SFR interrupt enable 1
IE1
000h
Detailed Description
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6.10 Input/Output Schematics
6.10.1 Port P1, P1.0 to P1.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
CAPD.x
P1SEL.x
0: Input
1: Output
0
P1DIR.x
Direction Control
From Module
1
0
1
P1OUT.x
Module X OUT
Bus
Keeper
P1.0/TA0
P1.1/TA0/MCLK
P1.2/TA1
P1.3/TBOUTH/SVSOUT
P1.4/TBCLK/SMCLK
P1.5/TACLK/ACLK
P1IN.x
EN
D
Module X IN
P1IE.x
P1IRQ.x
P1IFG.x
EN
Q
Set
Interrupt
Edge
Select
P1IES.x
P1SEL.x
Note: 0 ≤ x ≤ 5
Note: Port function is active if CAPD.x = 0
(1)
(2)
PnSEL.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P1SEL.0
P1DIR.0
P1DIR.0
P1OUT0
Out0 sig. (1)
P1IN.0
CCI0A (1)
P1IE.0
P1IFG.0
P1IES.0
(1)
P1SEL.1
P1DIR.1
P1DIR.1
P1OUT.1
MCLK
P1IN.1
CCI0B
P1IE.1
P1IFG.1
P1IES.1
P1SEL.2
P1DIR.2
P1DIR.2
P1OUT.2
Out1 sig. (1)
P1IN.2
CCI1A (1)
P1IE.2
P1IFG.2
P1IES.2
P1SEL.3
P1DIR.3
P1DIR.3
P1OUT.3
SVSOUT
P1IN.3
TBOUTH (2)
P1IE.3
P1IFG.3
P1IES.3
P1SEL.4
P1DIR.4
P1DIR.4
P1OUT.4
SMCLK
P1IN.4
TBCLK (2)
P1IE.4
P1IFG.4
P1IES.4
P1SEL.5
P1DIR.5
P1DIR5
P1OUT.5
ACLK
P1IN.5
TACLK (1)
P1IE.5
P1IFG.5
P1IES.5
Timer_A
Timer_B
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6.10.2 Port P1, P1.6 and P1.7, Input/Output With Schmitt Trigger
Pad Logic
Note: Port function is active if CAPD.6 = 0
CAPD.6
P1SEL.6
0: Input
1: Output
0
P1DIR.6
P1.6/
CA0
1
P1DIR.6
0
P1OUT.6
1
DV SS
Bus
Keeper
P1IN.6
EN
unused
D
P1IE.7
P1IRQ.07
EN
Interrupt
Edge
Select
Q
P1IFG.7
Set
P1IES.x
P1SEL.x
Comparator_A
P2CA
AVcc
CAREF
CAEX
CA0
CAF
CCI1B
+
to Timer_Ax
-
CA1
2
CAREF
Reference Block
Pad Logic
CAPD.7
Note: Port function is active if CAPD.7 = 0
P1SEL.7
0: input
1: output
0
P1DIR.7
P1.7/
CA1
1
P1DIR.7
0
P1OUT.7
1
DV SS
Bus
keeper
P1IN.7
EN
unused
P1IRQ.07
D
P1IE.7
P1IFG.7
EN
Q
Set
Interrupt
Edge
Select
P1IES.7
56
Detailed Description
P1SEL.7
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6.10.3 Port P2, P2.0 and P2.4 to P2.5, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
1
P2OUT.x
Module X OUT
Bus
Keeper
P2.0/TA2
P2.4/UTXD0
P2IN.x
P2.5/URXD0
EN
D
Module X IN
P2IE.x
P2IRQ.x
P2IFG.x
EN
Q
Set
Interrupt
Edge
Select
P2IES.x
Note:
(1)
(2)
P2SEL.x
x {0,4,5}
PnSel.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.0
P2DIR.0
P2DIR.0
P2OUT.0
Out2 sig. (1)
P2IN.0
CCI2A (1)
P2IE.0
P2IFG.0
P2IES.0
P2Sel.4
P2DIR.4
DVCC
P2OUT.4
UTXD0 (2)
P2IN.4
unused
P2IE.4
P2IFG.4
P2IES.4
P2Sel.5
P2DIR.5
DVSS
P2OUT.5
DVSS
P2IN.5
URXD0 (2)
P2IE.5
P2IFG.5
P2IES.5
Timer_A
USART0
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6.10.4 Port P2, P2.1 to P2.3, Input/Output With Schmitt Trigger
Pad Logic
DVSS
DVSS
Module IN of pin
P1.3/TBOUTH/SVSOUT
P1DIR.3
P1SEL.3
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
P2OUT.x
1
0
1
Module X OUT
Bus
Keeper
P2.1/TB0
P2.2/TB1
P2IN.x
P2.3/TB2
EN
Module X IN
D
P2IE.x
P2IRQ.x
Q
P2IFG.x
EN
Set
Interrupt
Edge
Select
P2IES.x
P2SEL.x
Note: 1 ≤ x ≤ 3
PnSel.x
PnDIR.x
Direction
Control
From Module
PnOUT.x
Module X
OUT
PnIN.x
Module X IN
PnIE.x
PnIFG.x
PnIES.x
P2Sel.1
P2DIR.1
P2DIR.1
P2OUT.1
Out0 sig. (1)
P2IN.1
CCI0A (1)
CCI0B
P2IE.1
P2IFG.1
P2IES.1
P2IE.2
P2IFG.2
P2IES.2
P2IE.3
P2IFG.3
P2IES.3
P2Sel.2
P2Sel.3
(1)
58
P2DIR.2
P2DIR.3
P2DIR.2
P2DIR.3
P2OUT.2
P2OUT.3
Out1 sig. (1)
Out2 sig. (1)
(1)
P2IN.2
CCI1A
CCI1B
(1)
P2IN.3
CCI2A
CCI2B
Timer_B
Detailed Description
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6.10.5 Port P2, P2.6 and P2.7, Input/Output With Schmitt Trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD
Segment xx
P2SEL.x
0: Input
1: Output
0
P2DIR.x
Direction Control
From Module
1
0
P2OUT.x
1
Module X OUT
Bus
Keeper
P2.6/CAOUT/S19
P2.7/ADC12CLK/S18
P2IN.x
EN
Module X IN
D
P2IE.x
P2IRQ.x
P2IFG.x
EN
Interrupt
Edge
Select
Q
Set
P2IES.x
P2SEL.x
Note: 6 ≤ x ≤ 7
PnSel.x
PnDIR.x
Direction
Control
From
Module
PnOUT.x
Module X
OUT
PnIN.x
Module X
IN
PnIE.x
PnIFG.x
PnIES.x
Port/LCD
P2Sel.6
P2DIR.6
P2DIR.6
P2OUT.6
CAOUT (1)
P2IN.6
unused
P2IE.6
P2IFG.6
P2IES.6
0: LCDPx < 02h
P2IN.7
unused
P2IE.7
P2IFG.7
P2IES.7
0: LCDPx < 02h
P2Sel.7
(1)
(2)
P2DIR.7
P2DIR.7
P2OUT.7
ADC12CLK
(2)
Comparator_A
ADC12
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6.10.6 Port P3, P3.0 to P3.3, Input/Output With Schmitt Trigger
MSP430x43xIPN (80-Pin) Only
0: Port active
1: Segment xx function active
LCDPx[0]
LCDPx[1]
LCDPx[2]
Pad Logic
x43xIPZ and x44xIPZ have not segment
Function on Port P3: Both lines are low.
Segment xx
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
1
P3OUT.x
Module X OUT
Bus
Keeper
P3.0/STE0/S31
P3.1/SIMO0/S30
P3.2/SOMI0/S29
P3.3/UCLK0/S28
P3IN.x
EN
D
Module X IN
Note: 0 ≤ x ≤ 3
Direction Control
From Module
PnOUT.x
P3DIR.0
DVSS
P3DIR.1
DCM_SIMO0
P3DIR.2
P3DIR.3
PnSel.x
PnDIR.x
P3Sel.0
P3Sel.1
P3Sel.2
P3Sel.3
Module X OUT
PnIN.x
P3OUT.0
DVSS
P3IN.0
STE0(in)
P3OUT.1
SIMO0(out)
P3IN.1
SIMO0(in)
DCM_SOMI0
P3OUT.2
SOMIO(out)
P3IN.2
SOMI0(in)
DCM_UCLK0
P3OUT.3
UCLK0(out)
P3IN.3
UCLK0(in)
Direction Control for SIMO0 and UCLK0
SYNC
MM
60
DCM_SIMO0
DCM_UCLK0
Direction Control for SOMI0
SYNC
MM
STC
STC
STE
STE
Detailed Description
Module X IN
DCM_SOMI0
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.7 Port P3, P3.4 to P3.7, Input/Output With Schmitt Trigger
0: Port active
1: Segment xx function active
Pad Logic
LCDPx[2]
Segment xx
P3SEL.x
0: Input
1: Output
0
P3DIR.x
Direction Control
From Module
1
0
P3OUT.x
1
Module X OUT
Bus
Keeper
P3.4/S27
P3.5/S26
P3.6/S25/DMAE0
P3.7/S24
P3IN.x
EN
Module X IN
D
Note: 4 ≤ x ≤ 7
PnSel.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P3SEL.4
P3DIR.4
P3DIR.4
P3OUT.4
DVSS
P3IN.4
unused
P3SEL.5
P3DIR.5
P3DIR.5
P3OUT.5
DVSS
P3IN.5
unused
P3SEL.6
P3DIR.6
P3DIR.6
P3OUT.6
DVSS
P3IN.6
DMAE0
P3SEL.7
P3DIR.7
P3DIR.7
P3OUT.7
DVSS
P3IN.7
unused
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Detailed Description
61
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.10.8 Port P4, P4.0 to P4.5, Input/Output With Schmitt Trigger
0: Port active
1: Segment xx function active
Pad Logic
Port/LCD
Segment xx
P4SEL.x
0: Input
1: Output
0
P4DIR.x
Direction Control
From Module
1
0
1
P4OUT.x
Module X OUT
Bus
Keeper
P4.0/S9
P4.1/S8
P4.2/S7
P4.3/S6
P4.4/S5
P4.5/S4
P4IN.x
EN
Module X IN
D
Note: 0 ≤ x ≤ 5
62
PnSEL.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P4SEL.0
P4DIR.0
P4DIR.0
P4OUT.0
DVSS
P4IN.0
unused
P4SEL.1
P4DIR.1
P4DIR.1
P4OUT.1
DVSS
P4IN.1
unused
P4SEL.2
P4DIR.2
P4DIR.2
P4OUT.2
DVSS
P4IN.2
unused
P4SEL.3
P4DIR.3
P4DIR.3
P4OUT.3
DVSS
P4IN.3
unused
P4SEL.4
P4DIR.4
P4DIR.4
P4OUT.4
DVSS
P4IN.4
unused
P4SEL.5
P4DIR.5
P4DIR.5
P4OUT.5
DVSS
P4IN.5
unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P4.0 to P4.5
LCDPx < 01h
LCDPx ≥ 01h
Detailed Description
Copyright © 2004–2014, Texas Instruments Incorporated
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.9 Port P4, P4.6, Input/Output With Schmitt Trigger
INCH=15(1)
a15 (1)
0: Segment S3 disabled
1: Segment S3 enabled
Pad Logic
1, If LCDPx ≥ 01h
Segment S3
P4SEL.6
0: input
1: output
0
P4DIR.6
Direction Control
From Module
1
0
P4OUT.6
1
Module XOUT
Bus
keeper
P4.6/S3/A15
P4IN.6
EN
D
Module X IN
(1)
Signal from or to ADC12
PnSEL.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P4SEL.6
P4DIR.6
P4DIR.6
P4OUT.6
DVSS
P4IN.6
unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P4.6
LCDPx < 01h
LCDPx ≥ 01h
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Detailed Description
63
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.10.10 Port P4, P4.7, Input/Output With Schmitt Trigger
INCH=14
(1)
a14
(1)
OAADC0
0: Segment S2 disabled
1: Segment S2 enabled
Pad Logic
1, If LCDPx ≥ 01h
Segment S2
P4SEL.7
0: input
1: output
0
P4DIR.7
Direction Control
From Module
1
0
P4OUT.7
1
Module XOUT
Bus
keeper
P4.7/S2/A14
P4IN.7
EN
D
Module X IN
(1)
64
Signal from or to ADC12
PnSel.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P4Sel.7
P4DIR.7
P4DIR.7
P4OUT.7
DVSS
P4IN.7
Unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P4.7
LCDPx < 01h
LCDPx ≥ 01h
Detailed Description
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.11 Port P5, P5.0, Input/Output With Schmitt Trigger
OAADC0
INCH=13(1)
a13 (1)
0: Segment S1 disabled
1: Segment S1 enabled
Pad Logic
1, If LCDPx ≥ 01h
Segment S1
P5SEL.0
0: input
1: output
0
P5DIR.0
Direction Control
From Module
1
0
P5OUT.0
1
Module XOUT
Bus
keeper
P5.0/S1/A13
P5IN.0
EN
D
Module X IN
(1)
Signal from or to ADC12
PnSEL.x
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P5SEL.0
P5DIR.0
P5DIR.0
P5OUT.0
DVSS
P5IN.0
unused
DEVICE
PORT BITS
PORT FUNCTION
LCD SEGMENT FUNCTION
MSP430FG43x
P5.0
LCDPx < 01h
LCDPx ≥ 01h
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Detailed Description
65
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.10.12 Port P5, P5.1, Input/Output With Schmitt Trigger
INCH=12(1)
OAADC0
a12(1)
0: Segment S0 disabled
1: Segment S0 enabled
1, If LCDPx ≥ 01h
Pad Logic
DAC12.1OPS
Segment S0
P5SEL.1
0: input
1: output
0
P5DIR.1
Direction Control
From Module
1
0
P5OUT.1
1
Module XOUT
Bus
keeper
P5.1/S0/
A12/DAC1
P5IN.1
EN
D
Module X IN
’0’, if DAC12.1CALON=0 AND
DAC12.1AMPx>1 AND DAC12.1OPS=1
+
1
0
-
’1’, if DAC12.1AMPx>1
’1’, if DAC12.1AMPx=1
DAC12.1OPS
DAC12.1OPS
1
P6.7/A7/
DAC1/SVSIN
DAC1_2_OA
(1)
0
Signal from or to ADC12
Function
P5SEL.1
LCDPx
DAC12.1OPS
DAC12.1AMPx
3-State
X
X
1
0
0V
X
X
1
1
DAC1 output
(the output voltage can be converted with ADC12, channel A12)
X
X
1
>1
ADC12
Channel 12, A12
1
X
0
X
LCD
Segment S0, initial state
0
≥ 01h
0
X
Port
P5.1
0
< 01h
0
X
DAC12
66
Description
PnSEL.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
Segment
Port/LCD
P5SEL.1
P5DIR.1
P5DIR.1
P5OUT.1
DVSS
P5IN.1
Unused
S0
0: LCDPx < 01h
Detailed Description
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.13 Port P5, P5.2 to P5.4, Input/Output With Schmitt Trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.2/COM1
P5.3/COM2
P5.4/COM3
P5IN.x
EN
Module X IN
D
Note: 2 ≤ x ≤ 4
PnSel.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
LCD signal
Port/LCD
P5Sel.2
P5DIR.2
P5DIR.2
P5OUT.2
DVSS
P5IN.2
Unused
COM1
P5SEL.2
P5Sel.3
P5DIR.3
P5DIR.3
P5OUT.3
DVSS
P5IN.3
Unused
COM2
P5SEL.3
P5Sel.4
P5DIR.4
P5DIR.4
P5OUT.4
DVSS
P5IN.4
Unused
COM3
P5SEL.4
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Detailed Description
67
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.10.14 Port P5, P5.5 to P5.7, Input/Output With Schmitt Trigger
0: Port active
1: LCD function active
Port/LCD
LCD signal
Pad Logic
P5SEL.x
0: Input
1: Output
0
P5DIR.x
Direction Control
From Module
1
0
1
P5OUT.x
Module X OUT
Bus
Keeper
P5.5/R13
P5.6/R23
P5.7/R33
P5IN.x
EN
D
Module X IN
Note: 5 ≤ x ≤ 7
68
PnSel.x
PnDIR.x
Direction
Control From
Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
LCD signal
Port/LCD
P5Sel.5
P5DIR.5
P5DIR.5
P5OUT.5
DVSS
P5IN.5
Unused
R13
P5SEL.5
P5Sel.6
P5DIR.6
P5DIR.6
P5OUT.6
DVSS
P5IN.6
Unused
R23
P5SEL.6
P5Sel.7
P5DIR.7
P5DIR.7
P5OUT.7
DVSS
P5IN.7
Unused
R33
P5SEL.7
Detailed Description
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.15 Port P6, P6.0, P6.2, and P6.4, Input/Output With Schmitt Trigger
(1)(2)
INCH=x
(1)(2)
ax
(1)
P6SEL.x
(1)
0
P6DIR.x
Direction Control
From Module
P6OUT.x
Pad Logic
0: input
1: output
1
(1)
0
1
Module XOUT
Bus
keeper
P6.0/A0/OA0I0
P6.2/A2/OA0I1
P6.4/A4/OA1I0
(1)
P6IN.x
EN
(1)
D
Module X IN
+
-
(1)
(1)
x = {0, 2, 4}
(2)
Signal from or to ADC12
OA0 / OA1
PnSel.x (1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.0
P6DIR.0
P6DIR.0
P6OUT.0
DVSS
P6IN.0
unused
P6Sel.2
P6DIR.2
P6DIR.2
P6OUT.2
DVSS
P6IN.2
unused
P6Sel.4
P6DIR.4
P6DIR.4
P6OUT.4
DVSS
P6IN.4
unused
The signal at pin P6.x/Ax is used by the 12-bit ADC module.
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69
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.10.16 Port P6, P6.1, Input/Output With Schmitt Trigger
INCH=1(1)
a1 (1)
P6SEL.1
0
P6DIR.1
Direction Control
From Module
P6OUT.1
Pad Logic
0: input
1: output
1
0
1
Module XOUT
Bus
keeper
P6.1/A1/OA0O
P6IN.1
EN
D
Module X IN
’1’, if OAADC1 = 1 OR OAFCx = 0
+
0
OA0
-
(1)
(1)
70
1
OA0
Signal from or to ADC12
PnSel.x (1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.1
P6DIR.1
P6DIR.1
P6OUT.1
DVSS
P6IN.1
unused
The signal at pin P6.x/Ax is used by the 12-bit ADC module.
Detailed Description
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.17 Port P6, P6.3, Input/Output With Schmitt Trigger
INCH=3(1)
a3 (1)
P6SEL.3
Pad Logic
0: input
1: output
0
P6DIR.3
Direction Control
From Module
P6OUT.3
1
0
1
Module XOUT
Bus
keeper
P6.3/A3/OA1I1/OA1O
P6IN.3
EN
D
Module X IN
’1’, if OAADC1 = 1 OR OAFCx = 0
+
0
OA1
-
(1)
(1)
1
OA1
Signal from or to ADC12
PnSel.x (1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.3
P6DIR.3
P6DIR.3
P6OUT.3
DVSS
P6IN.3
unused
The signal at pin P6.x/Ax is used by the 12-bit ADC module.
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Detailed Description
71
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.10.18 Port P6, P6.5, Input/Output With Schmitt Trigger
INCH=5(1)
a5 (1)
P6SEL.5
Pad Logic
0: input
1: output
0
P6DIR.5
Direction Control
From Module
P6OUT.5
1
0
1
Module XOUT
Bus
keeper
P6.5/A5/OA2I1/OA2O
P6IN.5
EN
D
Module X IN
’1’, if OAADC1 = 1 OR OAFCx = 0
0
+
OA2
-
(1)
(1)
72
1
OA2
Signal from or to ADC12
PnSel.x (1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.5
P6DIR.5
P6DIR.5
P6OUT.5
DVSS
P6IN.5
unused
The signal at pins P6.x/Ax is used by the 12-bit ADC module.
Detailed Description
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.19 Port P6, P6.6, Input/Output With Schmitt Trigger
0: Port active, T- Switch off
1: T- Switch is on, Port disabled
INCH=6(1)
a6 (1)
’1’, if DAC12.0AMP>0
P6SEL.6
P6DIR.6
0
P6DIR.6
1
P6OUT.6
0
0: input
1: output
Pad Logic
1
DVSS
Bus
keeper
P6.6/A6/DAC0/OA2I0
P6IN.6
EN
D
’0’, if DAC12CALON = 0 AND
DAC12AMPx>1 AND DAC12OPS = 0
+
-
1
0
’1’, if DAC12AMPx>1
(1)
’1’, if DAC12AMPx=1
DAC12OPS
Signal from or to ADC12
DAC12OPS
0
Ve REF+/DAC0
DAC0_2_OA
1
(1)
PnSel.x (1)
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6Sel.6
P6DIR.6
P6DIR.6
P6OUT.6
DVSS
P6IN.6
unused
The signal at pins P6.x/Ax is used by the 12-bit ADC module.
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Detailed Description
73
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
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6.10.20 Port P6, P6.7, Input/Output With Schmitt Trigger
To SVS Mux (15) (2)
0: Port active, T−Switch off
1: T−Switch is on, Port disabled
INCH=7(1)
a7 (1)
’1’, if DAC12.1AMP>0
DAC12.1OPS
’1’, if VLD=15 (3)
P6SEL.7
P6DIR.7
Pad Logic
0: input
1: output
0
1
P6DIR.7
0
P6OUT.7
1
DVSS
Bus
keeper
P6.7/A7/
DAC1/SVSIN
P6IN.7
EN
D
’0’, if DAC12CALON = 0 AND
DAC12AMPx>1 AND DAC12OPS = 0
+
−
1
0
’1’, if DAC12AMPx>1
’1’, if DAC12AMPx=1
DAC12OPS
DAC12OPS
0
P5.1/S0/
A12/DAC1
DAC1_2_OA
1
PnSel.x
(1)
P6Sel.7
(1)
74
(1)
Signal from or to ADC12
(2)
Signal to SVS block, selected if VLD=15
(3)
VLD control bits are located in SVS
PnDIR.x
Direction Control
From Module
PnOUT.x
Module X OUT
PnIN.x
Module X IN
P6DIR.7
P6DIR.7
P6OUT.7
DVSS
P6IN.7
unused
The signal at pins P6.x/Ax is used by the 12-bit ADC module. The signal at pin P6.7/A7/SVSIN is also connected to the input multiplexer
in the module brownout/supply voltage supervisor.
Detailed Description
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.21 VeREF+/DAC0
DAC12.0OPS
0
DAC0_2_OA
P6.6/A6/DAC0/OA2I0
1
Reference Voltage to DAC1
Reference Voltage to ADC12
(1)
Reference Voltage to DAC0
Ve REF+ /DAC0
’0’, if DAC12CALON = 0
DAC12AMPx>1 AND DAC12OPS=1
+
-
1
0
’1’, if DAC12AMPx>1
’1’, if DAC12AMPx=1
DAC12OPS
(1) If the reference of DAC0 is taken from pin Ve
/DAC0, unpredictable voltage levels will be on pin.
REF+
In this situation, the DAC0 output is fed back to its own reference input.
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Detailed Description
75
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
www.ti.com
6.10.22 JTAG Pins TMS, TCK, TDI/TCLK, TDO/TDI, Input/Output With Schmitt Trigger or Output
TDO
Controlled by JTAG
Controlled by JTAG
TDO/TDI
JTAG
Controlled
by JTAG
DV CC
TDI
Burn and Test
Fuse
TDI/TCLK
Test
and
Emulation
DV CC
TMS
Module
TMS
DV CC
TCK
TCK
RST/NMI
Tau ~ 50 ns
Brownout
TCK
76
Detailed Description
G
D
U
S
G
D
U
S
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SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
6.10.23 JTAG Fuse Check Mode
MSP430 devices that have the fuse on the TDI/TCLK terminal have a fuse check mode that tests the
continuity of the fuse the first time the JTAG port is accessed after a power-on reset (POR). When
activated, a fuse check current (I(TF)) of 1 mA at 3 V can flow from the TDI/TCLK pin to ground if the fuse
is not burned. Care must be taken to avoid accidentally activating the fuse check mode and increasing
overall system power consumption.
Activation of the fuse check mode occurs with the first negative edge on the TMS pin after power up or if
the TMS is being held low during power up. The second positive edge on the TMS pin deactivates the
fuse check mode. After deactivation, the fuse check mode remains inactive until another POR occurs.
After each POR the fuse check mode has the potential to be activated.
The fuse check current only flows when the fuse check mode is active and the TMS pin is in a low state
(see Figure 6-8). Therefore, the additional current flow can be prevented by holding the TMS pin high
(default condition). The JTAG pins are terminated internally and therefore do not require external
termination.
Time TMS Goes Low After POR
TMS
I(TF)
ITDI/TCLK
Figure 6-8. Fuse Check Mode Current
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG439 MSP430FG438 MSP430FG437
Detailed Description
77
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
www.ti.com
7 Device and Documentation Support
7.1
Device Support
7.1.1
Development Support
TI offers an extensive line of development tools, including tools to evaluate the performance of the
processors, generate code, develop algorithm implementations, and fully integrate and debug software
and hardware modules. The tool's support documentation is electronically available within the Code
Composer Studio™ Integrated Development Environment (IDE).
The following products support development of the MSP430FG43x device applications:
Software Development Tools: Code Composer Studio™ Integrated Development Environment (IDE):
including Editor C/C++/Assembly Code Generation, and Debug plus additional development tools.
For a complete listing of development-support tools for the MSP430FG43x platform, visit the Texas
Instruments website at www.ti.com. For information on pricing and availability, contact the nearest TI field
sales office or authorized distributor.
7.1.1.1
Development Kit
The MSP-FET430U80 is a powerful flash emulation tool that includes the hardware and software required
to quickly begin application development on the MSP430 MCU. It includes a ZIF socket target board and a
USB debugging interface (MSP-FET) used to program and debug the MSP430 in-system through the
JTAG interface or the pin saving Spy Bi-Wire (2-wire JTAG) protocol. The flash memory can be erased
and programmed in seconds with only a few keystrokes, and because the MSP430 flash is ultra-low
power, no external power supply is required.
The debugging tool interfaces the MSP430 to the included integrated software environment and includes
code to start your design immediately.
7.1.2
Device and Development Tool Nomenclature
To designate the stages in the product development cycle, TI assigns prefixes to the part numbers of all
MSP430 MCU devices and support tools. Each MSP430 MCU commercial family member has one of
three prefixes: MSP, PMS, or XMS (for example, MSP430F5259). Texas Instruments recommends two of
three possible prefix designators for its support tools: MSP and MSPX. These prefixes represent
evolutionary stages of product development from engineering prototypes (with XMS for devices and MSPX
for tools) through fully qualified production devices and tools (with MSP for devices and MSP for tools).
Device development evolutionary flow:
XMS – Experimental device that is not necessarily representative of the final device's electrical
specifications
PMS – Final silicon die that conforms to the device's electrical specifications but has not completed quality
and reliability verification
MSP – Fully qualified production device
Support tool development evolutionary flow:
MSPX – Development-support product that has not yet completed Texas Instruments internal qualification
testing.
MSP – Fully-qualified development-support product
XMS and PMS devices and MSPX development-support tools are shipped against the following
disclaimer:
"Developmental product is intended for internal evaluation purposes."
78
Device and Documentation Support
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG439 MSP430FG438 MSP430FG437
MSP430FG439, MSP430FG438, MSP430FG437
www.ti.com
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
MSP devices and MSP development-support tools have been characterized fully, and the quality and
reliability of the device have been demonstrated fully. TI's standard warranty applies.
Predictions show that prototype devices (XMS and PMS) have a greater failure rate than the standard
production devices. Texas Instruments recommends that these devices not be used in any production
system because their expected end-use failure rate still is undefined. Only qualified production devices are
to be used.
TI device nomenclature also includes a suffix with the device family name. This suffix indicates the
package type (for example, PZP) and temperature range (for example, T). Figure 7-1 provides a legend
for reading the complete device name for any family member.
MSP 430 F 5 438 A I ZQW T XX
Processor Family
Optional: Additional Features
430 MCU Platform
Optional: Tape and Reel
Device Type
Packaging
Series
Feature Set
Processor Family
Optional: Temperature Range
Optional: A = Revision
CC = Embedded RF Radio
MSP = Mixed Signal Processor
XMS = Experimental Silicon
PMS = Prototype Device
TI’s Low Power Microcontroller Platform
430 MCU Platform
Device Type
Memory Type
C = ROM
F = Flash
FR = FRAM
G = Flash or FRAM (Value Line)
L = No Nonvolatile Memory
Specialized Application
AFE = Analog Front End
BT = Preprogrammed with Bluetooth
BQ = Contactless Power
CG = ROM Medical
FE = Flash Energy Meter
FG = Flash Medical
FW = Flash Electronic Flow Meter
Series
1 Series = Up to 8 MHz
2 Series = Up to 16 MHz
3 Series = Legacy
4 Series = Up to 16 MHz w/ LCD
5 Series = Up to 25 MHz
6 Series = Up to 25 MHz w/ LCD
0 = Low Voltage Series
Feature Set
Various Levels of Integration Within a Series
Optional: A = Revision
N/A
Optional: Temperature Range S = 0°C to 50°C
C = 0°C to 70°C
I = -40°C to 85°C
T = -40°C to 105°C
Packaging
www.ti.com/packaging
Optional: Tape and Reel
T = Small Reel
R = Large Reel
No Markings = Tube or Tray
Optional: Additional Features -EP = Enhanced Product (-40°C to 105°C)
-HT = Extreme Temperature Parts (-55°C to 150°C)
-Q1 = Automotive Q100 Qualified
Figure 7-1. Device Nomenclature
Device and Documentation Support
Submit Documentation Feedback
Product Folder Links: MSP430FG439 MSP430FG438 MSP430FG437
Copyright © 2004–2014, Texas Instruments Incorporated
79
MSP430FG439, MSP430FG438, MSP430FG437
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
7.2
www.ti.com
Documentation Support
The following documents describe the MSP430FG43x microcontrollers. Copies of these documents are
available on the Internet at www.ti.com.
7.2.1
SLAU056
MSP430x4xx Family User's Guide. Detailed description of all modules and peripherals
available in this device family.
SLAZ365
MSP430FG439 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
SLAZ364
MSP430FG438 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
SLAZ363
MSP430FG437 Device Erratasheet. Describes the known exceptions to the functional
specifications for all silicon revisions of this device.
Related Links
Table 7-1 lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 7-1. Related Links
PARTS
PRODUCT FOLDER
SAMPLE & BUY
TECHNICAL
DOCUMENTS
TOOLS &
SOFTWARE
SUPPORT &
COMMUNITY
MSP430FG439
Click here
Click here
Click here
Click here
Click here
MSP430FG438
Click here
Click here
Click here
Click here
Click here
MSP430FG437
Click here
Click here
Click here
Click here
Click here
7.2.2
Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the
respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views;
see TI's Terms of Use.
TI E2E™ Community
TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At
e2e.ti.com, you can ask questions, share knowledge, explore ideas, and help solve problems with fellow
engineers.
TI Embedded Processors Wiki
Texas Instruments Embedded Processors Wiki. Established to help developers get started with embedded
processors from Texas Instruments and to foster innovation and growth of general knowledge about the
hardware and software surrounding these devices.
7.3
Trademarks
MSP430, E2E are trademarks of Texas Instruments.
7.4
Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.5
Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
80
Device and Documentation Support
Copyright © 2004–2014, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: MSP430FG439 MSP430FG438 MSP430FG437
MSP430FG439, MSP430FG438, MSP430FG437
www.ti.com
SLAS380D – APRIL 2004 – REVISED NOVEMBER 2014
8 Mechanical Packaging and Orderable Information
8.1
Packaging Information
The following pages include mechanical packaging and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and
revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Mechanical Packaging and Orderable Information
Submit Documentation Feedback
Product Folder Links: MSP430FG439 MSP430FG438 MSP430FG437
Copyright © 2004–2014, Texas Instruments Incorporated
81
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
MSP430A008IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG439
MSP430A017IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG437
MSP430A018IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG439
MSP430A079IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG438
MSP430A095IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG438
MSP430FG437IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG437
MSP430FG437IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG437
MSP430FG437IZCAR
ACTIVE
NFBGA
ZCA
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG437
MSP430FG437IZCAT
ACTIVE
NFBGA
ZCA
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG437
MSP430FG438IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG438
MSP430FG438IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG438
MSP430FG438IZCAR
ACTIVE
NFBGA
ZCA
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG438
MSP430FG438IZCAT
ACTIVE
NFBGA
ZCA
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG438
MSP430FG439IPN
ACTIVE
LQFP
PN
80
119
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG439
MSP430FG439IPNR
ACTIVE
LQFP
PN
80
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-3-260C-168 HR
-40 to 85
M430FG439
MSP430FG439IZCAR
ACTIVE
NFBGA
ZCA
113
2500
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG439
MSP430FG439IZCAT
ACTIVE
NFBGA
ZCA
113
250
Green (RoHS
& no Sb/Br)
SNAGCU
Level-3-260C-168 HR
-40 to 85
FG439
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
15-Apr-2017
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2015
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
MSP430FG437IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430FG437IZCAR
NFBGA
ZCA
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG437IZCAT
NFBGA
ZCA
113
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG438IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430FG438IZCAR
NFBGA
ZCA
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG438IZCAT
NFBGA
ZCA
113
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG439IPNR
LQFP
PN
80
1000
330.0
24.4
15.0
15.0
2.1
20.0
24.0
Q2
MSP430FG439IZCAR
NFBGA
ZCA
113
2500
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
MSP430FG439IZCAT
NFBGA
ZCA
113
250
330.0
16.4
7.3
7.3
1.5
12.0
16.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
27-Jun-2015
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
MSP430FG437IPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430FG437IZCAR
NFBGA
ZCA
113
2500
341.0
336.6
31.8
MSP430FG437IZCAT
NFBGA
ZCA
113
250
341.0
336.6
31.8
MSP430FG438IPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430FG438IZCAR
NFBGA
ZCA
113
2500
341.0
336.6
31.8
MSP430FG438IZCAT
NFBGA
ZCA
113
250
341.0
336.6
31.8
MSP430FG439IPNR
LQFP
PN
80
1000
367.0
367.0
45.0
MSP430FG439IZCAR
NFBGA
ZCA
113
2500
341.0
336.6
31.8
MSP430FG439IZCAT
NFBGA
ZCA
113
250
341.0
336.6
31.8
Pack Materials-Page 2
MECHANICAL DATA
MTQF010A – JANUARY 1995 – REVISED DECEMBER 1996
PN (S-PQFP-G80)
PLASTIC QUAD FLATPACK
0,27
0,17
0,50
0,08 M
41
60
61
40
80
21
0,13 NOM
1
20
Gage Plane
9,50 TYP
12,20
SQ
11,80
14,20
SQ
13,80
0,25
0,05 MIN
0°– 7°
0,75
0,45
1,45
1,35
Seating Plane
0,08
1,60 MAX
4040135 / B 11/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-026
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
1
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