TI1 CSD97396Q4MT Synchronous buck nexfet power stage Datasheet

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CSD97396Q4M
SLPS572 – DECEMBER 2015
CSD97396Q4M Synchronous Buck NexFET™ Power Stage
1 Features
2 Applications
•
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•
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•
•
•
•
•
•
•
•
•
•
1
Over 93% System Efficiency at 15 A
Max Rated Continuous Current 30 A, Peak 65 A
High Frequency Operation (up to 2 MHz)
High Density – SON 3.5 mm × 4.5 mm Footprint
Ultra-Low Inductance Package
System-Optimized PCB Footprint
Ultra-Low Quiescent (ULQ) Current Mode
3.3 V and 5 V PWM Signal Compatible
Diode Emulation Mode With FCCM
Input Voltages up to 24 V
Tri-State PWM Input
Integrated Bootstrap Diode
Shoot-Through Protection
RoHS Compliant – Lead Free Terminal Plating
Halogen Free
Ultrabook/Notebook DC/DC Converters
Multiphase Vcore and DDR Solutions
Point-of-Load Synchronous Buck in Networking,
Telecom, and Computing Systems
3 Description
The CSD97396Q4M NexFET™ Power Stage is a
highly optimized design for use in a high-power, highdensity synchronous buck converter. This product
integrates the driver IC and NexFET technology to
complete the power stage switching function. The
driver IC has a built-in selectable diode emulation
function that enables DCM operation to improve light
load efficiency. In addition, the driver IC supports
ULQ mode that enables connected standby for
Windows® 8. With the PWM input in tri-state,
quiescent current is reduced to 130 µA, with
immediate response. When SKIP# is held at tri-state,
the current is reduced to 8 µA (typically 20 µs is
required to resume switching). This combination
produces a high current, high efficiency, and high
speed switching device in a small 3.5 × 4.5 mm
outline package. In addition, the PCB footprint is
optimized to help reduce design time and simplify the
completion of the overall system design.
Device Information(1)
ORDER NUMBER
CSD97396Q4M
CSD97396Q4MT
PACKAGE
SON 3.5 × 4.5 mm
Plastic Package
MEDIA AND QTY
13-inch reel
2500
7-inch reel
250
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
SPACER
Typical Power Stage Efficiency and Power Loss
VIN
VOUT
VCC
VCC
VOUT
PWM1
+Is1
-Is2
+NTC
-NTC
+Is2
-Is2
PWM2
VOUT
SS
RT
PGND
Multi-Phase
Controller
Efficiency (%)
CSD97396
100
10
90
8
VDD = 5 V
VIN = 12 V
VOUT = 1.8 V
LOUT = 0.29 PH
fSW = 500 kHz
TA = 25qC
80
70
6
4
60
Power Loss (W)
Application Diagram
2
50
0
5
10
15
20
Output Current (A)
25
0
30
D000
CSD97396
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CSD97396Q4M
SLPS572 – DECEMBER 2015
www.ti.com
Table of Contents
1
2
3
4
5
6
7
Features ..................................................................
Applications ...........................................................
Description .............................................................
Revision History.....................................................
Pin Configuration and Functions .........................
Specifications.........................................................
1
1
1
2
3
4
6.1
6.2
6.3
6.4
6.5
4
4
4
4
5
9
Overview ...................................................................
Functional Block Diagram .........................................
Feature Description...................................................
Device Functional Modes..........................................
Layout ................................................................... 14
9.1 Layout Guidelines ................................................... 14
9.2 Layout Example ...................................................... 14
9.3 Thermal Considerations .......................................... 14
10 Device and Documentation Support ................. 15
10.1
10.2
10.3
10.4
Detailed Description .............................................. 6
7.1
7.2
7.3
7.4
8
Absolute Maximum Ratings ......................................
ESD Ratings..............................................................
Recommended Operating Conditions.......................
Thermal Information ..................................................
Electrical Characteristics...........................................
8.1 Application Information.............................................. 9
8.2 Typical Application ................................................... 9
8.3 System Example ..................................................... 12
Community Resources..........................................
Trademarks ...........................................................
Electrostatic Discharge Caution ............................
Glossary ................................................................
15
15
15
15
11 Mechanical, Packaging, and Orderable
Information ........................................................... 16
6
6
6
8
11.1 Mechanical Drawing.............................................. 16
11.2 Recommended PCB Land Pattern........................ 17
11.3 Recommended Stencil Opening ........................... 17
Application and Implementation .......................... 9
4 Revision History
2
DATE
REVISION
NOTES
December 2015
*
Initial release.
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SLPS572 – DECEMBER 2015
5 Pin Configuration and Functions
SON 3.5 × 4.5 mm
Top View
SKIP#
1
8
PWM
VDD
2
7
BOOT
PGND
3
6
BOOT_R
9
PGND
VSW
4
5
VIN
Pin Functions
PIN
NO.
DESCRIPTION
NAME
1
SKIP#
This pin enables the Diode Emulation function. When this pin is held low, diode emulation mode is enabled for the
Sync FET. When SKIP# is high, the CSD97396Q4M operates in forced continuous conduction mode. A tri-state
voltage on SKIP# puts the driver into a very low power state.
2
VDD
Supply voltage to gate drivers and internal circuitry.
3
PGND
Power ground, needs to be connected to Pin 9 and PCB
4
VSW
Voltage switching node – pin connection to the output inductor.
5
VIN
Input voltage pin. Connect input capacitors close to this pin.
6
BOOT_R
7
BOOT
Bootstrap capacitor connection. Connect a minimum 0.1 µF 16 V X5R, ceramic cap from BOOT to BOOT_R pins. The
bootstrap capacitor provides the charge to turn on the Control FET. The bootstrap diode is integrated. Boot_R is
internally connected to VSW.
8
PWM
Pulse width modulated 3-state input from external controller. Logic low sets Control FET gate low and Sync FET gate
high. Logic high sets Control FET gate high and Sync FET gate Low. Open or High Z sets both MOSFET gates low if
greater than the Tri-State Shutdown Hold-off Time (t3HT)
9
PGND
Power Ground
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6 Specifications
6.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted) (1)
MIN
MAX
UNIT
VIN to PGND
–0.3
30
V
VSW to PGND , VIN to VSW
–0.3
30
V
–7
33
V
VDD to PGND
–0.3
6
V
PWM, SKIP# to PGND
–0.3
6
V
BOOT to PGND
–0.3
35
V
–2
38
V
–0.3
6
V
VSW to PGND, VIN to VSW (<10 ns)
BOOT to PGND (<10 ns)
BOOT to BOOT_R
BOOT to BOOT_R (duty cycle <0.2%)
8
V
PD
Power dissipation
8
W
TJ
Operating temperature
–40
150
°C
Tstg
Storage temperature
–55
150
°C
(1)
Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only
and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
VALUE
V(ESD)
(1)
(2)
Human body model (HBM)
Electrostatic discharge
(1)
UNIT
±1000
Charged device model (CDM) (2)
V
±500
JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process.
JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
TA = 25°C (unless otherwise noted)
VDD
Gate drive voltage
MIN
MAX
4.5
5.5
V
24
V
30
A
65
A
(1)
VIN
Input supply voltage
IOUT
Continuous output current
IOUT-PK
Peak output current (3)
VIN = 12 V, VDD = 5 V, VOUT = 1.8 V,
ƒSW = 500 kHz, LOUT = 0.29 µH (2)
ƒSW
Switching frequency
CBST = 0.1 µF (min)
2000
On-time duty cycle
(1)
(2)
(3)
UNIT
kHz
85%
Minimum PWM on-time
40
Operating temperature
–40
ns
125
°C
Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For
reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings.
Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
System conditions as defined in Note 2. Peak Output Current is applied for tp = 10 ms, duty cycle ≤1%
6.4 Thermal Information
TA = 25°C (unless otherwise noted)
THERMAL METRIC
RθJC
RθJB
(1)
(2)
4
Junction-to-case thermal resistance (top of package) (1)
Junction-to-board thermal resistance
(2)
MIN
TYP
MAX
UNIT
22.8
°C/W
2.5
°C/W
RθJC is determined with the device mounted on a 1 inch² (6.45 cm²), 2 oz (0.071 mm thick) Cu pad on a 1.5 inch x 1.5 inch, 0.06 inch
(1.52 mm) thick FR4 board.
RθJB value based on hottest board temperature within 1 mm of the package.
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6.5 Electrical Characteristics
TA = 25°C, VDD = POR to 5.5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
PLOSS
Power Loss (1)
VIN = 12 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 25°C
1.9
W
Power Loss (2)
VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 25°C
2.2
W
Power Loss (2)
VIN = 19 V, VDD = 5 V, VOUT = 1.8 V, IOUT = 15 A,
ƒSW = 500 kHz, LOUT = 0.29 µH, TJ = 125°C
2.6
W
VIN
IQ
VIN quiescent current
PWM = Floating, VDD = 5 V, VIN= 24 V
1
µA
VDD
IDD
Standby supply current
IDD
Operating supply current
PWM = Float, SKIP# = VDD or 0 V
SKIP# = Float
PWM = 50% Duty cycle, ƒSW = 500 kHz
130
µA
8
µA
7.8
mA
POWER-ON RESET AND UNDERVOLTAGE LOCKOUT
VDD Rising
Power-on reset
VDD Falling
UVLO
4.15
3.7
Hysteresis
V
V
0.2
mV
PWM AND SKIP# I/O SPECIFICATIONS
Pull up to VDD
1700
RI
Input impedance
VIH
Logic level high
VIL
Logic level low
VIH
Hysteresis
VTS
Tri-state voltage
tTHOLD(off1)
Tri-state activation time
(falling) PWM (2)
60
tTHOLD(off2)
Tri-state activation time
(rising) PWM (2)
60
tTSKF
Tri-state activation time
(falling) SKIP# (2)
1
tTSKR
Tri-state activation time
(rising) SKIP# (2)
1
t3RD(PWM)
Tri-state exit time PWM (2)
100
ns
t3RD(SKIP#)
Tri-state exit time SKIP# (2)
50
µs
240
mV
2
µA
Pull down (to GND)
kΩ
800
2.65
0.6
0.2
1.3
V
2
ns
µs
BOOTSTRAP SWITCH
VFBST
IRLEAK
(1)
(2)
Forward voltage
Reverse leakage
IF = 10 mA
(2)
VBST – VDD = 25 V
120
Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins.
Specified by design.
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7 Detailed Description
7.1 Overview
The CSD97396Q4M NexFET™ Power Stage is a highly optimized design for use in a high-power, high-density
synchronous buck converter.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Powering CSD97396Q4M and Gate Drivers
An external VDD voltage is required to supply the integrated gate driver IC and provide the necessary gate drive
power for the MOSFETs. A 1 µF 10 V X5R or higher ceramic capacitor is recommended to bypass VDD pin to
PGND. A bootstrap circuit to provide gate drive power for the Control FET is also included. The bootstrap supply
to drive the Control FET is generated by connecting a 100 nF 16 V X5R ceramic capacitor between BOOT and
BOOT_R pins. An optional RBOOT resistor can be used to slow down the turn on speed of the Control FET and
reduce voltage spikes on the VSW node. A typical 1 Ω to 4.7 Ω value is a compromise between switching loss
and VSW spike amplitude.
7.3.2 Undervoltage Lockout (UVLO) Protection
The UVLO comparator evaluates the VDD voltage level. As VVDD rises, both the Control FET and Sync FET
gates hold actively low at all times until VVDD reaches the higher UVLO threshold (VUVLO_H)., Then the driver
becomes operational and responds to PWM and SKIP# commands. If VDD falls below the lower UVLO threshold
(VUVLO_L = VUVLO_H – Hysteresis), the device disables the driver and drives the outputs of the Control FET and
Sync FET gates actively low. Figure 1 shows this function.
CAUTION
Do not start the driver in the very low power mode (SKIP# = Tri-state).
6
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Feature Description (continued)
VUVLO_H
VUVLO_L
VVDD
Driver On
UDG-12218
Figure 1. UVLO Operation
7.3.3 PWM Pin
The PWM pin incorporates an input tri-state function. The device forces the gate driver outputs to low when
PWM is driven into the tri-state window and the driver enters a low power state with zero exit latency. The pin
incorporates a weak pull-up to maintain the voltage within the tri-state window during low-power modes.
Operation into and out of tri-state mode follows the timing diagram outlined in Figure 2.
When VDD reaches the UVLO_H level, a tri-state voltage range (window) is set for the PWM input voltage. The
window is defined the PWM voltage range between PWM logic high (VIH) and logic low (VIL) thresholds. The
device sets high-level input voltage and low-level input voltage threshold levels to accommodate both 3.3 V
(typical) and 5 V (typical) PWM drive signals.
When the PWM exits tri-state, the driver enters CCM for a period of 4 µs, regardless of the state of the SKIP#
pin. Normal operation requires this time period in order for the auto-zero comparator to resume.
Figure 2. PWM Tri-State Timing Diagram
7.3.4 SKIP# Pin
The SKIP# pin incorporates the input tri-state buffer as PWM. The function is somewhat different. When SKIP# is
low, the zero crossing (ZX) detection comparator is enabled, and DCM mode operation occurs if the load current
is less than the critical current. When SKIP# is high, the ZX comparator disables, and the converter enters FCCM
mode. When both SKIP# and PWM are tri-stated, normal operation forces the gate driver outputs low and the
driver enters a low-power state. In the low-power state, the UVLO comparator remains off to reduce quiescent
current. When SKIP# is pulled low, the driver wakes up and is able to accept PWM pulses in less than 50 µs.
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Feature Description (continued)
Table 1 shows the logic functions of UVLO, PWM, SKIP#, the Control FET Gate and the Sync FET Gate.
Table 1. Logic Functions of the Driver IC
UVLO
(1)
(2)
(3)
PWM
SKIP#
SYNC FET GATE
CONTROL FET GATE
MODE
Active
—
—
Low
Low
Disabled
Inactive
Low
Low
High (1)
Low
DCM (1)
Inactive
Low
High
High
Low
FCCM
Inactive
High
H or L
Low
High
Inactive
Tri-state
H or L
Low
Low
LQ (2)
Inactive
—
Tri-state
Low
Low
ULQ (3)
Until zero crossing protection occurs.
Low quiescent current (LQ)
Ultra-low quiescent current (ULQ)
7.3.4.1 Zero Crossing (ZX) Operation
The zero crossing comparator is adaptive for improved accuracy. As the output current decreases from a heavy
load condition, the inductor current also reduces and eventually arrives at a valley, where it touches zero current,
which is the boundary between continuous conduction and discontinuous conduction modes. The SW pin detects
the zero-current condition. When this zero inductor current condition occurs, the ZX comparator turns off the
rectifying MOSFET.
7.3.5 Integrated Boost-Switch
To maintain a BST-SW voltage close to VDD (to get lower conduction losses on the high-side FET), the
conventional diode between the VDD pin and the BST pin is replaced by a FET which is gated by the DRVL
signal.
7.4 Device Functional Modes
Table 1 shows the different functional modes of CSD97396. The diode emulation mode is enabled with SKIP#
pulled low, which improves light load efficiency. With PWM in tri-state, Power Stage enters LQ mode and the
quiescent current is reduced to 130 µA. When SKIP# is held in tri-state, ULQ mode is enabled and the current is
decreased to 8 µA.
8
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The Power Stage CSD97396Q4M is a highly optimized design for synchronous buck applications using NexFET
devices with a 5 V gate drive. The Control FET and Sync FET silicon are parametrically tuned to yield the lowest
power loss and highest system efficiency. As a result, a rating method is used that is tailored towards a more
systems centric environment. The high-performance gate driver IC integrated in the package helps minimize the
parasitics and results in extremely fast switching of the power MOSFETs. System level performance curves such
as Power Loss, SOA, and normalized graphs allow engineers to predict the product performance in the actual
application.
8.2 Typical Application
Figure 3. Application Schematic
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Typical Application (continued)
8.2.1 Application Curves
TJ = 125°C, unless stated otherwise. The Typical CSD97396Q4M System Characteristic curves (see Figure 6 and Figure 7)
are based on measurements made on a PCB design with dimensions of 4.0" (W) × 3.5" (L) × 0.062" (T) and 6 copper layers
of 1 oz. copper thickness. See System Example for detailed explanation.
12
1.05
Typ
Max
1
Power Loss, Normalized
Power Loss (W)
10
8
6
4
0.95
0.9
0.85
0.8
0.75
0.7
2
0.65
0
3
6
9
VIN = 12 V
ƒSW = 500 kHz
12
15
18
21
Output Current (A)
24
27
0.6
-50
30
VDD = 5 V
LOUT = 0.29 µH
VOUT = 1.8 V
VIN = 12 V
ƒSW = 500 kHz
35
35
30
30
25
25
20
15
10
400 LFM
200 LFM
100 LFM
Nat. conv.
VDD = 5 V
LOUT = 0.29 µH
125
150
D002
VOUT = 1.8 V
20
15
10
5
Min
Typ
0
0
0
10
20
VIN = 12 V
ƒSW = 500 kHz
30
40
50
60
70
Ambient Temperature (qC)
VDD = 5 V
LOUT = 0.29 µH
80
90
100
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0
20
D003
VOUT = 1.8 V
Figure 6. Safe Operating Area – PCB Horizontal Mount
10
0
25
50
75
100
TC - Junction Temperature (qC)
Figure 5. Power Loss vs Temperature
Output Current (A)
Output Current (A)
Figure 4. Power Loss vs Output Current
5
-25
D001
VIN = 12 V
ƒSW = 500 kHz
40
60
80
100
Board Temperature (qC)
VDD = 5 V
LOUT = 0.29 µH
120
140
D004
VOUT = 1.8 V
Figure 7. Typical Safe Operating Area
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Typical Application (continued)
3.8
1.14
1.6
1.3
3.3
1.12
1.3
1.25
2.7
1.1
1.1
1.2
2.2
1.08
0.9
1.15
1.6
1.06
0.7
1.1
1.1
1.04
0.4
0.0
0.95
200
400
-0.5
800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
D005
600
VIN = 12 V
IOUT = 25 A
VDD = 5 V
LOUT = 0.29 µH
1.02
0.2
1
0.0
0.98
3
VOUT = 1.8 V
9
11
13
15
Input Voltage (V)
17
19
21
-0.2
23
D006
VDD = 5 V
LOUT = 0.29 µH
VOUT = 1.8 V
Figure 9. Normalized Power Loss vs Input Voltage
4.4
1.2
2.2
1.3
3.3
1.15
1.7
1.2
2.2
1.1
1.1
1.1
1.1
1.05
0.6
1
0.0
1
0.0
0.9
-1.1
0.8
0.7
0.8
1.2
1.6
VIN = 12 V
ƒSW = 500 kHz
2
2.4
2.8
Output Voltage (V)
VDD = 5 V
LOUT = 0.29 µH
3.2
Power Loss, Normalized
1.4
SOA Temperature Adj. (qC)
Power Loss, Normalized
7
IOUT = 25 A
ƒSW = 500 kHz
Figure 8. Normalized Power Loss vs Frequency
0.95
-0.6
-2.2
0.9
-1.1
-3.3
3.6
0.85
0
9.4
30
9.3
Driver Current (mA)
35
25
20
15
9
5
8.8
VIN = 12 V
LOUT = 0.29 µH
VDD = 5 V
VOUT = 1.8 V
IOUT = 25 A
Figure 12. Driver Current vs Frequency
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D008
IOUT = 25 A
9.1
8.9
800 1000 1200 1400 1600 1800 2000 2200
Switching Frequency (kHz)
D009
VDD = 5 V
VOUT = 1.8 V
-1.7
1200
9.2
10
600
1000
Figure 11. Normalized Power Loss vs Output Inductance
9.5
400
400
600
800
Output Inductance (nH)
VIN = 12 V
ƒSW = 500 kHz
40
0
200
200
D007
IOUT = 25 A
Figure 10. Normalized Power Loss vs Output Voltage
Driver Current (mA)
5
SOA Temperature Adj. (qC)
0.5
1
Power Loss, Normalized
1.05
SOA Temperature Adj. (qC)
1.35
SOA Temperature Adj. (qC)
Power Loss, Normalized
TJ = 125°C, unless stated otherwise. The Typical CSD97396Q4M System Characteristic curves (see Figure 6 and Figure 7)
are based on measurements made on a PCB design with dimensions of 4.0" (W) × 3.5" (L) × 0.062" (T) and 6 copper layers
of 1 oz. copper thickness. See System Example for detailed explanation.
8.7
-75
-50
-25
0
25
50
75
100
TC - Junction Temperature (qC)
VIN = 12 V
IOUT = 25 A
VDD = 5 V
LOUT = 0.29 µH
125
150
D010
VOUT = 1.8 V
Figure 13. Driver Current vs Temperature
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8.3 System Example
8.3.1 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are primarily needed by engineers to estimate the loss
generated by the devices. In an effort to simplify the design process for engineers, Texas Instruments has
provided measured power loss performance curves. Figure 4 plots the power loss of the CSD97396Q4M as a
function of load current. This curve is measured by configuring and running the CSD97396Q4M as it would be in
the final application (see Figure 14). The measured power loss is the CSD97396Q4M device power loss which
consists of both input conversion loss and gate drive loss. Equation 1 is used to generate the power loss curve.
Power Loss = (VIN × IIN) + (VDD × IDD) – (VSW_AVG × IOUT)
(1)
The power loss curve in Figure 4 is measured at the maximum recommended junction temperature of
TJ = 125°C under isothermal test conditions.
8.3.2 SOA Curves
The SOA curves in the CSD97396Q4M datasheet give engineers guidance on the temperature boundaries within
an operating system by incorporating the thermal resistance and system power loss. Figure 6 and Figure 7
outline the temperature and airflow conditions required for a given load current. The area under the curve
dictates the safe operating area. All the curves are based on measurements made on a PCB design with
dimensions of 4.0 inches (W) × 3.5 inches (L) × 0.062 inch (T) and 6 copper layers of 1 oz. copper thickness.
8.3.3 Normalized Curves
The normalized curves in the CSD97396Q4M data sheet give engineers guidance on the Power Loss and SOA
adjustments based on their application specific needs. These curves show how the power loss and SOA
boundaries will adjust for a given set of systems conditions. The primary Y-axis is the normalized change in
power loss and the secondary Y-axis is the change is system temperature required in order to comply with the
SOA curve. The change in power loss is a multiplier for the Power Loss curve and the change in temperature is
subtracted from the SOA curve.
CSD97396Q4M
Vin
VDD
Gate Drive
Voltage (VDD)
A
VIN
VDD
A
Input Current (IIN)
Boot
Gate Drive
Current (IDD)
BST
HSgate
V
DRVH
CBoot
Control
FET
Cin
V
Input Voltage
(VIN)
Boot_R
Vsw
SKIP#
LL
VSW
LO
VO
A
SKIP#
PWM
LSgate
PWM
DRVL
Sync
FET
Co
Output Current
(IOUT)
GND
PGND
Averaging
Circuit
V
Averaged Switched
Node Voltage
(VSW_AVG)
Figure 14. Power Loss Test Circuit
12
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System Example (continued)
8.3.4 Calculating Power Loss and SOA
The user can estimate product loss and SOA boundaries by arithmetic means (see the Design Example).
Though the Power Loss and SOA curves in this datasheet are taken for a specific set of test conditions, the
following procedure will outline the steps engineers should take to predict product performance for any set of
system conditions.
8.3.4.1 Design Example
Operating Conditions: Output Current (lOUT) = 20 A, Input Voltage (VIN ) = 7 V, Output Voltage (VOUT) = 2.0 V,
Switching Frequency (ƒSW) = 800 kHz, Output Inductor (LOUT) = 0.2 µH
8.3.4.2 Calculating Power Loss
•
•
•
•
•
•
Typical Power Loss at 20 A = 3.71 W (Figure 4)
Normalized Power Loss for switching frequency ≈ 1.01 (Figure 8)
Normalized Power Loss for input voltage ≈ 1.04 (Figure 9)
Normalized Power Loss for output voltage ≈ 1.04 (Figure 10)
Normalized Power Loss for output inductor ≈ 1.07 (Figure 11)
Final calculated Power Loss = 3.71 W × 1.01 × 1.04 × 1.04 × 1.07 ≈ 4.34 W
8.3.4.3 Calculating SOA Adjustments
•
•
•
•
•
SOA adjustment for switching frequency ≈ 0.16°C (Figure 8)
SOA adjustment for input voltage ≈ 0.42°C (Figure 9)
SOA adjustment for output voltage ≈ 0.46°C (Figure 10)
SOA adjustment for output inductor ≈ 0.74°C (Figure 11)
Final calculated SOA adjustment = 0.16 + 0.42 + 0.46 + 0.74 ≈ 1.78°C
Figure 15. Power Stage CSD97396Q4M SOA
In the design example above, the estimated power loss of the CSD97396Q4M would increase to 4.23 W. In
addition, the maximum allowable board and/or ambient temperature would have to decrease by 1.78°C.
Figure 15 graphically shows how the SOA curve would be adjusted accordingly.
1. Start by drawing a horizontal line from the application current to the SOA curve.
2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient
temperature of 1.78°C. In the event the adjustment value is a negative number, subtracting the negative number
would yield an increase in allowable board/ambient temperature.
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9 Layout
9.1 Layout Guidelines
9.1.1 Recommended PCB Design Overview
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and
thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. Below
is a brief description on how to address each parameter.
9.1.2 Electrical Performance
The CSD97396Q4M has the ability to switch at voltage rates greater than 10 kV/µs. Special care must be then
taken with the PCB layout design and placement of the input capacitors, inductor and output capacitors.
• The placement of the input capacitors relative to VIN and PGND pins of CSD97396Q4M device should have the
highest priority during the component placement routine. It is critical to minimize these node lengths. As such,
ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 16).
The example in Figure 16 uses 1 × 1 nF 0402 25 V and 3 × 10 µF 1206 25 V ceramic capacitors (TDK Part #
C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an
appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power
Stage C5, C8 and C6, C19 should follow in order.
• The bootstrap cap CBOOT 0.1 µF 0603 16 V ceramic capacitor should be closely connected between BOOT
and BOOT_R pins
• The switching node of the output inductor should be placed relatively close to the Power Stage
CSD97396Q4M VSW pins. Minimizing the VSW node length between these two components will reduce the
PCB conduction losses and actually reduce the switching noise level. (1)
9.2 Layout Example
Figure 16. Recommended PCB Layout (Top Down View)
9.3 Thermal Considerations
The CSD97396Q4M has the ability to use the GND planes as the primary thermal path. As such, the use of
thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder
voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount
of solder attach that will wick down the via barrel:
• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 16 uses vias with a 10 mil drill hole
and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask.
In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and
manufacturing capabilities.
(1)
14
Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of
Missouri – Rolla
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10 Device and Documentation Support
10.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
10.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments.
Windows is a registered trademark of Microsoft Corporation.
All other trademarks are the property of their respective owners.
10.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
10.4 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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CSD97396Q4M
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11 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
11.1 Mechanical Drawing
•°
c1
a1
D2
0.300
(x45°)
1
8
5
MILLIMETERS
DIM
16
4
INCHES
MIN
NOM
MAX
MIN
NOM
MAX
A
0.800
0.900
1.000
0.031
0.035
0.039
a1
0.000
0.000
0.080
0.000
0.000
0.003
b
0.150
0.200
0.250
0.006
0.008
0.010
b1
2.000
2.200
2.400
0.079
0.087
0.095
b2
0.150
0.200
0.250
0.006
0.008
0.010
c1
0.150
0.200
0.250
0.006
0.008
0.010
D2
3.850
3.950
4.050
0.152
0.156
0.160
E
4.400
4.500
4.600
0.173
0.177
0.181
E1
3.400
3.500
3.600
0.134
0.138
0.142
E2
2.000
2.100
2.200
0.079
0.083
0.087
e
0.400 TYP
K
0.300 TYP
0.016 TYP
0.012 TYP
L
0.300
0.400
0.500
0.012
0.016
0.020
L1
0.180
0.230
0.280
0.007
0.009
0.011
θ
0.00
—
—
0.00
—
—
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11.2 Recommended PCB Land Pattern
(0.010)
0.250
(x18)
(0.006)
0.150
(0.006)
0.150
(0.016)
0.400
(0.024)
0.600 (x 2)
(0.008)
0.200
(x2)
(0.087)
2.200
R0.100
R0.100
0.225 ( x 2)
(0.009)
(0.088)
2.250
(0.012)
0.300
(0.159)
4.050
11.3 Recommended Stencil Opening
(0.008)
0.200
(0.008)
0.200
(0.029)
0.738 (x 8)
(0.016)
0.400
(0.015)
0.390
(0.014)
0.350
0.300
(0.012)
R0.100
0.850 (x8)
(0.033)
(0.012)
0.300
R0.100
0.225 ( x 2)
(0.004)
0.115
0.440 (0.017)
(0.009)
0.225
(0.008)
0.200
(0.087)
2.200
0.200
(0.008)
NOTE: Dimensions are in mm (inches).
Stencil is 100 µm thick.
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PACKAGE OPTION ADDENDUM
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16-Dec-2015
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
CSD97396Q4M
ACTIVE
VSON-CLIP
DPC
8
2500
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
97396M
CSD97396Q4MT
ACTIVE
VSON-CLIP
DPC
8
250
Pb-Free (RoHS
Exempt)
CU NIPDAU
Level-2-260C-1 YEAR
-40 to 150
97396M
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
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16-Dec-2015
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
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