STMicroelectronics M36W108T100ZM5T 8 mbit 1mb x8, boot block flash memory and 1 mbit 128kb x8 sram low voltage multi-memory product Datasheet

M36W108T
M36W108B
8 Mbit (1Mb x8, Boot Block) Flash Memory and
1 Mbit (128Kb x8) SRAM Low Voltage Multi-Memory Product
NOT FOR NEW DESIGN
■
M36W108T and M36W108B are replaced
respectively by the M36W108AT and
M36W108AB
■
SUPPLY VOLTAGE
– VCCF = VCCS = 2.7V to 3.6V: for Program,
Erase and Read
■
ACCESS TIME: 100ns
■
LOW POWER CONSUMPTION
LGA
BGA
LBGA48 (ZM)
6 x 8 solder balls
– Read: 40mA max. (SRAM chip)
LGA48 (ZN)
6 x 8 solder lands
– Stand-by: 30µA max. (SRAM chip)
– Read: 10mA max. (Flash chip)
– Stand-by: 100µA max. (Flash chip)
FLASH MEMORY
■ 8 Mbit (1Mb x 8) BOOT BLOCK ERASE
■
PROGRAMMING TIME: 10µs typical
■
PROGRAM/ERASE CONTROLLER (P/E.C.)
Figure 1. Logic Diagram
– Program Byte-by-Byte
VCCF VCCS
– Status Register bits and Ready/Busy Output
■
MEMORY BLOCKS
– Boot Block (Top or Bottom location)
– Parameter and Main Blocks
■
BLOCK, MULTI-BLOCK and CHIP ERASE
■
ERASE SUSPEND and RESUME MODES
20
A0-A19
– Read and Program another Block during
Erase Suspend
■
■
8
100,000 PROGRAM/ERASE CYCLES per
BLOCK
ELECTRONIC SIGNATURE
– Manufacturer Code: 20h
DQ0-DQ7
W
EF
G
M36W108T
M36W108B
RB
RP
E1S
E2S
– Device Code, M36W108T: D2h
– Device Code, M36W108B: DCh
SRAM
■ 1 Mbit (128Kb x 8)
■
POWER DOWN FEATURES USING TWO
CHIP ENABLE INPUTS
■
LOW VCC DATA RETENTION: 2V
May 1999
This is information on a product still in production but not recommended for new designs.
VSS
AI02509
1/35
M36W108T, M36W108B
Figure 2. LBGA and LGA Connections (Top View)
1
2
3
A
W
A14
A11
B
VCCS
A18
C
A17
D
4
5
6
G
A10
E1S
A8
DQ7
DQ5
VSS
NC
A5
DQ4
DQ2
DQ1
VSS
EF
NC
DQ0
A0
A1
E
NC
NC
DQ3
A6
A3
A2
F
NC
VCCF
NC
A19
A7
A4
G
NC
DQ6
A13
RP
RB
E2S
H
NC
A12
NC
A16
A15
A9
AI02508
Table 1. Signal Names
A0-A16
Address Inputs
A17-A19
Address Inputs for Flash Chip
DQ0-DQ7
Data Input/Outputs, Command Inputs
for Flash Chip
EF
Chip Enable for Flash Chip
E1S, E2S
Chip Enable for SRAM Chip
G
Output Enable
W
Write Enable
RP
Reset for Flash Chip
RB
Ready/Busy Output for Flash Chip
VCCF
Supply Voltage for Flash Chip
VCCS
Supply Voltage for SRAM Chip
VSS
Ground
2/35
DESCRIPTION
The M36W108 is multi-chip device containing an
8 Mbit boot block Flash memory and a 1 Mbit of
SRAM. The device is offered in the new Chip
Scale Package solutions: LBGA48 1.0 mm ball
pitch and LGA48 1.0 mm land pitch.
The two components, of the package’s overall 9
Mbit of memory, are distinguishable by use of the
three chip enable lines: EF for the Flash memory,
E1S and E2S for the SRAM.
The Flash memory component is identical with the
M29W008 device. It is a non-volatile memory that
may be erased electrically at the block or chip level
and programmed in-system on a Byte-by-Byte basis using only a single 2.7V to 3.6V V CCF supply.
For Program and Erase operations the necessary
high voltages are generated internally. The device
can also be programmed in standard programmers. The array matrix organization allows each
block to be erased and reprogrammed without affecting other blocks.
Instructions for Read/Reset, Auto Select for reading the Electronic Signature, Programming, Block
M36W108T, M36W108B
Table 2. Absolute Maximum Ratings (1)
Symbol
Value
Unit
Ambient Operating Temperature (3)
–40 to 85
°C
TBIAS
Temperature Under Bias
–50 to 125
°C
TSTG
Storage Temperature
–65 to 150
°C
VIO (2)
Input or Output Voltage
–0.5 to VCC +0.5
V
VCCF
Flash Chip Supply Voltage
–0.6 to 5
V
VCCS
SRAM Chip Supply Voltage
–0.3 to 4.6
V
EF, RP Voltage
0.6 to 13.5
V
0.7
W
TA
V(EF, RP)
PD
Parameter
Power Dissipation
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may
cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions
above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents.
2. Minimum Voltage may undershoot to –2V during transition and for less than 20ns.
3. Depends on range.
and Chip Erase, Erase Suspend and Resume are
written to the device in cycles of commands to a
Command Interface using standard microprocessor write timings.
The SRAM component is a low power SRAM that
features fully static operation requiring no external
clocks or timing strobes, with equal address access and cycle times. It requires a single 2.7V to
3.6V V CCS supply, and all inputs and outputs are
TTL compatible.
SIGNAL DESCRIPTIONS
See Figure 1 and Table 1.
Address Inputs (A0-A16). Addresses A0 to A16
are common inputs for the Flash chip and the
SRAM chip. The address inputs for the Flash
memory or the SRAM array are latched during a
write operation on the falling edge of Flash Chip
Enable (EF), SRAM Chip Enable (E1S or E2S) or
Write Enable (W).
Address Inputs (A17-A19). Address A17 to A19
are address inputs for the Flash chip. They are
latched during a write operation on the falling edge
of Flash Chip Enable (EF) or Write Enable (W).
Data Input/Outputs (DQ0-DQ7). The input is
data to be programmed in the Flash or SRAM
memory array or a command to be written to the
C.I. of the Flash chip. Both are latched on the rising edge of Flash Chip Enable (EF), SRAM Chip
Enable (E1S or E2S) or Write Enable (W). The
output is data from the Flash memory or SRAM array, the Electronic Signature Manufacturer or Device codes or the Status register Data Polling bit
DQ7, the Toggle Bits DQ6 and DQ2, the Error bit
DQ5 or the Erase Timer bit DQ3. Outputs are valid
when Flash Chip Enable (EF) or SRAM Chip Enable (E1S or E2S) and Output Enable (G) are active. The output is high impedance when the both
the Flash chip and the SRAM chip are deselected
or the outputs are disabled and when Reset (RP)
is at a V IL.
Flash Chip Enable (EF). The Chip Enable input
for Flash activates the memory control logic, input
buffers, decoders and sense amplifiers. EF at VIH
deselects the memory and reduces the power consumption to the standby level. EF can also be
used to control writing to the command register
and to the Flash memory array, while W remains
at VIL. It is not allowed to set EF at VIL, E1S at VIL
and E2S at V IH at the same time.
SRAM Chip Enable (E1S, E2S). The Chip Enable inputs for SRAM activate the memory control
logic, input buffers, decoders and sense amplifiers. E1S at VIH or E2S at VIL deselects the memory and reduces the power consumption to the
standby level. E1S and E2S can also be used to
control writing to the SRAM memory array, while
W remains at VIL. It is not allowed to set EF at VIL,
E1S at VIL and E2S at VIH at the same time.
Output Enable (G). The Output Enable gates the
outputs through the data buffers during a read operation. When G is High the outputs are High impedance.
Write Enable (W). The Write Enable input controls writing to the Command Register of the Flash
chip and Address/Data latches.
3/35
M36W108T, M36W108B
Table 3. Main Operation Modes (1)
Operation Mode
EF
E1S
E2S
G
W
RP
DQ0-DQ7
VIL
VIH
X
VIL
VIH
VIH
Data Output
VIL
X
VIL
VIL
VIH
VIH
Data Output
VIH
VIL
VIH
VIL
VIH
X
Data Output
VIL
VIH
X
VIH
VIL
VIH
Data Input
VIL
X
VIL
VIH
VIL
VIH
Data Input
VIH
VIL
VIH
X
VIL
X
Data Input
X
VIH
X
VIH
VIH
X
Hi-Z
X
X
VIL
VIH
VIH
X
Hi-Z
SRAM Chip Output Disable
VIH
VIL
VIH
VIH
VIH
X
Hi-Z
Flash Chip Stand-by
VIH
X
X
X
X
VIH
Hi-Z
X
VIH
X
X
X
VIL
Hi-Z
X
X
VIL
X
X
VIL
Hi-Z
X
VIH
X
X
X
VIL
Hi-Z
X
X
VIL
X
X
VIL
Hi-Z
Flash Chip Read
SRAM Chip Read
Flash Chip Write
SRAM Chip Write
Flash Chip Output Disable
Flash Chip Reset
SRAM Chip Stand-by
Note: 1. X = VIL or VIH.
Reset Input (RP). The Reset input provides
hardware reset of the Flash chip. Reset of the
Flash memory is achieved by pulling RP to VIL for
at least t PLPX. When the reset pulse is given, if the
Flash memory is in Read or Standby modes, it will
be available for new operations in tPHEL after the
rising edge of RP.
If the Flash memory is in Erase or Program mode
the reset will take tPLYH during which the Ready/
Busy (RB) signal will be held at VIL. The end of the
Flash memory reset will be indicated by the rising
edge of RB. A hardware reset during an Erase or
Program operation will corrupt the data being programmed or the block(s) being erased. See Table
17 and Figure 9.
Ready/Busy Output (RB). Ready/Busy is an
open-drain output of the Flash chip. It gives the internal state of the Program/Erase Controller (P/
E.C.) of the Flash device. When RB is Low, the
Flash device is busy with a Program or Erase operation and it will not accept any additional program or erase instructions except the Erase
Suspend instruction. When RB is High, the Flash
device is ready for any Read, Program or Erase
operation. The RB will also be High when the
Flash memory is put in Erase Suspend or Standby
modes.
4/35
VCCF Supply Voltage. Flash memory power supply for all operations (Read, Program and Erase).
VCCS Supply Voltage. SRAM power supply for
all operations (Read, Program).
VSS Ground. VSS is the reference for all voltage
measurements.
POWER SUPPLY
Power Up. The Flash memory Command Interface is reset on power up to Read Array. Either
Flash Chip Enable (EF) or Write Enable (W) inputs
must be tied to VIH during Power Up to allow maximum security and the possibility to write a command on the first rising edge of EF and W. Any
write cycle initiation is blocked when VCCF is below
VLKO.
Supply Rails. Normal precautions must be taken
for supply voltage decoupling; each device in a
system should have the V CCF, VCCS rails decoupled with a 0.1µF capacitor close to the V CCF,
VCCS and V SS pins. The PCB trace widths should
be sufficient to carry the V CCF and V CCS program
currents and the V CCF erase current required.
M36W108T, M36W108B
Figure 3. Internal Functional Arrangement
VCCF
VSS
RP
RB
EF
8 Mbit
Flash Memory
(1Mb x 8)
A0-A19
DQ0-DQ7
W
G
VCCS
A0-A16
VSS
1 Mbit SRAM
(128 Kb x 8)
E1S
E2S
AI02444
5/35
M36W108T, M36W108B
FLASH MEMORY COMPONENT
Organization and Architecture
Organization. The Flash chip is organized as
1Mbit x 8. The memory uses the address inputs
A0-A19 and the Data Input/Outputs DQ0-DQ7.
Memory control is provided by Chip Enable (EF),
Output Enable (G) and Write Enable (W) inputs.
Erase and Program operations are controlled by
an internal Program/Erase Controller (P/E.C.).
Status Register data output on DQ7 provides a
Data Polling signal, while Status Register data outputs on DQ6 and DQ2 provide Toggle signals to
indicate the state of the P/E.C. operations. A
Ready/Busy (RB) output indicates the completion
of the internal algorithms.
Memory Blocks. The device features asymmetrically blocked architecture providing system memory integration. Both Top and Bottom Boot Block
devices have an array of 19 blocks, one Boot
Block of 16K Bytes, two Parameter Blocks of 8K
Bytes, one Main Block of 32K Bytes and fifteen
Main Blocks of 64K Bytes. The Top Boot Block
version has the Boot Block at the top of the memory address space and the Bottom Boot Block version locates the Boot Block starting at the bottom.
The memory maps and block address tables are
showed in Figures 4, 5 and Tables 4, 5. Each
block can be erased separately, any combination
of blocks can be specified for multi-block erase or
the entire chip may be erased. The Erase operations are managed automatically by the P/E.C.
The block erase operation can be suspended in
order to read from or program to any block not being erased, and then resumed.
Device Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write
command, Output Disable, Standby and Reset
(see Table 6).
Read. Read operations are used to output the
contents of the Memory Array, the Electronic Signature or the Status Register. Both Chip Enable
(EF) and Output Enable (G) must be low, with
Write Enable (W) high, in order to read the output
of the memory.
Table 4. Top Boot Block, Flash Block Address
Table 5. Bottom Boot Block, Flash Block
Address
Size (KWord)
Address Range
16
FC000h-FFFFFh
Size (KWord)
8
FA000h-FBFFFh
64
F0000h-FFFFFh
8
F8000h-F9FFFh
64
E0000h-EFFFFh
32
F0000h-F7FFFh
64
D0000h-DFFFFh
E0000h-EFFFFh
64
C0000h-CFFFFh
64
D0000h-DFFFFh
64
B0000h-BFFFFh
64
C0000h-CFFFFh
64
A0000h-AFFFFh
64
B0000h-BFFFFh
64
90000h-9FFFFh
64
A0000h-AFFFFh
64
80000h-8FFFFh
64
90000h-9FFFFh
64
70000h-7FFFFh
64
80000h-8FFFFh
64
60000h-6FFFFh
70000h-7FFFFh
64
50000h-5FFFFh
64
60000h-6FFFFh
64
40000h-4FFFFh
64
50000h-5FFFFh
64
30000h-3FFFFh
64
40000h-4FFFFh
64
20000h-2FFFFh
64
30000h-3FFFFh
64
10000h-1FFFFh
64
20000h-2FFFFh
32
08000h-0FFFFh
64
10000h-1FFFFh
8
06000h-07FFFh
00000h-0FFFFh
8
04000h-05FFFh
16
00000h-03FFFh
64
64
64
6/35
Address Range
M36W108T, M36W108B
Instructions and Commands
Seven instructions are defined (see Table 7) to
perform Read Array, Auto Select (to read the Electronic Signature), Program, Block Erase, Chip
Erase, Erase Suspend and Erase Resume. The
internal P/E.C. automatically handles all timing
and verification of the Program and Erase operations. The Status Register Data Polling, Toggle,
Error bits and the RB output may be read at any
time, during programming or erase, to monitor the
progress of the operation.
Instructions, made up of commands written in cycles, can be given to the Program/Erase Controller
through a Command Interface (C.I.).
The C.I. latches commands written to the memory.
Commands are made of address and data sequences. Two coded cycles unlock the Command
Interface. They are followed by an input command
or a confirmation command. The coded sequence
consists of writing the data AAh at the address
5555h during the first cycle and the data 55h at the
address 2AAAh during the second cycle.
Write. Write operations are used to give Instruction Commands to the memory or to latch input
data to be programmed. A write operation is initiated when Chip Enable (EF) is Low and Write Enable (W) is at VIL with Output Enable (G) at VIH.
Addresses are latched on the falling edge of W or
EF whichever occurs last. Commands and Input
Data are latched on the rising edge of W or EF
whichever occurs first.
Output Disable. The data outputs are high impedance when the Output Enable (G) is at VIH with
Write Enable (W) at VIH.
Standby. The memory is in standby when Chip
Enable (EF) is at V IH and the P/E.C. is idle. The
power consumption is reduced to the standby level
and the outputs are high impedance, independent
of the Output Enable (G) or Write Enable (W) inputs.
Automatic Standby. After 150ns of bus inactivity
and when CMOS levels are driving the addresses,
the chip automatically enters a pseudo-standby
mode where consumption is reduced to the CMOS
standby value, while outputs still drive the bus.
Table 6. Flash User Bus Operations (1)
Operation
EF
G
W
RP
A0
A1
A6
A9
A12
A15
DQ0-DQ7
Read Byte
VIL
VIL
VIH
VIH
A0
A1
A6
A9
A12
A15
Data Output
Write Byte
VIL
VIH
VIL
VIH
A0
A1
A6
A9
A12
A15
Data Input
Output Disable
VIL
VIH
VIH
VIH
X
X
X
X
X
X
Hi-Z
Stand-by
VIH
X
X
VIH
X
X
X
X
X
X
Hi-Z
X
X
X
VIL
X
X
X
X
X
X
Hi-Z
Reset
Note: 1. X = VIL or VIH.
Table 7. Read Flash Electronic Signature
Code
EF
G
W
A0
A1
Other
Addresses
DQ0-DQ7
VIL
VIL
VIH
VIL
VIL
Don’t care
20h
M36W108T
VIL
VIL
VIH
VIH
VIL
Don’t care
D2h
M36W108B
VIL
VIL
VIH
VIH
VIL
Don’t care
DCh
Device
Manufact. Code
Device Code
7/35
M36W108T, M36W108B
Table 8. Flash Commands
Hex Code
Command
00h
Invalid/Reserved
10h
Chip Erase Confirm
20h
Reserved
30h
Block Erase Resume/Confirm
80h
Set-up Erase
90h
Read Electronic Signature/
Block Protection Status
A0h
Program
B0h
Erase Suspend
F0h
Read Array/Reset
Instructions are composed of up to six cycles. The
first two cycles input a Coded Sequence to the
Command Interface which is common to all instructions (see Table 9). The third cycle inputs the
instruction set-up command. Subsequent cycles
output the addressed data or Electronic Signature
for Read operations. In order to give additional
data protection, the instructions for Program and
Block or Chip Erase require further command inputs. For a Program instruction, the fourth command cycle inputs the address and data to be
programmed. For an Erase instruction (block or
chip), the fourth and fifth cycles input a further
Coded Sequence before the Erase confirm command on the sixth cycle. Erasure of a memory
block may be suspended, in order to read data
from another block or to program data in another
block, and then resumed.
When power is first applied or if V CCF falls below
VLKO, the command interface is reset to Read Array.
8/35
Command sequencing must be followed exactly.
Any invalid combination of commands will reset
the device to Read Array. The increased number
of cycles has been chosen to assure maximum
data security.
Read/Reset (RD) Instruction. The Read/Reset
instruction consists of one write cycle giving the
command F0h. It can be optionally preceded by
the two Coded cycles. Subsequent read operations will read the memory array addressed and
output the data read. A wait state of tPLYH is necessary after Read/Reset prior to any valid read if
the memory was in an Erase or Program mode
when the RD instruction is given (see Table 17
and Figure 9).
Auto Select (AS) Instruction. This instruction
uses the two Coded cycles followed by one write
cycle giving the command 90h to address 5555h
for command set-up. A subsequent read will output the Manufacturer Code or the Device Code
(Electronic Signature) depending on the levels of
A0 and A1 (see Table 7). The Electronic Signature
can be read from the memory allowing programming equipment or applications to automatically
match their interface to the characteristics of the
Flash memory. The Manufacturer Code, 20h, is
output when the addresses lines A0 and A1 are at
VIL, the Device Code is output when A0 is at VIH
with A1 at VIL. Other address inputs are ignored.
Program (PG) Instruction. This instruction uses
four write cycles. The Program command A0h is
written to address 5555h on the third cycle after
two Coded Cycles. A fourth write operation latches the Address and the Data to be written and
starts the P/E.C. Read operations output the Status Register bits after the programming has started. Memory programming is made only by writing
’0’ in place of ’1’. Status bits DQ6 and DQ7 determine if programming is on-going and DQ5 allows
verification of any possible error. Programming at
an address not in blocks being erased is also possible during erase suspend. In this case, DQ2 will
toggle at the address being programmed.
M36W108T, M36W108B
Block Erase (BE) Instruction. This instruction
uses a minimum of six write cycles. The Erase
Set-up command 80h is written to address 5555h
on third cycle after the two Coded cycles. The
Block Erase Confirm command 30h is similarly
written on the sixth cycle after another two Coded
Cycles. During the input of the second command
an address within the block to be erased is given
and latched into the memory.
Additional block Erase Confirm commands and
block addresses can be written subsequently to
erase other blocks in parallel, without further Coded cycles. The erase will start after the erase timeout period (see Erase Timer Bit DQ3 description).
Thus, additional Erase Confirm commands for other blocks must be given within this delay. The input
of a new Erase Confirm command will restart the
timeout period. The status of the internal timer can
be monitored through the level of DQ3, if DQ3 is ’0’
the Block Erase Command has been given and
the timeout is running, if DQ3 is ’1’, the timeout has
expired and the P/E.C. is erasing the block(s). If
the second command given is not an erase confirm or if the Coded cycles are wrong, the instruction aborts, and the device is reset to Read Array.
It is not necessary to program the block with 00h
as the P/E.C. will do this automatically before to
erasing to FFh. Read operations after the sixth rising edge of W or EF output the Status Register
bits.
During the execution of the erase by the P/E.C.,
the memory only accepts the Erase Suspend (ES)
and Read/Reset (RD) instructions. A Read/Reset
command will definitively abort erasure and result
in invalid data in blocks being erased. A complete
state of the block erase operation is given by the
Status Register bits (see DQ2, DQ3, DQ5, DQ6
and DQ7 description).
Chip Erase (CE) Instruction. This
instruction
uses six write cycles. The Erase Set-up command
80h is written to address 5555h on the third cycle
after the two Coded Cycles. The Chip Erase Confirm command 10h is similarly written on the sixth
cycle after another two Coded Cycles. If the sec-
ond command given is not an erase confirm or if
the Coded Sequence is wrong, the instruction
aborts and the device is reset to Read Array. It is
not necessary to program the array with 00h first
as the P/E.C. will automatically do this before
erasing it to FFh. Read operations after the sixth
rising edge of W or EF output the Status Register
bits. A complete state of the chip erase operation
is given by the Status Register bits (see DQ2,
DQ3, DQ5, DQ6 and DQ7 description).
Erase Suspend (ES) Instruction. The
Block
Erase operation may be suspended by this instruction which consists of writing the command
B0h without any specific address. No Coded Cycles are required. It permits reading of data from
another block and programming in another block
while an erase operation is in progress. Erase suspend is accepted only during the Block Erase instruction execution. Writing this command during
the erase timeout period will, in addition to suspending the erase, terminate the timeout. The
Toggle bit DQ6 stops toggling when the P/E.C. is
suspended. The Toggle bits will stop toggling between 0.1µs and 15µs after the Erase Suspend
(ES) command has been written. The device will
then automatically be set to Read Memory Array
mode. When erase is suspended, a Read from
blocks being erased will output DQ2 toggling and
DQ6 at '1'. A Read from a block not being erased
returns valid data. During suspension the memory
will respond only to the Erase Resume (ER) and
the Program (PG) instructions. A Program operation can be initiated during Erase Suspend in one
of the blocks not being erased. It will result in both
DQ2 and DQ6 toggling when the data is being programmed. A Read/Reset command will definitively
abort erasure and result in invalid data in the
blocks being erased.
Erase Resume (ER) Instruction. If an Erase
Suspend instruction was previously executed, the
erase operation may be resumed by giving the
command 30h, at any address, and without any
Coded cycles.
9/35
M36W108T, M36W108B
Table 9. Flash Instructions (1)
Mne.
Instr.
Cyc.
1+
Read/Reset
RD (2,4) Memory
Array
1st Cyc. 2nd Cyc. 3rd Cyc. 4th Cyc. 5th Cyc. 6th Cyc.
Addr. (3,7)
Data
3+
Addr. (3,7)
Data
AS (4)
Auto Select
3+
Addr. (3,7)
Data
Addr. (3,7)
PG
Program
BE
Block Erase
6
Addr. (3,7)
Data
CE
Chip Erase
6
Addr. (3,7)
Data
Erase
ES (10) Suspend
1
Erase
Resume
1
ER
X
Read Memory Array until a new write cycle is initiated.
F0h
5555h
2AAAh
5555h
AAh
55h
F0h
5555h
2AAAh
5555h
AAh
55h
90h
5555h
2AAAh
5555h
AAh
55h
A0h
5555h
2AAAh
5555h
5555h
2AAAh
Block
Address
Additional
Block (8)
AAh
55h
80h
AAh
55h
30h
30h
5555h
2AAAh
5555h
5555h
2AAAh
5555h
AAh
55h
80h
AAh
55h
10h
4
Data
Addr. (3,7)
Data
Addr. (3,7)
Data
7th Cyc.
Read Memory Array until a new write cycle
is initiated.
Read Electronic Signature or Block
Protection Status until a new write cycle is
initiated. See Note 5 and 6.
Program
Address Read Data Polling or Toggle Bit
Program until Program completes.
Data
Note 9
X
B0h
X
30h
Read until Toggle stops, then read all the data needed from any
Block(s) not being erased then Resume Erase.
Read Data Polling or Toggle Bits until Erase completes or Erase
is suspended another time.
Note: 1. Commands not interpreted in this table will default to read array mode.
2. A wait of tPLYH is necessary after a Read/Reset command if the memory was in an Erase, Erase Suspend or Program mode before
starting any new operation (see Table 14 and Figure 7).
3. X = Don’t care.
4. The first cycles of the RD or AS instructions are followed by read operations. Any number of read cycles can occur after the command cycles.
5. Signature Address bits A0, A1, at VIL will output Manufacturer code (20h). Address bits A0 at VIH and A1, at VIL will output Device
code.
6. Block Protection Address: A0, at V IL, A1 at VIH and A13-A19 within the Block will output the Block Protection status.
7. For Coded cycles address inputs A15-A19 are don’t care.
8. Optional, additional Blocks addresses must be entered within the erase timeout delay after last write entry, timeout status can be
verified through DQ3 value (see Erase Timer Bit DQ3 description). When full command is entered, real Data Polling or Toggle bit
until Erase is completed or suspended.
9. Read Data Polling, Toggle bits or RB until Erase completes.
10. During Erase Suspend, Read and Data Program functions are allowed in blocks not being erased.
10/35
M36W108T, M36W108B
Table 10. Flash Status Register Bits (1)
DQ
7
Name
Logic Level
Definition
‘1’
Erase Complete or erase block
in Erase Suspend
‘0’
Erase On-going
DQ
Program Complete or data of
non erase block during Erase
Suspend
DQ
Program On-going
Data
Polling
‘-1-0-1-0-1-0-1-’
DQ
6
Toggle Bit
‘-1-1-1-1-1-1-1-’
5
4
3
2
Erase or Program On-going
Program Complete
Erase Complete or Erase
Suspend on currently
addressed block
Note
Indicates the P/E.C. status, check during
Program or Erase, and on completion before
checking bits DQ5 for Program or Erase
Success.
Successive reads output complementary
data on DQ6 while Programming or Erase
operations are on-going. DQ6 remains at
constant level when P/E.C. operations are
completed or Erase Suspend is
acknowledged.
‘1’
Program or Erase Error
‘0’
Program or Erase On-going
‘1’
Erase Timeout Period Expired
P/E.C. Erase operation has started. Only
possible command entry is Erase Suspend
(ES).
‘0’
Erase Timeout Period
On-going
An additional block to be erased in parallel
can be entered to the P/E.C.
Error Bit
This bit is set to ‘1’ in the case of
Programming or Erase failure.
Reserved
Erase
Time Bit
‘-1-0-1-0-1-0-1-’
Chip Erase, Erase or Erase
Suspend on the currently
addressed block.
Erase Error due to the
currently addressed block
(when DQ5 = ‘1’)
‘1’
Program on-going, Erase
on-going on another block or
Erase Complete
DQ
Erase Suspend read on non
Erase Suspend block
Toggle Bit
1
Reserved
0
Reserved
Indicates the erase status and allows to
identify the erased block.
Note: 1. Logic level ‘1’ is High, ‘0’ is Low. -0-1-0-0-0-1-1-1-0- represent bit value in successive Read operations.
11/35
M36W108T, M36W108B
Table 11. Flash Polling and Toggle Bits (1)
Mode
DQ7
DQ6
DQ2
DQ7
Toggle
1
Erase
0
Toggle
Note 1
Erase Suspend Read
(in Erase Suspend
block)
1
1
Toggle
Erase Suspend Read
(outside Erase Suspend
block)
DQ7
DQ6
DQ2
Erase Suspend Program
DQ7
Toggle
N/A
Program
Note: 1. Toggle if the address is within a block being erased.
‘1’ if the address is within a block not being erased.
Status Register Bits
P/E.C. status is indicated during execution by Data
Polling on DQ7, detection of Toggle on DQ6 and
DQ2, or Error on DQ5 and Erase Timer DQ3 bits.
Any read attempt during Program or Erase command execution will automatically output these
five Status Register bits. The P/E.C. automatically
sets bits DQ2, DQ3, DQ5, DQ6 and DQ7. Other
bits (DQ0, DQ1 and DQ4) are reserved for future
use and should be masked (see Table 10 and Table 11).
Data Polling Bit (DQ7). When Programming operations are in progress, this bit outputs the complement of the bit being programmed on DQ7.
During Erase operation, it outputs a ’0’. After completion of the operation, DQ7 will output the bit last
programmed or a ’1’ after erasing. Data Polling is
valid and only effective during P/E.C. operation,
that is after the fourth W pulse for programming or
after the sixth W pulse for erase. It must be performed at the address being programmed or at an
address within the block being erased. If all the
blocks selected for erasure are protected, DQ7 will
be set to '0' for about 100µs, and then return to the
previous addressed memory data value. See Figure 9 for the Data Polling flowchart and Figure 11
for the Data Polling waveforms. DQ7 will also flag
the Erase Suspend mode by switching from '0' to
'1' at the start of the Erase Suspend. In order to
monitor DQ7 in the Erase Suspend mode an address within a block being erased must be provided. For a Read Operation in Erase Suspend
mode, DQ7 will output '1' if the read is attempted
on a block being erased and the data value on oth-
12/35
er blocks. During Program operation in Erase Suspend Mode, DQ7 will have the same behaviour as
in the normal program execution outside of the
suspend mode.
Toggle Bit (DQ6). When Programming or Erasing operations are in progress, successive attempts to read DQ6 will output complementary
data. DQ6 will toggle following toggling of either G,
or EF when G is at VIL. The operation is completed when two successive reads yield the same output data. The next read will output the bit last
programmed or a '1' after erasing. The toggle bit
DQ6 is valid only during P/E.C. operations, that is
after the fourth W pulse for programming or after
the sixth W pulse for Erase. If the blocks selected
for erasure are protected, DQ6 will toggle for about
100µs and then return back to Read. DQ6 will be
set to '1' if a Read operation is attempted on an
Erase Suspend block. When erase is suspended
DQ6 will toggle during programming operations in
a block different to the block in Erase Suspend. Either EF or G toggling will cause DQ6 to toggle.
See Figure 11 for Toggle Bit flowchart and Figure
15 for Toggle Bit waveforms.
Toggle Bit (DQ2). This toggle bit, together with
DQ6, can be used to determine the device status
during the Erase operations. It can also be used to
identify the block being erased. During Erase or
Erase Suspend a read from a block being erased
will cause DQ2 to toggle. A read from a block not
being erased will set DQ2 to '1' during erase and
to DQ2 during Erase Suspend. During Chip Erase
a read operation will cause DQ2 to toggle as all
blocks are being erased. DQ2 will be set to '1' during program operation and when erase is complete. After erase completion and if the error bit
DQ5 is set to '1', DQ2 will toggle if the faulty block
is addressed.
Error Bit (DQ5). This bit is set to '1' by the P/E.C.
when there is a failure of programming, block
erase, or chip erase that results in invalid data in
the memory block. In case of an error in block
erase or program, the block in which the error occurred or to which the programmed data belongs,
must be discarded. The DQ5 failure condition will
also appear if a user tries to program a '1' to a location that is previously programmed to '0'. Other
Blocks may still be used. The error bit resets after
a Read/Reset (RD) instruction. In case of success
of Program or Erase, the error bit will be set to '0'.
Erase Timer Bit (DQ3). This bit is set to '0' by the
P/E.C. when the last block Erase command has
been entered to the Command Interface and it is
awaiting the Erase start. When the erase timeout
period is finished, after 50µs to 90µs, DQ3 returns
to '1'.
M36W108T, M36W108B
Table 12. Flash Program/Erase Times and Endurance
(TA = 0 to 70 °C; VCC = 2.7 V to 3.6 V)
Flash Memory Chip
Parameter
Unit
Typ
Typical after
100k W/E Cycles
Chip Erase (Preprogrammed)
5
3.3
Chip Erase
12
sec
Boot Block Erase
2.4
sec
Parameter Block Erase
2.3
sec
Main Block (32Kb) Erase
2.7
sec
Main Block (64Kb) Erase
3.3
Min
Max
sec
15
sec
Chip Program (Byte)
8
8
sec
Byte Program
10
10
µs
Program/Erase Cycles (per Block)
100,000
cycles
13/35
M36W108T, M36W108B
occurring edge. The Write cycle can be terminated
by the rising edge of E1S, the rising edge of W or
the falling edge of E2S, whichever occurs first.
If the Output is enabled (E1S=VIL, E2S=VIH and
G=VIL), then W will return the outputs to high impedance within tWLQZ of its falling edge. Care must
be taken to avoid bus contention in this type of operation. Data input must be valid for tDVWH before
the rising edge of Write Enable, or for tDVE1H before the rising edge of E1S or for tDVE2L before the
falling edge of E2S, whichever occurs first, and remain valid for tWHDX, tE1HDX or tE2LDX (see Table
22, Figures 17, 18, 19).
Output Disable. The data outputs are high impedance when the Output Enable (G) is at VIH with
Write Enable (W) at VIH.
Power-Down. The SRAM chip has a Chip Enable
power-down feature which invokes an automatic
standby mode (see Table 21, Figure 16) whenever
either Chip Enable is de-asserted (E1S=V IH or
E2S=VIL).
Data Retention
The SRAM data retention performances as VCCS
go down to V DR are described in Table 23 and Figures 22, 23. In E1S controlled data retention
mode, minimum standby current mode is entered
when E1S ≥ VCCS – 0.2V and E2S ≤ 0.2V or
E2S ≥ VCCS – 0.2V. In E2S controlled data retention mode, minimum standby current mode is entered when E2S ≤ 0.2V.
SRAM COMPONENT
Device Operations
The following operations can be performed using
the appropriate bus cycles: Read Array, Write Array, Output Disable, Power Down (see Table 13).
Read. Read operations are used to output the
contents of the SRAM Array. The SRAM is in Read
mode whenever Write Enable (W) is at VIH with
Output Enable (G) at V IL, and both Chip Enables
(E1S and E2S) are asserted.
Valid data will be available at the eight output pins
within t AVQV after the last stable address, providing G is Low, E1S is Low and E2S is High. If Chip
Enable or Output Enable access times are not
met, data access will be measured from the limiting parameter (tE1LQV, t E2HQV, or t GLQV) rather
than the address. Data out may be indeterminate
at tE1LQX, tE2HQX and tGLQX, but data lines will always be valid at t AVQV (see Table 21, Figure 14,
Figure 15).
Write. Write operations are used to write data in
the SRAM. The SRAM is in Write mode whenever
the W and E1S pins are at VIL, with E2S at VIH. Either the Chip Enable inputs (E1S and E2S) or the
Write Enable input (W) must be de-asserted during address transitions for subsequent write cycles. Write begins with the concurrence of both
Chip Enables being active with W at VIL. A Write
begins at the latest transition among E1S going to
VIL, E2S going to VIH and W going to VIL. Therefore, address setup time is referenced to Write Enable and both Chip Enables as tAVWL, t AVE1L and
tAVE2H respectively, and is determined by the latter
Table 13. SRAM User Bus Operations (1)
Operation
E1S
E2S
W
G
DQ0-DQ7
Power
Read
VIL
VIH
VIH
VIL
Data Output
Active
Write
VIL
VIH
VIL
X
Data Input
Active
Output Disable
VIL
VIH
VIH
VIH
Hi-Z
Active
VIH
X
X
X
Hi-Z
Stand-by TTL
X
VIL
X
X
Hi-Z
Stand-by TTL/CMOS
Power Down
Note: 1. X = VIL or VIH.
14/35
M36W108T, M36W108B
Table 14. DC Characteristics
(TA = 0 to 70°C, –20 to 85°C, –40 to 85°C; VCCF = VCCS = 2.7V to 3.6V)
Symbol
Parameter
ILI
Input Leakage Current
ILO
Output Leakage Current
Test Condition
Min
Max
Unit
0V ≤ VIN ≤ VCCF / VCCS
–1
1
µA
0V ≤ VOUT ≤ VCCF / VCCS
–1
1
µA
ICCF1
Flash Chip Supply Current (Read)
EF = VIL, G = VIH, f = 6MHz,
V ≤ VOUT ≤ VCCF
10
mA
ICCF2 (1)
Flash Chip Supply Current (Write)
Program or Erase in progress
20
µA
EF = VCCF ± 0.2V
100
µA
E1S = VIL, E2S = VIH, f= 10MHz
40
mA
E1S = VIL, E2S = VIH, f= 1MHz
10
mA
ICCF3
Flash Chip Supply Current (Stand-by)
ICCS1
SRAM Chip Supply Current (Read)
ICCS2 (1)
SRAM Chip Supply Current (Write)
20
mA
SRAM Chip Supply Current (Stand-by)
20
µA
ICCS3
VILF
Flash Chip Input Low Voltage
–0.5
0.8
V
VIHF
Flash Chip Input High Voltage
0.7 VCCF
VCCF + 0.3
V
VILS
SRAM Chip Input Low Voltage
–0.3
0.4
V
VIHS
SRAM Chip Input High Voltage
2.2
VCCS + 0.3
V
VOLF
Flash Chip Output Low Voltage
IOL = 1.8mA
0.45
V
VOHF
Flash Chip Output High Voltage
IOH = –100µA
VOLS
SRAM Chip Output Low Voltage
IOL = 2.1mA
VOHS
SRAM Chip Output High Voltage
IOH = –1.0mA
VCCF – 0.4
V
0.4
V
2.2
V
Note: 1. Sampled only, not 100% tested.
Table 15. Capacitance (1)
(TA = 25 °C, f = 1 MHz)
Symbol
CIN
COUT
Parameter
Test Condition
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
Input Capacitance
Output Capacitance
Min
Note: 1. Sampled only, not 100% tested.
Table 16. AC Measurement Conditions
Figure 5. AC Testing Load Circuit
Input Rise and Fall Times
≤ 10ns
Input Pulse Voltages
0 to 3V
Input and Output Timing Ref. Voltages
0.8V
1N914
1.5V
3.3kΩ
Figure 4. AC Testing Input/Output Waveforms
DEVICE
UNDER
TEST
3V
OUT
CL = 30pF or 100pF
1.5V
0V
AI01417
CL includes JIG capacitance
AI01968
15/35
M36W108T, M36W108B
Table 17. Flash Read AC Characteristics
(TA = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; VCCF = 2.7V to 3.6V)
Flash Memory Chip
Symbol
Alt
Parameter
100
120
CL = 30pF
CL = 100pF
Test Condition
Unit
Min
tAVAV
tRC
Address Valid to Next Address Valid
EF = VIL, G = VIL
tAVQV
tACC
Address Valid to Output Valid
EF = VIL, G = VIL
tELQX (1)
tLZ
Chip Enable Low to Output Transition
G = VIL
tELQV (2)
tCE
Chip Enable Low to Output Valid
G = VIL
tGLQX (1)
tOLZ
Output Enabled Low to Output
Transition
EF = VIL
tGLQV (2)
tOE
Output Enable Low to Output Valid
EF = VIL
tEHQX
tOH
Chip Enable High to Output Transition
G = VIL
tEHQZ (1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
tGHQX
tOH
Output Enable High to Output
Transition
EF = VIL
tGHQZ (1)
tDF
Output Enable High to Output Hi-Z
EF = VIL
tAXQX
tOH
Address Transition to Output Transition
EF = VIL, G = VIL
100
(1,3)
Min
Max
120
100
0
ns
120
0
100
0
0
0
0
0
0
0
ns
ns
30
0
10
ns
ns
30
30
ns
ns
50
30
ns
ns
120
40
tRRB
RP Low to Read Mode
tREADY
tPLYH
Max
ns
ns
10
µs
tPHEL
tRH
RP High to Chip Enable Low
50
50
ns
tPLPX
tRP
RP Pulse Width
500
500
ns
0
0
ns
tCCR (4)
Note: 1.
2.
3.
4.
16/35
Chip Enabled Recovery Time
Sampled only, not 100% tested.
G may be delayed by up to t ELQV - tGLQV after the falling edge of EF without increasing tELQV.
To be considered only if the Reset pulse is given while the memory is in Erase, Erase Suspend or Program Mode.
See Flash-SRAM Switching Waveforms.
Note: Write Enable (W) = High.
DQ0-DQ7
G
EF
A0-A19
tAVQV
tGLQV
tGLQX
tELQX
tELQV
VALID
tAVAV
VALID
tGHQZ
tGHQX
tEHQX
tEHQZ
tAXQX
AI02511B
M36W108T, M36W108B
Figure 6. Flash Read Mode AC Waveforms
17/35
M36W108T, M36W108B
Table 18. Flash Write AC Characteristics, Write Enable Controlled
(TA = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; VCCF = 2.7V to 3.6V)
Flash Memory Chip
Symbol
Alt
100
120
CL = 30pF
CL = 100pF
Parameter
Unit
Min
tAVAV
tWC
Address Valid to Next Address Valid
tELWL
tCS
tWLWH
Max
Min
Max
100
120
ns
Chip Enable Low to Write Enable Low
0
0
ns
tWP
Write Enable Low to Write Enable High
50
50
ns
tDVWH
tDS
Input Valid to Write Enable High
50
50
ns
tWHDX
tDH
Write Enable High to Input Transition
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
50
50
ns
Output Enable High to Write Enable Low
0
0
ns
tGHWL
tVCHEL
tVCS
VCC High to Chip Enable Low
50
50
µs
tWHGL
tOEH
Write Enable High to Output Enable Low
0
0
ns
tPHPHH (1,2)
tVIDR
RP Rise Time to VID
500
500
ns
tPLPX
tRP
RP Pulse Width
500
500
ns
tWHRL (1)
tBUSY
Program Erase Valid to RB Delay
tPHWL (1)
tRSP
RP High to Write Enable Low
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
18/35
90
4
90
4
ns
µs
M36W108T, M36W108B
Figure 7. Flash Write AC Waveforms, W Controlled
tAVAV
A0-A19
VALID
tWLAX
tAVWL
tWHEH
EF
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7
tWHDX
VALID
VCCF
tVCHEL
RB
tWHRL
AI02512
Note: Address are latched on the falling edge of W, Data is latched on the rising edge of W.
19/35
M36W108T, M36W108B
Table 19. Flash Write AC Characteristics, Chip Enable Controlled
(TA = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; VCCF = 2.7V to 3.6V)
Flash Memory Chip
Symbol
Alt
100
120
CL = 30pF
CL = 100pF
Parameter
Unit
Min
tAVAV
tWC
Address Valid to Next Address Valid
tWLEL
tWS
tELEH
Max
Min
Max
100
120
ns
Write Enable Low to Chip Enable Low
0
0
ns
tCP
Chip Enable Low to Chip Enable High
50
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
50
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
30
20
ns
tAVEL
tAS
Address Valid to Chip Enable Low
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
50
50
ns
0
0
ns
50
50
µs
0
0
ns
tGHEL
Output Enable High Chip Enable Low
tVCHWL
tVCS
VCC High to Write Enable Low
tEHGL
tOEH
Chip Enable High to Output Enable Low
tPHPHH (1,2)
tVIDR
RP Rise Time to VID
500
500
ns
tPLPX
tRP
RP Pulse Width
500
500
ns
tEHRL (1)
tBUSY
Program Erase Valid to RB Delay
tPHWL (1)
tRSP
RP High to Write Enable Low
Note: 1. Sampled only, not 100% tested.
2. This timing is for Temporary Block Unprotection operation.
20/35
90
4
90
4
ns
µs
M36W108T, M36W108B
Figure 8. Flash Write AC Waveforms, EF Controlled
tAVAV
VALID
A0-A19
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
EF
tEHEL
tDVEH
DQ0-DQ7
tEHDX
VALID
VCCF
tVCHWL
RB
tEHRL
AI02513
Note: Address are latched on the falling edge of EF, Data is latched on the rising edge of EF.
Figure 9. Flash Read and Write AC Waveforms, RP Related
EF
tPHEL
W
tPHWL
RB
RP
tPLPX
tPHPHH
tPLYH
AI02514
21/35
M36W108T, M36W108B
Table 20. Flash Data Polling and Toggle Bits AC Characteristics (1)
(TA = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; VCCF = 2.7V to 3.6V)
Flash Memory Chip
Symbol
100
120
CL = 30pF
CL = 100pF
Parameter
Unit
Min
Max
Min
Max
Write Enable High to DQ7 Valid (Program, W Controlled)
10
2400
10
2400
ms
Write Enable High to DQ7 Valid (Chip Erase, W
Controlled)
1.0
60
1.0
60
sec
Chip Enable High to DQ7 Valid (Program, EF Controlled)
10
2400
10
2400
µs
tEHQ7V
Chip Enable High to DQ7 Valid (Chip Erase, EF
Controlled)
1.0
60
1.0
60
sec
tQ7VQV
Q7 Valid to Output Valid (Data Polling)
50
ns
tWHQ7V
tWHQV
tEHQV
Write Enable High to Output Valid (Program)
10
2400
10
2400
µs
Write Enable High to Output Valid (Chip Erase)
1.0
60
1.0
60
sec
Chip Enable High to Output Valid (Program)
10
2400
10
2400
µs
Chip Enable High to Output Valid (Chip Erase)
1.0
60
1.0
60
sec
Note: 1. All other timings are defined in Read AC Characteristics table.
22/35
40
DQ0-DQ6
DQ7
W
G
EF
A0-A19
LAST WRITE
CYCLE OF
PROGRAM
OR ERASE
INSTRUCTION
DATA POLLING
READ CYCLES
tWHQ7V
tEHQ7V
tELQV
tAVQV
tQ7VQV
IGNORE
DQ7
DATA POLLING (LAST) CYCLE
tGLQV
ADDRESS (WITHIN BLOCKS)
VALID
VALID
AI02515B
MEMORY
ARRAY
READ CYCLE
M36W108T, M36W108B
Figure 10. Flash Data Polling DQ7 AC Waveforms
23/35
24/35
DATA
TOGGLE
READ CYCLE
Note: All other timings are as a normal Read cycle.
LAST WRITE
CYCLE OF
PROGRAM
OF ERASE
INSTRUCTION
DQ0-DQ1,DQ3-DQ5,DQ7
DQ6,DQ2
W
G
EF
A0-A19
DATA TOGGLE
READ CYCLE
IGNORE
STOP TOGGLE
tWHQV
tEHQV
tAVQV
MEMORY ARRAY
READ CYCLE
VALID
VALID
tGLQV
tELQV
VALID
AI02516
M36W108T, M36W108B
Figure 11. Flash Data Toggle DQ6, DQ2 AC Waveforms
M36W108T, M36W108B
Figure 12. Flash Data Polling Flowchart
Figure 13. Flash Data Toggle Flowchart
START
START
READ
DQ2, DQ5 & DQ6
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
NO
NO
YES
NO
DQ5
=1
YES
READ DQ2, DQ6
YES
DQ2, DQ6
=
TOGGLE
NO
FAIL
DQ5
=1
YES
READ DQ7
DQ7
=
DATA
NO
DQ2, DQ6
=
TOGGLE
YES
NO
YES
PASS
FAIL
PASS
AI01369
AI01873
25/35
M36W108T, M36W108B
Table 21. SRAM Read AC Characteristics
(TA = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; VCCS = 2.7 V to 3.6 V)
SRAM Chip
100
Symbol
Parameter
Unit
CL = 100pF
Min
Max
tAVAV
Read Cycle Time
tAVQV
Address Valid to Output Valid
100
ns
tE1LQV
Chip Enable 1 Low to Output Valid
100
ns
tE2HQV
Chip Enable 2 High to Output Valid
100
ns
tGLQV
Output Enable Low to Output Valid
50
ns
tE1LQX
Chip Enable 1 Low to Output Transition
10
ns
tE2HQX
Chip Enable 2 High to Output Transition
10
ns
tGLQX
Output Enable Low to Output Transition
5
ns
tE1HQZ
Chip Enable 1 High to Output Hi-Z
0
30
ns
tE2LQZ
Chip Enable 2 Low to Output Hi-Z
0
30
ns
tGHQZ
Output Enable High to Output Hi-Z
0
30
ns
tAXQX
Address Transition to Output Transition
15
ns
tPU (1)
Chip Enable 1 Low or Chip Enable 2 High to Power Up
0
ns
tPD (1)
Chip Enable 1 High or Chip Enable 2 Low to Power Down
tCCR (2)
100
Chip Enable Recovery Time
ns
100
0
ns
Note: 1. Sampled only. Not 100% tested.
2. See Flash-SRAM Switching Waveforms.
Figure 14. SRAM Read Mode AC Waveforms, Address Controlled
tAVAV
A0-A16
VALID
tAVQV
tAXQX
DQ0-DQ7
DATA VALID
DATA VALID
AI02436
Note: E1S = Low, E2S = High, G = Low, W = High.
26/35
ns
M36W108T, M36W108B
Figure 15. SRAM Read AC Waveforms, E1S, E2S or G Controlled
tAVAV
VALID
A0-A16
tAVQV
tAXQX
tE1LQV
tE1HQZ
E1S
tE1LQX
tE2HQV
tE2LQZ
E2S
tE2HQX
tGLQV
tGHQZ
G
tGLQX
DQ0-DQ7
DATA VALID
AI02435
Note: Write Enable (W) = High.
Figure 16. SRAM Stand-by AC Waveforms
E1S
E2S
ICC4
ICC5
tPU
tPD
50%
AI02517
27/35
M36W108T, M36W108B
Table 22. SRAM Write AC Characteristics
(TA = 0 to 70 °C, –20 to 85 °C or –40 to 85 °C; VCCS = 2.7 V to 3.6 V)
SRAM Chip
100
Symbol
Parameter
Unit
CL = 100pF
Min
tAVAV
Write Cycle Time
tAVWL
Max
100
ns
Address Valid to Write Enable Low
0
ns
tAVWH
Address Valid to Write Enable High
80
ns
tWLWH
Write Enable Pulse Width
70
ns
tWHAX
Write Enable High to Address Transition
0
ns
tWHDX
Write Enable High to Input Transition
0
ns
tWHQX
Write Enable High to Output Transition
0
ns
tWLQZ
Write Enable Low to Output Hi-Z
0
tAVE1L
Address Valid to Chip Enable 1 Low
0
ns
tAVE2H
Address Valid to Chip Enable 2 High
0
ns
tE1HAX
Chip Enable 1 High to Address Transition
0
ns
tE2LAX
Chip Enable 2 Low to Address Transition
0
ns
tDVWH
Input Valid to Write Enable High
40
ns
tDVE1H
Input Valid to Chip Enable 1 High
40
ns
tDVE2L
Input Valid to Chip Enable 2 Low
40
ns
30
ns
Figure 17. SRAM Write AC Waveforms, W Controlled
tAVAV
VALID
A0-A16
tAVWH
tAVE1L
tWHAX
E1S
tAVE2H
E2S
tAVWL
tWLWH
W
tWHQX
tWLQZ
tDVWH
DQ0-DQ7
tWHDX
INPUT VALID
AI02434
Note: Output Enable (G) = Low.
28/35
M36W108T, M36W108B
Figure 18. SRAM Write AC Waveforms, E1S Controlled
tAVAV
VALID
A0-A16
tAVE1L
tE1HAX
E1S
E2S
tAVWL
W
tDVE1H
tWHDX
INPUT VALID
DQ0-DQ7
AI02433
Note: Output Enable (G) = High.
Figure 19. SRAM Write AC Waveforms, E2S Controlled
tAVAV
VALID
A0-A16
E1S
tAVE2H
tE2LAX
E2S
tAVWL
W
tDVE2L
DQ0-DQ7
tWHDX
INPUT VALID
AI02432
Note: Output Enable (G) = High.
29/35
M36W108T, M36W108B
Table 23. SRAM Low VCC Data Retention Characteristics (1, 2)
(TA = 0 to 70 °C; VCCS = 2.7 V to 3.6 V)
Symbol
Parameter
Test Condition
ICCDR
Supply Current (Data Retention)
VCCS = 3V, E1S ≥ VCCS – 0.2V,
E2S ≥ VCCS – 0.2V or E2S ≤ 0.2V, f = 0
VDR
Supply Voltage (Data Retention)
E1S ≥ VCCS – 0.2V,E2S ≤ 0.2V, f = 0
2
tCDR
Chip Disable to Power Down
E1S ≥ VCCS – 0.2V,E2S ≤ 0.2V, f = 0
0
ns
5
ms
tR
Min
Operation Recovery Time
Max
Unit
20
µA
3.6
V
Note: 1. All other Inputs VIH ≤ VCC – 0.2V or VIL ≤ 0.2V.
2. Sampled only. Not 100% tested.
Figure 20. SRAM Low VCC Data Retention AC Waveforms, E1S Controlled
tCDR
DATA RETENTION MODE
tR
VCCS
2.7 V
2.2 V
VDR
E1S ≥ VCCS – 0.2V
E1S V
SS
AI02438
30/35
M36W108T, M36W108B
Figure 21. SRAM Low VCC Data Retention AC Waveforms, E2S Controlled
DATA RETENTION MODE
VCCS
2.7 V
E2S
tCDR
tR
VDR
0.4 V
E2S ≤ 0.2V
VSS
AI02437
Figure 22. Flash-SRAM Switching Waveforms
EF
tCCR
tCCR
E1S
E2S
AI02510
31/35
M36W108T, M36W108B
Table 24. Ordering Information Scheme
Example:
M36W108T
100 ZM
1
T
Product Family
M36 = MMP (Flash + SRAM)
Operating Voltage
W = 2.7V to 3.6V
SRAM Chip size & organization
1 = 1 Mbit (128Kb x8)
Flash Chip size & orgnization
08 = 8 Mbit (1Mb x8), Boot Block
Array Matrix
T = Top Boot
B = Bottom Boot
Speed
100 = 100 ns
120 = 120 ns
Package
ZM = LBGA48: 1mm pitch
ZN = LGA48: 1mm pitch
Temperature Range
1 = 0 to 70 °C
5 = –20 to 85 °C
6 = –40 to 85 °C
Option
T = Tape & Reel Packing
The M36W108T and M36W108B are replaced respectively by the new version M36W108AT and
M36W108AB.
For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the STMicroelectronics Sales Office nearest to you.
32/35
M36W108T, M36W108B
Table 25. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
1.250
1.150
1.350
0.049
0.045
0.053
A1
0.300
0.250
0.350
0.012
0.010
0.014
A2
0.950
–
–
0.037
–
–
b
0.400
0.350
0.450
0.016
0.014
0.018
ddd
0.150
0.006
D
10.000
9.800
10.200
0.394
0.386
0.402
D1
5.000
–
–
0.197
–
–
e
1.000
–
–
0.039
–
–
E
12.000
11.800
12.200
0.472
0.465
0.480
E1
7.000
–
–
0.276
–
–
SD
0.500
–
–
0.020
–
–
SE
0.500
–
–
0.020
–
–
Figure 23. LBGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline
D
D1
SD
BALL "A1"
E
SE
E1
ddd
e
b
A
A2
A1
BGA-Z01
Drawing is not to scale.
33/35
M36W108T, M36W108B
Table 26. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Mechanical Data
mm
inches
Symb
Typ
Min
Max
Typ
Min
Max
A
0.950
0.900
1.000
0.037
0.035
0.039
b
0.450
0.420
0.480
0.018
0.017
0.019
D
10.000
9.800
10.200
0.394
0.386
0.402
D1
5.000
–
–
0.197
–
–
D2
9.200
–
–
0.362
–
–
e
1.000
–
–
0.039
–
–
E
12.000
11.800
12.200
0.472
0.465
0.480
E1
7.000
–
–
0.276
–
–
E2
10.200
–
–
0.402
–
–
SD
0.500
–
–
0.020
–
–
SE
0.500
–
–
0.020
–
–
Figure 24. LGA48 - 6 x 8 balls, 1.0 mm pitch, Package Outline
D
D2
D1
SD
LAND "A1"
E E2
SE
E1
e
b
A
LGA-Z02
Drawing is not to scale.
34/35
M36W108T, M36W108B
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.
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35/35
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