REJ09B0145-0600
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
8
H8/3847R Group, H8/3847S Group,
H8/38347 Group, H8/38447 Group
Hardware Manual
Renesas 8-Bit Single-Chip Microcomputer
H8 Family/H8/300L Super Low Power Series
H8/3847R Group
H8/3847S Group
H8/3842R
H8/3843R
H8/3844R
H8/3845R
H8/3846R
H8/3847R
H8/3844S
H8/3845S
H8/3846S
H8/3847S
H8/38347 Group
H8/38447 Group
Rev. 6.00
Revision Date: Aug 04, 2006
H8/38342
H8/38343
H8/38344
H8/38345
H8/38346
H8/38347
H8/38442
H8/38443
H8/38444
H8/38445
H8/38446
H8/38447
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 6.00 Aug 04, 2006 page ii of xxxvi
Preface
The H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447 Group are a highperformance single-chip microcomputers that integrate peripheral functions necessary for system
configuration with an H8/300L CPU core.
The on-chip peripheral functions include ROM, RAM, six timers, 14-bit PWM, a serial
communication interface (SCI), an A/D converter, LCD controller/driver, and I/O ports, providing
an ideal configuration as a microcomputer for embedding in sophisticated control systems. PROM
(ZTAT™*1), Flash memory (F-ZTAT™*2) and mask ROM are available as on-chip ROM,
enabling users to respond quickly and flexibly to changing application specifications and the
demands of the transition from initial to full-fledged volume production.
Notes: 1. ZTAT is a trademark of Renesas Technology Corp.
2. F-ZTAT is a trademark of Renesas Technology Corp.
Intended Readership: This manual is intended for users undertaking the design of an application
system using the H8/3847R Group, H8/3847S Group, H8/38347 Group, and
H8/38447 Group. Readers using this manual require a basic knowledge of
electrical circuits, logic circuits, and microcomputers.
Purpose:
The purpose of this manual is to give users an understanding of the hardware
functions and electrical characteristics of the H8/3847R Group, H8/3847S
Group, H8/38347 Group, and H8/38447 Group. Details of execution
instructions can be found in the H8/300L Series Programming Manual,
which should be read in conjunction with the present manual.
Using this Manual:
• For an overall understanding of the H8/3847R Group, H8/3847S Group, H8/38347 Group,
H8/38447 Group’s functions
Follow the Table of Contents. This manual is broadly divided into sections on the CPU, system
control functions, peripheral functions, and electrical characteristics.
• For a detailed understanding of CPU functions
Refer to the separate publication H8/300L Series Programming Manual.
Note on bit notation:
Bits are shown in high-to-low order from left to right.
Rev. 6.00 Aug 04, 2006 page iii of xxxvi
Notes: The following limitations apply when using the on-chip emulator for program
development and debugging.
1. Pin P24 is reserved for use exclusively by the on-chip emulator and cannot be used for
other operations.
2. Pins P25, P26, and P27 cannot be used. In order to use these pins it is necessary to
install additional hardware on the user board.
3. The address area from H'E000 to H'EFFF is used by the on-chip emulator and therefore
cannot be accessed by the user.
4. The address area from H'F300 to H'F6FF must not be accessed under any
circumstances.
5. When the on-chip emulator is used, pin P24 functions as an I/O pin, pins P25 and P26
function as input pins, and pin P27 functions as an output pin.
6. During a break, the watchdog timer continues to operate. Therefore, an internal reset is
generated if an overflow occurs during the break.
Related Material:
The latest information is available at our Web Site. Please make sure that
you have the most up-to-date information available.
(http://www.renesas.com/)
User's Manuals on the H8/3847:
Manual Title
Document No.
H8/3847R Group, H8/3847S Group, H8/38347 Group, H8/38447 Group
Hardware Manual
This manual
H8/300L Series Programming Manual
REJ09B0214-0200
User's manuals for development tools:
Manual Title
Document No.
C/C++ Compiler, Assembler, Optimizing Linkage Editor User’s Manual
REJ10B0161-0100
H8S, H8/300 Series Simulator/Debugger User’s Manual
REJ10B0211-0200
High-Performance Embedded Workshop User’s Manual
ADE-702-201
H8S, H8/300 Series High-Performance Embedded Workshop,
High-Performance Debugging Interface User’s Manual
ADE-702-231
Rev. 6.00 Aug 04, 2006 page iv of xxxvi
Application Note:
Manual Title
Document No.
H8/300L Series Application Note
ADE-502-065
Rev. 6.00 Aug 04, 2006 page v of xxxvi
Rev. 6.00 Aug 04, 2006 page vi of xxxvi
Main Revisions for this Edition
Item
Page
Revision (See Manual for Details)
All
“Under development” indication deleted from H8/38447 Group
Preface
iv
Added
Notes:
6. During a break, the watchdog timer continues to operate.
Therefore, an internal reset is generated if an overflow occurs
during the break.
1.3.2 Pin Functions
33
Table amended
Table 1.6 Pin
Functions
8.3.1 Overview
Pin No.
213
Type
Symbol
FP-100B
TFP-100B
TFP-100G
System
control
TEST
14
FP-100A
I/O
Name and Functions
17
Intput
Test pin: This pin is reserved and
cannot be used. It should be
connected to VSS.
Description amended
Port 2 is an 8-bit I/O port. Figure 8.2 shows its pin configuration.
In the F-ZTAT version, the on-chip pull-up MOS for pin P24 is on
during the reset period. It turns off and normal operation resumes
after the reset is cleared. The pull-up MOS is controlled by
hardware; it cannot be manipulated by a user program. This
should be considered when making connections to external
circuitry. Note that the mask ROM and ZTAT versions do not have
this function.
8.3.4 Pin States
Table 8.7 Port 2 Pin
States
218
Table and notes amended
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P27 to P25
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
P24*1
Pull-up
MOS on
P24*2
Highimpedance
P23
P22/SO1
P21/SI1
P20/SCK1
Highimpedance
Notes: 1. Applies to the F-ZTAT version of the H8/38347 Group and H8/38447 Group.
2. Applies to H8/3847R Group and H8/3847S Group. Also applies to the mask ROM
version of the H8/38347 Group and H8/38447 Group.
Rev. 6.00 Aug 04, 2006 page vii of xxxvi
Item
Page
Revision (See Manual for Details)
8.15.1 The
Management of the
Un-Use Terminal
256
Description amended
•
If an unused pin is an output pin, handle it in one of the
following ways:
Set the output of the unused pin to high and pull it up to
VCC with an external resistor of approximately 100 kΩ.
Set the output of the unused pin to low and pull it down to
Vss with an external resistor of approximately 100 kΩ.
15.8.2 DC
Characteristics
519,
525
Table 15.26 DC
Characteristics
Table and notes amended
Item
Symbol
Applicable Pins
Pull-up
MOS
current
–Ip
P10 to P17,
P24*6,
P30 to P37,
P50 to P57,
P60 to P67
Notes:
4. Except current which flows to the pull-up MOS or output buffer
5. Voltage maintained in standby mode
6. Applies to the F-ZTAT version. The specified values for this pin
in reference values.
C.2 Block Diagrams
of Port 2
634
Figure title amended
Figure C.2 (a-1)
Port 2 Block Diagram
(Pins P27 to P23, Not
Including P24 in the FZTAT Version of the
H8/38347 Group and
H8/38447 Group)
Figure C.2 (a-2)
635
Port 2 Block Diagram
(Pin P24 in the F-ZTAT
Version of the
H8/38347 Group and
H8/38447 Group)
Newly added
Rev. 6.00 Aug 04, 2006 page viii of xxxvi
Item
Page
Appendix D Port
660
States in the Different
Processing States
Table D.1 Port States
Overview
Revision (See Manual for Details)
Table and notes amended
Port
Reset
P27 to P20 Highimpedance*3
Notes: 1. High level output when MOS pull-up is in on state.
2. Reset output from P32 pin only (H8/3847R Group and
H8/3847S Group).
3. On-chip pull-up MOS turns on for pin P24 only (F-ZTAT Version
of the H8/38347 Group and H8/38447 Group).
Rev. 6.00 Aug 04, 2006 page ix of xxxvi
Rev. 6.00 Aug 04, 2006 page x of xxxvi
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
1
Overview........................................................................................................................... 1
Internal Block Diagram..................................................................................................... 7
Pin Arrangement and Functions........................................................................................ 9
1.3.1 Pin Arrangement .................................................................................................. 9
1.3.2 Pin Functions ....................................................................................................... 32
Section 2 CPU ...................................................................................................................... 39
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Overview...........................................................................................................................
2.1.1 Features................................................................................................................
2.1.2 Address Space......................................................................................................
2.1.3 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
2.2.1 General Registers .................................................................................................
2.2.2 Control Registers .................................................................................................
2.2.3 Initial Register Values..........................................................................................
Data Formats .....................................................................................................................
2.3.1 Data Formats in General Registers ......................................................................
2.3.2 Memory Data Formats .........................................................................................
Addressing Modes.............................................................................................................
2.4.1 Addressing Modes ...............................................................................................
2.4.2 Effective Address Calculation..............................................................................
Instruction Set ...................................................................................................................
2.5.1 Data Transfer Instructions....................................................................................
2.5.2 Arithmetic Operations..........................................................................................
2.5.3 Logic Operations..................................................................................................
2.5.4 Shift Operations ...................................................................................................
2.5.5 Bit Manipulations.................................................................................................
2.5.6 Branching Instructions .........................................................................................
2.5.7 System Control Instructions.................................................................................
2.5.8 Block Data Transfer Instruction...........................................................................
Basic Operational Timing .................................................................................................
2.6.1 Access to On-Chip Memory (RAM, ROM).........................................................
2.6.2 Access to On-Chip Peripheral Modules...............................................................
CPU States ........................................................................................................................
2.7.1 Overview..............................................................................................................
2.7.2 Program Execution State......................................................................................
39
39
40
41
42
42
42
44
44
45
46
47
47
49
53
55
57
58
59
61
65
67
68
70
70
71
73
73
75
Rev. 6.00 Aug 04, 2006 page xi of xxxvi
2.8
2.9
2.7.3 Program Halt State...............................................................................................
2.7.4 Exception-Handling State ....................................................................................
Memory Map ....................................................................................................................
2.8.1 Memory Map .......................................................................................................
Application Notes .............................................................................................................
2.9.1 Notes on Data Access ..........................................................................................
2.9.2 Notes on Bit Manipulation...................................................................................
2.9.3 Notes on Use of the EEPMOV Instruction ..........................................................
75
75
76
76
83
83
85
92
Section 3 Exception Handling ......................................................................................... 93
3.1
3.2
3.3
3.4
Overview...........................................................................................................................
Reset..................................................................................................................................
3.2.1 Overview..............................................................................................................
3.2.2 Reset Sequence ....................................................................................................
3.2.3 Interrupt Immediately after Reset ........................................................................
Interrupts ...........................................................................................................................
3.3.1 Overview..............................................................................................................
3.3.2 Interrupt Control Registers...................................................................................
3.3.3 External Interrupts ...............................................................................................
3.3.4 Internal Interrupts.................................................................................................
3.3.5 Interrupt Operations .............................................................................................
3.3.6 Interrupt Response Time......................................................................................
Application Notes .............................................................................................................
3.4.1 Notes on Stack Area Use .....................................................................................
3.4.2 Notes on Rewriting Port Mode Registers.............................................................
3.4.3 Method for Clearing Interrupt Request Flags ......................................................
93
93
93
93
94
95
95
97
107
108
108
113
114
114
115
118
Section 4 Clock Pulse Generators ................................................................................... 119
4.1
4.2
4.3
4.4
4.5
Overview...........................................................................................................................
4.1.1 Block Diagram .....................................................................................................
4.1.2 System Clock and Subclock.................................................................................
System Clock Generator ...................................................................................................
Subclock Generator...........................................................................................................
Prescalers ..........................................................................................................................
Note on Oscillators............................................................................................................
4.5.1 Definition of Oscillation Stabilization Wait Time ...............................................
4.5.2 Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator
Element)...............................................................................................................
Rev. 6.00 Aug 04, 2006 page xii of xxxvi
119
119
119
120
122
125
126
127
129
Section 5 Power-Down Modes ........................................................................................ 131
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
Overview...........................................................................................................................
5.1.1 System Control Registers.....................................................................................
Sleep Mode .......................................................................................................................
5.2.1 Transition to Sleep Mode.....................................................................................
5.2.2 Clearing Sleep Mode............................................................................................
5.2.3 Clock Frequency in Sleep (Medium-Speed) Mode..............................................
Standby Mode ...................................................................................................................
5.3.1 Transition to Standby Mode.................................................................................
5.3.2 Clearing Standby Mode .......................................................................................
5.3.3 Oscillator Settling Time after Standby Mode is Cleared .....................................
5.3.4 Standby Mode Transition and Pin States .............................................................
5.3.5 Notes on External Input Signal Changes before/after Standby Mode..................
Watch Mode......................................................................................................................
5.4.1 Transition to Watch Mode ...................................................................................
5.4.2 Clearing Watch Mode ..........................................................................................
5.4.3 Oscillator Settling Time after Watch Mode is Cleared ........................................
5.4.4 Notes on External Input Signal Changes before/after Watch Mode ....................
Subsleep Mode..................................................................................................................
5.5.1 Transition to Subsleep Mode ...............................................................................
5.5.2 Clearing Subsleep Mode ......................................................................................
Subactive Mode ................................................................................................................
5.6.1 Transition to Subactive Mode ..............................................................................
5.6.2 Clearing Subactive Mode.....................................................................................
5.6.3 Operating Frequency in Subactive Mode.............................................................
Active (Medium-Speed) Mode .........................................................................................
5.7.1 Transition to Active (Medium-Speed) Mode .......................................................
5.7.2 Clearing Active (Medium-Speed) Mode..............................................................
5.7.3 Operating Frequency in Active (Medium-Speed) Mode......................................
Direct Transfer ..................................................................................................................
5.8.1 Overview of Direct Transfer ................................................................................
5.8.2 Direct Transition Times .......................................................................................
5.8.3 Notes on External Input Signal Changes before/after Direct Transition..............
Module Standby Mode......................................................................................................
5.9.1 Setting Module Standby Mode ............................................................................
5.9.2 Clearing Module Standby Mode ..........................................................................
5.9.3 Usage Note...........................................................................................................
131
134
138
138
139
139
140
140
140
140
141
142
144
144
144
144
144
145
145
145
146
146
146
146
147
147
147
147
148
148
149
151
152
152
152
154
Section 6 ROM ..................................................................................................................... 155
6.1
Overview........................................................................................................................... 155
Rev. 6.00 Aug 04, 2006 page xiii of xxxvi
6.1.1 Block Diagram .....................................................................................................
PROM Mode (H8/3847R).................................................................................................
6.2.1 Setting to PROM Mode .......................................................................................
6.2.2 Socket Adapter Pin Arrangement and Memory Map...........................................
6.3 Programming (H8/3847R) ................................................................................................
6.3.1 Writing and Verifying..........................................................................................
6.3.2 Programming Precautions ....................................................................................
6.4 Reliability of Programmed Data .......................................................................................
6.5 Flash Memory Overview...................................................................................................
6.5.1 Features................................................................................................................
6.5.2 Block Diagram .....................................................................................................
6.5.3 Block Configuration.............................................................................................
6.5.4 Register Configuration.........................................................................................
6.6 Descriptions of Registers of the Flash Memory................................................................
6.6.1 Flash Memory Control Register 1 (FLMCR1).....................................................
6.6.2 Flash Memory Control Register 2 (FLMCR2).....................................................
6.6.3 Erase Block Register (EBR) ................................................................................
6.6.4 Flash Memory Power Control Register (FLPWCR) ............................................
6.6.5 Flash Memory Enable Register (FENR) ..............................................................
6.7 On-Board Programming Modes ........................................................................................
6.7.1 Boot Mode ...........................................................................................................
6.7.2 Programming/Erasing in User Program Mode.....................................................
6.8 Flash Memory Programming/Erasing ...............................................................................
6.8.1 Program/Program-Verify .....................................................................................
6.8.2 Erase/Erase-Verify...............................................................................................
6.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................
6.9 Program/Erase Protection..................................................................................................
6.9.1 Hardware Protection ............................................................................................
6.9.2 Software Protection..............................................................................................
6.9.3 Error Protection....................................................................................................
6.10 Programmer Mode ............................................................................................................
6.10.1 Socket Adapter.....................................................................................................
6.10.2 Programmer Mode Commands ............................................................................
6.10.3 Memory Read Mode ............................................................................................
6.10.4 Auto-Program Mode ............................................................................................
6.10.5 Auto-Erase Mode .................................................................................................
6.10.6 Status Read Mode ................................................................................................
6.10.7 Status Polling .......................................................................................................
6.10.8 Programmer Mode Transition Time.....................................................................
6.10.9 Notes on Memory Programming..........................................................................
6.2
Rev. 6.00 Aug 04, 2006 page xiv of xxxvi
156
157
157
157
160
160
165
166
167
167
168
168
170
171
171
174
174
175
176
177
178
180
180
181
184
184
186
186
186
186
187
187
187
190
193
195
196
198
199
199
6.11 Power-Down States for Flash Memory............................................................................. 200
Section 7 RAM ..................................................................................................................... 201
7.1
Overview........................................................................................................................... 201
7.1.1 Block Diagram ..................................................................................................... 201
Section 8 I/O Ports .............................................................................................................. 203
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Overview...........................................................................................................................
Port 1.................................................................................................................................
8.2.1 Overview..............................................................................................................
8.2.2 Register Configuration and Description...............................................................
8.2.3 Pin Functions .......................................................................................................
8.2.4 Pin States..............................................................................................................
8.2.5 MOS Input Pull-Up..............................................................................................
Port 2.................................................................................................................................
8.3.1 Overview..............................................................................................................
8.3.2 Register Configuration and Description...............................................................
8.3.3 Pin Function .........................................................................................................
8.3.4 Pin States..............................................................................................................
Port 3.................................................................................................................................
8.4.1 Overview..............................................................................................................
8.4.2 Register Configuration and Description...............................................................
8.4.3 Pin Functions .......................................................................................................
8.4.4 Pin States..............................................................................................................
8.4.5 MOS Input Pull-Up..............................................................................................
Port 4.................................................................................................................................
8.5.1 Overview..............................................................................................................
8.5.2 Register Configuration and Description...............................................................
8.5.3 Pin Functions .......................................................................................................
8.5.4 Pin States..............................................................................................................
Port 5.................................................................................................................................
8.6.1 Overview..............................................................................................................
8.6.2 Register Configuration and Description...............................................................
8.6.3 Pin Functions .......................................................................................................
8.6.4 Pin States..............................................................................................................
8.6.5 MOS Input Pull-Up..............................................................................................
Port 6.................................................................................................................................
8.7.1 Overview..............................................................................................................
8.7.2 Register Configuration and Description...............................................................
8.7.3 Pin Functions .......................................................................................................
203
205
205
205
210
211
212
213
213
213
217
218
219
219
219
223
225
225
226
226
226
228
229
230
230
230
232
233
233
234
234
234
236
Rev. 6.00 Aug 04, 2006 page xv of xxxvi
8.8
8.9
8.10
8.11
8.12
8.13
8.14
8.15
8.7.4 Pin States..............................................................................................................
8.7.5 MOS Input Pull-Up..............................................................................................
Port 7.................................................................................................................................
8.8.1 Overview..............................................................................................................
8.8.2 Register Configuration and Description...............................................................
8.8.3 Pin Functions .......................................................................................................
8.8.4 Pin States..............................................................................................................
Port 8.................................................................................................................................
8.9.1 Overview..............................................................................................................
8.9.2 Register Configuration and Description...............................................................
8.9.3 Pin Functions .......................................................................................................
8.9.4 Pin States..............................................................................................................
Port 9.................................................................................................................................
8.10.1 Overview..............................................................................................................
8.10.2 Register Configuration and Description...............................................................
8.10.3 Pin Functions .......................................................................................................
8.10.4 Pin States..............................................................................................................
Port A................................................................................................................................
8.11.1 Overview..............................................................................................................
8.11.2 Register Configuration and Description...............................................................
8.11.3 Pin Functions .......................................................................................................
8.11.4 Pin States..............................................................................................................
Port B ................................................................................................................................
8.12.1 Overview..............................................................................................................
8.12.2 Register Configuration and Description...............................................................
Port C ................................................................................................................................
8.13.1 Overview..............................................................................................................
8.13.2 Register Configuration and Description...............................................................
Input/Output Data Inversion Function ..............................................................................
8.14.1 Overview..............................................................................................................
8.14.2 Register Configuration and Descriptions .............................................................
8.14.3 Note on Modification of Serial Port Control Register .........................................
Application Note ...............................................................................................................
8.15.1 The Management of the Un-Use Terminal ..........................................................
236
237
238
238
238
240
240
241
241
241
243
243
244
244
244
246
247
248
248
248
250
250
251
251
251
252
252
252
253
253
253
256
256
256
Section 9 Timers .................................................................................................................. 257
9.1
9.2
Overview...........................................................................................................................
Timer A.............................................................................................................................
9.2.1 Overview..............................................................................................................
9.2.2 Register Descriptions ...........................................................................................
Rev. 6.00 Aug 04, 2006 page xvi of xxxvi
257
258
258
260
9.3
9.4
9.5
9.6
9.7
9.2.3 Timer Operation...................................................................................................
9.2.4 Timer A Operation States ....................................................................................
9.2.5 Application Note..................................................................................................
Timer C .............................................................................................................................
9.3.1 Overview..............................................................................................................
9.3.2 Register Descriptions ...........................................................................................
9.3.3 Timer Operation...................................................................................................
9.3.4 Timer C Operation States.....................................................................................
9.3.5 Usage Note...........................................................................................................
Timer F..............................................................................................................................
9.4.1 Overview..............................................................................................................
9.4.2 Register Descriptions ...........................................................................................
9.4.3 CPU Interface.......................................................................................................
9.4.4 Operation .............................................................................................................
9.4.5 Application Notes ................................................................................................
Timer G.............................................................................................................................
9.5.1 Overview..............................................................................................................
9.5.2 Register Descriptions ...........................................................................................
9.5.3 Noise Canceler .....................................................................................................
9.5.4 Operation .............................................................................................................
9.5.5 Application Notes ................................................................................................
9.5.6 Timer G Application Example .............................................................................
Watchdog Timer ...............................................................................................................
9.6.1 Overview..............................................................................................................
9.6.2 Register Descriptions ...........................................................................................
9.6.3 Timer Operation...................................................................................................
9.6.4 Watchdog Timer Operation States .......................................................................
Asynchronous Event Counter (AEC) ................................................................................
9.7.1 Overview..............................................................................................................
9.7.2 Register Descriptions ...........................................................................................
9.7.3 Operation .............................................................................................................
9.7.4 Asynchronous Event Counter Operation Modes..................................................
9.7.5 Application Notes ................................................................................................
264
265
265
266
266
268
271
273
274
275
275
278
285
288
291
294
294
296
301
302
306
311
312
312
313
317
319
320
320
322
327
329
329
Section 10 Serial Communication Interface ................................................................ 331
10.1 Overview........................................................................................................................... 331
10.2 SCI1 .................................................................................................................................. 332
10.2.1 Overview.............................................................................................................. 332
10.2.2 Register Descriptions ........................................................................................... 334
10.2.3 Operation ............................................................................................................. 340
Rev. 6.00 Aug 04, 2006 page xvii of xxxvi
10.2.4 Operation in SSB Mode .......................................................................................
10.2.5 Interrupt Source ...................................................................................................
10.2.6 Application Notes ................................................................................................
10.3 SCI3 ..................................................................................................................................
10.3.1 Overview..............................................................................................................
10.3.2 Register Descriptions ...........................................................................................
10.3.3 Operation .............................................................................................................
10.3.4 Interrupts..............................................................................................................
10.3.5 Application Notes ................................................................................................
343
346
346
347
347
351
374
403
404
Section 11 14-Bit PWM.....................................................................................................
11.1 Overview...........................................................................................................................
11.1.1 Features................................................................................................................
11.1.2 Block Diagram .....................................................................................................
11.1.3 Pin Configuration.................................................................................................
11.1.4 Register Configuration.........................................................................................
11.2 Register Descriptions ........................................................................................................
11.2.1 PWM Control Register (PWCR)..........................................................................
11.2.2 PWM Data Registers U and L (PWDRU, PWDRL)............................................
11.2.3 Clock Stop Register 2 (CKSTPR2)......................................................................
11.3 Operation...........................................................................................................................
11.3.1 Operation .............................................................................................................
11.3.2 PWM Operation Modes .......................................................................................
409
409
409
410
410
411
411
411
413
414
415
415
416
Section 12 A/D Converter ................................................................................................. 417
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram .....................................................................................................
12.1.3 Pin Configuration.................................................................................................
12.1.4 Register Configuration.........................................................................................
12.2 Register Descriptions ........................................................................................................
12.2.1 A/D Result Registers (ADRRH, ADRRL)...........................................................
12.2.2 A/D Mode Register (AMR) .................................................................................
12.2.3 A/D Start Register (ADSR)..................................................................................
12.2.4 Clock Stop Register 1 (CKSTPR1)......................................................................
12.3 Operation...........................................................................................................................
12.3.1 A/D Conversion Operation ..................................................................................
12.3.2 Start of A/D Conversion by External Trigger Input.............................................
12.3.3 A/D Converter Operation Modes .........................................................................
12.4 Interrupts ...........................................................................................................................
Rev. 6.00 Aug 04, 2006 page xviii of xxxvi
417
417
418
419
419
420
420
420
422
423
424
424
424
425
425
12.5 Typical Use .......................................................................................................................
12.6 Application Notes .............................................................................................................
12.6.1 Application Notes ................................................................................................
12.6.2 Permissible Signal Source Impedance .................................................................
12.6.3 Influences on Absolute Precision.........................................................................
425
428
428
429
429
Section 13 LCD Controller/Driver .................................................................................
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Block Diagram .....................................................................................................
13.1.3 Pin Configuration.................................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions ........................................................................................................
13.2.1 LCD Port Control Register (LPCR).....................................................................
13.2.2 LCD Control Register (LCR)...............................................................................
13.2.3 LCD Control Register 2 (LCR2)..........................................................................
13.2.4 Clock Stop Register 2 (CKSTPR2)......................................................................
13.3 Operation...........................................................................................................................
13.3.1 Settings up to LCD Display .................................................................................
13.3.2 Relationship between LCD RAM and Display ....................................................
13.3.3 Luminance Adjustment Function (V0 Pin)...........................................................
13.3.4 Low-Power-Consumption LCD Drive System ....................................................
13.3.5 Operation in Power-Down Modes .......................................................................
13.3.6 Boosting the LCD Drive Power Supply...............................................................
13.3.7 Connection to HD66100 ......................................................................................
431
431
431
432
433
433
434
434
436
438
440
441
441
444
452
453
457
458
459
Section 14 Power Supply Circuit .................................................................................... 461
14.1
14.2
14.3
14.4
14.5
Overview...........................................................................................................................
When Using Internal Power Supply Step-Down Circuit...................................................
When Not Using Internal Power Supply Step-Down Circuit............................................
H8/3847S Group ...............................................................................................................
Notes on Switching from the H8/3847R to the H8/38347 or H8/38447 ...........................
461
461
462
462
462
Section 15 Electrical Characteristics.............................................................................. 463
15.1 H8/3847R Group Absolute Maximum Ratings (Regular Specifications) .........................
15.2 H8/3847R Electrical Characteristics (Regular Specifications) .........................................
15.2.1 Power Supply Voltage and Operating Range.......................................................
15.2.2 DC Characteristics ...............................................................................................
15.2.3 AC Characteristics ...............................................................................................
15.2.4 A/D Converter Characteristics .............................................................................
463
464
464
467
472
477
Rev. 6.00 Aug 04, 2006 page xix of xxxvi
15.2.5 LCD Characteristics.............................................................................................
15.3 H8/3847R Group Absolute Maximum Ratings (Wide-range Specification) ....................
15.4 H8/3847R Electrical Characteristics (Wide-range Specification).....................................
15.4.1 Power Supply Voltage and Operating Range.......................................................
15.4.2 DC Characteristics ...............................................................................................
15.4.3 AC Characteristics ...............................................................................................
15.4.4 A/D Converter Characteristics .............................................................................
15.4.5 LCD Characteristics.............................................................................................
15.5 H8/3847S Group Absolute Maximum Ratings .................................................................
15.6 H8/3847S Group Electrical Characteristics ......................................................................
15.6.1 Power Supply Voltage and Operating Range.......................................................
15.6.2 DC Characteristics ...............................................................................................
15.6.3 AC Characteristics ...............................................................................................
15.6.4 A/D Converter Characteristics .............................................................................
15.6.5 LCD Characteristics.............................................................................................
15.7 Absolute Maximum Ratings of H8/38347 Group and H8/38447 Group ..........................
15.8 Electrical Characteristics of H8/38347 Group and H8/38447 Group................................
15.8.1 Power Supply Voltage and Operating Ranges .....................................................
15.8.2 DC Characteristics ...............................................................................................
15.8.3 AC Characteristics ...............................................................................................
15.8.4 A/D Converter Characteristics .............................................................................
15.8.5 LCD Characteristics.............................................................................................
15.8.6 Flash Memory Characteristics..............................................................................
15.9 Operation Timing..............................................................................................................
15.10 Output Load Circuit ..........................................................................................................
15.11 Resonator ..........................................................................................................................
15.12 Usage Note........................................................................................................................
478
480
481
481
484
489
494
495
497
498
498
500
505
510
511
513
514
514
517
526
530
531
532
535
539
540
541
Appendix A CPU Instruction Set .................................................................................... 543
A.1
A.2
A.3
Instructions........................................................................................................................ 543
Operation Code Map......................................................................................................... 551
Number of Execution States.............................................................................................. 553
Appendix B Internal I/O Registers ................................................................................. 560
B.1
B.2
Addresses .......................................................................................................................... 560
Functions........................................................................................................................... 564
Appendix C I/O Port Block Diagrams........................................................................... 630
C.1
C.2
Block Diagrams of Port 1.................................................................................................. 630
Block Diagrams of Port 2.................................................................................................. 634
Rev. 6.00 Aug 04, 2006 page xx of xxxvi
C.3
C.4
C.5
C.6
C.7
C.8
C.9
C.10
C.11
C.12
Block Diagrams of Port 3..................................................................................................
Block Diagrams of Port 4..................................................................................................
Block Diagram of Port 5 ...................................................................................................
Block Diagram of Port 6 ...................................................................................................
Block Diagram of Port 7 ...................................................................................................
Block Diagrams of Port 8..................................................................................................
Block Diagram of Port 9 ...................................................................................................
Block Diagram of Port A ..................................................................................................
Block Diagram of Port B ..................................................................................................
Block Diagram of Port C ..................................................................................................
639
648
652
653
654
655
656
657
658
659
Appendix D Port States in the Different Processing States .................................... 660
Appendix E List of Product Codes ................................................................................ 661
Appendix F Package Dimensions .................................................................................. 668
Appendix G Specifications of Chip Form .................................................................... 672
Appendix H Form of Bonding Pads .............................................................................. 674
Appendix I
Specifications of Chip Tray ..................................................................... 677
Rev. 6.00 Aug 04, 2006 page xxi of xxxvi
Figures
Section 1 Overview
Figure 1.1 (1) Block Diagram (H8/3847R Group and H8/3847S Group) ................................
Figure 1.1 (2) Block Diagram (H8/38347 Group and H8/38447 Group) .................................
Figure 1.2
Pin Arrangement (FP-100B, TFP-100B and TFP-100G: Top View) ................
Figure 1.3
Pin Arrangement (FP-100A: Top View) ...........................................................
Figure 1.4
Bonding Pad Location Diagram of H8/3847R Group (Mask ROM Version)
(Top View) ........................................................................................................
Figure 1.5
Bonding Pad Location Diagram of H8/3847S Group (Mask ROM Version)
(Top View) ........................................................................................................
Figure 1.6
Bonding Pad Location Diagram of HCD64F38347 and HCD64F38447
(Top View) ........................................................................................................
Figure 1.7
Bonding Pad Location Diagram of H8/38347 Group (Mask ROM Version)
and H8/38447 Group (Mask ROM Version) (Top View)..................................
Section 2 CPU
Figure 2.1
CPU Registers ...................................................................................................
Figure 2.2
Stack Pointer......................................................................................................
Figure 2.3
Register Data Formats .......................................................................................
Figure 2.4
Memory Data Formats.......................................................................................
Figure 2.5
Data Transfer Instruction Codes........................................................................
Figure 2.6
Arithmetic, Logic, and Shift Instruction Codes .................................................
Figure 2.7
Bit Manipulation Instruction Codes...................................................................
Figure 2.8
Branching Instruction Codes .............................................................................
Figure 2.9
System Control Instruction Codes .....................................................................
Figure 2.10
Block Data Transfer Instruction Code ...............................................................
Figure 2.11
On-Chip Memory Access Cycle........................................................................
Figure 2.12
On-Chip Peripheral Module Access Cycle (2-State Access).............................
Figure 2.13
On-Chip Peripheral Module Access Cycle (3-State Access).............................
Figure 2.14
CPU Operation States........................................................................................
Figure 2.15
State Transitions ................................................................................................
Figure 2.16 (1) H8/3842R, H8/38342 and H8/38442 Memory Map ..........................................
Figure 2.16 (2) H8/3843R, H8/38343 and H8/38443 Memory Map ..........................................
Figure 2.16 (3) H8/3844R, H8/3844S, H8/38344 and H8/38444 Memory Map ........................
Figure 2.16 (4) H8/3845R, H8/3845S, H8/38345 and H8/38445 Memory Map ........................
Figure 2.16 (5) H8/3846R, H8/3846S, H8/38346 and H8/38446 Memory Map ........................
Figure 2.16 (6) H8/3847R, H8/3847S, H8/38347 and H8/38447 Memory Map ........................
Rev. 6.00 Aug 04, 2006 page xxii of xxxvi
7
8
10
11
12
17
22
27
41
42
45
46
56
60
63
66
68
69
70
71
72
74
75
77
78
79
80
81
82
Figure 2.17
Figure 2.18
Data Size and Number of States for Access to and from On-Chip Peripheral
Modules ............................................................................................................. 84
Timer Configuration Example........................................................................... 86
Section 3 Exception Handling
Figure 3.1
Reset Sequence ..................................................................................................
Figure 3.2
Block Diagram of Interrupt Controller ..............................................................
Figure 3.3
Flow Up to Interrupt Acceptance ......................................................................
Figure 3.4
Stack State after Completion of Interrupt Exception Handling .........................
Figure 3.5
Interrupt Sequence.............................................................................................
Figure 3.6
Operation when Odd Address is Set in SP ........................................................
Figure 3.7
Port Mode Register Setting and Interrupt Request Flag Clearing Procedure ....
Section 4 Clock Pulse Generators
Figure 4.1
Block Diagram of Clock Pulse Generators........................................................
Figure 4.2
Typical Connection to Crystal Oscillator ..........................................................
Figure 4.3
Typical Connection to Ceramic Oscillator ........................................................
Figure 4.4
Board Design of Oscillator Circuit ....................................................................
Figure 4.5
External Clock Input (Example) ........................................................................
Figure 4.6
Typical Connection to 32.768 kHz/38.4 kHz Crystal Oscillator (Subclock).....
Figure 4.7
Equivalent Circuit of 32.768 kHz/38.4 kHz Crystal Oscillator .........................
Figure 4.8
Pin Connection when not Using Subclock ........................................................
Figure 4.9 (a) Pin Connection when Inputting External Clock
(H8/38347R Group and H8/3847S Group)........................................................
Figure 4.9 (b) Pin Connection when Inputting External Clock
(H8/38347 Group and H8/38447 Group) ..........................................................
Figure 4.10
Example of Crystal and Ceramic Oscillator Element Arrangement ..................
Figure 4.11
Negative Resistance Measurement and Circuit Modification Suggestions .......
Figure 4.12
Oscillation Stabilization Wait Time ..................................................................
94
108
110
111
112
114
117
119
120
120
121
121
122
122
123
123
124
126
127
128
Section 5 Power-Down Modes
Figure 5.1
Mode Transition Diagram.................................................................................. 132
Figure 5.2
Standby Mode Transition and Pin States........................................................... 141
Figure 5.3
External Input Signal Capture when Signal Changes before/after
Standby Mode or Watch Mode.......................................................................... 143
Section 6 ROM
Figure 6.1
ROM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444)......... 156
Figure 6.2
Socket Adapter Pin Correspondence (with HN27C101) ................................... 158
Figure 6.3
H8/3847R Memory Map in PROM Mode......................................................... 159
Rev. 6.00 Aug 04, 2006 page xxiii of xxxvi
Figure 6.4
Figure 6.5
Figure 6.6
Figure 6.7
Figure 6.8
Figure 6.9
Figure 6.10
Figure 6.11
Figure 6.12
Figure 6.13
Figure 6.14
Figure 6.15
Figure 6.16
Figure 6.17
Figure 6.18
Figure 6.19
Figure 6.20
High-Speed, High-Reliability Programming Flow Chart ..................................
PROM Write/Verify Timing..............................................................................
Recommended Screening Procedure .................................................................
Block Diagram of Flash Memory ......................................................................
Flash Memory Block Configuration ..................................................................
Programming/Erasing Flowchart Example in User Program Mode ..................
Program/Program-Verify Flowchart..................................................................
Erase/Erase-Verify Flowchart ...........................................................................
Socket Adapter Pin Correspondence Diagram ..................................................
Timing Waveforms for Memory Read after Memory Write .............................
Timing Waveforms in Transition from Memory Read Mode to Another
Mode..................................................................................................................
CE and OE Enable State Read Timing Waveforms...........................................
CE and OE Clock System Read Timing Waveforms ........................................
Auto-Program Mode Timing Waveforms..........................................................
Auto-Erase Mode Timing Waveforms ..............................................................
Status Read Mode Timing Waveforms..............................................................
Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence...............................................................................
161
164
166
168
169
180
182
185
189
191
192
192
193
194
196
197
199
Section 7 RAM
Figure 7.1
RAM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444)......... 201
Section 8 I/O Ports
Figure 8.1
Port 1 Pin Configuration....................................................................................
Figure 8.2
Port 2 Pin Configuration....................................................................................
Figure 8.3
Port 3 Pin Configuration....................................................................................
Figure 8.4
Port 4 Pin Configuration....................................................................................
Figure 8.5
Port 5 Pin Configuration....................................................................................
Figure 8.6
Port 6 Pin Configuration....................................................................................
Figure 8.7
Port 7 Pin Configuration....................................................................................
Figure 8.8
Port 8 Pin Configuration....................................................................................
Figure 8.9
Port 9 Pin Configuration....................................................................................
Figure 8.10
Port A Pin Configuration ...................................................................................
Figure 8.11
Port B Pin Configuration ...................................................................................
Figure 8.12
Port C Pin Configuration ...................................................................................
Figure 8.13
Input/Output Data Inversion Function...............................................................
205
213
219
226
230
234
238
241
244
248
251
252
253
Section 9 Timers
Figure 9.1
Block Diagram of Timer A................................................................................ 259
Rev. 6.00 Aug 04, 2006 page xxiv of xxxvi
Figure 9.2
Figure 9.3
Figure 9.4
Figure 9.5
Figure 9.6
Figure 9.7
Figure 9.8
Figure 9.9
Figure 9.10
Figure 9.11
Figure 9.12
Figure 9.13
Figure 9.14
Figure 9.15
Figure 9.16
Figure 9.17
Figure 9.18
Figure 9.19
Figure 9.20
Figure 9.21
Block Diagram of Timer C ................................................................................
Block Diagram of Timer F ................................................................................
Write Access to TCR (CPU → TCF) ................................................................
Read Access to TCF (TCF → CPU)..................................................................
TMOFH/TMOFL Output Timing......................................................................
Clear Interrupt Request Flag when Interrupt Factor Generation Signal
is Valid ..............................................................................................................
Block Diagram of Timer G................................................................................
Noise Canceler Block Diagram .........................................................................
Noise Canceler Timing (Example) ....................................................................
Input Capture Input Timing (without Noise Cancellation Function).................
Input Capture Input Timing (with Noise Cancellation Function)......................
Timing of Input Capture by Input Capture Input...............................................
TCG Clear Timing.............................................................................................
Port Mode Register Manipulation and Interrupt Enable Flag Clearing
Procedure...........................................................................................................
Timer G Application Example...........................................................................
Block Diagram of Watchdog Timer ..................................................................
Typical Watchdog Timer Operations (Example)...............................................
Block Diagram of Asynchronous Event Counter ..............................................
Example of Software Processing when Using ECH and ECL as 16-Bit
Event Counter ....................................................................................................
Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters.............................................................................................................
Section 10 Serial Communication Interface
Figure 10.1
SCI1 Block Diagram .........................................................................................
Figure 10.2
Transfer Format .................................................................................................
Figure 10.3
Example of SSB Connections............................................................................
Figure 10.4
Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1) ..........................
Figure 10.5
HOLD TAIL and LATCH TAIL Output Waveforms .......................................
Figure 10.6
SCI3 Block Diagram .........................................................................................
Figure 10.7 (a) RDRF Setting and RXI Interrupt.......................................................................
Figure 10.7 (b) TDRE Setting and TXI Interrupt .......................................................................
Figure 10.7 (c) TEND Setting and TEI Interrupt .......................................................................
Figure 10.8
Data Format in Asynchronous Communication ................................................
Figure 10.9
Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-bit data, parity, 2 stop bits).......................................
Figure 10.10 Example of SCI3 Initialization Flowchart .........................................................
Figure 10.11 Example of Data Transmission Flowchart (Asynchronous Mode)....................
267
276
286
287
289
293
295
301
302
304
304
305
305
310
311
312
318
321
327
328
333
340
343
344
344
349
378
378
378
379
381
382
383
Rev. 6.00 Aug 04, 2006 page xxv of xxxvi
Figure 10.12
Figure 10.13
Figure 10.14
Figure 10.15
Figure 10.16
Figure 10.17
Figure 10.18
Figure 10.19
Figure 10.20
Figure 10.21
Figure 10.22
Figure 10.23
Figure 10.24
Figure 10.25
Figure 10.26
Figure 10.27
Example of Operation when Transmitting in Asynchronous Mode
(8-bit data, parity, 1 stop bit) .............................................................................
Example of Data Reception Flowchart (Asynchronous Mode) .........................
Example of Operation when Receiving in Asynchronous Mode
(8-bit data, parity, 1 stop bit) .............................................................................
Data Format in Synchronous Communication...................................................
Example of Data Transmission Flowchart (Synchronous Mode) ......................
Example of Operation when Transmitting in Synchronous Mode.....................
Example of Data Reception Flowchart (Synchronous Mode) ...........................
Example of Operation when Receiving in Synchronous Mode .........................
Example of Simultaneous Data Transmission/Reception Flowchart
(Synchronous Mode) .........................................................................................
Example of Inter-Processor Communication Using Multiprocessor Format
(Sending data H'AA to receiver A)....................................................................
Example of Multiprocessor Data Transmission Flowchart................................
Example of Operation when Transmitting Using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)..........................................................
Example of Multiprocessor Data Reception Flowchart.....................................
Example of Operation when Receiving Using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)..........................................................
Receive Data Sampling Timing in Asynchronous Mode...................................
Relation between RDR Read Timing and Data .................................................
384
385
388
389
391
392
393
394
395
397
398
399
400
402
406
407
Section 11 14-Bit PWM
Figure 11.1
Block Diagram of the 14 bit PWM.................................................................... 410
Figure 11.2
PWM Output Waveform.................................................................................... 416
Section 12 A/D Converter
Figure 12.1
Block Diagram of the A/D Converter................................................................
Figure 12.2
External Trigger Input Timing...........................................................................
Figure 12.3
Typical A/D Converter Operation Timing.........................................................
Figure 12.4
Flow Chart of Procedure for Using A/D Converter (Polling by Software) .......
Figure 12.5
Flow Chart of Procedure for Using A/D Converter (Interrupts Used)...............
Figure 12.6
Analog Input Circuit Example...........................................................................
418
424
426
427
428
429
Section 13 LCD Controller/Driver
Figure 13.1
Block Diagram of LCD Controller/Driver.........................................................
Figure 13.2
Example of A Waveform with 1/2 Duty and 1/2 Bias.......................................
Figure 13.3
Handling of LCD Drive Power Supply when Using 1/2 Duty...........................
Figure 13.4
Examples of LCD Power Supply Pin Connections............................................
432
439
441
442
Rev. 6.00 Aug 04, 2006 page xxvi of xxxvi
Figure 13.5
Figure 13.6
Figure 13.7
Figure 13.8
Figure 13.9
Figure 13.10
Figure 13.11
Figure 13.12
Figure 13.13
Figure 13.14
Figure 13.15
Figure 13.16
Figure 13.17
Figure 13.18
LCD RAM Map with Segments Not Externally Expanded (1/4 Duty) .............
LCD RAM Map with Segments Not Externally Expanded (1/3 Duty) .............
LCD RAM Map with Segments Not Externally Expanded (1/2 Duty) .............
LCD RAM Map with Segments Not Externally Expanded (Static Mode) ........
LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/4 duty) ...............................................
LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/3 duty) ...............................................
LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/2 duty) ...............................................
LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” static) ....................................................
LCD Drive Power Supply Unit..........................................................................
Example of Low-Power-Consumption LCD Drive Operation ..........................
Output Waveforms for Each Duty Cycle (A Waveform) ..................................
Output Waveforms for Each Duty Cycle (B Waveform) ..................................
Connection of External Split-Resistance ...........................................................
Connection to HD66100....................................................................................
444
445
446
447
448
449
450
451
452
454
455
456
458
460
Section 14 Power Supply Circuit
Figure 14.1
Power Supply Connection when Internal Step-Down Circuit is Used .............. 461
Figure 14.2
Power Supply Connection when Internal Step-Down Circuit is Not Used........ 462
Section 15 Electrical Characteristics
Figure 15.1
Clock Input Timing ...........................................................................................
Figure 15.2
RES Low Width ................................................................................................
Figure 15.3
Input Timing......................................................................................................
Figure 15.4
UD Pin Minimum Modulation Width Timing ...................................................
Figure 15.5
SCI1 Input/Output Timing.................................................................................
Figure 15.6
SCK3 Input Clock Timing.................................................................................
Figure 15.7
SCI3 Synchronous Mode Input/Output Timing.................................................
Figure 15.8
Segment Expansion Signal Timing....................................................................
Figure 15.9
Output Load Condition......................................................................................
Figure 15.10 Resonator Equivalent Circuit.............................................................................
Figure 15.11 Recommended Resonators.................................................................................
535
535
535
536
536
537
537
538
539
540
540
Appendix C I/O Port Block Diagrams
Figure C.1 (a) Port 1 Block Diagram (Pins P17 to P14) ............................................................ 630
Figure C.1 (b) Port 1 Block Diagram (Pin P13)......................................................................... 631
Figure C.1 (c) Port 1 Block Diagram (Pin P12, P11) ................................................................. 632
Rev. 6.00 Aug 04, 2006 page xxvii of xxxvi
Figure C.1 (d) Port 1 Block Diagram (Pin P10)......................................................................... 633
Figure C.2 (a-1) Port 2 Block Diagram (Pins P27 to P23, Not Including P24 in the F-ZTAT Version
of the H8/38347 Group and H8/38447 Group).................................................. 634
Figure C.2 (a-2) Port 2 Block Diagram (Pin P24 in the F-ZTAT Version of the H8/38347 Group
and H8/38447 Group)........................................................................................ 635
Figure C.2 (b) Port 2 Block Diagram (Pin P22)......................................................................... 636
Figure C.2 (c) Port 2 Block Diagram (Pin P21)......................................................................... 637
Figure C.2 (d) Port 2 Block Diagram (Pin P20)......................................................................... 638
Figure C.3 (a) Port 3 Block Diagram (Pin P37 to P36) .............................................................. 639
Figure C.3 (b) Port 3 Block Diagram (Pin P35)......................................................................... 640
Figure C.3 (c) Port 3 Block Diagram (Pin P34)......................................................................... 641
Figure C.3 (d) Port 3 Block Diagram (Pin P33)......................................................................... 642
Figure C.3 (e-1) Port 3 Block Diagram (Pin P32, H8/3847R Group and H8/3847S Group) ........ 643
Figure C.3 (e-2) Port 3 Block Diagram (Pin P32, H8/38347 Group and H8/38447 Group)......... 644
Figure C.3 (f-1) Port 3 Block Diagram (Pin P31, H8/3847R Group and H8/3847S Group))....... 645
Figure C.3 (f-2) Port 3 Block Diagram (Pin P31, H8/38347 Group and H8/38447 Group)......... 646
Figure C.3 (g) Port 3 Block Diagram (Pin P30)......................................................................... 647
Figure C.4 (a) Port 4 Block Diagram (Pin P43)......................................................................... 648
Figure C.4 (b) Port 4 Block Diagram (Pin P42)......................................................................... 649
Figure C.4 (c) Port 4 Block Diagram (Pin P41)......................................................................... 650
Figure C.4 (d) Port 4 Block Diagram (Pin P40)......................................................................... 651
Figure C.5
Port 5 Block Diagram ........................................................................................ 652
Figure C.6
Port 6 Block Diagram ........................................................................................ 653
Figure C.7
Port 7 Block Diagram ........................................................................................ 654
Figure C.8
Port 8 Block Diagram ........................................................................................ 655
Figure C.9
Port 9 Block Diagram ........................................................................................ 656
Figure C.10
Port A Block Diagram ....................................................................................... 657
Figure C.11
Port B Block Diagram ....................................................................................... 658
Figure C.12
Port C Block Diagram ....................................................................................... 659
Appendix F Package Dimensions
Figure F.1
FP-100A Package Dimensions ..........................................................................
Figure F.2
FP-100B Package Dimensions ..........................................................................
Figure F.3
TFP-100B Package Dimensions ........................................................................
Figure F.4
TFP-100G Package Dimensions........................................................................
668
669
670
671
Appendix G Specifications of Chip Form
Figure G.1
Chip Sectional Figure ........................................................................................ 672
Figure G.2
Chip Sectional Figure ........................................................................................ 672
Figure G.3
Chip Sectional Figure ........................................................................................ 673
Rev. 6.00 Aug 04, 2006 page xxviii of xxxvi
Figure G.4
Chip Sectional Figure ........................................................................................ 673
Appendix H Form of Bonding Pads
Figure H.1
Bonding Pad Form............................................................................................. 674
Figure H.2
Bonding Pad Form............................................................................................. 675
Figure H.3
Bonding Pad Form............................................................................................. 676
Appendix I Specifications of Chip Tray
Figure I.1
Specifications of Chip Tray...............................................................................
Figure I.2
Specifications of Chip Tray...............................................................................
Figure I.3
Specifications of Chip Tray...............................................................................
Figure I.4
Specifications of Chip Tray...............................................................................
677
678
679
680
Rev. 6.00 Aug 04, 2006 page xxix of xxxvi
Tables
Section 1 Overview
Table 1.1
Features .................................................................................................................. 2
Table 1.2
Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version) .................. 13
Table 1.3
Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version) .................. 18
Table 1.4
Bonding Pad Coordinates of HCD64F38347 and HCD64F38447......................... 23
Table 1.5
Bonding Pad Coordinates of H8/38347 Group (Mask ROM Version)
and H8/38447 Group (Mask ROM Version) .......................................................... 28
Table 1.6
Pin Functions.......................................................................................................... 32
Section 2 CPU
Table 2.1
Addressing Modes..................................................................................................
Table 2.2
Effective Address Calculation................................................................................
Table 2.3
Instruction Set ........................................................................................................
Table 2.4
Data Transfer Instructions ......................................................................................
Table 2.5
Arithmetic Instructions...........................................................................................
Table 2.6
Logic Operation Instructions..................................................................................
Table 2.7
Shift Instructions ....................................................................................................
Table 2.8
Bit-Manipulation Instructions ................................................................................
Table 2.9
Branching Instructions ...........................................................................................
Table 2.10 System Control Instructions ...................................................................................
Table 2.11 Block Data Transfer Instruction .............................................................................
Table 2.12 Registers with Shared Addresses............................................................................
Table 2.13 Registers with Write-Only Bits ..............................................................................
47
50
53
55
57
58
59
61
65
67
68
90
91
Section 3 Exception Handling
Table 3.1
Exception Handling Types and Priorities...............................................................
Table 3.2
Interrupt Sources and Their Priorities ....................................................................
Table 3.3
Interrupt Control Registers .....................................................................................
Table 3.4
Interrupt Wait States...............................................................................................
Table 3.5
Conditions Under which Interrupt Request Flag is Set to 1 ...................................
93
96
97
113
116
Section 5 Power-Down Modes
Table 5.1
Operating Modes ....................................................................................................
Table 5.2
Internal State in Each Operating Mode ..................................................................
Table 5.3
System Control Registers .......................................................................................
Table 5.4
Clock Frequency and Settling Time (Times are in ms) ..........................................
Table 5.5
Setting and Clearing Module Standby Mode by Clock Stop Register....................
131
133
134
141
153
Rev. 6.00 Aug 04, 2006 page xxx of xxxvi
Section 6 ROM
Table 6.1
Setting to PROM Mode.......................................................................................... 157
Table 6.2
Socket Adapter ....................................................................................................... 157
Table 6.3
Mode Selection in PROM Mode (H8/3847R)........................................................ 160
Table 6.4
DC Characteristics.................................................................................................. 162
Table 6.5
AC Characteristics.................................................................................................. 163
Table 6.6
Register Configuration ........................................................................................... 170
Table 6.7
Division of Blocks to Be Erased ............................................................................ 175
Table 6.8
Setting Programming Modes.................................................................................. 177
Table 6.9
Boot Mode Operation............................................................................................. 179
Table 6.10 Oscillating Frequencies (fOSC) for which Automatic Adjustment of LSI Bit Rate Is
Possible .................................................................................................................. 179
Table 6.11 Reprogram Data Computation Table...................................................................... 183
Table 6.12 Additional-Program Data Computation Table ....................................................... 183
Table 6.13 Programming Time................................................................................................. 183
Table 6.14 Command Sequence in Programmer Mode............................................................ 188
Table 6.15 AC Characteristics in Transition to Memory Read Mode ...................................... 190
Table 6.16 AC Characteristics in Transition from Memory Read Mode to Another Mode ..... 191
Table 6.17 AC Characteristics in Memory Read Mode ........................................................... 192
Table 6.18 AC Characteristics in Auto-Program Mode ........................................................... 194
Table 6.19 AC Characteristics in Auto-Erase Mode ................................................................ 195
Table 6.20 AC Characteristics in Status Read Mode ............................................................... 197
Table 6.21 Status Read Mode Return Codes............................................................................ 198
Table 6.22 Status Polling Output Truth Table.......................................................................... 198
Table 6.23 Stipulated Transition Times to Command Wait State ............................................ 199
Table 6.24 Flash Memory Operating States ............................................................................. 200
Section 8 I/O Ports
Table 8.1
Port Functions ........................................................................................................
Table 8.2
Port 1 Registers ......................................................................................................
Table 8.3
Port 1 Pin Functions ...............................................................................................
Table 8.4
Port 1 Pin States .....................................................................................................
Table 8.5
Port 2 Registers ......................................................................................................
Table 8.6
Port 2 Pin Functions ...............................................................................................
Table 8.7
Port 2 Pin States .....................................................................................................
Table 8.8
Port 3 Registers ......................................................................................................
Table 8.9
Port 3 Pin Functions ...............................................................................................
Table 8.10 Port 3 Pin States .....................................................................................................
Table 8.11 Port 4 Registers ......................................................................................................
Table 8.12 Port 4 Pin Functions ...............................................................................................
203
205
210
211
213
217
218
219
223
225
226
228
Rev. 6.00 Aug 04, 2006 page xxxi of xxxvi
Table 8.13
Table 8.14
Table 8.15
Table 8.16
Table 8.17
Table 8.18
Table 8.19
Table 8.20
Table 8.21
Table 8.22
Table 8.23
Table 8.24
Table 8.25
Table 8.26
Table 8.27
Table 8.28
Table 8.29
Table 8.30
Table 8.31
Table 8.32
Table 8.33
Table 8.34
Port 4 Pin States .....................................................................................................
Port 5 Registers ......................................................................................................
Port 5 Pin Functions ...............................................................................................
Port 5 Pin States .....................................................................................................
Port 6 Registers ......................................................................................................
Port 6 Pin Functions ...............................................................................................
Port 6 Pin States .....................................................................................................
Port 7 Registers ......................................................................................................
Port 7 Pin Functions ...............................................................................................
Port 7 Pin States .....................................................................................................
Port 8 Registers ......................................................................................................
Port 8 Pin Functions ...............................................................................................
Port 8 Pin States .....................................................................................................
Port 9 Registers ......................................................................................................
Port 9 Pin Functions ...............................................................................................
Port 9 Pin States .....................................................................................................
Port A Registers .....................................................................................................
Port A Pin Functions ..............................................................................................
Port A Pin States ....................................................................................................
Port B Register .......................................................................................................
Port C Register .......................................................................................................
Register Configuration ...........................................................................................
229
230
232
233
234
236
236
238
240
240
241
243
243
244
246
247
248
250
250
251
252
253
Section 9 Timers
Table 9.1
Timer Functions ..................................................................................................... 257
Table 9.2
Pin Configuration ................................................................................................... 259
Table 9.3
Timer A Registers .................................................................................................. 260
Table 9.4
Timer A Operation States....................................................................................... 265
Table 9.5
Pin Configuration ................................................................................................... 267
Table 9.6
Timer C Registers................................................................................................... 268
Table 9.7
Timer C Operation States ....................................................................................... 273
Table 9.8
Pin Configuration ................................................................................................... 277
Table 9.9
Timer F Registers ................................................................................................... 277
Table 9.10 Timer F Operation Modes ...................................................................................... 290
Table 9.11 Pin Configuration ................................................................................................... 296
Table 9.12 Timer G Registers .................................................................................................. 296
Table 9.13 Timer G Operation Modes ..................................................................................... 306
Table 9.14 Internal Clock Switching and TCG Operation ....................................................... 307
Table 9.15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin Switching,
and Conditions for Their Occurrence ..................................................................... 309
Rev. 6.00 Aug 04, 2006 page xxxii of xxxvi
Table 9.16
Table 9.17
Table 9.18
Table 9.19
Table 9.20
Table 9.21
Input Capture Input Signal Input Edges Due to Noise Canceler Function Switching,
and Conditions for Their Occurrence ..................................................................... 309
Watchdog Timer Registers ..................................................................................... 313
Watchdog Timer Operation States ......................................................................... 319
Pin Configuration ................................................................................................... 321
Asynchronous Event Counter Registers ................................................................. 322
Asynchronous Event Counter Operation Modes .................................................... 329
Section 10
Table 10.1
Table 10.2
Table 10.3
Table 10.4
Table 10.5
Table 10.6
Table 10.6
Table 10.7
Table 10.8
Table 10.9
Table 10.9
Table 10.10
Table 10.11
Table 10.12
Table 10.13
Table 10.14
Table 10.15
Table 10.16
Table 10.17
Serial Communication Interface
Overview of SCI Functions ....................................................................................
SCI1 Pin Configuration ..........................................................................................
Registers .................................................................................................................
Pin Configuration ...................................................................................................
Registers .................................................................................................................
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)........
Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)........
Relation between n and Clock................................................................................
Maximum Bit Rate for Each Frequency (Asynchronous Mode) ............................
Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1) ..........
Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2) ..........
Relation between n and Clock................................................................................
SMR Settings and Corresponding Data Transfer Formats .....................................
SMR and SCR3 Settings and Clock Source Selection ...........................................
Transmit/Receive Interrupts ...................................................................................
Data Transfer Formats (Asynchronous Mode) .......................................................
Receive Error Detection Conditions and Receive Data Processing........................
SCI3 Interrupt Requests .........................................................................................
SSR Status Flag States and Receive Data Transfer ................................................
331
334
334
350
350
365
366
366
367
368
369
370
375
376
377
380
387
403
404
Section 11 14-Bit PWM
Table 11.1 Pin Configuration ................................................................................................... 410
Table 11.2 Register Configuration ........................................................................................... 411
Table 11.3 PWM Operation Modes.......................................................................................... 416
Section 12 A/D Converter
Table 12.1 Pin Configuration ................................................................................................... 419
Table 12.2 Register Configuration ........................................................................................... 419
Table 12.3 A/D Converter Operation Modes ........................................................................... 425
Rev. 6.00 Aug 04, 2006 page xxxiii of xxxvi
Section 13 LCD Controller/Driver
Table 13.1 Pin Configuration ...................................................................................................
Table 13.2 LCD Controller/Driver Registers ...........................................................................
Table 13.3 Output Levels .........................................................................................................
Table 13.4 Power-Down Modes and Display Operation..........................................................
433
433
457
457
Section 15
Table 15.1
Table 15.2
Table 15.3
Table 15.4
Table 15.5
Table 15.6
Table 15.7
Table 15.8
Table 15.9
Table 15.10
Table 15.11
Table 15.12
Table 15.13
Table 15.14
Table 15.15
Table 15.16
Table 15.17
Table 15.18
Table 15.19
Table 15.20
Table 15.21
Table 15.22
Table 15.23
Table 15.24
Table 15.25
Table 15.26
Table 15.27
Table 15.28
Table 15.29
Table 15.30
Table 15.31
Table 15.32
463
467
472
475
476
477
478
479
480
484
489
492
493
494
495
496
497
500
505
508
509
510
511
512
513
517
526
528
529
530
531
532
Electrical Characteristics
Absolute Maximum Ratings...................................................................................
DC Characteristics..................................................................................................
Control Signal Timing............................................................................................
Serial Interface (SCI1) Timing...............................................................................
Serial Interface (SCI3-1, SCI3-2) Timing ..............................................................
A/D Converter Characteristics ...............................................................................
LCD Characteristics ...............................................................................................
Segment External Expansion AC Characteristics...................................................
Absolute Maximum Ratings...................................................................................
DC Characteristics..................................................................................................
Control Signal Timing............................................................................................
Serial Interface (SCI1) Timing...............................................................................
Serial Interface (SCI3-1, SCI3-2) Timing ..............................................................
A/D Converter Characteristics ...............................................................................
LCD Characteristics ...............................................................................................
Segment External Expansion AC Characteristics...................................................
Absolute Maximum Ratings...................................................................................
DC Characteristics..................................................................................................
Control Signal Timing............................................................................................
Serial Interface (SCI1) Timing...............................................................................
Serial Interface (SCI3-1, SCI3-2) Timing ..............................................................
A/D Converter Characteristics ...............................................................................
LCD Characteristics ...............................................................................................
Segment External Expansion AC Characteristics...................................................
Absolute Maximum Ratings...................................................................................
DC Characteristics..................................................................................................
Control Signal Timing............................................................................................
Serial Interface (SCI1) Timing...............................................................................
Serial Interface (SCI3) Timing...............................................................................
A/D Converter Characteristics ...............................................................................
LCD Characteristics ...............................................................................................
Flash Memory Characteristics................................................................................
Rev. 6.00 Aug 04, 2006 page xxxiv of xxxvi
Appendix A CPU Instruction Set
Table A.1 Instruction Set ........................................................................................................
Table A.2 Operation Code Map ..............................................................................................
Table A.3 Number of Cycles in Each Instruction ...................................................................
Table A.4 Number of Cycles in Each Instruction ...................................................................
544
552
554
555
Appendix E List of Product Codes
Table E.1
Product Code Lineup.............................................................................................. 661
Rev. 6.00 Aug 04, 2006 page xxxv of xxxvi
Rev. 6.00 Aug 04, 2006 page xxxvi of xxxvi
Section 1 Overview
Section 1 Overview
1.1
Overview
The H8/300L Series is a series of single-chip microcomputers (MCU: microcomputer unit), built
around the high-speed H8/300L CPU and equipped with peripheral system functions on-chip.
Within the H8/300L Series, the H8/3847R Group, H8/3847S Group, H8/38347 Group, and
H8/38447 Group comprise single-chip microcomputers equipped with an LCD (liquid crystal
display) controller/driver. Other on-chip peripheral functions include six types of timers, a 14-bit
pulse width modulator (PWM), three serial communication interface channels, and an A/D
converter. Together, these functions make the H8/3847R Group, H8/3847S Group, H8/38347
Group, and H8/38447 Group ideally suited for embedded applications in systems requiring low
power consumption and LCD display. Also available are models incorporating 16 Kbytes to 60
Kbytes of ROM and 1 Kbyte to 2 Kbytes of RAM on-chip.
The H8/3847R is also available in a ZTAT™*1 version with on-chip PROM which can be
programmed as required by the user.
The H8/38347 and H8/38447 are available in a F-ZTAT™*2 version with on-chip flash memory
that can be programmed on-board.
Table 1.1 summarizes the features of the H8/3847R Group, H8/3847S Group, H8/38347 Group,
and H8/38447 Group.
Notes: 1. ZTAT (Zero Turn Around Time) is a trademark of Renesas Technology Corp.
2. F-ZTAT is a trademark of Renesas Technology Corp.
Rev. 6.00 Aug 04, 2006 page 1 of 680
REJ09B0145-0600
Section 1 Overview
Table 1.1
Features
Item
Description
CPU
High-speed H8/300L CPU
•
General-register architecture
General registers: Sixteen 8-bit registers (can be used as eight 16-bit
registers)
•
•
•
Interrupts
Clock pulse
generators
Operating speed
Max. operating speed: 8 MHz
Add/subtract: 0.25 µs (operating at 8 MHz)
Multiply/divide: 1.75 µs (operating at 8 MHz)
Can run on 32.768 kHz or 38.4 kHz subclock
Instruction set compatible with H8/300 CPU
Instruction length of 2 bytes or 4 bytes
Basic arithmetic operations between registers
MOV instruction for data transfer between memory and registers
Typical instructions
Multiply (8 bits × 8 bits)
Divide (16 bits ÷ 8 bits)
Bit accumulator
Register-indirect designation of bit position
37 interrupt sources
•
13 external interrupt sources (IRQ4 to IRQ0, WKP7 to WKP0)
•
24 internal interrupt sources
Two on-chip clock pulse generators
•
System clock pulse generator:
Maximum 16 MHz (H8/3847R Group, H8/38347 Group, and H8/38447
Group)
Maximum 10 MHz (H8/3847S Group)
•
Subclock pulse generator: 32.768 kHz, 38.4 kHz
Rev. 6.00 Aug 04, 2006 page 2 of 680
REJ09B0145-0600
Section 1 Overview
Item
Description
Power-down
modes
•
Seven power-down modes
•
Sleep (high-speed) mode
•
Sleep (medium-speed) mode
•
Standby mode
•
Watch mode
•
Subsleep mode
•
Subactive mode
•
Active (medium-speed) mode
Memory
I/O ports
Large on-chip memory
•
H8/3842R, H8/38342, H8/38442: 16-Kbyte ROM, 1-Kbyte RAM
•
H8/3843R, H8/38343, H8/38443: 24-Kbyte ROM, 1-Kbyte RAM
•
H8/3844R, H8/3844S, H8/38344, H8/38444: 32-Kbyte ROM, 2-Kbyte RAM
•
H8/3845R, H8/3845S, H8/38345, H8/38445: 40-Kbyte ROM, 2-Kbyte RAM
•
H8/3846R, H8/3846S, H8/38346, H8/38446: 48-Kbyte ROM, 2-Kbyte RAM
•
H8/3847R, H8/3847S, H8/38347, H8/38447: 60-Kbyte ROM, 2-Kbyte RAM
84 pins
•
71 I/O pins
•
13 input pins
Rev. 6.00 Aug 04, 2006 page 3 of 680
REJ09B0145-0600
Section 1 Overview
Item
Description
Timers
Six on-chip timers
•
Timer A: 8-bit timer
Count-up timer with selection of eight internal clock signals divided from the
system clock (φ)* and four clock signals divided from the watch clock (φw)*
•
Asynchronous event counter: 16-bit timer
•
•
•
•
Timer C: 8-bit timer
Count-up/down timer with selection of seven internal clock signals or
event input from external pin
Auto-reloading
Timer F: 16-bit timer
Can be used as two independent 8-bit timers
Count-up timer with selection of four internal clock signals or event
input from external pin
Provision for toggle output by means of compare-match function
Timer G: 8-bit timer
Count-up timer with selection of four internal clock signals
Incorporates input capture function (built-in noise canceler)
Watchdog timer
Serial
communication
interface
14-bit PWM
Count-up timer able to count asynchronous external events
independently of the MCU's internal clocks
Reset signal generated by overflow of 8-bit counter
Three serial communication interface channels on chip
•
SCI1: Synchronous serial interface
Choice of 8-bit or 16-bit transfer data
•
SCI3-1: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
•
SCI3-2: 8-bit synchronous/asynchronous serial interface
Incorporates multiprocessor communication function
Pulse-division PWM output for reduced ripple
•
Can be used as a 14-bit D/A converter by connecting to an external lowpass filter.
Rev. 6.00 Aug 04, 2006 page 4 of 680
REJ09B0145-0600
Section 1 Overview
Item
Description
A/D converter
Successive approximations using a resistance ladder
LCD
controller/driver
•
12-channel analog input pins
•
Conversion time: 31/φ or 62/φ per channel
LCD controller/driver equipped with a maximum of 40 segment pins and four
common pins
•
Choice of four duty cycles (static, 1/2, 1/3, or 1/4)
•
Segment pins can be switched to general-purpose port function in 8-bit units
Rev. 6.00 Aug 04, 2006 page 5 of 680
REJ09B0145-0600
Section 1 Overview
Item
Description
Product lineup
Mask ROM
Version
ZTAT
Version
F-ZTAT
Version
HD6433847R
HD6433847S
HD64338347
HD64338447
HD6473847R
HD64F38347
HD64F38447
FP-100A (H8/3847R only)
FP-100B
TFP-100B
TFP-100G
Die
60 K/2 K
HD6433846R
HD6433846S
HD64338346
HD64338446
—
—
FP-100A (H8/3846R only)
FP-100B
TFP-100B
TFP-100G
Die
48 K/2 K
HD6433845R
HD6433845S
HD64338345
HD64338445
—
—
FP-100A (H8/3845R only)
FP-100B
TFP-100B
TFP-100G
Die
40 K/2 K
HD6433844R
HD6433844S
HD64338344
HD64338444
—
HD64F38344
HD64F38444
FP-100A (H8/3844R only)
FP-100B
TFP-100B
TFP-100G
Die (Mask ROM version
only)
32 K/2 K
HD6433843R
HD64338343
HD64338443
—
—
FP-100A (H8/3843R only)
FP-100B
TFP-100B
TFP-100G
Die
24 K/1 K
HD6433842R
HD64338342
HD64338442
—
—
FP-100A (H8/3842R only)
FP-100B
TFP-100B
TFP-100G
Die
16 K/1 K
Package
See appendix E for a list of product codes.
Note:
*
See section 4, Clock Pulse Generators, for the definition of φ and φw.
Rev. 6.00 Aug 04, 2006 page 6 of 680
REJ09B0145-0600
ROM/RAM
Size (Byte)
Section 1 Overview
1.2
Internal Block Diagram
Figure 1.1 (1) shows a block diagram of the H8/3847R Group and H8/3847S Group.
LCD power
supply
RES
TEST
VSS
VSS
VCC
CVCC*
X1
X2
Sub clock
OSC
Port A
Port 9
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
14-bit PWM
Timer G
LCD
controller/driver
WDT
A/D (10-bit)
Asynchronous
counter
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Port B
AVSS
Port 8
Serial
communication
interface 3-2
Timer F
AVCC
Port 7
System clock
OSC
Port 2
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Port 6
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Port C
PC0/AN8
PC1/AN9
PC2/AN10
PC3/AN11
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
P97/SEG40/CL1
P96/SEG39/CL2
P95/SEG38/DO
P94/SEG37/M
P93/SEG36
P92/SEG35
P91/SEG34
P90/SEG33
Serial
communication
interface 3-1
Timer C
Port 3
P30/PWM
P31/UD
P32/RESO
P33/SCK31
P34/RXD31
P35/TXD31
P36/AEVH
P37/AEVL
Serial
communication
interface 1
Timer A
V0
V1
V2
V3
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
RAM
(2 K and 1 K)
Port 4
P20/SCK1
P21/SI1
P22/SO1
P23
P24
P25
P26
P27
H8/300L
CPU
ROM
(60 K, 48 K, 40 K, 32 K,
24 K, and 16 K)
Port 5
P10/TMOW
P11/TMOFL
P12/TMOFH
P13/TMIG
P14/IRQ4/ADTRG
P15/IRQ1/TMIC
P16/IRQ2
P17/IRQ3/TMIF
Port 1
OSC1
OSC2
Figure 1.1 (2) shows a block diagram of the H8/38347 Group and H8/38447 Group.
Note: * Vcc in the H8/3847S
Figure 1.1 (1) Block Diagram (H8/3847R Group and H8/3847S Group)
Rev. 6.00 Aug 04, 2006 page 7 of 680
REJ09B0145-0600
LCD power
supply
RES
TEST
VSS
VSS
VCC
CVCC
X1
X2
Sub clock
OSC
Port A
Port 9
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
14-bit PWM
Timer G
LCD
controller/driver
WDT
A/D (10-bit)
Asynchronous
counter
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
Port B
AVSS
Port 8
Serial
communication
interface 3-2
Timer F
AVCC
Port 7
System clock
OSC
Port 2
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Port 6
P50/WKP0/SEG1
P51/WKP1/SEG2
P52/WKP2/SEG3
P53/WKP3/SEG4
P54/WKP4/SEG5
P55/WKP5/SEG6
P56/WKP6/SEG7
P57/WKP7/SEG8
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Port C
PC0/AN8
PC1/AN9
PC2/AN10
PC3/AN11
P40/SCK32
P41/RXD32
P42/TXD32
P43/IRQ0
P97/SEG40
P96/SEG39
P95/SEG38
P94/SEG37
P93/SEG36
P92/SEG35
P91/SEG34
P90/SEG33
Serial
communication
interface 3-1
Timer C
Port 3
P30/PWM
P31/UD/EXCL
P32
P33/SCK31
P34/RXD31
P35/TXD31
P36/AEVH
P37/AEVL
Serial
communication
interface 1
Timer A
V0
V1
V2
V3
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
RAM
(2 K and 1 K)
Port 4
P20/SCK1
P21/SI1
P22/SO1
P23
P24
P25
P26
P27
H8/300L
CPU
ROM
(60 K, 48 K, 40 K, 32 K,
24 K, and 16 K)
Port 5
P10/TMOW
P11/TMOFL
P12/TMOFH
P13/TMIG
P14/IRQ4/ADTRG
P15/IRQ1/TMIC
P16/IRQ2
P17/IRQ3/TMIF
Port 1
OSC1
OSC2
Section 1 Overview
Note: When the on-chip emulator is used, pins P24, P25, P26, and P27 are reserved for use exclusively by the
emulator and therefore cannot be accessed by the user.
Figure 1.1 (2) Block Diagram (H8/38347 Group and H8/38447 Group)
Rev. 6.00 Aug 04, 2006 page 8 of 680
REJ09B0145-0600
Section 1 Overview
1.3
Pin Arrangement and Functions
1.3.1
Pin Arrangement
The pin arrangements of the H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447
Group are shown in figures 1.2 and 1.3 (figure 1.3 only applies to the H8/3847R Group). The
bonding pad location diagram of the H8/3847R Group (Mask ROM version) is shown in figure
1.4. The bonding pad coordinates of the H8/3847R Group (Mask ROM version) are given in table
1.2. The bonding pad location diagram of the H8/3847S Group (Mask ROM version) is shown in
figure 1.5. The bonding pad coordinates of the H8/3847S Group (Mask ROM version) are given in
table 1.3.
The bonding pad location diagram of the HCD64F38347 and HCD64F38447 is shown in figure
1.6. The bonding pad coordinates of the HCD64F38347 and HCD64F38447 are given in table 1.4.
The bonding pad location diagram of the H8/38347 Group (Mask ROM version) and H8/38447
Group (Mask ROM version) is shown in figure 1.7. The bonding pad coordinates of the H8/38347
Group (Mask ROM version) and H8/38447 Group (Mask ROM version) are given in table 1.5.
Rev. 6.00 Aug 04, 2006 page 9 of 680
REJ09B0145-0600
P90/SEG33
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Section 1 Overview
V3
PB5/AN5
93
33
VSS
PB6/AN6
94
32
CVCC (VCC in the H8/3847S)
PB7/AN7
95
31
P37/AEVL
PC0/AN8
96
30
P36/AEVH
PC1/AN9
97
29
P35/TXD31
PC2/AN10
98
28
P34/RXD31
PC3/AN11
99
27
P33/SCK31
100
26
P32/RESO (P32*)
AVSS
25
34
24
92
P30/PWM
P31/UD (P31/UD/EXCL*)
V2
PB4/AN4
23
35
P27
91
22
V1
PB3/AN3
P26
36
21
90
P25
V0
PB2/AN2
20
37
P24
89
19
VCC
PB1/AN1
P23
38
18
88
P22/SO1
PA3/COM4
PB0/AN0
17
39
P21/SI1
87
16
PA2/COM3
AVCC
P20/SCK1
40
15
86
RES
PA1/COM2
P43/IRQ0
14
41
TEST
85
13
PA0/COM1
P42/TXD32
OSC1
42
12
84
OSC2
P50/WKP0/SEG1
P41/RXD32
11
43
VSS
83
10
P51/WKP1/SEG2
P40/SCK32
X2
44
9
82
X1
P52/WKP2/SEG3
P97/SEG40/CL1 (P97/SEG40*)
8
45
P17/IRQ3/TMIF
81
7
P53/WKP3/SEG4
P96/SEG39/CL2 (P96/SEG39*)
P16/IRQ2
46
6
80
P15/IRQ1/TMIC
P54/WKP4/SEG5
P95/SEG38/DO (P95/SEG38*)
5
47
P14/IRQ4/ADTRG
79
4
P55/WKP5/SEG6
P94/SEG37/M (P94/SEG37*)
P13/TMIG
48
3
78
P12/TMOFH
P56/WKP6/SEG7
P93/SEG36
2
P57/WKP7/SEG8
49
1
50
77
P10/TMOW
76
P92/SEG35
P11/TMOFL
P91/SEG34
Notes: When the on-chip emulator is used, pins P24, P25, P26, and P27 are reserved for use exclusively by the emulator and therefore
cannot be accessed by the user.
* H8/38347, H8/38447
Figure 1.2 Pin Arrangement (FP-100B, TFP-100B and TFP-100G: Top View)
Rev. 6.00 Aug 04, 2006 page 10 of 680
REJ09B0145-0600
23
24
25
26
27
28
29
30
P25
P26
P27
P30/PWM
P31/UD
P32/RESO
P33/SCK31
19
P20/SCK1
P24
18
RES
22
17
TEST
P23
16
OSC1
21
15
OSC2
P22/SO1
14
VSS
20
13
X2
P21/SI1
12
X1
9
P15/IRQ1/TMIC
11
8
P14/IRQ4/ADTRG
P17/IRQ3/TMIF
7
P13/TMIG
10
6
P12/TMOFH
P16/IRQ2
5
P11/TMOFL
3
AVSS
4
2
PC3/AN11
P10/TMOW
1
PC2/AN10
P92/SEG35
P91/SEG34
P90/SEG33
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
Section 1 Overview
P93/SEG36
81
50
P54/WKP4/SEG5
P94/SEG37/M
82
49
P53/WKP3/SEG4
P95/SEG38/DO
83
48
P52/WKP2/SEG3
P96/SEG39/CL2
84
47
P51/WKP1/SEG2
P97/SEG40/CL1
85
46
P50/WKP0/SEG1
P40/SCK32
86
45
PA0/COM1
P41/RXD32
87
44
PA1/COM2
P42/TXD32
88
43
PA2/COM3
P43/IRQ0
89
42
PA3/COM4
AVCC
90
41
VCC
PB0/AN0
91
40
V0
PB1/AN1
92
39
V1
PB2/AN2
93
38
V2
PB3/AN3
94
37
V3
PB4/AN4
95
36
VSS
PB5/AN5
96
35
CVCC
PB6/AN6
97
34
P37/AEVL
PB7/AN7
98
33
P36/AEVH
PC0/AN8
99
32
P35/TXD31
PC1/AN9
100
31
P34/RXD31
Figure 1.3 Pin Arrangement (FP-100A: Top View)
Rev. 6.00 Aug 04, 2006 page 11 of 680
REJ09B0145-0600
Section 1 Overview
100 99
98 97 96 95 94 93 92 91 90 89 88 87 86 8584 83
82 81 80
79 78
77 76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26 27
Y
X
(0, 0)
Type code
28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
52
51
43 44 45 46 47 48
49 50
: NC Pad
Chip size : 6.10mm × 6.23mm
Voltage level on the back of the chip : GND
Figure 1.4 Bonding Pad Location Diagram of H8/3847R Group (Mask ROM Version)
(Top View)
Rev. 6.00 Aug 04, 2006 page 12 of 680
REJ09B0145-0600
Section 1 Overview
Table 1.2
Bonding Pad Coordinates of H8/3847R Group (Mask ROM Version)
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
1
P10/TMOW
-2866
1939
2
P11/TMOFL
-2866
1694
3
P12/TMOFH
-2866
1500
4
P13/TMIG
-2866
1326
5
P14/IRQ4/ADTRG
-2866
984
6
P15/IRQ1/TMIC
-2866
810
7
P16/IRQ2
-2866
636
8
P17/IRQ3/TMIF
-2866
462
9
X1
-2866
288
10
X2
-2866
116
11
VSS
-2866
-56
12
OSC2
-2866
-228
13
OSC1
-2866
-402
14
TEST
-2866
-576
15
RES
-2866
-749
16
P20/SCK1
-2866
-920
17
P21/SI1
-2866
-1094
18
P22/SO1
-2866
-1266
19
P23
-2866
-1440
20
P24
-2866
-1612
21
P25
-2866
-1785
22
P26
-2866
-1969
23
P27
-2866
-2153
24
P30/PWM
-2866
-2327
25
P31/UD
-2866
-2503
26
P32/RESO
-2866
-2931
27
P33/SCK31
-2669
-2931
28
P34/RXD31
-2142
-2931
29
P35/TXD31
-1971
-2931
30
P36/AEVH
-1798
-2931
Rev. 6.00 Aug 04, 2006 page 13 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
31
P37/AEVL
-1624
-2931
32
CVCC
-1413
-2931
33
VSS
-1213
-2931
34
V3
-1017
-2931
35
V2
-844
-2931
36
V1
-672
-2931
37
V0
-496
-2931
38
VCC
-320
-2931
39
PA3/COM4
-112
-2931
40
PA2/COM3
76
-2931
41
PA1/COM2
320
-2931
42
PA0/COM1
544
-2931
43
P50/WKP0/SEG1
842
-2931
44
P51/WKP1/SEG2
1069
-2931
45
P52/WKP2/SEG3
1256
-2931
46
P53/WKP3/SEG4
1641
-2931
47
P54/WKP4/SEG5
1829
-2931
48
P55/WKP5/SEG6
2017
-2931
49
P56/WKP6/SEG7
2648
-2931
50
P57/WKP7/SEG8
2865
-2931
51
P60/SEG9
2866
-2484
52
P61/SEG10
2866
-2296
53
P62/SEG11
2866
-2061
54
P63/SEG12
2866
-1846
55
P64/SEG13
2866
-1658
56
P65/SEG14
2866
-1430
57
P66/SEG15
2866
-1244
58
P67/SEG16
2866
-1056
59
P70/SEG17
2866
-828
60
P71/SEG18
2866
-640
61
P72/SEG19
2866
-452
62
P73/SEG20
2866
-264
Rev. 6.00 Aug 04, 2006 page 14 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
63
P74/SEG21
2866
-76
64
P75/SEG22
2866
112
65
P76/SEG23
2866
300
66
P77/SEG24
2866
528
67
P80/SEG25
2866
756
68
P81/SEG26
2866
944
69
P82/SEG27
2866
1132
70
P83/SEG28
2866
1318
71
P84/SEG29
2866
1506
72
P85/SEG30
2866
1694
73
P86/SEG31
2866
1882
74
P87/SEG32
2866
2070
75
P90/SEG33
2866
2367
76
P91/SEG34
2866
2931
77
P92/SEG35
2654
2931
78
P93/SEG36
1998
2931
79
P94/SEG37/M
1803
2931
80
P95/SEG38/DO
1396
2931
81
P96/SEG39/CL2
1209
2931
82
P97/SEG40/CL1
977
2931
83
P40/SCK32
631
2931
84
P41/RXD32
456
2931
85
P42/TXD32
284
2931
86
P43/IRQ0
109
2931
87
AVCC
-64
2931
88
PB0/AN0
-236
2931
89
PB1/AN1
-409
2931
90
PB2/AN2
-581
2931
91
PB3/AN3
-753
2931
92
PB4/AN4
-925
2931
93
PB5/AN5
-1097
2931
94
PB6/AN6
-1268
2931
Rev. 6.00 Aug 04, 2006 page 15 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
95
PB7/AN7
-1532
2931
96
PC0/AN8
-1704
2931
97
PC1/AN9
-1876
2931
98
PC2/AN10
-2048
2931
99
PC3/AN11
-2658
2931
100
AVSS
-2866
2931
Note:
*
These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The
home-point position is the chip’s center and the center is located at half the distance
between the upper and lower pads and left and right pads.
Rev. 6.00 Aug 04, 2006 page 16 of 680
REJ09B0145-0600
Section 1 Overview
100
99
98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80
79 78 77
76 75
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Type code
Y
X
(0, 0)
Base type code
27
28 29 30 31 32 33 34 35 36 37 38 39 40
41 42
43 44 45 46 47 48
49
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
: NC Pad
Chip size : 3.55mm × 3.45mm
Voltage level on the back of the chip : GND
Figure 1.5 Bonding Pad Location Diagram of H8/3847S Group (Mask ROM Version)
(Top View)
Rev. 6.00 Aug 04, 2006 page 17 of 680
REJ09B0145-0600
Section 1 Overview
Table 1.3
Bonding Pad Coordinates of H8/3847S Group (Mask ROM Version)
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
1
P10/TMOW
-1655
1260
2
P11/TMOFL
-1655
999
3
P12/TMOFH
-1655
799
4
P13/TMIG
-1655
629
5
P14/IRQ4/ADTRG
-1655
451
6
P15/IRQ1/TMIC
-1655
334
7
P16/IRQ2
-1655
226
8
P17/IRQ3/TMIF
-1655
122
9
X1
-1655
37
10
X2
-1655
-48
11
VSS
-1655
-138
12
OSC2
-1655
-223
13
OSC1
-1655
-308
14
TEST
-1655
-393
15
RES
-1655
-478
16
P20/SCK1
-1655
-563
17
P21/SI1
-1655
-648
18
P22/SO1
-1655
-733
19
P23
-1655
-818
20
P24
-1655
-903
21
P25
-1655
-988
22
P26
-1655
-1073
23
P27
-1655
-1158
24
P30/PWM
-1655
-1243
25
P31/UD
-1655
-1480
26
P32/RESO
-1580
-1605
27
P33/SCK31
-1357
-1605
28
P34/RXD31
-1178
-1605
29
P35/TXD31
-1093
-1605
30
P36/AEVH
-992
-1605
Rev. 6.00 Aug 04, 2006 page 18 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
31
P37/AEVL
-906
-1605
32
VCC
-821
-1605
33
VSS
-736
-1605
34
V3
-651
-1605
35
V2
-566
-1605
36
V1
-481
-1605
37
V0
-396
-1605
38
VCC
-310
-1605
39
PA3/COM4
-215
-1605
40
PA2/COM2
-85
-1605
41
PA1/COM1
64
-1605
42
PA0/COM0
197
-1605
43
P50/WKP0/SEG1
421
-1605
44
P51/WKP1/SEG2
528
-1605
45
P52/WKP2/SEG3
635
-1605
46
P53/WKP3/SEG4
742
-1605
47
P54/WKP4/SEG5
849
-1605
48
P55/WKP5/SEG6
957
-1605
49
P56/WKP6/SEG7
1154
-1605
50
P57/WKP7/SEG8
1570
-1605
51
P60/SEG9
1655
-1527
52
P61/SEG10
1655
-1294
53
P62/SEG11
1655
-1209
54
P63/SEG12
1655
-1117
55
P64/SEG13
1655
-1010
56
P65/SEG14
1655
-903
57
P66/SEG15
1655
-796
58
P67/SEG16
1655
-689
59
P70/SEG17
1655
-559
60
P71/SEG18
1655
-452
61
P72/SEG19
1655
-345
62
P73/SEG20
1655
-237
Rev. 6.00 Aug 04, 2006 page 19 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
63
P74/SEG21
1655
-130
64
P75/SEG22
1655
-23
65
P76/SEG23
1655
84
66
P77/SEG24
1655
191
67
P80/SEG25
1655
317
68
P81/SEG26
1655
424
69
P82/SEG27
1655
532
70
P83/SEG28
1655
639
71
P84/SEG29
1655
746
72
P85/SEG30
1655
853
73
P86/SEG31
1655
960
74
P87/SEG32
1655
1067
75
P90/SEG33
1655
1527
76
P91/SEG34
1466
1605
77
P92/SEG35
1230
1605
78
P93/SEG36
1145
1605
79
P94/SEG37/M
1060
1605
80
P95/SEG38/DO
854
1605
81
P96/SEG39/CL2
747
1605
82
P97/SEG40/CL1
640
1605
83
P40/SCK32
524
1605
84
P41/RXD32
439
1605
85
P42/TXD32
354
1605
86
P43/IRQ0
269
1605
87
AVCC
101
1605
88
PB0/AN0
16
1605
89
PB1/AN1
-92
1605
90
PB2/AN2
-207
1605
91
PB3/AN3
-319
1605
92
PB4/AN4
-431
1605
93
PB5/AN5
-543
1605
94
PB6/AN6
-655
1605
Rev. 6.00 Aug 04, 2006 page 20 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
95
PB7/AN7
-767
1605
96
PC0/AN8
-879
1605
97
PC1/AN9
-991
1605
98
PC2/AN10
-1103
1605
99
PC3/AN11
-1290
1605
100
AVSS
-1523
1605
Note:
*
These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The
home-point position is the chip’s center and the center is located at half the distance
between the upper and lower pads and left and right pads.
Rev. 6.00 Aug 04, 2006 page 21 of 680
REJ09B0145-0600
Section 1 Overview
101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
80 79 78 77
Type code
76
75
74
73
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
72
71
70
69
68
Y
67
(0, 0)
66
65
64
63
62
61
60
X
59
58
57
56
24
25
26
55
54
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49
50 51
53
52
: NC Pad
Chip size : 4.35mm × 4.83mm
Voltage level on the back of the chip : GND
Figure 1.6 Bonding Pad Location Diagram of HCD64F38347 and HCD64F38447
(Top View)
Rev. 6.00 Aug 04, 2006 page 22 of 680
REJ09B0145-0600
Section 1 Overview
Table 1.4
Bonding Pad Coordinates of HCD64F38347 and HCD64F38447
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
1
P10/TMOW
-2056
1570
2
P11/TMOFL
-2056
1360
3
P12/TMOFH
-2056
1259
4
P13/TMIG
-2056
1158
5
P14/IRQ4/ADTRG
-2056
941
6
P15/IRQ1/TMIC
-2056
839
7
P16/IRQ2
-2056
737
8
P17/IRQ3/TMIF
-2056
635
9
X1
-2056
533
10
X2
-2056
431
11
VSS
-2056
329
12
VSS
-2056
193
13
OSC2
-2056
106
14
OSC1
-2056
20
15
TEST
-2056
-66
16
RES
-2056
-244
17
P20/SCK1
-2056
-402
18
P21/SI1
-2056
-574
19
P22/SO1
-2056
-747
20
P23
-2056
-919
21
P24
-2056
-1091
22
P25
-2056
-1263
23
P26
-2056
-1349
24
P27
-2056
-1521
25
P30/PWM
-2056
-1607
26
P31/UD/EXCL
-2056
-1779
27
P32
-1777
-2295
28
P33/SCK31
-1530
-2295
29
P34/RXD31
-1382
-2295
30
P35/TXD31
-1280
-2295
31
P36/AEVH
-1178
-2295
Rev. 6.00 Aug 04, 2006 page 23 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
32
P37/AEVL
-1076
-2295
33
CVCC
-896
-2295
34
VSS
-710
-2295
35
V3
-584
-2295
36
V2
-483
-2295
37
V1
-382
-2295
38
V0
-281
-2295
39
VCC
-145
-2295
40
PA3/COM4
51
-2295
41
PA2/COM3
176
-2295
42
PA1/COM2
301
-2295
43
PA0/COM1
441
-2295
44
P50/WKP0/SEG1
604
-2295
45
P51/WKP1/SEG2
775
-2295
46
P52/WKP2/SEG3
883
-2295
47
P53/WKP3/SEG4
1022
-2295
48
P54/WKP4/SEG5
1147
-2295
49
P55/WKP5/SEG6
1302
-2295
50
P56/WKP6/SEG7
1530
-2295
51
P57/WKP7/SEG8
1777
-2295
52
P60/SEG9
2056
-1955
53
P61/SEG10
2056
-1830
54
P62/SEG11
2056
-1651
55
P63/SEG12
2056
-1481
56
P64/SEG13
2056
-1300
57
P65/SEG14
2056
-1111
58
P66/SEG15
2056
-879
59
P67/SEG16
2056
-671
60
P70/SEG17
2056
-505
61
P71/SEG18
2056
-380
62
P72/SEG19
2056
-255
Rev. 6.00 Aug 04, 2006 page 24 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
63
P73/SEG20
2056
-130
64
P74/SEG21
2056
-6
65
P75/SEG22
2056
119
66
P76/SEG23
2056
244
67
P77/SEG24
2056
457
68
P80/SEG25
2056
660
69
P81/SEG26
2056
784
70
P82/SEG27
2056
909
71
P83/SEG28
2056
1034
72
P84/SEG29
2056
1159
73
P85/SEG30
2056
1378
74
P86/SEG31
2056
1503
75
P87/SEG32
2056
1627
76
P90/SEG33
2056
1840
77
P91/SEG34
1777
2295
78
P92/SEG35
1530
2295
79
P93/SEG36
1302
2295
80
P94/SEG37
1147
2295
81
P95/SEG38
901
2295
82
P96/SEG39
728
2295
83
P97/SEG40
603
2295
84
P40/SCK32
451
2295
85
P41/RXD32
350
2295
86
P42/TXD32
175
2295
87
P43/IRQ0
73
2295
88
AVCC
-155
2295
89
PB0/AN0
-290
2295
90
PB1/AN1
-440
2295
91
PB2/AN2
-588
2295
92
PB3/AN3
-695
2295
93
PB4/AN4
-801
2295
94
PB5/AN5
-890
2295
Rev. 6.00 Aug 04, 2006 page 25 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
95
PB6/AN6
-996
2295
96
PB7/AN7
-1102
2295
97
PC0/AN8
-1208
2295
98
PC1/AN9
-1313
2295
99
PC2/AN10
-1419
2295
100
PC3/AN11
-1530
2295
AVSS
-1777
2295
101
Note:
*
These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The
home-point position is the chip’s center and the center is located at half the distance
between the upper and lower pads and left and right pads. Pad numbers 11, 12, and 34
are power supply (Vss) pads and must be connected. They should not be left open. Pad
number 15 (TEST) must be connected to the Vss position. The device will not operate
properly if the pads are not connected as indicated.
Rev. 6.00 Aug 04, 2006 page 26 of 680
REJ09B0145-0600
Section 1 Overview
Base type code
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77
Type code
76
75
74
1
73
2
72
3
4
5
71
6
7
8
9
10
68
70
69
67
Y
66
65
11
12
13
14
15
64
63
(0, 0)
62
X
61
16
17
18
19
20
21
22
23
24
60
25
52
59
58
57
56
55
54
53
51
26
27 28 29 30 31 32 33 34 35 36 37
38 39 40 41 42
43 44 45 46 47 48 49 50
Chip size : 3.55mm × 3.77mm
Voltage level on the back of the chip : GND
Figure 1.7 Bonding Pad Location Diagram of H8/38347 Group (Mask ROM Version)
and H8/38447 Group (Mask ROM Version) (Top View)
Rev. 6.00 Aug 04, 2006 page 27 of 680
REJ09B0145-0600
Section 1 Overview
Table 1.5
Bonding Pad Coordinates of H8/38347 Group (Mask ROM Version)
and H8/38447 Group (Mask ROM Version)
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
1
P10/TMOW
-1658
1349
2
P11/TMOFL
-1658
1191
3
P12/TMOFH
-1658
1104
4
P13/TMIG
-1658
1006
5
P14/IRQ4/ADTRG
-1658
907
6
P15/IRQ1/TMIC
-1658
751
7
P16/IRQ2
-1658
653
8
P17/IRQ3/TMIF
-1658
555
9
X1
-1658
456
10
X2
-1658
358
11
VSS
-1658
232
12
OSC2
-1658
88
13
OSC1
-1658
-11
14
TEST
-1658
-113
15
RES
-1658
-212
16
P20/SCK1
-1658
-393
17
P21/SI1
-1658
-491
18
P22/SO1
-1658
-590
19
P23
-1658
-688
20
P24
-1658
-786
21
P25
-1658
-884
22
P26
-1658
-983
23
P27
-1658
-1081
24
P30/PWM
-1658
-1168
25
P31/UD/EXCL
-1658
-1337
26
P32
-1629
-1767
27
P33/SCK31
-1300
-1767
28
P34/RXD31
-1202
-1767
29
P35/TXD31
-1103
-1767
30
P36/AEVH
-1005
-1767
Rev. 6.00 Aug 04, 2006 page 28 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
31
P37/AEVL
-907
-1767
32
CVCC
-742
-1767
33
VSS
-625
-1767
34
V3
-508
-1767
35
V2
-416
-1767
36
V1
-324
-1767
37
V0
-207
-1767
38
VCC
-21
-1767
39
PA3/COM4
107
-1767
40
PA2/COM3
232
-1767
41
PA1/COM2
356
-1767
42
PA0/COM1
481
-1767
43
P50/WKP0/SEG1
637
-1767
44
P51/WKP1/SEG2
762
-1767
45
P52/WKP2/SEG3
887
-1767
46
P53/WKP3/SEG4
1012
-1767
47
P54/WKP4/SEG5
1158
-1767
48
P55/WKP5/SEG6
1245
-1767
49
P56/WKP6/SEG7
1332
-1767
50
P57/WKP7/SEG8
1483
-1767
51
P60/SEG9
1658
-1483
52
P61/SEG10
1658
-1335
53
P62/SEG11
1658
-1210
54
P63/SEG12
1658
-1085
55
P64/SEG13
1658
-960
56
P65/SEG14
1658
-836
57
P66/SEG15
1658
-711
58
P67/SEG16
1658
-586
59
P70/SEG17
1658
-459
60
P71/SEG18
1658
-334
61
P72/SEG19
1658
-209
62
P73/SEG20
1658
-85
Rev. 6.00 Aug 04, 2006 page 29 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
63
P74/SEG21
1658
40
64
P75/SEG22
1658
165
65
P76/SEG23
1658
290
66
P77/SEG24
1658
414
67
P80/SEG25
1658
602
68
P81/SEG26
1658
727
69
P82/SEG27
1658
852
70
P83/SEG28
1658
976
71
P84/SEG29
1658
1101
72
P85/SEG30
1658
1226
73
P86/SEG31
1658
1351
74
P87/SEG32
1658
1475
75
P90/SEG33
1658
1613
76
P91/SEG34
1500
1767
77
P92/SEG35
1290
1767
78
P93/SEG36
1202
1767
79
P94/SEG37
1066
1767
80
P95/SEG38
941
1767
81
P96/SEG39
816
1767
82
P97/SEG40
692
1767
83
P40/SCK32
574
1767
84
P41/RXD32
476
1767
85
P42/TXD32
377
1767
86
P43/IRQ0
279
1767
87
AVCC
126
1767
88
PB0/AN0
-25
1767
89
PB1/AN1
-131
1767
90
PB2/AN2
-237
1767
91
PB3/AN3
-343
1767
92
PB4/AN4
-449
1767
93
PB5/AN5
-554
1767
94
PB6/AN6
-660
1767
Rev. 6.00 Aug 04, 2006 page 30 of 680
REJ09B0145-0600
Section 1 Overview
Coordinates*
Pad No.
Pad Name
X (µm)
Y (µm)
95
PB7/AN7
-766
1767
96
PC0/AN8
-872
1767
97
PC1/AN9
-978
1767
98
PC2/AN10
-1084
1767
99
PC3/AN11
-1190
1767
100
AVSS
-1629
1767
Note:
*
These values show the coordinates of the centers of pads. The accuracy is ±5 µm. The
home-point position is the chip’s center and the center is located at half the distance
between the upper and lower pads and left and right pads. Pad numbers 11, 33, and
100 are power supply (VSS) pads and must be connected. They should not be left open.
Pad number 14 (TEST) must be connected to the Vss position. The device will not
operate properly if the pads are not connected as indicated.
Rev. 6.00 Aug 04, 2006 page 31 of 680
REJ09B0145-0600
Section 1 Overview
1.3.2
Pin Functions
Table 1.6 outlines the pin functions of the H8/3847R Group, H8/3847S Group, H8/38347 Group,
and H8/38447 Group.
Table 1.6
Pin Functions
Pin No.
Type
Symbol
FP-100B
TFP-100B
TFP-100G
Power
source
pins
VCC
CVCC
38
32
41
35
Input
Power supply: All VCC pins should
be connected to the system power
supply. See section 14, Power
Supply Circuit, for a CVcc pin (Vcc pin
in the H8/3847S Group).
VSS
11
33
14
36
Input
Ground: All VSS pins should be
connected to the system power
supply (0 V).
AVCC
87
90
Input
Analog power supply: This is the
power supply pin for the A/D
converter. When the A/D converter
is not used, connect this pin to the
system power supply.
AVSS
100
3
Input
Analog ground: This is the A/D
converter ground pin. It should be
connected to the system power
supply (0V).
V0
37
40
Output
V1
V2
V3
36
35
34
39
38
37
Input
LCD power supply: These are the
power supply pins for the LCD
controller/driver. They incorporate a
power supply split-resistance, and
are normally used with V0 and V1
shorted.
FP-100A
I/O
Name and Functions
Rev. 6.00 Aug 04, 2006 page 32 of 680
REJ09B0145-0600
Section 1 Overview
Pin No.
FP-100B
TFP-100B
TFP-100G
FP-100A
I/O
Name and Functions
Clock pins OSC1
13
16
Input
OSC2
12
15
Output
These pins connect to a crystal or
ceramic oscillator, or can be used to
input an external clock. See section
4, Clock Pulse Generators, for a
typical connection diagram.
X1
9
12
Input
X2
10
13
These pins connect to a 32.768 kHz
or 38.4 kHz crystal oscillator. Output
See section 4, Clock Pulse
Generators, for a typical connection
diagram.
EXCL
25
Input
These pins are used to input a
32.768 kHz or 38.4 kHz external
clock. See section 4, Clock Pulse
Generators, for a connection
example. This function is only
available on the H8/38347 Group
and H8/38447 Group.
RES
15
18
Input
Reset: When this pin is driven low,
the chip is reset
RESO
26
29
Output
Reset output: Outputs the CPU
internal reset signal.
Type
System
control
Symbol
This function is not implemented in
the H8/38347 Group and H8/38447
Group.
Interrupt
pins
TEST
14
17
Intput
Test pin: This pin is reserved and
cannot be used. It should be
connected to VSS.
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
86
6
7
8
5
89
9
10
11
8
Input
IRQ interrupt request 0 to 4: These
are input pins for edge-sensitive
external interrupts, with a selection
of rising or falling edge.
WKP7 to
WKP0
50 to 43
53 to 46
Input
Wakeup interrupt request 0 to 7:
These are input pins for rising or
falling- edge-sensitive external
interrupts.
Rev. 6.00 Aug 04, 2006 page 33 of 680
REJ09B0145-0600
Section 1 Overview
Pin No.
FP-100B
TFP-100B
TFP-100G
FP-100A
I/O
Name and Functions
1
4
Output
Clock output: This is an output pin
for waveforms generated by the
timer A output circuit.
AEVL
AEVH
31
30
34
33
Input
Asynchronous event counter
event input: This is an event input
pin for input to the asynchronous
event counter.
TMIC
6
9
Input
Timer C event input: This is an
event input pin for input to the timer
C counter.
UD
25
28
Input
Timer C up/down select: This pin
selects up- or down-counting for the
timer C counter. The counter
operates as a down-counter when
this pin is high, and as an up-counter
when low.
TMIF
8
11
Input
Timer F event input: This is an
event input pin for input to the timer
F counter.
TMOFL
2
5
Output
Timer FL output: This is an output
pin for waveforms generated by the
timer FL output compare function.
TMOFH
3
6
Output
Timer FH output: This is an output
pin for waveforms generated by the
timer FH output compare function.
TMIG
4
7
Input
Timer G capture input: This is an
input pin for timer G input capture.
14-bit
PWM pin
PWM
24
27
Output
14-bit PWM output: This is an
output pin for waveforms generated
by the 14-bit PWM
I/O ports
PB7 to PB0 95 to 88
98 to 91
Input
Port B: This is an 8-bit input port.
PC3 to PC0 99 to 96
2, 1,
100, 99
Input
Port C: This is a 4-bit input port.
P43
89
Input
Port 4 (bit 3): This is a 1-bit input
port.
88 to 86
I/O
Port 4 (bits 2 to 0): This is a 3-bit
I/O port. Input or output can be
designated for each bit by means of
port control register 4 (PCR4).
Type
Symbol
Timer pins TMOW
86
P42 to P40 85 to 83
Rev. 6.00 Aug 04, 2006 page 34 of 680
REJ09B0145-0600
Section 1 Overview
Pin No.
Type
Symbol
I/O ports
FP-100B
TFP-100B
TFP-100G
FP-100A
I/O
Name and Functions
PA3 to PA0 39 to 42
42 to 45
I/O
Port A: This is a 4-bit I/O port. Input
or output can be designated for each
bit by means of port control register
A (PCRA).
P17 to P10 8 to 1
11 to 4
I/O
Port 1: This is an 8-bit I/O port.
Input or output can be designated for
each bit by means of port control
register 1 (PCR1).
P27 to P20 23 to 16
26 to 19
I/O
Port 2: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register
2 (PCR2).
When the on-chip emulator is used,
pins P24, P25, P26, and P27 are
reserved for use exclusively by the
emulator and therefore cannot be
accessed by the user. With the FZTAT version, pull up pin P24 to
high level to cancel a reset in the in
the user mode.
P37 to P30 31 to 24
34 to 27
I/O
Port 3: This is an 8-bit I/O port.
Input or output can be designated for
each bit by means of port control
register 3 (PCR3).
P57 to P50 50 to 43
53 to 46
I/O
Port 5: This is an 8-bit I/O port.
Input or output can be designated for
each bit by means of port control
register 5 (PCR5).
P67 to P60 58 to 51
61 to 54
I/O
Port 6: This is an 8-bit I/O port.
Input or output can be designated for
each bit by means of port control
register 6 (PCR6).
P77 to P70 66 to 59
69 to 62
I/O
Port 7: This is an 8-bit I/O port.
Input or output can be designated for
each bit by means of port control
register 7 (PCR7).
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Section 1 Overview
Pin No.
Type
Symbol
I/O ports
FP-100A
I/O
Name and Functions
P87 to P80 74 to 67
77 to 70
I/O
Port 8: This is an 8-bit I/O port.
Input or output can be designated for
each bit by means of port control
register 8 (PCR8).
P97 to P90 82 to 75
85 to 78
I/O
Port 9: This is an 8-bit I/O port. Input
or output can be designated for each
bit by means of port control register
9 (PCR9).
17
20
Input
SCI1 receive data input: This is the
SCI1 data input pin.
18
21
Output
SCI1 transmit data output: This is
the SCI1 data output pin.
16
19
I/O
SCI1 clock I/O: This is the SCI1
clock I/O pin.
RXD31
28
31
Input
SCI3-1 receive data input: This is
the SCI31 data input pin.
TXD31
29
32
Output
SCI3-1 transmit data output: This
is the SCI31 data output pin.
SCK31
27
30
I/O
SCI3-1 clock I/O: This is the SCI31
clock I/O pin.
RXD32
84
87
Input
SCI3-2 receive data input: This is
the SCI32 data input pin.
TXD32
85
88
Output
SCI3-2 transmit data output: This
is the SCI32 data output pin.
SCK32
83
86
I/O
SCI3-2 clock I/O: This is the SCI32
clock I/O pin.
AN11 to
An0
99 to 88
2,1
100 to 91
Input
Analog input channels 11 to 0:
These are analog data input
channels to the A/D converter
ADTRG
5
8
Input
A/D converter trigger input: This is
the external trigger input pin to the
A/D converter
Serial
SI1
communication
SO1
interface
(SCI)
SCK1
A/D
converter
FP-100B
TFP-100B
TFP-100G
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Section 1 Overview
Pin No.
Type
Symbol
LCD
COM4 to
controller/ COM1
driver
SEG40 to
SEG1
CL1
FP-100B
TFP-100B
TFP-100G
FP-100A
I/O
Name and Functions
39 to 42
42 to 45
Output
LCD common output: These are
the LCD common output pins.
82 to 43
85 to 46
Output
LCD segment output: These are
the LCD segment output pins.
82
85
Output
LCD latch clock: This is the display
data latch clock output pin for
external expansion of the segment.
This function is not implemented in
the H8/38347 Group and H8/38447
Group.
CL2
81
84
Output
LCD shift clock: This is the display
data shift clock output pin for
external expansion of the segment.
This function is not implemented in
the H8/38347 Group and H8/38447
Group.
DO
80
83
Output
LCD serial data output: This is the
serial display data output pin for
external expansion of the segment.
This function is not implemented in
the H8/38347 Group and H8/38447
Group.
M
79
82
Output
LCD alternating signal: This is the
LCD alternating signal output pin for
external expansion of the segment.
This function is not implemented in
the H8/38347 Group and H8/38447
Group.
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Section 2 CPU
2.1
Overview
The H8/300L CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1
Features
Features of the H8/300L CPU are listed below.
• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including:
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct
Register indirect
Register indirect with displacement
Register indirect with post-increment or pre-decrement
Absolute address
Immediate
Program-counter relative
Memory indirect
• 64-Kbyte address space
• High-speed operation
All frequently used instructions are executed in two to four states
High-speed arithmetic and logic operations
8- or 16-bit register-register add or subtract: 0.25 µs*
8 × 8-bit multiply:
1.75 µs*
16 ÷ 8-bit divide:
1.75 µs*
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• Low-power operation modes
SLEEP instruction for transfer to low-power operation
Note: * These values are at φ = 8 MHz.
2.1.2
Address Space
The H8/300L CPU supports an address space of up to 64 Kbytes for storing program code and
data.
See section 2.8, Memory Map, for details of the memory map.
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2.1.3
Register Configuration
Figure 2.1 shows the register structure of the H8/300L CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7
0 7
0
R0H
R0L
R1H
R1L
R2H
R2L
R3H
R3L
R4H
R4L
R5H
R5L
R6H
R7H
R6L
(SP)
SP: Stack pointer
R7L
Control registers (CR)
15
0
PC
CCR
7 6 5 4 3 2 1 0
I UHUNZ VC
PC: Program counter
CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
Figure 2.1 CPU Registers
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Section 2 CPU
2.2
Register Descriptions
2.2.1
General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2.2 Stack Pointer
2.2.2
Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC): This 16-bit register indicates the address of the next instruction the CPU
will execute. All instructions are fetched 16 bits (1 word) at a time, so the least significant bit of
the PC is ignored (always regarded as 0).
Condition Code Register (CCR): This 8-bit register contains internal status information,
including the interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and
carry (C) flags. These bits can be read and written by software (using the LDC, STC, ANDC,
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ORC, and XORC instructions). The N, Z, V, and C flags are used as branching conditions for
conditional branching (Bcc) instructions.
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written
by software. For further details, see section 3.3, Interrupts.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to store the value shifted out of the end bit
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Refer to the H8/300L Series Programming Manual for the action of each instruction on the flag
bits.
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2.2.3
Initial Register Values
When the CPU is reset, the program counter (PC) is initialized to the value stored at address
H'0000 in the vector table, and the I bit in the CCR is set to 1. The other CCR bits and the general
registers are not initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer
should be initialized by software, by the first instruction executed after a reset.
2.3
Data Formats
The H8/300L CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n in a byte operand
(n = 0, 1, 2, ..., 7).
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
• The DAA and DAS instructions perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.
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2.3.1
Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2.3.
Data Type
Register No.
Data Format
7
1-bit data
RnH
1-bit data
RnL
Byte data
RnH
Byte data
RnL
Word data
Rn
7
0
6
5
4
3
2
1
Don't care
0
7
Don't care
7
7
0
6
5
4
4-bit BCD data
RnL
1
0
Don't care
LSB
Don't care
0
MSB
LSB
15
0
MSB
LSB
7
RnH
2
0
MSB
7
4-bit BCD data
3
4
03
Upper digit
Lower digit
Don't care
4
7
Don't care
Upper digit
03
Lower digit
Legend:
RnH: Upper byte of general register
RnL: Lower byte of general register
MSB: Most significant bit
LSB: Least significant bit
Figure 2.3 Register Data Formats
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Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.4 indicates the data formats in memory. The H8/300L CPU can access word data stored
in memory (MOV.W instruction), but the word data must always begin at an even address. If word
data starting at an odd address is accessed, the least significant bit of the address is regarded as 0,
and the word data starting at the preceding address is accessed. The same applies to instruction
codes.
Data Type
Address
Data Format
7
1-bit data
Address n
7
Byte data
Address n
MSB
Even address
MSB
Word data
Odd address
Byte data (CCR) on stack
Word data on stack
0
6
5
4
3
2
1
0
LSB
Upper 8 bits
Lower 8 bits
LSB
Even address
MSB
CCR
LSB
Odd address
MSB
CCR*
LSB
Even address
MSB
Odd address
LSB
CCR: Condition code register
Note: * Ignored on return
Figure 2.4 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. When the CCR is pushed on the stack, two identical copies of the CCR are pushed to
make a complete word. When they are restored, the lower byte is ignored.
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2.4
Addressing Modes
2.4.1
Addressing Modes
The H8/300L CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Addressing Modes
No.
Address Modes
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
@Rn+
Register indirect with pre-decrement
@–Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8
Memory indirect
@@aa:8
1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand in memory.
3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting
address must be even.
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4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
• Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address of
the operand. After the operand is accessed, the register is incremented by 1 for MOV.B or 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
• Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented by
1 or 2 to obtain the address of the operand in memory. The register retains the decremented
value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For MOV.W, the original
contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and
JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand (#xx:8) in its second
byte, or a 16-bit operand (#xx:16) in its third and fourth bytes. Only MOV.W instructions can
contain 16-bit immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some
bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits
and added to the program counter contents to generate a branch destination address. The
possible branching range is –126 to +128 bytes (–63 to +64 words) from the current address.
The displacement should be an even number.
8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. The word located at this
address contains the branch destination address.
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The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300L Series, the lower end of the
address area is also used as a vector area. See section 3.3, Interrupts, for details on the vector
area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See section 2.3.2, Memory Data Formats, for further
information.
2.4.2
Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions can use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify the operand. Register indirect (1) (BSET, BCLR, BNOT, and BTST
instructions) or 3-bit immediate addressing (6) can be used independently to specify a bit position
in the operand.
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4
3
2
rm
op
7 6
rm
4 3
4 3
rn
0
0
op
disp
7 6
rm
op
7 6
rm
4 3
4 3
0
0
15
op
7 6
rm
4 3
0
Register indirect with pre-decrement,
@–Rn
15
Register indirect with
post-increment, @Rn+
15
Register indirect with displacement,
@(d:16, Rn)
15
Register indirect, @Rn
op
8 7
Register direct, Rn
1
15
Addressing Mode and
Instruction Format
No.
0
0
0
Contents (16 bits) of register
indicated by rm
0
1 or 2
Contents (16 bits) of register
indicated by rm
disp
Contents (16 bits) of register
indicated by rm
Contents (16 bits) of register
indicated by rm
3
rm
0
3
rn
Effective Address (EA)
0
15
15
15
15
0
0
0
0
Operand is contents of registers indicated by rm/rn
Incremented or decremented
by 1 if operand is byte size,
1 or 2
and by 2 if word size
15
15
15
15
Effective Address Calculation Method
Section 2 CPU
Table 2.2 Effective Address Calculation
7
6
5
No..
op
op
IMM
op
8 7
abs
op
8 7
IMM
abs
15
op
8 7
disp
Program-counter relative
@(d:8, PC)
15
#xx:16
15
Immediate
#xx:8
15
@aa:16
15
Absolute address
@aa:8
Addressing Mode and
Instruction Format
0
0
0
0
0
PC contents
Sign extension
15
disp
0
15
15
H'FF
8 7
Effective Address (EA)
0
0
15
0
Operand is 1- or 2-byte immediate data
Effective Address Calculation Method
Section 2 CPU
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Legend:
rm, rn: Register field
Operation field
op:
disp: Displacement
IMM: Immediate data
abs: Absolute address
op
8 7
abs
Memory indirect, @@aa:8
8
15
Addressing Mode and
Instruction Format
No.
0
15
8 7
abs
Memory contents (16 bits)
H'00
0
Effective Address Calculation Method
15
Effective Address (EA)
0
Section 2 CPU
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Section 2 CPU
2.5
Instruction Set
The H8/300L Series can use a total of 55 instructions, which are grouped by function in table 2.3.
Table 2.3
Instruction Set
Function
Instructions
Number
Data transfer
1
1
MOV, PUSH* , POP*
1
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS, SUBS,
DAA, DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
AND, OR, XOR, NOT
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR
8
Bit manipulation
Branch
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR, BIOR, 14
BXOR, BIXOR, BLD, BILD, BST, BIST
2
Bcc* , JMP, BSR, JSR, RTS
5
System control
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
8
Block data transfer
EEPMOV
1
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to the machine
language.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
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Notation
Rd
General register (destination)
Rs
General register (source)
Rn
General register
(EAd), <Ead>
Destination operand
(EAs), <Eas>
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
~
Logical negation (logical complement)
:3
3-bit length
:8
8-bit length
:16
16-bit length
( ), < >
Contents of operand indicated by effective address
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2.5.1
Data Transfer Instructions
Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.
Table 2.4
Data Transfer Instructions
Instruction
Size*
MOV
B/W
Function
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general
register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for word data. The @aa:8
addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not
specify byte size for these two modes.
POP
W
@SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to
MOV.W @SP+, Rn.
PUSH
W
Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to
MOV.W Rn, @–SP.
Note:
*
Size: Operand size
B:
Byte
W:
Word
Certain precautions are required in data access. See section 2.9.1, Notes on Data Access, for
details.
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15
8
7
0
op
rm
15
8
rn
0
rm
8
Rm→Rn
7
op
15
MOV
rn
@Rm←→Rn
7
0
op
rm
rn
@(d:16, Rm)←→Rn
disp
15
8
7
0
op
rm
15
8
op
7
0
rn
15
@Rm+→Rn, or
Rn→ @-Rm
rn
abs
8
@aa:8←→Rn
7
0
op
rn
@aa:16←→Rn
abs
15
8
op
7
0
rn
15
IMM
8
#xx:8→Rn
7
0
op
rn
#xx:16→Rn
IMM
15
8
7
op
0
1
1
1
rn
Legend:
op:
Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data
Figure 2.5 Data Transfer Instruction Codes
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PUSH, POP
@SP+ → Rn, or
Rn → @-SP
Section 2 CPU
2.5.2
Arithmetic Operations
Table 2.5 describes the arithmetic instructions.
Table 2.5
Arithmetic Instructions
Instruction
Size*
Function
ADD
SUB
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
ADDX
SUBX
B
INC
DEC
B
ADDS
SUBS
W
DAA
DAS
B
MULXU
B
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in
two general registers, or addition or subtraction on immediate data
and data in a general register.
Rd ± 1 → Rd
Increments or decrements a general register by 1.
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts 1 or 2 to or from a general register
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to 4-bit BCD) an addition or subtraction
result in a general register by referring to the CCR
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result
DIVXU
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
CMP
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and indicates the result in the CCR.
Word data can be compared only between two general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register
Note:
*
Size: Operand size
B:
Byte
W:
Word
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Section 2 CPU
2.5.3
Logic Operations
Table 2.6 describes the four instructions that perform logic operations.
Table 2.6
Logic Operation Instructions
Instruction
Size*
Function
AND
B
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data
OR
B
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data
XOR
B
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data
NOT
B
~ Rd → Rd
Obtains the one’s complement (logical complement) of general
register contents
Note:
*
Size: Operand size
B:
Byte
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Section 2 CPU
2.5.4
Shift Operations
Table 2.7 describes the eight shift instructions.
Table 2.7
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B
Rd shift → Rd
SHLL
SHLR
B
Rd shift → Rd
ROTL
ROTR
B
Rd rotate → Rd
ROTXL
ROTXR
B
Note:
Performs an arithmetic shift operation on general register contents
Performs a logical shift operation on general register contents
Rotates general register contents
Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit
*
Size: Operand size
B:
Byte
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Section 2 CPU
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
8
7
op
0
rm
15
8
7
0
op
15
8
7
0
rm
8
op
rn
7
7
op
0
rm
8
op
rn
7
rn
15
ADD, ADDX, SUBX,
CMP (#XX:8)
IMM
8
15
MULXU, DIVXU
0
rn
15
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
rn
op
15
ADD, SUB, CMP,
ADDX, SUBX (Rm)
rn
AND, OR, XOR (Rm)
0
IMM
8
AND, OR, XOR (#xx:8)
7
op
0
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
Legend:
Operation field
op:
rm, rn: Register field
IMM: Immediate data
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
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Section 2 CPU
2.5.5
Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.
Table 2.8
Bit-Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.
BNOT
B
~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit
number is specified by 3-bit immediate data or the lower three bits of
a general register.
BTST
B
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIAND
B
C ∧ [~ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIOR
B
C ∨ [~ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
Note:
*
Size: Operand size
B:
Byte
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Section 2 CPU
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIXOR
B
C ⊕ [~(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag.
BILD
B
~ (<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or memory to
the C flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
BIST
B
~ C → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
Copies the inverse of the C flag to a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
Note:
*
Size: Operand size
B:
Byte
Certain precautions are required in bit manipulation. See section 2.9.2, Notes on Bit
Manipulation, for details.
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Section 2 CPU
BSET, BCLR, BNOT, BTST
15
8
7
op
0
IMM
15
8
7
op
0
rm
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
Operand: register direct (Rn)
Bit No.: register direct (Rm)
rn
7
op
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
op
rn
0
0
0
0 Operand: register indirect (@Rn)
op
rm
0
0
0
0 Bit No.:
op
15
8
15
8
7
0
7
abs
IMM
15
8
0
Operand: absolute (@aa:8)
0
0
7
0 Bit No.:
immediate (#xx:3)
0
op
abs
op
register direct (Rm)
0
op
op
immediate (#xx:3)
rm
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Legend:
Operation field
op:
rm, rn: Register field
Absolute address
abs:
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes
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Section 2 CPU
BIAND, BIOR, BIXOR, BILD, BIST
15
8
7
0
op
15
IMM
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Legend:
Operation field
op:
rm, rn: Register field
Absolute address
abs:
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes (cont)
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Section 2 CPU
2.5.6
Branching Instructions
Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats.
Table 2.9
Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the designated address if condition cc is true. The
branching conditions are given below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
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Section 2 CPU
15
8
op
7
0
cc
15
disp
8
7
op
0
rm
15
Bcc
8
0
0
0
7
0
JMP (@Rm)
0
op
JMP (@aa:16)
abs
15
8
7
0
op
abs
15
8
JMP (@@aa:8)
7
0
op
disp
15
8
7
op
0
rm
15
BSR
8
0
0
0
7
0
JSR (@Rm)
0
op
JSR (@aa:16)
abs
15
8
7
op
0
abs
15
8
7
op
Legend:
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address
Figure 2.8 Branching Instruction Codes
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JSR (@@aa:8)
0
RTS
Section 2 CPU
2.5.7
System Control Instructions
Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats.
Table 2.10 System Control Instructions
Instruction
Size*
Function
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition from active mode to a power-down mode. See
section 5, Power-Down Modes, for details.
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition
code register
STC
B
CCR → Rd
Copies the condition code register to a specified general register
ANDC
B
CCR ∧ #IMM → CCR
Logically ANDs the condition code register with immediate data
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data
NOP
—
PC + 2 → PC
Only increments the program counter
Note:
*
Size: Operand size
B:
Byte
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Section 2 CPU
15
8
7
0
op
15
8
RTE, SLEEP, NOP
7
0
op
15
rn
8
7
LDC, STC (Rn)
0
op
IMM
ANDC, ORC,
XORC, LDC (#xx:8)
Legend:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2.9 System Control Instruction Codes
2.5.8
Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction
Size
Function
EEPMOV
—
If R4L ≠ 0 then
repeat
until
@R5+ → @R6+
R4L –1 → R4L
R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by
R5 to locations starting at the address indicated by R6. After the
transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See section 2.9.3, Notes on
Use of the EEPMOV Instruction, for details.
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Section 2 CPU
15
8
7
0
op
op
Legend:
op: Operation field
Figure 2.10 Block Data Transfer Instruction Code
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Section 2 CPU
2.6
Basic Operational Timing
CPU operation is synchronized by a system clock (φ) or a subclock (φSUB). For details on these
clock signals see section 4, Clock Pulse Generators. The period from a rising edge of φ or φSUB to
the next rising edge is called one state. A bus cycle consists of two states or three states. The
cycle differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing
access in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φ or φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in two states or three states. The data bus width is 8 bits,
so access is by byte size only. This means that for accessing word data, two instructions must be
used. Figures 2.12 and 2.13 show the on-chip peripheral module access cycle.
Two-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
φ or φ SUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle (2-State Access)
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Section 2 CPU
Three-state access to on-chip peripheral modules
Bus cycle
T1 state
T2 state
T3 state
φ or φ SUB
Internal
address bus
Address
Internal
read signal
Internal
data bus
(read access)
Read data
Internal
write signal
Internal
data bus
(write access)
Write data
Figure 2.13 On-Chip Peripheral Module Access Cycle (3-State Access)
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Section 2 CPU
2.7
CPU States
2.7.1
Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode and subactive mode. In the program halt state there are a sleep (high-speed or
medium-speed) mode, standby mode, watch mode, and sub-sleep mode. These states are shown in
figure 2.14. Figure 2.15 shows the state transitions.
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Section 2 CPU
CPU state
Reset state
The CPU is initialized
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Subactive mode
The CPU executes
successive program
instructions at reduced
speed, synchronized
by the subclock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Low-power
modes
Sleep (high-speed)
mode
Sleep (medium-speed)
mode
Standby mode
Watch mode
Subsleep mode
Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 5, Power-Down Modes, for details on the modes and their transitions.
Figure 2.14 CPU Operation States
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Section 2 CPU
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
occurs
Program halt state
Interrupt
source
occurs
Exceptionhandling
complete
Program execution state
SLEEP instruction executed
Figure 2.15 State Transitions
2.7.2
Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are three modes in this state, two active modes (high speed and medium speed) and one
subactive mode. Operation is synchronized with the system clock in active mode (high speed and
medium speed), and with the subclock in subactive mode. See section 5, Power-Down Modes for
details on these modes.
2.7.3
Program Halt State
In the program halt state there are five modes: two sleep modes (high speed and medium speed),
standby mode, watch mode, and subsleep mode. See section 5, Power-Down Modes for details on
these modes.
2.7.4
Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 3.3, Interrupts.
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Section 2 CPU
2.8
Memory Map
2.8.1
Memory Map
The memory map of the H8/3842R, H8/38342, and H8/38442 is shown in figure 2.16 (1), that of
the H8/3843R, H8/38343, and H8/38443 in figure 2.16 (2), that of the H8/3844R, H8/3844S,
H8/38344, and H8/38444 in figure 2.16 (3), that of the H8/3845R, H8/3845S, H8/38345, and
H8/38445 in figure 2.16 (4), that of the H8/3846R, H8/3846S, H8/38346, and H8/38446 in figure
2.16 (5), and that of the H8/3847R, H8/3847S, H8/38347, and H8/38447 in figure 2.16 (6).
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Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
16 Kbytes
On-chip ROM
(16384 bytes)
H'3FFF
Not used
H'F740
LCD RAM
(32 bytes)
H'F75F
Not used
H'F780
On-chip RAM
1024 bytes
H'FB7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2.16 (1) H8/3842R, H8/38342 and H8/38442 Memory Map
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Section 2 CPU
H'0000
H'0029
Interrupt
vector area
H'002A
24 Kbytes
On-chip ROM
(24576 bytes)
H'5FFF
Not used
H'F740
H'F75F
LCD RAM
(32 bytes)
Not used
H'F780
On-chip RAM
1024 bytes
H'FB7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2.16 (2) H8/3843R, H8/38343 and H8/38443 Memory Map
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Section 2 CPU
HD6433844R (Mask ROM Version)
HD6433844S (Mask ROM Version)
HD64338344 (Mask ROM Version)
HD64338444 (Mask ROM Version)
HD64F38344 (Flash Memory Version)
HD64F38444 (Flash Memory Version)
H'0000
H'0000
Interrupt vector area
H'0029
Interrupt vector area
H'0029
H'002A
32 Kbytes
H'002A
32 Kbytes
(32768 bytes)
(32768 bytes)
On-chip ROM
On-chip ROM
H'7FFF
H'7FFF
Not used
H'E000
H'EFFF
Firmware for on-chip emulator*1
Not used
Not used
H'F020
H'F02B
Internal I/O registers
Not used
H'F300
H'F6FF
(Work area for programming
flash memory: 1 Kbyte)*2
Not used
H'F740
H'F75F
H'F740
LCD RAM
(32 bytes)
H'F75F
Not used
Not used
H'F780
H'F780
On-chip RAM
H'FF7F
2048 bytes
On-chip RAM
Internal I/O registers
Not used
H'FF90
(112 bytes)
H'FFFF
2048 bytes
H'FF7F
Not used
H'FF90
LCD RAM
(32 bytes)
Internal I/O registers
(112 bytes)
H'FFFF
Notes: 1. Not accessible by the user when the on-chip emulator is used.
2. A programming control program is used to program flash memory. Do not use a user program to perform
programming when the on-chip emulator is used. This area is not used in the mask ROM version.
Figure 2.16 (3) H8/3844R, H8/3844S, H8/38344 and H8/38444 Memory Map
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Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
40 Kbytes
On-chip ROM
(40960 bytes)
H'9FFF
Not used
H'F740
LCD RAM
(32 bytes)
H'F75F
Not used
H'F780
On-chip RAM
2048 bytes
H'FF7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2.16 (4) H8/3845R, H8/3845S, H8/38345 and H8/38445 Memory Map
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Section 2 CPU
H'0000
Interrupt vector area
H'0029
H'002A
48 Kbytes
(49152 bytes)
On-chip ROM
H'BFFF
Not used
H'F740
H'F75F
LCD RAM
(32 bytes)
Not used
H'F780
On-chip RAM
2048 bytes
H'FF7F
Not used
H'FF90
Internal I/O registers
(112 bytes)
H'FFFF
Figure 2.16 (5) H8/3846R, H8/3846S, H8/38346 and H8/38446 Memory Map
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Section 2 CPU
HD6433847R (Mask ROM Version)
HD6433847S (Mask ROM Version)
HD64338347 (Mask ROM Version)
HD64338447 (Mask ROM Version)
HD6473847R (PROM Version)
HD64F38347 (Flash Memory Version)
HD64F38447 (Flash Memory Version)
H'0000
H'0000
Interrupt vector area
H'0029
H'0029
H'002A
H'002A
On-chip ROM
H'E000
H'EFFF
61440 bytes
Interrupt vector area
On-chip ROM
60928 bytes
H'EDFF
Firmware for on-chip emulator*1
Not used
H'F020
H'F02B
Internal I/O registers
Not used
Not used
H'F300
H'F6FF
(Work area for programming
flash memory: 1 Kbyte)*2
Not used
H'F740
H'F75F
H'F740
LCD RAM
(32 bytes)
H'F75F
Not used
Not used
H'F780
H'F780
On-chip RAM
2048 bytes
H'FF7F
On-chip RAM
2048 bytes
H'FF7F
Not used
H'FF90
LCD RAM
(32 bytes)
Internal I/O registers
Not used
H'FF90
(112 bytes)
H'FFFF
Internal I/O registers
(112 bytes)
H'FFFF
Notes: 1. Not accessible by the user when the on-chip emulator is used.
2. A programming control program is used to program flash memory. Do not use a user program to perform
programming when the on-chip emulator is used. This area is not used in the mask ROM version.
Figure 2.16 (6) H8/3847R, H8/3847S, H8/38347 and H8/38447 Memory Map
Rev. 6.00 Aug 04, 2006 page 82 of 680
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Section 2 CPU
2.9
Application Notes
2.9.1
Notes on Data Access
1. Access to Empty Areas:
The address space of the H8/300L CPU includes empty areas in addition to the RAM,
registers, and ROM areas available to the user. If these empty areas are mistakenly accessed
by an application program, the following results will occur.
Data transfer from CPU to empty area:
The transferred data will be lost. This action may also cause the CPU to misoperate.
Data transfer from empty area to CPU:
Unpredictable data is transferred.
2. Access to Internal I/O Registers:
Internal data transfer to or from on-chip modules other than the ROM and RAM areas makes
use of an 8-bit data width. If word access is attempted to these areas, the following results will
occur.
Word access from CPU to I/O register area:
Upper byte: Will be written to I/O register.
Lower byte: Transferred data will be lost.
Word access from I/O register to CPU:
Upper byte: Will be written to upper part of CPU register.
Lower byte: Unpredictable data will be written to lower part of CPU register.
Byte size instructions should therefore be used when transferring data to or from I/O registers
other than the on-chip ROM and RAM areas. Figure 2.17 shows the data size and number of
states in which on-chip peripheral modules can be accessed.
Rev. 6.00 Aug 04, 2006 page 83 of 680
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Section 2 CPU
Access
States
Word
Byte
H'0000
H'0029
Interrupt vector area
(42 bytes)
H'002A
2
32Kbytes
On-chip ROM
H'7FFF
Not used
—
—
—
H'F740
LCD RAM
(20 bytes)
2
H'F753
—
Not used
—
—
H'F780
On-chip RAM
2
2048 bytes
H'FF7F
Not used
—
H'FF90
Internal I/O registers
(112 bytes)
H'FF98 to H'FF9F
H'FFA8 to H'FFAF
H'FFFF
—
—
×
2
×
3
×
2
×
3
×
2
Note: The H8/3844R, H8/3844S, H8/38344, and H8/38444 are shown as an example.
Figure 2.17 Data Size and Number of States for Access to and from
On-Chip Peripheral Modules
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Section 2 CPU
2.9.2
Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation
Operation
1
Read
Read byte data at the designated address
2
Modify
Modify a designated bit in the read data
3
Write
Write the altered byte data to the designated address
1. Bit Manipulation in Two Registers Assigned to the Same Address
Example 1: timer load register and timer counter
Figure 2.18 shows an example in which two timer registers share the same address. When a bit
manipulation instruction accesses the timer load register and timer counter of a reloadable timer,
since these two registers share the same address, the following operations take place.
Order of Operation
Operation
1
Read
Timer counter data is read (one byte)
2
Modify
The CPU modifies (sets or resets) the bit designated in the instruction
3
Write
The altered byte data is written to the timer load register
The timer counter is counting, so the value read is not necessarily the same as the value in the
timer load register. As a result, bits other than the intended bit in the timer load register may be
modified to the timer counter value.
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Section 2 CPU
Read
Count clock
Timer counter
Reload
Write
Timer load register
Internal bus
Figure 2.18 Timer Configuration Example
Example 2: BSET instruction executed designating port 3
P37 and P36 are designated as input pins, with a low-level signal input at P37 and a high-level
signal at P36. The remaining pins, P35 to P30, are output pins and output low-level signals. In this
example, the BSET instruction is used to change pin P30 to high-level output.
[A: Prior to executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
[B: BSET instruction executed]
BSET
#0
,
@PDR3
The BSET instruction is executed designating port 3.
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Section 2 CPU
[C: After executing BSET]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
0
0
1
1
1
1
1
1
PDR3
0
1
0
0
0
0
0
1
[D: Explanation of how BSET operates]
When the BSET instruction is executed, first the CPU reads port 3.
Since P37 and P36 are input pins, the CPU reads the pin states (low-level and high-level input).
P35 to P30 are output pins, so the CPU reads the value in PDR3. In this example PDR3 has a value
of H'80, but the value read by the CPU is H'40.
Next, the CPU sets bit 0 of the read data to 1, changing the PDR3 data to H'41. Finally, the CPU
writes this value (H'41) to PDR3, completing execution of BSET.
As a result of this operation, bit 0 in PDR3 becomes 1, and P30 outputs a high-level signal.
However, bits 7 and 6 of PDR3 end up with different values.
To avoid this problem, store a copy of the PDR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PDR3.
[A: Prior to executing BSET]
The PDR3 value (H'80) is written to a work area in
memory (RAM0) as well as to PDR3.
MOV. B #H'80 ,
MOV. B R0L
,
MOV. B R0L
,
R0L
@RAM0
@PDR3
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
RAM0
1
0
0
0
0
0
0
0
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Section 2 CPU
[B: BSET instruction executed]
BSET
#0
,
@RAM0
The BSET instruction is executed designating the PDR3
work area (RAM0).
[C: After executing BSET]
MOV. B @RAM0,
MOV. B R0L,
R0L
@PDR3
The work area (RAM0) value is written to PDR3.
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
1
RAM0
1
0
0
0
0
0
0
1
2. Bit Manipulation in a Register Containing a Write-only Bit
Example 3: BCLR instruction executed designating port 3 control register PCR3
As in the examples above, P37 and P36 are input pins, with a low-level signal input at P37 and a
high-level signal at P36. The remaining pins, P35 to P30, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P30 to an input port. It is
assumed that a high-level signal will be input to this input pin.
[A: Prior to executing BCLR]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
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Section 2 CPU
[B: BCLR instruction executed]
BSET
#0
,
@PCR3
The BCLR instruction is executed designating PCR3.
[C: After executing BCLR]
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
1
1
1
1
1
1
1
0
PDR3
1
0
0
0
0
0
0
0
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads PCR3. Since PCR3 is a write-only
register, the CPU reads a value of H'FF, even though the PCR3 value is actually H'3F.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE. Finally, this value
(H'FE) is written to PCR3 and BCLR instruction execution ends.
As a result of this operation, bit 0 in PCR3 becomes 0, making P30 an input port. However, bits 7
and 6 in PCR3 change to 1, so that P37 and P36 change from input pins to output pins.
To avoid this problem, store a copy of the PCR3 data in a work area in memory. Perform the bit
manipulation on the data in the work area, then write this data to PCR3.
[A: Prior to executing BCLR]
The PCR3 value (H'3F) is written to a work area in
memory (RAM0) as well as to PCR3.
MOV. B #H'3F ,
MOV. B R0L
,
MOV. B R0L
,
R0L
@RAM0
@PCR3
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
PCR3
0
0
1
1
1
1
1
1
PDR3
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
1
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Section 2 CPU
[B: BCLR instruction executed]
BCLR
#0
,
The BCLR instruction is executed designating the PCR3
work area (RAM0).
@RAM0
[C: After executing BCLR]
MOV. B @RAM0,
MOV. B R0L,
The work area (RAM0) value is written to PCR3.
R0L
@PCR3
P37
P36
P35
P34
P33
P32
P31
P30
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
High
level
PCR3
0
0
1
1
1
1
1
0
PDR3
1
0
0
0
0
0
0
0
RAM0
0
0
1
1
1
1
1
0
Table 2.12 lists the pairs of registers that share identical addresses. Table 2.13 lists the registers
that contain write-only bits.
Table 2.12 Registers with Shared Addresses
Register Name
Abbr.
Address
Timer counter and timer load register C
Port data register 1*
TCC/TLC
H'FFB5
PDR1
H'FFD4
Port data register 2*
PDR2
H'FFD5
Port data register 3*
Port data register 4*
PDR3
H'FFD6
PDR4
H'FFD7
Port data register 5*
Port data register 6*
PDR5
H'FFD8
PDR6
H'FFD9
Port data register 7*
PDR7
H'FFDA
Port data register 8*
PDR8
H'FFDB
Port data register 9*
Port data register A*
PDR9
H'FFDC
PDRA
H'FFDD
Note:
*
Port data registers have the same addresses as input pins.
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Section 2 CPU
Table 2.13 Registers with Write-Only Bits
Register Name
Abbr.
Address
Port control register 1
PCR1
H'FFE4
Port control register 2
PCR2
H'FFE5
Port control register 3
PCR3
H'FFE6
Port control register 4
PCR4
H'FFE7
Port control register 5
PCR5
H'FFE8
Port control register 6
PCR6
H'FFE9
Port control register 7
PCR7
H'FFEA
Port control register 8
PCR8
H'FFEB
Port control register 9
PCR9
H'FFEC
Port control register A
PCRA
H'FFED
Timer control register F
TCRF
H'FFB6
PWM control register
PWCR
H'FFD0
PWM data register U
PWDRU
H'FFD1
PWM data register L
PWDRL
H'FFD2
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Section 2 CPU
2.9.3
Notes on Use of the EEPMOV Instruction
• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
R5 →
← R6
R5 + R4L →
← R6 + R4L
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
R5 + R4L →
← R6
H'FFFF
Not allowed
Rev. 6.00 Aug 04, 2006 page 92 of 680
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← R6 + R4L
Section 3 Exception Handling
Section 3 Exception Handling
3.1
Overview
Exception handling is performed in the H8/3847R Group when a reset or interrupt occurs. Table
3.1 shows the priorities of these two types of exception handling.
Table 3.1
Exception Handling Types and Priorities
Priority
Exception Source
Time of Start of Exception Handling
High
Reset
Exception handling starts as soon as the reset state is cleared
Interrupt
When an interrupt is requested, exception handling starts after
execution of the present instruction or the exception handling in
progress is completed
Low
3.2
Reset
3.2.1
Overview
A reset is the highest-priority exception. The internal state of the CPU and the registers of the onchip peripheral modules are initialized.
3.2.2
Reset Sequence
As soon as the RES pin goes low, all processing is stopped and the chip enters the reset state.
To make sure the chip is reset properly, observe the following precautions.
• At power on: Hold the RES pin low until the clock pulse generator output stabilizes.
• Resetting during operation: Hold the RES pin low for at least 10 system clock cycles.
Reset exception handling takes place as follows.
• The CPU internal state and the registers of on-chip peripheral modules are initialized, with the
I bit of the condition code register (CCR) set to 1.
• The PC is loaded from the reset exception handling vector address (H'0000 to H'0001), after
which the program starts executing from the address indicated in PC.
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Section 3 Exception Handling
When system power is turned on or off, the RES pin should be held low.
Figure 3.1 shows the reset sequence starting from RES input.
Reset cleared
Program initial
instruction prefetch
Vector fetch Internal
processing
RES
φ
Internal
address bus
(1)
(2)
Internal read
signal
Internal write
signal
Internal data
bus (16-bit)
(2)
(3)
(1) Reset exception handling vector address (H'0000)
(2) Program start address
(3) First instruction of program
Figure 3.1 Reset Sequence
3.2.3
Interrupt Immediately after Reset
After a reset, if an interrupt were to be accepted before the stack pointer (SP: R7) was initialized,
PC and CCR would not be pushed onto the stack correctly, resulting in program runaway. To
prevent this, immediately after reset exception handling all interrupts are masked. For this reason,
the initial program instruction is always executed immediately after a reset. This instruction
should initialize the stack pointer (e.g. MOV.W #xx: 16, SP).
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Section 3 Exception Handling
3.3
Interrupts
3.3.1
Overview
The interrupt sources include 13 external interrupts (IRQ4 to IRQ0, WKP7 to WKP0) and 24
internal interrupts from on-chip peripheral modules. Table 3.2 shows the interrupt sources, their
priorities, and their vector addresses. When more than one interrupt is requested, the interrupt with
the highest priority is processed.
The interrupts have the following features:
• Internal and external interrupts can be masked by the I bit in CCR. When the I bit is set to 1,
interrupt request flags can be set but the interrupts are not accepted.
• IRQ4 to IRQ0 and WKP7 to WKP0 can be set to either rising edge sensing or falling edge
sensing.
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Section 3 Exception Handling
Table 3.2
Interrupt Sources and Their Priorities
Interrupt Source
RES
Watchdog timer
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
WKP0
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
SCI1
Timer A
Asynchronous
counter
Timer C
Interrupt
Reset
Vector Number
0
Vector Address Priority
H'0000 to H'0001 High
IRQ0
4
H'0008 to H'0009
IRQ1
5
H'000A to H'000B
IRQ2
6
H'000C to H'000D
IRQ3
7
H'000E to H'000F
IRQ4
8
H'0010 to H'0011
WKP0
9
H'0012 to H'0013
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
SCI1 transfer complete
10
H'0014 to H'0015
Timer A overflow
11
H'0016 to H'0017
Asynchronous counter
12
H'0018 to H'0019
overflow
Timer C overflow or
13
H'001A to H'001B
underflow
Timer FL
Timer FL compare match
14
H'001C to H'001D
Timer FL overflow
Timer FH
Timer FH compare match
15
H'001E to H'001F
Timer FH overflow
Timer G
Timer G input capture
16
H'0020 to H'0021
Timer G overflow
SCI3-1
SCI3-1 transmit end
17
H'0022 to H'0023
SCI3-1 transmit data empty
SCI3-1 receive data full
SCI3-1 overrrun error
SCI3-1 framing error
SCI3-1 parity error
SCI3-2
SCI3-2 transmit end
18
H'0024 to H'0025
SCI3-2 transmit data empty
SCI3-2 receive data full
SCI3-2 overrun error
SCI3-2 framing error
SCI3-2 parity error
A/D
A/D conversion end
19
H'0026 to H'0027
(SLEEP instruction Direct transfer
20
H'0028 to H'0029
executed)
Low
Note: Vector addresses H'0002 to H'0007 are reserved and cannot be used.
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Section 3 Exception Handling
3.3.2
Interrupt Control Registers
Table 3.3 lists the registers that control interrupts.
Table 3.3
Interrupt Control Registers
Name
Abbreviation
R/W
Initial Value
Address
IRQ edge select register
IEGR
R/W
H'E0
H'FFF2
Interrupt enable register 1
IENR1
R/W
H'00
H'FFF3
Interrupt enable register 2
IENR2
R/W
H'00
H'FFF4
Interrupt request register 1
IRR1
R/W *
H'20
H'FFF6
Interrupt request register 2
IRR2
H'00
H'FFF7
Wakeup interrupt request register
IWPR
R/W *
R/W *
H'00
H'FFF9
Wakeup edge select register
WEGR
R/W
H'00
H'FF90
Note:
*
Write is enabled only for writing of 0 to clear a flag.
1. IRQ Edge Select Register (IEGR)
Bit
7
6
5
4
3
2
1
0
—
—
—
IEG4
IEG3
IEG2
IEG1
IEG0
Initial value
1
1
1
0
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
IEGR is an 8-bit read/write register used to designate whether pins IRQ4 to IRQ0 are set to rising
edge sensing or falling edge sensing.
Bits 7 to 5: Reserved bits
Bits 7 to 5 are reserved: they are always read as 1 and cannot be modified.
Bit 4: IRQ4 edge select (IEG4)
Bit 4 selects the input sensing of the IRQ4 pin and ADTRG pin.
Bit 4
IEG4
Description
0
Falling edge of IRQ4 and ADTRG pin input is detected
1
Rising edge of IRQ4 and ADTRG pin input is detected
(initial value)
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Section 3 Exception Handling
Bit 3: IRQ3 edge select (IEG3)
Bit 3 selects the input sensing of the IRQ3 pin and TMIF pin.
Bit 3
IEG3
Description
0
Falling edge of IRQ3 and TMIF pin input is detected
1
Rising edge of IRQ3 and TMIF pin input is detected
(initial value)
Bit 2: IRQ2 edge select (IEG2)
Bit 2 selects the input sensing of pin IRQ2.
Bit 2
IEG2
Description
0
Falling edge of IRQ2 pin input is detected
1
Rising edge of IRQ2 pin input is detected
(initial value)
Bit 1: IRQ1 edge select (IEG1)
Bit 3 selects the input sensing of the IRQ1 pin and TMIC pin.
Bit 1
IEG1
Description
0
Falling edge of IRQ1 and TMIC pin input is detected
1
Rising edge of IRQ1 and TMIC pin input is detected
(initial value)
Bit 0: IRQ0 edge select (IEG0)
Bit 0 selects the input sensing of pin IRQ0.
Bit 0
IEG0
Description
0
Falling edge of IRQ0 pin input is detected
1
Rising edge of IRQ0 pin input is detected
Rev. 6.00 Aug 04, 2006 page 98 of 680
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(initial value)
Section 3 Exception Handling
2. Interrupt Enable Register 1 (IENR1)
Bit
7
6
5
4
3
2
1
0
IENTA
IENS1
IENWP
IEN4
IEN3
IEN2
IEN1
IEN0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IENR1 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Timer A interrupt enable (IENTA)
Bit 7 enables or disables timer A overflow interrupt requests.
Bit 7
IENTA
Description
0
Disables timer A interrupt requests
1
Enables timer A interrupt requests
(initial value)
Bit 6: SCI1 interrupt enable (IENS1)
Bit 6 enables or disables SCI1 transfer complete interrupt requests.
Bit 6
IENS1
Description
0
Disables SCI1 interrupt requests
1
Enables SCI1 interrupt requests
(initial value)
Bit 5: Wakeup interrupt enable (IENWP)
Bit 5 enables or disables WKP7 to WKP0 interrupt requests.
Bit 5
IENWP
Description
0
Disables WKP7 to WKP0 interrupt requests
1
Enables WKP7 to WKP0 interrupt requests
(initial value)
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Section 3 Exception Handling
Bits 4 to 0: IRQ4 to IRQ0 interrupt enable (IEN4 to IEN0)
Bits 4 to 0 enable or disable IRQ4 to IRQ0 interrupt requests.
Bit n
IENn
Description
0
Disables interrupt requests from pin IRQn
1
Enables interrupt requests from pin IRQn
(initial value)
(n = 4 to 0)
3. Interrupt Enable Register 2 (IENR2)
Bit
7
6
5
4
IENDT
IENAD
—
IENTG
3
1
0
IENTC
IENEC
2
IENTFH IENTFL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IENR2 is an 8-bit read/write register that enables or disables interrupt requests.
Bit 7: Direct transfer interrupt enable (IENDT)
Bit 7 enables or disables direct transfer interrupt requests.
Bit 7
IENDT
Description
0
Disables direct transfer interrupt requests
1
Enables direct transfer interrupt requests
(initial value)
Bit 6: A/D converter interrupt enable (IENAD)
Bit 6 enables or disables A/D converter interrupt requests.
Bit 6
IENAD
Description
0
Disables A/D converter interrupt requests
1
Enables A/D converter interrupt requests
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
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Section 3 Exception Handling
Bit 4: Timer G interrupt enable (IENTG)
Bit 4 enables or disables timer G input capture or overflow interrupt requests.
Bit 4
IENTG
Description
0
Disables timer G interrupt requests
1
Enables timer G interrupt requests
(initial value)
Bit 3: Timer FH interrupt enable (IENTFH)
Bit 3 enables or disables timer FH compare match and overflow interrupt requests.
Bit 3
IENTFH
Description
0
Disables timer FH interrupt requests
1
Enables timer FH interrupt requests
(initial value)
Bit 2: Timer FL interrupt enable (IENTFL)
Bit 2 enables or disables timer FL compare match and overflow interrupt requests.
Bit 2
IENTFL
Description
0
Disables timer FL interrupt requests
1
Enables timer FL interrupt requests
(initial value)
Bit 1: Timer C interrupt enable (IENTC)
Bit 1 enables or disables timer C overflow and underflow interrupt requests.
Bit 1
IENTC
Description
0
Disables timer C interrupt requests
1
Enables timer C interrupt requests
(initial value)
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Section 3 Exception Handling
Bit 0: Asynchronous event counter interrupt enable (IENEC)
Bit 0 enables or disables asynchronous event counter interrupt requests.
Bit 0
IENEC
Description
0
Disables asynchronous event counter interrupt requests
1
Enables asynchronous event counter interrupt requests
(initial value)
For details of SCI3-1 and SCI3-2 interrupt control, see 6. Serial control register 3 (SCR3) in
section 10.3.2.
4. Interrupt Request Register 1 (IRR1)
Bit
7
6
5
4
3
2
1
0
IRRTA
IRRS1
—
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
Initial value
0
0
1
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
—
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note: * Only a write of 0 for flag clearing is possible
IRR1 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a timer A,
SCI1, or IRQ4 to IRQ0 interrupt is requested. The flags are not cleared automatically when an
interrupt is accepted. It is necessary to write 0 to clear each flag.
Bit 7: Timer A interrupt request flag (IRRTA)
Bit 7
IRRTA
Description
0
Clearing condition:
When IRRTA = 1, it is cleared by writing 0
1
Setting condition:
When the timer A counter value overflows from H'FF to H'00
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Section 3 Exception Handling
Bit 6: SCI1 interrupt request flag (IRRS1)
Bit 6
IRRS1
Description
0
Clearing condition:
When IRRS1 = 1, it is cleared by writing 0
1
Setting condition:
When SCI1 completes transfer
(initial value)
Bit 5: Reserved bit
Bit 5 is reserved; it is always read as 1 and cannot be modified.
Bits 4 to 0: IRQ4 to IRQ0 interrupt request flags (IRRI4 to IRRI0)
Bit n
IRRIn
Description
0
Clearing condition:
When IRRIn = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When pin IRQn is designated for interrupt input and the designated
signal edge is input
(n = 4 to 0)
5. Interrupt Request Register 2 (IRR2)
Bit
7
6
5
4
IRRDT
IRRAD
—
IRRTG
Initial value
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/(W)*
R/(W)*
3
1
0
IRRTC
IRREC
0
0
0
R/(W)*
R/(W)*
R/(W)*
2
IRRTFH IRRTFL
Note: * Only a write of 0 for flag clearing is possible
IRR2 is an 8-bit read/write register, in which a corresponding flag is set to 1 when a direct
transfer, A/D converter, Timer G, Timer FH, Timer FC, or Timer C interrupt is requested. The
flags are not cleared automatically when an interrupt is accepted. It is necessary to write 0 to clear
each flag.
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Section 3 Exception Handling
Bit 7: Direct transfer interrupt request flag (IRRDT)
Bit 7
IRRDT
Description
0
Clearing condition:
When IRRDT = 1, it is cleared by writing 0
1
Setting condition:
When a direct transfer is made by executing a SLEEP instruction
while DTON = 1 in SYSCR2
(initial value)
Bit 6: A/D converter interrupt request flag (IRRAD)
Bit 6
IRRAD
Description
0
Clearing condition:
When IRRAD = 1, it is cleared by writing 0
1
Setting condition:
When A/D conversion is completed and ADSF is cleared to 0 in ADSR
(initial value)
Bit 5: Reserved bit
Bit 5 is a readable/writable reserved bit. It is initialized to 0 by a reset.
Bit 4: Timer G interrupt request flag (IRRTG)
Bit 4
IRRTG
Description
0
Clearing condition:
When IRRTG = 1, it is cleared by writing 0
1
Setting condition:
When the TMIG pin is designated for TMIG input and the designated signal edge is
input, and when TCG overflows while OVIE is set to 1 in TMG
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Section 3 Exception Handling
Bit 3: Timer FH interrupt request flag (IRRTFH)
Bit 3
IRRTFH
Description
0
Clearing condition:
When IRRTFH = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When TCFH and OCRFH match in 8-bit timer mode, or when TCF (TCFL, TCFH)
and OCRF (OCRFL, OCRFH) match in 16-bit timer mode
Bit 2: Timer FL interrupt request flag (IRRTFL)
Bit 2
IRRTFL
Description
0
Clearing condition:
When IRRTFL= 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When TCFL and OCRFL match in 8-bit timer mode
Bit 1: Timer C interrupt request flag (IRRTC)
Bit 1
IRRTC
Description
0
Clearing condition:
When IRRTC= 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When the timer C counter value overflows (from H'FF to H'00) or underflows
(from H'00 to H'FF)
Bit 0: Asynchronous event counter interrupt request flag (IRREC)
Bit 0
IRREC
Description
0
Clearing condition:
When IRREC = 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When ECH overflows in 16-bit counter mode, or ECH or ECL overflows in 8-bit
counter mode
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Section 3 Exception Handling
6. Wakeup Interrupt Request Register (IWPR)
Bit
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Note:
*
All bits can only be written with 0, for flag clearing.
IWPR is an 8-bit read/write register containing wakeup interrupt request flags. When one of pins
WKP7 to WKP0 is designated for wakeup input and a rising or falling edge is input at that pin, the
corresponding flag in IWPR is set to 1. A flag is not cleared automatically when the
corresponding interrupt is accepted. Flags must be cleared by writing 0.
Bits 7 to 0: Wakeup interrupt request flags (IWPF7 to IWPF0)
Bit n
IWPFn
Description
0
Clearing condition:
When IWPFn= 1, it is cleared by writing 0
(initial value)
1
Setting condition:
When pin WKPn is designated for wakeup input and a rising or falling edge is input
at that pin
(n = 7 to 0)
7. Wakeup Edge Select Register (WEGR)
Bit
7
6
5
4
3
2
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WEGR is an 8-bit read/write register that specifies rising or falling edge sensing for pins WKPn.
WEGR is initialized to H'00 by a reset.
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Section 3 Exception Handling
Bit n: WKPn edge select (WKEGSn)
Bit n selects WKPn pin input sensing.
Bit n
WKEGSn
Description
0
WKPn pin falling edge detected
1
WKPn pin rising edge detected
(initial value)
(n = 7 to 0)
3.3.3
External Interrupts
There are 13 external interrupts: IRQ4 to IRQ0 and WKP7 to WKP0.
1. Interrupts WKP7 to WKP0
Interrupts WKP7 to WKP0 are requested by either rising or falling edge input to pins WKP7 to
WKP0. When these pins are designated as pins WKP7 to WKP0 in port mode register 5 and a
rising or falling edge is input, the corresponding bit in IWPR is set to 1, requesting an interrupt.
Recognition of wakeup interrupt requests can be disabled by clearing the IENWP bit to 0 in
IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When WKP7 to WKP0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
number 9 is assigned to interrupts WKP7 to WKP0. All eight interrupt sources have the same
vector number, so the interrupt-handling routine must discriminate the interrupt source.
2. Interrupts IRQ4 to IRQ0
Interrupts IRQ4 to IRQ0 are requested by input signals to pins IRQ4 to IRQ0. These interrupts are
detected by either rising edge sensing or falling edge sensing, depending on the settings of bits
IEG4 to IEG0 in IEGR.
When these pins are designated as pins IRQ4 to IRQ0 in port mode register 3 and 1 and the
designated edge is input, the corresponding bit in IRR1 is set to 1, requesting an interrupt.
Recognition of these interrupt requests can be disabled individually by clearing bits IEN4 to IEN0
to 0 in IENR1. These interrupts can all be masked by setting the I bit to 1 in CCR.
When IRQ4 to IRQ0 interrupt exception handling is initiated, the I bit is set to 1 in CCR. Vector
numbers 8 to 4 are assigned to interrupts IRQ4 to IRQ0. The order of priority is from IRQ0 (high)
to IRQ4 (low). Table 3.2 gives details.
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Section 3 Exception Handling
3.3.4
Internal Interrupts
There are 24 internal interrupts that can be requested by the on-chip peripheral modules. When a
peripheral module requests an interrupt, the corresponding bit in IRR1 or IRR2 is set to 1.
Recognition of individual interrupt requests can be disabled by clearing the corresponding bit in
IENR1 or IENR2. All these interrupts can be masked by setting the I bit to 1 in CCR. When
internal interrupt handling is initiated, the I bit is set to 1 in CCR. Vector numbers from 20 to 10
are assigned to these interrupts. Table 3.2 shows the order of priority of interrupts from on-chip
peripheral modules.
3.3.5
Interrupt Operations
Interrupts are controlled by an interrupt controller. Figure 3.2 shows a block diagram of the
interrupt controller. Figure 3.3 shows the flow up to interrupt acceptance.
Priority decision logic
Interrupt controller
External or
internal
interrupts
Interrupt
request
External
interrupts or
internal
interrupt
enable
signals
I
CCR (CPU)
Figure 3.2 Block Diagram of Interrupt Controller
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Section 3 Exception Handling
Interrupt operation is described as follows.
• When an interrupt condition is met while the interrupt enable register bit is set to 1, an
interrupt request signal is sent to the interrupt controller.
• When the interrupt controller receives an interrupt request, it sets the interrupt request flag.
• From among the interrupts with interrupt request flags set to 1, the interrupt controller selects
the interrupt request with the highest priority and holds the others pending. (Refer to table 3.2
for a list of interrupt priorities.)
• The interrupt controller checks the I bit of CCR. If the I bit is 0, the selected interrupt request
is accepted; if the I bit is 1, the interrupt request is held pending.
• If the interrupt is accepted, after processing of the current instruction is completed, both PC
and CCR are pushed onto the stack. The state of the stack at this time is shown in figure 3.4.
The PC value pushed onto the stack is the address of the first instruction to be executed upon
return from interrupt handling.
• The I bit of CCR is set to 1, masking further interrupts.
• The vector address corresponding to the accepted interrupt is generated, and the interrupt
handling routine located at the address indicated by the contents of the vector address is
executed.
Notes: 1. When disabling interrupts by clearing bits in an interrupt enable register, or when
clearing bits in an interrupt request register, always do so while interrupts are masked
(I = 1).
2. If the above clear operations are performed while I = 0, and as a result a conflict arises
between the clear instruction and an interrupt request, exception processing for the
interrupt will be executed after the clear instruction has been executed.
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Section 3 Exception Handling
Program execution state
IRRI0 = 1
No
Yes
IEN0 = 1
No
Yes
IRRI1 = 1
No
Yes
IEN1 = 1
Yes
No
IRRI2 = 1
No
Yes
IEN2 = 1
No
Yes
IRRDT = 1
No
Yes
IENDT = 1
Yes
No
I=0
Yes
PC contents saved
CCR contents saved
I←1
Branch to interrupt
handling routine
Legend:
PC: Program counter
CCR: Condition code register
I:
I bit of CCR
Figure 3.3 Flow Up to Interrupt Acceptance
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No
Section 3 Exception Handling
SP – 4
SP (R7)
CCR
SP – 3
SP + 1
CCR *
SP – 2
SP + 2
PCH
SP – 1
SP + 3
PCL
SP (R7)
SP + 4
Even address
Stack area
Prior to start of interrupt
exception handling
PC and CCR
saved to stack
After completion of interrupt
exception handling
Legend:
PCH: Upper 8 bits of program counter (PC)
PCL:
Lower 8 bits of program counter (PC)
CCR: Condition code register
Stack pointer
SP:
Notes: 1. PC shows the address of the first instruction to be executed upon
return from the interrupt handling routine.
2. Register contents must always be saved and restored by word access,
starting from an even-numbered address.
* Ignored on return.
Figure 3.4 Stack State after Completion of Interrupt Exception Handling
Figure 3.5 shows a typical interrupt sequence.
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Internal data bus
(16 bits)
Internal write
signal
Internal read
signal
Internal
address bus
φ
Interrupt
request signal
Figure 3.5 Interrupt Sequence
(4)
Instruction
prefetch
(3)
Internal
processing
(5)
(1)
Stack access
(6)
(7)
(9)
Vector fetch
(8)
(10)
(9)
Prefetch instruction of
Internal
interrupt-handling routine
processing
(1) Instruction prefetch address (Instruction is not executed. Address is saved as PC contents, becoming return address.)
(2)(4) Instruction code (not executed)
(3) Instruction prefetch address (Instruction is not executed.)
(5) SP – 2
(6) SP – 4
(7) CCR
(8) Vector address
(9) Starting address of interrupt-handling routine (contents of vector)
(10) First instruction of interrupt-handling routine
(2)
(1)
Interrupt level
decision and wait for
end of instruction
Interrupt is
accepted
Section 3 Exception Handling
Section 3 Exception Handling
3.3.6
Interrupt Response Time
Table 3.4 shows the number of wait states after an interrupt request flag is set until the first
instruction of the interrupt handler is executed.
Table 3.4
Interrupt Wait States
Item
States
Total
Waiting time for completion of executing instruction*
1 to 13
15 to 27
Saving of PC and CCR to stack
4
Vector fetch
2
Instruction fetch
4
Internal processing
4
Note:
*
Not including EEPMOV instruction.
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Section 3 Exception Handling
3.4
Application Notes
3.4.1
Notes on Stack Area Use
When word data is accessed in the H8/3847R Group, the least significant bit of the address is
regarded as 0. Access to the stack always takes place in word size, so the stack pointer (SP: R7)
should never indicate an odd address. Use PUSH Rn (MOV.W Rn, @–SP) or POP Rn (MOV.W
@SP+, Rn) to save or restore register values.
Setting an odd address in SP may cause a program to crash. An example is shown in figure 3.6.
SP→
PCH
PC L
SP→
R1L
PC L
SP→
H'FEFC
H'FEFD
H'FEFF
BSR instruction
SP set to H'FEFF
MOV. B R1L, @−R7
Stack accessed beyond SP
Contents of PCH are lost
Legend:
PCH: Upper byte of program counter
PCL: Lower byte of program counter
R1L: General register R1L
SP: Stack pointer
Figure 3.6 Operation when Odd Address is Set in SP
When CCR contents are saved to the stack during interrupt exception handling or restored when
RTE is executed, this also takes place in word size. Both the upper and lower bytes of word data
are saved to the stack; on return, the even address contents are restored to CCR while the odd
address contents are ignored.
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Section 3 Exception Handling
3.4.2
Notes on Rewriting Port Mode Registers
When a port mode register is rewritten to switch the functions of external interrupt pins, the
following points should be observed.
When an external interrupt pin function is switched by rewriting the port mode register that
controls pins IRQ4 to IRQ0, WKP7 to WKP0, the interrupt request flag may be set to 1 at the time
the pin function is switched, even if no valid interrupt is input at the pin. Be sure to clear the
interrupt request flag to 0 after switching pin functions. Table 3.5 shows the conditions under
which interrupt request flags are set to 1 in this way.
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Section 3 Exception Handling
Table 3.5
Conditions Under which Interrupt Request Flag is Set to 1
Interrupt Request
Flags Set to 1
IRR1
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Conditions
When PMR1 bit IRQ4 is changed from 0 to 1 while pin IRQ4 is low and IEGR
bit IEG4 = 0.
When PMR1 bit IRQ4 is changed from 1 to 0 while pin IRQ4 is low and IEGR
bit IEG4 = 1.
When PMR1 bit IRQ3 is changed from 0 to 1 while pin IRQ3 is low and IEGR
bit IEG3 = 0.
When PMR1 bit IRQ3 is changed from 1 to 0 while pin IRQ3 is low and IEGR
bit IEG3 = 1.
When PMR1 bit IRQ2 is changed from 0 to 1 while pin IRQ2 is low and IEGR
bit IEG2 = 0.
When PMR1 bit IRQ2 is changed from 1 to 0 while pin IRQ2 is low and IEGR
bit IEG2 = 1.
When PMR1 bit IRQ1 is changed from 0 to 1 while pin IRQ1 is low and IEGR
bit IEG1 = 0.
When PMR1 bit IRQ1 is changed from 1 to 0 while pin IRQ1 is low and IEGR
bit IEG1 = 1.
When PMR3 bit IRQ0 is changed from 0 to 1 while pin IRQ0 is low and IEGR
bit IEG0 = 0.
When PMR3 bit IRQ0 is changed from 1 to 0 while pin IRQ0 is low and IEGR
bit IEG0 = 1.
When PMR5 bit WKP7 is changed from 0 to 1 while pin WKP7 is low.
When PMR5 bit WKP6 is changed from 0 to 1 while pin WKP6 is low.
When PMR5 bit WKP5 is changed from 0 to 1 while pin WKP5 is low.
When PMR5 bit WKP4 is changed from 0 to 1 while pin WKP4 is low.
When PMR5 bit WKP3 is changed from 0 to 1 while pin WKP3 is low.
When PMR5 bit WKP2 is changed from 0 to 1 while pin WKP2 is low.
When PMR5 bit WKP1 is changed from 0 to 1 while pin WKP1 is low.
When PMR5 bit WKP0 is changed from 0 to 1 while pin WKP0 is low.
Figure 3.7 shows the procedure for setting a bit in a port mode register and clearing the interrupt
request flag.
When switching a pin function, mask the interrupt before setting the bit in the port mode register.
After accessing the port mode register, execute at least one instruction (e.g., NOP), then clear the
interrupt request flag from 1 to 0. If the instruction to clear the flag is executed immediately after
the port mode register access without executing an intervening instruction, the flag will not be
cleared.
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Section 3 Exception Handling
An alternative method is to avoid the setting of interrupt request flags when pin functions are
switched by keeping the pins at the high level so that the conditions in table 3.5 do not occur.
CCR I bit←1
Interrupts masked. (Another possibility
is to disable the relevant interrupt in
interrupt enable register 1.)
Set port mode register bit
Execute NOP instruction
After setting the port mode register bit,
first execute at least one instruction
(e.g., NOP), then clear the interrupt
request flag to 0
Clear interrupt request flag to 0
CCR I bit←0
Interrupt mask cleared
Figure 3.7 Port Mode Register Setting and Interrupt Request Flag
Clearing Procedure
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Section 3 Exception Handling
3.4.3
Method for Clearing Interrupt Request Flags
Use the recommended method, given below when clearing the flags of interrupt request registers
(IRR1, IRR2, IWPR).
• Recommended method
Use a single instruction to clear flags. The bit control instruction and byte-size data transfer
instruction can be used. Two examples of program code for clearing IRRI1 (bit 1 of IRR1) are
given below.
BCLR
#1,
@IRR1:8
MOV.B R1L, @IRR1:8 (set the value of R1L to B'11111101)
• Example of a malfunction
When flags are cleared with multiple instructions, other flags might be cleared during
execution of the instructions, even though they are currently set, and this will cause a
malfunction.
Here is an example in which IRRI0 is cleared and disabled in the process of clearing IRRI1
(bit 1 of IRR1).
MOV.B @IRR1:8,R1L ......... IRRI0 = 0 at this time
AND.B #B'11111101,R1L ..... Here, IRRI0 = 1
MOV.B R1L,@IRR1:8 ......... IRRI0 is cleared to 0
In the above example, it is assumed that an IRQ0 interrupt is generated while the AND.B
instruction is executing.
The IRQ0 interrupt is disabled because, although the original objective is clearing IRRI1,
IRRI0 is also cleared.
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Section 4 Clock Pulse Generators
Section 4 Clock Pulse Generators
4.1
Overview
Clock oscillator circuitry (CPG: clock pulse generator) is provided on-chip, including both a
system clock pulse generator and a subclock pulse generator. The system clock pulse generator
consists of a system clock oscillator and system clock dividers. The subclock pulse generator
consists of a subclock oscillator circuit and a subclock divider.
4.1.1
Block Diagram
Figure 4.1 shows a block diagram of the clock pulse generators.
OSC 1
OSC 2
System clock
oscillator
φ OSC
(f OSC)
φ OSC/2
System clock
divider (1/2)
System
clock
divider
φOSC/128
φOSC/64
φOSC/32
φOSC/16
φ
Prescaler S
(13 bits)
System clock pulse generator
EXCL*
X1
X2
Subclock
oscillator
φW
(f W )
Subclock
divider
(1/2, 1/4, 1/8)
φ W /2
φ W/4
φ W /8
Subclock pulse generator
φ/2
to
φ/8192
φW
φ SUB
Prescaler W
(5 bits)
φW /2
φW /4
φW /8
to
φW /128
Note: * H8/38347 Group and H8/38447 Group only.
Figure 4.1 Block Diagram of Clock Pulse Generators
4.1.2
System Clock and Subclock
The basic clock signals that drive the CPU and on-chip peripheral modules are φ and φSUB. Four
of the clock signals have names: φ is the system clock, φSUB is the subclock, φOSC is the oscillator
clock, and φW is the watch clock.
The clock signals available for use by peripheral modules are φ/2, φ/4, φ/8, φ/16, φ/32, φ/64,
φ/128, φ/256, φ/512, φ/1024, φ/2048, φ/4096, φ/8192, φW, φW/2, φW/4, φW/8, φW/16, φW/32, φW/64,
and φW/128. The clock requirements differ from one module to another.
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Section 4 Clock Pulse Generators
4.2
System Clock Generator
Clock pulses can be supplied to the system clock divider either by connecting a crystal or ceramic
oscillator, or by providing external clock input.
1. Connecting a Crystal Oscillator
Figure 4.2 shows a typical method of connecting a crystal oscillator. For information on
recommended resonators, see the product AC characteristics listed in section 15, Electrical
Characteristics. Please consult with the resonator manufacturer when selecting a resonator model.
C1
OSC 1
R f = 1 MΩ ±20%
Rf
OSC 2
C2
Figure 4.2 Typical Connection to Crystal Oscillator
2. Connecting a Ceramic Oscillator
Figure 4.3 shows a typical method of connecting a ceramic oscillator. For information on
recommended resonators, see the product AC characteristics listed in section 15, Electrical
Characteristics. Please consult with the resonator manufacturer when selecting a resonator model.
C1
OSC 1
R f = 1 MΩ ±20%
Rf
OSC 2
C2
Figure 4.3 Typical Connection to Ceramic Oscillator
3. Notes on Board Design
When generating clock pulses by connecting a crystal or ceramic oscillator, pay careful attention
to the following points.
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Section 4 Clock Pulse Generators
Avoid running signal lines close to the oscillator circuit, since the oscillator may be adversely
affected by induction currents. (See figure 4.4.)
The board should be designed so that the oscillator and load capacitors are located as close as
possible to pins OSC1 and OSC2.
To be avoided
Signal A Signal B
C1
OSC 1
OSC 2
C2
Figure 4.4 Board Design of Oscillator Circuit
4. External Clock Input Method
Connect an external clock signal to pin OSC1, and leave pin OSC2 open. Figure 4.5 shows a
typical connection.
OSC 1
OSC 2
External clock input
Open
Figure 4.5 External Clock Input (Example)
Frequency
Oscillator Clock (φ
φOSC)
Duty cycle
45% to 55%
Note: The circuit parameters above are recommended by the crystal or ceramic oscillator
manufacturer.
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Section 4 Clock Pulse Generators
The circuit parameters are affected by the crystal or ceramic oscillator and floating
capacitance when designing the board. When using the oscillator, consult with the crystal
or ceramic oscillator manufacturer to determine the circuit parameters.
4.3
Subclock Generator
1. Connecting a 32.768 kHz/38.4 kHz Crystal Oscillator
Clock pulses can be supplied to the subclock divider by connecting a 32.768 kHz/38.4 kHz crystal
oscillator, as shown in figure 4.6. Follow the same precautions as noted under 3. notes on board
design for the system clock in section 4.2.
C1
X1
X2
C1 = C 2 = 15 pF (typ.)
C2
Note: Circuit constants should be determined in consultation
with the resonator manufacturer.
Oscillation frequency
Manufacturer
Products Name
38.4 kHz
Seiko Instrument Inc.
VTC-200
32.768 kHz
Nihon Denpa Kogyo
MX73P
Figure 4.6 Typical Connection to 32.768 kHz/38.4 kHz Crystal Oscillator (Subclock)
Figure 4.7 shows the equivalent circuit of the 32.768 kHz/38.4 kHz crystal oscillator.
CS
LS
RS
X1
X2
C0
C0 = 1.5 pF typ
RS = 14 k Ω typ
f W = 32.768 kHz/38.4kHz
Figure 4.7 Equivalent Circuit of 32.768 kHz/38.4 kHz Crystal Oscillator
Rev. 6.00 Aug 04, 2006 page 122 of 680
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Section 4 Clock Pulse Generators
2. Pin Connection when Not Using Subclock
When the subclock is not used, connect pin X1 to GND and leave pin X2 open, as shown in figure
4.8.
X1
GND
X2
Open
Figure 4.8 Pin Connection when not Using Subclock
3. External Clock Input
• H8/3847R Group and H8/3847S Group
Connect the external clock to the X1 pin and leave the X2 pin open, as shown in figure 4.9 (a).
X1
X2
External clock input
Open
Figure 4.9 (a) Pin Connection when Inputting External Clock
(H8/38347R Group and H8/3847S Group)
Frequency
Subclock (φ
φw)
Duty
45% to 55%
Rev. 6.00 Aug 04, 2006 page 123 of 680
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Section 4 Clock Pulse Generators
• H8/38347 Group and H8/38447 Group
Connect pin X1 to GND and leave pin X2 open. Input an external clock to pin EXCL. Set bit
EXCL in register PMR2 to 1 to supply the external clock to the internal components of the device.
A connection example is shown in figure 4.9 (b).
X1
GND
X2
Open
P31/UD/EXCL
External clock input
Figure 4.9 (b) Pin Connection when Inputting External Clock
(H8/38347 Group and H8/38447 Group)
Frequency
Subclock (φ
φw)
Duty
45% to 55%
4. Notes on H8/38347 and H8/38447
In the H8/38347 and H8/38447 the subclock oscillator input pin is controlled by the EXCL bit in
the PMR2 register. When EXCL is cleared to 0 the X1 pin (resonator connection only) is used,
and when EXCL is set to 1 the EXCL pin (external clock only) is used. Caution is necessary when
switching from the H8/3847R to a program. Writing 1 to bit 7 in PMR2 (empty bit with initial
value 1 on H8/3847R) selects EXCL as the input pin, so no subclock is supplied internally even if
a resonator is connected. Furthermore, P31 becomes unusable. To prevent this it is necessary to
change the program so that 0 is written to the EXCL bit.
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Section 4 Clock Pulse Generators
4.4
Prescalers
The H8/3847R Group is equipped with two on-chip prescalers having different input clocks
(prescaler S and prescaler W). Prescaler S is a 13-bit counter using the system clock (φ) as its
input clock. Its prescaled outputs provide internal clock signals for on-chip peripheral modules.
Prescaler W is a 5-bit counter using a 32.768 kHz or 38.4 kHz signal divided by 4 (φW/4) as its
input clock. Its prescaled outputs are used by timer A as a time base for timekeeping.
1. Prescaler S (PSS)
Prescaler S is a 13-bit counter using the system clock (φ) as its input clock. It is incremented once
per clock period.
Prescaler S is initialized to H'0000 by a reset, and starts counting on exit from the reset state.
In standby mode, watch mode, subactive mode, and subsleep mode, the system clock pulse
generator stops. Prescaler S also stops and is initialized to H'0000.
The CPU cannot read or write prescaler S.
The output from prescaler S is shared by timer A, timer C, timer F, timer G, SCI1, SCI3-1, SC3-2,
the A/D converter, the LCD controller, the watchdog timer, and the 14-bit PWM. The divider
ratio can be set separately for each on-chip peripheral function.
In active (medium-speed) mode the clock input to prescaler S is φosc/16, φosc/32, φosc/64, or
φosc/128.
2. Prescaler W (PSW)
Prescaler W is a 5-bit counter using a 32.768 kHz/38.4 kHz signal divided by 4 (φW/4) as its input
clock.
Prescaler W is initialized to H'00 by a reset, and starts counting on exit from the reset state.
Even in standby mode, watch mode, subactive mode, or subsleep mode, prescaler W continues
functioning so long as clock signals are supplied to pins X1 and X2.
Prescaler W can be reset by setting 1s in bits TMA3 and TMA2 of timer mode register A (TMA).
Output from prescaler W can be used to drive timer A, in which case timer A functions as a time
base for timekeeping.
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Section 4 Clock Pulse Generators
4.5
Note on Oscillators
Oscillator characteristics are closely related to board design and should be carefully evaluated by
the user in mask ROM, ZTAT™ and F-ZTAT™ versions, referring to the examples shown in this
section. Oscillator circuit constants will differ depending on the oscillator element, stray
capacitance in its interconnecting circuit, and other factors. Suitable constants should be
determined in consultation with the oscillator element manufacturer. Design the circuit so that the
oscillator element never receives voltages exceeding its maximum rating.
TEST
OSC1
OSC2
Vss
X2
X1
P17
(Vss)
Figure 4.10 Example of Crystal and Ceramic Oscillator Element Arrangement
Figure 4.11 (1) shows an example measuring circuit with the negative resistance suggested by the
oscillator manufacturer. Note that if the negative resistance of the circuit is less than that suggested
by the oscillator manufacturer, it may be difficult to start the main oscillator.
If it is determined that oscillation is not occurring because the negative resistance is lower than the
level suggested by the oscillator manufacturer, the circuit may be modified as shown in figure 4.11
(2) through (4). Which of the modification suggestions to use and the capacitor capacitance should
be decided based upon an evaluation of factors such as the negative resistance and the frequency
deviation.
Rev. 6.00 Aug 04, 2006 page 126 of 680
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Section 4 Clock Pulse Generators
Modification
point
OSC1
OSC1
C1
C1
Rf
Rf
OSC2
OSC2
C2
C2
Negative resistance,
addition of −R
(1) Negative Resistance Measuring Circuit
(2) Oscillator Circuit Modification Suggestion 1
Modification
point
Modification
point
C3
OSC1
C1
OSC1
C1
Rf
C2
Rf
OSC2
OSC2
(3) Oscillator Circuit Modification Suggestion 2
C2
(4) Oscillator Circuit Modification Suggestion 3
Figure 4.11 Negative Resistance Measurement and Circuit Modification Suggestions
4.5.1
Definition of Oscillation Stabilization Wait Time
Figure 4.12 shows the oscillation waveform (OSC2), system clock (φ), and microcomputer
operating mode when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator.
As shown in figure 4.12, as the system clock oscillator is halted in standby mode, watch mode,
and subactive mode, when a transition is made to active (high-speed/medium-speed) mode, the
sum of the following two times (oscillation stabilization time and wait time) is required.
Rev. 6.00 Aug 04, 2006 page 127 of 680
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Section 4 Clock Pulse Generators
1. Oscillation Stabilization Time (trc)
The time from the point at which the system clock oscillator oscillation waveform starts to change
when an interrupt is generated, until the amplitude of the oscillation waveform increases and the
oscillation frequency stabilizes.
2. Wait Time
The time required for the CPU and peripheral functions to begin operating after the oscillation
waveform frequency and system clock have stabilized.
The wait time setting is selected with standby timer select bits 2 to 0 (STS2 to STS0) (bits 6 to 4 in
system control register 1 (SYSCR1)).
Oscillation
waveform
(OSC2)
System clock
(φ)
Oscillation
stabilization
time
Wait time
Operating
mode
Standby mode,
watch mode,
or subactive
mode
Oscillation stabilization wait time
Active (high-speed) mode or
active (medium-speed) mode
Interrupt accepted
Figure 4.12 Oscillation Stabilization Wait Time
When standby mode, watch mode, or subactive mode is cleared by an interrupt or reset, and a
transition is made to active (high-speed/medium-speed) mode, the oscillation waveform begins to
change at the point at which the interrupt is accepted. Therefore, when an oscillator element is
connected in standby mode, watch mode, or subactive mode, since the system clock oscillator is
halted, the time from the point at which this oscillation waveform starts to change until the
Rev. 6.00 Aug 04, 2006 page 128 of 680
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Section 4 Clock Pulse Generators
amplitude of the oscillation waveform increases and the oscillation frequency stabilizes—that is,
the oscillation stabilization time—is required.
The oscillation stabilization time in the case of these state transitions is the same as the oscillation
stabilization time at power-on (the time from the point at which the power supply voltage reaches
the prescribed level until the oscillation stabilizes), specified by "oscillation stabilization time trc"
in the AC characteristics.
Meanwhile, once the system clock has halted, a wait time of at least 8 states is necessary in order
for the CPU and peripheral functions to operate normally.
Thus, the time required from interrupt generation until operation of the CPU and peripheral
functions is the sum of the above described oscillation stabilization time and wait time. This total
time is called the oscillation stabilization wait time, and is expressed by equation (1) below.
Oscillation stabilization wait time = oscillation stabilization time + wait time
= trc + (8 to 131,072 states) ................. (1)
Therefore, when a transition is made from standby mode, watch mode, or subactive mode, to
active (high-speed/medium-speed) mode, with an oscillator element connected to the system clock
oscillator, careful evaluation must be carried out on the installation circuit before deciding on the
oscillation stabilization wait time. In particular, since the oscillation stabilization time is affected
by installation circuit constants, stray capacitance, and so forth, suitable constants should be
determined in consultation with the oscillator element manufacturer.
4.5.2
Notes on Use of Crystal Oscillator Element (Excluding Ceramic Oscillator
Element)
When a microcomputer operates, the internal power supply potential fluctuates slightly in
synchronization with the system clock. Depending on the individual crystal oscillator element
characteristics, the oscillation waveform amplitude may not be sufficiently large immediately after
the oscillation stabilization wait time, making the oscillation waveform susceptible to influence by
fluctuations in the power supply potential. In this state, the oscillation waveform may be
disrupted, leading to an unstable system clock and erroneous operation of the microcomputer.
If erroneous operation occurs, change the setting of standby timer select bits 2 to 0 (STS2 to
STS0) (bits 6 to 4 in system control register 1 (SYSCR1)) to give a longer wait time.
For example, if erroneous operation occurs with a wait time setting of 16 states, check the
operation with a wait time setting of 8,192 states or more.
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Section 4 Clock Pulse Generators
If the same kind of erroneous operation occurs after a reset as after a state transition, hold the RES
pin low for a longer period.
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Section 5 Power-Down Modes
Section 5 Power-Down Modes
5.1
Overview
This LSI has nine modes of operation after a reset. These include eight power-down modes, in
which power dissipation is significantly reduced. Table 5.1 gives a summary of the nine operating
modes.
Table 5.1
Operating Modes
Operating Mode
Description
Active (high-speed) mode
The CPU and all on-chip peripheral functions are operable on the
system clock in high-speed operation
Active (medium-speed) mode
The CPU and all on-chip peripheral functions are operable on the
system clock in low-speed operation
Subactive mode
The CPU is operable on the subclock in low-speed operation
Sleep (high-speed) mode
The CPU halts. On-chip peripheral functions are operable on the
system clock
Sleep (medium-speed) mode
The CPU halts. On-chip peripheral functions operate at a
frequency of 1/64, 1/32, 1/16, or 1/8 of the system clock frequency
Subsleep mode
The CPU halts. The time-base function of timer A, timer C, timer
G, timer F, WDT, SCI1, SCI3-1, SCI3-2, AEC, and LCD
controller/driver are operable on the subclock.
Watch mode
The CPU halts. The time-base function of timer A, timer F, timer
G, AEC, and LCD controller/driver are operable on the subclock.
Standby mode
The CPU and all on-chip peripheral functions halt
Module standby mode
Individual on-chip peripheral functions specified by software enter
standby mode and halt
Of these nine operating modes, all but the active (high-speed) mode are power-down modes. In
this section the two active modes (high-speed and medium speed) will be referred to collectively
as active mode.
Figure 5.1 shows the transitions among these operation modes. Table 5.2 indicates the internal
states in each mode.
Rev. 6.00 Aug 04, 2006 page 131 of 680
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Section 5 Power-Down Modes
Program
execution state
Reset state
SLEEP
instruction(a)
Active
(high-speed)
mode
P (d)
EE
SL uction
tr
ins
Program
halt state
Program
halt state
)
P (a
EE tion
L
c
S ru
st
inin SL
st E
ru E
ct P
io
n (b
SLEEP
instruction(f)
SL
instr EEP
uctio (d
n )
(4)
)
i
(1)
SLEEP
instruction(e)
(1)
Subactive
mode
SLEEP
instruction(b)
(3)
Sleep
(medium-speed)
mode
ins SLE
tru EP
cti
on (j)
ins SLE
tru EP
ctio
n (i)
)
SLEEP
instruction(i)
P (e
EE tion
L
S ruc
t
ns
SLEEP
instruction(h)
ins SLEE
tru
ctio P
n (e)
Active
(medium-speed)
mode
(1)
Watch
mode
SLEEP
instruction(g)
(4)
Standby
mode
Sleep
(high-speed)
mode
(3)
SLEEP
instruction(c)
(2)
Subsleep
mode
Power-down modes
Mode Transition Conditions (2)
Mode Transition Conditions (1)
LSON MSON SSBY TMA3 DTON
(a)
(b)
(c)
(d)
(e)
(f)
(g)
(h)
(i)
(J)
0
0
1
0
*
0
0
0
1
0
0
1
*
*
*
0
1
1
*
0
0
0
0
1
1
0
0
1
1
1
*
*
1
0
1
*
*
1
1
1
0
0
0
0
0
1
1
1
1
1
Interrupt Sources
(2)
Timer A, Timer F, Timer G interrupt, IRQ0 interrupt,
WKP7 to WKP0 interrupt
Timer A, Timer C, Timer F, Timer G, SCI1, SCI3-1,
SCI3-2 interrupt, IRQ4 to IRQ0 interrupts,
WKP7 to WKP0 interrupts, AEC
(3)
All interrupts
(4)
IRQ1 or IRQ0 interrupt, WKP7 to WKP0 interrupts
(1)
* Don't care
Notes: 1. A transition between different modes cannot be made to occur simply because an interrupt
request is generated. Make sure that interrupt handling is performed after the interrupt is
accepted.
2. Details on the mode transition conditions are given in the explanations of each mode,
in sections 5.2 to 5.9.
Figure 5.1 Mode Transition Diagram
Rev. 6.00 Aug 04, 2006 page 132 of 680
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Section 5 Power-Down Modes
Table 5.2
Internal State in Each Operating Mode
Active Mode
Sleep Mode
Function
HighSpeed
MediumSpeed
HighSpeed
MediumSpeed
Watch
Mode
Subactive
Mode
Subsleep
Mode
Standby
Mode
System clock oscillator
Functions
Functions
Functions
Functions
Halted
Halted
Halted
Halted
Subclock oscillator
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
CPU
Functions
Functions
Halted
Halted
Halted
Functions
Halted
Halted
Retained
Retained
Retained
Retained
Retained
Instructions
operations RAM
Registers
1
Retained*
I/O ports
External
IRQ0
interrupts
IRQ1
Functions
Functions
Functions
Functions
Functions Functions
6
Retained*
Functions
Functions
Retained*6
IRQ2
IRQ3
IRQ4
WKP0
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions
Functions*5 Functions*5 Functions*5 Retained
Functions*8 Functions Functions Functions*8
WKP1
WKP2
WKP3
WKP4
WKP5
WKP6
WKP7
Peripheral Timer A
functions
Asynchronous counter
Timer C
Retained
WDT
Notes:
Functions/ Functions/ Retained
2
2
Retained* Retained*
Functions/ Retained
7
Retained*
Timer G,
Timer F
Functions/ Functions/ Functions/
Retained*9 Retained*2 Retained*2
SCI1
Retained
Functions/ Functions/ Retained
Retained*9 Retained*9
SCI3-1,
SCI3-2
Reset
Functions/ Functions/ Reset
3
3
Retained* Retained*
PWM
Retained
Retained
Retained
Retained
A/D
converter
Retained
Retained
Retained
Retained
LCD
Functions/ Functions/ Functions/ Retained
4
4
4
Retained* Retained* Retained*
1.
2.
3.
4.
5.
6.
7.
8.
9.
Register contents are retained, but output is high-impedance state.
Functions if an external clock or the φW /4 internal clock is selected; otherwise halted and retained.
Functions if φW /2 is selected as the internal clock; otherwise halted and retained.
Functions if φW or φW /2 or φW /4 is selected as the operating clock; otherwise halted and retained.
Functions if the timekeeping time-base function is selected.
External interrupt requests are ignored. Interrupt request register contents are not altered.
Functions if φW /32 is selected as the internal clock; otherwise halted and retained.
Incrementing is possible, but interrupt generation is not.
Functions if the φW /4 internal clock is selected; otherwise halted and retained.
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Section 5 Power-Down Modes
5.1.1
System Control Registers
The operation mode is selected using the system control registers described in table 5.3.
Table 5.3
System Control Registers
Name
Abbreviation
R/W
Initial Value
Address
System control register 1
SYSCR1
R/W
H'07
H'FFF0
System control register 2
SYSCR2
R/W
H'F0
H'FFF1
1. System Control Register 1 (SYSCR1)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SYSCR1 is an 8-bit read/write register for control of the power-down modes.
Upon reset, SYSCR1 is initialized to H'07.
Bit 7: Software standby (SSBY)
This bit designates transition to standby mode or watch mode.
Bit 7
SSBY
Description
0
•
When a SLEEP instruction is executed in active mode,
a transition is made to sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to subsleep mode
•
When a SLEEP instruction is executed in active mode, a transition is made to
standby mode or watch mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to watch mode
1
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REJ09B0145-0600
(initial value)
Section 5 Power-Down Modes
Bits 6 to 4: Standby timer select 2 to 0 (STS2 to STS0)
These bits designate the time the CPU and peripheral modules wait for stable clock operation after
exiting from standby mode or watch mode to active mode due to an interrupt. The designation
should be made according to the operating frequency so that the waiting time is at least equal to
the oscillation settling time.
Bit 6
STS2
Bit 5
STS1
Bit 4
STS0
Description
0
0
0
Wait time = 8,192 states
0
0
1
Wait time = 16,384 states
0
1
0
Wait time = 32,768 states
0
1
1
Wait time = 65,536 states
1
0
0
Wait time = 131,072 states
1
0
1
Wait time = 2 states
1
1
0
Wait time = 8 states
1
1
1
Wait time = 16 states
(initial value)
(External clock input mode)
Note: When inputting the external clock, set the standby timer select to the external clock input
mode. Also, when not using the external clock, do not set the standby timer select to the
external clock input mode.
Bit 3: Low speed on flag (LSON)
This bit chooses the system clock (φ) or subclock (φSUB) as the CPU operating clock when watch
mode is cleared. The resulting operation mode depends on the combination of other control bits
and interrupt input.
Bit 3
LSON
Description
0
The CPU operates on the system clock (φ)
1
The CPU operates on the subclock (φSUB)
(initial value)
Bits 2: Reserved bits
Bit 2 is reserved: it is always read as 1 and cannot be modified.
Rev. 6.00 Aug 04, 2006 page 135 of 680
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Section 5 Power-Down Modes
Bits 1 and 0: Active (medium-speed) mode clock select (MA1, MA0)
Bits 1 and 0 choose φOSC/128, φOSC/64, φOSC/32, or φOSC/16 as the operating clock in active
(medium-speed) mode and sleep (medium-speed) mode. MA1 and MA0 should be written in
active (high-speed) mode or subactive mode.
Bit 1
MA1
Bit 0
MA0
Description
0
0
φOSC/16
0
1
φOSC/32
1
0
φOSC/64
1
1
φOSC/128
(initial value)
2. System Control Register 2 (SYSCR2)
Bit
7
6
5
4
3
2
1
0
—
—
—
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
—
—
—
R/W
R/W
R/W
R/W
R/W
SYSCR2 is an 8-bit read/write register for power-down mode control.
Bits 7 to 5: Reserved bits
These bits are reserved; they are always read as 1, and cannot be modified.
Bit 4: Noise elimination sampling frequency select (NESEL)
This bit selects the frequency at which the watch clock signal (φW) generated by the subclock
pulse generator is sampled, in relation to the oscillator clock (φOSC) generated by the system clock
pulse generator. When φOSC = 2 to 16 MHz, clear NESEL to 0.
Bit 4
NESEL
Description
0
Sampling rate is φOSC/16
1
Sampling rate is φOSC/4
Rev. 6.00 Aug 04, 2006 page 136 of 680
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(initial value)
Section 5 Power-Down Modes
Bit 3: Direct transfer on flag (DTON)
This bit designates whether or not to make direct transitions among active (high-speed), active
(medium-speed) and subactive mode when a SLEEP instruction is executed. The mode to which
the transition is made after the SLEEP instruction is executed depends on a combination of this
and other control bits.
Bit 3
DTON
Description
0
•
When a SLEEP instruction is executed in active mode, a
transition is made to standby mode, watch mode, or sleep mode
•
When a SLEEP instruction is executed in subactive mode, a transition is made
to watch mode or subsleep mode
•
When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
•
When a SLEEP instruction is executed in subactive mode, a direct transition is
made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0, and
MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1, LSON =
0, and MSON = 1
1
(initial value)
Bit 2: Medium speed on flag (MSON)
After standby, watch, or sleep mode is cleared, this bit selects active (high-speed) or active
(medium-speed) mode.
Bit 2
MSON
Description
0
Operation in active (high-speed) mode
1
Operation in active (medium-speed) mode
(initial value)
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Section 5 Power-Down Modes
Bits 1 and 0: Subactive mode clock select (SA1 and SA0)
These bits select the CPU clock rate (φW/2, φW/4, or φW/8) in subactive mode. SA1 and SA0
cannot be modified in subactive mode.
Bit 1
SA1
Bit 0
SA0
Description
0
0
φW /8
0
1
φW /4
1
*
φW /2
Note:
*
(initial value)
Don’t care
5.2
Sleep Mode
5.2.1
Transition to Sleep Mode
1. Transition to Sleep (High-Speed) Mode
The system goes from active mode to sleep (high-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0 and the MSON and DTON
bits in SYSCR2 are also cleared to 0. In sleep mode CPU operation is halted but the on-chip
peripheral functions. CPU register contents are retained.
2. Transition to Sleep (Medium-Speed) Mode
The system goes from active mode to sleep (medium-speed) mode when a SLEEP instruction is
executed while the SSBY and LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2
is set to 1, and the DTON bit in SYSCR2 is cleared to 0. In sleep (medium-speed) mode, as in
sleep (high-speed) mode, CPU operation is halted but the on-chip peripheral functions are
operational. The clock frequency in sleep (medium-speed) mode is determined by the MA1 and
MA0 bits in SYSCR1. CPU register contents are retained.
The CPU may operate at a 1/2 state faster timing at transition to sleep (medium-speed) mode.
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Section 5 Power-Down Modes
5.2.2
Clearing Sleep Mode
Sleep mode is cleared by any interrupt (timer A, timer C, timer F, timer G, asynchronous counter,
IRQ4 to IRQ0, WKP7 to WKP0, SCI1, SCI3-1, SCI3-2, or A/D converter), or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, sleep mode is cleared and interrupt exception handling starts.
A transition is made from sleep (high-speed) mode to active (high-speed) mode, or from sleep
(medium-speed) mode to active (medium-speed) mode. Sleep mode is not cleared if the I bit of
the condition code register (CCR) is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
To synchronize the interrupt request signal with the system clock, up to 2/φ (s) delay may
occur after the interrupt request signal occurrence, before the interrupt exception handling
start.
• Clearing by RES input
When the RES pin goes low, the CPU goes into the reset state and sleep mode is cleared.
5.2.3
Clock Frequency in Sleep (Medium-Speed) Mode
Operation in sleep (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
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Section 5 Power-Down Modes
5.3
Standby Mode
5.3.1
Transition to Standby Mode
The system goes from active mode to standby mode when a SLEEP instruction is executed while
the SSBY bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and bit TMA3 in
TMA is cleared to 0. In standby mode the clock pulse generator stops, so the CPU and on-chip
peripheral modules stop functioning, but as long as the rated voltage is supplied, the contents of
CPU registers, on-chip RAM, and some on-chip peripheral module registers are retained. On-chip
RAM contents will be further retained down to a minimum RAM data retention voltage. The I/O
ports go to the high-impedance state.
5.3.2
Clearing Standby Mode
Standby mode is cleared by an interrupt (IRQ1 or IRQ0), WKP7 to WKP0 or by input at the RES
pin.
• Clearing by interrupt
When an interrupt is requested, the system clock pulse generator starts. After the time set in
bits STS2 to STS0 in SYSCR1 has elapsed, a stable system clock signal is supplied to the
entire chip, standby mode is cleared, and interrupt exception handling starts. Operation
resumes in active (high-speed) mode if MSON = 0 in SYSCR2, or active (medium-speed)
mode if MSON = 1. Standby mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
When the RES pin goes low, the system clock pulse generator starts. After the pulse generator
output has stabilized, if the RES pin is driven high, the CPU starts reset exception handling.
Since system clock signals are supplied to the entire chip as soon as the system clock pulse
generator starts functioning, the RES pin should be kept at the low level until the pulse
generator output stabilizes.
5.3.3
Oscillator Settling Time after Standby Mode is Cleared
Bits STS2 to STS0 in SYSCR1 should be set as follows.
• When a crystal oscillator is used
The table below gives settings for various operating frequencies. Set bits STS2 to STS0 for a
waiting time at least as long as the oscillation settling time.
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Section 5 Power-Down Modes
Table 5.4
Clock Frequency and Settling Time (Times are in ms)
STS2
STS1
STS0
Waiting Time
2 MHz
1 MHz
0
0
0
8,192 states
4.1
8.2
0
0
1
16,384 states
8.2
16.4
0
1
0
32,768 states
16.4
32.8
0
1
1
65,536 states
32.8
65.5
1
0
0
131,072 states
65.5
131.1
1
0
1
2 states (not available)
0.001
0.002
1
1
0
8 states
0.004
0.008
1
1
1
16 states
0.008
0.016
• When an external clock is used
STS2 = 1, STS1 = 0, and STS0 = 1 are recommended. Other values can be set, but with other
settings, operation may start before the standby time is over.
5.3.4
Standby Mode Transition and Pin States
When a SLEEP instruction is executed in active (high-speed) mode or active (medium-speed)
mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in SYSCR1, and bit TMA3 is
cleared to 0 in TMA, a transition is made to standby mode. At the same time, pins go to the highimpedance state (except pins for which the pull-up MOS is designated as on). Figure 5.2 shows
the timing in this case.
φ
Internal data bus
SLEEP instruction fetch
Fetch of next instruction
SLEEP instruction execution
Pins
Internal processing
Port output
High-impedance
Active (high-speed) mode or active (medium-speed) mode
Standby mode
Figure 5.2 Standby Mode Transition and Pin States
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Section 5 Power-Down Modes
5.3.5
Notes on External Input Signal Changes before/after Standby Mode
1. When external input signal changes before/after standby mode or watch mode
When an external input signal such as IRQ or WKP is input, both the high- and low-level
widths of the signal must be at least two cycles of system clock φ or subclock φSUB (referred to
together in this section as the internal clock). As the internal clock stops in standby mode and
watch mode, the width of external input signals requires careful attention when a transition is
made via these operating modes.
2. When external input signals cannot be captured because internal clock stops
The case of falling edge capture is illustrated in figure 5.3
As shown in the case marked "Capture not possible," when an external input signal falls
immediately after a transition to active (high-speed or medium-speed) mode or subactive
mode, after oscillation is started by an interrupt via a different signal, the external input signal
cannot be captured if the high-level width at that point is less than 2 tcyc or 2 tsubcyc.
3. Recommended timing of external input signals
To ensure dependable capture of an external input signal, high- and low-level signal widths of
at least 2 tcyc or 2 tsubcyc are necessary before a transition is made to standby mode or watch
mode, as shown in "Capture possible: case 1."
External input signal capture is also possible with the timing shown in "Capture possible: case
2" and "Capture possible: case 3," in which a 2 tcyc or 2 tsubcyc level width is secured.
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Section 5 Power-Down Modes
Operating
mode
Active (high-speed,
medium-speed) mode
or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
Wait for Active (high-speed,
Standby mode oscillation medium-speed) mode
or watch mode to settle or subactive mode
tcyc
tsubcyc
tcyc
tsubcyc
φ or φSUB
External input signal
Capture possible:
case 1
Capture possible:
case 2
Capture possible:
case 3
Capture not
possible
Interrupt by different
signall
Figure 5.3 External Input Signal Capture when Signal Changes before/after
Standby Mode or Watch Mode
4. Input pins to which these notes apply:
IRQ4 to IRQ0, WKP7 to WKP0, ADTRG, TMIC, TMIF, TMIG
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Section 5 Power-Down Modes
5.4
Watch Mode
5.4.1
Transition to Watch Mode
The system goes from active or subactive mode to watch mode when a SLEEP instruction is
executed while the SSBY bit in SYSCR1 is set to 1 and bit TMA3 in TMA is set to 1.
In watch mode, operation of on-chip peripheral modules is halted except for timer A, timer F,
timer G, AEC, and the LCD controller/driver (for which operation or halting can be set) is halted.
As long as a minimum required voltage is applied, the contents of CPU registers, the on-chip
RAM and some registers of the on-chip peripheral modules, are retained. I/O ports keep the same
states as before the transition.
5.4.2
Clearing Watch Mode
Watch mode is cleared by an interrupt (timer A, timer F, timer G, IRQ0, or WKP7 to WKP0) or by
input at the RES pin.
• Clearing by interrupt
When watch mode is cleared by interrupt, the mode to which a transition is made depends on
the settings of LSON in SYSCR1 and MSON in SYSCR2. If both LSON and MSON are
cleared to 0, transition is to active (high-speed) mode; if LSON = 0 and MSON = 1, transition
is to active (medium-speed) mode; if LSON = 1, transition is to subactive mode. When the
transition is to active mode, after the time set in SYSCR1 bits STS2 to STS0 has elapsed, a
stable clock signal is supplied to the entire chip, watch mode is cleared, and interrupt exception
handling starts. Watch mode is not cleared if the I bit of CCR is set to 1 or the particular
interrupt is disabled in the interrupt enable register.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
5.4.3
Oscillator Settling Time after Watch Mode is Cleared
The waiting time is the same as for standby mode; see section 5.3.3, Oscillator Settling Time after
Standby Mode is Cleared.
5.4.4
Notes on External Input Signal Changes before/after Watch Mode
See section 5.3.5, Notes on External Input Signal Changes before/after Standby Mode.
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Section 5 Power-Down Modes
5.5
Subsleep Mode
5.5.1
Transition to Subsleep Mode
The system goes from subactive mode to subsleep mode when a SLEEP instruction is executed
while the SSBY bit in SYSCR1 is cleared to 0, LSON bit in SYSCR1 is set to 1, and TMA3 bit in
TMA is set to 1. In subsleep mode, operation of on-chip peripheral modules other than the A/D
converter, PWM and WDT is halted. As long as a minimum required voltage is applied, the
contents of CPU registers, the on-chip RAM and some registers of the on-chip peripheral modules
are retained. I/O ports keep the same states as before the transition.
5.5.2
Clearing Subsleep Mode
Subsleep mode is cleared by an interrupt (timer A, timer C, timer F, timer G, asynchronous
counter, SCI1, SCI3-2, SCI3-1, IRQ4 to IRQ0, WKP7 to WKP0) or by a low input at the RES pin.
• Clearing by interrupt
When an interrupt is requested, subsleep mode is cleared and interrupt exception handling
starts. Subsleep mode is not cleared if the I bit of CCR is set to 1 or the particular interrupt is
disabled in the interrupt enable register.
To synchronize the interrupt request signal with the subclock, up to 2/φSUB (s) delay may occur
after the interrupt request signal occurrence, before the interrupt exception handling start.
• Clearing by RES input
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in section
5.3.2, Clearing Standby Mode.
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Section 5 Power-Down Modes
5.6
Subactive Mode
5.6.1
Transition to Subactive Mode
Subactive mode is entered from watch mode if a timer A, timer F, timer G, IRQ0, or WKP7 to
WKP0 interrupt is requested while the LSON bit in SYSCR1 is set to 1. From subsleep mode,
subactive mode is entered if a timer A, timer C, timer F, timer G, asynchronous counter, SCI1,
SCI3-1, SCI3-2, IRQ4 to IRQ0, or WKP7 to WKP0 interrupt is requested. A transition to subactive
mode does not take place if the I bit of CCR is set to 1 or the particular interrupt is disabled in the
interrupt enable register.
5.6.2
Clearing Subactive Mode
Subactive mode is cleared by a SLEEP instruction or by a low input at the RES pin.
• Clearing by SLEEP instruction
If a SLEEP instruction is executed while the SSBY bit in SYSCR1 is set to 1 and TMA3 bit in
TMA is set to 1, subactive mode is cleared and watch mode is entered. If a SLEEP instruction
is executed while SSBY = 0 and LSON = 1 in SYSCR1 and TMA3 = 1 in TMA, subsleep
mode is entered. Direct transfer to active mode is also possible; see section 5.8, Direct
Transfer, below.
• Clearing by RES pin
Clearing by RES pin is the same as for standby mode; see 2. Clearing by RES pin in section
5.3.2.
5.6.3
Operating Frequency in Subactive Mode
The operating frequency in subactive mode is set in bits SA1 and SA0 in SYSCR2. The choices
are φW/2, φW/4, and φW/8.
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Section 5 Power-Down Modes
5.7
Active (Medium-Speed) Mode
5.7.1
Transition to Active (Medium-Speed) Mode
If the RES pin is driven low, active (medium-speed) mode is entered. If the LSON bit in SYSCR2
is set to 1 while the LSON bit in SYSCR1 is cleared to 0, a transition to active (medium-speed)
mode results from IRQ0, IRQ1, or WKP7 to WKP0 interrupts in standby mode, timer A, timer F,
timer G, IRQ0, or WKP7 to WKP0 interrupts in watch mode, or any interrupt in sleep mode. A
transition to active (medium-speed) mode does not take place if the I bit of CCR is set to 1 or the
particular interrupt is disabled in the interrupt enable register.
The CPU may operate at a 1/2 state faster timing at transition to active (medium-speed) mode.
5.7.2
Clearing Active (Medium-Speed) Mode
Active (medium-speed) mode is cleared by a SLEEP instruction.
• Clearing by SLEEP instruction
A transition to standby mode takes place if the SLEEP instruction is executed while the SSBY
bit in SYSCR1 is set to 1, the LSON bit in SYSCR1 is cleared to 0, and the TMA3 bit in TMA
is cleared to 0. The system goes to watch mode if the SSBY bit in SYSCR1 is set to 1 and bit
TMA3 in TMA is set to 1 when a SLEEP instruction is executed.
When both SSBY and LSON are cleared to 0 in SYSCR1 and a SLEEP instruction is executed,
sleep mode is entered. Direct transfer to active (high-speed) mode or to subactive mode is also
possible. See section 5.8, Direct Transfer, below for details.
• Clearing by RES pin
When the RES pin is driven low, a transition is made to the reset state and active (mediumspeed) mode is cleared.
5.7.3
Operating Frequency in Active (Medium-Speed) Mode
Operation in active (medium-speed) mode is clocked at the frequency designated by the MA1 and
MA0 bits in SYSCR1.
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Section 5 Power-Down Modes
5.8
Direct Transfer
5.8.1
Overview of Direct Transfer
The CPU can execute programs in three modes: active (high-speed) mode, active (medium-speed)
mode, and subactive mode. A direct transfer is a transition among these three modes without the
stopping of program execution. A direct transfer can be made by executing a SLEEP instruction
while the DTON bit in SYSCR2 is set to 1. After the mode transition, direct transfer interrupt
exception handling starts.
If the direct transfer interrupt is disabled in interrupt enable register 2, a transition is made instead
to sleep mode or watch mode. Note that if a direct transition is attempted while the I bit in CCR is
set to 1, sleep mode or watch mode will be entered, and it will be impossible to clear the resulting
mode by means of an interrupt.
• Direct transfer from active (high-speed) mode to active (medium-speed) mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is set to 1, and the DTON
bit in SYSCR2 is set to 1, a transition is made to active (medium-speed) mode via sleep mode.
• Direct transfer from active (medium-speed) mode to active (high-speed) mode
When a SLEEP instruction is executed in active (medium-speed) mode while the SSBY and
LSON bits in SYSCR1 are cleared to 0, the MSON bit in SYSCR2 is cleared to 0, and the
DTON bit in SYSCR2 is set to 1, a transition is made to active (high-speed) mode via sleep
mode.
• Direct transfer from active (high-speed) mode to subactive mode
When a SLEEP instruction is executed in active (high-speed) mode while the SSBY and
LSON bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in
TMA is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (high-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is cleared to 0,
the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (high-speed) mode via watch mode after the waiting time set in SYSCR1 bits
STS2 to STS0 has elapsed.
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Section 5 Power-Down Modes
• Direct transfer from active (medium-speed) mode to subactive mode
When a SLEEP instruction is executed in active (medium-speed) while the SSBY and LSON
bits in SYSCR1 are set to 1, the DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA
is set to 1, a transition is made to subactive mode via watch mode.
• Direct transfer from subactive mode to active (medium-speed) mode
When a SLEEP instruction is executed in subactive mode while the SSBY bit in SYSCR1 is
set to 1, the LSON bit in SYSCR1 is cleared to 0, the MSON bit in SYSCR2 is set to 1, the
DTON bit in SYSCR2 is set to 1, and the TMA3 bit in TMA is set to 1, a transition is made
directly to active (medium-speed) mode via watch mode after the waiting time set in SYSCR1
bits STS2 to STS0 has elapsed.
5.8.2
Direct Transition Times
1. Time for direct transition from active (high-speed) mode to active (medium-speed) mode
A direct transition from active (high-speed) mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in active (high-speed) mode while bits SSBY and LSON are both
cleared to 0 in SYSCR1, and bits MSON and DTON are both set to 1 in SYSCR2. The time from
execution of the SLEEP instruction to the end of interrupt exception handling (the direct transition
time) is given by equation (1) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (1)
Example: Direct transition time = (2 + 1) × 2tosc + 14 × 16tosc = 230tosc (when φ/8 is selected as
the CPU operating clock)
Notation:
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
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Section 5 Power-Down Modes
2. Time for direct transition from active (medium-speed) mode to active (high-speed) mode
A direct transition from active (medium-speed) mode to active (high-speed) mode is performed by
executing a SLEEP instruction in active (medium-speed) mode while bits SSBY and LSON are
both cleared to 0 in SYSCR1, and bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2.
The time from execution of the SLEEP instruction to the end of interrupt exception handling (the
direct transition time) is given by equation (2) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tcyc before transition) + (number of interrupt
exception handling execution states) × (tcyc after transition)
.................................. (2)
Example: Direct transition time = (2 + 1) × 16tosc + 14 × 2tosc = 76tosc (when φ/8 is selected as
the CPU operating clock)
Notation:
tosc: OSC clock cycle time
tcyc: System clock (φ) cycle time
3. Time for direct transition from subactive mode to active (high-speed) mode
A direct transition from subactive mode to active (high-speed) mode is performed by executing a
SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is cleared to 0 in
SYSCR1, bit MSON is cleared to 0 and bit DTON is set to 1 in SYSCR2, and bit TMA3 is set to 1
in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (3) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (3)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 2tosc = 24tw + 16412tosc (when
φw/8 is selected as the CPU operating clock, and wait time = 8192 states)
Notation:
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
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Section 5 Power-Down Modes
4. Time for direct transition from subactive mode to active (medium-speed) mode
A direct transition from subactive mode to active (medium-speed) mode is performed by
executing a SLEEP instruction in subactive mode while bit SSBY is set to 1 and bit LSON is
cleared to 0 in SYSCR1, bits MSON and DTON are both set to 1 in SYSCR2, and bit TMA3 is set
to 1 in TMA. The time from execution of the SLEEP instruction to the end of interrupt exception
handling (the direct transition time) is given by equation (4) below.
Direct transition time = { (Number of SLEEP instruction execution states) + (number of internal
processing states) } × (tsubcyc before transition) + { (wait time set in
STS2 to STS0) + (number of interrupt exception handling execution
states) } × (tcyc after transition)
........................ (4)
Example: Direct transition time = (2 + 1) × 8tw + (8192 + 14) × 16tosc = 24tw + 131296tosc
(when φw/8 or φ8 is selected as the CPU operating clock, and wait time = 8192 states)
Notation:
tosc:
tw:
tcyc:
tsubcyc:
OSC clock cycle time
Watch clock cycle time
System clock (φ) cycle time
Subclock (φSUB) cycle time
5.8.3
Notes on External Input Signal Changes before/after Direct Transition
1. Direct transition from active (high-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
2. Direct transition from active (medium-speed) mode to subactive mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
3. Direct transition from subactive mode to active (high-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
4. Direct transition from subactive mode to active (medium-speed) mode
Since the mode transition is performed via watch mode, see section 5.3.5, Notes on External
Input Signal Changes before/after Standby Mode.
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Section 5 Power-Down Modes
5.9
Module Standby Mode
5.9.1
Setting Module Standby Mode
Module standby mode is set for individual peripheral functions. All the on-chip peripheral
modules can be placed in module standby mode. When a module enters module standby mode,
the system clock supply to the module is stopped and operation of the module halts. This state is
identical to standby mode.
Module standby mode is set for a particular module by setting the corresponding bit to 0 in clock
stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
5.9.2
Clearing Module Standby Mode
Module standby mode is cleared for a particular module by setting the corresponding bit to 1 in
clock stop register 1 (CKSTPR1) or clock stop register 2 (CKSTPR2). (See table 5.5.)
Following a reset, clock stop register 1 (CKSTPR1) and clock stop register 2 (CKSTPR2) are both
initialized to H'FF.
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Section 5 Power-Down Modes
Table 5.5
Setting and Clearing Module Standby Mode by Clock Stop Register
Register Name
Bit Name
CKSTPR1
TACKSTP
TCCKSTP
TFCKSTP
TGCKSTP
ADCKSTP
S1CKSTP
S32CKSTP
S31CKSTP
CKSTPR2
LDCKSTP
PWCKSTP
WDCKSTP
AECKSTP
Operation
1
Timer A module standby mode is cleared
0
Timer A is set to module standby mode
1
Timer C module standby mode is cleared
0
Timer C is set to module standby mode
1
Timer F module standby mode is cleared
0
Timer F is set to module standby mode
1
Timer G module standby mode is cleared
0
Timer G is set to module standby mode
1
A/D converter module standby mode is cleared
0
A/D converter is set to module standby mode
1
SCI1 module standby mode is cleared
0
SCI1 is set to module standby mode
1
SCI3-2 module standby mode is cleared
0
SCI3-2 is set to module standby mode
1
SCI3-1 module standby mode is cleared
0
SCI3-1 is set to module standby mode
1
LCD module standby mode is cleared
0
LCD is set to module standby mode
1
PWM module standby mode is cleared
0
PWM is set to module standby mode
1
Watchdog timer module standby mode is cleared
0
Watchdog timer is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
0
Asynchronous event counter is set to module standby mode
Note: For details of module operation, see the sections on the individual modules.
Rev. 6.00 Aug 04, 2006 page 153 of 680
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Section 5 Power-Down Modes
5.9.3
Usage Note
If, due to the timing with which a peripheral module issues interrupt requests, the module in
question is set to module standby mode before an interrupt is processed, the module will stop with
the interrupt request still pending. In this situation, interrupt processing will be repeated
indefinitely unless interrupts are prohibited.
It is therefore necessary to ensure that no interrupts are generated when a module is set to module
standby mode. The surest way to do this is to specify the module standby mode setting only when
interrupts are prohibited (interrupts prohibited using the interrupt enable register or interrupts
masked using bit CCR-I).
Rev. 6.00 Aug 04, 2006 page 154 of 680
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Section 6 ROM
Section 6 ROM
6.1
Overview
The H8/3842R, H8/38342, and H8/38442 have 16 Kbytes of mask ROM, the H8/3843R,
H8/38343, and H8/38443 have 24 Kbytes of mask ROM, the H8/3844R, H8/3844S, H8/38344,
and H8/38444 have 32 Kbytes of mask ROM, the H8/3845R, H8/3845S, H8/38345, and H8/38445
have 40 Kbytes of mask ROM, the H8/3846R, H8/3846S, H8/38346, and H8/38446 have 48
Kbytes of mask ROM, and the H8/3847R, H8/3847S, H8/38347, and H8/38447 have 60 Kbytes of
mask ROM on-chip. The ROM is connected to the CPU by a 16-bit data bus, allowing high-speed
two-state access for both byte data and word data. The H8/3847R has a ZTAT™ version with 60Kbyte PROM.
The H8/3847S Group does not have a ZTAT™ version. The H8/3847R ZTAT™ version must be
used.
The F-ZTAT™ versions of the H8/38347 and H8/38447 are equipped with 60 Kbytes of flash
memory. The F-ZTAT™ versions of the H8/38344 and H8/38444 are equipped with 32 Kbytes of
flash memory.
Rev. 6.00 Aug 04, 2006 page 155 of 680
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Section 6 ROM
6.1.1
Block Diagram
Figure 6.1 shows a block diagram of the on-chip ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0000
H'0001
H'0002
H'0002
H'0003
On-chip ROM
H'7FFE
H'7FFE
H'7FFF
Even-numbered
address
Odd-numbered
address
Figure 6.1 ROM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444)
Rev. 6.00 Aug 04, 2006 page 156 of 680
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Section 6 ROM
6.2
PROM Mode (H8/3847R)
6.2.1
Setting to PROM Mode
If the on-chip ROM is PROM, setting the chip to PROM mode stops operation as a
microcontroller and allows the PROM to be programmed in the same way as the standard
HN27C101 EPROM. However, page programming is not supported. Table 6.1 shows how to set
the chip to PROM mode.
Table 6.1
Setting to PROM Mode
Pin Name
Setting
TEST
High level
PB4/AN4
Low level
PB5/AN5
PB6/AN6
6.2.2
High level
Socket Adapter Pin Arrangement and Memory Map
A standard PROM programmer can be used to program the PROM. A socket adapter is required
for conversion to 32 pins, as listed in table 6.2.
Figure 6.2 shows the pin-to-pin wiring of the socket adapter. Figure 6.3 shows a memory map.
Table 6.2
Socket Adapter
Package
Socket Adapter Model (Manufacturer)
100-pin (FP-100B)
ME3887ESHS1H (MINATO)
H7388BQ100D3201 (DATA-I/O)
100-pin (FP-100A)
ME3887ESFS1H (MINATO)
H7388AQ100D3201 (DATA-I/O)
100-pin (TFP-100B)
ME3887ESNS1H (MINATO)
H7388BT100D3201 (DATA-I/O)
100-pin (TFP-100G)
ME3887ESMS1H (MINATO)
H7388GT100D3201 (DATA-I/O)
Rev. 6.00 Aug 04, 2006 page 157 of 680
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Section 6 ROM
H8/3847R
EPROM socket
HN27C101
(32-pin)
FP-100B,
TFP-100B
FP-100A
Pin
Pin
15
18
RES
VPP
1
51
54
P60
EO0
13
52
55
P61
EO1
14
53
56
P62
EO2
15
54
57
P63
EO3
17
55
58
P64
EO4
18
56
59
P65
EO5
19
57
60
P66
EO6
20
58
61
P67
EO7
21
74
77
P87
EA0
12
73
76
P86
EA1
11
72
75
P85
EA2
10
71
74
P84
EA3
9
70
73
P83
EA4
8
69
72
P82
EA5
7
68
71
P81
EA6
6
67
70
P80
EA7
5
59
62
P70
EA8
27
86
89
P43
EA9
26
61
64
P72
EA10
23
62
65
P73
EA11
25
63
66
P74
EA12
4
64
67
P75
EA13
28
65
68
P76
EA14
29
5
8
P14
EA15
3
6
9
P15
EA16
66
69
P77
CE
22
60
63
P71
OE
24
4
7
P13
PGM
31
38, 32
41, 35
VCC, CVCC
VCC
32
87
90
AVCC
14
17
TEST
9
12
X1
94
97
PB6
2
5
P11
3
6
P12
7
10
P16
11, 33
14, 36
VSS
VSS
16
100
3
AVSS
92
95
PB4
93
96
PB5
2
Note: Pins not indicated in the figure should be left open.
Figure 6.2 Socket Adapter Pin Correspondence (with HN27C101)
Rev. 6.00 Aug 04, 2006 page 158 of 680
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Section 6 ROM
Address in
MCU mode
Address in
PROM mode
H'0000
H'0000
On-chip PROM
H'EDFF
H'EDFF
Uninstalled area*
H'1FFFF
Note: * The output data is not guaranteed if this address area is read in PROM mode. Therefore,
when programming with a PROM programmer, be sure to specify addresses from H'0000
to H'EDFF. If programming is inadvertently performed from H'EE00 onward, it may not be
possible to continue PROM programming and verification.
When programming, H'FF should be set as the data in this address area (H'EE00 to
H'1FFFF).
Figure 6.3 H8/3847R Memory Map in PROM Mode
Rev. 6.00 Aug 04, 2006 page 159 of 680
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Section 6 ROM
6.3
Programming (H8/3847R)
The write, verify, and other modes are selected as shown in table 6.3 in PROM mode.
(H8/3847R)
Table 6.3
Mode Selection in PROM Mode (H8/3847R)
Pins
Mode
CE
OE
PGM
VPP
VCC
EO7 to EO0
EA16 to EA0
Write
L
H
L
VPP
VCC
Data input
Address input
Verify
L
L
H
VPP
VCC
Data output
Address input
VPP
VCC
High impedance Address input
Programming
L
L
L
disabled
L
H
H
H
L
L
H
H
H
Legend:
L:
Low level
H:
High level
VPP:
VPP level
VCC: VCC level
The specifications for writing and reading are identical to those for the standard HN27C101
EPROM. However, page programming is not supported, and so page programming mode must not
be set. A PROM programmer that only supports page programming mode cannot be used. When
selecting a PROM programmer, ensure that it supports high-speed, high-reliability byte-by-byte
programming. Also, be sure to specify addresses from H'0000 to H'EDFF.
6.3.1
Writing and Verifying
An efficient, high-speed, high-reliability method is available for writing and verifying the PROM
data. This method achieves high speed without voltage stress on the device and without lowering
the reliability of written data. The basic flow of this high-speed, high-reliability programming
method is shown in figure 6.4.
Rev. 6.00 Aug 04, 2006 page 160 of 680
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Section 6 ROM
Start
Set write/verify mode
VCC = 6.0 V ± 0.25 V, VPP = 12.5 V ± 0.3 V
Address = 0
n=0
n+1 →n
No
Yes
n < 25
Write time t PW = 0.2 ms ± 5%
No Go
Address + 1 → address
Verify
Go
Write time tOPW = 0.2n ms
Last address?
No
Yes
Set read mode
VCC = 5.0 V ± 0.25 V, VPP = VCC
No Go
Error
Read all
addresses?
Go
End
Figure 6.4 High-Speed, High-Reliability Programming Flow Chart
Rev. 6.00 Aug 04, 2006 page 161 of 680
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Section 6 ROM
Tables 6.4 and 6.5 give the electrical characteristics in programming mode.
Table 6.4
DC Characteristics
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C)
Item
Symbol
Min
Typ
Max
Input highEO7 to EO0, EA16 to
level voltage EA0 OE, CE, PGM
VIH
2.4
—
VCC + 0.3 V
Input lowEO7 to EO0, EA16 to
level voltage EA0 OE, CE, PGM
VIL
–0.3
—
0.8
V
Output high- EO7 to EO0
level voltage
VOH
2.4
—
—
V
IOH = –200 µA
Output low
EO7 to EO0
level voltage
VOL
—
—
0.45
V
IOL = 0.8 mA
Input leakage EO7 to EO0, EA16 to
current
EA0 OE, CE, PGM
|ILI|
—
—
2
µA
Vin = 5.25 V/0.5 V
VCC current
ICC
—
—
40
mA
VPP current
IPP
—
—
40
mA
Rev. 6.00 Aug 04, 2006 page 162 of 680
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Unit
Test Condition
Section 6 ROM
Table 6.5
AC Characteristics
(Conditions: VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C)
Item
Symbol
Min Typ
Max
Unit Test Condition
Address setup time
tAS
2
—
—
µs
OE setup time
tOES
2
—
—
µs
Data setup time
tDS
2
—
—
µs
Address hold time
tAH
0
—
—
µs
Data hold time
2
—
—
µs
Data output disable time
tDH
2
tDF*
—
—
130
µs
VPP setup time
tVPS
2
—
—
µs
Programming pulse width
tPW
0.19 0.20
0.21
ms
PGM pulse width for overwrite programming
tOPW *
0.19 —
5.25
ms
CE setup time
tCES
2
—
—
µs
VCC setup time
tVCS
2
—
—
µs
Data output delay time
tOE
0
—
200
ns
3
Figure 6.5*
1
Notes: 1. Input pulse level: 0.45 V to 2.2 V
Input rise time/fall time ≤ 20 ns
Timing reference levels Input: 0.8 V, 2.0 V
Output: 0.8 V, 2.0 V
2. tDF is defined at the point at which the output is floating and the output level cannot be
read.
3. tOPW is defined by the value given in figure 6.4, High-Speed, High-Reliability
Programming Flow Chart.
Rev. 6.00 Aug 04, 2006 page 163 of 680
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Section 6 ROM
Figure 6.5 shows a PROM write/verify timing diagram.
Write
Verify
Address
tAS
Data
tAH
Input data
tDS
VPP
tDH
tDF
VPP
VCC
VCC
Output data
tVPS
VCC+1
VCC
tVCS
CE
tCES
PGM
tPW
tOES
tOE
OE
tOPW*
Note: * topw is defined by the value shown in figure 6.4, High-Speed, High-Reliability Programming Flowchart.
Figure 6.5 PROM Write/Verify Timing
Rev. 6.00 Aug 04, 2006 page 164 of 680
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Section 6 ROM
6.3.2
Programming Precautions
• Use the specified programming voltage and timing.
• The programming voltage in PROM mode (VPP) is 12.5 V. Use of a higher voltage can
permanently damage the chip. Be especially careful with respect to PROM programmer
overshoot.
• Setting the PROM programmer to Renesas specifications for the HN27C101 will result in
correct VPP of 12.5 V.
• Make sure the index marks on the PROM programmer socket, socket adapter, and chip are
properly aligned. If they are not, the chip may be destroyed by excessive current flow. Before
programming, be sure that the chip is properly mounted in the PROM programmer.
• Avoid touching the socket adapter or chip while programming, since this may cause contact
faults and write errors.
• Take care when setting the programming mode, as page programming is not supported.
• When programming with a PROM programmer, be sure to specify addresses from H'0000 to
H'EDFF. If programming is inadvertently performed from H'EE00 onward, it may not be
possible to continue PROM programming and verification. When programming, H'FF should
be set as the data in address area H'EE00 to H'1FFFF.
Rev. 6.00 Aug 04, 2006 page 165 of 680
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Section 6 ROM
6.4
Reliability of Programmed Data
A highly effective way to improve data retention characteristics is to bake the programmed chips
at 150°C, then screen them for data errors. This procedure quickly eliminates chips with PROM
memory cells prone to early failure.
Figure 6.6 shows the recommended screening procedure.
Program chip and verify
programmed data
Bake chip for 24 to 48 hours at
125°C to 150°C with power off
Read and check program
Install
Figure 6.6 Recommended Screening Procedure
If a series of programming errors occurs while the same PROM programmer is in use, stop
programming and check the PROM programmer and socket adapter for defects. Please inform
Renesas Technology of any abnormal conditions noted during or after programming or in
screening of program data after high-temperature baking.
Rev. 6.00 Aug 04, 2006 page 166 of 680
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Section 6 ROM
6.5
Flash Memory Overview
6.5.1
Features
The features of the 60 Kbytes or 32 Kbytes of flash memory built into the F-ZTAT versions are
summarized below.
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The 60-Kbyte flash memory is configured as follows: 1 Kbyte × 4 blocks, 28 Kbytes
× 1 block, 16 Kbytes × 1 block, 8 Kbytes × 1 block and 4 Kbytes × 1 block. The 32-Kbyte
flash memory is configured as follows: 1 Kbyte × 4 blocks, 28 Kbytes × 1 block. To erase
the entire flash memory, each block must be erased in turn.
• Reprogramming capability
The flash memory can be reprogrammed up to 1,000 times.
• On-board programming
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is started to erase or program of the entire flash memory. In normal user
program mode, individual blocks can be erased or programmed.
• Programmer mode
Flash memory can be programmed/erased in programmer mode using a PROM
programmer, as well as in on-board programming mode.
• Automatic bit rate adjustment
For data transfer in boot mode, this LSI's bit rate can be automatically adjusted to match
the transfer bit rate of the host.
• Programming/erasing protection
Sets software protection against flash memory programming/erasing.
• Power-down mode
The power supply circuit is partly halted in the subactive mode and can be read in the
power-down mode.
Rev. 6.00 Aug 04, 2006 page 167 of 680
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Section 6 ROM
6.5.2
Block Diagram
Internal address bus
Internal data bus (16 bits)
Module bus
FLMCR1
FLMCR2
Bus interface/controller
EBR
Operating
mode
TES pin
P24 pin
P26 pin
FLPWCR
FENR
Flash memory
Legend:
FLMCR1:
FLMCR2:
EBR:
FLPWCR:
FENR:
Flash memory control register 1
Flash memory control register 2
Erase block register
Flash memory power control register
Flash memory enable register
Figure 6.7 Block Diagram of Flash Memory
6.5.3
Block Configuration
Figure 6.8 shows the block configuration of flash memory. The thick lines indicate erasing units,
the narrow lines indicate programming units, and the values are addresses. The flash memory is
divided into 1 Kbyte × 4 blocks, 28 Kbytes × 1 block, 16 Kbytes × 1 block, 8 Kbytes × 1 block
and 4 Kbytes × 1 block. Erasing is performed in these units. Programming is performed in 128byte units starting from an address with lower eight bits H'00 or H'80.
Rev. 6.00 Aug 04, 2006 page 168 of 680
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Section 6 ROM
H'0000
H'0001
H'0002
H'0080
H'0081
H'0082
H'0380
H'0381
H'0382
H'0400
H'0401
H'0402
H'0480
H'0481
H'0482
H'0780
H'0781
H'0782
H'0800
H'0801
H'0802
H'0880
H'0881
H'0882
Programming unit: 128 bytes
H'007F
H'00FF
Erase unit
1 Kbyte
H'03FF
Programming unit: 128 bytes
H'047F
H'04FF
Erase unit
1 Kbyte
H'07FF
Programming unit: 128 bytes
H'087F
H'080F
Erase unit
1 Kbyte
H'0B80
H'0B81
H'0B82
H'0C00
H'0C01
H'0C02
H'0C80
H'0C81
H'0C82
H'0F80
H'0F81
H'0F82
H'1000
H'1001
H'1002
H'1080
H'1081
H'1082
H'7F80
H'7F81
H'7F82
H'8000
H'8001
H'8002
H'8080
H'8081
H'8082
H'BF80
H'BF81
H'BF82
H'C000
H'C001
H'C002
H'C080
H'C081
H'C082
H'DF80
H'DF81
H'DF82
H'E000
H'E001
H'E002
H'E080
H'E081
H'E082
H'ECFF
H'EF80
H'EF81
H'EF82
H'EFFF
H'0BFF
Programming unit: 128 bytes
H'0C7F
H'0CFF
Erase unit
1 Kbyte
H'0FFF
Programming unit: 128 bytes
H'107F
H'10FF
Erase unit
28 Kbytes
H'7FFF
Programming unit: 128 bytes
H'807F
H'8CFF
Erase unit
16 Kbyte
H'BFFF
Programming unit: 128 bytes
H'C07F
H'CCFF
Erase unit
8 Kbyte
H'DFFF
Programming unit: 128 bytes
H'E07F
Erase unit
4 Kbyte
Figure 6.8 Flash Memory Block Configuration
Rev. 6.00 Aug 04, 2006 page 169 of 680
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Section 6 ROM
6.5.4
Register Configuration
Table 6.6 lists the register configuration to control the flash memory when the built in flash
memory is effective.
Table 6.6
Register Configuration
Register Name
Abbreviation
R/W
Initial Value
Address
Flash memory control register 1
FLMCR1
R/W
H'00
H'F020
Flash memory control register 2
FLMCR2
R
H'00
H'F021
Flash memory power control register
FLPWCR
R/W
H'00
H'F022
Erase block register
EBR
R/W
H'00
H'F023
Flash memory enable register
FENR
R/W
H'00
H'F02B
Note: FLMCR1, FLMCR2, FLPWCR, EBR, and FENR are 8 bit registers. Only byte access is
enabled which are two-state access. These registers are dedicated to the product in which
flash memory is included. The product in which PROM or ROM is included does not have
these registers. When the corresponding address is read in these products, the value is
undefined. A write is disabled.
Rev. 6.00 Aug 04, 2006 page 170 of 680
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Section 6 ROM
6.6
Descriptions of Registers of the Flash Memory
6.6.1
Flash Memory Control Register 1 (FLMCR1)
Bit
7
6
5
4
3
2
1
0
—
SWE
ESU
PSU
EV
PV
E
P
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FLMCR1 is a register that makes the flash memory change to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 6.8, Flash
Memory Programming/Erasing. By setting this register, the flash memory enters program mode,
erase mode, program-verify mode, or erase-verify mode. Read the data in the state that bits 6 to 0
of this register are cleared when using flash memory as normal built-in ROM.
Bit 7—Reserved
This bit is always read as 0 and cannot be modified.
Bit 6—Software Write Enable (SWE)
This bit is to set enabling/disabling of programming/enabling of flash memory (set when bits 5 to
0 and the EBR register are to be set).
Bit 6
SWE
Description
0
Programming/erasing is disabled. Other FLMCR1 register bits and all EBR bits
cannot be set.
(initial value)
1
Flash memory programming/erasing is enabled.
Rev. 6.00 Aug 04, 2006 page 171 of 680
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Section 6 ROM
Bit 5—Erase Setup (ESU)
This bit is to prepare for changing to erase mode. Set this bit to 1 before setting the E bit to 1 in
FLMCR1 (do not set SWE, PSU, EV, PV, E, and P bits at the same time).
Bit 5
ESU
Description
0
The erase setup state is cancelled
1
The flash memory changes to the erase setup state. Set this bit to 1 before setting
the E bit to 1 in FLMCR1.
(initial value)
Bit 4—Program Setup (PSU)
This bit is to prepare for changing to program mode. Set this bit to 1 before setting the P bit to 1
in FLMCR1 (do not set SWE, ESU, EV, PV, E, and P bits at the same time).
Bit 4
PSU
Description
0
The program setup state is cancelled
1
The flash memory changes to the program setup state. Set this bit to 1 before
setting the P bit to 1 in FLMCR1.
(initial value)
Bit 3—Erase-Verify (EV)
This bit is to set changing to or cancelling erase-verify mode (do not set SWE, ESU, PSU, PV, E,
and P bits at the same time).
Bit 3
EV
Description
0
Erase-verify mode is cancelled
1
The flash memory changes to erase-verify mode
Rev. 6.00 Aug 04, 2006 page 172 of 680
REJ09B0145-0600
(initial value)
Section 6 ROM
Bit 2—Program-Verify (PV)
This bit is to set changing to or cancelling program-verify mode (do not set SWE, ESU, PSU, EV,
E, and P bits at the same time).
Bit 2
PV
Description
0
Program-verify mode is cancelled
1
The flash memory changes to program-verify mode
(initial value)
Bit 1—Erase (E)
This bit is to set changing to or cancelling erase mode (do not set SWE, ESU, PSU, EV, PV, and P
bits at the same time).
Bit 1
E
Description
0
Erase mode is cancelled
1
When this bit is set to 1, while the SWE = 1 and ESU = 1, the flash memory
changes to erase mode.
(initial value)
Bit 0—Program (P)
This bit is to set changing to or cancelling program mode (do not set SWE, ESU, PSU, EV, PV,
and E bits at the same time).
Bit 0
P
Description
0
Program mode is cancelled
1
When this bit is set to 1, while the SWE = 1 and PSU = 1, the flash memory
changes to program mode.
(initial value)
Rev. 6.00 Aug 04, 2006 page 173 of 680
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Section 6 ROM
6.6.2
Flash Memory Control Register 2 (FLMCR2)
Bit
7
6
5
4
3
2
1
0
FLER
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
—
—
—
—
—
—
—
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to.
Bit 7—Flash Memory Error (FLER)
This bit is set when the flash memory detects an error and goes to the error-protection state during
programming or erasing to the flash memory. See section 6.9.3, Error Protection, for details.
Bit 7
FLER
Description
0
The flash memory operates normally.
1
Indicates that an error has occurred during an operation on flash memory
(programming or erasing).
(initial value)
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
6.6.3
Erase Block Register (EBR)
Bit
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EBR specifies the flash memory erase area block. EBR is initialized to H'00 when the SWE bit in
FLMCR1 is 0. Do not set more than one bit at a time, as this will cause all the bits in EBR to be
automatically cleared to 0. When each bit is set to 1 in EBR, the corresponding block can be
erased. Other blocks change to the erase-protection state. See table 6.7 for the method of dividing
blocks of the flash memory. When the whole bits are to be erased, erase them in turn in unit of a
block.
Rev. 6.00 Aug 04, 2006 page 174 of 680
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Section 6 ROM
Table 6.7
Division of Blocks to Be Erased
EBR
Bit Name
Block (Size)
Address
0
EB0
EB0 (1 Kbyte)
H'0000 to H'03FF
1
EB1
EB1 (1 Kbyte)
H'0400 to H'07FF
2
EB2
EB2 (1 Kbyte)
H'0800 to H'0BFF
3
EB3
EB3 (1 Kbyte)
H'0C00 to H'0FFF
4
EB4
EB4 (28 Kbytes)
H'1000 to H'7FFF
5
EB5
EB5 (16 Kbyte)
H'8000 to H'BFFF
6
EB6
EB6 (8 Kbyte)
H'C000 to H'DFFF
7
EB7
EB7 (4 Kbytes)
H'E000 to H'EFFF
6.6.4
Flash Memory Power Control Register (FLPWCR)
Bit
7
6
5
4
3
2
1
0
PDWND
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
—
—
—
—
—
—
—
FLPWCR enables or disables a transition to the flash memory power-down mode when the LSI
switches to subactive mode. The power supply circuit can be read in the subactive mode, although
it is partly halted in the power-down mode.
Bit 7—Power-down Disable (PDWND)
This bit selects the power-down mode of the flash memory when a transition to the subactive
mode is made.
Bit 7
PDWND
Description
0
When this bit is 0 and a transition is made to the subactive mode, the flash memory
enters the power-down mode.
(initial value)
1
When this bit is 1, the flash memory remains in the normal mode even after a
transition is made to the subactive mode.
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 6.00 Aug 04, 2006 page 175 of 680
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Section 6 ROM
6.6.5
Flash Memory Enable Register (FENR)
Bit
7
6
5
4
3
2
1
0
FLSHE
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
—
—
—
—
—
—
—
FENR controls CPU access to the flash memory control registers, FLMCR1, FLMCR2, EBR, and
FLPWCR.
Bit 7—Flash Memory Control Register Enable (FLSHE)
This bit controls access to the flash memory control registers.
Bit 7
FLSHE
Description
0
Flash memory control registers cannot be accessed
1
Flash memory control registers can be accessed
Bits 6 to 0—Reserved
These bits are always read as 0 and cannot be modified.
Rev. 6.00 Aug 04, 2006 page 176 of 680
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(initial value)
Section 6 ROM
6.7
On-Board Programming Modes
There are two modes for programming/erasing of the flash memory; boot mode, which enables onboard programming/erasing, and programmer mode, in which programming/erasing is performed
with a PROM programmer. On-board programming/erasing can also be performed in user
program mode. At reset-start in reset mode, the device changes to a mode depending on the TEST
pin settings, P24 pin settings, and input level of each port, as shown in table 6.8. The input level of
each pin must be defined four states before the reset ends.
When changing to boot mode, the boot program built into this LSI is initiated. The boot program
transfers the programming control program from the externally-connected host to on-chip RAM
via SCI32. After erasing the entire flash memory, the programming control program is executed.
This can be used for programming initial values in the on-board state or for a forcible return when
programming/erasing can no longer be done in user program mode. In user program mode,
individual blocks can be erased and programmed by branching to the user program/erase control
program prepared by the user.
Table 6.8
Setting Programming Modes
TEST
P24
P26
PB0
PB1
PB2
LSI State after Reset End
0
1
X
X
X
X
User Mode
0
0
1
X
X
X
Boot Mode
1
X
X
0
0
0
Programmer Mode
X: Don’t care
Rev. 6.00 Aug 04, 2006 page 177 of 680
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Section 6 ROM
6.7.1
Boot Mode
Table 6.9 shows the boot mode operations between reset end and branching to the programming
control program. The device uses SCI32 in the boot mode.
1. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 6.8, Flash Memory Programming/Erasing.
2. SCI3 should be set to asynchronous mode, and the transfer format as follows: 8-bit data, 1 stop
bit, and no parity. The inversion function of TXD and RXD pins by the SPCR register is set to
“Not to be inverted,” so do not put the circuit for inverting a value between the host and this
LSI.
3. When the boot program is initiated, the chip measures the low-level period of asynchronous
SCI communication data (H'00) transmitted continuously from the host. The chip then
calculates the bit rate of transmission from the host, and adjusts the SCI3 bit rate to match that
of the host. The reset should end with the RXD pin high. The RXD and TXD pins should be
pulled up on the board if necessary. After the reset is complete, it takes approximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rate adjustment. The host should confirm that this adjustment end indication
(H'00) has been received normally, and transmit one H'55 byte to the chip. If reception could
not be performed normally, initiate boot mode again by a reset. Depending on the host's
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit rates of the host and the chip. To operate the SCI properly, set the host's transfer bit
rate and system clock frequency of this LSI within the ranges listed in table 6.10.
5. In boot mode, a part of the on-chip RAM area is used by the boot program. The area H'F780 to
H'FEEF is the area to which the programming control program is transferred from the host.
The boot program area cannot be used until the execution state in boot mode switches to the
programming control program.
6. Before branching to the programming control program, the chip terminates transfer operations
by SCI3 (by clearing the RE and TE bits in SCR to 0), however the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of write data or verify data with the host. The TXD pin is high (PCR42 = 1, P42 = 1). The
contents of the CPU general registers are undefined immediately after branching to the
programming control program. These registers must be initialized at the beginning of the
programming control program, as the stack pointer (SP), in particular, is used implicitly in
subroutine calls, etc.
7. Boot mode can be cleared by a reset. End the reset after driving the reset pin low, waiting at
least 20 states, and then setting the TEST pin and P24 pin. Boot mode is also cleared when a
WDT overflow occurs.
Rev. 6.00 Aug 04, 2006 page 178 of 680
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Section 6 ROM
8. Do not change the TEST pin and P24 pin input levels in boot mode.
Table 6.9
Boot Mode Operation
Host Operation
LSI Operation
Item
Processing Contents
Processing Contents
Bit rate
adjustment
Continuously transmits data H'00 at
specified bit rate.
Flash memory erase
Transmits data H'55 when data H'00
is received and no error occurs.
Branches to boot program at reset-start.
· Measures low-level period of receive data H'00.
· Calculates bit rate and sets it in BRR of SCI3.
· Transmits data H'00 to the host to indicate that the
adjustment has ended.
Checks flash memory data, erases all flash memory
blocks in case of written data existing, and transmits
data H'AA to host. (If erase could not be done,
transmits data H'FF to host and aborts operation.)
Transfer of
programming control
program
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Transfer of
programming control
program (repeated for
N times)
Transmits 1-byte of programming
control program
Echobacks the 2-byte received data to host.
Echobacks received data to host and also
transfers it to RAM.
Transmits 1-byte data H'AA to host.
Execution of
Programming
control program
Branches to programming control program
transferred to on-chip RAM and starts execution.
Table 6.10 Oscillating Frequencies (fOSC) for which Automatic Adjustment of LSI Bit Rate
Is Possible
Product Group
Host Bit Rate
Oscillating Frequencies (fOSC) Range of LSI
H8/38347F-ZTAT
19,200 bps
16 MHz
H8/38344F-ZTAT
9,600 bps
8 to 16 MHz
H8/38447F-ZTAT
4,800 bps
6 to 16 MHz
H8/38444F-ZTAT
2,400 bps
2 to 16 MHz
1,200 bps
2 to 16 MHz
Rev. 6.00 Aug 04, 2006 page 179 of 680
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Section 6 ROM
6.7.2
Programming/Erasing in User Program Mode
The term user mode refers to the status when a user program is being executed. On-board
programming/erasing of an individual flash memory block can also be performed in user program
mode by branching to a user program/erase control program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the user program/erase control program or a program that provides the user program/erase
control program from external memory. As the flash memory itself cannot be read during
programming/erasing, transfer the user program/erase control program to on-chip RAM, as in boot
mode. Figure 6.9 shows a sample procedure for programming/erasing in user program mode.
Prepare a user program/erase control program in accordance with the description in section 6.8,
Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Figure 6.9 Programming/Erasing Flowchart Example in User Program Mode
6.8
Flash Memory Programming/Erasing
A software method using the CPU is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 setting, the flash memory operates in one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The programming control program in boot mode and the user program/erase control
Rev. 6.00 Aug 04, 2006 page 180 of 680
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Section 6 ROM
program in user program mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 6.8.1, Program/Program-Verify and section 6.8.2,
Erase/Erase-Verify, respectively.
6.8.1
Program/Program-Verify
When writing data or programs to the flash memory, the program/program-verify flowchart shown
in figure 6.10 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be written to the flash memory without subjecting the
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if writing fewer than 128 bytes. In this case, H'FF data must be written to the
extra addresses.
3. Prepare the following data storage areas in RAM: A 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation according to table 6.11, and additional programming data
computation according to table 6.12.
4. Consecutively transfer 128 bytes of data in byte units from the reprogramming data area or
additional-programming data area to the flash memory. The program address and 128-byte
data are latched in the flash memory. The lower 8 bits of the start address in the flash memory
destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Figure 6.12 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
An overflow cycle of approximately 6.6 ms is allowed.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
8. The maximum number of repetitions of the program/program-verify sequence of the same bit
is 1,000.
Rev. 6.00 Aug 04, 2006 page 181 of 680
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Section 6 ROM
Write pulse application subroutine
Apply Write Pulse
START
Set SWE bit in FLMCR1
WDT enable
Wait 1 µs
Set PSU bit in FLMCR1
Store 128-byte program data in program
data area and reprogram data area
Wait 50 µs
n=1
Set P bit in FLMCR1
m=0
Wait (Wait time = programming time)
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
Clear P bit in FLMCR1
Apply Write pulse
Wait 5 µs
Set PV bit in FLMCR1
Clear PSU bit in FLMCR1
Wait 4 µs
Wait 5 µs
Set block start address as
verify address
Disable WDT
n←n+1
H'FF dummy write to verify address
End Sub
Wait 2 µs
Read verify data
Verify data =
write data?
Increment address
No
m=1
Yes
n≤6?
No
Yes
Additional-programming data
computation
Reprogram data computation
No
128-byte
data verification
completed?
Yes
Clear PV bit in FLMCR1
Wait 2 µs
n ≤ 6?
No
Yes
Successively write 128-byte data from
additional-programming data area
in RAM to flash memory
Sub-Routine-Call
Apply Write Pulse
m=0?
No
n ≤ 1000 ?
Yes
Clear SWE bit in FLMCR1
Wait 100 µs
End of programming
No
Clear SWE bit in FLMCR1
Wait 100 µs
Programming failure
Figure 6.10 Program/Program-Verify Flowchart
Rev. 6.00 Aug 04, 2006 page 182 of 680
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Yes
Section 6 ROM
Table 6.11 Reprogram Data Computation Table
Program Data
Verify Data
Reprogram Data
Comments
0
0
1
Programming completed
0
1
0
Reprogram bit
1
0
1
—
1
1
1
Remains in erased state
Table 6.12 Additional-Program Data Computation Table
Reprogram Data
Verify Data
Additional-Program
Data
Comments
0
0
0
Additional-program bit
0
1
1
No additional programming
1
0
1
No additional programming
1
1
1
No additional programming
In Additional
Programming
Comments
Table 6.13 Programming Time
n
Programming
(Number of Writes) Time
1 to 6
30
10
7 to 1,000
200
—
Note: Time shown in µs.
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Section 6 ROM
6.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 6.11 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
register (EBR). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overerasing due to program runaway, etc. An
overflow cycle of approximately 19.8 ms is allowed.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 1 bit
is b'0. Verify data can be read in word size from the address to which a dummy write was
performed.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/eraseverify sequence as before. The maximum number of repetitions of the erase/erase-verify
sequence is 100.
6.8.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, are disabled while flash memory is being programmed or erased, or while the boot
program is executing, for the following three reasons:
1. Interrupt during programming/erasing may cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handling starts before the vector address is written or during
programming/erasing, a correct vector cannot be fetched and the CPU malfunctions.
3. If an interrupt occurs during boot program execution, normal boot mode sequence cannot be
carried out.
Rev. 6.00 Aug 04, 2006 page 184 of 680
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Section 6 ROM
Erase start
SWE bit ← 1
Wait 1 µs
n←1
Set EBR
Enable WDT
ESU bit ← 1
Wait 100 µs
E bit ← 1
Wait 10 ms
E bit ← 0
Wait 10 µs
ESU bit ← 0
Wait 10 µs
Disable WDT
EV bit ← 1
Wait 20 µs
Set block start address as verify address
H'FF dummy write to verify address
Wait 2 µs
n←n+1
Read verify data
No
Verify data = all 1s ?
Increment address
Yes
No
Last address of block ?
Yes
No
EV bit ← 0
EV bit ← 0
Wait 4 µs
Wait 4µs
All erase block erased ?
n ≤100 ?
Yes
No
Yes
SWE bit ← 0
SWE bit ← 0
Wait 100 µs
Wait 100 µs
End of erasing
Erase failure
Figure 6.11 Erase/Erase-Verify Flowchart
Rev. 6.00 Aug 04, 2006 page 185 of 680
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Section 6 ROM
6.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and error protection.
6.9.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset, subactive mode, subsleep mode, watch mode,
or standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), and erase block register (EBR) are initialized. In a reset via the RES pin, the reset
state is not entered unless the RES pin is held low until oscillation stabilizes after powering on. In
the case of a reset during operation, hold the RES pin low for the RES pulse width specified in the
AC Characteristics section.
6.9.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1. When software protection is in effect, setting the P or E bit
in FLMCR1 does not cause a transition to program mode or erase mode. By setting the erase
block register (EBR), erase protection can be set for individual blocks. When EBR is set to H'00,
erase protection is set for all blocks.
6.9.3
Error Protection
In error protection, an error is detected when CPU runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is aborted. Aborting the program/erase operation
prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When the flash memory of the relevant address area is read during programming/erasing
(including vector read and instruction fetch)
• Immediately after exception handling excluding a reset during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
The FLMCR1, FLMCR2, and EBR settings are retained, however program mode or erase mode is
aborted at the point at which the error occurred. Program mode or erase mode cannot be re-entered
Rev. 6.00 Aug 04, 2006 page 186 of 680
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Section 6 ROM
by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition can be
made to verify mode. Error protection can be cleared only by a power-on reset.
6.10
Programmer Mode
In programmer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as a discrete flash memory. Use a PROM programmer that supports the MCU
device type with the on-chip Renesas Technology (former Hitachi Ltd.) 64-Kbyte flash memory
(F-ZTAT64V3). A 10-MHz input clock is required. For the conditions for transition to
programmer mode, see table 6.8.
6.10.1
Socket Adapter
The socket adapter converts the pin allocation of the F-ZTAT device to that of the discrete flash
memory HN28F101. The address of the on-chip flash memory is H'0000 to H'EFFF. Figure 6.12
shows a socket-adapter-pin correspondence diagram.
6.10.2
Programmer Mode Commands
The following commands are supported in programmer mode.
• Memory Read Mode
• Auto-Program Mode
• Auto-Erase Mode
• Status Read Mode
Status polling is used for auto-programming, auto-erasing, and status read modes. In status read
mode, detailed internal information is output after the execution of auto-programming or autoerasing. Table 6.14 shows the sequence of each command. In auto-programming mode, 129 cycles
are required since 128 bytes are written at the same time. In memory read mode, the number of
cycles depends on the number of address write cycles (n).
Rev. 6.00 Aug 04, 2006 page 187 of 680
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Section 6 ROM
Table 6.14 Command Sequence in Programmer Mode
1st Cycle
2nd Cycle
Command Name
Number
of Cycles
Mode
Address
Data
Mode
Address
Data
Memory read
1+n
Write
X
H'00
Read
RA
Dout
Auto-program
129
Write
X
H'40
Write
WA
Din
Auto-erase
2
Write
X
H'20
Write
X
H'20
Status read
2
Write
X
H'71
Write
X
H'71
n: the number of address write cycles
Rev. 6.00 Aug 04, 2006 page 188 of 680
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Section 6 ROM
F-ZTAT Device
Pin No.
FP-100B
TFP-100B
TFP-100G
Pin Name
60
P71
66
3
51
52
53
54
55
56
57
58
74
73
72
71
70
69
68
67
59
85
61
62
63
64
65
86
32, 38
87
9
14
36
5
P77
P12
P60
P61
P62
P63
P64
P65
P66
P67
P87
P86
P85
P84
P83
P82
P81
P80
P70
P42
P72
P73
P74
P75
P76
P43
CVcc, Vcc
AVcc
X1
TEST
V1
P14
100, 11
33
88
89
90
13, 12
15
Other than the above
AVss, Vss
Vss
PB0
PB1
PB2
OSC1, OSC2
RES
(OPEN)
Socket Adapter
(Conversion to
32-Pin
Arrangement)
HN28F101 (32 Pins)
Pin Name
Pin No.
FWE
A9
A16
A15
WE
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
A0
A1
A2
A3
A4
A5
A6
A7
A8
OE
A10
A11
A12
A13
A14
CE
Vcc
Vss
1
26
2
3
31
13
14
15
17
18
19
20
21
12
11
10
9
8
7
6
5
27
24
23
25
4
28
29
22
32
16
Legend:
FWE:
I/O7 to I/O0:
A16 to A0:
CE:
OE:
WE:
Oscillator circuit
Power-on
reset circuit
Flash-write enable
Data input/output
Address input
Chip enable
Output enable
Write enable
Note: The oscillation frequency
of the oscillator circuit
should be 10 MHz.
Figure 6.12 Socket Adapter Pin Correspondence Diagram
Rev. 6.00 Aug 04, 2006 page 189 of 680
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Section 6 ROM
6.10.3
Memory Read Mode
1. After completion of auto-program/auto-erase/status read operations, a transition is made to the
command wait state. When reading memory contents, a transition to memory read mode must
first be made with a command write, after which the memory contents are read. Once memory
read mode has been entered, consecutive reads can be performed.
2. In memory read mode, command writes can be performed in the same way as in the command
wait state.
3. After powering on, memory read mode is entered.
4. Tables 6.14 to 6.16 show the AC characteristics.
Table 6.15 AC Characteristics in Transition to Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.13
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Rev. 6.00 Aug 04, 2006 page 190 of 680
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Section 6 ROM
Command write
Memory read mode
Address stable
A15−A0
tces
tceh
tnxtc
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7−I/O0
Note: Data is latched on the rising edge of WE.
Figure 6.13 Timing Waveforms for Memory Read after Memory Write
Table 6.16 AC Characteristics in Transition from Memory Read Mode to Another Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.14
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
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REJ09B0145-0600
Section 6 ROM
Memory read mode
A15−A0
Other mode command write
Address stable
tces
tnxtc
tceh
CE
OE
twep
tf
tr
WE
tds
tdh
I/O7−I/O0
Note: Do not enable WE and OE at the same time.
Figure 6.14 Timing Waveforms in Transition from Memory Read Mode to Another Mode
Table 6.17 AC Characteristics in Memory Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Access time
tacc
—
20
µs
Figure 6.15
CE output delay time
tce
—
150
ns
Figure 6.16
OE output delay time
toe
—
150
ns
Output disable delay time
tdf
—
100
ns
Data output hold time
toh
5
—
ns
A15−A0
Address stable
Address stable
CE
OE
WE
tacc
tacc
toh
toh
I/O7−I/O0
Figure 6.15 CE and OE Enable State Read Timing Waveforms
Rev. 6.00 Aug 04, 2006 page 192 of 680
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Section 6 ROM
A15−A0
Address stable
Address stable
tce
tce
CE
toe
toe
OE
WE
tacc
tacc
toh
tdf
toh
tdf
I/O7−I/O0
Figure 6.16 CE and OE Clock System Read Timing Waveforms
6.10.4
Auto-Program Mode
1. When reprogramming previously programmed addresses, perform auto-erasing before autoprogramming.
2. Perform auto-programming once only on the same address block. It is not possible to program
an address block that has already been programmed.
3. In auto-program mode, 128 bytes are programmed simultaneously. This should be carried out
by executing 128 consecutive byte transfers. A 128-byte data transfer is necessary even when
programming fewer than 128 bytes. In this case, H'FF data must be written to the extra
addresses.
4. The lower 7 bits of the transfer address must be low. If a value other than an effective address
is input, processing will switch to a memory write operation but a write error will be flagged.
5. Memory address transfer is performed in the second cycle (figure 6.17). Do not perform
transfer after the third cycle.
6. Do not perform a command write during a programming operation.
7. Perform one auto-program operation for a 128-byte block for each address. Two or more
additional programming operations cannot be performed on a previously programmed address
block.
8. Confirm normal end of auto-programming by checking I/O6. Alternatively, status read mode
can also be used for this purpose (I/O7 status polling uses the auto-program operation end
decision pin).
9. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
10. Table 6.18 shows the AC characteristics.
Rev. 6.00 Aug 04, 2006 page 193 of 680
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Section 6 ROM
Table 6.18 AC Characteristics in Auto-Program Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.17
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
twsts
1
—
ms
Status polling access time
tspa
—
150
ns
Address setup time
tas
0
—
ns
Address hold time
tah
60
—
ns
Memory write time
twrite
1
3000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
Address
stable
A15−A0
tces
tceh
tnxtc
tnxtc
CE
OE
tf
twep
tr
tas
tah
twsts
tspa
WE
tds
tdh
I/O7
twrite
Write operation end decision signal
I/O6
I/O5−I/O0
Data transfer
1 to 128 bytes
Write normal end decision signal
H'40
H'00
Figure 6.17 Auto-Program Mode Timing Waveforms
Rev. 6.00 Aug 04, 2006 page 194 of 680
REJ09B0145-0600
Section 6 ROM
6.10.5
Auto-Erase Mode
1. Auto-erase mode supports only entire memory erasing.
2. Do not perform a command write during auto-erasing.
3. Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also
be used for this purpose (I/O7 status polling uses the auto-erase operation end decision pin).
4. Status polling I/O6 and I/O7 pin information is retained until the next command write. As long
as the next command write has not been performed, reading is possible by enabling CE and
OE.
5. Table 6.19 shows the AC characteristics.
Table 6.19 AC Characteristics in Auto-Erase Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Command write cycle
tnxtc
20
—
µs
Figure 6.18
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
Status polling start time
tests
1
—
ms
Status polling access time
tspa
—
150
ns
Memory erase time
terase
100
40000
ms
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
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REJ09B0145-0600
Section 6 ROM
A15−A0
tces
tceh
tnxtc
tnxtc
CE
OE
tf
twep
tr
tests
tspa
WE
tds
terase
tdh
I/O7
Erase end
decision signal
I/O6
Erase normal
end
decision signal
I/O5−I/O0
H'20
H'20
H'00
Figure 6.18 Auto-Erase Mode Timing Waveforms
6.10.6
Status Read Mode
1. Status read mode is provided to identify the kind of abnormal end. Use this mode when an
abnormal end occurs in auto-program mode or auto-erase mode.
2. The return code is retained until a command write other than a status read mode command
write is executed.
3. Table 6.20 shows the AC characteristics and 6.20 shows the return codes.
Rev. 6.00 Aug 04, 2006 page 196 of 680
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Section 6 ROM
Table 6.20 AC Characteristics in Status Read Mode
Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Max
Unit
Notes
Read time after command write
tnxtc
20
—
µs
Figure 6.19
CE hold time
tceh
0
—
ns
CE setup time
tces
0
—
ns
Data hold time
tdh
50
—
ns
Data setup time
tds
50
—
ns
Write pulse width
twep
70
—
ns
OE output delay time
toe
—
150
ns
Disable delay time
tdf
—
100
ns
CE output delay time
tce
—
150
ns
WE rise time
tr
—
30
ns
WE fall time
tf
—
30
ns
A15−A0
tces
tceh
tnxtc tces
tceh
tnxtc
tnxtc
CE
tce
OE
twep
tf
tr
twep
tf
tr
toe
WE
tds
I/O7−/O0
tdh
H'71
tds
tdf
tdh
H'71
Note: I/O2 and I/O3 are undefined.
Figure 6.19 Status Read Mode Timing Waveforms
Rev. 6.00 Aug 04, 2006 page 197 of 680
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Section 6 ROM
Table 6.21 Status Read Mode Return Codes
Pin Name
Initial Value
Indications
I/O7
0
1: Abnormal end
0: Normal end
I/O6
0
I/O5
0
1: Command error
0: Otherwise
1: Programming error
0: Otherwise
I/O4
0
1: Erasing error
0: Otherwise
I/O3
0
I/O2
0
I/O1
0
1: Over counting of writing or erasing
0: Otherwise
I/O0
0
1: Effective address error
0: Otherwise
6.10.7
Status Polling
1. The I/O7 status polling flag indicates the operating status in auto-program/auto-erase mode.
2. The I/O6 status polling flag indicates a normal or abnormal end in auto-program/auto-erase
mode.
Table 6.22 Status Polling Output Truth Table
I/O7
I/O6
I/O0 to 5
Status
0
0
0
During internal operation
1
0
0
Abnormal end
1
1
0
Normal end
0
1
0
—
Rev. 6.00 Aug 04, 2006 page 198 of 680
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Section 6 ROM
6.10.8
Programmer Mode Transition Time
Commands cannot be accepted during the oscillation stabilization period or the programmer mode
setup period. After the programmer mode setup time, a transition is made to memory read mode.
Table 6.23 Stipulated Transition Times to Command Wait State
Item
Symbol
Min
Max
Unit
Notes
Oscillation stabilization time(crystal oscillator)
Tosc1
10
—
ms
Figure 6.20
Oscillation stabilization time(ceramic oscillator)
Tosc1
5
—
ms
Programmer mode setup time
Tbmv
10
—
ms
Vcc hold time
Tdwn
0
—
ms
tosc1
tbmv
Auto-program mode
Auto-erase mode
tdwn
Vcc
RES
Figure 6.20 Oscillation Stabilization Time, Boot Program Transfer Time,
and Power-Down Sequence
6.10.9
Notes on Memory Programming
1. When performing programming using programmer mode on a chip that has been
programmed/erased in an on-board programming mode, auto-erasing is recommended before
carrying out auto-programming.
2. The flash memory is initially in the erased state when the device is shipped by Renesas
Technology. For other chips for which the erasure history is unknown, it is recommended that
auto-erasing be executed to check and supplement the initialization (erase) level.
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Section 6 ROM
6.11
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read and written to at high speed.
• Power-down operating mode
The power supply circuit of the flash memory is partly halted and can be read under low power
consumption.
• Standby mode
All flash memory circuits are halted.
Table 6.24 shows the correspondence between the operating modes of this LSI and the flash
memory. In subactive mode, the flash memory can be set to operate in power-down mode with the
PDWND bit in FLPWCR. When the flash memory returns to its normal operating state from
power-down mode or standby mode, a period to stabilize the power supply circuits that were
stopped is needed. When the flash memory returns to its normal operating state, bits STS2 to STS0
in SYSCR1 must be set to provide a wait time of at least 20 µs, even when the external clock is
being used.
Table 6.24 Flash Memory Operating States
Flash Memory Operating State
LSI Operating State
PDWND = 0 (Initial value)
PDWND = 1
Active mode
Normal operating mode
Normal operating mode
Subactive mode
Power-down mode
Normal operating mode
Sleep mode
Normal operating mode
Normal operating mode
Subsleep mode
Standby mode
Standby mode
Standby mode
Standby mode
Standby mode
Watch mode
Standby mode
Standby mode
Rev. 6.00 Aug 04, 2006 page 200 of 680
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Section 7 RAM
Section 7 RAM
7.1
Overview
The H8/3842R, H8/3843R, H8/38342, H8/38343, H8/38442, and H8/38443 have 1 Kbytes of
high-speed static RAM, and H8/3844R, H8/3844S, H8/38344, H8/38444, H8/3845R, H8/3845S,
H8/38345, H8/38445, H8/3846R, H8/3846S, H8/38346, H8/38446, H8/3847R, H8/3847S,
H8/38347, and H8/38447 have 2 Kbytes of high-speed static RAM on-chip. The RAM is
connected to the CPU by a 16-bit data bus, allowing high-speed 2-state access for both byte data
and word data.
7.1.1
Block Diagram
Figure 7.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'F780
H'F780
H'F781
H'F782
H'F782
H'F783
On-chip RAM
H'FF7E
H'FF7E
H'FF7F
Even-numbered
address
Odd-numbered
address
Figure 7.1 RAM Block Diagram (H8/3844R, H8/3844S, H8/38344 and H8/38444)
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Section 7 RAM
Rev. 6.00 Aug 04, 2006 page 202 of 680
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Section 8 I/O Ports
Section 8 I/O Ports
8.1
Overview
The H8/3847R Group, H8/3847S Group and H8/38347 Group are provided with eight 8-bit I/O
ports, one 4-bit I/O port, one 3-bit I/O port, one 8-bit input-only port, one 4-bit input-only port,
and one 1-bit input-only port. Table 8.1 indicates the functions of each port.
Each port has of a port control register (PCR) that controls input and output, and a port data
register (PDR) for storing output data. Input or output can be assigned to individual bits.
See section 2.9.2, Notes on Bit Manipulation, for information on executing bit-manipulation
instructions to write data in PCR or PDR.
Ports 5, 6, 7, 8, 9, and A are also used as liquid crystal display segment and common pins,
selectable in 8-bit units.
Block diagrams of each port are given in Appendix C, I/O Port Block Diagrams
Table 8.1
Port
Port Functions
Description
Port 1 • 8-bit I/O port
• MOS input pull-up
option
Port 2 • 8-bit I/O port
• Open-drain output
option
Pins
Other Functions
Function
Switching
Registers
P17 to P15/IRQ3 to External interrupts 3 to 1
IRQ1/TMIF, TMIC Timer event interrupts
TMIF, TMIC
PMR1,
TCRF,
TMC
P14/IRQ4/ADTRG External interrupt 4 and A/D
converter external trigger
PMR1,
AMR
P13/TMIG
Timer G input capture input
PMR1
P12, P11/
TMOFH, TMOFL
Timer F output compare output
PMR1
P10/TMOW
Timer A clock output
PMR1
P20/SCK1
P21/SI1
P22/SO1
SCI1 data output (SO1), data input
(SI1), clock input/output (SCK1)
PMR2
• Large-current port P27 to P23
(H8/3847R Group,
H8/38347 Group
and H8/38447
Group)
None
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Section 8 I/O Ports
Port
Description
Port 3 • 8-bit I/O port
• MOS input pull-up
option
Function
Switching
Registers
Pins
Other Functions
P37/AEVL
P36/AEVH
P35/TXD31
P34/RXD31
P33/SCK31
SCI3-1 data output (TXD31), data
PMR3
input (RXD31), clock input/output
SCR31
(SCK31), and asynchronous counter SMR31
event inputs AEVL, AEVH
• Large-current port
(H8/3847R Group,
1
P32/RESO*
H8/38347 Group
2
P31/UD/EXCL*
and H8/38447
P30/PWM
Group)
Reset output* , timer C count-up/
down select input, and 14-bit PWM
2
output, external subclock input*
PMR2
PMR3
P43/IRQ0
External interrupt 0
PMR3
P42/TXD32
P41/RXD32
P40/SCK32
SCI3-2 data output (TXD32), data
input (RXD32), clock input/output
(SCK32)
SCR32
SMR32
P57 to P50/
WKP7 to WKP0/
SEG8 to SEG1
Wakeup input (WKP7 to WKP0),
segment output (SEG8 to SEG1)
PMR5
LPCR
P67 to P60/
SEG16 to SEG9
Segment output (SEG16 to SEG9)
LPCR
Port 7 • 8-bit I/O port
P77 to P70/
SEG24 to SEG17
Segment output (SEG24 to SEG17)
LPCR
Port 8 • 8-bit I/O port
P87 to P80/
SEG32 to SEG25
3
P97/SEG40/CL1*
3
P96/SEG39/CL2*
3
P95/SEG38/DO*
3
P94/SEG37/M*
P93 to P90/
SEG36 to SEG33
Segment output (SEG32 to SEG25)
LPCR
Port 4 • 1-bit input port
• 3-bit I/O port
Port 5 • 8-bit I/O port
• MOS input pull-up
option
Port 6 • 8-bit I/O port
• MOS input pull-up
option
Port 9 • 8-bit I/O port
1
• Segment output (SEG40 to SEG37) LPCR
3
• Latch clock (CL1)* , shift clock
3
3
(CL2)* , display data (DO)* and
3
*
alternating signal (M) for external
expansion of segment
• Segment output (SEG36 to SEG33)
Port A • 4-bit I/O port
PA3 to PA0/
COM4 to COM1
Common output (COM4 to COM1)
LPCR
Port B • 8-bit input port
PB7 to PB0/
AN7 to AN0
A/D converter analog input
AMR
Port C • 4-bit input port
PC3 to PC0/
AN11 to AN8
A/D converter analog input
AMR
Notes: 1. The RESO function is not implemented in the H8/38347 Group and H8/38447 Group.
2. The EXCL function is only implemented in the H8/38347 Group and H8/38447 Group.
3. The external expansion function for LCD segments is not implemented in the H8/38347
Group and H8/38447 Group.
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Section 8 I/O Ports
8.2
Port 1
8.2.1
Overview
Port 1 is an 8-bit I/O port. Figure 8.1 shows its pin configuration.
P1 7 /IRQ 3 /TMIF
P1 6 /IRQ 2
P1 5 /IRQ 1 /TMIC
Port 1
P1 4 /IRQ 4 /ADTRG
P1 3 /TMIG
P1 2 /TMOFH
P1 1 /TMOFL
P1 0 /TMOW
Figure 8.1 Port 1 Pin Configuration
8.2.2
Register Configuration and Description
Table 8.2 shows the port 1 register configuration.
Table 8.2
Port 1 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 1
PDR1
R/W
H'00
H'FFD4
Port control register 1
PCR1
W
H'00
H'FFE4
Port pull-up control register 1
PUCR1
R/W
H'00
H'FFE0
Port mode register 1
PMR1
R/W
H'00
H'FFC8
Rev. 6.00 Aug 04, 2006 page 205 of 680
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Section 8 I/O Ports
1. Port Data Register 1 (PDR1)
Bit
7
6
5
4
3
2
1
0
P1 7
P1 6
P1 5
P1 4
P1 3
P1 2
P1 1
P1 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR1 is an 8-bit register that stores data for port 1 pins P17 to P10. If port 1 is read while PCR1
bits are set to 1, the values stored in PDR1 are read, regardless of the actual pin states. If port 1 is
read while PCR1 bits are cleared to 0, the pin states are read.
Upon reset, PDR1 is initialized to H'00.
2. Port Control Register 1 (PCR1)
Bit
7
6
5
4
3
2
1
0
PCR1 7
PCR1 6
PCR1 5
PCR1 4
PCR1 3
PCR1 2
PCR1 1
PCR1 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR1 is an 8-bit register for controlling whether each of the port 1 pins P17 to P10 functions as an
input pin or output pin. Setting a PCR1 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR1 and in PDR1 are valid only
when the corresponding pin is designated in PMR1 as a general I/O pin.
Upon reset, PCR1 is initialized to H'00.
PCR1 is a write-only register, which is always read as all 1s.
3. Port Pull-up Control Register 1 (PUCR1)
Bit
7
6
5
4
3
2
1
0
PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR1 controls whether the MOS pull-up of each of the port 1 pins P17 to P10 is on or off. When
a PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR1 is initialized to H'00.
Rev. 6.00 Aug 04, 2006 page 206 of 680
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Section 8 I/O Ports
4. Port Mode Register 1 (PMR1)
Bit
7
6
5
4
3
2
1
0
IRQ3
IRQ2
IRQ1
IRQ4
TMIG
TMOFH
TMOFL
TMOW
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR1 is an 8-bit read/write register, controlling the selection of pin functions for port 1 pins.
Upon reset, PMR1 is initialized to H'00.
Bit 7: P17/IRQ3/TMIF pin function switch (IRQ3)
This bit selects whether pin P17/IRQ3/TMIF is used as P17 or as IRQ3/TMIF.
Bit 7
IRQ3
Description
0
Functions as P17 I/O pin
1
Functions as IRQ3/TMIF input pin
(initial value)
Note: Rising or falling edge sensing can be designated for IRQ3/TMIF. For details on TMIF
settings, see 3. Timer Control Register F (TCRF) in section 9.4.2.
Bit 6: P16/IRQ2 pin function switch (IRQ2)
This bit selects whether pin P16/IRQ2 is used as P16 or as IRQ2.
Bit 6
IRQ2
Description
0
Functions as P16 I/O pin
1
Functions as IRQ2 input pin
(initial value)
Note: Rising or falling edge sensing can be designated for IRQ2.
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Section 8 I/O Ports
Bit 5: P15/IRQ1/TMIC pin function switch (IRQ1)
This bit selects whether pin P15/IRQ1/TMIC is used as P15 or as IRQ1/TMIC.
Bit 5
IRQ1
Description
0
Functions as P15 I/O pin
1
Functions as IRQ1/TMIC input pin
(initial value)
Note: Rising or falling edge sensing can be designated for IRQ1/TMIC.
For details of TMIC pin setting, see 1. Timer mode register C (TMC) in section 9.3.2.
Bit 4: P14/IRQ4/ADTRG pin function switch (IRQ4)
This bit selects whether pin P14/IRQ4/ADTRG is used as P14 or as IRQ4/ADTRG.
Bit 4
IRQ4
Description
0
Functions as P14 I/O pin
1
Functions as IRQ4/ADTRG input pin
(initial value)
Note: For details of ADTRG pin setting, see section 12.3.2, Start of A/D Conversion by External
Trigger Input.
Bit 3: P13/TMIG pin function switch (TMIG)
This bit selects whether pin P13/TMIG is used as P13 or as TMIG.
Bit 3
TMIG
Description
0
Functions as P13 I/O pin
1
Functions as TMIG input pin
(initial value)
Bit 2: P12/TMOFH pin function switch (TMOFH)
This bit selects whether pin P12/TMOFH is used as P12 or as TMOFH.
Bit 2
TMOFH
Description
0
Functions as P12 I/O pin
1
Functions as TMOFH output pin
Rev. 6.00 Aug 04, 2006 page 208 of 680
REJ09B0145-0600
(initial value)
Section 8 I/O Ports
Bit 1: P11/TMOFL pin function switch (TMOFL)
This bit selects whether pin P11/TMOFL is used as P11 or as TMOFL.
Bit 1
TMOFL
Description
0
Functions as P11 I/O pin
1
Functions as TMOFL output pin
(initial value)
Bit 0: P10/TMOW pin function switch (TMOW)
This bit selects whether pin P10/TMOW is used as P10 or as TMOW.
Bit 0
TMOW
Description
0
Functions as P10 I/O pin
1
Functions as TMOW output pin
(initial value)
Rev. 6.00 Aug 04, 2006 page 209 of 680
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Section 8 I/O Ports
8.2.3
Pin Functions
Table 8.3 shows the port 1 pin functions.
Table 8.3
Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/IRQ3/TMIF
The pin function depends on bit IRQ3 in PMR1, bits CKSL2 to CKSL0 in TCRF,
and bit PCR17 in PCR1.
IRQ3
PCR17
CKSL2 to CKSL0
Pin function
0
0
1
1
*
0**
IRQ3/TMIF
input pin
Note: When this pin is used as the TMIF input pin, clear bit IEN3 to 0 in IENR1
to disable the IRQ3 interrupt.
P16/IRQ2
Not 0**
P17 output pin IRQ3 input pin
The pin function depends on bits IRQ2 in PMR1 and bit PCR16 in PCR1.
IRQ2
PCR16
Pin function
P15/IRQ1
TMIC
*
P17 input pin
0
0
P16 input pin
1
P16 output pin
1
*
IRQ2 input pin
The pin function depends on bit IRQ1 in PMR1, bits TMC2 to TMC0 in TMC, and
bit PCR15 in PCR1.
IRQ1
PCR15
TMC2 to TMC0
Pin function
0
0
1
1
*
Not 111
111
IRQ1 inpu
IRQ1/TMIC
input pin
t pin
Note: When this pin is used as the TMIC input pin, clear bit IEN1 to 0 in IENR1
to disable the IRQ1 interrupt.
P14/IRQ4
ADTRG
*
P15 input pin
P15 output pin
The pin function depends on bit IRQ4 in PMR1, bit TRGE in AMR, and bit PCR14
in PCR1.
IRQ4
PCR14
TRGE
Pin function
0
0
1
1
*
0
1
P14 output pin IRQ4 input pin IRQ4/ADTR
G input pin
Note: When this pin is used as the ADTRG input pin, clear bit IEN4 to 0 in
IENR1 to disable the IRQ4 interrupt.
*
P14 input pin
Rev. 6.00 Aug 04, 2006 page 210 of 680
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Section 8 I/O Ports
Pin
Pin Functions and Selection Method
P13/TMIG
The pin function depends on bit TMIG in PMR1 and bit PCR13 in PCR1.
TMIG
PCR13
Pin function
P12/TMOFH
0
0
P13 input pin
1
P13 output pin
1
*
TMIG input pin
The pin function depends on bit TMOFH in PMR1 and bit PCR12 in PCR1.
TMOFH
PCR12
Pin function
P11/TMOFL
0
0
P12 input pin
1
P12 output pin
1
*
TMOFH output pin
The pin function depends on bit TMOFL in PMR1 and bit PCR11 in PCR1.
TMOFL
PCR11
Pin function
P10/TMOW
0
0
P11 input pin
1
P11 output pin
1
*
TMOFL output pin
The pin function depends on bit TMOW in PMR1 and bit PCR10 in PCR1.
TMOW
PCR10
Pin function
0
0
P10 input pin
1
P10 output pin
1
*
TMOW output pin
*: Don’t care
8.2.4
Pin States
Table 8.4 shows the port 1 pin states in each operating mode.
Table 8.4
Port 1 Pin States
Pins
Reset
P17/IRQ3/TMIF
P16/IRQ2
P15/IRQ1/TMIC
P14/IRQ4/ADTRG
P13/TMIG
P12/TMOFH
P11/TMOFL
P10/TMOW
HighRetains
impedance previous
state
Note:
*
Sleep
Subsleep
Standby
Watch
Retains
previous
state
HighRetains
impedance* previous
state
Subactive
Active
Functional
Functional
A high-level signal is output when the MOS pull-up is in the on state.
Rev. 6.00 Aug 04, 2006 page 211 of 680
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Section 8 I/O Ports
8.2.5
MOS Input Pull-Up
Port 1 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR1 bit is cleared to 0, setting the corresponding PUCR1 bit to 1 turns on the MOS input pull-up
for that pin. The MOS input pull-up function is in the off state after a reset.
PCR1n
0
0
1
PUCR1n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 212 of 680
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Section 8 I/O Ports
8.3
Port 2
8.3.1
Overview
Port 2 is an 8-bit I/O port. Figure 8.2 shows its pin configuration.
In the F-ZTAT version, the on-chip pull-up MOS for pin P24 is on during the reset period. It turns
off and normal operation resumes after the reset is cleared. The pull-up MOS is controlled by
hardware; it cannot be manipulated by a user program. This should be considered when making
connections to external circuitry. Note that the mask ROM and ZTAT versions do not have this
function.
P27
P26
P25
P24
Port 2
P23
P22/SO1
P21/SI1
P20/SCK1
Figure 8.2 Port 2 Pin Configuration
8.3.2
Register Configuration and Description
Table 8.5 shows the port 2 register configuration.
Table 8.5
Port 2 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 2
PDR2
R/W
H'00
H'FFD5
Port control register 2
PCR2
W
H'00
H'FFE5
Port mode register 2
PMR2
R/W
H'D8*
H'FFC9
Port mode register 4
PMR4
R/W
H'00
H'FFCB
Note:
*
H'58 in the H8/38347 Group and H8/38447 Group.
Rev. 6.00 Aug 04, 2006 page 213 of 680
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Section 8 I/O Ports
1. Port Data Register 2 (PDR2)
Bit
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR2 is an 8-bit register that stores data for port 2 pins P27 to P20. If port 2 is read while PCR2
bits are set to 1, the values stored in PDR2 are read, regardless of the actual pin states. If port 2 is
read while PCR2 bits are cleared to 0, the pin states are read.
Upon reset, PDR2 is initialized to H'00.
2. Port Control Register 2 (PCR2)
Bit
7
6
5
4
3
2
1
0
PCR27
PCR26
PCR25
PCR24
PCR23
PCR22
PCR21
PCR20
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR2 is an 8-bit register for controlling whether each of the port 2 pins P27 to P20 functions as an
input pin or output pin. Setting a PCR2 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR2 and PDR2 are valid only
when the corresponding pin is designated in PMR1 as a general I/O pin.
Upon reset, PCR2 is initialized to H'00.
PCR2 is a write-only register, which is always read as all 1s.
3. Port Mode Register 2 (PMR2)
• H8/3847R Group, H8/3847S Group
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
SO1
SI1
SCK1
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register that controls the selection of pin functions for port 2 pins P20,
P21, and P23, and the PMOS on/off state for the P22/SO1 pin.
Upon reset, PMR2 is initialized to H'D8.
Rev. 6.00 Aug 04, 2006 page 214 of 680
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Section 8 I/O Ports
• H8/38347 Group and H8/38447 Group
Bit
7
6
5
4
3
2
1
0
EXCL
—
POF1
—
—
SO1
SI1
SCK1
Initial value
0
1
0
1
1
0
0
0
Read/Write
R/W
—
R/W
—
—
R/W
R/W
R/W
PMR2 is an 8-bit read/write register that controls the selection of pin functions for pins P20, P21,
and P23, the PMOS on/off state for the P22/SO1 pin, and external clock input to pin P31.
Upon reset, PMR2 is initialized to H'58.
• H8/3847R Group and H8/3847S Group
Bit 7: Reserved bit
Bit 7 is reserved. It is always read as 1 and cannot be modified.
• H8/38347 Group and H8/38447 Group
Bit 7: P31/UD/EXCL pin function switch (EXCL)
This bit selects whether pin P31/UD/EXCL is used as P31/UD or as EXCL. When the pin is used
as EXCL an external clock should be input to it. See section 4, Clock Pulse Generators, for a
connection example.
Bit 7
EXCL
Description
0
Functions as P31/UD I/O pin
1
Functions as EXCL input pin
(initial value)
Bits 6, 4, and 3: Reserved bits
Bits 6, 4, and 3 are reserved; they are always read as 1 and cannot be modified.
Bit 5: P22/SO1 pin PMOS control (POF1)
This bit controls the on/off state of the P22/SO1 pin output buffer PMOS.
Bit 5
POF1
Description
0
CMOS output
1
NMOS open-drain output
(initial value)
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Section 8 I/O Ports
Bit 2: P22/SO1 pin function switch (SO1)
This bit selects whether pin P22/SO1 is used as P22 or as SO1.
Bit 2
SO1
Description
0
Functions as P22 I/O pin
1
Functions as SO1 output pin
(initial value)
Bit 1: P21/SI1 pin function switch (SI1)
This bit selects whether pin P21/SI1 is used as P21 or as SI1.
Bit 1
SI1
Description
0
Functions as P21 I/O pin
1
Functions as SI1 input pin
(initial value)
Bit 0: P20/SCK1 pin function switch (SCK1)
This bit selects whether pin P20/SCK1 is used as P20 or as SCK1.
Bit 0
SCK1
Description
0
Functions as P20 I/O pin
1
Functions as SCK1 I/O pin
(initial value)
4. Port Mode Register 4 (PMR4)
Bit
7
6
5
4
3
2
1
0
NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR4 is an 8-bit read/write register that controls whether individual port 2 pins are CMOS
outputs or NMOS open-drain outputs when 1 is set in PCR2.
Upon reset, PMR4 is initialized to H'00.
Rev. 6.00 Aug 04, 2006 page 216 of 680
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Section 8 I/O Ports
Bit n: NMOS open-drain output select (NMODn)
These bits select NMOS open-drain output when pin P2n is used as an output pin.
Bit n
NMODn
Description
0
CMOS output
1
NMOS open-drain output
(initial value)
(n = 7 to 0)
8.3.3
Pin Function
Table 8.6 shows the port 2 pin functions.
Table 8.6
Port 2 Pin Functions
Pin
Pin Functions and Selection Method
P27 to P23
The pin function depends on the corresponding bit in PCR2.
(n = 7 to 3)
PCR2n
Pin function
P22/SO1
0
0
P22 input pin
1
P22 output pin
1
*
SO1 output pin
The pin function depends on bit SI1 in PMR2 and bit PCR21 in PCR2.
SI1
PCR21
Pin function
P20/SCK1
1
P2n output pin
The pin function depends on bit SO1 in PMR2 and bit PCR22 in PCR2.
SO1
PCR22
Pin function
P21/SI1
0
P2n input pin
0
0
P21 input pin
1
P21 output pin
1
*
SI1 input pin
The pin function depends on bit SCK1 in PMR2 and bit PCR20 in PCR2.
SCK1
PCR20
Pin function
0
0
P20 input pin
1
P20 output pin
1
*
SCK1 I/O pin
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 217 of 680
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Section 8 I/O Ports
8.3.4
Pin States
Table 8.7 shows the port 2 pin states in each operating mode.
Table 8.7
Port 2 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P27 to P25
Highimpedance
Retains
previous
state
Functional
Functional
Pull-up
MOS on
Retains
previous
state
Highimpedance
P24*1
Retains
previous
state
P24*2
P23
Highimpedance
P22/SO1
P21/SI1
P20/SCK1
Highimpedance
Notes: 1. Applies to the F-ZTAT version of the H8/38347 Group and H8/38447 Group.
2. Applies to H8/3847R Group and H8/3847S Group. Also applies to the mask ROM
version of the H8/38347 Group and H8/38447 Group.
Rev. 6.00 Aug 04, 2006 page 218 of 680
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Section 8 I/O Ports
8.4
Port 3
8.4.1
Overview
Port 3 is an 8-bit I/O port, configured as shown in figure 8.3.
P3 7 /AEVL
P3 6 /AEVH
P3 5 /TXD31
P3 4 /RXD31
Port 3
P3 3 /SCK 31
P3 2 /RESO*1
P3 1 /UD/EXCL*2
P3 0 /PWM
Notes: 1. The RESO function is not implemented in the H8/38347 Group and H8/38447 Group.
2. The EXCL function only applies to the H8/38347 Group and H8/38447 Group.
Figure 8.3 Port 3 Pin Configuration
8.4.2
Register Configuration and Description
Table 8.8 shows the port 3 register configuration.
Table 8.8
Port 3 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 3
PDR3
R/W
H'00
H'FFD6
Port control register 3
PCR3
W
H'00
H'FFE6
Port pull-up control register 3
PUCR3
R/W
H'00
H'FFE1
Port mode register 2
PMR2
R/W
H'D8*
H'FFC9
Port mode register 3
PMR3
R/W
H'04
H'FFCA
Note:
*
H'58 in the H8/38347 Group and H8/38447 Group.
Rev. 6.00 Aug 04, 2006 page 219 of 680
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Section 8 I/O Ports
1. Port Data Register 3 (PDR3)
Bit
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P3 3
P32
P31
P3 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR3 is an 8-bit register that stores data for port 3 pins P37 to P30. If port 3 is read while PCR3
bits are set to 1, the values stored in PDR3 are read, regardless of the actual pin states. If port 3 is
read while PCR3 bits are cleared to 0, the pin states are read.
Upon reset, PDR3 is initialized to H'00.
2. Port Control Register 3 (PCR3)
Bit
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR34
PCR3 3
PCR3 2
PCR31
PCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR3 is an 8-bit register for controlling whether each of the port 3 pins P37 to P30 functions as an
input pin or output pin. Setting a PCR3 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR3 and in PDR3 are valid only
when the corresponding pin is designated in PMR3 as a general I/O pin.
Upon reset, PCR3 is initialized to H'00.
PCR3 is a write-only register, which is always read as all 1s.
3. Port Pull-up Control Register 3 (PUCR3)
Bit
7
6
5
4
3
2
1
0
PUCR37 PUCR36 PUCR3 5 PUCR34 PUCR3 3 PUCR3 2 PUCR31 PUCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR3 controls whether the MOS pull-up of each of the port 3 pins P37 to P30 is on or off. When
a PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR3 is initialized to H'00.
Rev. 6.00 Aug 04, 2006 page 220 of 680
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Section 8 I/O Ports
4. Port Mode Register 3 (PMR3)
Bit
7
6
5
4
3
2
1
0
AEVL
AEVH
WDCKS
NCS
IRQ0
RESO*
UD
PWM
Initial value
0
0
0
0
0
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR3 is an 8-bit read/write register, controlling the selection of pin functions for port 3 pins.
Upon reset, PMR3 is initialized to H'04.
Note: * The RESO bit is not implemented in the H8/38347 Group and H8/38447 Group.
Bit 7: P37/AEVL pin function switch (AEVL)
This bit selects whether pin P37/AEVL is used as P37 or as AEVL.
Bit 7
AEVL
Description
0
Functions as P37 I/O pin
1
Functions as AEVL input pin
(initial value)
Bit 6: P36/AEVH pin function switch (AEVH)
This bit selects whether pin P36/AEVH is used as P36 or as AEVH.
Bit 6
AEVH
Description
0
Functions as P36 I/O pin
1
Functions as AEVH input pin
(initial value)
Bit 5: Watchdog timer source clock select (WDCKS)
This bit selects the watchdog timer source clock.
Bit 5
WDCKS
Description
0
φ/8192 selected
1
φw/32 selected
(initial value)
Rev. 6.00 Aug 04, 2006 page 221 of 680
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Section 8 I/O Ports
Bit 4: TMIG noise canceler select (NCS)
This bit controls the noise canceler for the input capture input signal (TMIG).
Bit 4
NCS
Description
0
Noise cancellation function not used
1
Noise cancellation function used
(initial value)
Bit 3: P43/IRQ0 pin function switch (IRQ0)
This bit selects whether pin P43/IRQ0 is used as P43 or as IRQ0.
Bit 3
IRQ0
IRQ
Description
0
Functions as P43 input pin
1
Functions as IRQ0 input pin
(initial value)
Bit 2: P32/RESO pin function switch (RESO)
This bit selects whether pin P32/RESO is used as P32 or as RESO.
Bit 2
RESO
Description
0
Functions as P32 I/O pin
1
Functions as RESO output pin
(initial value)
In the H8/38347 Group and H8/38447 Group this bit is reserved and cannot be written to.
Bit 1: P31/UD pin function switch (UD)
This bit selects whether pin P31/UD is used as P31 or as UD.
Bit 1
UD
Description
0
Functions as P31 I/O pin
1
Functions as UD input pin
Rev. 6.00 Aug 04, 2006 page 222 of 680
REJ09B0145-0600
(initial value)
Section 8 I/O Ports
In the H8/38347 Group and H8/38447 Group this pin is a combined P31/UD/EXCL pin. Refer to
the description of port mode register 2 in 8.3, Port 2, for details on switching to the EXCL pin
function.
Bit 0: P30/PWM pin function switch (PWM)
This bit selects whether pin P30/PWM is used as P30 or as PWM.
Bit 0
PWM
Description
0
Functions as P30 I/O pin
1
Functions as PWM output pin
8.4.3
(initial value)
Pin Functions
Table 8.9 shows the port 3 pin functions.
Table 8.9
Port 3 Pin Functions
Pin
Pin Functions and Selection Method
P37/AEVL
The pin function depends on bit SO1 in PMR3 and bit PCR32 in PCR3.
AEVL
PCR37
Pin function
P36/AEVH
1
*
AEVL input pin
0
0
P36 input pin
1
P36 output pin
1
*
AEVH input pin
The pin function depends on bit TE in SCR3-1, bit SPC31 in SPCR, and bit
PCR35 in PCR3.
SPC31
TE
PCR35
Pin function
P34/RXD31
1
P37 output pin
The pin function depends on bit AEVH in PMR3 and bit PCR36 in PCR3.
AEVH
PCR36
Pin function
P35/TXD31
0
0
P37 input pin
0
0
0
P35 input pin
1
P35output pin
1
1
*
TXD31 output pin
The pin function depends on bit RE in SCR3-1 and bit PCR34 in PCR3.
RE
PCR34
Pin function
0
0
P34 input pin
1
P34 output pin
1
*
RXD31 input pin
Rev. 6.00 Aug 04, 2006 page 223 of 680
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Section 8 I/O Ports
Pin
Pin Functions and Selection Method
P33/SCK31
The pin function depends on bits CKE1, CKE0, and SMR31 in SCR3-1 and bit
PCR33 in PCR3.
CKE1
CKE0
COM31
PCR33
Pin function
P32/RESO
(H8/3847R,
H8/3847S)
•
1
0
1
P33 input pin P33 output pin
*
SCK31
output pin
H8/3847R Group, H8/3847S Group
RESO
PCR32
Pin function
•
P31/UD
(H8/3847R,
H8/3847S)
•
0
0
P32 input pin
1
P32 output pin
1
*
RESO output pin
H8/38347 Group, H8/38447 Group
The pin function depends on bit PCR32 in PCR3.
PCR32
Pin function
0
P32 input pin
1
P32 output pin
H8/3847R Group, H8/3847S Group
The pin function depends on bit UD in PMR3 and bit PCR31 in PCR3.
UD
PCR31
Pin function
•
0
0
P31 input pin
1
P31 output pin
1
*
UD input pin
H8/38347 Group, H8/38447 Group
The pin function depends on bit EXCL in PMR2, bit UD in PMR3, and bit PCR31
in PCR3.
EXCL
UD
PCR31
Pin function
P30/PWM
0
1
*
*
*
SCK31
input pin
1
*
The pin function depends on bit RESO in PMR3 and bit PCR32 in PCR3.
P32
(H8/38347,
H8/38447)
P31/UD/EXCL
(H8/38347,
H8/38447)
0
0
0
0
0
P31 input pin
1
P31 output pin
1
*
UD input pin
1
*
*
EXCL input pin
The pin function depends on bit PWM in PMR3 and bit PCR30 in PCR3.
PWM
PCR30
Pin function
0
0
P30 input pin
1
P30 output pin
1
*
PWM output pin
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 224 of 680
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Section 8 I/O Ports
8.4.4
Pin States
Table 8.10 shows the port 3 pin states in each operating mode.
Table 8.10 Port 3 Pin States
Pins
Reset
Sleep
Subsleep
Standby
P37/AEVL
P36/AEVH
P35/TXD31
P34/RXD31
P33/SCK31
Highimpedance
Retains
previous
state
Retains
previous
state
HighRetains
impedance*1 previous
state
P32/RESO*2
Reset output
P32*3
P31/UD*2
P31/UD/EXCL*3
P30/PWM
Highimpedance
Watch
Subactive
Active
Functional
Functional
Notes: 1. A high-level signal is output when the MOS pull-up is in the on state.
2. Applies to H8/3847R Group and H8/3847S Group.
3. Applies to H8/38347 Group and H8/38447 Group.
8.4.5
MOS Input Pull-Up
Port 3 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR3 bit is cleared to 0, setting the corresponding PUCR3 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR3n
0
0
1
PUCR3n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 225 of 680
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Section 8 I/O Ports
8.5
Port 4
8.5.1
Overview
Port 4 is a 3-bit I/O port and 1-bit input port, configured as shown in figure 8.4.
P4 3 /IRQ0
P4 2 /TXD32
Port 4
P4 1 /RXD32
P4 0 /SCK32
Figure 8.4 Port 4 Pin Configuration
8.5.2
Register Configuration and Description
Table 8.11 shows the port 4 register configuration.
Table 8.11 Port 4 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 4
PDR4
R/W
H'F8
H'FFD7
Port control register 4
PCR4
W
H'F8
H'FFE7
1. Port Data Register 4 (PDR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
P43
P4 2
P4 1
P4
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
R
R/W
R/W
R/W
0
PDR4 is an 8-bit register that stores data for port 4 pins P42 to P40. If port 4 is read while PCR4
bits are set to 1, the values stored in PDR4 are read, regardless of the actual pin states. If port 4 is
read while PCR4 bits are cleared to 0, the pin states are read.
Upon reset, PDR4 is initialized to H'F8.
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Section 8 I/O Ports
2. Port Control Register 4 (PCR4)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
PCR42
PCR4 1
PCR4 0
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
PCR4 is an 8-bit register for controlling whether each of port 4 pins P42 to P40 functions as an
input pin or output pin. Setting a PCR4 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR4 and PDR4 settings are valid when the
corresponding pins are designated for general-purpose input/output by SCR3-2.
Upon reset, PCR4 is initialized to H'F8.
PCR4 is a write-only register, which always reads all 1s.
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Section 8 I/O Ports
8.5.3
Pin Functions
Table 8.12 shows the port 4 pin functions.
Table 8.12 Port 4 Pin Functions
Pin
Pin Functions and Selection Method
P43/IRQ0
The pin function depends on bit IRQ0 in PMR3.
IRQ0
Pin function
P42/TXD32
0
0
1
1
*
TXD32 output pin
1
P42 output pin
0
P42 input pin
The pin function depends on bit RE in SCR3-2 and bit PCR41 in PCR4.
RE
PCR41
Pin function
P40/SCK32
1
IRQ0 input pin
The pin function depends on bit TE in SCR3-2, bit SPC32 in SPCR, and bit
PCR42 in PCR4.
SPC32
TE
PCR42
Pin function
P41/RXD32
0
P43 input pin
0
1
*
RXD32 input pin
1
P41 output pin
0
P41 input pin
The pin function depends on bits CKE1 and CKE0 in SCR3-2, bit COM32 in
SMR32, and bit PCR40 in PCR4.
CKE1
CKE0
COM32
PCR40
Pin function
0
0
0
0
P40 input pin
1
1
P40 output pin
1
*
*
SCK32
output pin
1
*
*
*
SCK32
input pin
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 228 of 680
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Section 8 I/O Ports
8.5.4
Pin States
Table 8.13 shows the port 4 pin states in each operating mode.
Table 8.13 Port 4 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P43/IRQ0
P42/TXD32
P41/RXD32
P40/SCK32
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
Rev. 6.00 Aug 04, 2006 page 229 of 680
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Section 8 I/O Ports
8.6
Port 5
8.6.1
Overview
Port 5 is an 8-bit I/O port, configured as shown in figure 8.5.
P57/WKP7/SEG8
P56/WKP6/SEG7
P55/WKP5/SEG6
Port 5
P54/WKP4/SEG5
P53/WKP3/SEG4
P52/WKP2/SEG3
P51/WKP1/SEG2
P50/WKP0/SEG1
Figure 8.5 Port 5 Pin Configuration
8.6.2
Register Configuration and Description
Table 8.14 shows the port 5 register configuration.
Table 8.14 Port 5 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 5
PDR5
R/W
H'00
H'FFD8
Port control register 5
PCR5
W
H'00
H'FFE8
Port pull-up control register 5
PUCR5
R/W
H'00
H'FFE2
Port mode register 5
PMR5
R/W
H'00
H'FFCC
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Section 8 I/O Ports
1. Port Data Register 5 (PDR5)
Bit
7
6
5
4
3
2
1
0
P5 7
P5 6
P55
P5 4
P53
P52
P51
P5 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR5 is an 8-bit register that stores data for port 5 pins P57 to P50. If port 5 is read while PCR5
bits are set to 1, the values stored in PDR5 are read, regardless of the actual pin states. If port 5 is
read while PCR5 bits are cleared to 0, the pin states are read.
Upon reset, PDR5 is initialized to H'00.
2. Port Control Register 5 (PCR5)
Bit
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR5 is an 8-bit register for controlling whether each of the port 5 pins P57 to P50 functions as an
input pin or output pin. Setting a PCR5 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR5 and PDR5 settings are valid when the
corresponding pins are designated for general-purpose input/output by PMR5 and bits SGS3 to
SGS0 in LPCR.
Upon reset, PCR5 is initialized to H'00.
PCR5 is a write-only register, which is always read as all 1s.
3. Port Pull-Up Control Register 5 (PUCR5)
Bit
7
6
5
4
3
2
1
0
PUCR57 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR5 controls whether the MOS pull-up of each of port 5 pins P57 to P50 is on or off. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
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Section 8 I/O Ports
Upon reset, PUCR5 is initialized to H'00.
4. Port Mode Register 5 (PMR5)
Bit
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PMR5 is an 8-bit read/write register, controlling the selection of pin functions for port 5 pins.
Upon reset, PMR5 is initialized to H'00.
Bit n: P5n/WKPn/SEGn+1 pin function switch (WKPn)
When pin P5n/WKPn/SEGn+1 is not used as SEGn+1, these bits select whether the pin is used as P5n
or WKPn.
Bit n
WKPn
Description
0
Functions as P5n I/O pin
1
Functions as WKPn input pin
(initial value)
(n = 7 to 0)
Note: For use as SEGn+1, see section 13.2.1, LCD Port Control Register (LPCR).
8.6.3
Pin Functions
Table 8.15 shows the port 5 pin functions.
Table 8.15 Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P57/WKP7/
SEG8 to
The pin function depends on bit WKPn in PMR5, bit PCR5n in PCR5, and bits
SEG8 to SGS3 to SGS0 in LPCR.
P50/WKP0/
SEG1
SGS3 to SGS0
WKPn
PCR5n
Pin function
0***
0
0
P5n input pin
1
P5n output pin
1
*
WKPn
input pin
1***
*
*
SEGn+1
output pin
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 232 of 680
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Section 8 I/O Ports
8.6.4
Pin States
Table 8.16 shows the port 5 pin states in each operating mode.
Table 8.16 Port 5 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P57/WKP7/
SEG8 to P50/
WKP0/SEG1
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance*
Retains
previous
state
Functional
Functional
Note:
*
8.6.5
A high-level signal is output when the MOS pull-up is in the on state.
MOS Input Pull-Up
Port 5 has a built-in MOS input pull-up function that can be controlled by software. When a
PCR5 bit is cleared to 0, setting the corresponding PUCR5 bit to 1 turns on the MOS pull-up for
that pin. The MOS pull-up function is in the off state after a reset.
PCR5n
0
0
1
PUCR5n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
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Section 8 I/O Ports
8.7
Port 6
8.7.1
Overview
Port 6 is an 8-bit I/O port. The port 6 pin configuration is shown in figure 8.6.
P67/SEG16
P66/SEG15
P65/SEG14
P64/SEG13
Port 6
P63/SEG12
P62/SEG11
P61/SEG10
P60/SEG9
Figure 8.6 Port 6 Pin Configuration
8.7.2
Register Configuration and Description
Table 8.17 shows the port 6 register configuration.
Table 8.17 Port 6 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 6
PDR6
R/W
H'00
H'FFD9
Port control register 6
PCR6
W
H'00
H'FFE9
Port pull-up control register 6
PUCR6
R/W
H'00
H'FFE3
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Section 8 I/O Ports
1. Port Data Register 6 (PDR6)
Bit
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P6 3
P62
P61
P6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR6 is an 8-bit register that stores data for port 6 pins P67 to P60.
If port 6 is read while PCR6 bits are set to 1, the values stored in PDR6 are read, regardless of the
actual pin states. If port 6 is read while PCR6 bits are cleared to 0, the pin states are read.
Upon reset, PDR6 is initialized to H'00.
2. Port Control Register 6 (PCR6)
Bit
7
6
5
4
3
2
1
0
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR6 is an 8-bit register for controlling whether each of the port 6 pins P67 to P60 functions as an
input pin or output pin.
Setting a PCR6 bit to 1 makes the corresponding pin (P67 to P60) an output pin, while clearing the
bit to 0 makes the pin an input pin. PCR6 and PDR6 settings are valid when the corresponding
pins are designated for general-purpose input/output by bits SGS3 to SGS0 in LPCR.
Upon reset, PCR6 is initialized to H'00.
PCR6 is a write-only register, which always reads all 1s.
Rev. 6.00 Aug 04, 2006 page 235 of 680
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Section 8 I/O Ports
3. Port Pull-Up Control Register 6 (PUCR6)
Bit
7
6
5
4
3
2
1
0
PUCR67 PUCR66 PUCR6 5 PUCR64 PUCR6 3 PUCR6 2 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PUCR6 controls whether the MOS pull-up of each of the port 6 pins P67 to P60 is on or off. When
a PCR6 bit is cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for
the corresponding pin, while clearing the bit to 0 turns off the MOS pull-up.
Upon reset, PUCR6 is initialized to H'00.
8.7.3
Pin Functions
Table 8.18 shows the port 6 pin functions.
Table 8.18 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/SEG16
to P60/SEG9
The pin function depends on bit PCR6n in PCR6 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 0)
SGS3 to SGS0
PCR6n
Pin function
00**, 010*
0
P6n input pin
011**, 1***
*
SEGn+9 output pin
1
P6n output pin
*: Don’t care
8.7.4
Pin States
Table 8.19 shows the port 6 pin states in each operating mode.
Table 8.19 Port 6 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P67/SEG16 to
P60/SEG9
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance*
Retains
previous
state
Functional
Functional
Note:
*
A high-level signal is output when the MOS pull-up is in the on state.
Rev. 6.00 Aug 04, 2006 page 236 of 680
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Section 8 I/O Ports
8.7.5
MOS Input Pull-Up
Port 6 has a built-in MOS pull-up function that can be controlled by software. When a PCR6 bit is
cleared to 0, setting the corresponding PUCR6 bit to 1 turns on the MOS pull-up for that pin. The
MOS pull-up function is in the off state after a reset.
PCR6n
0
0
1
PUCR6n
0
1
*
MOS input pull-up
Off
On
Off
(n = 7 to 0)
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 237 of 680
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Section 8 I/O Ports
8.8
Port 7
8.8.1
Overview
Port 7 is an 8-bit I/O port, configured as shown in figure 8.7.
P77/SEG24
P76/SEG23
P75/SEG22
P74/SEG21
Port 7
P73/SEG20
P72/SEG19
P71/SEG18
P70/SEG17
Figure 8.7 Port 7 Pin Configuration
8.8.2
Register Configuration and Description
Table 8.20 shows the port 7 register configuration.
Table 8.20 Port 7 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 7
PDR7
R/W
H'00
H'FFDA
Port control register 7
PCR7
W
H'00
H'FFEA
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Section 8 I/O Ports
1. Port Data Register 7 (PDR7)
Bit
7
6
5
4
3
2
1
0
P7 7
P7 6
P75
P7 4
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR7 is an 8-bit register that stores data for port 7 pins P77 to P70. If port 7 is read while PCR7
bits are set to 1, the values stored in PDR7 are read, regardless of the actual pin states. If port 7 is
read while PCR7 bits are cleared to 0, the pin states are read.
Upon reset, PDR7 is initialized to H'00.
2. Port Control Register 7 (PCR7)
Bit
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR7 is an 8-bit register for controlling whether each of the port 7 pins P77 to P70 functions as an
input pin or output pin. Setting a PCR7 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR7 and PDR7 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR7 is initialized to H'00.
PCR7 is a write-only register, which always reads as all 1s.
Rev. 6.00 Aug 04, 2006 page 239 of 680
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Section 8 I/O Ports
8.8.3
Pin Functions
Table 8.21 shows the port 7 pin functions.
Table 8.21 Port 7 Pin Functions
Pin
Pin Functions and Selection Method
P77/SEG24
to P70/SEG17
The pin function depends on bit PCR7n in PCR7 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 0)
SGS3 to SGS0
PCR7n
Pin function
00**
0
P7n input pin
1
P7n output pin
01**, 1***
*
SEGn+17 output pin
*: Don’t care
8.8.4
Pin States
Table 8.22 shows the port 7 pin states in each operating mode.
Table 8.22 Port 7 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P77/SEG24
to
P70/SEG17
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
Rev. 6.00 Aug 04, 2006 page 240 of 680
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Section 8 I/O Ports
8.9
Port 8
8.9.1
Overview
Port 8 is an 8-bit I/O port configured as shown in figure 8.8.
P87/SEG32
P86/SEG31
P85/SEG30
P84/SEG29
Port 8
P83/SEG28
P82/SEG27
P81/SEG26
P80/SEG25
Figure 8.8 Port 8 Pin Configuration
8.9.2
Register Configuration and Description
Table 8.23 shows the port 8 register configuration.
Table 8.23 Port 8 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 8
PDR8
R/W
H'00
H'FFDB
Port control register 8
PCR8
W
H'00
H'FFEB
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Section 8 I/O Ports
1. Port Data Register 8 (PDR8)
Bit
7
6
5
4
3
2
1
0
P8 7
P8 6
P85
P8 4
P83
P82
P81
P8 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR8 is an 8-bit register that stores data for port 8 pins P87 to P80. If port 8 is read while PCR8
bits are set to 1, the values stored in PDR8 are read, regardless of the actual pin states. If port 8 is
read while PCR8 bits are cleared to 0, the pin states are read.
Upon reset, PDR8 is initialized to H'00.
2. Port Control Register 8 (PCR8)
Bit
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR8 is an 8-bit register for controlling whether each of the port 8 pins P87 to P80 functions as an
input or output pin. Setting a PCR8 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. PCR8 and PDR8 settings are valid when the
corresponding pins are designated for general-purpose input/output by bits SGS3 to SGS0 in
LPCR.
Upon reset, PCR8 is initialized to H'00.
PCR8 is a write-only register, which is always read as all 1s.
Rev. 6.00 Aug 04, 2006 page 242 of 680
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Section 8 I/O Ports
8.9.3
Pin Functions
Table 8.24 shows the port 8 pin functions.
Table 8.24 Port 8 Pin Functions
Pin
Pin Functions and Selection Method
P87/SEG32
to P80/SEG25
The pin function depends on bit PCR8n in PCR8 and bits SGS3 to SGS0 in
LPCR.
(n = 7 to 0)
SGS3 to SGS0
PCR8n
Pin function
000*
1
P8n output pin
0
P8n input pin
001*, 01**,1***
*
SEGn+25 output pin
*: Don’t care
8.9.4
Pin States
Table 8.25 shows the port 8 pin states in each operating mode.
Table 8.25 Port 8 Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
P87/SEG32 to
P80/SEG25
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
Rev. 6.00 Aug 04, 2006 page 243 of 680
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Section 8 I/O Ports
8.10
Port 9
8.10.1
Overview
Port 9 is an 8-bit I/O port. Figure 8.9 shows its pin configuration.
P97/SEG40/CL1*
P96/SEG39/CL2*
P95/SEG38/DO*
P94/SEG37/M*
Port 9
P93/SEG36
P92/SEG35
P91/SEG34
P90/SEG33
Note: * The CL1, CL2, DO, and M functions are not implemented on the H8/38347 Group and
H8/38447 Group.
Figure 8.9 Port 9 Pin Configuration
8.10.2
Register Configuration and Description
Table 8.26 shows the port 9 register configuration.
Table 8.26 Port 9 Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register 9
PDR9
R/W
H'00
H'FFDC
Port control register 9
PCR9
R
H'00
H'FFEC
Rev. 6.00 Aug 04, 2006 page 244 of 680
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Section 8 I/O Ports
1. Port Data Register 9 (PDR9)
Bit
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDR9 is an 8-bit register that stores data for port 9 pins P97 to P90. If port 9 is read while PCR9
bits are set to 1, the values stored in PDR9 are read, regardless of the actual pin states. If port 9 is
read while PCR9 bits are cleared to 0, the pin states are read.
Upon reset, PDR9 is initialized to H'00.
2. Port Control Register 9 (PCR9)
Bit
7
6
5
4
3
2
1
0
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCR9 is an 8-bit register for controlling whether each of the port 9 pins P97 to P90 functions as an
input pin or output pin. Setting a PCR9 bit to 1 makes the corresponding pin an output pin, while
clearing the bit to 0 makes the pin an input pin. The settings in PCR9 and PDR9 are valid only
when the corresponding pin is designated by bits SGS3 to SGS0 in LPCR as a general I/O pin.
Upon reset, PCR9 is initialized to H'00.
PCR9 is a write-only register, which is always read as all 1s.
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Section 8 I/O Ports
8.10.3
Pin Functions
Table 8.27 shows the port 9 pin functions. The SGX = 0 setting also functions on the H8/38347
and H8/38447.
Table 8.27 Port 9 Pin Functions
Pin
Pin Functions and Selection Method
P97/SEG40/CL1
The pin function depends on bit PCR97 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR97
Pin function
P96/SEG39/CL2
1
P97 output pin
0000
1
*
CL1
output pin
0000
0
0
P96 input pin
1
P96 output pin
Not 0000
0
*
SEG39
output pin
0000
1
*
CL2
output pin
The pin function depends on bit PCR95 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR95
Pin function
P94/SEG37/M
0
P97 input pin
Not 0000
0
*
SEG40
output pin
The pin function depends on bit PCR96 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR96
Pin function
P95/SEG38/DO
0000
0
0000
0
0
P95 input pin
1
P95 output pin
Not 0000
0
*
SEG38
output pin
0000
1
*
DO
output pin
The pin function depends on bit PCR94 in PCR9 and bits SGX and SGS3 to
SGS0 in LPCR.
SGS3 to SGS0
SGX
PCR94
Pin function
0000
0
0
P94 input pin
1
P94 output pin
Not 0000
0
*
SEG37
output pin
0000
1
*
M output pin
*: Don’t care
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Section 8 I/O Ports
Pin
Pin Functions and Selection Method
P93/SEG36 to
P90/SEG33
The pin function depends on bit PCR9n in PCR9 and bits SGS3 to SGS0 in
LPCR.
(n = 3 to 0)
SGS3 to SGS0
PCR9n
Pin function
0000
0
1
P9n input pin
P9n output pin
Not 0000
*
SEGn+33 output pin
*: Don’t care
8.10.4
Pin States
Table 8.28 shows the port 9 pin states in each operating mode.
Table 8.28 Port 9 Pin States
Pins
Reset
P97/SEG40/CL1 HighP96/SEG39/CL2 impedance
P95/SEG38/DO
P94/SEG37/M
P93/SEG36 to
P90/SEG33
Sleep
Subsleep
Standby
Watch
Subactive
Active
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
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Section 8 I/O Ports
8.11
Port A
8.11.1
Overview
Port A is a 4-bit I/O port, configured as shown in figure 8.10.
PA3/COM4
PA2/COM3
Port A
PA1/COM2
PA0/COM1
Figure 8.10 Port A Pin Configuration
8.11.2
Register Configuration and Description
Table 8.29 shows the port A register configuration.
Table 8.29 Port A Registers
Name
Abbr.
R/W
Initial Value
Address
Port data register A
PDRA
R/W
H'F0
H'FFDD
Port control register A
PCRA
W
H'F0
H'FFED
1. Port Data Register A (PDRA)
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
Read/Write
—
—
—
—
3
0
2
1
PA 2
PA 1
0
0
0
0
R/W
R/W
R/W
R/W
PA 3
PA 0
PDRA is an 8-bit register that stores data for port A pins PA3 to PA0. If port A is read while
PCRA bits are set to 1, the values stored in PDRA are read, regardless of the actual pin states. If
port A is read while PCRA bits are cleared to 0, the pin states are read.
Upon reset, PDRA is initialized to H'F0.
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Section 8 I/O Ports
2. Port Control Register A (PCRA)
Bit
7
6
5
4
—
—
—
—
Initial value
1
1
1
1
Read/Write
—
—
—
—
3
0
2
1
PCRA 2
PCRA 1
0
0
0
0
R/W
R/W
R/W
R/W
PCRA 3
PCRA 0
PCRA controls whether each of port A pins PA3 to PA0 functions as an input pin or output pin.
Setting a PCRA bit to 1 makes the corresponding pin an output pin, while clearing the bit to 0
makes the pin an input pin. PCRA and PDRA settings are valid when the corresponding pins are
designated for general-purpose input/output by LPCR.
Upon reset, PCRA is initialized to H'F0.
PCRA is a write-only register, which always reads all 1s.
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Section 8 I/O Ports
8.11.3
Pin Functions
Table 8.30 shows the port A pin functions.
Table 8.30 Port A Pin Functions
Pin
Pin Functions and Selection Method
PA3/COM4
The pin function depends on bit PCRA3 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA3
Pin function
PA2/COM3
0000
0
1
PA2 input pin
PA2 output pin
Not 0000
*
COM3 output pin
The pin function depends on bit PCRA1 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA1
Pin function
PA0/COM1
Not 0000
*
COM4 output pin
The pin function depends on bit PCRA2 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA2
Pin function
PA1/COM2
0000
0
1
PA3 input pin
PA3 output pin
0000
0
PA1 input pin
1
PA1 output pin
Not 0000
*
COM2 output pin
The pin function depends on bit PCRA0 in PCRA and bits SGS3 to SGS0.
SGS3 to SGS0
PCRA0
Pin function
0000
0
1
PA0 input pin
PA0 output pin
Not 0000
*
COM1 output pin
*: Don’t care
8.11.4
Pin States
Table 8.31 shows the port A pin states in each operating mode.
Table 8.31 Port A Pin States
Pins
Reset
Sleep
Subsleep
Standby
Watch
Subactive
Active
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Highimpedance
Retains
previous
state
Retains
previous
state
Highimpedance
Retains
previous
state
Functional
Functional
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Section 8 I/O Ports
8.12
Port B
8.12.1
Overview
Port B is an 8-bit input-only port, configured as shown in figure 8.11.
PB7/AN7
PB6/AN6
PB5/AN5
PB4/AN4
Port B
PB3/AN3
PB2/AN2
PB1/AN1
PB0/AN0
Figure 8.11 Port B Pin Configuration
8.12.2
Register Configuration and Description
Table 8.32 shows the port B register configuration.
Table 8.32 Port B Register
Name
Abbr.
R/W
Address
Port data register B
PDRB
R
H'FFDE
1. Port Data Register B (PDRB)
Bit
7
PB
Read/Write
R
7
6
5
4
PB 6
PB 5
PB
R
R
R
4
3
2
1
0
PB 3
PB 2
PB 1
PB
R
R
R
R
0
Reading PDRB always gives the pin states. However, if a port B pin is selected as an analog input
channel for the A/D converter by AMR bits CH3 to CH0, that pin reads 0 regardless of the input
voltage.
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Section 8 I/O Ports
8.13
Port C
8.13.1
Overview
Port C is a 4-bit input-only port, configured as shown in figure 8.12.
PC3/AN11
PC2/AN10
Port C
PC1/AN9
PC0/AN8
Figure 8.12 Port C Pin Configuration
8.13.2
Register Configuration and Description
Table 8.33 shows the port C register configuration.
Table 8.33 Port C Register
Name
Abbr.
R/W
Address
Port data register C
PDRC
R
H'FFDF
1. Port Data Register C (PDRC)
Bit
Read/Write
7
6
5
4
3
2
1
0
—
—
—
—
PC3
PC2
PC1
PC0
—
—
—
—
R
R
R
R
Reading PDRC always gives the pin states.
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Section 8 I/O Ports
Reading the pin for which an analog input channel is selected by the AMR CH3 to CH0 of the
A/D converter, "0" is read regardless of the input voltage.
8.14
Input/Output Data Inversion Function
8.14.1
Overview
With input pins RXD31, and RXD32, and output pins TXD31 and TXD32, the data can be handled in
inverted form.
SCINV0
SCINV2
RXD31
RXD32
P34/RXD31
P41/RXD32
SCINV1
SCINV3
P35/TXD31
P42/TXD32
TXD31
TXD32
Figure 8.13 Input/Output Data Inversion Function
8.14.2
Register Configuration and Descriptions
Table 8.34 shows the registers used by the input/output data inversion function.
Table 8.34 Register Configuration
Name
Abbr.
R/W
Address
Serial port control register
SPCR
R/W
H'FF91
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Section 8 I/O Ports
1. Serial Port Control Register (SPCR)
Bit
7
6
5
4
—
—
SPC32
SPC31
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
3
2
1
0
SCINV3 SCINV2 SCINV1 SCINV0
SPCR is an 8-bit readable/writable register that performs RXD31, RXD32, TXD31, and TXD32 pin
input/output data inversion switching. SPCR is initialized to H'C0 by a reset.
Bits 7 and 6: Reserved bits
Bits 7 and 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5: P42/TXD32 pin function switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P42 I/O pin
1
Functions as TXD32 output pin*
Note:
*
(initial value)
Set the TE bit in SCR3 after setting this bit to 1.
Bit 4: P35/TXD31 pin function switch (SPC31)
This bit selects whether pin P35/TXD31 is used as P35 or as TXD31.
Bit 4
SPC31
Description
0
Functions as P35 I/O pin
1
Functions as TXD31 output pin*
Note:
*
Set the TE bit in SCR3 after setting this bit to 1.
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(initial value)
Section 8 I/O Ports
Bit 3: TXD32 pin output data inversion switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
(initial value)
Bit 2: RXD32 pin input data inversion switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bit 1: TXD31 pin output data inversion switch
Bit 1 specifies whether or not TXD31 pin output data is to be inverted.
Bit 1
SCINV1
Description
0
TXD31 output data is not inverted
1
TXD31 output data is inverted
(initial value)
Bit 0: RXD31 pin input data inversion switch
Bit 0 specifies whether or not RXD31 pin input data is to be inverted.
Bit 0
SCINV0
Description
0
RXD31 input data is not inverted
1
RXD31 input data is inverted
(initial value)
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Section 8 I/O Ports
8.14.3
Note on Modification of Serial Port Control Register
When a serial port control register is modified, the data being input or output up to that point is
inverted immediately after the modification, and an invalid data change is input or output. When
modifying a serial port control register, do so in a state in which data changes are invalidated.
8.15
Application Note
8.15.1
The Management of the Un-Use Terminal
If an I/O pin not used by the user system is floating, pull it up or down.
• If an unused pin is an input pin, handle it in one of the following ways:
Pull it up to VCC with an on-chip pull-up MOS.
Pull it up to VCC with an external resistor of approximately 100 kΩ.
Pull it down to VSS with an external resistor of approximately 100 kΩ.
For a pin also used by the A/D converter, pull it up to AVCC.
• If an unused pin is an output pin, handle it in one of the following ways:
Set the output of the unused pin to high and pull it up to VCC with an external resistor of
approximately 100 kΩ.
Set the output of the unused pin to low and pull it down to VSS with an external resistor of
approximately 100 kΩ.
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Section 9 Timers
Section 9 Timers
9.1
Overview
This LSI provides six timers: timers A, C, F, G, and a watchdog timer, and an asynchronous event
counter. The functions of these timers are outlined in table 9.1.
Table 9.1
Timer Functions
Name
Functions
Internal Clock
Event
Waveform
Input Pin Output Pin Remarks
Timer A
• 8-bit interval timer
φ/8 to φ/8192
—
• Interval function
(8 choices)
• Time base
φW /128 (choice of
4 overflow periods)
• Clock output
φ/4 to φ/32 φW , φW /4 —
to φW /32 (9 choices)
TMOW
• 8-bit timer
φ/4 to φ/8192, φW/4
(7 choices)
TMIC
—
TMIF
TMOFL
TMOFH
TMIG
—
Timer C
• Interval function
—
• Event counting function
• Up-count/down-count
selectable
Timer F
φ/4 to φ/32, φW /4
• Event counting function (4 choices)
• 16-bit timer
Up-count/
down-count
controllable by
software or
hardware
• Also usable as two
independent 8-bit
timers
• Output compare output
function
Timer G
• 8-bit timer
• Input capture function
φ/2 to φ/64, φW /4
(4 choices)
Built-in capture
input signal
noise canceler
• Interval function
Watchdog
timer
• Reset signal generated φ/8192
φw/32
when 8-bit counter
overflows
Counter
clearing option
—
—
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Section 9 Timers
Name
Functions
Asynchro- • 16-bit counter
nous event
• Also usable as two
counter
independent 8-bit
counters
Internal Clock
—
Event
Waveform
Input Pin Output Pin Remarks
AEVL
AEVH
—
• Counts events
asynchronous to φ and
φW
9.2
Timer A
9.2.1
Overview
Timer A is an 8-bit timer with interval timing and real-time clock time-base functions. The clock
time-base function is available when a 32.768 kHz crystal oscillator is connected. A clock signal
divided from 32.768 kHz, from 38.4 kHz (if a 38.4 kHz crystal oscillator is connected), or from
the system clock, can be output at the TMOW pin.
1. Features
Features of timer A are given below.
• Choice of eight internal clock sources (φ/8192, φ/4096, φ/2048, φ/512, φ/256, φ/128, φ/32,
φ/8).
• Choice of four overflow periods (1 s, 0.5 s, 0.25 s, 31.25 ms) when timer A is used as a clock
time base (using a 32.768 kHz crystal oscillator).
• An interrupt is requested when the counter overflows.
• Any of nine clock signals can be output at the TMOW pin: 32.768 kHz divided by 32, 16, 8, or
4 (1 kHz, 2 kHz, 4 kHz, 8 kHz, 32.768 kHz) or 38.4 kHz divided by 32, 16, 8, or 4 (1.2 kHz,
2.4 kHz, 4.8 kHz, 9.6 kHz, 38.4 kHz), and the system clock divided by 32, 16, 8, or 4.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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Section 9 Timers
2. Block Diagram
Figure 9.1 shows a block diagram of timer A.
CWORS
PSW
φW /4
φW/32
φW/16
φW/8
φW/4
TMA
Internal data bus
1/4
φ W/128
φ
÷64*
φ/8192, φ/4096, φ/2048,
φ/512, φ/256, φ/128,
φ/32, φ/8
÷8*
φ/32
φ/16
φ/8
φ/4
÷256*
TCA
TMOW
÷128*
φW
PSS
IRRTA
Legend:
TMA:
TCA:
IRRTA:
PSW:
PSS:
CWOSR:
Timer mode register A
Timer counter A
Timer A overflow interrupt request flag
Prescaler W
Prescaler S
Subclock output select register
Note: * Can be selected only when the prescaler W output (φW/128) is used as the TCA input clock.
Figure 9.1 Block Diagram of Timer A
3. Pin Configuration
Table 9.2 shows the timer A pin configuration.
Table 9.2
Pin Configuration
Name
Abbr.
I/O
Function
Clock output
TMOW
Output
Output of waveform generated by timer A output circuit
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Section 9 Timers
4. Register Configuration
Table 9.3 shows the register configuration of timer A.
Table 9.3
Timer A Registers
Name
Abbr.
R/W
Initial Value
Address
Timer mode register A
TMA
R/W
H'10
H'FFB0
Timer counter A
TCA
R
H'00
H'FFB1
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Subclock output select register
CWOSR
R/W
H'FE
H'FF92
9.2.2
Register Descriptions
1. Timer Mode Register A (TMA)
Bit
7
6
5
4
3
2
1
0
TMA7
TMA6
TMA5
TMA3
TMA2
TMA1
TMA0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TMA is an 8-bit read/write register for selecting the prescaler, input clock, and output clock.
Upon reset, TMA is initialized to H'10.
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Section 9 Timers
Bits 7 to 5: Clock output select (TMA7 to TMA5)
Bits 7 to 5 choose which of eight clock signals is output at the TMOW pin. The system clock
divided by 32, 16, 8, or 4 can be output in active mode and sleep mode. A 32.768 kHz or 38.4
kHz signal divided by 32, 16, 8, or 4 can be output in active mode, sleep mode, and subactive
mode. φw is output in all modes except the reset state.
CWOSR
TMA
CWOS
Bit 7
TMA7
Bit 6
TMA6
Bit 5
TMA5
Clock Output
0
0
0
0
φ/32
1
φ/16
0
φ/8
1
φ/4
0
φW /32
1
φW /16
1
0
φW /8
1
φW /4
*
*
φW
1
1
1
*
0
(initial value)
*: Don’t care
Bit 4: Reserved bit
Bit 4 is reserved; it is always read as 1, and cannot be modified.
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Section 9 Timers
Bits 3 to 0: Internal clock select (TMA3 to TMA0)
Bits 3 to 0 select the clock input to TCA. The selection is made as follows.
Description
Bit 3
TMA3
Bit 2
TMA2
Bit 1
TMA1
Bit 0
TMA0
Prescaler and Divider Ratio
or Overflow Period
0
0
0
0
PSS, φ/8192
1
PSS, φ/4096
1
0
PSS, φ/2048
1
PSS, φ/512
0
0
PSS, φ/256
1
PSS, φ/128
0
PSS, φ/32
1
PSS, φ/8
0
PSW, 1 s
Clock time base
1
PSW, 0.5 s
(when using
0
PSW, 0.25 s
32.768 kHz)
1
PSW, 0.03125 s
0
PSW and TCA are reset
1
1
1
0
0
1
1
0
1
1
0
1
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Function
(initial value) Interval timer
Section 9 Timers
2. Timer Counter A (TCA)
Bit
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCA is an 8-bit read-only up-counter, which is incremented by internal clock input. The clock
source for input to this counter is selected by bits TMA3 to TMA0 in timer mode register A
(TMA). TCA values can be read by the CPU in active mode, but cannot be read in subactive
mode. When TCA overflows, the IRRTA bit in interrupt request register 1 (IRR1) is set to 1.
TCA is cleared by setting bits TMA3 and TMA2 of TMA to 11.
Upon reset, TCA is initialized to H'00.
3. Clock Stop Register 1 (CKSTPR1)
Bit:
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer A is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 0: Timer A module standby mode control (TACKSTP)
Bit 0 controls setting and clearing of module standby mode for timer A.
TACKSTP
Description
0
Timer A is set to module standby mode
1
Timer A module standby mode is cleared
(initial value)
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Section 9 Timers
4. Subclock Output Select Register (CWOSR)
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CWOS
Initial value:
1
1
1
1
1
1
1
0
Read/Write:
R
R
R
R
R
R
R
R/W
Bit:
CWOSR is an 8-bit read/write register that selects the clock to be output from the TMOW pin.
CWOSR is initialized to H'FE by a reset.
Bits 7 to 1: Reserved bits
Bits 7 to 1 are reserved; they are always read as 1 and cannot be modified.
Bit 0: TMOW pin clock select (CWOS)
Bit 0 selects the clock to be output from the TMOW pin.
Bit 0
CWOS
Description
0
Clock output from timer A is output (see TMA)
1
φW is output
9.2.3
(initial value)
Timer Operation
1. Interval Timer Operation
When bit TMA3 in timer mode register A (TMA) is cleared to 0, timer A functions as an 8-bit
interval timer.
Upon reset, TCA is cleared to H'00 and bit TMA3 is cleared to 0, so up-counting and interval
timing resume immediately. The clock input to timer A is selected by bits TMA2 to TMA0 in
TMA; any of eight internal clock signals output by prescaler S can be selected.
After the count value in TCA reaches H'FF, the next clock signal input causes timer A to
overflow, setting bit IRRTA to 1 in interrupt request register 1 (IRR1). If IENTA = 1 in interrupt
enable register 1 (IENR1), a CPU interrupt is requested.*
At overflow, TCA returns to H'00 and starts counting up again. In this mode timer A functions as
an interval timer that generates an overflow output at intervals of 256 input clock pulses.
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Section 9 Timers
Note: * For details on interrupts, see section 3.3, Interrupts.
2. Real-time Clock Time Base Operation
When bit TMA3 in TMA is set to 1, timer A functions as a real-time clock time base by counting
clock signals output by prescaler W. The overflow period of timer A is set by bits TMA1 and
TMA0 in TMA. A choice of four periods is available. In time base operation (TMA3 = 1), setting
bit TMA2 to 1 clears both TCA and prescaler W to their initial values of H'00.
3. Clock Output
Setting bit TMOW in port mode register 1 (PMR1) to 1 causes a clock signal to be output at pin
TMOW. Nine different clock output signals can be selected by means of bits TMA7 to TMA5 in
TMA and bit CWOS in CWOSR. The system clock divided by 32, 16, 8, or 4 can be output in
active mode and sleep mode. A 32.768 kHz or 38.4 kHz signal divided by 32, 16, 8, or 4 can be
output in active mode, sleep mode, watch mode, subactive mode, and subsleep mode. The 32.768
kHz or 38.4 kHz clock is output in all modes except the reset state.
9.2.4
Timer A Operation States
Table 9.4 summarizes the timer A operation states.
Table 9.4
Timer A Operation States
Operation Mode
Reset Active
Watch
Subactive
Subsleep
Module
Standby Standby
TCA
Reset Functions Functions Halted
Halted
Halted
Halted
Halted
Clock time base Reset Functions Functions Functions Functions Functions Halted
Halted
TMA
Interval
CWOSR
Sleep
Reset Functions Retained Retained Functions Retained Retained Retained
Note: When the real-time clock time base function is selected as the internal clock of TCA in
active mode or sleep mode, the internal clock is not synchronous with the system clock, so
it is synchronized by a synchronizing circuit. This may result in a maximum error of 1/φ (s) in
the count cycle.
9.2.5
Application Note
When bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) is cleared to 0, bit 3 (TMA3) of
the timer mode register A (TMA) cannot be rewritten.
Set bit 0 (TACKSTP) of the clock stop register 1 (CKSTPR1) to 1 before rewriting bit 3 (TMA3)
of the timer mode register A (TMA).
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Section 9 Timers
9.3
Timer C
9.3.1
Overview
Timer C is an 8-bit timer that increments each time a clock pulse is input. This timer has two
operation modes, interval and auto reload.
1. Features
Features of timer C are given below.
• Choice of seven internal clock sources (φ/8192, φ/2048, φ/512, φ/64, φ/16, φ/4, φW/4) or an
external clock (can be used to count external events).
• An interrupt is requested when the counter overflows.
• Up/down-counter switching is possible by hardware or software.
• Subactive mode and subsleep mode operation is possible when φW/4 is selected as the internal
clock, or when an external clock is selected.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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Section 9 Timers
2. Block Diagram
Figure 9.2 shows a block diagram of timer C.
UD
φ
TCC
PSS
Internal data bus
TMC
TMIC
TLC
φW/4
IRRTC
Legend:
TMC :
TCC :
:
TLC
IRRTC :
PSS :
Timer mode register C
Timer counter C
Timer load register C
Timer C overflow interrupt request flag
Prescaler S
Figure 9.2 Block Diagram of Timer C
3. Pin Configuration
Table 9.5 shows the timer C pin configuration.
Table 9.5
Pin Configuration
Name
Abbr.
I/O
Function
Timer C event input
TMIC
Input
Input pin for event input to TCC
Timer C up/down-count selection
UD
Input
Timer C up/down select
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Section 9 Timers
4. Register Configuration
Table 9.6 shows the register configuration of timer C.
Table 9.6
Timer C Registers
Name
Abbr.
R/W
Initial Value
Address
Timer mode register C
TMC
R/W
H'18
H'FFB4
Timer counter C
TCC
R
H'00
H'FFB5
Timer load register C
TLC
W
H'00
H'FFB5
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.3.2
Register Descriptions
1. Timer Mode Register C (TMC)
Bit
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
TMC is an 8-bit read/write register for selecting the auto-reload function and input clock, and
performing up/down-counter control.
Upon reset, TMC is initialized to H'18.
Bit 7: Auto-reload function select (TMC7)
Bit 7 selects whether timer C is used as an interval timer or auto-reload timer.
Bit 7
TMC7
Description
0
Interval timer function selected
1
Auto-reload function selected
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(initial value)
Section 9 Timers
Bits 6 and 5: Counter up/down control (TMC6, TMC5)
Selects whether TCC up/down control is performed by hardware using UD pin input, or whether
TCC functions as an up-counter or a down-counter.
Bit 6
TMC6
Bit 5
TMC5
Description
0
0
TCC is an up-counter
0
1
TCC is a down-counter
1
*
Hardware control by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
(initial value)
*: Don't care
Bits 4 and 3: Reserved bits
Bits 4 and 3 are reserved; they are always read as 1 and cannot be modified.
Bits 2 to 0: Clock select (TMC2 to TMC0)
Bits 2 to 0 select the clock input to TCC. For external event counting, either the rising or falling
edge can be selected.
Bit 2
TMC2
Bit 1
TMC1
Bit 0
TMC0
Description
0
0
0
Internal clock: φ/8192
0
0
1
Internal clock: φ/2048
0
1
0
Internal clock: φ/512
0
1
1
Internal clock: φ/64
1
0
0
Internal clock: φ/16
1
0
1
Internal clock: φ/4
1
1
0
Internal clock: φW /4
1
1
1
External event (TMIC): rising or falling edge*
Note:
*
(initial value)
The edge of the external event signal is selected by bit IEG1 in the IRQ edge select
register (IEGR). See 1. IRQ edge select register (IEGR) in section 3.3.2 for details.
IRQ1 must be set to 1 in port mode register 1 (PMR1) before setting 111 in bits TMC2
to TMC0.
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Section 9 Timers
2. Timer Counter C (TCC)
Bit
7
6
5
4
3
2
1
0
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TCC is an 8-bit read-only up-counter, which is incremented by internal clock or external event
input. The clock source for input to this counter is selected by bits TMC2 to TMC0 in timer mode
register C (TMC). TCC values can be read by the CPU at any time.
When TCC overflows from H'FF to H'00 or to the value set in TLC, or underflows from H'00 to
H'FF or to the value set in TLC, the IRRTC bit in IRR2 is set to 1.
TCC is allocated to the same address as TLC.
Upon reset, TCC is initialized to H'00.
3. Timer Load Register C (TLC)
Bit
7
6
5
4
3
2
1
0
TLC7
TLC6
TLC5
TLC4
TLC3
TLC2
TLC1
TLC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
TLC is an 8-bit write-only register for setting the reload value of timer counter C (TCC).
When a reload value is set in TLC, the same value is loaded into timer counter C as well, and TCC
starts counting up from that value. When TCC overflows or underflows during operation in autoreload mode, the TLC value is loaded into TCC. Accordingly, overflow/underflow periods can be
set within the range of 1 to 256 input clocks.
The same address is allocated to TLC as to TCC.
Upon reset, TLC is initialized to H'00.
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Section 9 Timers
4. Clock Stop Register 1 (CKSTPR1)
7
Bit:
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer C is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1: Timer C module standby mode control (TCCKSTP)
Bit 1 controls setting and clearing of module standby mode for timer C.
TCCKSTP
Description
0
Timer C is set to module standby mode
1
Timer C module standby mode is cleared
9.3.3
(initial value)
Timer Operation
1. Interval Timer Operation
When bit TMC7 in timer mode register C (TMC) is cleared to 0, timer C functions as an 8-bit
interval timer.
Upon reset, TCC is initialized to H'00 and TMC to H'18, so TCC continues up-counting as an
interval up-counter without halting immediately after a reset. The timer C operating clock is
selected from seven internal clock signals output by prescalers S and W, or an external clock input
at pin TMIC. The selection is made by bits TMC2 to TMC0 in TMC.
TCC up/down-count control can be performed either by software or hardware. The selection is
made by bits TMC6 and TMC5 in TMC.
After the count value in TCC reaches H'FF (H'00), the next clock input causes timer C to overflow
(underflow), setting bit IRRTC to 1 in IRR2. If IENTC = 1 in interrupt enable register 2 (IENR2),
a CPU interrupt is requested.
At overflow (underflow), TCC returns to H'00 (H'FF) and starts counting up (down) again.
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Section 9 Timers
During interval timer operation (TMC7 = 0), when a value is set in timer load register C (TLC),
the same value is set in TCC.
Note: For details on interrupts, see section 3.3, Interrupts.
2. Auto-reload Timer Operation
Setting bit TMC7 in TMC to 1 causes timer C to function as an 8-bit auto-reload timer. When a
reload value is set in TLC, the same value is loaded into TCC, becoming the value from which
TCC starts its count.
After the count value in TCC reaches H'FF (H'00), the next clock signal input causes timer C to
overflow/underflow. The TLC value is then loaded into TCC, and the count continues from that
value. The overflow/underflow period can be set within a range from 1 to 256 input clocks,
depending on the TLC value.
The clock sources, up/down control, and interrupts in auto-reload mode are the same as in interval
mode.
In auto-reload mode (TMC7 = 1), when a new value is set in TLC, the TLC value is also set in
TCC.
3. Event Counter Operation
Timer C can operate as an event counter, counting rising or falling edges of an external event
signal input at pin TMIC. External event counting is selected by setting bits TMC2 to TMC0 in
timer mode register C to all 1s (111).
When timer C is used to count external event input, bit IRQ1 in PMR1 should be set to 1 and bit
IEN1 in IENR1 cleared to 0 to disable interrupt IRQ1 requests.
4. TCC Up/Down Control by Hardware
With timer C, TCC up/down control can be performed by UD pin input. When bit TMC6 is set to
1 in TMC, TCC functions as an up-counter when UD pin input is high, and as a down-counter
when low.
When using UD pin input, set bit UD to 1 in PMR3.
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Section 9 Timers
9.3.4
Timer C Operation States
Table 9.7 summarizes the timer C operation states.
Table 9.7
Timer C Operation States
TCC
Interval
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Auto reload
Reset
Functions Functions Halted
Functions/ Functions/ Halted
Halted*
Halted*
Halted
Reset
Functions Retained
Functions Retained
Retained
*
Retained
Standby
Module
Standby
Active
Note:
Watch
Subsleep
Reset
TMC
Sleep
Subactive
Operation Mode
Retained
When φw/4 is selected as the TCC internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode or subsleep mode, either
select φw/4 as the internal clock or select an external clock. The counter will not
operate on any other internal clock. If φw/4 is selected as the internal clock for the
counter when φw/8 has been selected as subclock φSUB, the lower 2 bits of the counter
operate on the same cycle, and the operation of the least significant bit is unrelated to
the operation of the counter.
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Section 9 Timers
9.3.5
Usage Note
Note the following regarding the operation of timer C.
(1) Counting errors caused by external event input
Timer counter errors may occur under the following conditions.
Conditions
•
An external event (TMIC) is used in subsleep mode.
Symptom
•
The counter increments or decrements twice for a single external event input.
Approximate rate of occurrence
The approximate rate of occurrence in cases where the external event input is not
synchronized with internal operation is defined by the following equation.
Approximate rate of occurrence P = 30 ns / tsubcyc
For example, if tsubcyc = 61.06 µs (subclock φw/2), P = 0.0005 (0.05%). If 2,000 external
event inputs occur, there is a likelihood that one of them will cause the counter to
increment or decrement twice (+2 or –2).
The symptom described is caused by the internal circuit configuration of the device and
therefore difficult to avoid. Therefore, it is not advisable to use the clock counter for
applications requiring a high degree of accuracy.
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Section 9 Timers
9.4
Timer F
9.4.1
Overview
Timer F is a 16-bit timer with a built-in output compare function. As well as counting external
events, timer F also provides for counter resetting, interrupt request generation, toggle output, etc.,
using compare match signals. Timer F can also be used as two independent 8-bit timers (timer FH
and timer FL).
1. Features
Features of timer F are given below.
• Choice of four internal clock sources (φ/32, φ/16, φ/4, φw/4) or an external clock (can be used
as an external event counter)
• TMOFH pin (TMOFL pin) toggle output provided using a single compare match signal (toggle
output initial value can be set)
• Counter resetting by a compare match signal
• Two interrupt sources: one compare match, one overflow
• Can operate as two independent 8-bit timers (timer FH and timer FL) (in 8-bit mode).
Timer FH 8-Bit Timer*
Timer FL 8-Bit Timer/Event Counter
Internal clock
Choice of 4 (φ/32, φ/16, φ/4, φw/4)
Event input
—
TMIF pin
Toggle output
One compare match signal,
output to TMOFH pin
(initial value settable)
One compare match signal,
output to TMOFL pin
(initial value settable)
Counter reset
Counter can be reset by compare match signal
Interrupt sources
One compare match
One overflow
Note:
*
When timer F operates as a 16-bit timer, it operates on the timer FL overflow signal.
• Operation in watch mode, subactive mode, and subsleep mode
When φw/4 is selected as the internal clock, timer F can operate in watch mode, subactive
mode, and subsleep mode.
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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Section 9 Timers
2. Block Diagram
Figure 9.3 shows a block diagram of timer F.
φ
PSS
IRRTFL
TCRF
φw/4
TMIF
TCFL
Toggle
circuit
Comparator
Internal data bus
TMOFL
OCRFL
TCFH
TMOFH
Toggle
circuit
Comparator
Match
OCRFH
TCSRF
IRRTFH
Legend:
TCRF:
TCSRF:
TCFH:
TCFL:
OCRFH:
OCRFL:
IRRTFH:
IRRTFL:
PSS:
Timer control register F
Timer control/status register F
8-bit timer counter FH
8-bit timer counter FL
Output compare register FH
Output compare register FL
Timer FH interrupt request flag
Timer FL interrupt request flag
Prescaler S
Figure 9.3 Block Diagram of Timer F
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Section 9 Timers
3. Pin Configuration
Table 9.8 shows the timer F pin configuration.
Table 9.8
Pin Configuration
Name
Abbr.
I/O
Function
Timer F event input
TMIF
Input
Event input pin for input to TCFL
Timer FH output
TMOFH
Output
Timer FH toggle output pin
Timer FL output
TMOFL
Output
Timer FL toggle output pin
4. Register Configuration
Table 9.9 shows the register configuration of timer F.
Table 9.9
Timer F Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control register F
TCRF
W
H'00
H'FFB6
Timer control/status register F
TCSRF
R/W
H'00
H'FFB7
8-bit timer counter FH
TCFH
R/W
H'00
H'FFB8
8-bit timer counter FL
TCFL
R/W
H'00
H'FFB9
Output compare register FH
OCRFH
R/W
H'FF
H'FFBA
Output compare register FL
OCRFL
R/W
H'FF
H'FFBB
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
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Section 9 Timers
9.4.2
Register Descriptions
1. 16-bit Timer Counter (TCF)
8-bit Timer Counter (TCFH)
8-bit Timer Counter (TCFL)
TCF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCFH
TCFL
TCF is a 16-bit read/write up-counter configured by cascaded connection of 8-bit timer counters
TCFH and TCFL. In addition to the use of TCF as a 16-bit counter with TCFH as the upper 8 bits
and TCFL as the lower 8 bits, TCFH and TCFL can also be used as independent 8-bit counters.
TCFH and TCFL can be read and written by the CPU, but when they are used in 16-bit mode, data
transfer to and from the CPU is performed via a temporary register (TEMP). For details of TEMP,
see section 9.4.3, CPU Interface.
TCFH and TCFL are each initialized to H'00 upon reset.
a. 16-bit mode (TCF)
When CKSH2 is cleared to 0 in TCRF, TCF operates as a 16-bit counter. The TCF input
clock is selected by bits CKSL2 to CKSL0 in TCRF.
TCF can be cleared in the event of a compare match by means of CCLRH in TCSRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF is 1 at this time, IRRTFH is set to 1 in IRR2, and if IENTFH in IENR2 is 1, an
interrupt request is sent to the CPU.
b. 8-bit mode (TCFL/TCFH)
When CKSH2 is set to 1 in TCRF, TCFH and TCFL operate as two independent 8-bit
counters. The TCFH (TCFL) input clock is selected by bits CKSH2 to CKSH0 (CKSL2 to
CKSL0) in TCRF.
TCFH (TCFL) can be cleared in the event of a compare match by means of CCLRH
(CCLRL) in TCSRF.
When TCFH (TCFL) overflows from H'FF to H'00, OVFH (OVFL) is set to 1 in TCSRF.
If OVIEH (OVIEL) in TCSRF is 1 at this time, IRRTFH (IRRTFL) is set to 1 in IRR2, and
if IENTFH (IENTFL) in IENR2 is 1, an interrupt request is sent to the CPU.
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Section 9 Timers
2. 16-bit Output Compare Register (OCRF)
8-bit Output Compare Register (OCRFH)
8-bit Output Compare Register (OCRFL)
OCRF
Bit:
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value:
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write:
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRFH
OCRFL
OCRF is a 16-bit read/write register composed of the two registers OCRFH and OCRFL. In
addition to the use of OCRF as a 16-bit register with OCRFH as the upper 8 bits and OCRFL as
the lower 8 bits, OCRFH and OCRFL can also be used as independent 8-bit registers.
OCRFH and OCRFL can be read and written by the CPU, but when they are used in 16-bit mode,
data transfer to and from the CPU is performed via a temporary register (TEMP). For details of
TEMP, see section 9.4.3, CPU Interface.
OCRFH and OCRFL are each initialized to H'FF upon reset.
a. 16-bit mode (OCRF)
When CKSH2 is cleared to 0 in TCRF, OCRF operates as a 16-bit register. OCRF contents
are constantly compared with TCF, and when both values match, CMFH is set to 1 in
TCSRF. At the same time, IRRTFH is set to 1 in IRR2. If IENTFH in IENR2 is 1 at this
time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin by means of compare matches, and
the output level can be set (high or low) by means of TOLH in TCRF.
b. 8-bit mode (OCRFH/OCRFL)
When CKSH2 is set to 1 in TCRF, OCRFH and OCRFL operate as two independent 8-bit
registers. OCRFH contents are compared with TCFH, and OCRFL contents are with
TCFL. When the OCRFH (OCRFL) and TCFH (TCFL) values match, CMFH (CMFL) is
set to 1 in TCSRF. At the same time, IRRTFH (IRRTFL) is set to 1 in IRR2. If IENTFH
(IENTFL) in IENR2 is 1 at this time, an interrupt request is sent to the CPU.
Toggle output can be provided from the TMOFH pin (TMOFL pin) by means of compare
matches, and the output level can be set (high or low) by means of TOLH (TOLL) in
TCRF.
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Section 9 Timers
3. Timer Control Register F (TCRF)
Bit:
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
W
W
W
W
W
W
W
W
TCRF is an 8-bit write-only register that switches between 16-bit mode and 8-bit mode, selects the
input clock from among four internal clock sources or external event input, and sets the output
level of the TMOFH and TMOFL pins.
TCRF is initialized to H'00 upon reset.
Bit 7: Toggle output level H (TOLH)
Bit 7 sets the TMOFH pin output level. The output level is effective immediately after this bit is
written.
Bit 7
TOLH
Description
0
Low level
1
High level
(initial value)
Bits 6 to 4: Clock select H (CKSH2 to CKSH0)
Bits 6 to 4 select the clock input to TCFH from among four internal clock sources or TCFL
overflow.
Bit 6
CKSH2
Bit 5
CKSH1
Bit 4
CKSH0
Description
0
0
0
16-bit mode, counting on TCFL overflow signal
0
0
1
0
1
0
0
1
1
Not available
1
0
0
Internal clock: counting on φ/32
1
0
1
Internal clock: counting on φ/16
1
1
0
Internal clock: counting on φ/4
1
1
1
Internal clock: counting on φw/4
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(initial value)
Section 9 Timers
Bit 3: Toggle output level L (TOLL)
Bit 3 sets the TMOFL pin output level. The output level is effective immediately after this bit is
written.
Bit 3
TOLL
Description
0
Low level
1
High level
(initial value)
Bits 2 to 0: Clock select L (CKSL2 to CKSL0)
Bits 2 to 0 select the clock input to TCFL from among four internal clock sources or external event
input.
Bit 2
CKSL2
Bit 1
CKSL1
Bit 0
CKSL0
Description
0
0
0
Counting on external event (TMIF) rising/falling
0
0
1
edge*
0
1
0
0
1
1
Not available
1
0
0
Internal clock: counting on φ/32
1
0
1
Internal clock: counting on φ/16
1
1
0
Internal clock: counting on φ/4
1
1
1
Internal clock: counting on φw/4
Note:
*
(initial value)
External event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
For details, see 1. IRQ edge select register (IEGR) in section 3.3.2.
Note that the timer F counter may increment if the setting of IRQ3 in port mode register
1 (PMR1) is changed from 0 to 1 while the TMIF pin is low in order to change the TMIF
pin function.
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Section 9 Timers
4. Timer Control/Status Register F (TCSRF)
Bit:
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R/(W)*
R/(W)*
R/W
R/W
R/(W)*
R/(W)*
R/W
R/W
Note:
*
Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
TCSRF is an 8-bit read/write register that performs counter clear selection, overflow flag setting,
and compare match flag setting, and controls enabling of overflow interrupt requests.
TCSRF is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCFH has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 7
OVFH
Description
0
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting condition:
Set when TCFH overflows from H'FF to H'00
(initial value)
Bit 6: Compare match flag H (CMFH)
Bit 6 is a status flag indicating that TCFH has matched OCRFH. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 6
CMFH
Description
0
Clearing condition:
After reading CMFH = 1, cleared by writing 0 to CMFH
1
Setting condition:
Set when the TCFH value matches the OCRFH value
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(initial value)
Section 9 Timers
Bit 5: Timer overflow interrupt enable H (OVIEH)
Bit 5 selects enabling or disabling of interrupt generation when TCFH overflows.
Bit 5
OVIEH
Description
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
(initial value)
Bit 4: Counter clear H (CCLRH)
In 16-bit mode, bit 4 selects whether TCF is cleared when TCF and OCRF match.
In 8-bit mode, bit 4 selects whether TCFH is cleared when TCFH and OCRFH match.
Bit 4
CCLRH
0
1
Description
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
(initial value)
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Bit 3: Timer overflow flag L (OVFL)
Bit 3 is a status flag indicating that TCFL has overflowed from H'FF to H'00. This flag is set by
hardware and cleared by software. It cannot be set by software.
Bit 3
OVFL
Description
0
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting condition:
Set when TCFL overflows from H'FF to H'00
(initial value)
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Section 9 Timers
Bit 2: Compare match flag L (CMFL)
Bit 2 is a status flag indicating that TCFL has matched OCRFL. This flag is set by hardware and
cleared by software. It cannot be set by software.
Bit 2
CMFL
Description
0
Clearing condition:
After reading CMFL = 1, cleared by writing 0 to CMFL
1
Setting condition:
Set when the TCFL value matches the OCRFL value
(initial value)
Bit 1: Timer overflow interrupt enable L (OVIEL)
Bit 1 selects enabling or disabling of interrupt generation when TCFL overflows.
Bit 1
OVIEL
Description
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
(initial value)
Bit 0: Counter clear L (CCLRL)
Bit 0 selects whether TCFL is cleared when TCFL and OCRFL match.
Bit 0
CCLRL
Description
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
(initial value)
5. Clock Stop Register 1 (CKSTPR1)
Bit:
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer F is described here. For details of the other bits, see the
sections on the relevant modules.
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Section 9 Timers
Bit 2: Timer F module standby mode control (TFCKSTP)
Bit 2 controls setting and clearing of module standby mode for timer F.
TFCKSTP
Description
0
Timer F is set to module standby mode
1
Timer F module standby mode is cleared
9.4.3
(initial value)
CPU Interface
TCF and OCRF are 16-bit read/write registers, but the CPU is connected to the on-chip peripheral
modules by an 8-bit data bus. When the CPU accesses these registers, it therefore uses an 8-bit
temporary register (TEMP).
In 16-bit mode, TCF read/write access and OCRF write access must be performed 16 bits at a time
(using two consecutive byte-size MOV instructions), and the upper byte must be accessed before
the lower byte. Data will not be transferred correctly if only the upper byte or only the lower byte
is accessed.
In 8-bit mode, there are no restrictions on the order of access.
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Section 9 Timers
1. Write Access
Write access to the upper byte results in transfer of the upper-byte write data to TEMP. Next,
write access to the lower byte results in transfer of the data in TEMP to the upper register byte,
and direct transfer of the lower-byte write data to the lower register byte.
Figure 9.4 shows an example in which H'AA55 is written to TCF.
Write to upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(
)
TCFL
(
)
Write to lower byte
CPU
(H'55)
Module data bus
Bus
interface
TEMP
(H'AA)
TCFH
(H'AA)
TCFL
(H'55)
Figure 9.4 Write Access to TCR (CPU → TCF)
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Section 9 Timers
2. Read Access
In access to TCF, when the upper byte is read the upper-byte data is transferred directly to the
CPU and the lower-byte data is transferred to TEMP. Next, when the lower byte is read, the
lower-byte data in TEMP is transferred to the CPU.
In access to OCRF, when the upper byte is read the upper-byte data is transferred directly to the
CPU. When the lower byte is read, the lower-byte data is transferred directly to the CPU.
Figure 9.5 shows an example in which TCF is read when it contains H'AAFF.
Read upper byte
CPU
(H'AA)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(H'AA)
TCFL
(H'FF)
Read lower byte
CPU
(H'FF)
Module data bus
Bus
interface
TEMP
(H'FF)
TCFH
(AB)*
TCFL
(00)*
Note: * H'AB00 if counter has been updated once.
Figure 9.5 Read Access to TCF (TCF → CPU)
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Section 9 Timers
9.4.4
Operation
Timer F is a 16-bit counter that increments on each input clock pulse. The timer F value is
constantly compared with the value set in output compare register F, and the counter can be
cleared, an interrupt requested, or port output toggled, when the two values match. Timer F can
also function as two independent 8-bit timers.
1. Timer F Operation
Timer F has two operating modes, 16-bit timer mode and 8-bit timer mode. The operation in each
of these modes is described below.
a. Operation in 16-bit timer mode
When CKSH2 is cleared to 0 in timer control register F (TCRF), timer F operates as a 16bit timer.
Following a reset, timer counter F (TCF) is initialized to H'0000, output compare register F
(OCRF) to H'FFFF, and timer control register F (TCRF) and timer control/status register F
(TCSRF) to H'00. The counter starts incrementing on external event (TMIF) input. The
external event edge selection is set by IEG3 in the IRQ edge select register (IEGR).
The timer F operating clock can be selected from four internal clocks or an external clock
by means of bits CKSL2 to CKSL0 in TCRF.
OCRF contents are constantly compared with TCF, and when both values match, CMFH is
set to 1 in TCSRF. If IENTFH in IENR2 is 1 at this time, an interrupt request is sent to the
CPU, and at the same time, TMOFH pin output is toggled. If CCLRH in TCSRF is 1, TCF
is cleared. TMOFH pin output can also be set by TOLH in TCRF.
When TCF overflows from H'FFFF to H'0000, OVFH is set to 1 in TCSRF. If OVIEH in
TCSRF and IENTFH in IENR2 are both 1, an interrupt request is sent to the CPU.
b. Operation in 8-bit timer mode
When CKSH2 is set to 1 in TCRF, TCF operates as two independent 8-bit timers, TCFH
and TCFL. The TCFH/TCFL input clock is selected by CKSH2 to CKSH0/CKSL2 to
CKSL0 in TCRF.
When the OCRFH/OCRFL and TCFH/TCFL values match, CMFH/CMFL is set to 1 in
TCSRF. If IENTFH/IENTFL in IENR2 is 1, an interrupt request is sent to the CPU, and at
the same time, TMOFH pin/TMOFL pin output is toggled. If CCLRH/CCLRL in TCSRF
is 1, TCFH/TCFL is cleared. TMOFH pin/TMOFL pin output can also be set by
TOLH/TOLL in TCRF.
When TCFH/TCFL overflows from H'FF to H'00, OVFH/OVFL is set to 1 in TCSRF. If
OVIEH/OVIEL in TCSRF and IENTFH/IENTFL in IENR2 are both 1, an interrupt request
is sent to the CPU.
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Section 9 Timers
2. TCF Increment Timing
TCF is incremented by clock input (internal clock or external event input).
a. Internal clock operation
Bits CKSH2 to CKSH0 or CKSL2 to CKSL0 in TCRF select one of four internal clock
sources (φ/32, φ/16, φ/4, or φw/4) created by dividing the system clock (φ or φw).
b. External event operation
External event input is selected by clearing CKSL2 to 0 in TCRF. TCF can increment on
either the rising or falling edge of external event input. External event edge selection is set
by IEG3 in the interrupt controller's IEGR register. An external event pulse width of at
least 2 system clocks (φ) is necessary. Shorter pulses will not be counted correctly.
3. TMOFH/TMOFL Output Timing
In TMOFH/TMOFL output, the value set in TOLH/TOLL in TCRF is output. The output is
toggled by the occurrence of a compare match. Figure 9.6 shows the output timing.
φ
TMIF
(when IEG3 = 1)
Count input
clock
TCF
OCRF
N+1
N
N
N
N+1
N
Compare match
signal
TMOFH TMOFL
Figure 9.6 TMOFH/TMOFL Output Timing
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Section 9 Timers
4. TCF Clear Timing
TCF can be cleared by a compare match with OCRF.
5. Timer Overflow Flag (OVF) Set Timing
OVF is set to 1 when TCF overflows from H'FFFF to H'0000.
6. Compare Match Flag set Timing
The compare match flag (CMFH or CMFL) is set to 1 when the TCF and OCRF values match.
The compare match signal is generated in the last state during which the values match (when TCF
is updated from the matching value to a new value). When TCF matches OCRF, the compare
match signal is not generated until the next counter clock.
7. Timer F Operation Modes
Timer F operation modes are shown in table 9.10.
Table 9.10 Timer F Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
TCF
Reset
Functions
Functions
Functions/ Functions/ Functions/ Halted
Halted*
Halted*
Halted*
Halted
OCRF
Reset
Functions
Held
Held
Functions
Held
Held
Held
TCRF
Reset
Functions
Held
Held
Functions
Held
Held
Held
TCSRF
Reset
Functions
Held
Held
Functions
Held
Held
Held
Note:
*
Subactive Subsleep
Standby
Module
Standby
When φw/4 is selected as the TCF internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When the counter is operated in subactive mode, watch mode, or subsleep
mode, φw/4 must be selected as the internal clock. The counter will not operate if any
other internal clock is selected.
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Section 9 Timers
9.4.5
Application Notes
The following types of contention and operation can occur when timer F is used.
1. 16-bit Timer Mode
In toggle output, TMOFH pin output is toggled when all 16 bits match and a compare match signal
is generated. If a TCRF write by a MOV instruction and generation of the compare match signal
occur simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
TMOFL pin output is unstable in 16-bit mode, and should not be used; the TMOFL pin should be
used as a port pin.
If an OCRFL write and compare match signal generation occur simultaneously, the compare
match signal is invalid. However, if the written data and the counter value match, a compare
match signal will be generated at that point. As the compare match signal is output in
synchronization with the TCFL clock, a compare match will not result in compare match signal
generation if the clock is stopped.
Compare match flag CMFH is set when all 16 bits match and a compare match signal is generated.
Compare match flag CMFL is set if the setting conditions for the lower 8 bits are satisfied.
When TCF overflows, OVFH is set. OVFL is set if the setting conditions are satisfied when the
lower 8 bits overflow. If a TCFL write and overflow signal output occur simultaneously, the
overflow signal is not output.
2. 8-bit Timer Mode
a. TCFH, OCRFH
In toggle output, TMOFH pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur
simultaneously, TOLH data is output to the TMOFH pin as a result of the TCRF write.
If an OCRFH write and compare match signal generation occur simultaneously, the
compare match signal is invalid. However, if the written data and the counter value match,
a compare match signal will be generated at that point. The compare match signal is output
in synchronization with the TCFH clock.
If a TCFH write and overflow signal output occur simultaneously, the overflow signal is
not output.
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Section 9 Timers
b. TCFL, OCRFL
In toggle output, TMOFL pin output is toggled when a compare match occurs. If a TCRF
write by a MOV instruction and generation of the compare match signal occur
simultaneously, TOLL data is output to the TMOFL pin as a result of the TCRF write.
If an OCRFL write and compare match signal generation occur simultaneously, the
compare match signal is invalid. However, if the written data and the counter value match,
a compare match signal will be generated at that point. As the compare match signal is
output in synchronization with the TCFL clock, a compare match will not result in compare
match signal generation if the clock is stopped.
If a TCFL write and overflow signal output occur simultaneously, the overflow signal is
not output.
3. Clear Timer FH, Timer FL Interrupt Request Flags (IRRTFH, IRRTFL), Timer
Overflow Flags H, L (OVFH, OVFL) and Compare Match Flags H, L (CMFH, CMFL)
When φw/4 is selected as the internal clock, “Interrupt factor generation signal” will be operated
with φw and the signal will be outputted with φw width. And, “Overflow signal” and “Compare
match signal” are controlled with 2 cycles of φw signals. Those signals are outputted with 2 cycles
width of φw (figure 9.7)
In active (high-speed, medium-speed) mode, even if you cleared interrupt request flag during the
term of validity of “Interrupt factor generation signal”, same interrupt request flag is set. (figure
9.7 (1)) And, you cannot be cleared timer overflow flag and compare match flag during the term
of validity of “Overflow signal” and “Compare match signal”.
For interrupt request flag is set right after interrupt request is cleared, interrupt process to one time
timer FH, timer FL interrupt might be repeated. (figure 9.7 (2)) Therefore, to definitely clear
interrupt request flag in active (high-speed, medium-speed) mode, clear should be processed after
the time that calculated with below (1) formula. And, to definitely clear timer overflow flag and
compare match flag, clear should be processed after read timer control status register F (TCSRF)
after the time that calculated with below (1) formula. For ST of (1) formula, please substitute the
longest number of execution states in used instruction. (10 states of RTE instruction when
MULXU, DIVXU instruction is not used, 14 states when MULXU, DIVXU instruction is used) In
subactive mode, there are not limitation for interrupt request flag, timer overflow flag, and
compare match flag clear.
The term of validity of “Interrupt factor generation signal”
= 1 cycle of φw + waiting time for completion of executing instruction
+ interrupt time synchronized with φ = 1/φw + ST × (1/φ) + (2/φ) (second).....(1)
ST: Executing number of execution states
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Section 9 Timers
Method 1 is recommended to operate for time efficiency.
Method 1
1. Prohibit interrupt in interrupt handling routine (set IENFH, IENFL to 0).
2. After program process returned normal handling, clear interrupt request flags (IRRTFH,
IRRTFL) after more than that calculated with (1) formula.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
4. Operate interrupt permission (set IENFH, IENFL to 1).
Method 2
1. Set interrupt handling routine time to more than time that calculated with (1) formula.
2. Clear interrupt request flags (IRRTFH, IRRTFL) at the end of interrupt handling routine.
3. After read timer control status register F (TCSRF), clear timer overflow flags (OVFH,
OVFL) and compare match flags (CMFH, CMFL).
All above attentions are also applied in 16-bit mode and 8-bit mode.
Interrupt request
flag clear
Interrupt request
flag clear
(2)
Program process
Interrupt
Interrupt
Normal
φw
Interrupt factor
generation signal
(Internal signal,
nega-active)
Overflow signal,
Compare match signal
(Internal signal,
nega-active)
Interrupt request flag
(IRRTFH, IRRTFL)
(1)
Figure 9.7 Clear Interrupt Request Flag when Interrupt Factor Generation Signal is Valid
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Section 9 Timers
4. Timer Counter (TCF) Read/Write
When φw/4 is selected as the internal clock in active (high-speed, medium-speed) mode, write on
TCF is impossible. And, when read TCF, as the system clock and internal clock are mutually
asynchronous, TCF synchronizes with synchronization circuit. This results in a maximum TCF
read value error of ±1.
When read/write TCF in active (high-speed, medium-speed) mode is needed, please select internal
clock except for φw/4 before read/write.
In subactive mode, even φw/4 is selected as the internal clock, normal read/write TCF is possible.
9.5
Timer G
9.5.1
Overview
Timer G is an 8-bit timer with dedicated input capture functions for the rising/falling edges of
pulses input from the input capture input pin (input capture input signal). High-frequency
component noise in the input capture input signal can be eliminated by a noise canceler, enabling
accurate measurement of the input capture input signal duty cycle. If input capture input is not set,
timer G functions as an 8-bit interval timer.
1. Features
Features of timer G are given below.
• Choice of four internal clock sources (φ/64, φ/32, φ/2, φw/4)
• Dedicated input capture functions for rising and falling edges
• Level detection at counter overflow
It is possible to detect whether overflow occurred when the input capture input signal was high
or when it was low.
• Selection of whether or not the counter value is to be cleared at the input capture input signal
rising edge, falling edge, or both edges
• Two interrupt sources: one input capture, one overflow. The input capture input signal rising
or falling edge can be selected as the interrupt source.
• A built-in noise canceler eliminates high-frequency component noise in the input capture input
signal.
• Watch mode, subactive mode and subsleep mode operation is possible when φw/4 is selected
as the internal clock.
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Section 9 Timers
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
2. Block Diagram
Figure 9.8 shows a block diagram of timer G.
φ
PSS
Level
detector
φw/4
ICRGF
Noise
canceler
TMIG
Edge
detector
NCS
Internal data bus
TMG
TCG
ICRGR
IRRTG
Legend:
TMG
TCG
ICRGF
ICRGR
IRRTG
NCS
PSS
:
:
:
:
:
:
:
Timer mode register G
Timer counter G
Input capture register GF
Input capture register GR
Timer G interrupt request flag
Noise canceler select
Prescaler S
Figure 9.8 Block Diagram of Timer G
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Section 9 Timers
3. Pin Configuration
Table 9.11 shows the timer G pin configuration.
Table 9.11 Pin Configuration
Name
Abbr.
I/O
Function
Input capture input
TMIG
Input
Input capture input pin
4. Register Configuration
Table 9.12 shows the register configuration of timer G.
Table 9.12 Timer G Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control register G
TMG
R/W
H'00
H'FFBC
Timer counter G
TCG
—
H'00
—
Input capture register GF
ICRGF
R
H'00
H'FFBD
Input capture register GR
ICRGR
R
H'00
H'FFBE
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
9.5.2
Register Descriptions
1. Timer Counter (TCG)
Bit:
7
6
5
4
3
2
1
0
TCG7
TCG6
TCG5
TCG4
TCG3
TCG2
TCG1
TCG0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
—
—
—
—
—
—
—
—
TCG is an 8-bit up-counter which is incremented by clock input. The input clock is selected by
bits CKS1 and CKS0 in TMG.
TMIG in PMR1 is set to 1 to operate TCG as an input capture timer, or cleared to 0 to operate
TCG as an interval timer*. In input capture timer operation, the TCG value can be cleared by the
rising edge, falling edge, or both edges of the input capture input signal, according to the setting
made in TMG.
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Section 9 Timers
When TCG overflows from H'FF to H'00, if OVIE in TMG is 1, IRRTG is set to 1 in IRR2, and if
IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
TCG cannot be read or written by the CPU. It is initialized to H'00 upon reset.
Note: * An input capture signal may be generated when TMIG is modified.
2. Input Capture Register GF (ICRGF)
7
6
5
4
3
2
1
0
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGF0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
Bit:
ICRGF is an 8-bit read-only register. When a falling edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGF. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
ICRGF is initialized to H'00 upon reset.
3. Input Capture Register GR (ICRGR)
Bit:
7
6
5
4
3
2
1
0
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGR0
Initial value:
0
0
0
0
0
0
0
0
Read/Write:
R
R
R
R
R
R
R
R
ICRGR is an 8-bit read-only register. When a rising edge of the input capture input signal is
detected, the current TCG value is transferred to ICRGR. If IIEGS in TMG is 1 at this time,
IRRTG is set to 1 in IRR2, and if IENTG in IENR2 is 1, an interrupt request is sent to the CPU.
For details of the interrupt, see section 3.3, Interrupts.
To ensure dependable input capture operation, the pulse width of the input capture input signal
must be at least 2φ or 2φSUB (when the noise canceler is not used).
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Section 9 Timers
ICRGR is initialized to H'00 upon reset.
4. Timer Mode Register G (TMG)
Bit:
Initial value:
Read/Write:
Note:
*
7
6
5
4
3
2
1
0
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
0
R/(W)*
0
R/(W)*
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
Bits 7 and 6 can only be written with 0, for flag clearing.
TMG is an 8-bit read/write register that performs TCG clock selection from four internal clock
sources, counter clear selection, and edge selection for the input capture input signal interrupt
request, controls enabling of overflow interrupt requests, and also contains the overflow flags.
TMG is initialized to H'00 upon reset.
Bit 7: Timer overflow flag H (OVFH)
Bit 7 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is high. This flag is set by hardware and cleared by software. It cannot be set by
software.
Bit 7
OVFH
Description
0
Clearing condition:
After reading OVFH = 1, cleared by writing 0 to OVFH
1
Setting condition:
Set when TCG overflows from H'FF to H'00
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(initial value)
Section 9 Timers
Bit 6: Timer overflow flag L (OVFL)
Bit 6 is a status flag indicating that TCG has overflowed from H'FF to H'00 when the input capture
input signal is low, or in interval operation. This flag is set by hardware and cleared by software.
It cannot be set by software.
Bit 6
OVFL
Description
0
Clearing condition:
After reading OVFL = 1, cleared by writing 0 to OVFL
1
Setting condition:
Set when TCG overflows from H'FF to H'00
(initial value)
Bit 5: Timer overflow interrupt enable (OVIE)
Bit 5 selects enabling or disabling of interrupt generation when TCG overflows.
Bit 5
OVIE
Description
0
TCG overflow interrupt request is disabled
1
TCG overflow interrupt request is enabled
(initial value)
Bit 4: Input capture interrupt edge select (IIEGS)
Bit 4 selects the input capture input signal edge that generates an interrupt request.
Bit 4
IIEGS
Description
0
Interrupt generated on rising edge of input capture input signal
1
Interrupt generated on falling edge of input capture input signal
(initial value)
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Section 9 Timers
Bits 3 and 2: Counter clear 1 and 0 (CCLR1, CCLR0)
Bits 3 and 2 specify whether or not TCG is cleared by the rising edge, falling edge, or both edges
of the input capture input signal.
Bit 3
CCLR1
Bit 2
CCLR0
Description
0
0
TCG clearing is disabled
0
1
TCG cleared by falling edge of input capture input signal
1
0
TCG cleared by rising edge of input capture input signal
1
1
TCG cleared by both edges of input capture input signal
(initial value)
Bits 1 and 0: Clock select (CKS1, CKS0)
Bits 1 and 0 select the clock input to TCG from among four internal clock sources.
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
Internal clock: counting on φ/64
0
1
Internal clock: counting on φ/32
1
0
Internal clock: counting on φ/2
1
1
Internal clock: counting on φw/4
(initial value)
5. Clock Stop Register 1 (CKSTPR1)
Bit:
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value:
1
1
1
1
1
1
1
1
Read/Write:
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to timer G is described here. For details of the other bits, see the
sections on the relevant modules.
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Section 9 Timers
Bit 3: Timer G module standby mode control (TGCKSTP)
Bit 3 controls setting and clearing of module standby mode for timer G.
TGCKSTP
Description
0
Timer G is set to module standby mode
1
Timer G module standby mode is cleared
9.5.3
(initial value)
Noise Canceler
The noise canceler consists of a digital low-pass filter that eliminates high-frequency component
noise from the pulses input from the input capture input pin. The noise canceler is set by NCS* in
PMR3.
Figure 9.9 shows a block diagram of the noise canceler.
Sampling
clock
C
Input capture
input signal
C
D
Q
D
Latch
Q
Latch
C
D
C
Q
Latch
C
D
Q
Latch
D
Q
Latch
Match
detector
Noise
canceler
output
t
Sampling clock
∆t: Set by CKS1 and CKS0
Figure 9.9 Noise Canceler Block Diagram
The noise canceler consists of five latch circuits connected in series and a match detector circuit.
When the noise cancellation function is not used (NCS = 0), the system clock is selected as the
sampling clock. When the noise cancellation function is used (NCS = 1), the sampling clock is the
internal clock selected by CKS1 and CKS0 in TMG, the input capture input is sampled on the
rising edge of this clock, and the data is judged to be correct when all the latch outputs match. If
all the outputs do not match, the previous value is retained. After a reset, the noise canceler output
is initialized when the falling edge of the input capture input signal has been sampled five times.
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Section 9 Timers
Therefore, after making a setting for use of the noise cancellation function, a pulse with at least
five times the width of the sampling clock is a dependable input capture signal. Even if noise
cancellation is not used, an input capture input signal pulse width of at least 2φ or 2φSUB is
necessary to ensure that input capture operations are performed properly
Note: * An input capture signal may be generated when the NCS bit is modified.
Figure 9.10 shows an example of noise canceler timing.
In this example, high-level input of less than five times the width of the sampling clock at the
input capture input pin is eliminated as noise.
Input capture
input signal
Sampling clock
Noise canceler
output
Eliminated as noise
Figure 9.10 Noise Canceler Timing (Example)
9.5.4
Operation
Timer G is an 8-bit timer with built-in input capture and interval functions.
1. Timer G Functions
Timer G is an 8-bit up-counter with two functions, an input capture timer function and an interval
timer function.
The operation of these two functions is described below.
a. Input capture timer operation
When the TMIG bit is set to 1 in port mode register 1 (PMR1), timer G functions as an
input capture timer*.
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Section 9 Timers
In a reset, timer mode register G (TMG), timer counter G (TCG), input capture register GF
(ICRGF), and input capture register GR (ICRGR) are all initialized to H'00.
Following a reset, TCG starts incrementing on the φ/64 internal clock.
The input clock can be selected from four internal clock sources by bits CKS1 and CKS0 in
TMG.
When a rising edge/falling edge is detected in the input capture signal input from the TMIG
pin, the TCG value at that time is transferred to ICRGR/ICRGF. When the edge selected
by IIEGS in TMG is input, IRRTG is set to 1 in IRR2, and if the IENTG bit in IENR2 is 1
at this time, an interrupt request is sent to the CPU. For details of the interrupt, see section
3.3, Interrupts.
TCG can be cleared by a rising edge, falling edge, or both edges of the input capture signal,
according to the setting of bits CCLR1 and CCLR0 in TMG. If TCG overflows when the
input capture signal is high, the OVFH bit is set in TMG; if TCG overflows when the input
capture signal is low, the OVFL bit is set in TMG. If the OVIE bit in TMG is 1 when these
bits are set, IRRTG is set to 1 in IRR2, and if the IENTG bit in IENR2 is 1, timer G sends
an interrupt request to the CPU. For details of the interrupt, see section 3.3, Interrupts.
Timer G has a built-in noise canceler that enables high-frequency component noise to be
eliminated from pulses input from the TMIG pin. For details, see section 9.5.3, Noise
Canceler.
Note: * An input capture signal may be generated when TMIG is modified.
b. Interval timer operation
When the TMIG bit is cleared to 0 in PMR1, timer G functions as an interval timer.
Following a reset, TCG starts incrementing on the φ/64 internal clock. The input clock can
be selected from four internal clock sources by bits CKS1 and CKS0 in TMG. TCG
increments on the selected clock, and when it overflows from H'FF to H'00, the OVFL bit
is set to 1 in TMG. If the OVIE bit in TMG is 1 at this time, IRRTG is set to 1 in IRR2,
and if the IENTG bit in IENR2 is 1, timer G sends an interrupt request to the CPU. For
details of the interrupt, see section 3.3, Interrupts.
2. Increment Timing
TCG is incremented by internal clock input. Bits CKS1 and CKS0 in TMG select one of four
internal clock sources (φ/64, φ/32, φ/2, or φw/4) created by dividing the system clock (φ) or watch
clock (φw).
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Section 9 Timers
3. Input Capture Input Timing
a. Without noise cancellation function
For input capture input, dedicated input capture functions are provided for rising and falling
edges.
Figure 9.11 shows the timing for rising/falling edge input capture input.
Input capture
input signal
Input capture
signal F
Input capture
signal R
Figure 9.11 Input Capture Input Timing (without Noise Cancellation Function)
b. With noise cancellation function
When noise cancellation is performed on the input capture input, the passage of the input
capture signal through the noise canceler results in a delay of five sampling clock cycles from
the input capture input signal edge.
Figure 9.12 shows the timing in this case.
Input capture
input signal
Sampling clock
Noise canceler
output
Input capture
signal R
Figure 9.12 Input Capture Input Timing (with Noise Cancellation Function)
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Section 9 Timers
4. Timing of Input Capture by Input Capture Input
Figure 9.13 shows the timing of input capture by input capture input
Input capture
signal
TCG
N-1
N
N+1
Input capture
H'XX
register
N
Figure 9.13 Timing of Input Capture by Input Capture Input
5. TCG Clear Timing
TCG can be cleared by the rising edge, falling edge, or both edges of the input capture input
signal.
Figure 9.14 shows the timing for clearing by both edges.
Input capture
input signal
Input capture
signal F
Input capture
signal R
TCG
N
H'00
N
H'00
Figure 9.14 TCG Clear Timing
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Section 9 Timers
6. Timer G Operation Modes
Timer G operation modes are shown in table 9.13.
Table 9.13 Timer G Operation Modes
Reset Active
TCG
Input capture
Reset Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
Interval
Reset Functions* Functions* Functions/ Functions/ Functions/ Halted
halted*
halted*
halted*
Halted
ICRGF
Reset Functions* Functions* Functions/ Functions/ Functions/ Held
halted*
halted*
halted*
Held
ICRGR
Reset Functions* Functions* Functions/ Functions/ Functions/ Held
halted*
halted*
halted*
Held
Reset Functions Held
Held
TMG
Note:
9.5.5
*
Sleep
Watch
Module
Subactive Subsleep Standby Standby
Operation Mode
Held
Functions Held
Held
When φw/4 is selected as the TCG internal clock in active mode or sleep mode, since
the system clock and internal clock are mutually asynchronous, synchronization is
maintained by a synchronization circuit. This results in a maximum count cycle error of
1/φ (s). When φw/4 is selected as the TCG internal clock in watch mode, TCG and the
noise canceler operate on the φw/4 internal clock without regard to the φ subclock
(φw/8, φw/4, φw/2). Note that when another internal clock is selected, TCG and the
noise canceler do not operate, and input of the input capture input signal does not result
in input capture.
To operate the timer G in subactive mode or subsleep mode, select φw/4 as the TCG
internal clock and φw/2 as the subclock φSUB. Note that when other internal clock is
selected, or when φw/8 or φw/4 is selected as the subclock φSUB, TCG and the noise
canceler do not operate.
Application Notes
1. Internal Clock Switching and TCG Operation
Depending on the timing, TCG may be incremented by a switch between difference internal clock
sources. Table 9.14 shows the relation between internal clock switchover timing (by write to bits
CKS1 and CKS0) and TCG operation.
When TCG is internally clocked, an increment pulse is generated on detection of the falling edge
of an internal clock signal, which is divided from the system clock (φ) or subclock (φw). For this
reason, in a case like No. 3 in table 9.14 where the switch is from a high clock signal to a low
clock signal, the switchover is seen as a falling edge, causing TCG to increment.
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Section 9 Timers
Table 9.14 Internal Clock Switching and TCG Operation
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
1
Goes from low level to low level
Clock before
switching
Clock after
switching
Count
clock
TCG
N
N+1
Write to CKS1 and CKS0
2
Goes from low level to high level
Clock before
switching
Clock before
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
3
Goes from high level to low level
Clock before
switching
Clock before
switching
*
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
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Section 9 Timers
No.
Clock Levels Before and After
Modifying Bits CKS1 and CKS0
TCG Operation
4
Goes from high level to high level
Clock before
switching
Clock before
switching
Count
clock
TCG
N
N+1
N+2
Write to CKS1 and CKS0
Note:
*
The switchover is seen as a falling edge, and TCG is incremented.
2. Notes on Port Mode Register Modification
The following points should be noted when a port mode register is modified to switch the input
capture function or the input capture input noise canceler function.
• Switching input capture input pin function
Note that when the pin function is switched by modifying TMIG in port mode register 1 (PMR1),
which performs input capture input pin control, an edge will be regarded as having been input at
the pin even though no valid edge has actually been input. Input capture input signal input edges,
and the conditions for their occurrence, are summarized in table 9.15.
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Section 9 Timers
Table 9.15 Input Capture Input Signal Input Edges Due to Input Capture Input Pin
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge
When TMIG is modified from 0 to 1 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
Generation of falling edge
When TMIG is modified from 1 to 0 while the TMIG pin is high
When NCS is modified from 0 to 1 while the TMIG pin is low, then
TMIG is modified from 0 to 1 before the signal is sampled five times by
the noise canceler
When NCS is modified from 0 to 1 while the TMIG pin is high, then
TMIG is modified from 1 to 0 after the signal is sampled five times by
the noise canceler
Note: When the P13 pin is not set as an input capture input pin, the timer G input capture input
signal is low.
• Switching input capture input noise canceler function
When performing noise canceler function switching by modifying NCS in port mode register 3
(PMR3), which controls the input capture input noise canceler, TMIG should first be cleared to 0.
Note that if NCS is modified without first clearing TMIG, an edge will be regarded as having been
input at the pin even though no valid edge has actually been input. Input capture input signal input
edges, and the conditions for their occurrence, are summarized in table 9.16.
Table 9.16 Input Capture Input Signal Input Edges Due to Noise Canceler Function
Switching, and Conditions for Their Occurrence
Input Capture Input
Signal Input Edge
Conditions
Generation of rising edge
When the TMIG pin level is switched from low to high while TMIG is
set to 1, then NCS is modified from 0 to 1 before the signal is sampled
five times by the noise canceler
Generation of falling edge
When the TMIG pin level is switched from high to low while TMIG is
set to 1, then NCS is modified from 1 to 0 before the signal is sampled
five times by the noise canceler
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Section 9 Timers
When the pin function is switched and an edge is generated in the input capture input signal, if this
edge matches the edge selected by the input capture interrupt select (IIEGS) bit, the interrupt
request flag will be set to 1. The interrupt request flag should therefore be cleared to 0 before use.
Figure 9.15 shows the procedure for port mode register manipulation and interrupt request flag
clearing. When switching the pin function, set the interrupt-disabled state before manipulating the
port mode register, then, after the port mode register operation has been performed, wait for the
time required to confirm the input capture input signal as an input capture signal (at least two
system clocks when the noise canceler is not used; at least five sampling clocks when the noise
canceler is used), before clearing the interrupt enable flag to 0. There are two ways of preventing
interrupt request flag setting when the pin function is switched: by controlling the pin level so that
the conditions shown in tables 9.15 and 9.16 are not satisfied, or by setting the opposite of the
generated edge in the IIEGS bit in TMG.
Set I bit to 1 in CCR
Manipulate port mode register
TMIG confirmation time
Clear interrupt request flag to 0
Clear I bit to 0 in CCR
Disable interrupts. (Interrupts can also be disabled by
manipulating the interrupt enable bit in interrupt enable
register 2.)
After manipulating he port mode register, wait for the
TMIG confirmation time (at least two system clocks when
the noise canceler is not used; at least five sampling
clocks when the noise canceler is used), then clear the
interrupt enable flag to 0.
Enable interrupts
Figure 9.15 Port Mode Register Manipulation and Interrupt Enable Flag Clearing
Procedure
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Section 9 Timers
9.5.6
Timer G Application Example
Using timer G, it is possible to measure the high and low widths of the input capture input signal
as absolute values. For this purpose, CCLR1 and CCLR0 should both be set to 1 in TMG.
Figure 9.16 shows an example of the operation in this case.
Input capture
input signal
H'FF
Input capture
register GF
Input capture
register GR
H'00
TCG
Counter cleared
Figure 9.16 Timer G Application Example
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Section 9 Timers
9.6
Watchdog Timer
9.6.1
Overview
The watchdog timer has an 8-bit counter that is incremented by an input clock. If a system
runaway allows the counter value to overflow before being rewritten, the watchdog timer can reset
the chip internally.
1. Features
Features of the watchdog timer are given below.
• Incremented by internal clock source (φ/8192 or φw/32).
• A reset signal is generated when the counter overflows. The overflow period can be set from
from 1 to 256 times 8192/φ or 32/φw (from approximately 4 ms to 1000 ms when φ = 2.00
MHz).
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
2. Block Diagram
Figure 9.17 shows a block diagram of the watchdog timer.
φw/32
PSS
φ/8192
TCW
Legend:
TCSRW: Timer control/status register W
TCW:
Timer counter W
PSS:
Prescaler S
Figure 9.17 Block Diagram of Watchdog Timer
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Internal data bus
φ
TCSRW
Reset signal
Section 9 Timers
3. Register Configuration
Table 9.17 shows the register configuration of the watchdog timer.
Table 9.17 Watchdog Timer Registers
Name
Abbr.
R/W
Initial Value
Address
Timer control/status register W
TCSRW
R/W
H'AA
H'FFB2
Timer counter W
TCW
R/W
H'00
H'FFB3
Clock stop register 2
CKSTP2
R/W
H'FF
H'FFFB
Port mode register 3
PMR3
R/W
H'00
H'FFCA
9.6.2
Register Descriptions
1. Timer Control/Status Register W (TCSRW)
Bit
7
6
5
4
3
2
1
0
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
Initial value
1
0
1
0
1
0
1
0
Read/Write
R
R/(W)*
R
R/(W)*
R
R/(W)*
R
R/(W)*
Note: * Write is permitted only under certain conditions, which are given in the descriptions of
the individual bits.
TCSRW is an 8-bit read/write register that controls write access to TCW and TCSRW itself,
controls watchdog timer operations, and indicates operating status.
Bit 7: Bit 6 write inhibit (B6WI)
Bit 7 controls the writing of data to bit 6 in TCSRW.
Bit 7
B6WI
Description
0
Bit 6 is write-enabled
1
Bit 6 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
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Section 9 Timers
Bit 6: Timer counter W write enable (TCWE)
Bit 6 controls the writing of data to TCW.
Bit 6
TCWE
Description
0
Data cannot be written to TCW
1
Data can be written to TCW
(initial value)
Bit 5: Bit 4 write inhibit (B4WI)
Bit 5 controls the writing of data to bit 4 in TCSRW.
Bit 5
B4WI
Description
0
Bit 4 is write-enabled
1
Bit 4 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 4: Timer control/status register W write enable (TCSRWE)
Bit 4 controls the writing of data to TCSRW bits 2 and 0.
Bit 4
TCSRWE
Description
0
Data cannot be written to bits 2 and 0
1
Data can be written to bits 2 and 0
(initial value)
Bit 3: Bit 2 write inhibit (B2WI)
Bit 3 controls the writing of data to bit 2 in TCSRW.
Bit 3
B2WI
Description
0
Bit 2 is write-enabled
1
Bit 2 is write-protected
This bit is always read as 1. Data written to this bit is not stored.
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(initial value)
Section 9 Timers
Bit 2: Watchdog timer on (WDON)
Bit 2 enables watchdog timer operation.
Bit 2
WDON
Description
0
Watchdog timer operation is disabled
Clearing condition:
Reset, or when TCSRWE = 1 and 0 is written in both B2WI and
WDON
1
Watchdog timer operation is enabled
Setting condition:
When TCSRWE = 1 and 0 is written in B2WI and 1 is written in
WDON
(initial value)
Counting starts when this bit is set to 1, and stops when this bit is cleared to 0.
Bit 1: Bit 0 write inhibit (B0WI)
Bit 1 controls the writing of data to bit 0 in TCSRW.
Bit 1
B0WI
Description
0
Bit 0 is write-enabled
1
Bit 0 is write-protected
(initial value)
This bit is always read as 1. Data written to this bit is not stored.
Bit 0: Watchdog timer reset (WRST)
Bit 0 indicates that TCW has overflowed, generating an internal reset signal. The internal reset
signal generated by the overflow resets the entire chip. WRST is cleared to 0 by a reset from the
RES pin, or when software writes 0.
Bit 0
WRST
Description
0
Clearing condition:
Reset by RES pin
When TCSRWE = 1, and 0 is written in both B0WI and WRST
1
Setting condition:
When TCW overflows and an internal reset signal is generated
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Section 9 Timers
2. Timer Counter W (TCW)
Bit
7
6
5
4
3
2
1
0
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCW is an 8-bit read/write up-counter, which is incremented by internal clock input. The input
clock is φ/8192 or φw/32. The TCW value can always be written or read by the CPU.
When TCW overflows from H'FF to H'00, an internal reset signal is generated and WRST is set to
1 in TCSRW. Upon reset, TCW is initialized to H'00.
3. Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
—
—
—
—
3
2
1
0
AECKSTP WDCKSTP PWCKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the watchdog timer is described here. For details of the other
bits, see the sections on the relevant modules.
Bit 2: Watchdog timer module standby mode control (WDCKSTP)
Bit 2 controls setting and clearing of module standby mode for the watchdog timer.
WDCKSTP
Description
0
Watchdog timer is set to module standby mode
1
Watchdog timer module standby mode is cleared
(initial value)
Note: WDCKSTP is valid when the WDON bit is cleared to 0 in timer control/status register W
(TCSRW). If WDCKSTP is set to 0 while WDON is set to 1 (during watchdog timer
operation), 0 will be set in WDCKSTP but the watchdog timer will continue its watchdog
function and will not enter module standby mode. When the watchdog function ends and
WDON is cleared to 0 by software, the WDCKSTP setting will become valid and the
watchdog timer will enter module standby mode.
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Section 9 Timers
4. Port Mode Register 3 (PMR3)
Bit
7
6
5
4
—
—
—
—
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
AECKSTP WDCKSTP PWCKSTP LDCKSTP
PMR3 is an 8-bit read/write register, mainly controlling the selection of pin functions for port 3
pins. Only the bit relating to the watchdog timer is described here. For details of the other bits,
see section 8, I/O Ports.
Bit 5: Watchdog timer source clock select (WDCKS)
WDCKS
Description
0
φ/8192 selected
1
φw/32 selected
9.6.3
(initial value)
Timer Operation
The watchdog timer has an 8-bit counter (TCW) that is incremented by clock input (φ/8192 or
φw/32). The input clock is selected by bit WDCKS in port mode register 3 (PMR3): φ/8192 is
selected when WDCKS is cleared to 0, and φw/32 when set to 1. When TCSRWE = 1 in TCSRW,
if 0 is written in B2WI and 1 is simultaneously written in WDON, TCW starts counting up. When
the TCW count value reaches H'FF, the next clock input causes the watchdog timer to overflow,
and an internal reset signal is generated one base clock (φ or φSUB) cycle later. The internal reset
signal is output for 512 clock cycles of the φOSC clock. It is possible to write to TCW, causing
TCW to count up from the written value. The overflow period can be set in the range from 1 to
256 input clocks, depending on the value written in TCW.
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Section 9 Timers
Figure 9.18 shows an example of watchdog timer operations.
Example: φ = 2 MHz and the desired overflow period is 30 ms.
2 × 106
× 30 × 10–3 = 7.3
8192
The value set in TCW should therefore be 256 – 8 = 248 (H'F8).
TCW overflow
H'FF
H'F8
TCW count
value
H'00
Start
H'F8 written
in TCW
H'F8 written in TCW
Reset
Internal reset
signal
512 φOSC clock cycles
Figure 9.18 Typical Watchdog Timer Operations (Example)
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Section 9 Timers
9.6.4
Watchdog Timer Operation States
Table 9.18 summarizes the watchdog timer operation states.
Table 9.18 Watchdog Timer Operation States
Operation
Mode
Reset
Active
TCW
Reset
Functions Functions Halted
Functions/ Halted
Halted*
Halted
Halted
TCSRW
Reset
Functions Functions Retained
Functions/ Retained
Halted*
Retained
Retained
Note:
*
Sleep
Watch
Subactive Subsleep Standby
Module
Standby
Functions when φw/32 is selected as the input clock.
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Section 9 Timers
9.7
Asynchronous Event Counter (AEC)
9.7.1
Overview
The asynchronous event counter is incremented by external event clock input.
1. Features
Features of the asynchronous event counter are given below.
• Can count asynchronous events
• Can count external events input asynchronously without regard to the operation of base clocks
φ and φSUB.
• The counter has a 16-bit configuration, enabling it to count up to 65536 (216) events.
• Can also be used as two independent 8-bit event counter channels.
• Counter resetting and halting of the count-up function controllable by software
• Automatic interrupt generation on detection of event counter overflow
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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Section 9 Timers
2. Block Diagram
Figure 9.19 shows a block diagram of the asynchronous event counter.
IRREC
OVH
ECH
CK
ECL
CK
AEVH
Internal data bus
ECCSR
OVL
AEVL
Legend:
ECCSR
ECH
ECL
AEVH
AEVL
IRREC
: Event counter control/status register
: Event counter H
: Event counter L
: Asynchronous event input H
: Asynchronous event input L
: Event counter overflow interrupt request flag
Figure 9.19 Block Diagram of Asynchronous Event Counter
3. Pin Configuration
Table 9.19 shows the asynchronous event counter pin configuration.
Table 9.19 Pin Configuration
Name
Abbr.
I/O
Function
Asynchronous event input H
AEVH
Input
Event input pin for input to event counter H
Asynchronous event input L
AEVL
Input
Event input pin for input to event counter L
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Section 9 Timers
4. Register Configuration
Table 9.20 shows the register configuration of the asynchronous event counter.
Table 9.20 Asynchronous Event Counter Registers
Name
Abbr.
R/W
Initial Value
Address
Event counter control/status register
ECCSR
R/W
H'00
H'FF95
Event counter H
ECH
R
H'00
H'FF96
Event counter L
ECL
R
H'00
H'FF97
Clock stop register 2
CKSTP2
R/W
H'FF
H'FFFB
9.7.2
Register Descriptions
1. Event Counter Control/Status Register (ECCSR)
Bit
7
6
5
4
3
2
1
0
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Bits 7 and 6 can only be written with 0, for flag clearing.
ECCSR is an 8-bit read/write register that controls counter overflow detection, counter resetting,
and halting of the count-up function.
ECCSR is initialized to H'00 upon reset.
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Section 9 Timers
Bit 7: Counter overflow flag H (OVH)
Bit 7 is a status flag indicating that ECH has overflowed from H'FF to H'00. This flag is set when
ECH overflows. It is cleared by software but cannot be set by software. OVH is cleared by
reading it when set to 1, then writing 0.
When ECH and ECL are used as a 16-bit event counter with CH2 cleared to 0, OVH functions as a
status flag indicating that the 16-bit event counter has overflowed from H'FFFF to H'0000.
Bit 7
OVH
Description
0
ECH has not overflowed
Clearing condition:
After reading OVH = 1, cleared by writing 0 to OVH
1
ECH has overflowed
Setting condition:
Set when ECH overflows from H'FF to H'00
(initial value)
Bit 6: Counter overflow flag L (OVL)
Bit 6 is a status flag indicating that ECL has overflowed from H'FF to H'00. This flag is set when
ECL overflows. It is cleared by software but cannot be set by software. OVL is cleared by
reading it when set to 1, then writing 0.
Bit 6
OVL
Description
0
ECL has not overflowed
Clearing condition:
After reading OVL = 1, cleared by writing 0 to OVL
1
ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00 while CH2 is set to 1
(initial value)
Bit 5: Reserved bit
Bit 5 is reserved; it can be read and written, and is initialized to 0 upon reset.
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Bit 4: Channel select (CH2)
Bit 4 selects whether ECH and ECL are used as a single-channel 16-bit event counter or as two
independent 8-bit event counter channels. When CH2 is cleared to 0, ECH and ECL function as a
16-bit event counter which is incremented each time an event clock is input to the AEVL pin as
asynchronous event input. In this case, the overflow signal from ECL is selected as the ECH input
clock. When CH2 is set to 1, ECH and ECL function as independent 8-bit event counters which
are incremented each time an event clock is input to the AEVH or AEVL pin, respectively, as
asynchronous event input.
Bit 4
CH2
Description
0
ECH and ECL are used together as a single-channel 16-bit event counter
(initial value)
1
ECH and ECL are used as two independent 8-bit event counter channels
Bit 3: Count-up enable H (CUEH)
Bit 3 enables event clock input to ECH. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECH value is held. The AEVH pin or the ECL overflow signal can be selected as the event clock
source by bit CH2.
Bit 3
CUEH
Description
0
ECH event clock input is disabled
ECH value is held
1
ECH event clock input is enabled
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(initial value)
Section 9 Timers
Bit 2: Count-up enable L (CUEL)
Bit 3 enables event clock input to ECL. When 1 is written to this bit, event clock input is enabled
and increments the counter. When 0 is written to this bit, event clock input is disabled and the
ECL value is held.
Bit 2
CUEL
Description
0
ECL event clock input is disabled
ECL value is held
1
ECL event clock input is enabled
(initial value)
Bit 1: Counter reset control H (CRCH)
Bit 1 controls resetting of ECH. When this bit is cleared to 0, ECH is reset. When 1 is written to
this bit, the counter reset is cleared and the ECH count-up function is enabled.
Bit 1
CRCH
Description
0
ECH is reset
1
ECH reset is cleared and count-up function is enabled
(initial value)
Bit 0: Counter reset control L (CRCL)
Bit 0 controls resetting of ECL. When this bit is cleared to 0, ECL is reset. When 1 is written to
this bit, the counter reset is cleared and the ECL count-up function is enabled.
Bit 0
CRCL
Description
0
ECL is reset
1
ECL reset is cleared and count-up function is enabled
(initial value)
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Section 9 Timers
2. Event Counter H (ECH)
Bit
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
ECH is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the upper 8-bit up-counter of a 16-bit event counter configured in combination with ECL.
Either the external asynchronous event AEVH pin or the overflow signal from lower 8-bit counter
ECL can be selected as the input clock source by bit CH2. ECH can be cleared to H'00 by
software, and is also initialized to H'00 upon reset.
3. Event Counter L (ECL)
ECL is an 8-bit read-only up-counter that operates either as an independent 8-bit event counter or
as the lower 8-bit up-counter of a 16-bit event counter configured in combination with ECH. The
event clock from the external asynchronous event AEVL pin is used as the input clock source.
ECL can be cleared to H'00 by software, and is also initialized to H'00 upon reset.
Bit
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial Value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
1
0
4. Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
—
—
—
—
3
2
AECKSTP WDCKSTP PWCKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the asynchronous event counter is described here. For details of
the other bits, see the sections on the relevant modules.
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Section 9 Timers
Bit 3: Asynchronous event counter module standby mode control (AECKSTP)
Bit 3 controls setting and clearing of module standby mode for the asynchronous event counter.
AECKSTP
Description
0
Asynchronous event counter is set to module standby mode
1
Asynchronous event counter module standby mode is cleared
9.7.3
(initial value)
Operation
1. 16-bit Event Counter Operation
When bit CH2 is cleared to 0 in ECCSR, ECH and ECL, operate as a 16-bit event counter. Figure
9.20 shows an example of the software processing when ECH and ECL are used as a 16-bit event
counter.
Start
Clear CH2 to 0
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH and OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.20 Example of Software Processing when Using ECH and ECL as 16-Bit Event
Counter
As CH2 is cleared to 0 by a reset, ECH and ECL operate as a 16-bit event counter after a reset.
They can also be used as a 16-bit event counter by carrying out the software processing shown in
the example in figure 9.20. The operating clock source is asynchronous event input from the
AEVL pin. When the next clock is input after the count value reaches H'FF in both ECH and
ECL, ECH and ECL overflow from H'FFFF to H'0000, the OVH flag is set to 1 in ECCSR, the
ECH and ECL count values each return to H'00, and counting up is restarted. When overflow
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Section 9 Timers
occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is 1 at this time, an interrupt
request is sent to the CPU.
2. 8-bit Event Counter Operation
When bit CH2 is set to 1 in ECCSR, ECH and ECL operate as independent 8-bit event counters.
Figure 9.21 shows an example of the software processing when ECH and ECL are used as 8-bit
event counters.
Start
Set CH2 to 1
Clear CUEH, CUEL, CRCH, and CRCL to 0
Clear OVH, OVL to 0
Set CUEH, CUEL, CRCH, and CRCL to 1
End
Figure 9.21 Example of Software Processing when Using ECH and ECL as 8-Bit Event
Counters
ECH and ECL can be used as 8-bit event counters by carrying out the software processing shown
in the example in figure 9.21. The 8-bit event counter operating clock source is asynchronous
event input from the AEVH pin for ECH, and asynchronous event input from the AEVL pin for
ECL. When the next clock is input after the ECH count value reaches H'FF, ECH overflows, the
OVH flag is set to 1 in ECCSR, the ECH count value returns to H'00, and counting up is restarted.
Similarly, when the next clock is input after the ECL count value reaches H'FF, ECL overflows,
the OVL flag is set to 1 in ECCSR, the ECL count value returns to H'00, and counting up is
restarted. When overflow occurs, the IRREC bit is set to 1 in IRR2. If the IENEC bit in IENR2 is
1 at this time, an interrupt request is sent to the CPU.
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Section 9 Timers
9.7.4
Asynchronous Event Counter Operation Modes
Asynchronous event counter operation modes are shown in table 9.21.
Table 9.21 Asynchronous Event Counter Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive Subsleep
Standby
Module
Standby
ECCSR
Reset
Functions
Functions
Held*
Functions
Functions
Held*
Held
ECH
Reset
Functions
Functions
Functions* Functions
Functions
Functions* Halted
ECL
Reset
Functions
Functions
Functions* Functions
Functions
Functions* Halted
Note:
9.7.5
*
When an asynchronous external event is input, the counter increments but the counter
overflow H/L flags are not affected.
Application Notes
1. When reading the values in ECH and ECL, the correct value will not be returned if the event
counter increments during the read operation. Therefore, if the counter is being used in the 8bit mode, clear bits CUEH and CUEL in ECCSR to 0 before reading ECH or ECL. If the
counter is being used in the 16-bit mode, clear CUEL only to 0 before reading ECH or ECL.
2. In the H8/3847R Group, if the internal power supply step-down circuit is not used, the
maximum clock frequency to be input to the AEVH and AEVL pins is 16 MHz when Vcc =
4.5 to 5.5 V, 10 MHz when Vcc = 2.7 to 5.5 V, and 4 MHz when Vcc = 1.8 to 5.5 V. If the
internal power step-down circuit is used, the maximum clock frequency to be input is 10 MHz
when Vcc = 2.7 to 5.5 V, and 4 MHz when Vcc = 1.8 to 5.5 V. In the H8/3847S Group, the
maximum clock frequency to be input is 10 MHz when Vcc = 2.7 to 3.6 V, and 4 MHz when
Vcc = 1.8 to 3.6 V. In the H8/38347 Group and H8/38447 Group, the maximum clock
frequency to be input is 16 MHz when Vcc = 2.7 to 5.5 V. In addition, ensure that the high and
low widths of the clock are at least 32 ns. The duty cycle is immaterial.
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Section 9 Timers
Maximum AEVH/AEVL Pin
Input Clock Frequency
Mode
16-bit mode
H8/3847R Group
• When not using the internal
step-down circuit
VCC = 4.5 to 5.5 V/16 MHz
VCC = 2.7 to 5.5 V/10 MHz
VCC = 1.8 to 5.5 V/4 MHz
• When using the internal
step-down circuit
VCC = 2.7 to 5.5 V/10 MHz
VCC = 1.8 to 5.5 V/4 MHz
8-bit mode Active (high-speed), sleep (high-speed)
H8/3847S Group
VCC = 2.7 to 3.6 V/10 MHz
VCC = 1.8 to 3.6 V/4 MHz
H8/38347 Group
VCC = 2.7 to 5.5 V/16 MHz
H8/38447 Group
VCC = 4.5 to 5.5 V/16 MHz
VCC = 2.7 to 5.5 V/10 MHz
8-bit mode Active (medium-speed), sleep (medium-speed) (φ/16)
fOSC = 1 MHz to 16 MHz
8-bit mode Watch, subactive, subsleep, standby
φw = 32.768 kHz or 38.4 kHz
2 · fOSC
(φ/32)
fOSC
(φ/64)
1/2 · fOSC
(φ/128) 1/4 · fOSC
(φw/2)
1000 kHz
(φw/4)
500 kHz
(φw/8)
250 kHz
3. When using the clock in the 16-bit mode, set CUEH to 1 first, then set CRCH to 1 in ECCSR.
Or, set CUEH and CRCH simultaneously before inputting the clock. After that, do not change
the CUEH value while using in the 16-bit mode. Otherwise, an error counter increment may
occur. Also, to reset the counter, clear CRCH and CRCL to 0 simultaneously or clear CRCL
and CRCH to 0 sequentially, in that order.
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Section 10 Serial Communication Interface
Section 10 Serial Communication Interface
10.1
Overview
This LSI is provided with three serial communication interface (SCI) channels. The functions of
the three SCI channels are summarized in table 10.1.
Table 10.1 Overview of SCI Functions
SCI Name
Functions
Features
SCI1
Synchronous serial transfer functions
•Choice of transfer data length (8 or 16
bits)
•Choice of 8 internal clocks (φ/1024 to φ/4,
φW /4) or external clock
•Continuous clock output function
•Interrupt generated on completion of
transfer
Synchronous serial transfer functions
•8-bit transfer data length
•On-chip baud rate generator
SCI31,
SCI32
•Transmission/reception/simultaneous
transmission and reception
Asynchronous serial transfer functions
•Multiprocessor communication function
•Open-drain output option
•Receive error detection
•Break detection
•Interrupt generated on completion of
transfer or in case of error
•Choice of transfer data length (5 or 7 or 8
bits)
•Choice of stop bit length (1 or 2 bits)
•Parity addition function
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Section 10 Serial Communication Interface
10.2
SCI1
10.2.1
Overview
Serial communication interface 1 (SCI1) can carry out 8-bit or 16-bit serial data transfer in
synchronous mode. It is also provided with a communication function called a Synchronized
Serial Bus (SSB) that enables a number of ICs to be controlled.
1. Features
Features of SCI1 are listed below.
• Choice of 8-bit or 16-bit transfer data length
• Choice of 8 internal clocks (φ/1024, φ/256, φ/64, φ/32, φ/16, φ/8, φ/4, or φW/4) or external
clock as clock source
• Interrupt request generated on completion of transfer
• Choice of hold mode or latch mode in SSB mode
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Section 10 Serial Communication Interface
2. Block Diagram
Figure 10.1 shows a block diagram of SCI1.
φ
PSS
SCK1
SCR1
Transmit/receive
control circuit
SCSR1
Transfer bit counter
SI1
Transfer bit counter
φW/4
SDRU
SDRL
SO1
IRRS1
Legend:
SCR1:
SCSR1:
SDRU:
SDRL:
IRRS1:
PSS:
Serial control register 1
Serial control status register 1
Serial data register U
Serial data register L
Serial 1 interrupt request flag
Prescaler S
Figure 10.1 SCI1 Block Diagram
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Section 10 Serial Communication Interface
3. Pin Configuration
Table 10.2 shows the SCI1 pin configuration.
Table 10.2 SCI1 Pin Configuration
Name
Abbr.
I/O
Function
SCI1 clock
SCK1
I/O
SCI1 clock input/output
SCI1 data input
SI1
Input
SCI1 receive data input
SCI1 data output
SO1
Output
SCI1 transmit data output
4. Register Configuration
Table 10.3 shows the SCI1 register configuration.
Table 10.3 Registers
Name
Abbr.
R/W
Initial Value
Address
Serial control register 1
SCR1
R/W
H'00
H'FFA0
Serial control status register 1
SCSR1
R/W
H'9C
H'FFA1
Serial data register U
SDRU
R/W
Undefined
H'FFA2
Serial data register L
SDRL
R/W
Undefined
H'FFA3
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
10.2.2
Register Descriptions
1. Serial Control Register 1 (SCR1)
Bit
7
6
5
4
3
2
1
0
SNC1
SNC0
MRKON
LTCH
CKS3
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR1 is an 8-bit read/write register that controls the operating mode, serial clock source, and
prescaler division ratio.
Upon reset, SCR1 is initialized to H'00. If this register is written to during transfer, transfer will be
halted.
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Section 10 Serial Communication Interface
Bits 7 and 6: Operating mode select 1 and 0 (SNC1, SNC0)
Bits 7 and 6 select the operating mode.
Bit 7
SNC1
Bit 6
SNC0
Description
0
0
8-bit synchronous mode
0
1
16-bit synchronous mode
1
0
1
1
Continuous clock output mode*
2
Reserved*
(initial value)
1
Notes: 1. Use pins SI1 and SO1 as ports.
2. Do not set bits SNC1 and SNC0 to 11.
Bit 5: TAIL MARK control (MRKON)
Bit 5 controls tail mark output after transfer of 8-bit or 16-bit data.
Bit 5
MRKON
Description
0
TAIL MARK is not output (synchronous mode)
1
TAIL MARK is output (SSB mode)
(initial value)
Bit 4: LATCH TAIL select (LTCH)
Bit 4 selects whether LATCH TAIL or HOLD TAIL is output as the tail mark when MRKON = 1
(i.e. in SSB mode).
Bit 4
LTCH
Description
0
HOLD TAIL is output
1
LATCH TAIL is output
(initial value)
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Section 10 Serial Communication Interface
Bit 3: Clock source select 3 (CKS3)
Bit 3 selects the clock source to be supplied and sets the SCK1 pin to input or output mode.
Bit 3
CKS3
Description
0
Clock source is prescaler S, SCK1 is output pin
1
Clock source is external clock, SCK1 is input pin
(initial value)
Bits 2 to 0: Clock select 2 to 0 (CKS2 to CKS0)
When CKS3 is cleared to 0, bits 2 to 0 selects the prescaler division ratio and the serial clock
cycle.
Serial Clock Cycle
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Prescaler Division Ratio
φ = 2.5 MHz
0
0
0
φ/1024 (initial value)
409.6 µs
0
0
1
φ/256
102.4 µs
0
1
0
φ/64
25.6 µs
0
1
1
φ/32
12.8 µs
1
0
0
φ/16
6.4 µs
1
0
1
φ/8
3.2 µs
1
1
0
φ/4
1.6 µs
1
1
1
φW /4
122 µs
2. Serial Control Status Register 1 (SCSR1)
Bit
7
6
5
4
3
2
1
0
—
SOL
ORER
—
—
—
MTRF
STF
Initial value
1
0
0
1
1
1
0
0
Read/Write
—
R/W
R/(W)*
—
—
—
R
R/W
Note: * Only a write of 0 for flag clearing is possible.
SCSR1 is an 8-bit register that indicates the operational and error status of SCI1.
Upon reset, SCSR1 is initialized to H'9C.
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Section 10 Serial Communication Interface
Bit 7: Reserved bit
Bits 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6: Extension data bit (SOL)
The SOL bit changes the output level of the SO1 pin. When read, SOL returns the output level of
the SO1 pin. After transfer is completed, SO1 pin output retains the value of the last bit of the
transmit data, and therefore the SO1 pin output level can be changed by manipulating this bit
before or after transmission. However, the SOL bit setting becomes invalid when the next
transmission starts*. Therefore, when changing the SO1 pin output level after transmission, a write
operation must be performed on the SOL bit each time transmission is completed. Writing to this
register during data transfer will cause incorrect operation, so this register should not be
manipulated during transmission.
Note: * The SOL bit setting is also invalid in SSB mode.
Bit 6
SOL
Description
0
Read
SO1 pin output level is low
Write
Changes SO1 pin output to low level
Read
SO1 pin output level is high
Write
Changes SO1 pin output to high level
1
(initial value)
Bit 5: Overrun error flag (ORER)
Bit 5 indicates that an overrun error has occurred when using an external clock. If extra pulses are
superimposed on the regular serial clock due to extraneous noise, etc., the transfer data cannot be
guaranteed. If the clock is input after transfer is completed, this will be interpreted as an overrun
state and this bit will be set to 1.
Bit 5
ORER
Description
0
Clearing condition:
After reading ORER = 1, cleared by writing 0 to ORER
(initial value)
1
Setting condition:
When an external clock is used and the clock is input after transfer is completed
Bits 4 to 2: Reserved bits
Bits 4 to 2 are reserved; they are always read as 0 and cannot be modified.
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Section 10 Serial Communication Interface
Bit 1: Tail mark transmission flag (MTRF)
When MRKON = 1, bit 1 indicates that a tail mark is being transmitted. MTRF is a read-only bit,
and cannot be modified.
Bit 1
MTRF
Description
0
Idle state, or 8-bit/16-bit data transfer in progress
1
Tail mark transmission in progress
(initial value)
Bit 0: Start flag (STF)
The STF bit controls the start of transfer operations. SCI1 transfer operation is started when this
bit is set to 1.
STF remains set to 1 during transfer and while SCI1 is waiting for a start bit, and is cleared to 0
when transfer ends.
Bit 0
STF
Description
0
Read
Transfer operation stopped
Write
Invalid
Read
Transfer operation in progress
Write
Starts transfer operation
1
(initial value)
3. Serial Data Register U (SDRU)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SDRU7
SDRU6
SDRU5
SDRU4
SDRU3
SDRU2
SDRU1
SDRU0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRU is an 8-bit read/write register used as the data register for the upper 8 bits in 16-bit transfer
(while SDRL is used for the lower 8 bits).
The data written into SDRU is output to SDRL in LSB-first order. In the replacement process, data
is input LSB-first from the SI1 pin, and the data is shifted in the MSB → LSB direction.
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Section 10 Serial Communication Interface
SDRU read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRU is undefined upon reset.
4. Serial Data Register L (SDRL)
7
6
5
4
3
2
1
0
SDRL7
SDRL6
SDRL5
SDRL4
SDRL3
SDRL2
SDRL1
SDRL0
Bit
Initial value
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SDRL is an 8-bit read/write register used as the data register in 8-bit transfer, and as the data
register for the lower 8 bits in 16-bit transfer (while SDRU is used for the upper 8 bits).
In 8-bit transfer, the data written into SDRL is output from the SO1 pin in LSB-first order. In the
replacement process, data is input LSB-first from the SI1 pin, and the data is shifted in the MSB →
LSB direction.
The operation in 16-bit transfer is the same as for 8-bit transfer, except that the input data is taken
from SDRU.
SDRL read/write operations must only be performed after data transmission/reception has been
completed. Data contents are not guaranteed if read/write operations are executed while data
transmission/reception is in progress.
The value of SDRL is undefined upon reset.
5. Clock Stop Register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to SCI1 is described here. For details of the other bits, see the
sections on the relevant modules.
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Section 10 Serial Communication Interface
Bit 7: SCI1 module standby mode control (S1CKSTP)
Bit 7 controls setting and clearing of module standby mode for SCI1.
Bit 7
S1CKSTP
Description
0
SCI1 is set to module standby mode*
1
SCI1 module standby mode is cleared
Note:
*
10.2.3
(initial value)
Setting to module standby mode resets SCR1, SCSR1, SDRU, and SDRL.
Operation
Either 8-bit or 16-bit transfer data can be selected as the transfer format. An internal clock or
external clock can be selected as the clock source. When an external clock is used, overrun errors
can be detected.
1. Clock
The serial clock can be selected from 8 internal clocks or an external clock. When an internal
clock is selected, the SCK1 pin functions as the clock output pin. When continuous clock output
mode is set (SNC1, SNC0 = 10 in SCR1), the clock selected by bits CKS2 to CKS0 (φ/1024 to
φW/4) is output continuously from the SCK1 pin. When an external clock is selected, the SCK1 pin
functions as the clock input pin.
2. Data Transfer Format
The SCI1 transfer format is shown in figure 10.2. LSB-first transfer is used (i.e. transmission and
reception are performed starting with the least significant bit of the transfer data). Transfer data is
output from one falling edge of the serial clock until the next falling edge. Receive data is latched
at the rising edge of the serial clock.
SCK1
SO1/SI1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Figure 10.2 Transfer Format
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Bit 6
Bit 7
Section 10 Serial Communication Interface
3. Data Transfer Operations
Transmitting: The procedure for transmitting data is as follows.
(1) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 pin functions. If
necessary, also designate the SO1 pin as an NMOS open-drain output with bit POF1 in PMR2.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) Write the transfer data to SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL
(4) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1
pin.
(5) After transmission is completed, IRRS1 is set to 1 in IRR1.
When an internal clock is used, the serial clock is output from the SCK1 pin simultaneously with
transmit data output. When transmission ends, the serial clock is not output until the start flag is
next set to 1. During this interval, the SO1 pin continuously outputs the last bit of the previous
data.
When an external clock is used, data is transmitted in synchronization with the clock input from
the SCK1 pin. If the serial clock continues to be input after the end of transmission, this is regarded
as an overrun state, and the ORER flag is set to 1 in SCSR1 (consequently, transmission is not
performed).
While transmission is halted, the output value of the SO1 pin can be changed by means of the SOL
bit in SCSR1.
Receiving: The procedure for receiving data is as follows.
(1) Set both SI1 and SCK1 to 1 in PMR2 to designate the SI1 and SCK1 pin functions.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) When STF is set to 1 in SCSR1, SCI1 starts operating and receive data is taken in from the SI1
pin.
(4) After reception is completed, IRRS1 is set to 1 in IRR1.
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Section 10 Serial Communication Interface
(5) Read the transfer data from SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL
(6) If the serial clock continues to be input after the end of reception, this is regarded as an overrun
state, and the ORER flag is set to 1 in SCSR1 (consequently, reception is not performed).
Simultaneous transmitting and receiving: The procedure for simultaneously transmitting and
receiving data is as follows.
(1) Set SO1, SI1, and SCK1 all to 1 in PMR2 to designate the SO1, SI1, and SCK1 pin functions. If
necessary, also designate the SO1 pin as an NMOS open-drain output with bit POF1 in PMR2.
(2) Clear SNC1 in SCR1 to 0, clear or set SNC0 to 0 or 1, and clear MRKON to 0, to select 8-bit
synchronous mode or 16-bit synchronous mode, and select the serial clock with bits CKS3 to
CKS0. When data is written to SCR1 with MRKON in SCR1 cleared to 0, the internal state of
SCI1 is initialized.
(3) Write the transfer data to SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL
(4) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1
pin, or receive data is input from the SI1 pin.
(5) After transmission/reception is completed, IRRS1 is set to 1 in IRR1.
(6) Read the transfer data from SDRL/SDRU.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte from SDRU, lower byte from SDRL
When an internal clock is used, the serial clock is output from the SCK1 pin simultaneously with
transmit data output. When transmission ends, the serial clock is not output until the start flag is
next set to 1. During this interval, the SO1 pin continuously outputs the last bit of the previous
data.
When an external clock is used, data is transmitted and received in synchronization with the clock
input from the SCK1 pin. If the serial clock continues to be input after the end of
transmission/reception, this is regarded as an overrun state, and the ORER flag is set to 1 in
SCSR1 (consequently, transmission/reception is not performed).
While transmission is halted, the output value of the SO1 pin can be changed by means of the SOL
bit in SCSR1.
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Section 10 Serial Communication Interface
10.2.4
Operation in SSB Mode
SSB communication uses two lines, SCL (Serial Clock) and SDA (Serial Data), and enables a
number of ICs to be controlled when connected as shown in figure 10.3.
In SSB mode, a tail mark is attached and transmitted following an 8-bit or 16-bit data transfer.
Either HOLD TAIL or LATCH TAIL can be selected as the tail mark.
SCL
H8/3847R SCK1
Group chip SO1
IC-A
IC-B
SDA
SCL
SDA
SCL
SDA
SCL
SDA
IC-C
Figure 10.3 Example of SSB Connections
1. Clock
The serial clock can be selected from 8 internal clocks or an external clock, but since the H8/3847
Group chip provides the clock output, an external clock should not be selected. The transfer rate
can be selected with bits CKS2 to CKS0 in SCR1; since this is also the tail mark transfer rate, the
setting should provide for a serial clock cycle of at least 2 µs.
2. Data Transfer Format
The SCI1 transfer format is shown in figure 10.4. LSB-first transfer is used (i.e. transmission is
performed starting with the least significant bit of the transfer data). A tail mark is added after an
8-bit or 16-bit transfer.
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Section 10 Serial Communication Interface
SCK1
SO1
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 14
Bit 15
Tail mark
1 frame
Figure 10.4 Transfer Format (When SNC1 = 0, SNC0 = 1, MRKON = 1)
3. Tail Mark
There are two tail marks: HOLD TAIL and LATCH TAIL. The output waveforms of HOLD TAIL
and LATCH TAIL are shown in figure 10.5. Time t in figure 10.5 is determined by the serial clock
cycle set by bits CKS2 to CKS0 in SCR1.
HOLD TAIL
SCK1
t
SO1
t
Bit 14
t
2t
t
t
t
Bit 15
Bit 0
LATCH TAIL
SCK1
t
SO1
Bit 14
t
t
2t
t
t
Bit 15
Figure 10.5 HOLD TAIL and LATCH TAIL Output Waveforms
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Section 10 Serial Communication Interface
4. Transmitting
The procedure for transmitting data is as follows.
(1) Set SOL to 1 in SCSR1.
(2) Set both SO1 and SCK1 to 1 in PMR2 to designate the SO1 and SCK1 pin functions. Set POF1
to 1 in PMR2 to designate the SO1 pin as an NMOS open-drain output.
(3) Clear SNC1 in SCR1 to 0, and clear or set SNC0 to 0 or 1, to select 8-bit mode or 16-bit mode.
Set MRKON to 1 in SCR1 to select SSB mode.
(4) Write the transfer data to SDRL/SDRU. Set the tail mark with LTCH in SCR1.
8-bit transfer mode: SDRL
16-bit transfer mode: Upper byte to SDRU, lower byte to SDRL
(5) When STF is set to 1 in SCSR1, SCI1 starts operating and transmit data is output from the SO1
pin.
(6) After 8-bit or 16-bit data has been transmitted, STF is reset to 0 in SCSR1 and at the same time
IRRS1 is set to 1 in IRR2. Following data transmission, the selected tail mark is output. MTRF
is set to 1 in SCSR1 during tail mark output.
Data can be transmitted continuously by repeating steps (4) to (6). Ensure that SCI1 is in the idle
state before modifying the MRKON bit in SCR1.
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Section 10 Serial Communication Interface
10.2.5
Interrupt Source
SCI1 has one interrupt source: transfer completion.
When SCI1 completes transfer, IRRS1 is set to 1 in IRR1. The SCI1 interrupt source can be
enabled or disabled by the IENS1 bit in IENR1.
For details, see section 3.3, Interrupts.
10.2.6
Application Notes
(1) When SCK1 is designated as an input pin and an external clock is selected as the clock source,
the external clock must not be input before transfer operation is started by setting STF to 1 in
SCSR1.
(2) In subactive or subsleep mode, SCI1 can be used only when the CPU operation clock is φW/2.
(3) Do not read or write to SCSRI during serial transfer. Use one of the following methods to
confirm that serial transfer has ended.
(a) Use SCI1 interrupt exception handling.
Set IENSI to 1 in IENR1, and execute interrupt exception handling.
(b) Perform IRR1 polling.
Confirm that IRRS1 has been set to 1 in IRRI while SCI interrupts are disabled (IENS1 = 0
in IEHR1).
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Section 10 Serial Communication Interface
10.3
SCI3
10.3.1
Overview
In addition to SCI1, this LSI has two serial communication interfaces, SCI3-1 and SCI3-2, with
identical functions. In this manual, the generic term SCI3 is used to refer to both of these SCIs.
Serial communication interface 3 (SCI3) can carry out serial data communication in either
asynchronous or synchronous mode. It is also provided with a multiprocessor communication
function that enables serial data to be transferred among processors.
1. Features
Features of SCI3 are listed below.
• Choice of asynchronous or synchronous mode for serial data communication
Asynchronous mode
Serial data communication is performed asynchronously, with synchronization provided
character by character. In this mode, serial data can be exchanged with standard
asynchronous communication LSIs such as a Universal Asynchronous
Receiver/Transmitter (UART) or Asynchronous Communication Interface Adapter
(ACIA). A multiprocessor communication function is also provided, enabling serial data
communication among processors.
There is a choice of 16 data transfer formats.
Data length
7, 8, 5 bits
Stop bit length
1 or 2 bits
Parity
Even, odd, or none
Multiprocessor bit
“1” or “0”
Receive error detection
Parity, overrun, and framing errors
Break detection
Break detected by reading the RXD3X pin level directly when a framing
error occurs
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Section 10 Serial Communication Interface
Synchronous mode
Serial data communication is synchronized with a clock. In his mode, serial data can be
exchanged with another LSI that has a synchronous communication function.
Data length
8 bits
Receive error detection
Overrun errors
• Full-duplex communication
Separate transmission and reception units are provided, enabling transmission and reception to
be carried out simultaneously. The transmission and reception units are both double-buffered,
allowing continuous transmission and reception.
• On-chip baud rate generator, allowing any desired bit rate to be selected
• Choice of an internal or external clock as the transmit/receive clock source
• Six interrupt sources: transmit end, transmit data empty, receive data full, overrun error,
framing error, and parity error
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Section 10 Serial Communication Interface
2. Block Diagram
Figure 10.6 shows a block diagram of SCI3.
SCK 3x
External
clock
Internal clock (φ/64, φ/16, φw/2, φ)
Baud rate generator
BRC
BRR
SMR
Transmit/receive
control circuit
SCR3
SSR
TXD
TSR
TDR
RSR
RDR
Internal data bus
Clock
SPCR
RXD
Interrupt request
(TEI, TXI, RXI, ERI)
Legend:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR3:
SSR:
BRR:
BRC:
SPCR:
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register 3
Serial status register
Bit rate register
Bit rate counter
Serial port control register
Figure 10.6 SCI3 Block Diagram
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Section 10 Serial Communication Interface
3. Pin Configuration
Table 10.4 shows the SCI3 pin configuration.
Table 10.4 Pin Configuration
Name
Abbr.
I/O
Function
SCI3 clock
SCK3X
I/O
SCI3 clock input/output
SCI3 receive data input
RXD3X
Input
SCI3 receive data input
SCI3 transmit data output
TXD3X
Output
SCI3 transmit data output
4. Register Configuration
Table 10.5 shows the SCI3 register configuration.
Table 10.5 Registers
Name
Abbr.
R/W
Initial Value
Address
Serial mode register
SMR
R/W
H'00
H'FFA8/FF98
Bit rate register
BRR
R/W
H'FF
H'FFA9/FF99
Serial control register 3
SCR3
R/W
H'00
H'FFAA/FF9A
Transmit data register
TDR
R/W
H'FF
H'FFAB/FF9B
Serial data register
SSR
R/W
H'84
H'FFAC/FF9C
Receive data register
RDR
R
H'00
H'FFAD/FF9D
Transmit shift register
TSR
Protected
—
—
Receive shift register
RSR
Protected
—
—
Bit rate counter
BRC
Protected
—
—
Clock stop register 1
CKSTPR1
R/W
H'FF
H'FFFA
Serial port control register
SPCR
R/W
H'C0
H'FF91
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Section 10 Serial Communication Interface
10.3.2
Register Descriptions
1. Receive Shift Register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
RSR is a register used to receive serial data. Serial data input to RSR from the RXD3X pin is set in
the order in which it is received, starting from the LSB (bit 0), and converted to parallel data.
When one byte of data is received, it is transferred to RDR automatically.
RSR cannot be read or written directly by the CPU.
2. Receive Data Register (RDR)
Bit
7
6
5
4
3
2
1
0
RDR7
RDR6
RDR5
RDR4
RDR3
RDR2
RDR1
RDR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
RDR is an 8-bit register that stores received serial data.
When reception of one byte of data is finished, the received data is transferred from RSR to RDR,
and the receive operation is completed. RSR is then able to receive data. RSR and RDR are
double-buffered, allowing consecutive receive operations.
RDR is a read-only register, and cannot be written by the CPU.
RDR is initialized to H'00 upon reset, and in standby, watch or module standby mode.
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Section 10 Serial Communication Interface
3. Transmit Shift Register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
TSR is a register used to transmit serial data. Transmit data is first transferred from TDR to TSR,
and serial data transmission is carried out by sending the data to the TXD3X pin in order, starting
from the LSB (bit 0). When one byte of data is transmitted, the next byte of transmit data is
transferred to TDR, and transmission started, automatically. Data transfer from TDR to TSR is
not performed if no data has been written to TDR (if bit TDRE is set to 1 in the serial status
register (SSR)).
TSR cannot be read or written directly by the CPU.
4. Transmit Data Register (TDR)
Bit
7
6
5
4
3
2
1
0
TDR7
TDR6
TDR5
TDR4
TDR3
TDR2
TDR1
TDR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores transmit data. When TSR is found to be empty, the transmit
data written in TDR is transferred to TSR, and serial data transmission is started. Continuous
transmission is possible by writing the next transmit data to TDR during TSR serial data
transmission.
TDR can be read or written by the CPU at any time.
TDR is initialized to H'FF upon reset, and in standby, watch or module standby mode.
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Section 10 Serial Communication Interface
5. Serial Mode Register (SMR)
Bit
7
6
5
4
3
2
1
0
COM
CHR
PE
PM
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SMR is an 8-bit register used to set the serial data transfer format and to select the clock source for
the baud rate generator.
SMR can be read or written by the CPU at any time.
SMR is initialized to H'00 upon reset, and in standby, watch or module standby mode.
Bit 7: Communication mode (COM)
Bit 7 selects whether SCI3 operates in asynchronous mode or synchronous mode.
Bit 7
COM
Description
0
Asynchronous mode
1
Synchronous mode
(initial value)
Bit 6: Character length (CHR)
Bit 6 selects either 7 or 8 bits as the data length to be used in asynchronous mode. In synchronous
mode the data length is always 8 bits, irrespective of the bit 6 setting.
Bit 6
CHR
0
1
Description
8-bit data/5-bit data*
1
2
7-bit data* /5-bit data*
2
(initial value)
Notes: 1. When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted.
2. When 5-bit data is selected, set both PE and MP to 1. The three most significant bits
(bits 7, 6, and 5) of TDR are not transmitted.
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Section 10 Serial Communication Interface
Bit 5: Parity enable (PE)
Bit 5 selects whether a parity bit is to be added during transmission and checked during reception
in asynchronous mode. In synchronous mode parity bit addition and checking is not performed,
irrespective of the bit 5 setting.
Bit 5
PE
0
1
Description
Parity bit addition and checking disabled*
1, 2
Parity bit addition and checking enabled* *
2
(initial value)
Notes: 1. When PE is set to 1, even or odd parity, as designated by bit PM, is added to transmit
data before it is sent, and the received parity bit is checked against the parity
designated by bit PM.
2. For the case where 5-bit data is selected, see table 10.11.
Bit 4: Parity mode (PM)
Bit 4 selects whether even or odd parity is to be used for parity addition and checking. The PM bit
setting is only valid in asynchronous mode when bit PE is set to 1, enabling parity bit addition and
checking. The PM bit setting is invalid in synchronous mode, and in asynchronous mode if parity
bit addition and checking is disabled.
Bit 4
PM
0
1
Description
Even parity*
2
Odd parity*
1
(initial value)
Notes: 1. When even parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an even number; in reception,
a check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an even number.
2. When odd parity is selected, a parity bit is added in transmission so that the total
number of 1 bits in the transmit data plus the parity bit is an odd number; in reception, a
check is carried out to confirm that the number of 1 bits in the receive data plus the
parity bit is an odd number.
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Section 10 Serial Communication Interface
Bit 3: Stop bit length (STOP)
Bit 3 selects 1 bit or 2 bits as the stop bit length is asynchronous mode. The STOP bit setting is
only valid in asynchronous mode. When synchronous mode is selected the STOP bit setting is
invalid since stop bits are not added.
Bit 3
STOP
Description
1 stop bit*
2
2 stop bits*
1
0
1
(initial value)
Notes: 1. In transmission, a single 1 bit (stop bit) is added at the end of a transmit character.
2. In transmission, two 1 bits (stop bits) are added at the end of a transmit character.
In reception, only the first of the received stop bits is checked, irrespective of the STOP bit setting.
If the second stop bit is 1 it is treated as a stop bit, but if 0, it is treated as the start bit of the next
transmit character.
Bit 2: Multiprocessor mode (MP)
Bit 2 enables or disables the multiprocessor communication function. When the multiprocessor
communication function is disabled, the parity settings in the PE and PM bits are invalid. The MP
bit setting is only valid in asynchronous mode. When synchronous mode is selected the MP bit
should be set to 0. For details on the multiprocessor communication function, see section 10.3.3,4,
Multiprocessor Communication Function.
Bit 2
MP
Description
0
Multiprocessor communication function disabled*
1
Multiprocessor communication function enabled*
Note:
*
(initial value)
For the case where 5-bit data is selected, see table 10.11.
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Section 10 Serial Communication Interface
Bits 1 and 0: Clock select 1, 0 (CKS1, CKS0)
Bits 1 and 0 choose φ/64, φ/16, φ/2, or φ as the clock source for the baud rate generator.
For the relation between the clock source, bit rate register setting, and baud rate, see 8, Bit rate
register (BRR).
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
φ clock
(initial value)
*1
0
1
φW /2 clock /φW clock
1
0
φ/16 clock
1
1
φ/64 clock
*2
Notes: 1. φW /2 clock is selected in active (medium- and high-speed) or sleep (medium- and highspeed) mode.
2. φW clock is selected in subactive or subsleep mode. SCI3 can be used only when the
φW /2 is selected as the CPU clock in subactive or subsleep mode.
6. Serial Control Register 3 (SCR3)
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR3 is an 8-bit register for selecting transmit or receive operation, the asynchronous mode clock
output, interrupt request enabling or disabling, and the transmit/receive clock source.
SCR3 can be read or written by the CPU at any time.
SCR3 is initialized to H'00 upon reset, and in standby, watch or module standby mode.
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Section 10 Serial Communication Interface
Bit 7: Transmit interrupt enable (TIE)
Bit 7 selects enabling or disabling of the transmit data empty interrupt request (TXI) when
transmit data is transferred from the transmit data register (TDR) to the transmit shift register
(TSR), and bit TDRE in the serial status register (SSR) is set to 1.
TXI can be released by clearing bit TDRE or bit TIE to 0.
Bit 7
TIE
Description
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
(initial value)
Bit 6: Receive interrupt enable (RIE)
Bit 6 selects enabling or disabling of the receive data full interrupt request (RXI) and the receive
error interrupt request (ERI) when receive data is transferred from the receive shift register (RSR)
to the receive data register (RDR), and bit RDRF in the serial status register (SSR) is set to 1.
There are three kinds of receive error: overrun, framing, and parity.
RXI can be released by clearing bit RDRF or the FER, PER, or OER error flag to 0, or by clearing
bit RIE to 0.
Bit 6
RIE
Description
0
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt
request (ERI) enabled
(initial value)
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Section 10 Serial Communication Interface
Bit 5: Transmit enable (TE)
Bit 5 selects enabling or disabling of the start of transmit operation.
Bit 5
TE
0
1
Description
Transmit operation disabled* (TXD pin is I/O port)
2
Transmit operation enabled* (TXD pin is transmit data pin)
1
(initial value)
Notes: 1. Bit TDRE in SSR is fixed at 1.
2. When transmit data is written to TDR in this state, bit TDR in SSR is cleared to 0 and
serial data transmission is started. Be sure to carry out serial mode register (SMR)
settings, and setting of bit SPC31 or SPC32 in SPCR, to decide the transmission format
before setting bit TE to 1.
Bit 4: Receive enable (RE)
Bit 4 selects enabling or disabling of the start of receive operation.
Bit 4
RE
0
1
Description
Receive operation disabled* (RXD pin is I/O port)
2
Receive operation enabled* (RXD pin is receive data pin)
1
(initial value)
Notes: 1. Note that the RDRF, FER, PER, and OER flags in SSR are not affected when bit RE is
cleared to 0, and retain their previous state.
2. In this state, serial data reception is started when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode. Be sure to carry out serial
mode register (SMR) settings to decide the reception format before setting bit RE to 1.
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Section 10 Serial Communication Interface
Bit 3: Multiprocessor interrupt enable (MPIE)
Bit 3 selects enabling or disabling of the multiprocessor interrupt request. The MPIE bit setting is
only valid when asynchronous mode is selected and reception is carried out with bit MP in SMR
set to 1. The MPIE bit setting is invalid when bit COM is set to 1 or bit MP is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupt request disabled (normal receive operation)
Clearing condition:
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled*
Note:
*
(initial value)
Receive data transfer from RSR to RDR, receive error detection, and setting of the
RDRF, FER, and OER status flags in SSR is not performed. RXI, ERI, and setting of
the RDRF, FER, and OER flags in SSR, are disabled until data with the multiprocessor
bit set to 1 is received. When a receive character with the multiprocessor bit set to 1 is
received, bit MPBR in SSR is set to 1, bit MPIE is automatically cleared to 0, and RXI
and ERI requests (when bits TIE and RIE in serial control register 3 (SCR3) are set to
1) and setting of the RDRF, FER, and OER flags are enabled.
Bit 2: Transmit end interrupt enable (TEIE)
Bit 2 selects enabling or disabling of the transmit end interrupt request (TEI) if there is no valid
transmit data in TDR when MSB data is to be sent.
Bit 2
TEIE
Description
0
Transmit end interrupt request (TEI) disabled
1
Note:
(initial value)
Transmit end interrupt request (TEI) enabled*
*
TEI can be released by clearing bit TDRE to 0 and clearing bit TEND to 0 in SSR, or by
clearing bit TEIE to 0.
Bits 1 and 0: Clock enable 1 and 0 (CKE1, CKE0)
Bits 1 and 0 select the clock source and enabling or disabling of clock output from the SCK3X pin.
The combination of CKE1 and CKE0 determines whether the SCK3X pin functions as an I/O port,
a clock output pin, or a clock input pin.
The CKE0 bit setting is only valid in case of internal clock operation (CKE1 = 0) in asynchronous
mode. In synchronous mode, or when external clock operation is used (CKE1 = 1), bit CKE0
should be cleared to 0.
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Section 10 Serial Communication Interface
After setting bits CKE1 and CKE0, set the operating mode in the serial mode register (SMR).
For details on clock source selection, see table 10.12 in 10.3.3,1, Overview.
Bit 1
Bit 0
Description
CKE1
CKE0
Communication Mode
Clock Source
SCK3X Pin Function
0
0
Asynchronous
Internal clock
I/O port*
Synchronous
Internal clock
Asynchronous
Internal clock
Serial clock output*
2
Clock output*
Synchronous
Reserved
Asynchronous
External clock
Clock input*
Synchronous
External clock
Serial clock input
Asynchronous
Reserved
Synchronous
Reserved
0
1
1
0
1
1
1
1
3
Notes: 1. Initial value
2. A clock with the same frequency as the bit rate is output.
3. Input a clock with a frequency 16 times the bit rate.
7. Serial Status Register (SSR)
Bit
Initial value
Read/Write
Note:
*
7
6
5
4
3
2
1
0
TDRE
RDRF
OER
FER
PER
TEND
MPBR
MPBT
1
R/(W) *
0
0
0
0
1
0
0
R/(W)*
R/(W) *
R/(W)*
R/(W) *
R
R
R/W
Only a write of 0 for flag clearing is possible.
SSR is an 8-bit register containing status flags that indicate the operational status of SCI3, and
multiprocessor bits.
SSR can be read or written by the CPU at any time, but only a write of 1 is possible to bits TDRE,
RDRF, OER, PER, and FER. In order to clear these bits by writing 0, 1 must first be read.
Bits TEND and MPBR are read-only bits, and cannot be modified.
SSR is initialized to H'84 upon reset, and in standby, module standby, or watch mode.
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Section 10 Serial Communication Interface
Bit 7: Transmit data register empty (TDRE)
Bit 7 indicates that transmit data has been transferred from TDR to TSR.
Bit 7
TDRE
Description
0
Transmit data written in TDR has not been transferred to TSR
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmit data has not been written to TDR, or transmit data written in
TDR has been transferred to TSR
Setting conditions:
When bit TE in SCR3 is cleared to 0
When data is transferred from TDR to TSR
(initial value)
Bit 6: Receive data register full (RDRF)
Bit 6 indicates that received data is stored in RDR.
Bit 6
RDRF
Description
0
There is no receive data in RDR
Clearing conditions:
After reading RDRF = 1, cleared by writing 0 to RDRF
When RDR data is read by an instruction
(initial value)
1
There is receive data in RDR
Setting condition:
When reception ends normally and receive data is transferred from RSR to RDR
Note: If an error is detected in the receive data, or if the RE bit in SCR3 has been cleared to 0,
RDR and bit RDRF are not affected and retain their previous state.
Note that if data reception is completed while bit RDRF is still set to 1, an overrun error
(OER) will result and the receive data will be lost.
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Section 10 Serial Communication Interface
Bit 5: Overrun error (OER)
Bit 5 indicates that an overrun error has occurred during reception.
Bit 5
OER
0
1
Description
Reception in progress or completed*
Clearing condition:
After reading OER = 1, cleared by writing 0 to OER
2
An overrun error has occurred during reception*
Setting condition:
When reception is completed with RDRF set to 1
1
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit OER is not affected and retains its previous
state.
2. RDR retains the receive data it held before the overrun error occurred, and data
received after the error is lost. Reception cannot be continued with bit OER set to 1,
and in synchronous mode, transmission cannot be continued either.
Bit 4: Framing error (FER)
Bit 4 indicates that a framing error has occurred during reception in asynchronous mode.
Bit 4
FER
Description
0
Reception in progress or completed*
Clearing condition:
After reading FER = 1, cleared by writing 0 to FER
1
A framing error has occurred during reception
Setting condition:
When the stop bit at the end of the receive data is checked for a value
2
of 1 at the end of reception, and the stop bit is 0*
1
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit FER is not affected and retains its previous
state.
2. Note that, in 2-stop-bit mode, only the first stop bit is checked for a value of 1, and the
second stop bit is not checked. When a framing error occurs the receive data is
transferred to RDR but bit RDRF is not set. Reception cannot be continued with bit
FER set to 1. In synchronous mode, neither transmission nor reception is possible
when bit FER is set to 1.
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Section 10 Serial Communication Interface
Bit 3: Parity error (PER)
Bit 3 indicates that a parity error has occurred during reception with parity added in asynchronous
mode.
Bit 3
PER
0
1
Description
Reception in progress or completed*
Clearing condition:
After reading PER = 1, cleared by writing 0 to PER
2
A parity error has occurred during reception*
Setting condition:
When the number of 1 bits in the receive data plus parity bit does not
match the parity designated by bit PM in the serial mode register
(SMR)
1
(initial value)
Notes: 1. When bit RE in SCR3 is cleared to 0, bit PER is not affected and retains its previous
state.
2. Receive data in which it a parity error has occurred is still transferred to RDR, but bit
RDRF is not set. Reception cannot be continued with bit PER set to 1. In synchronous
mode, neither transmission nor reception is possible when bit FER is set to 1.
Bit 2: Transmit end (TEND)
Bit 2 indicates that bit TDRE is set to 1 when the last bit of a transmit character is sent.
Bit 2 is a read-only bit and cannot be modified.
Bit 2
TEND
Description
0
Transmission in progress
Clearing conditions:
After reading TDRE = 1, cleared by writing 0 to TDRE
When data is written to TDR by an instruction
1
Transmission ended
Setting conditions:
When bit TE in SCR3 is cleared to 0
When bit TDRE is set to 1 when the last bit of a transmit character is
sent
(initial value)
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Section 10 Serial Communication Interface
Bit 1: Multiprocessor bit receive (MPBR)
Bit 1 stores the multiprocessor bit in a receive character during multiprocessor format reception in
asynchronous mode.
Bit 1 is a read-only bit and cannot be modified.
Bit 1
MPBR
Description
0
Data in which the multiprocessor bit is 0 has been received*
1
Data in which the multiprocessor bit is 1 has been received
Note:
*
(initial value)
When bit RE is cleared to 0 in SCR3 with the multiprocessor format, bit MPBR is not
affected and retains its previous state.
Bit 0: Multiprocessor bit transfer (MPBT)
Bit 0 stores the multiprocessor bit added to transmit data when transmitting in asynchronous
mode. The bit MPBT setting is invalid when synchronous mode is selected, when the
multiprocessor communication function is disabled, and when not transmitting.
Bit 0
MPBT
Description
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
(initial value)
8. Bit Rate Register (BRR)
Bit
7
6
5
4
3
2
1
0
BRR7
BRR6
BRR5
BRR4
BRR3
BRR2
BRR1
BRR0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that designates the transmit/receive bit rate in accordance with the baud
rate generator operating clock selected by bits CKS1 and CKS0 of the serial mode register (SMR).
BRR can be read or written by the CPU at any time.
BRR is initialized to H'FF upon reset, and in standby, module standby, or watch mode.
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Section 10 Serial Communication Interface
Table 10.6 shows examples of BRR settings in asynchronous mode. The values shown are for
active (high-speed) mode.
Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
OSC
32.8 kHz
Bit Rate
(bit/s)
n
N
38.4 kHz
Error
(%) n
2 MHz
2.4576 MHz
4 MHz
N
Error
(%) n
N
Error
(%) n
N
Error
(%) n
N
Error
(%)
21
–0.83 —
—
—
110
Cannot be used,
—
—
—
—
—
—
2
150
as error exceeds
0
3
0
2
12
0.16
3
3
0
2
25
0.16
200
3%
0
2
0
0
155
0.16
3
2
0
—
—
—
250
—
—
—
0
124
0
0
153
–0.26 0
249
0
300
0
1
0
0
103
0.16
3
1
0
2
12
0.16
600
0
0
0
0
51
0.16
3
0
0
0
103
0.16
1200
—
—
—
0
25
0.16
2
1
0
0
51
0.16
2400
—
—
—
0
12
0.16
2
0
0
0
25
0.16
4800
—
—
—
—
—
—
0
7
0
0
12
0.16
9600
—
—
—
—
—
—
0
3
0
—
—
—
19200
—
—
—
—
—
—
0
1
0
—
—
—
31250
—
—
—
0
0
0
—
—
—
0
1
0
38400
—
—
—
—
—
—
0
0
0
—
—
—
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Section 10 Serial Communication Interface
Table 10.6 Examples of BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
OSC
10 MHz
16 MHz
Bit Rate
(bit/s)
n
N
Error
(%) n
N
Error
(%)
110
2
88
–0.25 2
141
0.03
150
2
64
0.16
103
0.16
200
2
48
–0.35 2
77
0.16
250
2
38
0.16
2
62
–0.79
300
—
—
—
2
51
0.16
600
—
—
—
2
25
0.16
1200
0
129
0.16
0
207
0.16
2400
0
64
0.16
0
103
0.16
4800
—
—
—
0
51
0.16
9600
—
—
—
0
25
0.16
19200
—
—
—
0
12
0.16
31250
0
4
0
0
7
0
38400
—
—
—
—
—
—
2
Notes: 1. The setting should be made so that the error is not more than 1%.
2. The value set in BRR is given by the following equation:
OSC
N=
—1
2n
(64 × 2 × B)
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of φOSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.7.)
Table 10.7
Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
0
2
3
φ
1
2
φW /2* /φW *
φ/16
φ/64
0
0
1
1
0
1
0
1
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Section 10 Serial Communication Interface
Notes: 1. φW /2 clock is selected in active (medium- and high-speed) or sleep
(medium- and high-speed) mode.
2. φW clock is selected in subactive or subsleep mode. SCI3 can be used only
when the φW/2 is selected as the CPU clock in subactive or subsleep mode.
3. The error in table 10.6 is the value obtained from the following equation, rounded to two
decimal places.
Error (%) =
B (rate obtained from n, N, OSC) — R (bit rate in left-hand column in table 10.6.)
R (bit rate in left-hand column in table 10.6.)
× 100
Table 10.8 shows the maximum bit rate for each frequency. The values shown are for active
(high-speed) mode.
Table 10.8 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
Setting
OSC (MHz)
Maximum Bit Rate (bit/s)
n
N
0.0384*
600
0
0
2
31250
0
0
2.4576
38400
0
0
4
62500
0
0
10
156250
0
0
250000
0
0
16
Note:
*
When SMR is set up to CKS1 = “0”, CKS0 = “1”.
Table 10.9 shows examples of BRR settings in synchronous mode. The values shown are for
active (high-speed) mode.
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Section 10 Serial Communication Interface
Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (1)
OSC
38.4 kHz
2 MHz
4 MHz
Bit Rate (bit/s) n
N
Error
n
N
Error
n
N
Error
200
0
23
0
—
—
—
—
—
—
250
—
—
—
—
—
—
2
124
0
300
2
0
0
—
—
—
—
—
—
500
—
—
—
—
—
—
1k
0
249
0
—
—
—
2.5k
0
99
0
0
199
0
5k
0
49
0
0
99
0
10k
0
24
0
0
49
0
25k
0
9
0
0
19
0
50k
0
4
0
0
9
0
100k
—
—
—
0
4
0
250k
0
0
0
0
1
0
0
0
0
500k
1M
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Section 10 Serial Communication Interface
Table 10.9 Examples of BRR Settings for Various Bit Rates (Synchronous Mode) (2)
OSC
10 MHz
16 MHz
Bit Rate (bit/s) n
N
Error
n
N
Error
200
—
—
—
—
—
—
250
—
—
—
3
124
0
300
—
—
—
—
—
—
500
—
—
—
2
249
0
1k
—
—
—
2
124
0
2.5k
—
—
—
2
49
0
5k
0
249
0
2
24
0
10k
0
124
0
0
199
0
25k
0
49
0
0
79
0
50k
0
24
0
0
39
0
100k
—
—
—
0
19
0
250k
0
4
0
0
7
0
500k
—
—
—
0
3
0
1M
—
—
—
0
1
0
Blank: Cannot be set.
— : A setting can be made, but an error will result.
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Section 10 Serial Communication Interface
Notes: The value set in BRR is given by the following equation:
OSC
N=
—1
2n
(8 × 2 × B)
where
B: Bit rate (bit/s)
N: Baud rate generator BRR setting (0 ≤ N ≤ 255)
OSC: Value of φOSC (Hz)
n: Baud rate generator input clock number (n = 0, 2, or 3)
(The relation between n and the clock is shown in table 10.10.)
Table 10.10 Relation between n and Clock
SMR Setting
n
Clock
CKS1
CKS0
0
0
2
3
φ
1
2
φW /2* /φW *
φ/16
φ/64
0
0
1
1
0
1
0
1
Notes: 1. φW /2 clock is selected in active (medium- and high-speed) or sleep (mediumand high-speed) mode.
2. φW clock is selected in subactive or subsleep mode. SCI3 can be used only
when the φW/2 is selected as the CPU operation clock in subactive or subsleep
mode.
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Section 10 Serial Communication Interface
9. Clock Stop Register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bits relating to SCI3 are described here. For details of the other bits, see the
sections on the relevant modules.
Bit 6: SCI3-1 module standby mode control (S31CKSTP)
Bit 6 controls setting and clearing of module standby mode for SCI31.
S31CKSTP
Description
0
SCI3-1 is set to module standby mode*
1
SCI3-1 module standby mode is cleared
Note:
*
(initial value)
Setting to module standby mode resets all the registers in SCI31.
Bit 5: SCI3-2 module standby mode control (S32CKSTP)
Bit 5 controls setting and clearing of module standby mode for SCI32.
S32CKSTP
Description
0
SCI3-2 is set to module standby mode*
1
SCI3-2 module standby mode is cleared
Note:
*
(initial value)
Setting to module standby mode resets all the registers in SCI32.
10. Serial Port Control Register (SPCR)
Bit
7
6
5
4
3
2
1
0
—
—
SPC32
SPC31
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
SCINV3 SCINV2 SCINV1 SCINV0
SPCR is an 8-bit readable/writable register that performs RXD31, RXD32, TXD31, and TXD32 pin
input/output data inversion switching. SPCR is initialized to H'C0 by a reset.
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Section 10 Serial Communication Interface
Bits 7 to 6: Reserved bits
Bits 7 to 6 are reserved; they are always read as 1 and cannot be modified.
Bit 5: P42/TXD32 pin function switch (SPC32)
This bit selects whether pin P42/TXD32 is used as P42 or as TXD32.
Bit 5
SPC32
Description
0
Functions as P42 I/O pin
1
Note:
(initial value)
Functions as TXD32 output pin*
*
Set the TE bit in SCR3 after setting this bit to 1.
Bit 4: P35/TXD31 pin function switch (SPC31)
This bit selects whether pin P35/TXD31 is used as P35 or as TXD31.
Bit 4
SPC31
Description
0
Functions as P35 I/O pin
1
Functions as TXD31 output pin*
Note:
*
(initial value)
Set the TE bit in SCR3 after setting this bit to 1.
Bit 3: TXD32 pin output data inversion switch
Bit 3 specifies whether or not TXD32 pin output data is to be inverted.
Bit 3
SCINV3
Description
0
TXD32 output data is not inverted
1
TXD32 output data is inverted
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(initial value)
Section 10 Serial Communication Interface
Bit 2: RXD32 pin input data inversion switch
Bit 2 specifies whether or not RXD32 pin input data is to be inverted.
Bit 2
SCINV2
Description
0
RXD32 input data is not inverted
1
RXD32 input data is inverted
(initial value)
Bit 1: TXD31 pin output data inversion switch
Bit 1 specifies whether or not TXD31 pin output data is to be inverted.
Bit 1
SCINV1
Description
0
TXD31 output data is not inverted
1
TXD31 output data is inverted
(initial value)
Bit 0: RXD31 pin input data inversion switch
Bit 0 specifies whether or not RXD31 pin input data is to be inverted.
Bit 0
SCINV0
Description
0
RXD31 input data is not inverted
1
RXD31 input data is inverted
(initial value)
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Section 10 Serial Communication Interface
10.3.3
Operation
1. Overview
SCI3 can perform serial communication in two modes: asynchronous mode in which
synchronization is provided character by character, and synchronous mode in which
synchronization is provided by clock pulses. The serial mode register (SMR) is used to select
asynchronous or synchronous mode and the data transfer format, as shown in table 10.11.
The clock source for SCI3 is determined by bit COM in SMR and bits CKE1 and CKE0 in SCR3,
as shown in table 10.12.
a. Asynchronous mode
• Choice of 5-, 7-, or 8-bit data length
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits. (The
combination of these parameters determines the data transfer format and the character length.)
• Framing error (FER), parity error (PER), overrun error (OER), and break detection during
reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a clock
with the same frequency as the bit rate can be output.
When external clock is selected: A clock with a frequency 16 times the bit rate must be input.
(The on-chip baud rate generator is not used.)
b. Synchronous mode
• Data transfer format: Fixed 8-bit data length
• Overrun error (OER) detection during reception
• Choice of internal or external clock as the clock source
When internal clock is selected: SCI3 operates on the baud rate generator clock, and a serial
clock is output.
When external clock is selected: The on-chip baud rate generator is not used, and SCI3
operates on the input serial clock.
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Section 10 Serial Communication Interface
Table 10.11 SMR Settings and Corresponding Data Transfer Formats
SMR
Data Transfer Format
bit 7
COM
bit 6 bit 2
CHR MP
bit 5
PE
bit 3
STOP Mode
Data
Length
Multiprocessor Parity
Bit
Bit
0
0
0
0
0
Asynchronous 8-bit data No
0
0
0
0
1
mode
0
0
0
1
0
0
0
0
1
1
0
1
0
0
0
0
1
0
0
1
0
1
0
1
0
0
1
0
1
1
0
0
1
0
0
0
0
1
0
1
0
0
1
1
0
0
0
1
1
1
0
1
1
0
0
0
1
1
0
1
0
1
1
1
0
0
1
1
1
1
1
*
0
*
*
No
Stop Bit
Length
1 bit
2 bits
Yes
1 bit
2 bits
7-bit data
No
1 bit
2 bits
Yes
1 bit
2 bits
8-bit data Yes
No
1 bit
2 bits
5-bit data No
1 bit
2 bits
7-bit data Yes
1 bit
2 bits
5-bit data No
Yes
1 bit
2 bits
Synchronous
mode
8-bit data No
No
No
*: Don’t care
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Section 10 Serial Communication Interface
Table 10.12 SMR and SCR3 Settings and Clock Source Selection
SMR
SCR3
bit 7
bit 1
COM
CKE1 CKE0 Mode
0
0
0
0
0
1
0
1
0
bit 0
Transmit/Receive Clock
Clock Source SCK3X Pin Function
Asynchronous Internal
mode
External
I/O port (SCK3X pin not used)
Outputs clock with same frequency as bit rate
Outputs clock with frequency 16 times bit rate
1
0
0
1
1
0
Synchronous
mode
Internal
Outputs serial clock
External
Inputs serial clock
0
1
1
Reserved (Do not specify these combinations)
1
0
1
1
1
1
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Section 10 Serial Communication Interface
c. Interrupts and continuous transmission/reception
SCI3 can carry out continuous reception using RXI and continuous transmission using TXI.
These interrupts are shown in table 10.13.
Table 10.13 Transmit/Receive Interrupts
Interrupt Flags
Interrupt Request Conditions
Notes
RXI
RDRF
RIE
When serial reception is performed
normally and receive data is transferred
from RSR to RDR, bit RDRF is set to 1,
and if bit RIE is set to 1 at this time, RXI is
enabled and an interrupt is requested.
(See figure 10.7 (a).)
The RXI interrupt routine reads the
receive data transferred to RDR
and clears bit RDRF to 0.
Continuous reception can be
performed by repeating the above
operations until reception of the
next RSR data is completed.
TXI
TDRE
TIE
When TSR is found to be empty (on
completion of the previous transmission)
and the transmit data placed in TDR is
transferred to TSR, bit TDRE is set to 1.
If bit TIE is set to 1 at this time, TXI is
enabled and an interrupt is requested.
(See figure 10.7 (b).)
The TXI interrupt routine writes the
next transmit data to TDR and
clears bit TDRE to 0. Continuous
transmission can be performed by
repeating the above operations
until the data transferred to TSR
has been transmitted.
TEI
TEND
TEIE
When the last bit of the character in TSR is
transmitted, if bit TDRE is set to 1, bit
TEND is set to 1. If bit TEIE is set to 1 at
this time, TEI is enabled and an interrupt is
requested. (See figure 10.7 (c).)
TEI indicates that the next transmit
data has not been written to TDR
when the last bit of the transmit
character in TSR is sent.
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Section 10 Serial Communication Interface
RDR
RDR
RSR (reception in progress)
RSR↑ (reception completed, transfer)
RXD3x pin
RXD3x pin
RDRF ← 1
(RXI request when RIE = 1)
RDRF = 0
Figure 10.7 (a) RDRF Setting and RXI Interrupt
TDR (next transmit data)
TDR
TSR (transmission in progress)
TSR↓ (transmission completed, transfer)
TXD3x pin
TXD3x pin
TDRE ← 1
(TXI request when TIE = 1)
TDRE = 0
Figure 10.7 (b) TDRE Setting and TXI Interrupt
TDR
TDR
TSR (transmission in progress)
TSR (reception completed)
TXD3x pin
TXD3x pin
TEND = 0
TEND ← 1
(TEI request when TEIE = 1)
Figure 10.7 (c) TEND Setting and TEI Interrupt
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Section 10 Serial Communication Interface
2. Operation in Asynchronous Mode
In asynchronous mode, serial communication is performed with synchronization provided
character by character. A start bit indicating the start of communication and one or two stop bits
indicating the end of communication are added to each character before it is sent.
SCI3 has separate transmission and reception units, allowing full-duplex communication. As the
transmission and reception units are both double-buffered, data can be written during transmission
and read during reception, making possible continuous transmission and reception.
a. Data transfer format
The general data transfer format in asynchronous communication is shown in figure 10.8.
(LSB)
Serial
data
(MSB)
1
Start
bit
Transmit/receive data
Parity
bit
1 bit
5, 7, or 8 bits
1 bit
or none
Stop
bit(s)
Mark
state
1 or 2 bits
One transfer data unit (character or frame)
Figure 10.8 Data Format in Asynchronous Communication
In asynchronous communication, the communication line is normally in the mark state (high
level). SCI3 monitors the communication line and when it detects a space (low level), identifies
this as a start bit and begins serial data communication.
One transfer data character consists of a start bit (low level), followed by transmit/receive data
(LSB-first format, starting from the least significant bit), a parity bit (high or low level), and
finally one or two stop bits (high level).
In asynchronous mode, synchronization is performed by the falling edge of the start bit during
reception. The data is sampled on the 8th pulse of a clock with a frequency 16 times the bit
period, so that the transfer data is latched at the center of each bit.
Table 10.14 shows the 16 data transfer formats that can be set in asynchronous mode. The format
is selected by the settings in the serial mode register (SMR).
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Section 10 Serial Communication Interface
Table 10.14 Data Transfer Formats (Asynchronous Mode)
SMR
CHR PE
Serial Data Transfer Format and Frame Length
MP
STOP
1
2
3
4
5
6
7
8
9
10 11 12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
0
1
0
S
8-bit data
MPB STOP
S
8-bit data
MPB STOP STOP
S
8-bit data
P
STOP
S
8-bit data
P
STOP STOP
S
5-bit data
STOP
S
5-bit data
STOP STOP
S
7-bit data
STOP
S
7-bit data
STOP STOP
S
7-bit data
MPB STOP
S
7-bit data
MPB STOP STOP
S
7-bit data
P
STOP
P
STOP STOP
0
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
0
0
1
0
1
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
S
7-bit data
1
1
1
0
S
5-bit data
P
STOP
1
1
1
1
S
5-bit data
P
STOP STOP
Legend:
Start bit
S:
STOP: Stop bit
Parity bit
P:
MPB: Multiprocessor bit
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Section 10 Serial Communication Interface
b. Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK3X pin can be selected as the SCI3 transmit/receive clock. The selection is made by means of
bit COM in SMR and bits SCE1 and CKE0 in SCR3. See table 10.12 for details on clock source
selection.
When an external clock is input at the SCK3X pin, the clock frequency should be 16 times the bit
rate.
When SCI3 operates on an internal clock, the clock can be output at the SCK3X pin. In this case
the frequency of the output clock is the same as the bit rate, and the phase is such that the clock
rises at the center of each bit of transmit/receive data, as shown in figure 10.9.
Clock
Serial
data
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 character (1 frame)
Figure 10.9 Phase Relationship between Output Clock and Transfer Data
(Asynchronous Mode) (8-bit data, parity, 2 stop bits)
c. Data transfer operations
• SCI3 initialization
Before data is transferred on SCI3, bits TE and RE in SCR3 must first be cleared to 0, and then
SCI3 must be initialized as follows.
Note: If the operation mode or data transfer format is changed, bits TE and RE must first be
cleared to 0.
When bit TE is cleared to 0, bit TDRE is set to 1.
Note that the RDRF, PER, FER, and OER flags and the contents of RDR are retained
when RE is cleared to 0.
When an external clock is used in asynchronous mode, the clock should not be stopped
during operation, including initialization. When an external clock is used in synchronous
mode, the clock should not be supplied during operation, including initialization.
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Section 10 Serial Communication Interface
Figure 10.10 shows an example of a flowchart for initializing SCI3.
Start
Clear bits TE and
RE to 0 in SCR3
1
Set bits CKE1
and CKE0
2
Set data transfer
format in SMR
3
Set value in BRR
1. Set clock selection in SCR3. Be sure to
clear the other bits to 0. If clock output
is selected in asynchronous mode, the
clock is output immediately after setting
bits CKE1 and CKE0. If clock output is
selected for reception in synchronous
mode, the clock is output immediately
after bits CKE1, CKE0, and RE are
set to 1.
2. Set the data transfer format in the serial
mode register (SMR).
Wait
Has 1-bit period
elapsed?
No
Yes
Set bits SPC31 and
SPC32 to 1 in SPCR
4
Set bits TIE, RIE,
MPIE, and TEIE in
SCR3, and set bits
RE and TE to 1
in PMR7
3. Write the value corresponding to the
transfer rate in BRR. This operation is
not necessary when an external clock
is selected.
4. Wait for at least one bit period, then set
bits TIE, RIE, MPIE, and TEIE in SCR3,
and set bits RE and TE to 1 in PMR7.
Setting bits TE and RE enables the TXD3x
and RXD3x pins to be used. In asynchronous
mode the mark state is established when
transmitting, and the idle state waiting for
a start bit when receiving.
End
Figure 10.10 Example of SCI3 Initialization Flowchart
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Section 10 Serial Communication Interface
• Transmitting
Figure 10.11 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
Read bit TDRE
in SSR
No
TDRE = 1?
Yes
Write transmit
data to TDR
2
Continue data
transmission?
Yes
2. When continuing data transmission,
be sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0
automatically.
3. If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
No
Read bit TEND
in SSR
TEND = 1?
1. Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then write transmit data to the transmit
data register (TDR). When data is
written to TDR, bit TDRE is cleared to 0
automatically.
(After the TE bit is set to 1, one frame of
1s is output, then transmission is possible.)
No
Yes
3
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to 0
in SCR3
End
Figure 10.11 Example of Data Transmission Flowchart (Asynchronous Mode)
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Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD3x pin using the relevant data transfer format in table
10.14. When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3
transfers data from TDR to TSR, and when the stop bit has been sent, starts transmission of the
next frame. If bit TDRE is set to 1, bit TEND in SSR bit is set to 1the mark state, in which 1s are
transmitted, is established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this
time, a TEI request is made.
Figure 10.12 shows an example of the operation when transmitting in asynchronous mode.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
Parity Stop Start
bit
bit bit
D7
0/1
1
0
1 frame
Transmit
data
D0
D1
D7
Parity Stop
bit
bit
0/1
1
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.12 Example of Operation when Transmitting in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
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Mark
state
1
Section 10 Serial Communication Interface
• Receiving
Figure 10.13 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
1
Read bits OER,
PER, FER in SSR
OER + PER
+ FER = 1?
1. Read bits OER, PER, and FER in the
serial status register (SSR) to determine
if there is an error. If a receive error has
occurred, execute receive error
processing.
Yes
2. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data
in RDR. When the RDR data is read,
bit RDRF is cleared to 0 automatically.
No
2
Read bit RDRF
in SSR
RDRF = 1?
3.
No
When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the stop bit of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
Yes
Read receive
data in RDR
4
3
Continue data
reception?
Receive error
processing
Yes
No
(A)
Clear bit RE to
0 in SCR3
End
Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode)
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Section 10 Serial Communication Interface
4
Start receive
error processing
Overrun error
processing
OER = 1?
Yes
No
FER = 1?
Break?
Yes
No
No
PER = 1?
Yes
4. If a receive error has
occurred, read bits OER,
PER, and FER in SSR to
identify the error, and after
carrying out the necessary
error processing, ensure
that bits OER, PER, and
FER are all cleared to 0.
Yes
Reception cannot be
resumed if any of these
bits is set to 1. In the case
of a framing error, a break
can be detected by reading
the value of the RXD3x pin.
Framing error
processing
No
Clear bits OER, PER,
FER to 0 in SSR
Parity error
processing
(A)
End of receive
error processing
Figure 10.13 Example of Data Reception Flowchart (Asynchronous Mode) (cont)
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Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 monitors the communication line, and when it detects a 0 start bit, performs internal
synchronization and begins reception. Reception is carried out in accordance with the relevant
data transfer format in table 10.14. The received data is first placed in RSR in LSB-to-MSB order,
and then the parity bit and stop bit(s) are received. SCI3 then carries out the following checks.
• Parity check
SCI3 checks that the number of 1 bits in the receive data conforms to the parity (odd or even)
set in bit PM in the serial mode register (SMR).
• Stop bit check
SCI3 checks that the stop bit is 1. If two stop bits are used, only the first is checked.
• Status check
SCI3 checks that bit RDRF is set to 0, indicating that the receive data can be transferred from
RSR to RDR.
If no receive error is found in the above checks, bit RDRF is set to 1, and the receive data is stored
in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the error checks identify a
receive error, bit OER, PER, or FER is set to 1 depending on the kind of error. Bit RDRF retains
its state prior to receiving the data. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
Table 10.15 shows the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Table 10.15 Receive Error Detection Conditions and Receive Data Processing
Receive Error Abbr.
Detection Conditions
Receive Data Processing
Overrun error
OER
When the next date receive
operation is completed while bit
RDRF is still set to 1 in SSR
Receive data is not transferred
from RSR to RDR
Framing error
FER
When the stop bit is 0
Receive data is transferred
from RSR to RDR
Parity error
PER
When the parity (odd or even) set Receive data is transferred
in SMR is different from that of the from RSR to RDR
received data
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Section 10 Serial Communication Interface
Figure 10.14 shows an example of the operation when receiving in asynchronous mode.
Start
bit
Serial
data
1
0
Receive
data
D0
D1
D7
Parity Stop Start
bit
bit bit
0/1
1
0
1 frame
Receive
data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
Mark state
(idle state)
1
1 frame
RDRF
FER
RXI request
LSI
operation
User
processing
RDRF
cleared to 0
RDR data read
0 start bit
detected
ERI request in
response to
framing error
Framing error
processing
Figure 10.14 Example of Operation when Receiving in Asynchronous Mode
(8-bit data, parity, 1 stop bit)
3. Operation in Synchronous Mode
In synchronous mode, SCI3 transmits and receives data in synchronization with clock pulses. This
mode is suitable for high-speed serial communication.
SCI3 has separate transmission and reception units, allowing full-duplex communication with a
shared clock.
As the transmission and reception units are both double-buffered, data can be written during
transmission and read during reception, making possible continuous transmission and reception.
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Section 10 Serial Communication Interface
a. Data transfer format
The general data transfer format in synchronous communication is shown in figure 10.15.
*
*
Serial
clock
LSB
Serial
data
Bit 0
Don't
care
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don't
care
8 bits
One transfer data unit (character or frame)
Note: * High level except in continuous transmission/reception
Figure 10.15 Data Format in Synchronous Communication
In synchronous communication, data on the communication line is output from one falling edge of
the serial clock until the next falling edge. Data confirmation is guaranteed at the rising edge of
the serial clock.
One transfer data character begins with the LSB and ends with the MSB. After output of the
MSB, the communication line retains the MSB state.
When receiving in synchronous mode, SCI3 latches receive data at the rising edge of the serial
clock.
The data transfer format uses a fixed 8-bit data length.
Parity and multiprocessor bits cannot be added.
b. Clock
Either an internal clock generated by the baud rate generator or an external clock input at the
SCK3x pin can be selected as the SCI3 serial clock. The selection is made by means of bit COM in
SMR and bits CKE1 and CKE0 in SCR3. See table 10.12 for details on clock source selection.
When SCI3 operates on an internal clock, the serial clock is output at the SCK3x pin. Eight pulses
of the serial clock are output in transmission or reception of one character, and when SCI3 is not
transmitting or receiving, the clock is fixed at the high level.
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Section 10 Serial Communication Interface
c. Data transfer operations
• SCI3 initialization
Data transfer on SCI3 first of all requires that SCI3 be initialized as described in “SCI
initialization” under 10.3.3, 2. c. Data transfer operations, and shown in figure 10.10.
• Transmitting
Figure 10.16 shows an example of a flowchart for data transmission. This procedure should be
followed for data transmission after initializing SCI3.
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Section 10 Serial Communication Interface
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
Read bit TDRE
in SSR
No
TDRE = 1?
Yes
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that
a write can be performed before writing
data to TDR. When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Write transmit
data to TDR
2
Continue data
transmission?
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically, the
clock is output, and data transmission is
started. When clock output is selected,
the clock is output and data transmission
started when data is written to TDR.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
Clear bit TE to 0
in SCR3
End
Figure 10.16 Example of Data Transmission Flowchart (Synchronous Mode)
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Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
When clock output mode is selected, SCI3 outputs 8 serial clock pulses. When an external clock
is selected, data is output in synchronization with the input clock.
Serial data is transmitted from the TXD3x pin in order from the LSB (bit 0) to the MSB (bit 7).
When the MSB (bit 7) is sent, checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and starts transmission of the next frame. If bit TDRE is set to 1, SCI3 sets bit
TEND to 1 in SSR, and after sending the MSB (bit 7), retains the MSB state. If bit TEIE in SCR3
is set to 1 at this time, a TEI request is made.
After transmission ends, the SCK pin is fixed at the high level.
Note: Transmission is not possible if an error flag (OER, FER, or PER) that indicates the data
reception status is set to 1. Check that these error flags are all cleared to 0 before a
transmit operation.
Figure 10.17 shows an example of the operation when transmitting in synchronous mode.
Serial
clock
Serial
data
Bit 0
Bit 1
Bit 7
1 frame
Bit 0
Bit 1
Bit 6
Bit 7
1 frame
TDRE
TEND
TXI request
LSI
operation
TDRE cleared
to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.17 Example of Operation when Transmitting in Synchronous Mode
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Section 10 Serial Communication Interface
• Receiving
Figure 10.18 shows an example of a flowchart for data reception. This procedure should be
followed for data reception after initializing SCI3.
Start
1
Read bit OER
in SSR
1. Read bit OER in the serial status register
(SSR) to determine if there is an error.
If an overrun error has occurred, execute
overrun error processing.
Yes
OER = 1?
2. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR. When the RDR data is read, bit
RDRF is cleared to 0 automatically.
No
2
Read bit RDRF
in SSR
RDRF = 1?
3. When continuing data reception, finish
reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current
frame. When the data in RDR is read,
bit RDRF is cleared to 0 automatically.
No
4. If an overrun error has occurred, read bit
OER in SSR, and after carrying out the
necessary error processing, clear bit OER
to 0. Reception cannot be resumed if bit
OER is set to 1.
Yes
Read receive
data in RDR
4
3
Continue data
reception?
Overrun error
processing
Yes
No
Clear bit RE to
0 in SCR3
End
4
Start overrun
error processing
Overrun error
processing
Clear bit OER to
0 in SSR
End of overrun
error processing
Figure 10.18 Example of Data Reception Flowchart (Synchronous Mode)
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Section 10 Serial Communication Interface
SCI3 operates as follows when receiving data.
SCI3 performs internal synchronization and begins reception in synchronization with the serial
clock input or output.
The received data is placed in RSR in LSB-to-MSB order.
After the data has been received, SCI3 checks that bit RDRF is set to 0, indicating that the receive
data can be transferred from RSR to RDR.
If this check shows that there is no overrun error, bit RDRF is set to 1, and the receive data is
stored in RDR. If bit RIE is set to 1 in SCR3, an RXI interrupt is requested. If the check
identifies an overrun error, bit OER is set to 1.
Bit RDRF remains set to 1. If bit RIE is set to 1 in SCR3, an ERI interrupt is requested.
See table 10.15 for the conditions for detecting a receive error, and receive data processing.
Note: No further receive operations are possible while a receive error flag is set. Bits OER,
FER, PER, and RDRF must therefore be cleared to 0 before resuming reception.
Figure 10.19 shows an example of the operation when receiving in synchronous mode.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
1 frame
Bit 1
Bit 6
Bit 7
1 frame
RDRF
OER
LSI
operation
RXI request
User
processing
RDRE cleared
to 0
RDR data read
RXI request
ERI request in
response to
overrun error
RDR data has
not been read
(RDRF = 1)
Overrun error
processing
Figure 10.19 Example of Operation when Receiving in Synchronous Mode
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Section 10 Serial Communication Interface
• Simultaneous transmit/receive
Figure 10.20 shows an example of a flowchart for a simultaneous transmit/receive operation. This
procedure should be followed for simultaneous transmission/reception after initializing SCI3.
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
1. Read the serial status register (SSR) and
check that bit TDRE is set to 1, then write
transmit data to the transmit data register
(TDR). When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Read bit TDRE
in SSR
No
TDRE = 1?
2. Read SSR and check that bit RDRF is set
to 1. If it is, read the receive data in RDR.
When the RDR data is read, bit RDRF is
cleared to 0 automatically.
Yes
Write transmit
data to TDR
3. When continuing data transmission/reception,
finish reading of bit RDRF and RDR before
receiving the MSB (bit 7) of the current frame.
Before receiving the MSB (bit 7) of the current
frame, also read TDRE = 1 to confirm that a
write can be performed, then write data to TDR.
When data is written to TDR, bit TDRE is cleared
to 0 automatically, and when the data in RDR is
read, bit RDRF is cleared to 0 automatically.
Read bit OER
in SSR
Yes
OER = 1?
No
2
4. If an overrun error has occurred, read bit OER
in SSR, and after carrying out the necessary
error processing, clear bit OER to 0. Transmission and reception cannot be resumed if bit
OER is set to 1.
See figure 10-18 for details on overrun error
processing.
Read bit RDRF
in SSR
No
RDRF = 1?
Yes
Read receive data
in RDR
4
3
Continue data
transmission/reception?
No
Clear bits TE and
RE to 0 in SCR3
End
Overrun error
processing
Yes
Notes: 1. When switching from transmission to simultaneous
transmission/reception, check that SCI3 has finished transmitting and
that bits TDRE and TEND are set to 1, clear bit TE to 0, and then set
bits TE and RE to 1.
2. When switching from reception to simultaneous transmission/reception,
check that SCI3 has finished receiving, clear bit RE to 0, then check
that bit RDRF and the error flags (OER, FER, and PER) are cleared to
0, and finally set bits TE and RE to 1.
Figure 10.20 Example of Simultaneous Data Transmission/Reception Flowchart
(Synchronous Mode)
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Section 10 Serial Communication Interface
4. Multiprocessor Communication Function
The multiprocessor communication function enables data to be exchanged among a number of
processors on a shared communication line. Serial data communication is performed in
asynchronous mode using the multiprocessor format (in which a multiprocessor bit is added to the
transfer data).
In multiprocessor communication, each receiver is assigned its own ID code. The serial
communication cycle consists of two cycles, an ID transmission cycle in which the receiver is
specified, and a data transmission cycle in which the transfer data is sent to the specified receiver.
These two cycles are differentiated by means of the multiprocessor bit, 1 indicating an ID
transmission cycle, and 0, a data transmission cycle.
The sender first sends transfer data with a 1 multiprocessor bit added to the ID code of the receiver
it wants to communicate with, and then sends transfer data with a 0 multiprocessor bit added to the
transmit data. When a receiver receives transfer data with the multiprocessor bit set to 1, it
compares the ID code with its own ID code, and if they are the same, receives the transfer data
sent next. If the ID codes do not match, it skips the transfer data until data with the multiprocessor
bit set to 1 is sent again.
In this way, a number of processors can exchange data among themselves.
Figure 10.21 shows an example of communication between processors using the multiprocessor
format.
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Section 10 Serial Communication Interface
Sender
Communication line
Serial
data
Receiver A
Receiver B
Receiver C
Receiver D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
H'01
(MPB = 1)
ID transmission cycle
(specifying the receiver)
H'AA
(MPB = 0)
Data transmission cycle
(sending data to the receiver
specified buy the ID)
MPB: Multiprocessor bit
Figure 10.21 Example of Inter-Processor Communication Using Multiprocessor Format
(Sending data H'AA to receiver A)
There is a choice of four data transfer formats. If a multiprocessor format is specified, the parity
bit specification is invalid. See table 10.14 for details.
For details on the clock used in multiprocessor communication, see section 10.3.3, 2. Operation in
Asynchronous Mode.
• Multiprocessor transmitting
Figure 10.22 shows an example of a flowchart for multiprocessor data transmission. This
procedure should be followed for multiprocessor data transmission after initializing SCI3.
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Section 10 Serial Communication Interface
Start
Sets bits SPC31 and
SPC32 to 1 in SPCR
1
Read bit TDRE
in SSR
TDRE = 1?
No
2. When continuing data transmission, be
sure to read TDRE = 1 to confirm that a
write can be performed before writing data
to TDR. When data is written to TDR, bit
TDRE is cleared to 0 automatically.
Yes
Set bit MPDT
in SSR
3. If a break is to be output when data
transmission ends, set the port PCR to 1
and clear the port PDR to 0, then clear bit
TE in SCR3 to 0.
Write transmit
data to TDR
2
Continue data
transmission?
1. Read the serial status register (SSR)
and check that bit TDRE is set to 1,
then set bit MPBT in SSR to 0 or 1 and
write transmit data to the transmit data
register (TDR). When data is written to
TDR, bit TDRE is cleared to 0 automatically.
Yes
No
Read bit TEND
in SSR
TEND = 1?
No
Yes
3
Break output?
No
Yes
Set PDR = 0,
PCR = 1
Clear bit TE to
0 in SCR3
End
Figure 10.22 Example of Multiprocessor Data Transmission Flowchart
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Section 10 Serial Communication Interface
SCI3 operates as follows when transmitting data.
SCI3 monitors bit TDRE in SSR, and when it is cleared to 0, recognizes that data has been written
to TDR and transfers data from TDR to TSR. It then sets bit TDRE to 1 and starts transmitting. If
bit TIE in SCR3 is set to 1 at this time, a TXI request is made.
Serial data is transmitted from the TXD pin using the relevant data transfer format in table 10.14.
When the stop bit is sent, SCI3 checks bit TDRE. If bit TDRE is cleared to 0, SCI3 transfers data
from TDR to TSR, and when the stop bit has been sent, starts transmission of the next frame. If
bit TDRE is set to 1 bit TEND in SSR bit is set to 1, the mark state, in which 1s are transmitted, is
established after the stop bit has been sent. If bit TEIE in SCR3 is set to 1 at this time, a TEI
request is made.
Figure 10.23 shows an example of the operation when transmitting using the multiprocessor
format.
Start
bit
Serial
data
1
0
Transmit
data
D0
D1
D7
MPB
0/1
Stop Start
bit bit
1
0
Transmit
data
D0
D1
MPB
D7
0/1
Stop
bit
Mark
state
1
1
1 frame
1 frame
TDRE
TEND
LSI
TXI request
operation
TDRE
cleared to 0
User
processing
Data written
to TDR
TXI request
TEI request
Figure 10.23 Example of Operation when Transmitting Using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)
• Multiprocessor receiving
Figure 10.24 shows an example of a flowchart for multiprocessor data reception. This procedure
should be followed for multiprocessor data reception after initializing SCI3.
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Section 10 Serial Communication Interface
Start
1
2
1. Set bit MPIE to 1 in SCR3.
Set bit MPIE to 1
in SCR3
2. Read bits OER and FER in the serial
status register (SSR) to determine if
there is an error. If a receive error has
occurred, execute receive error processing.
Read bits OER
and FER in SSR
OER + FER = 1?
3. Read SSR and check that bit RDRF is
set to 1. If it is, read the receive data in
RDR and compare it with this receiver's
own ID. If the ID is not this receiver's,
set bit MPIE to 1 again. When the RDR
data is read, bit RDRF is cleared to 0
automatically.
Yes
No
3
Read bit RDRF
in SSR
RDRF = 1?
4. Read SSR and check that bit RDRF is
set to 1, then read the data in RDR.
No
5. If a receive error has occurred, read bits
OER and FER in SSR to identify the error,
and after carrying out the necessary error
processing, ensure that bits OER and FER
are both cleared to 0. Reception cannot be
resumed if either of these bits is set to 1.
In the case of a framing error, a break can
be detected by reading the value of the
RXD3x pin.
Yes
Read receive
data in RDR
Own ID?
No
Yes
Read bits OER
and FER in SSR
OER + FER = 1?
Yes
No
4
Read bit RDRF
in SSR
RDRF = 1?
No
Yes
Read receive
data in RDR4
Continue data
reception?
5
Receive error
processing
Yes
No
(A)
Clear bit RE to
0 in SCR3
End
Figure 10.24 Example of Multiprocessor Data Reception Flowchart
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Section 10 Serial Communication Interface
Start receive
error processing
Overrun error
processing
OER = 1?
Yes
Yes
No
FER = 1?
No
Break?
Yes
No
Framing error
processing
Clear bits OER and
FER to 0 in SSR
End of receive
error processing
(A)
Figure 10.24 Example of Multiprocessor Data Reception Flowchart (cont)
Figure 10.25 shows an example of the operation when receiving using the multiprocessor format.
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Section 10 Serial Communication Interface
Start
bit
Serial
data
1
0
Receive
data (ID1)
D0
D1
MPB
D7
1
Stop Start
bit bit
1
0
Receive data
(Data1)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
ID1
LSI
operation
RXI request
MPIE cleared
to 0
RDRF cleared
to 0
User
processing
No RXI request
RDR retains
previous state
RDR data read
When data is not
this receiver's ID,
bit MPIE is set to
1 again
(a) When data does not match this receiver's ID
Start
bit
Serial
data
1
0
Receive
data (ID2)
D0
D1
MPB
D7
1
Stop Start
bit bit
1
0
Receive data
(Data2)
D0
1 frame
D1
D7
MPB
Stop
bit
Mark state
(idle state)
0
1
1
1 frame
MPIE
RDRF
RDR
value
LSI
operation
ID1
ID2
RXI request
MPIE cleared
to 0
User
processing
RDRF cleared
to 0
RDR data read
Data2
RXI request
When data is
this receiver's
ID, reception
is continued
RDRF cleared
to 0
RDR data read
Bit MPIE set to
1 again
(b) When data matches this receiver's ID
Figure 10.25 Example of Operation when Receiving Using Multiprocessor Format
(8-bit data, multiprocessor bit, 1 stop bit)
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Section 10 Serial Communication Interface
10.3.4
Interrupts
SCI3 can generate six kinds of interrupts: transmit end, transmit data empty, receive data full, and
three receive error interrupts (overrun error, framing error, and parity error). These interrupts have
the same vector address.
The various interrupt requests are shown in table 10.16.
Table 10.16 SCI3 Interrupt Requests
Interrupt Abbr.
Interrupt Request
Vector
Address
RXI
Interrupt request initiated by receive data full flag (RDRF)
H'0022/H'0024
TXI
Interrupt request initiated by transmit data empty flag (TDRE)
TEI
Interrupt request initiated by transmit end flag (TEND)
ERI
Interrupt request initiated by receive error flag
(OER, FER, PER)
Each interrupt request can be enabled or disabled by means of bits TIE and RIE in SCR3.
When bit TDRE is set to 1 in SSR, a TXI interrupt is requested. When bit TEND is set to 1 in
SSR, a TEI interrupt is requested. These two interrupts are generated during transmission.
The initial value of bit TDRE in SSR is 1. Therefore, if the transmit data empty interrupt request
(TXI) is enabled by setting bit TIE to 1 in SCR3 before transmit data is transferred to TDR, a TXI
interrupt will be requested even if the transmit data is not ready.
Also, the initial value of bit TEND in SSR is 1. Therefore, if the transmit end interrupt request
(TEI) is enabled by setting bit TEIE to 1 in SCR3 before transmit data is transferred to TDR, a TEI
interrupt will be requested even if the transmit data has not been sent.
Effective use of these interrupt requests can be made by having processing that transfers transmit
data to TDR carried out in the interrupt service routine.
To prevent the generation of these interrupt requests (TXI and TEI), on the other hand, the enable
bits for these interrupt requests (bits TIE and TEIE) should be set to 1 after transmit data has been
transferred to TDR.
When bit RDRF is set to 1 in SSR, an RXI interrupt is requested, and if any of bits OER, PER, and
FER is set to 1, an ERI interrupt is requested. These two interrupt requests are generated during
reception.
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Section 10 Serial Communication Interface
For further details, see section 3.3, Interrupts.
10.3.5
Application Notes
The following points should be noted when using SCI3.
1. Relation between Writes to TDR and bit TDRE
Bit TDRE in the serial status register (SSR) is a status flag that indicates that data for serial
transmission has not been prepared in TDR. When data is written to TDR, bit TDRE is cleared to
0 automatically. When SCI3 transfers data from TDR to TSR, bit TDRE is set to 1.
Data can be written to TDR irrespective of the state of bit TDRE, but if new data is written to
TDR while bit TDRE is cleared to 0, the data previously stored in TDR will be lost of it has not
yet been transferred to TSR. Accordingly, to ensure that serial transmission is performed
dependably, you should first check that bit TDRE is set to 1, then write the transmit data to TDR
once only (not two or more times).
2. Operation when a Number of Receive Errors Occur Simultaneously
If a number of receive errors are detected simultaneously, the status flags in SSR will be set to the
states shown in table 10.17. If an overrun error is detected, data transfer from RSR to RDR will
not be performed, and the receive data will be lost.
Table 10.17 SSR Status Flag States and Receive Data Transfer
SSR Status Flags
RDRF* OER FER
PER
Receive Data Transfer
RSR → RDR
Receive Error Status
1
1
0
0
×
0
0
1
0
Framing error
0
0
0
1
Parity error
1
1
1
0
×
Overrun error + framing error
1
1
0
1
×
Overrun error + parity error
0
0
1
1
1
1
1
1
Overrun error
Framing error + parity error
×
Overrun error + framing error + parity error
:
×:
Receive data is transferred from RSR to RDR.
Receive data is not transferred from RSR to RDR.
Note:
*
Bit RDRF retains its state prior to data reception. However, note that if RDR is read
after an overrun error has occurred in a frame because reading of the receive data in
the previous frame was delayed, RDRF will be cleared to 0.
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Section 10 Serial Communication Interface
3. Break Detection and Processing
When a framing error is detected, a break can be detected by reading the value of the RXD3X pin
directly. In a break, the input from the RXD3X pin becomes all 0s, with the result that bit FER is
set and bit PER may also be set.
SCI3 continues the receive operation even after receiving a break. Note, therefore, that even
though bit FER is cleared to 0 it will be set to 1 again.
4. Mark State and Break Detection
When bit TE is cleared to 0, the TXD3X pin functions as an I/O port whose input/output direction
and level are determined by PDR and PCR. This fact can be used to set the TXD3X pin to the
mark state, or to detect a break during transmission.
To keep the communication line in the mark state (1 state) until bit TE is set to 1, set PCR = 1 and
PDR = 1. Since bit TE is cleared to 0 at this time, the TXD3X pin functions as an I/O port and 1 is
output.
To detect a break, clear bit TE to 0 after setting PCR = 1 and PDR = 0.
When bit TE is cleared to 0, the transmission unit is initialized regardless of the current
transmission state, the TXD3X pin functions as an I/O port, and 0 is output from the TXD3X pin.
5. Receive Error Flags and Transmit Operation (Synchronous Mode Only)
When a receive error flag (OER, PER, or FER) is set to 1, transmission cannot be started even if
bit TDRE is cleared to 0. The receive error flags must be cleared to 0 before starting transmission.
Note also that receive error flags cannot be cleared to 0 even if bit RE is cleared to 0.
6. Receive Data Sampling Timing and Receive Margin in Asynchronous Mode
In asynchronous mode, SCI3 operates on a basic clock with a frequency 16 times the transfer rate.
When receiving, SCI3 performs internal synchronization by sampling the falling edge of the start
bit with the basic clock. Receive data is latched internally at the 8th rising edge of the basic clock.
This is illustrated in figure 10.26.
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Section 10 Serial Communication Interface
16 clock pulses
8 clock pulses
0
7
15 0
7
15 0
Internal
basic clock
Receive data
(RXD3x)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 10.26 Receive Data Sampling Timing in Asynchronous Mode
Consequently, the receive margin in asynchronous mode can be expressed as shown in equation
(1).
M ={(0.5 – 1 ) – D – 0.5 – (L – 0.5) F} × 100 [%]
N
2N
where
..... Equation (1)
M: Receive margin (%)
N: Ratio of bit rate to clock (N = 16)
D: Clock duty (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock frequency deviation
Substituting 0 for F (absolute value of clock frequency deviation) and 0.5 for D (clock duty) in
equation (1), a receive margin of 46.875% is given by equation (2).
When D = 0.5 and F = 0,
M = {0.5 — 1/(2 × 16)} × 100 [%]
= 46.875%
..... Equation (2)
However, this is only a computed value, and a margin of 20% to 30% should be allowed when
carrying out system design.
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Section 10 Serial Communication Interface
7. Relation between RDR Reads and Bit RDRF
In a receive operation, SCI3 continually checks the RDRF flag. If bit RDRF is cleared to 0 when
reception of one frame ends, normal data reception is completed. If bit RDRF is set to 1, this
indicates that an overrun error has occurred.
When the contents of RDR are read, bit RDRF is cleared to 0 automatically. Therefore, if bit
RDR is read more than once, the second and subsequent read operations will be performed while
bit RDRF is cleared to 0. Note that, when an RDR read is performed while bit RDRF is cleared to
0, if the read operation coincides with completion of reception of a frame, the next frame of data
may be read. This is illustrated in figure 10.27.
Communication
line
Frame 1
Frame 2
Frame 3
Data 1
Data 2
Data 3
Data 1
Data 2
RDRF
RDR
(A)
RDR read
(B)
RDR read
Data 1 is read at point (A)
Data 2 is read at point (B)
Figure 10.27 Relation between RDR Read Timing and Data
In this case, only a single RDR read operation (not two or more) should be performed after first
checking that bit RDRF is set to 1. If two or more reads are performed, the data read the first time
should be transferred to RAM, etc., and the RAM contents used. Also, ensure that there is
sufficient margin in an RDR read operation before reception of the next frame is completed. To
be precise in terms of timing, the RDR read should be completed before bit 7 is transferred in
synchronous mode, or before the STOP bit is transferred in asynchronous mode.
8. Transmission and Reception Operation at State Transition
Make sure state transition operation is performed after transmission and reception operations are
completed.
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Section 10 Serial Communication Interface
9. Cautions on Switching of SCK3X Pin Function
If the function of the SCK3X pin is switched from clock output to I/O port after using the SCI3 in
clock synchronization mode, the “low” level is output in a moment (1/2 of the system clock φ) at
the SCK3X pin function switching.
This momentary “low” level output can be avoided in either of the following two methods:
a. When disabling SCK3X pin clock output
When stopping signal transmission, clear the bits TE and RE in SCR3, and set the CKE1
bit to “1” and the CKE0 bit to “0” simultaneously with a single command.
In this case, use the COM bit in SMR set at “1”. This means it cannot be used as an I/O
port. Also, to avoid intermediate potential from being applied to the SCK3X pin, pull up the
line connected to the SCK3X pin to VCC potential with a resistance, or supply an output
from other devices.
b. When switching the SCK3X pin function from clock output to I/O port
When stopping signal transmission,
(1) Clear the bits TE and RE in SCR3, and set the CKE1 bit to “1” and the CKE0 bit to “0”
simultaneously with a single command.
(2) Then, clear the COM bit in SMR to “0”.
(3) Finally, clear the bits CKE1 and CKE0 in SCR3 to “0”. Avoid intermediate potential
from being applied to the SCK3X pin.
10. Setting in Subactive and Subsleep Modes
In subactive or subsleep mode, SCI3 can be used only when the φW/2 is selected as the CPU clock.
Set the SA1 bit in SYSCR2 to “1”.
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Section 11 14-Bit PWM
Section 11 14-Bit PWM
11.1
Overview
This LSI is provided with a 14-bit PWM (pulse width modulator) on-chip, which can be used as a
D/A converter by connecting a low-pass filter.
11.1.1
Features
Features of the 14-bit PWM are as follows.
• Choice of two conversion periods
Any of the following four conversion periods can be chosen:
131,072/φ, with a minimum modulation width of 8/φ (PWCR1 = 1, PWCR0 = 1)
65,536/φ, with a minimum modulation width of 4/φ (PWCR1 = 1, PWCR0 = 0)
32,768/φ, with a minimum modulation width of 2/φ (PWCR1 = 0, PWCR0 = 1)
16,384/φ, with a minimum modulation width of 1/φ (PWCR1 = 0, PWCR0 = 0)
• Pulse division method for less ripple
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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Section 11 14-Bit PWM
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the 14-bit PWM.
PWDRU
φ/2
φ/4
φ/8
φ/16
PWM
waveform
generator
Internal data bus
PWDRL
PWCR
PWM
Legend:
PWDRL: PWM data register L
PWDRU: PWM data register U
PWCR: PWM control register
Figure 11.1 Block Diagram of the 14 bit PWM
11.1.3
Pin Configuration
Table 11.1 shows the output pin assigned to the 14-bit PWM.
Table 11.1 Pin Configuration
Name
Abbr.
I/O
Function
PWM output pin
PWM
Output
Pulse-division PWM waveform output
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Section 11 14-Bit PWM
11.1.4
Register Configuration
Table 11.2 shows the register configuration of the 14-bit PWM.
Table 11.2 Register Configuration
Name
Abbr.
R/W
Initial Value
Address
PWM control register
PWCR
W
H'FC
H'FFD0
PWM data register U
PWDRU
W
H'C0
H'FFD1
PWM data register L
PWDRL
W
H'00
H'FFD2
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
11.2
Register Descriptions
11.2.1
PWM Control Register (PWCR)
Bit
7
6
5
4
3
2
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
—
—
—
—
—
—
W
W
1
0
PWCR1 PWCR0
PWCR is an 8-bit write-only register for input clock selection.
Upon reset, PWCR is initialized to H'FC.
Bits 7 to 2: Reserved bits
Bits 7 to 2 are reserved; they are always read as 1, and cannot be modified.
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Section 11 14-Bit PWM
Bits 1 and 0: Clock select 1 and 0 (PWCR1, PWCR0)
Bits 1 and 0 select the clock supplied to the 14-bit PWM. These bits are write-only bits; they are
always read as 1.
Bit 1
PWCR1
Bit 0
PWCR0
0
0
0
1
1
0
1
1
Note:
*
Description
The input clock is φ/2 (tφ* = 2/φ)
(initial value)
The conversion period is 16,384/φ, with a minimum modulation
width of 1/φ
The input clock is φ/4 (tφ* = 4/φ)
The conversion period is 32,768/φ, with a minimum modulation
width of 2/φ
The input clock is φ/8 (tφ* = 8/φ)
The conversion period is 65,536/φ, with a minimum modulation
width of 4/φ
The input clock is φ/16 (tφ* = 16/φ)
The conversion period is 131,072/φ, with a minimum
modulation width of 8/φ
Period of PWM input clock.
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Section 11 14-Bit PWM
11.2.2
PWM Data Registers U and L (PWDRU, PWDRL)
PWDRU
Bit
7
6
Initial value
1
1
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
7
6
5
4
3
2
1
0
5
4
3
2
1
0
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
PWDRL
Bit
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total highlevel width of one PWM waveform cycle.
When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM
waveform generator, updating the PWM waveform generation data. The 14-bit data should
always be written in the following sequence:
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRU and PWDRL are initialized to H'C000.
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Section 11 14-Bit PWM
11.2.3
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
—
—
—
—
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
AECKSTP WDCKSTP PWCKSTP LDCKSTP
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the PWM is described here. For details of the other bits, see the
sections on the relevant modules.
Bit 1: PWM module standby mode control (PWCKSTP)
Bit 1 controls setting and clearing of module standby mode for the PWM.
PWCKSTP
Description
0
PWM is set to module standby mode
1
PWM module standby mode is cleared
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(initial value)
Section 11 14-Bit PWM
11.3
Operation
11.3.1
Operation
When using the 14-bit PWM, set the registers in the following sequence.
1. Set bit PWM in port mode register 3 (PMR3) to 1 so that pin P30/PWM is designated for PWM
output.
2. Set bits PWCR1 and PWCR0 in the PWM control register (PWCR) to select a conversion
period of 131,072/φ (PWCR1 = 1, PWCR0 = 1), 65,536/φ (PWCR1 = 1, PWCR0 = 0),
32,768/φ (PWCR1 = 0, PWCR0 = 1), or 16,384/φ (PWCR1 = 0, PWCR0 = 0).
3. Set the output waveform data in PWM data registers U and L (PWDRU/L). Be sure to write in
the correct sequence, first PWDRL then PWDRU. When data is written to PWDRU, the data
in these registers will be latched in the PWM waveform generator, updating the PWM
waveform generation in synchronization with internal signals.
One conversion period consists of 64 pulses, as shown in figure 11.2. The total of the high-level
pulse widths during this period (TH) corresponds to the data in PWDRU and PWDRL. This
relation can be represented as follows.
TH = (data value in PWDRU and PWDRL + 64) × tφ/2
where tφ is the PWM input clock period: 2/φ (PWCR = H'0), 4/φ (PWCR = H'1), 8/φ (PWCR =
H'2), or 16/φ (PWCR = H'3).
Example: Settings in order to obtain a conversion period of 32,768 µs:
When PWCR1 = 0 and PWCR0 = 0, the conversion period is 16,384/φ, so φ must be 0.5
MHz. In this case, tfn = 512 µs, with 1/φ (resolution) = 2.0 µs.
When PWCR1 = 0 and PWCR0 = 1, the conversion period is 32,768/φ, so φ must be 1
MHz. In this case, tfn = 512 µs, with 2/φ (resolution) = 2.0 µs.
When PWCR1 = 1 and PWCR0 = 0, the conversion period is 65,536/φ , so φ must be 2
MHz. In this case, tfn = 512 µs, with 4/φ (resolution) = 2.0 µs.
Accordingly, for a conversion period of 32,768 µs, the system clock frequency (φ) must
be 0.5 MHz, 1 MHz, or 2 MHz.
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Section 11 14-Bit PWM
1 conversion period
t f1
t H1
t f2
t f63
t H2
t H3
t f64
t H63
t H64
TH = t H1 + t H2 + t H3 + ..... t H64
t f1 = t f2 = t f3 ..... = t f64
Figure 11.2 PWM Output Waveform
11.3.2
PWM Operation Modes
PWM operation modes are shown in table 11.3.
Table 11.3 PWM Operation Modes
Operation
Mode
Reset
Active
Sleep
Watch
Subactive
Subsleep Standby
Module
Standby
PWCR
Reset
Functions
Functions
Held
Held
Held
Held
Held
PWDRU
Reset
Functions
Functions
Held
Held
Held
Held
Held
PWDRL
Reset
Functions
Functions
Held
Held
Held
Held
Held
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Section 12 A/D Converter
Section 12 A/D Converter
12.1
Overview
This LSI includes on-chip a resistance-ladder-based successive-approximation analog-to-digital
converter, and can convert up to 12 channels of analog input.
12.1.1
Features
The A/D converter has the following features.
• 10-bit resolution
• 12 input channels
• Conversion time: approx. 12.4 µs per channel (at 5 MHz operation)
• Built-in sample-and-hold function
• Interrupt requested on completion of A/D conversion
• A/D conversion can be started by external trigger input
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
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Section 12 A/D Converter
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the A/D converter.
ADTRG
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
AN 8
AN 9
AN 10
AN 11
Multiplexer
ADSR
AVCC
+
Comparator
–
AVCC
Reference
voltage
Control logic
AVSS
AVSS
ADRRH
ADRRL
Legend:
AMR: A/D mode register
ADSR: A/D start register
ADRR: A/D result register
IRRAD: A/D conversion end interrupt request flag
Figure 12.1 Block Diagram of the A/D Converter
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Internal data bus
AMR
IRRAD
Section 12 A/D Converter
12.1.3
Pin Configuration
Table 12.1 shows the A/D converter pin configuration.
Table 12.1 Pin Configuration
Name
Abbr.
I/O
Function
Analog power supply
AVCC
Input
Power supply and reference voltage of analog part
Analog ground
AVSS
Input
Ground and reference voltage of analog part
Analog input 0
AN0
Input
Analog input channel 0
Analog input 1
AN1
Input
Analog input channel 1
Analog input 2
AN2
Input
Analog input channel 2
Analog input 3
AN3
Input
Analog input channel 3
Analog input 4
AN4
Input
Analog input channel 4
Analog input 5
AN5
Input
Analog input channel 5
Analog input 6
AN6
Input
Analog input channel 6
Analog input 7
AN7
Input
Analog input channel 7
Analog input 8
AN8
Input
Analog input channel 8
Analog input 9
AN9
Input
Analog input channel 9
Analog input 10
AN10
Input
Analog input channel 10
Analog input 11
AN11
Input
Analog input channel 11
External trigger input
ADTRG
Input
External trigger input for starting A/D conversion
12.1.4
Register Configuration
Table 12.2 shows the A/D converter register configuration.
Table 12.2 Register Configuration
Name
Abbr.
R/W
Initial Value
Address
A/D mode register
AMR
R/W
H'30
H'FFC6
A/D start register
ADSR
R/W
H'7F
H'FFC7
A/D result register H
ADRRH
R
Not fixed
H'FFC4
A/D result register L
ADRRL
R
Not fixed
H'FFC5
Clock stop register 1
CKSTPRT1
R/W
H'FF
H'FFFA
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Section 12 A/D Converter
12.2
Register Descriptions
12.2.1
A/D Result Registers (ADRRH, ADRRL)
Bit
5
4
3
2
1
0
ADR9 ADR8 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 ADR0
—
—
—
—
—
—
Not Not
fixed fixed
—
—
—
—
—
—
—
—
—
—
—
—
7
Initial value
Read/Write
R
6
R
5
4
3
2
1
0
7
6
Not Not Not
Not
Not
Not
Not Not
fixed fixed fixed fixed fixed fixed fixed fixed
R
R
R
R
R
R
R
R
ADRRL
ADRRH
ADRRH and ADRRL together comprise a 16-bit read-only register for holding the results of
analog-to-digital conversion. The upper 8 bits of the data are held in ADRRH, and the lower 2
bits in ADRRL.
ADRRH and ADRRL can be read by the CPU at any time, but the ADRRH and ADRRL values
during A/D conversion are not fixed. After A/D conversion is complete, the conversion result is
stored as 10-bit data, and this data is held until the next conversion operation starts.
ADRRH and ADRRL are not cleared on reset.
12.2.2
A/D Mode Register (AMR)
Bit
7
6
5
4
3
2
1
0
CKS
TRGE
—
—
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
AMR is an 8-bit read/write register for specifying the A/D conversion speed, external trigger
option, and the analog input pins.
Upon reset, AMR is initialized to H'30.
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Section 12 A/D Converter
Bit 7: Clock select (CKS)
Bit 7 sets the A/D conversion speed.
Conversion Time (Active (High-Speed) Mode)*
Bit 7
CKS
Conversion Period
φ = 1 MHz
φ = 5 MHz
0
62/φ (initial value)
62 µs
12.4 µs
1
31/φ
31 µs
—
Note:
*
For information on conversion time settings for which operation is guaranteed, see
section 15, Electrical Characteristics.
Bit 6: External trigger select (TRGE)
Bit 6 enables or disables the start of A/D conversion by external trigger input.
Bit 6
TRGE
Description
0
Disables start of A/D conversion by external trigger
1
Enables start of A/D conversion by rising or falling edge of external trigger at pin
ADTRG*
Note:
*
(initial value)
The external trigger (ADTRG) edge is selected by bit IEG4 of IEGR. See 1. IRQ edge
select register (IEGR) in section 3.3.2 for details.
Bits 5 and 4: Reserved bits
Bits 5 and 4 are reserved; they are always read as 1, and cannot be modified.
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Section 12 A/D Converter
Bits 3 to 0: Channel select (CH3 to CH0)
Bits 3 to 0 select the analog input channel.
The channel selection should be made while bit ADSF is cleared to 0.
Bit 3
CH3
Bit 2
CH2
Bit 1
CH1
Bit 0
CH0
Analog Input Channel
0
0
*
*
No channel selected
0
1
0
0
AN0
0
1
0
1
AN1
0
1
1
0
AN2
0
1
1
1
AN3
1
0
0
0
AN4
1
0
0
1
AN5
1
0
1
0
AN6
1
0
1
1
AN7
1
1
0
0
AN8
1
1
0
1
AN9
1
1
1
0
AN10
1
1
1
1
AN11
(initial value)
*: Don’t care
12.2.3
A/D Start Register (ADSR)
Bit
7
6
5
4
3
2
1
0
ADSF
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
The A/D start register (ADSR) is an 8-bit read/write register for starting and stopping A/D
conversion.
A/D conversion is started by writing 1 to the A/D start flag (ADSF) or by input of the designated
edge of the external trigger signal, which also sets ADSF to 1. When conversion is complete, the
converted data is set in ADRRH and ADRRL, and at the same time ADSF is cleared to 0.
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Section 12 A/D Converter
Bit 7: A/D start flag (ADSF)
Bit 7 controls and indicates the start and end of A/D conversion.
Bit 7
ADSF
Description
0
Read: Indicates the completion of A/D conversion
(initial value)
Write: Stops A/D conversion
1
Read: Indicates A/D conversion in progress
Write: Starts A/D conversion
Bits 6 to 0: Reserved bits
Bits 6 to 0 are reserved; they are always read as 1, and cannot be modified.
12.2.4
Clock Stop Register 1 (CKSTPR1)
Bit
7
6
5
4
3
2
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CKSTPR1 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the A/D converter is described here. For details of the other bits,
see the sections on the relevant modules.
Bit 4: A/D converter module standby mode control (ADCKSTP)
Bit 4 controls setting and clearing of module standby mode for the A/D converter.
ADCKSTP
Description
0
A/D converter is set to module standby mode
1
A/D converter module standby mode is cleared
(initial value)
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Section 12 A/D Converter
12.3
Operation
12.3.1
A/D Conversion Operation
The A/D converter operates by successive approximations, and yields its conversion result as 10bit data.
A/D conversion begins when software sets the A/D start flag (bit ADSF) to 1. Bit ADSF keeps a
value of 1 during A/D conversion, and is cleared to 0 automatically when conversion is complete.
The completion of conversion also sets bit IRRAD in interrupt request register 2 (IRR2) to 1. An
A/D conversion end interrupt is requested if bit IENAD in interrupt enable register 2 (IENR2) is
set to 1.
If the conversion time or input channel needs to be changed in the A/D mode register (AMR)
during A/D conversion, bit ADSF should first be cleared to 0, stopping the conversion operation,
in order to avoid malfunction.
12.3.2
Start of A/D Conversion by External Trigger Input
The A/D converter can be made to start A/D conversion by input of an external trigger signal.
External trigger input is enabled at pin ADTRG when bit IRQ4 in PMR1 is set to 1 and bit TRGE
in AMR is set to 1. Then when the input signal edge designated in bit IEG4 of interrupt edge
select register (IEGR) is detected at pin ADTRG, bit ADSF in ADSR will be set to 1, starting A/D
conversion.
Figure 12.2 shows the timing.
φ
Pin ADTRG
(when bit
IEG4 = 0)
ADSF
A/D conversion
Figure 12.2 External Trigger Input Timing
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Section 12 A/D Converter
12.3.3
A/D Converter Operation Modes
A/D converter operation modes are shown in table 12.3.
Table 12.3 A/D Converter Operation Modes
Operation
Mode
Reset
Active
Subactive
Subsleep
Standby
Module
Standby
AMR
Reset
Functions Functions Held
Held
Held
Held
Held
ADSR
Reset
Functions Functions Held
Held
Held
Held
Held
ADRRH
Held*
Functions Functions Held
Held
Held
Held
Held
ADRRL
Held*
Functions Functions Held
Held
Held
Held
Held
Note:
12.4
*
Sleep
Watch
Undefined in a power-on reset.
Interrupts
When A/D conversion ends (ADSF changes from 1 to 0), bit IRRAD in interrupt request register 2
(IRR2) is set to 1.
A/D conversion end interrupts can be enabled or disabled by means of bit IENAD in interrupt
enable register 2 (IENR2).
For further details see section 3.3, Interrupts.
12.5
Typical Use
An example of how the A/D converter can be used is given below, using channel 1 (pin AN1) as
the analog input channel. Figure 12.3 shows the operation timing.
1. Bits CH3 to CH0 of the A/D mode register (AMR) are set to 0101, making pin AN1 the analog
input channel. A/D interrupts are enabled by setting bit IENAD to 1, and A/D conversion is
started by setting bit ADSF to 1.
2. When A/D conversion is complete, bit IRRAD is set to 1, and the A/D conversion result is
stored is stored in ADRRH and ADRRL. At the same time ADSF is cleared to 0, and the A/D
converter goes to the idle state.
3. Bit IENAD = 1, so an A/D conversion end interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The A/D conversion result is read and processed.
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Section 12 A/D Converter
6. The A/D interrupt handling routine ends.
If ADSF is set to 1 again afterward, A/D conversion starts and steps 2 to 6 take place.
Figures 12.4 and 12.5 show flow charts of procedures for using the A/D converter.
Interrupt
(IRRAD)
Set *
IENAD
ADSF
Channel 1 (AN1)
operation state
A/D conversion starts
Idle
Set *
A/D conversion (1)
Set *
Idle
A/D conversion (2)
Idle
Read conversion result
ADRRH
ADRRL
A/D conversion result (1)
Read conversion result
A/D conversion result (2)
Note: * ( ) indicates instruction execution by software.
Figure 12.3 Typical A/D Converter Operation Timing
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Section 12 A/D Converter
Start
Set A/D conversion speed
and input channel
Disable A/D conversion
end interrupt
Start A/D conversion
Read ADSR
No
ADSF = 0?
Yes
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.4 Flow Chart of Procedure for Using A/D Converter (Polling by Software)
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Section 12 A/D Converter
Start
Set A/D conversion speed
and input channels
Enable A/D conversion
end interrupt
Start A/D conversion
A/D conversion
end interrupt?
No
Yes
Clear bit IRRAD to
0 in IRR2
Read ADRRH/ADRRL data
Yes
Perform A/D
conversion?
No
End
Figure 12.5 Flow Chart of Procedure for Using A/D Converter (Interrupts Used)
12.6
Application Notes
12.6.1
Application Notes
• Data in ADRRH and ADRRL should be read only when the A/D start flag (ADSF) in the A/D
start register (ADSR) is cleared to 0.
• Changing the digital input signal at an adjacent pin during A/D conversion may adversely
affect conversion accuracy.
• When A/D conversion is started after clearing module standby mode, wait for 10 φ clock
cycles before starting.
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Section 12 A/D Converter
• In active mode or sleep mode, analog power supply current (AISTOP1) flows into the ladder
resistance even when the A/D converter is not operating. Therefore, if the A/D converter is not
used, it is recommended that AVCC be connected to the system power supply and the
ADCKSTP (A/D converter module standby mode control) bit be cleared to 0 in clock stop
register 1 (CKSTPR1).
12.6.2
Permissible Signal Source Impedance
This LSI’s analog input is designed such that conversion precision is guaranteed for an input
signal for which the signal source impedance is 10 kΩ or less. This specification is provided to
enable the A/D converter’s sample-and-hold circuit input capacitance to be charged within the
sampling time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it
may not be possible to guarantee A/D conversion precision. However, a large capacitance
provided externally, the input load will essentially comprise only the internal input resistance of
10 kΩ, and the signal source impedance is ignored. However, as a low-pass filter effect is obtained
in this case, it may not be possible to follow an analog signal with a large differential coefficient
(e.g., 5 mV/µs or greater) (see figure 12.6). When converting a high-speed analog signal, a lowimpedance buffer should be inserted.
12.6.3
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND.
Care is also required to ensure that filter circuits do not interfere with digital signals or act as
antennas on the mounting board.
This LSI
Sensor output
impedance
A/D converter
equivalent circuit
10 kΩ
Up to 10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
20 pF
Figure 12.6 Analog Input Circuit Example
Rev. 6.00 Aug 04, 2006 page 429 of 680
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Section 12 A/D Converter
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Section 13 LCD Controller/Driver
Section 13 LCD Controller/Driver
13.1
Overview
This LSI has an on-chip segment type LCD control circuit, LCD driver, and power supply circuit,
enabling it to directly drive an LCD panel.
13.1.1
Features
Features of the LCD controller/driver are given below.
• Display capacity
Duty Cycle
Internal Driver
Segment External Expansion Driver*
Static
40 seg
256 seg
1/2
40 seg
128 seg
1/3
40 seg
64 seg
1/4
40 seg
64 seg
Note:
*
The external expansion function for LCD segments is not implemented in the H8/38347
Group and H8/38447 Group.
• LCD RAM capacity
8 bits × 32 bytes (256 bits)
• Word access to LCD RAM
• All eight segment output pins can be used individually as port pins.
• Common output pins not used because of the duty cycle can be used for common doublebuffering (parallel connection).
• Display possible in operating modes other than standby mode
• Choice of 11 frame frequencies
• Built-in power supply split-resistance, supplying LCD drive power
• Use of module standby mode enables this module to be placed in standby mode independently
when not used.
• A or B waveform selectable by software
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Section 13 LCD Controller/Driver
13.1.2
Block Diagram
Figure 13.1 shows a block diagram of the LCD controller/driver.
LCD drive power supply
M
φ/2 to φ/256
CL2
Common
data latch
φw
Internal data bus
V0
V1
V2
V3
VSS
Common
driver
COM4
SEG40/CL1*
SEG39/CL2*
SEG38/DO*
SEG37/M*
SEG36
LPCR
LCR
LCR2
Display timing generator
COM1
40-bit shift
register
CL1
Segment
driver
LCD RAM
(32 bytes)
SEG1
SEGn, DO
Legend:
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
Note: * The external expansion function for LCD segments is not implemented in the H8/38347 Group and H8/38447 Group.
Figure 13.1 Block Diagram of LCD Controller/Driver
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Section 13 LCD Controller/Driver
13.1.3
Pin Configuration
Table 13.1 shows the LCD controller/driver pin configuration.
Table 13.1 Pin Configuration
Name
Abbr.
I/O
Function
Segment output pins
SEG40 to SEG1
Output
LCD segment drive pins
All pins are multiplexed as port pins
(setting programmable)
Common output pins
COM4 to COM1
Output
LCD common drive pins
Pins can be used in parallel with static
or 1/2 duty
Segment external expansion CL1
signal pin*
Output
Multiplexed as the display data latch
clock, SEG40
CL2
Output
Multiplexed as the display data shift
clock, SEG39
M
Output
Multiplexed as the LCD alternating
signal, SEG37
DO
Output
Multiplexed as the serial display data,
SEG38
V0, V1, V2, V3
—
Used when a bypass capacitor is
connected externally, and when an
external power supply circuit is used
LCD power supply pins
Note:
13.1.4
* The external expansion function for LCD segments is not implemented in the H8/38347
Group and H8/38447 Group.
Register Configuration
Table 13.2 shows the register configuration of the LCD controller/driver.
Table 13.2 LCD Controller/Driver Registers
Name
Abbr.
R/W
Initial Value
Address
LCD port control register
LPCR
R/W
H'00
H'FFC0
LCD control register
LCR
R/W
H'80
H'FFC1
LCD control register 2
LCR2
R/W
H'60
H'FFC2
LCD RAM
—
R/W
Undefined
H'F740 to H'F753
Clock stop register 2
CKSTPR2
R/W
H'FF
H'FFFB
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Section 13 LCD Controller/Driver
13.2
Register Descriptions
13.2.1
LCD Port Control Register (LPCR)
Bit
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
SGX
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LPCR is an 8-bit read/write register which selects the duty cycle and LCD driver pin functions.
LPCR is initialized to H'00 upon reset.
Bits 7 to 5: Duty cycle select 1 and 0 (DTS1, DTS0), common function select (CMX)
The combination of DTS1 and DTS0 selects static, 1/2, 1/3, or 1/4 duty. CMX specifies whether
or not the same waveform is to be output from multiple pins to increase the common drive power
when not all common pins are used because of the duty setting.
Bit 7
DTS1
Bit 6
DTS0
Bit 5
CMX
Duty Cycle
0
0
0
Static
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
1/2 duty
1/3 duty
1/4 duty
Rev. 6.00 Aug 04, 2006 page 434 of 680
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Common
Drivers
Notes
COM1
(initial value)
Do not use COM4, COM3, and
COM2.
COM4 to COM1
COM4, COM3, and COM2 output
the same waveform as COM1.
COM2 to COM1
Do not use COM4 and COM3.
COM4 to COM1
COM4 outputs the same waveform
as COM3, and COM2 outputs the
same waveform as COM1.
COM3 to COM1
Do not use COM4.
COM4 to COM1
Do not use COM4.
COM4 to COM1
—
Section 13 LCD Controller/Driver
Bit 4: Expansion Signal Selection (SGX)
Bit 4 (SGX) selects whether the SEG40/CL1, SEG39/CL2, SEG38/DO, and SEG37/M pins are used as
segment pins (SEG40 to SEG37) or as segment external expansion signal pins (CL1, CL2, DO, and
M). In the H8/38347 Group and H8/38447 Group this bit should be left at its initial value and not
written to. Changing the value of this bit may prevent the SEG/COM signal from operating
normally.
Bit 4
SGX
Description
0
SEG40 to SEG37 pins*
1
CL1, CL2, DO, and M pins
Note:
*
(initial value)
Functions as ports when SGS3 to SGS0 are set at “0000”.
Bits 3 to 0: Segment driver select 3 to 0 (SGS3 to SGS0)
Bits 3 to 0 select the segment drivers to be used. The SGX = 0 setting is selected on the H8/38347
and H8/38447.
Function of Pins SEG40 to SEG1
Bit 4
SGX
SEG40
Bit 3 Bit 2 Bit 1 Bit 0 to
SGS3 SGS2 SGS1 SGS0 SEG33
SEG32
to
SEG25
SEG24
to
SEG17
SEG16
to
SEG9
SEG8
to
SEG1
Notes
0
0
0
0
0
Port
Port
Port
Port
Port
(initial value)
0
0
0
0
1
SEG
Port
Port
Port
Port
0
0
0
1
*
SEG
SEG
Port
Port
Port
0
0
1
0
*
SEG
SEG
SEG
Port
Port
0
0
1
1
*
SEG
SEG
SEG
SEG
Port
0
1
*
*
*
SEG
SEG
SEG
SEG
1
0
0
0
0
SEG
1
*
Port( ) Port
Port
Port
Port
1
0
0
0
1
Do not use
1
0
0
1
*
1
0
1
*
*
1
1
*
*
*
Note:
1. SEG40 to SEG37 are external expansion pins.
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 435 of 680
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Section 13 LCD Controller/Driver
13.2.2
LCD Control Register (LCR)
Bit
7
6
5
4
3
2
1
0
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
—
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCR is an 8-bit read/write register which performs LCD drive power supply on/off control and
display data control, and selects the frame frequency.
LCR is initialized to H'80 upon reset.
Bit 7: Reserved bit
Bit 7 is reserved; it is always read as 1 and cannot be modified.
Bit 6: LCD drive power supply on/off control (PSW)
Bit 6 can be used to turn the LCD drive power supply off when LCD display is not required in a
power-down mode, or when an external power supply is used. When the ACT bit is cleared to 0,
or in standby mode, the LCD drive power supply is turned off regardless of the setting of this bit.
Bit 6
PSW
Description
0
LCD drive power supply off
1
LCD drive power supply on
(initial value)
Bit 5: Display function activate (ACT)
Bit 5 specifies whether or not the LCD controller/driver is used. Clearing this bit to 0 halts
operation of the LCD controller/driver. The LCD drive power supply is also turned off, regardless
of the setting of the PSW bit. However, register contents are retained.
Bit 5
ACT
Description
0
LCD controller/driver operation halted
1
LCD controller/driver operates
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(initial value)
Section 13 LCD Controller/Driver
Bit 4: Display data control (DISP)
Bit 4 specifies whether the LCD RAM contents are displayed or blank data is displayed regardless
of the LCD RAM contents.
Bit 4
DISP
Description
0
Blank data is displayed
1
LCD RAM data is display
(initial value)
Bits 3 to 0: Frame frequency select 3 to 0 (CKS3 to CKS0)
Bits 3 to 0 select the operating clock and the frame frequency. In subactive mode, watch mode,
and subsleep mode, the system clock (φ) is halted, and therefore display operations are not
performed if one of the clocks from φ/2 to φ/256 is selected. If LCD display is required in these
modes, φw, φw/2, or φw/4 must be selected as the operating clock.
Frame Frequency*
2
Bit 3
CKS3
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Operating Clock
0
*
0
0
φw
0
*
0
1
φw/2
0
*
1
*
φw/4
64 Hz*
3
32 Hz*
1
0
0
0
φ/2
—
244 Hz
1
0
0
1
φ/4
977 Hz
122 Hz
1
0
1
0
φ/8
488 Hz
61 Hz
1
0
1
1
φ/16
244 Hz
30.5 Hz
1
1
0
0
φ/32
122 Hz
—
1
1
0
1
φ/64
61 Hz
—
1
1
1
0
φ/128
30.5 Hz
—
1
1
1
1
φ/256
—
—
φ = 2 MHz
φ = 250 kHz*
3
128 Hz* (initial value)
1
3
*: Don’t care
Notes: 1. This is the frame frequency in active (medium-speed, φosc/16) mode when φ = 2 MHz.
2. When 1/3 duty is selected, the frame frequency is 4/3 times the value shown.
3. This is the frame frequency when φw = 32.768 kHz.
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Section 13 LCD Controller/Driver
13.2.3
LCD Control Register 2 (LCR2)
Bit
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
SGX
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
LCR2 is an 8-bit read/write register which controls switching between the A waveform and B
waveform, and selects the duty cycle of the charge/discharge pulses which control disconnection
of the power supply split-resistance from the power supply circuit.
LCR2 is initialized to H'60 upon reset.
Bit 7: A waveform/B waveform switching control (LCDAB)
Bit 7 specifies whether the A waveform or B waveform is used as the LCD drive waveform.
Bit 7
LCDAB
Description
0
Drive using A waveform
1
Drive using B waveform
Bits 6 and 5: Reserved bits
Bits 6 and 5 are reserved; they are always read as 1 and cannot be modified.
Bit 4: Reserved bit
Bit 4 is reserved; it is always read as 0 and must not be written with 1.
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(initial value)
Section 13 LCD Controller/Driver
Bits 3 to 0: Charge/discharge pulse duty cycle select (CDS3 to CDS0)
Bit 3
CDS3
Bit 2
CDS2
Bit 1
CDS1
Bit 0
CDS0
Duty Cycle
Notes
0
0
0
0
1
Fixed high
0
0
0
1
1/8
0
0
1
0
2/8
0
0
1
1
3/8
0
1
0
0
4/8
0
1
0
1
5/8
0
1
1
0
6/8
0
1
1
1
0
1
0
*
*
1/16
1
1
*
*
1/32
(initial value)
Fixed low
*: Don’t care
Bits 3 to 0 select the duty cycle while the power supply split-resistance is connected to the power
supply circuit.
When a 0 duty cycle is selected, the power supply split-resistance is permanently disconnected
from the power supply circuit, so power should be supplied to pins V1, V2, and V3 by an external
circuit.
Figure 13.2 shows the waveform of the charge/discharge pulses. The duty cycle is Tc/Tw.
1 frame
TW
COM1
Tc
Charge/discharge
pulses
Tdc
Tc
: Power supply split-resistance
connected
Tdc : Power supply split-resistance
disconnected
Figure 13.2 Example of A Waveform with 1/2 Duty and 1/2 Bias
Rev. 6.00 Aug 04, 2006 page 439 of 680
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Section 13 LCD Controller/Driver
13.2.4
Clock Stop Register 2 (CKSTPR2)
Bit
7
6
5
4
—
—
—
—
3
2
1
0
AECKSTP WDCKSTP PWCKSTP LDCKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
CKSTPR2 is an 8-bit read/write register that performs module standby mode control for peripheral
modules. Only the bit relating to the LCD controller/driver is described here. For details of the
other bits, see the sections on the relevant modules.
Bit 0: LCD controller/driver module standby mode control (LDCKSTP)
Bit 0 controls setting and clearing of module standby mode for the LCD controller/driver.
Bit 0
LDCKSTP
Description
0
LCD controller/driver is set to module standby mode
1
LCD controller/driver module standby mode is cleared
Rev. 6.00 Aug 04, 2006 page 440 of 680
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(initial value)
Section 13 LCD Controller/Driver
13.3
Operation
13.3.1
Settings up to LCD Display
To perform LCD display, the hardware and software related items described below must first be
determined.
1. Hardware Settings
a. Using 1/2 duty
When 1/2 duty is used, interconnect pins V2 and V3 as shown in figure 13.3.
VCC
V0
V1
V2
V3
VSS
Figure 13.3 Handling of LCD Drive Power Supply when Using 1/2 Duty
b. Large-panel display
As the impedance of the built-in power supply split-resistance is large, it may not be
suitable for driving a large panel. If the display lacks sharpness when using a large panel,
refer to section 13.3.6, Boosting the LCD Drive Power Supply. When static or 1/2 duty is
selected, the common output drive capability can be increased. Set CMX to 1 when
selecting the duty cycle. In this mode, with a static duty cycle pins COM4 to COM1 output
the same waveform, and with 1/2 duty the COM1 waveform is output from pins COM2 and
COM1, and the COM2 waveform is output from pins COM4 and COM3.
c. Luminance adjustment function (V0 pin)
Connecting a resistance between the V0 and V1 pins enables the luminance to be adjusted.
For details, see section 13.3.3, Luminance Adjustment Function (V0 Pin).
Rev. 6.00 Aug 04, 2006 page 441 of 680
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Section 13 LCD Controller/Driver
d. LCD drive power supply setting
With this LSI, there are two ways of providing LCD power: by using the on-chip power
supply circuit, or by using an external circuit.
When the on-chip power supply circuit is used for the LCD drive power supply, the V0 and
V1 pins should be interconnected externally, as shown in figure 13.4 (a).
When an external power supply circuit is used for the LCD drive power supply, connect the
external power supply to the V1 pin, and short the V0 pin to VCC externally, as shown in
figure 13.4 (b).
VCC
VCC
V0
V0
V1
V1
V2
V2
V3
V3
VSS
External power supply
VSS
(a) Using on-chip power supply circuit
(b) Using external power supply circuit
Figure 13.4 Examples of LCD Power Supply Pin Connections
e. Low-power-consumption LCD drive system
Use of a low-power-consumption LCD drive system enables the power consumption
required for LCD drive to be optimized. For details, see section 13.3.4, Low-PowerConsumption LCD Drive System.
f. External expansion of segment
Segment can be expanded by externally connecting the HD66100. For details, see section
13.3.7, Connection to HD66100.
Rev. 6.00 Aug 04, 2006 page 442 of 680
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Section 13 LCD Controller/Driver
2. Software Settings
a. Duty selection
Any of four duty cycles—static, 1/2 duty, 1/3 duty, or 1/4 duty—can be selected with bits
DTS1 and DTS0.
b. Segment selection
The segment drivers to be used can be selected with bits SGS3 to SGS0.
c. Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 13.3.5, Operation
in Power-Down Modes.
d. A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
LCDAB.
Rev. 6.00 Aug 04, 2006 page 443 of 680
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Section 13 LCD Controller/Driver
13.3.2
Relationship between LCD RAM and Display
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles with the segment not externally expanded are
shown in figures 13.5 to 13.8, and ones with the segments externally expanded are shown in
figures 13.9 to 13.12.
After setting the registers required for display, data is written to the part corresponding to the duty
using the same kind of instruction as for ordinary RAM, and display is started automatically when
turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
H'F740
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
H'F753
SEG40
SEG40
SEG40
SEG40
SEG39
SEG39
SEG39
SEG39
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 13.5 LCD RAM Map with Segments Not Externally Expanded (1/4 Duty)
Rev. 6.00 Aug 04, 2006 page 444 of 680
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Section 13 LCD Controller/Driver
Bit 7
Bit 6
Bit 5
Bit 4
H'F740
SEG2
SEG2
H'F753
SEG40
COM3
Bit 3
Bit 2
Bit 1
Bit 0
SEG2
SEG1
SEG1
SEG1
SEG40
SEG40
SEG39
SEG39
SEG39
COM2
COM1
COM3
COM2
COM1
Space not used for display
Figure 13.6 LCD RAM Map with Segments Not Externally Expanded (1/3 Duty)
Rev. 6.00 Aug 04, 2006 page 445 of 680
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Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Display space
SEG40
SEG40
SEG39
SEG39
SEG38
SEG38
SEG37
SEG37
H'F74A
Space not used for display
H'F753
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13.7 LCD RAM Map with Segments Not Externally Expanded (1/2 Duty)
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Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Display
space
SEG40
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
H'F745
Space not
used for
display
H'F753
COM1
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13.8 LCD RAM Map with Segments Not Externally Expanded (Static Mode)
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Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG2
SEG2
SEG2
SEG2
SEG1
SEG1
SEG1
SEG1
Expansion
driver
display
space
H'F75F
SEG64
SEG64
SEG64
SEG64
SEG63
SEG63
SEG63
SEG63
COM4
COM3
COM2
COM1
COM4
COM3
COM2
COM1
Figure 13.9 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/4 duty)
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Section 13 LCD Controller/Driver
Bit 7
H'F740
Bit 6
Bit 5
Bit 4
SEG2
SEG2
SEG2
Bit 3
Bit 2
Bit 1
Bit 0
SEG1
SEG1
SEG1
Expansion
driver
display
space
H'F75F
SEG64
SEG64
SEG64
SEG63
SEG63
SEG63
COM3
COM2
COM1
COM3
COM2
COM1
Space not used for display
Figure 13.10 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/3 duty)
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Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG4
SEG4
SEG3
SEG3
SEG2
SEG2
SEG1
SEG1
Expansion
driver
display
space
H'F75F
SEG128
SEG128
SEG127
SEG127
SEG126
SEG126
SEG125
SEG125
COM2
COM1
COM2
COM1
COM2
COM1
COM2
COM1
Figure 13.11 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” 1/2 duty)
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Section 13 LCD Controller/Driver
H'F740
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
Expansion
driver
display
space
H'F75F
SEG256
SEG255
SEG254
SEG253
SEG252
SEG251
SEG250
SEG249
COM1
COM1
COM1
COM1
COM1
COM1
COM1
COM1
Figure 13.12 LCD RAM Map with Segment Externally Expanded
(SGX = “1”, SGS3 to SGS0 = “0000” static)
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Section 13 LCD Controller/Driver
13.3.3
Luminance Adjustment Function (V0 Pin)
Figure 13.13 shows a detailed block diagram of the LCD drive power supply unit.
The voltage output to the V0 pin is VCC. When this voltage is used directly as the LCD drive power
supply, the V0 and V1 pins should be shorted. Also, connecting a variable resistance, R, between
the V0 and V1 pins makes it possible to adjust the voltage applied to the V1 pin, and so to provide
luminance adjustment for the LCD panel.
VCC
V0
R
V1
V2
V3
VSS
Figure 13.13 LCD Drive Power Supply Unit
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Section 13 LCD Controller/Driver
13.3.4
Low-Power-Consumption LCD Drive System
The use of the built-in split-resistance is normally the easiest method for implementing the LCD
power supply circuit, but since the built-in resistance is fixed, a certain direct current flows
constantly from the built-in resistance’s VCC to VSS. As this current does not depend on the
current dissipation of the LCD panel, if an LCD panel with a small current dissipation is used, a
wasteful amount of power will be consumed. The H8/3847R Group is equipped with a function to
minimize this waste of power. Use of this function makes it possible to achieve the optimum
power supply circuit for the LCD panel’s current dissipation.
1. Principles
1. Capacitors are connected as external circuits to LCD power supply pins V1, V2, and V3, as
shown in figure 13.14.
2. The capacitors connected to V1, V2, and V3 are repeatedly charged and discharged in the
cycle shown in figure 13.14, maintaining the potentials.
3. At this time, the charged potential is a potential corresponding to the V1, V2, and V3 pins,
respectively. (For example, with 1/3 bias drive, the charge for V2 is 2/3 that of V1, and that
for V3 is 1/3 that of V1.)
4. Power is supplied to the LCD panel by means of the charges accumulated in these
capacitors.
5. The capacitances and charging/discharging periods of these capacitors are therefore
determined by the current dissipation of the LCD panel.
6. The charging and discharging periods can be selected by software.
2. Example of operation (with 1/3 bias drive)
1. During charging period Tc in the figure, the potential is divided among pins V1, V2, and
V3 by the built-in split-resistance (the potential of V2 being 2/3 that of V1, and that of V3
being 1/3 that of V1), as shown in figure 13.14, and external capacitors C1, C2, and C3 are
charged. The LCD panel is continues to be driven during this time.
2. In the following discharging period, Tdc, charging is halted and the charge accumulated in
each capacitor is discharged, driving the LCD panel.
3. At this time, a slight voltage drop occurs due to the discharging; optimum values must be
selected for the charging period and the capacitor capacitances to ensure that this does not
affect the driving of the LCD panel.
4. In this way, the capacitors connected to V1, V2, and V3 are repeatedly charged and
discharged in the cycle shown in figure 13.14, maintaining the potentials and continuously
driving the LCD panel.
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Section 13 LCD Controller/Driver
5. As can be seen from the above description, the capacitances and charging/discharging
periods of the capacitors are determined by the current dissipation of the LCD panel used.
The charging/discharging periods can be selected with bits CDS3 to CDS0.
6. The actual capacitor capacitances and charging/discharging periods must be determined
experimentally in accordance with the current dissipation requirements of the LCD panel.
An optimum current value can be selected, in contrast to the case in which a direct current
flows constantly in the built-in split-resistance.
Charging
period Tc
Discharging
period Tdc
Vd1
V1 potential
V0
V1
V2 potential
C1
V2
V1×2/3
Voltage drop
associated with
discharging due
to LCD panel
driving
Vd2
C2
V3 potential
V3
V1×1/3
C3
Vd3
Power supply voltage fluctuation in 1/3 bias system
Figure 13.14 Example of Low-Power-Consumption LCD Drive Operation
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Section 13 LCD Controller/Driver
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
V1
V2
V3
VSS
COM4
SEGn
V1
V2
V3
VSS
COM1
V1
V2
V3
VSS
V1
V2
V3
VSS
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
(b) Waveform with 1/3 duty
1 frame
1 frame
M
M
Data
Data
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
VSS
V1
VSS
(d) Waveform with static output
(c) Waveform with 1/2 duty
Figure 13.15 Output Waveforms for Each Duty Cycle (A Waveform)
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Section 13 LCD Controller/Driver
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
COM4
V1
V2
V3
VSS
SEGn
1 frame
1 frame
1 frame
1 frame
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
COM1
COM2
COM3
V1
V2
V3
VSS
SEGn
(a) Waveform with 1/4 duty
1 frame
1 frame
(b) Waveform with 1/3 duty
1 frame
1 frame
1 frame
1 frame
1 frame
M
M
Data
Data
V1
COM1
V1
V2, V3
VSS
COM1
COM2
V1
V2, V3
VSS
SEGn
SEGn
V1
V2, V3
VSS
VSS
V1
VSS
(d) Waveform with static output
(c) Waveform with 1/2 duty
Figure 13.16 Output Waveforms for Each Duty Cycle (B Waveform)
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Section 13 LCD Controller/Driver
Table 13.3 Output Levels
Data
0
0
1
1
M
0
1
0
1
Common output
V1
VSS
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V2, V3
V2, V3
V1
VSS
Segment output
V1
VSS
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Common output
V3
V2
V1
VSS
Segment output
V2
V3
VSS
V1
Static
1/2 duty
1/3 duty
1/4 duty
13.3.5
Operation in Power-Down Modes
In this LSI, the LCD controller/driver can be operated even in the power-down modes. The
operating state of the LCD controller/driver in the power-down modes is summarized in table
13.4.
In subactive mode, watch mode, and subsleep mode, the system clock oscillator stops, and
therefore, unless φw, φw/2, or φw/4 has been selected by bits CKS3 to CKS0, the clock will not be
supplied and display will halt. Since there is a possibility that a direct current will be applied to
the LCD panel in this case, it is essential to ensure that φw, φw/2, or φw/4 is selected. In active
(medium-speed) mode, the system clock is switched, and therefore CKS3 to CKS0 must be
modified to ensure that the frame frequency does not change.
Table 13.4 Power-Down Modes and Display Operation
Mode
Clock
Runs
Runs
Runs
Stops
Module
Subactive Subsleep Standby Standby
Stops
Stops
Stops
Stops*4
Runs
Runs
Runs
Runs
Runs
Reset Active
φ
φw
Sleep
Watch
Runs
Stops*1
Stops*2
Display ACT = “0” Stops Stops
Stops
Stops
Stops
Stops
operation ACT = “1” Stops Functions Functions Functions Functions Functions Stops*2
*3
*3
*3
Notes:
1.
2.
3.
4.
Stops*4
Stops
Stops
The subclock oscillator does not stop, but clock supply is halted.
The LCD drive power supply is turned off regardless of the setting of the PSW bit.
Display operation is performed only if φw, φw/2, or φw/4 is selected as the operating clock.
The clock supplied to the LCD stops.
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Section 13 LCD Controller/Driver
13.3.6
Boosting the LCD Drive Power Supply
When a large panel is driven, the on-chip power supply capacity may be insufficient. In this case,
the power supply impedance must be reduced. This can be done by connecting bypass capacitors
of around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 13.17, or by adding a split-resistance
externally.
VCC
V0
V1
R
This LSI
R = several kΩ to
several MΩ
V2
R
C= 0.1 to 0.3µF
V3
R
VSS
Figure 13.17 Connection of External Split-Resistance
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Section 13 LCD Controller/Driver
13.3.7
Connection to HD66100
If the segments are to be expanded externally, an HD66100 should be connected. Connecting one
HD66100 provides 80-segment expansion. When carrying out external expansion, select the
external expansion signal function of pins SEG40 to SEG37 with the SGX bit in LPCR, and set bits
SGS3 to SGS0 to 0000. Data is output externally from SEG1 of the LCD RAM. SEG36 to SEG1
function as ports.
Figure 13.18 shows examples of connection to an HD66100. The output level is determined by a
combination of the data and the M pin output, but these combinations differ from those in the
HD66100. Table 13.3 shows the output levels of the LCD drive power supply, and figures 13.15
and 13.16 show the common and segment waveforms for each duty cycle.
When ACT is cleared to 0, operation stops with CL2 = 0, CL1 = 0, M = 0, and DO at the data value
(1 or 0) being output at that instant. In standby mode, the expansion pins go to the highimpedance (floating) state.
When external expansion is implemented, the load in the LCD panel increases and the on-chip
power supply may not provide sufficient current capacity. In this case, measures should be taken
as described in section 13.3.6, Boosting the LCD Drive Power Supply.
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Section 13 LCD Controller/Driver
VCC
VCC
V0
V1
V2
V3
This LSI
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
M
VSS
SEG40/CL1
SEG39/CL2
SEG38/DO
SEG37/M
HD66100
(a) 1/3 bias, 1/4 duty or 1/3 duty
VCC
VCC
V0
V1
V2
V3
This LSI
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
M
VSS
SEG40/CL1
SEG39/CL2
SEG38/DO
SEG37/M
HD66100
(b) 1/2 duty
VCC
VCC
V0
V1
V2
V3
This LSI
V1
V4
V3
V2
GND
VEE
SHL
CL1
CL2
DI
M
VSS
SEG40/CL1
SEG39/CL2
SEG38/DO
SEG37/M
(c) Static
Figure 13.18 Connection to HD66100
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HD66100
Section 14 Power Supply Circuit
Section 14 Power Supply Circuit
14.1
Overview
H8/3847R Group, H8/38347 Group and H8/38447 Group incorporate an internal power supply
step-down circuit. Use of this circuit enables the internal power supply to be fixed at a constant
level of approximately 3.0 V to 3.2 V, independently of the voltage of the power supply connected
to the external VCC pin. As a result, the current consumed when an external power supply is used
at 3.0 V or above can be held down to virtually the same low level as when used at approximately
3.0 V. If the external power supply is 3.0 V or below, the internal voltage will be practically the
same as the external voltage. It is, of course, also possible to use the same level of external power
supply voltage and internal power supply voltage without using the internal power supply stepdown circuit.
14.2
When Using Internal Power Supply Step-Down Circuit
Connect the external power supply to the VCC pin, and connect a capacitance of approximately 0.1
µF, in the case of the H8/3847R, or approximately 0.33 µF, in the case of the H8/38347 or
H8/38447, between CVCC and VSS, as shown in figure 14.1. The internal step-down circuit is
made effective simply by adding this external circuit. In the external circuit interface, the external
power supply voltage connected to VCC and the GND potential connected to VSS are the reference
levels. For example, for port input/output levels, the VCC level is the reference for the high level,
and the VSS level is that for the low level. The LCD power supply and A/D converter analog
power supply are not affected by the internal step-down circuit.
VCC
Step-down circuit
Internal
logic
CVCC
Internal
power
supply
VSS
Stabilization capacitance
(approximately 0.1 µF, in the case of the H8/3847R,
or approximately 0.33 µF, in the case of the H8/38347
or H8/38447)
Figure 14.1 Power Supply Connection when Internal Step-Down Circuit is Used
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Section 14 Power Supply Circuit
14.3
When Not Using Internal Power Supply Step-Down Circuit
When the internal power supply step-down circuit is not used, connect the external power supply
to the CVCC pin and VCC pin, as shown in figure 14.2. The external power supply is then input
directly to the internal power supply. The permissible range for the power supply voltage is 1.8 V
to 5.5 V for the H8/3847R Group and 2.7 V to 3.6 V for the H8/38347 Group and H8/38447
Group. Normally, however, the internal power supply step-down circuit should be used. Operation
cannot be guaranteed if a voltage outside this range is input.
VCC
Step-down circuit
Internal
logic
CVCC
Internal
power
supply
VSS
Figure 14.2 Power Supply Connection when Internal Step-Down Circuit is Not Used
14.4
H8/3847S Group
The H8/3847S Group has two VCC pins, which should be interconnected externally.
14.5
Notes on Switching from the H8/3847R to the H8/38347 or H8/38447
Examine the following with regard to the power supply circuit.
(1) If the internal power supply step-down circuit was used on the H8/3847R
The stabilization capacitance value differs between the products. It is necessary to change the
value from 0.1 µF (H8/3847R) to 0.33 µF (H8/38347 or H8/38447). Note that these values are
rough guidelines and it is still necessary to confirm system operation.
(2) If the internal power supply step-down circuit was not used on the H8/3847R
Use of the internal power supply step-down circuit of the H8/38347 or H8/38447 is
recommended. Furthermore, operation at a VCC of 3.6 V or greater is not guaranteed if the
internal power supply step-down circuit is not used. It is therefore necessary to change the
CVCC connection to use the internal power supply step-down circuit.
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Section 15 Electrical Characteristics
Section 15 Electrical Characteristics
15.1
H8/3847R Group Absolute Maximum Ratings
(Regular Specifications)
Table 15.1 lists the absolute maximum ratings.
Table 15.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Notes
*1
Power supply voltage
VCC
–0.3 to +7.0
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.0
V
Input voltage
Ports other than Ports B and C
Vin
–0.3 to VCC +0.3
V
Ports B and C
AVin
V
°C
Operating temperature
Topr
–0.3 to AVCC +0.3
2
–20 to +75*
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. The operating temperature is the temperature range in which power (voltage Vcc shown
in "Electrical Characteristics") can be applied to the chip.
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Section 15 Electrical Characteristics
15.2
H8/3847R Electrical Characteristics (Regular Specifications)
15.2.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range of the H8/3847R Group are indicated by the shaded
region in the figures.
1. Power supply voltage and oscillator frequency range
38.4
fW (kHz)
fosc (MHz)
16.0
10.0
32.768
4.0
2.0
1.8
2.7
4.5
5.5
1.8
• All operating modes
• Sleep (high-speed) mode
• Internal power supply step-down circuit not used
fosc (MHz)
Note:
fosc is the oscillator frequency. When external
clocks are used, fosc=1MHz is the minimum.
10.0
4.0
2.0
1.8
5.5
2.7
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
• Internal power supply step-down circuit used
Note:
fosc is the oscillator frequency. When external
clocks are used, fosc=1MHz is the minimum.
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5.5
VCC (V)
VCC (V)
• Active (high-speed) mode
3.6
Section 15 Electrical Characteristics
2. Power supply voltage and operating frequency range
φ (MHz)
8.0
5.0
19.2
2.0
16.384
1.0
(0.5)
4.5
5.5
VCC (V)
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=1MHz.
9.6
φSUB (kHz)
2.7
1.8
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
• Internal power supply step-down circuit not used
8.192
4.8
4.096
1000
φ (kHz)
1.8
3.6
5.5
625
VCC (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
250
15.625
(7.813)
1.8
2.7
4.5
5.5
VCC (V)
• Active (medium-speed) mode (except A/D converter)
• Sleep (medium-speed) mode (except A/D converter)
• Internal power supply step-down circuit not used
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=15.625kHz.
φ (MHz)
5.0
2.0
1.0
(0.5)
1.8 2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
• Internal power supply step-down circuit used
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=1MHz.
φ (kHz)
625
250
15.625
(7.813)
1.8
2.7
5.5
VCC (V)
• Active (medium-speed) mode (except A/D converter)
• Sleep (medium-speed) mode (except A/D converter)
• Internal power supply step-down circuit used
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=15.625kHz.
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Section 15 Electrical Characteristics
3. Analog power supply voltage and A/D converter operating range
1000
φ (kHz)
φ (MHz)
5.0
625
500
1.0
0.5
1.8
2.7
4.5
1.8
5.5
2.7
4.5
5.5
AVCC (V)
AVCC (V)
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
• Internal power supply step-down circuit
• Internal power supply step-down circuit not used
φ (kHz)
not used and used
625
500
1.8
2.7
4.5
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
• Internal power supply step-down circuit not used
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Section 15 Electrical Characteristics
15.2.2
DC Characteristics
Table 15.2 lists the DC characteristics.
Table 15.2 DC Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*4
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Input
VIH
high
voltage
Min
Typ
Max
Unit Test Condition
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
0.8 VCC
—
VCC + 0.3
V
TMIG, SCK1, SCK31,
SCK32, ADTRG
0.9 VCC
—
VCC + 0.3
SI1, RXD31, RXD32, UD 0.7 VCC
—
VCC + 0.3
0.8 VCC
—
VCC + 0.3
0.8 VCC
—
VCC + 0.3
0.9 VCC
—
VCC + 0.3
OSC1
X1
Notes
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
0.9 VCC
—
VCC + 0.3
V
VCC = 1.8 V to 5.5 V
P10 to P17, P20 to P27, 0.7 VCC
P30 to P37, P40 to P43,
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
P50 to P57, P60 to P67, 0.8 VCC
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
VCC + 0.3
Except the above
PB0 to PB7,
0.7 VCC
—
AVCC + 0.3
VCC = 4.0 V to 5.5 V
PC0 to PC3
0.8 VCC
—
AVCC + 0.3
Except the above
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Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Input
VIL
low
voltage
Min
Typ
Max
Unit Test Condition
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
–0.3
—
0.2 VCC
V
TMIG, SCK1, SCK31,
SCK32, ADTRG
–0.3
—
0.1 VCC
—
0.3 VCC
–0.3
—
0.2 VCC
–0.3
—
0.2
V
Internal power supply
step-down circuit used
–0.3
—
0.2 VCC
V
VCC = 4.0 V to 5.5 V
V
VCC = 4.0 V to 5.5 V
Except the above
–0.3
—
0.1 VCC
–0.3
—
0.1 VCC
V
VCC = 1.8 V to 5.5 V
P10 to P17, P20 to P27, –0.3
P30 to P37, P40 to P43,
P50 to P57, P60 to P67,
—
0.3 VCC
V
VCC = 4.0 V to 5.5 V
P70 to P77, P80 to P87, –0.3
P90 to P97, PA0 to PA3,
PB0 to PB7,
PC0 to PC3
—
0.2 VCC
P10 to P17, P20 to P27, VCC – 1.0
P30 to P37, P40 to P42,
—
—
P50 to P57, P60 to P67, VCC – 0.5
P70 to P77, P80 to P87,
—
—
VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
P90 to P97, PA0 to PA3 VCC – 0.3
—
—
–IOH = 0.1 mA
P10 to P17, P40 to P42 —
—
0.6
—
—
0.5
IOL = 0.4 mA
P50 to P57, P60 to P67, —
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
0.5
IOL = 0.4 mA
P20 to P27, P30 to P37 —
—
1.5
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.6
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
0.5
IOL = 0.4 mA
X1
Output VOL
low
voltage
Except the above
SI1, RXD31, RXD32, UD –0.3
OSC1
Output VOH
high
voltage
VCC = 4.0 V to 5.5 V
Rev. 6.00 Aug 04, 2006 page 468 of 680
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Except the above
Except the above
V
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
Notes
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Input/ | IIL |
output
leakage
current
Min
Typ
Max
Unit Test Condition
Notes
—
—
20.0
µA
VIN = 0.5 V to
*2
—
—
1.0
VCC – 0.5 V
*1
OSC1, X1, P10 to P17, —
P20 to P27, P30 to P37,
P40 to P42, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P90 to P97,
PA0 to PA3
—
1.0
PB0 to PB7,
PC0 to PC3
—
1.0
RES, P43
—
µA
VIN = 0.5 V to
VCC – 0.5 V
VIN = 0.5 V to
AVCC – 0.5 V
Pull-up –Ip
MOS
current
P10 to P17, P30 to P37, 50.0
—
300.0
P50 to P57, P60 to P67 —
35.0
—
Input
CIN
capacitance
All input pins except
power supply, RES,
P43, PB0 to PB7
—
—
15.0
RES
—
—
80.0
*2
—
—
15.0
*1
—
—
50.0
*2
—
—
15.0
*1
PB0 to PB7
—
—
15.0
Active IOPE1
mode
current
dissipation
IOPE2
VCC
—
4.5
6.5
mA
Active (high-speed)
mode
VCC = 5 V,
fOSC = 10 MHz
*3
*5
*6
VCC
—
1.3
2.0
mA
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz,
φOSC/128
*3
*5
*6
Sleep ISLEEP
mode
current
dissipation
VCC
—
2.5
4.0
mA
VCC = 5 V,
fOSC = 10 MHz
*3
*5
*6
P43
µA
VCC = 5 V, VIN = 0 V
VCC = 2.7 V, VIN = 0 V
pF
Reference
value
f = 1 MHz, VIN =0 V,
Ta = 25°C
Rev. 6.00 Aug 04, 2006 page 469 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Unit Test Condition
—
15
30
µA
*3
VCC = 2.7 V, LCD on
5
*
32 kHz crystal
oscillator (φSUB = φW/2) *6
—
8
—
µA
*3
VCC = 2.7 V, LCD on
*5
32 kHz crystal
oscillator (φSUB = φW/8) Reference
value
*6
VCC
—
7.5
16
µA
*3
VCC = 2.7 V, LCD on
*5
32 kHz crystal
oscillator (φSUB = φW/2) *6
Watch IWATCH
mode
current
dissipation
VCC
—
2.8
6.0
µA
VCC = 2.7 V, 32 kHz
crystal oscillator
LCD not used
*3
*5
*6
Stand- ISTBY
by
mode
current
dissipation
VCC
—
1.0
5.0
µA
32 kHz crystal
oscillator not used
*3
*5
RAM
VRAM
data
retaining
voltage
VCC
1.5
—
—
V
Allow- IOL
able
output
low
current
(per
pin)
Output pins except
ports 2 and 3
—
—
2.0
mA
Ports 2 and 3
—
—
10.0
All output pins
—
—
0.5
Allow- ∑ IOL
able
output
low
current
(total)
Output pins except
ports 2 and 3
—
—
40.0
SubISUB
active
mode
current
dissipation
VCC
ISUBSP
Subsleep
mode
current
dissipation
Ports 2 and 3
—
—
80.0
All output pins
—
—
20.0
Rev. 6.00 Aug 04, 2006 page 470 of 680
REJ09B0145-0600
*3
*5
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
mA
Notes
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Allow- –IOH
able
output
high
current
(per
pin)
All output pins
Allow- ∑ – IOH
able
output
high
current
(total)
All output pins
Min
Typ
Max
Unit Test Condition
—
—
2.0
mA
—
—
0.2
—
—
15.0
—
—
10.0
Notes
VCC = 4.0 V to 5.5 V
Except the above
mA
VCC = 4.0 V to 5.5 V
Except the above
Notes: Connect the TEST pin to VSS.
1. Applies to the Mask ROM products.
2. Applies to the HD6473847R.
3. Pin states during current measurement.
RES Pin Internal State
Only CPU Operates
VCC
Mode
Active (high-speed)
mode
Active (mediumspeed) mode
Sleep mode
Subactive mode
Subsleep mode
VCC
VCC
VCC
Watch mode
VCC
Standby mode
VCC
Only timers operate
Only CPU Operates
Only timers operate,
CPU stops
Only time base
operates, CPU stops
CPU and timers both
stop
Other LCD Power
Pins Supply
Oscillator Pins
VCC
Halted
System clock oscillator:
Crystal
Subclock oscillator:
Pin X1 = GND
VCC
VCC
Halted
System clock oscillator:
crystal
VCC
Halted
Subclock oscillator:
VCC
Halted
crystal
VCC
Halted
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
4. The guaranteed temperature as an electrical characteristic for Die products is 75°C.
5. Excludes current in pull-up MOS transistors and output buffers.
6. When internal step-down circuit is used.
Rev. 6.00 Aug 04, 2006 page 471 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
15.2.3
AC Characteristics
Table 15.3 lists the control signal timing, and tables 15.4 and 15.5 list the serial interface timing.
Table 15.3 Control Signal Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*4
(including subactive mode) unless otherwise indicated.
Item
System clock
oscillation
frequency
Applicable
Symbol Pins
fOSC
OSC clock (φOSC) tOSC
cycle time
Values
Min
OSC1, OSC2 2
Typ
Max
Unit
Test Condition
Reference
Figure
—
16
MHz
VCC = 4.5 V to 5.5 V
*2
2
—
10
VCC = 2.7 V to 5.5 V
2
—
4
VCC = 1.8 V to 5.5 V
OSC1, OSC2 62.5
—
500
ns
(1000)
VCC = 4.5 V to 5.5 V
Figure 15.1
*2 *3
100
—
500
(1000)
VCC = 2.7 V to 5.5 V
Figure 15.1
*3
250
—
500
(1000)
VCC = 1.8 V to 5.5 V
System clock (φ) tcyc
cycle time
2
—
128
tOSC
—
—
244.1
µs
Subclock oscilla- fW
tion frequency
X1, X2
—
32.768 —
or
38.4
kHz
Watch clock (φW) tW
cycle time
X1, X2
—
30.5
or
26.0
—
µs
Figure 15.1
2
—
8
tW
*1
2
—
—
tcyc
OSC1, OSC2 —
20
45
µs
Figure 15.10
VCC = 2.2 V to 5.5 V
Figure 15.10
*2
—
0.1
8
ms
Figure 15.10
VCC = 2.2 V to 5.5 V
Figure 15.10
—
—
50
ms
Except the above
—
—
2.0
s
Subclock (φSUB)
cycle time
tsubcyc
Instruction cycle
time
Oscillation
trc
stabilization time
tsubcyc
X1, X2
Rev. 6.00 Aug 04, 2006 page 472 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Item
External clock
high width
External clock
low width
External clock
rise time
External clock
fall time
Values
Applicable
Symbol Pins
Min
Typ
Max
Unit
Test Condition
tCPH
25
—
—
ns
VCC = 4.5 V to 5.5 V Figure 15.1
*2
40
—
—
tCPL
tCPr
tCPf
OSC1
Reference
Figure
VCC = 2.7 V to 5.5 V Figure 15.1
100
—
—
X1
—
15.26
or
13.02
—
µs
VCC = 1.8 V to 5.5 V
OSC1
25
—
—
ns
40
—
—
VCC = 4.5 V to 5.5 V Figure 15.1
*2
VCC = 2.7 V to 5.5 V Figure 15.1
100
—
—
X1
—
15.26
or
13.02
—
µs
VCC = 1.8 V to 5.5 V
OSC1
—
—
6
ns
—
—
10
VCC = 2.7 V to 5.5 V Figure 15.1
—
—
25
VCC = 1.8 V to 5.5 V
X1
—
—
55.0
ns
Figure 15.1
OSC1
—
—
6
ns
VCC = 4.5 V to 5.5 V Figure 15.1
*2
—
—
10
VCC = 2.7 V to 5.5 V Figure 15.1
—
—
25
VCC = 1.8 V to 5.5 V
VCC = 4.5 V to 5.5 V Figure 15.1
*2
X1
—
—
55.0
ns
Figure 15.1
Pin RES low
width
tREL
RES
10
—
—
tcyc
Figure 15.2
Input pin high
width
tIH
IRQ0 to IRQ4, 2
WKP0 to
WKP7,
ADTRG,
TMIC
TMIF, TMIG,
AEVL, AEVH
—
—
tcyc
Figure 15.3
tsubcyc
Rev. 6.00 Aug 04, 2006 page 473 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Item
Input pin low
width
Applicable
Symbol Pins
tIL
UD pin minimum tUDH
modulation width tUDL
Notes: 1.
2.
3.
4.
Values
Min
Typ
Max
Unit
IRQ0 to IRQ4, 2
WKP0 to
WKP7,
ADTRG,
TMIC, TMIF,
TMIG, AEVL,
AEVH
—
—
tcyc
UD
—
4
Test Condition
Reference
Figure
Figure 15.3
tsubcyc
—
tcyc
Figure 15.4
tsubcyc
Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
When internal power supply step-down circuit is not used.
Figures in parentheses are the maximum tOSC rate with external clock input.
The guaranteed temperature as an electrical characteristic for Die products is 75°C.
Rev. 6.00 Aug 04, 2006 page 474 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Table 15.4 Serial Interface (SCI1) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*2 unless
otherwise indicated
Item
Applicable
Symbol Pins
Values
Min
Typ
Max
Unit Test Condition
Reference
Figure
Input clock cycle tScyc
SCK1
4
—
—
tcyc
Figure 15.5
Input clock high
width
tSCKH
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock low
width
tSCKL
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock rise
tSCKr
SCK1
—
—
60.0
ns
VCC = 4.0 V to 5.5 V
—
—
80.0
ns
Except the above
Figure 15.5
tSCKf
SCK1
—
—
60.0
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*1
—
—
80.0
ns
Except the above
Figure 15.5
tSOD
SO1
—
—
200.0
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*1
—
—
350.0
ns
Except the above
Figure 15.5
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*1
400.0
—
—
ns
Except the above
Figure 15.5
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*1
400.0
—
—
ns
Except the above
Figure 15.5
time
Input clock fall
time
Serial output
data delay time
Serial input data tSIS
SI1
setup time
Serial input data tSIH
hold time
SI1
Figure 15.5*1
Notes: 1. When internal power supply step-down circuit is not used.
2. The guaranteed temperature as an electrical characteristic for Die products is 75°C.
Rev. 6.00 Aug 04, 2006 page 475 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Table 15.5 Serial Interface (SCI3-1, SCI3-2) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*2
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Min
Typ
Max
Unit
Input clock
Asynchronous tScyc
4
—
—
tcyc or
cycle
Synchronous
6
—
—
tsubcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tScyc
Transmit data delay time
tTXD
—
—
1
tcyc or
(synchronous)
Receive data setup time
(synchronous)
Reference
Figure
Figure 15.6
Figure 15.6
VCC = 4.0 V to 5.5 V
Figure 15.7
—
—
1
tsubcyc
Except the above
tRXS
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
400.0
—
—
Except the above
Figure 15.7
tRXH
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
Figure 15.7*1
400.0
—
—
Except the above
Figure 15.7
(synchronous)
Receive data hold time
Test Conditions
Figure 15.7*1
Notes: 1. When internal power supply step-down circuit is not used
2. The guaranteed temperature as an electrical characteristic for Die products is 75°C.
Rev. 6.00 Aug 04, 2006 page 476 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
15.2.4
A/D Converter Characteristics
Table 15.6 shows the A/D converter characteristics.
Table 15.6 A/D Converter Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*6 unless otherwise indicated.
Item
Analog power
supply voltage
Analog input
voltage
Analog power
supply current
Analog input
capacitance
Allowable
signal source
impedance
Resolution
(data length)
Nonlinearity
error
Quantization
error
Absolute
accuracy
Conversion
time
Values
Applicable
Symbol Pins
Min
Typ
Max
Unit
AVCC
AVCC
1.8
—
5.5
V
AVIN
AN0 to AN11 – 0.3
—
AVCC + 0.3 V
AIOPE
AISTOP1
AVCC
AVCC
—
600
1.5
—
mA
µA
AISTOP2
CAIN
AVCC
—
AN0 to AN11 —
—
—
5
15.0
µA
pF
—
—
10.0
kΩ
—
—
10
bit
—
—
±2.5
LSB
—
—
±5.5
—
—
—
—
±7.5
±0.5
LSB
—
—
±3.0
LSB
—
—
±6.0
—
12.4
—
—
±8.0
124
62
—
124
RAIN
—
—
µs
Test Condition
AVCC = 5.0 V
Notes
*1
*2
Reference
value
*3
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
AVCC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
Except the above
*4
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
AVCC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
Except the above
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
Except the above
*4
*5
*5
*4
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. When internal power supply step-down circuit is not used.
5. Conversion time: 62 µs
6. The guaranteed temperature as an electrical characteristic for Die products is 75°C.
Rev. 6.00 Aug 04, 2006 page 477 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
15.2.5
LCD Characteristics
Table 15.7 shows the LCD characteristics.
Table 15.7 LCD Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*3
(including subactive mode) unless otherwise indicated.
Item
Symbol
Applicable Values
Pins
Min Typ
Max
Unit
Segment driver VDS
drop voltage
SEG1 to
SEG40
—
—
0.6
V
Common driver VDC
drop voltage
COM1 to
COM4
—
—
0.3
V
0.5
3.0
9.0
MΩ
2.2
—
5.5
V
LCD power
supply splitresistance
RLCD
Liquid crystal VLCD
display voltage
V1
Test
Conditions
Notes
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
Between V1
and VSS
*2
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: V1 ≥ V2 ≥ V3 ≥ VSS.
3. The guaranteed temperature as an electrical characteristic for Die products is 75°C.
Rev. 6.00 Aug 04, 2006 page 478 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Table 15.8 Segment External Expansion AC Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –20°C to +75°C*2 (including subactive mode)
unless otherwise indicated.
Item
Symbol
Values
Applicable
Pins
Min
Clock high width
tCWH
CL1, CL2
Clock low width
Clock setup time
tCWL
tCSU
CL2
CL1, CL2
800.0
800.0
500.0
Typ Max
Reference
Test
Unit Conditions Figure
—
ns
*1
Figure 15.8
ns
*1
Figure 15.8
ns
*1
Figure 15.8
Figure 15.8
—
—
—
—
—
tSU
DO
300.0
—
—
ns
*1
Data retaining time tDH
DO
300.0
—
—
ns
*1
Figure 15.8
*1
Figure 15.8
Data setup time
M delay time
tDM
Clock rise/fall time tCT
M
–1000.0
—
1000.0 ns
CL1, CL2
—
—
170.0
ns
Figure 15.8
Notes: 1. When the frame frequency is set at 488 Hz to 30.5 Hz.
2. The guaranteed temperature as an electrical characteristic for Die products is 75°C.
Rev. 6.00 Aug 04, 2006 page 479 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
15.3
H8/3847R Group Absolute Maximum Ratings (Wide-range
Specification)
Table 15.9 lists the absolute maximum ratings.
Table 15.9 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Programming voltage
VPP
–0.3 to +13.0
V
Input voltage
Ports other than Ports B and C
Vin
–0.3 to VCC +0.3
V
Ports B and C
AVin
–0.3 to AVCC +0.3
V
Operating temperature
Topr
–40 to +85
°C
Storage temperature
Tstg
–55 to +125
°C
Note: Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics. Exceeding
these values can result in incorrect operation and reduced reliability.
Rev. 6.00 Aug 04, 2006 page 480 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
15.4
H8/3847R Electrical Characteristics (Wide-range Specification)
15.4.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
1. Power supply voltage and oscillator frequency range
38.4
fW (kHz)
fosc (MHz)
16.0
10.0
32.768
4.0
2.0
1.8
2.7
4.5
5.5
1.8
5.5
VCC (V)
VCC (V)
• Active (high-speed) mode
3.6
• All operating modes
• Sleep (high-speed) mode
• Internal power supply step-down circuit not used
fosc (MHz)
Note:
fosc is the oscillator frequency. When external
clocks are used, fosc=1MHz is the minimum.
10.0
4.0
2.0
1.8
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
• Internal power supply step-down circuit used
Note:
fosc is the oscillator frequency. When external
clocks are used, fosc=1MHz is the minimum.
Rev. 6.00 Aug 04, 2006 page 481 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
2. Power supply voltage and operating frequency range
φ (MHz)
8.0
5.0
19.2
2.0
16.384
1.0
(0.5)
4.5
5.5
VCC (V)
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=1MHz.
9.6
φSUB (kHz)
2.7
1.8
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
• Internal power supply step-down circuit not used
8.192
4.8
4.096
1000
φ (kHz)
1.8
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
250
1.8
2.7
4.5
5.5
VCC (V)
• Active (medium-speed) mode (except A/D converter)
• Sleep (medium-speed) mode (except A/D converter)
• Internal power supply step-down circuit not used
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=15.625kHz.
5.0
φ (MHz)
5.5
VCC (V)
15.625
(7.813)
2.0
1.0
(0.5)
1.8 2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
• Internal power supply step-down circuit used
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=1MHz.
625
φ (kHz)
3.6
625
250
15.625
(7.813)
1.8
2.7
5.5
VCC (V)
• Active (medium-speed) mode (except A/D converter)
• Sleep (medium-speed) mode (except A/D converter)
• Internal power supply step-down circuit used
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=15.625kHz.
Rev. 6.00 Aug 04, 2006 page 482 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
3. Analog power supply voltage and A/D converter operating range
1000
φ (kHz)
φ (MHz)
5.0
625
500
1.0
0.5
1.8
2.7
4.5
1.8
5.5
2.7
4.5
5.5
AVCC (V)
AVCC (V)
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
• Internal power supply step-down circuit
• Internal power supply step-down circuit not used
φ (kHz)
not used and used
625
500
1.8
2.7
4.5
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
• Internal power supply step-down circuit not used
Rev. 6.00 Aug 04, 2006 page 483 of 680
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Section 15 Electrical Characteristics
15.4.2
DC Characteristics
Table 15.10 lists the DC characteristics.
Table 15.10 DC Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C
(including subactive mode) unless otherwise indicated.
Values
Item
Symbol Applicable Pins
Input
VIH
high
voltage
Min
Typ
Max
Unit Test Condition
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
0.8 VCC
—
VCC + 0.3
V
TMIG, SCK1, SCK31,
SCK32, ADTRG
0.9 VCC
—
VCC + 0.3
SI1, RXD31, RXD32, UD 0.7 VCC
—
VCC + 0.3
0.8 VCC
—
VCC + 0.3
0.8 VCC
—
VCC + 0.3
0.9 VCC
—
VCC + 0.3
OSC1
X1
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
V
VCC = 4.0 V to 5.5 V
Except the above
0.9 VCC
—
VCC + 0.3
V
VCC = 1.8 V to 5.5 V
P10 to P17, P20 to P27, 0.7 VCC
P30 to P37, P40 to P43,
—
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
P50 to P57, P60 to P67, 0.8 VCC
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
VCC + 0.3
Except the above
PB0 to PB7,
0.7 VCC
—
AVCC + 0.3
VCC = 4.0 V to 5.5 V
PC0 to PC3
0.8 VCC
—
AVCC + 0.3
Except the above
Rev. 6.00 Aug 04, 2006 page 484 of 680
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Notes
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Input
VIL
low
voltage
Min
Typ
Max
Unit Test Condition
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
–0.3
—
0.2 VCC
V
TMIG, SCK1, SCK31,
SCK32, ADTRG
–0.3
—
0.1 VCC
—
0.3 VCC
–0.3
—
0.2 VCC
–0.3
—
0.2
V
Internal power supply
step-down circuit used
–0.3
—
0.2 VCC
V
VCC = 4.0 V to 5.5 V
Output VOL
low
voltage
V
VCC = 4.0 V to 5.5 V
Except the above
–0.3
—
0.1 VCC
–0.3
—
0.1 VCC
V
VCC = 1.8 V to 5.5 V
P10 to P17, P20 to P27, –0.3
P30 to P37, P40 to P43,
P50 to P57, P60 to P67,
—
0.3 VCC
V
VCC = 4.0 V to 5.5 V
P70 to P77, P80 to P87, –0.3
P90 to P97, PA0 to PA3,
PB0 to PB7,
PC0 to PC3
—
0.2 VCC
P10 to P17, P20 to P27, VCC – 1.0
P30 to P37, P40 to P42,
—
—
P50 to P57, P60 to P67, VCC – 0.5
P70 to P77, P80 to P87,
—
—
VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
P90 to P97, PA0 to PA3 VCC – 0.3
—
—
–IOH = 0.1 mA
P10 to P17, P40 to P42 —
—
0.6
—
—
0.5
IOL = 0.4 mA
P50 to P57, P60 to P67, —
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
0.5
IOL = 0.4 mA
P20 to P27, P30 to P37 —
—
1.5
VCC = 4.0 V to 5.5 V
IOL = 10 mA
—
—
0.6
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
—
—
0.5
IOL = 0.4 mA
X1
Output VOH
high
voltage
Except the above
SI1, RXD31, RXD32, UD –0.3
OSC1
Notes
VCC = 4.0 V to 5.5 V
Except the above
Except the above
V
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
VCC = 4.0 V to 5.5 V
IOL = 1.6 mA
Rev. 6.00 Aug 04, 2006 page 485 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Input/ | IIL |
output
leakage
current
Min
Typ
Max
Unit Test Condition
Notes
—
—
20.0
µA
VIN = 0.5 V to
*2
—
—
1.0
VCC – 0.5 V
*1
OSC1, X1, P10 to P17, —
P20 to P27, P30 to P37,
P40 to P42, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P90 to P97,
PA0 to PA3
—
1.0
PB0 to PB7,
PC0 to PC3
—
1.0
RES, P43
—
µA
VIN = 0.5 V to
VCC – 0.5 V
VIN = 0.5 V to
AVCC – 0.5 V
Pull-up –Ip
MOS
current
P10 to P17, P30 to P37, 50.0
—
300.0
P50 to P57, P60 to P67 —
35.0
—
Input
CIN
capacitance
All input pins except
power supply, RES,
P43, PB0 to PB7
—
—
15.0
RES
—
—
80.0
*2
—
—
15.0
*1
—
—
50.0
*2
—
—
15.0
*1
PB0 to PB7
—
—
15.0
Active IOPE1
mode
current
dissipation
IOPE2
VCC
—
4.5
6.5
mA
Active (high-speed)
mode
VCC = 5 V,
fOSC = 10 MHz
*3
*4
*5
VCC
—
1.3
2.0
mA
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz,
φOSC/128
*3
*4
*5
Sleep ISLEEP
mode
current
dissipation
VCC
—
2.5
4.0
mA
VCC = 5 V,
fOSC = 10 MHz
*3
*4
*5
P43
Rev. 6.00 Aug 04, 2006 page 486 of 680
REJ09B0145-0600
µA
VCC = 5 V, VIN = 0 V
VCC = 2.7 V, VIN = 0 V
pF
Reference
value
f = 1 MHz, VIN =0 V,
Ta = 25°C
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Unit Test Condition
—
15
30
µA
*3
VCC = 2.7 V, LCD on
4
*
32 kHz crystal
oscillator (φSUB = φW/2) *5
—
8
—
µA
*3
VCC = 2.7 V, LCD on
*4
32 kHz crystal
oscillator (φSUB = φW/8) Reference
value
*5
VCC
—
7.5
16
µA
*3
VCC = 2.7 V, LCD on
*4
32 kHz crystal
oscillator (φSUB = φW/2) *5
Watch IWATCH
mode
current
dissipation
VCC
—
2.8
6.0
µA
VCC = 2.7 V, 32 kHz
crystal oscillator
LCD not used
*3
*4
*5
Stand- ISTBY
by
mode
current
dissipation
VCC
—
1.0
5.0
µA
32 kHz crystal
oscillator not used
*3
*4
RAM
VRAM
data
retaining
voltage
VCC
1.5
—
—
V
Allow- IOL
able
output
low
current
(per
pin)
Output pins except
ports 2 and 3
—
—
2.0
mA
Ports 2 and 3
—
—
10.0
All output pins
—
—
0.5
Allow- ∑ IOL
able
output
low
current
(total)
Output pins except
ports 2 and 3
—
—
40.0
SubISUB
active
mode
current
dissipation
VCC
ISUBSP
Subsleep
mode
current
dissipation
Ports 2 and 3
—
—
80.0
All output pins
—
—
20.0
Notes
*3
*4
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
mA
VCC = 4.0 V to 5.5 V
VCC = 4.0 V to 5.5 V
Rev. 6.00 Aug 04, 2006 page 487 of 680
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Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Allow- –IOH
able
output
high
current
(per
pin)
All output pins
Allow- ∑ – IOH
able
output
high
current
(total)
All output pins
Min
Typ
Max
Unit Test Condition
—
—
2.0
mA
—
—
0.2
—
—
15.0
—
—
10.0
Notes
VCC = 4.0 V to 5.5 V
Except the above
mA
VCC = 4.0 V to 5.5 V
Except the above
Notes: Connect the TEST pin to VSS.
1. Applies to the Mask ROM products.
2. Applies to the HD6473847R.
3. Pin States during Current Dissipation Measurement
Mode
Active (high-speed)
mode
Active (mediumspeed) mode
Sleep mode
Subactive mode
Subsleep mode
RES Pin
VCC
Internal State
Only CPU Operates
VCC
VCC
VCC
Watch mode
VCC
Standby mode
VCC
Only timers operate
Only CPU Operates
Only timers operate,
CPU stops
Only time base
operates, CPU stops
CPU and timers both
stop
Other LCD Power
Pins Supply
Oscillator Pins
VCC
Halted
System clock oscillator:
Crystal
Subclock oscillator:
Pin X1 = GND
VCC
VCC
Halted
System clock oscillator:
crystal
VCC
Halted
Subclock oscillator:
VCC
Halted
crystal
VCC
Halted
4. Excludes current in pull-up MOS transistors and output buffers.
5. When internal step-down circuit is used.
Rev. 6.00 Aug 04, 2006 page 488 of 680
REJ09B0145-0600
System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
Section 15 Electrical Characteristics
15.4.3
AC Characteristics
Table 15.11 lists the control signal timing, and tables 15.12 and 15.13 list the serial interface
timing.
Table 15.11 Control Signal Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C
(including subactive mode) unless otherwise indicated.
Item
System clock
oscillation
frequency
Applicable
Symbol Pins
fOSC
OSC clock (φOSC) tOSC
cycle time
Values
Min
OSC1, OSC2 2
Typ
Max
Unit
Test Condition
Reference
Figure
—
16
MHz
VCC = 4.5 V to 5.5 V
*2
2
—
10
VCC = 2.7 V to 5.5 V
2
—
4
VCC = 1.8 V to 5.5 V
OSC1, OSC2 62.5
—
500
ns
(1000)
VCC = 4.5 V to 5.5 V
Figure 15.1
*2 *3
100
—
500
(1000)
VCC = 2.7 V to 5.5 V
Figure 15.1
*3
250
—
500
(1000)
VCC = 1.8 V to 5.5 V
2
—
128
tOSC
244.1
µs
System clock (φ) tcyc
cycle time
—
—
Subclock oscilla- fW
tion frequency
X1, X2
—
32.768 —
or
38.4
kHz
Watch clock (φW) tW
cycle time
X1, X2
—
30.5
or
26.0
—
µs
Figure 15.1
2
—
8
tW
*1
2
—
—
tcyc
OSC1, OSC2 —
20
45
µs
Figure 15.10
VCC = 2.2 V to 5.5 V
Figure 15.10
*2
—
0.1
8
ms
Figure 15.10
VCC = 2.2 V to 5.5 V
Figure 15.10
Except the above
Subclock (φSUB)
cycle time
tsubcyc
Instruction cycle
time
Oscillation
trc
stabilization time
tsubcyc
X1, X2
—
—
50
ms
—
—
2.0
s
Rev. 6.00 Aug 04, 2006 page 489 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Item
External clock
high width
External clock
low width
External clock
rise time
External clock
fall time
Values
Applicable
Symbol Pins
Min
Typ
Max
Unit
Test Condition
tCPH
25
—
—
ns
VCC = 4.5 V to 5.5 V
Figure 15.1
*2
40
—
—
VCC = 2.7 V to 5.5 V
Figure 15.1
tCPL
tCPr
tCPf
OSC1
100
—
—
X1
—
15.26
or
13.02
—
µs
OSC1
25
—
—
ns
40
—
—
Reference
Figure
VCC = 1.8 V to 5.5 V
100
—
—
X1
—
15.26
or
13.02
—
µs
OSC1
—
—
6
ns
—
—
—
—
X1
—
—
55.0
ns
OSC1
—
—
6
ns
—
—
—
—
VCC = 4.5 V to 5.5 V
Figure 15.1
*2
VCC = 2.7 V to 5.5 V
Figure 15.1
VCC = 1.8 V to 5.5 V
VCC = 4.5 V to 5.5 V
Figure 15.1
*2
10
VCC = 2.7 V to 5.5 V
Figure 15.1
25
VCC = 1.8 V to 5.5 V
Figure 15.1
VCC = 4.5 V to 5.5 V
Figure 15.1
*2
10
VCC = 2.7 V to 5.5 V
Figure 15.1
25
VCC = 1.8 V to 5.5 V
X1
—
—
55.0
ns
Figure 15.1
Pin RES low
width
tREL
RES
10
—
—
tcyc
Figure 15.2
Input pin high
width
tIH
IRQ0 to IRQ4, 2
WKP0 to
WKP7,
ADTRG,
TMIC
TMIF, TMIG,
AEVL, AEVH
—
—
tcyc
Figure 15.3
Rev. 6.00 Aug 04, 2006 page 490 of 680
REJ09B0145-0600
tsubcyc
Section 15 Electrical Characteristics
Item
Input pin low
width
Applicable
Symbol Pins
tIL
UD pin minimum tUDH
modulation width tUDL
Values
Min
Typ
Max
Unit
IRQ0 to IRQ4, 2
WKP0 to
WKP7,
ADTRG,
TMIC, TMIF,
TMIG, AEVL,
AEVH
—
—
tcyc
UD
—
4
Test Condition
Reference
Figure
Figure 15.3
tsubcyc
—
tcyc
Figure 15.4
tsubcyc
Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
2. When internal power supply step-down circuit is not used.
3. Figures in parentheses are the maximum tOSC rate with external clock input.
Rev. 6.00 Aug 04, 2006 page 491 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Table 15.12 Serial Interface (SCI1) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C unless
otherwise indicated
Applicable
Symbol Pins
Item
Values
Min
Typ
Max
Unit Test Condition
Reference
Figure
Input clock cycle tScyc
SCK1
4
—
—
tcyc
Figure 15.5
Input clock high
width
tSCKH
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock low
width
tSCKL
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock rise
tSCKr
SCK1
—
—
60.0
ns
VCC = 4.0 V to 5.5 V
—
—
80.0
ns
Except the above
Figure 15.5
tSCKf
SCK1
—
—
60.0
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*
—
—
80.0
ns
Except the above
Figure 15.5
tSOD
SO1
—
—
200.0
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*
—
—
350.0
ns
Except the above
Figure 15.5
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*
400.0
—
—
ns
Except the above
Figure 15.5
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
Figure 15.5*
400.0
—
—
ns
Except the above
Figure 15.5
time
Input clock fall
time
Serial output
data delay time
Serial input data tSIS
SI1
setup time
Serial input data tSIH
hold time
Note:
*
SI1
When internal power supply step-down circuit is not used.
Rev. 6.00 Aug 04, 2006 page 492 of 680
REJ09B0145-0600
Figure 15.5*
Section 15 Electrical Characteristics
Table 15.13 Serial Interface (SCI3-1, SCI3-2) Timing
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C unless
otherwise indicated.
Values
Item
Symbol Min
Typ
Max
Unit
Input clock
Asynchronous tScyc
4
—
—
tcyc or
cycle
Synchronous
6
—
—
tsubcyc
Input clock pulse width
tSCKW
0.4
—
0.6
tScyc
Transmit data delay time
tTXD
—
—
1
tcyc or
(synchronous)
Receive data setup time
(synchronous)
Note:
*
Reference
Figure
Figure 15.6
Figure 15.6
VCC = 4.0 V to 5.5 V
Figure 15.7
—
—
1
tsubcyc
Except the above
tRXS
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
400.0
—
—
Except the above
Figure 15.7
tRXH
200.0
—
—
ns
VCC = 4.0 V to 5.5 V
Figure 15.7*
400.0
—
—
Except the above
Figure 15.7
(synchronous)
Receive data hold time
Test Conditions
Figure 15.7*
When internal power supply step-down circuit is not used
Rev. 6.00 Aug 04, 2006 page 493 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
15.4.4
A/D Converter Characteristics
Table 15.14 shows the A/D converter characteristics.
Table 15.14 A/D Converter Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C unless otherwise indicated.
Item
Analog power
supply voltage
Analog input
voltage
Analog power
supply current
Analog input
capacitance
Allowable
signal source
impedance
Resolution
(data length)
Nonlinearity
error
Quantization
error
Absolute
accuracy
Conversion
time
Values
Applicable
Symbol Pins
Min
Typ
Max
Unit
AVCC
AVCC
1.8
—
5.5
V
AVIN
AN0 to AN11 – 0.3
—
AVCC + 0.3 V
AIOPE
AISTOP1
AVCC
AVCC
—
600
1.5
—
mA
µA
AISTOP2
CAIN
AVCC
—
AN0 to AN11 —
—
—
5
15.0
µA
pF
—
—
10.0
kΩ
—
—
10
bit
—
—
±2.5
LSB
—
—
±5.5
—
—
—
—
±7.5
±0.5
LSB
—
—
±3.0
LSB
—
—
±6.0
—
12.4
—
—
±8.0
124
62
—
124
RAIN
—
—
µs
Test Condition
Notes
*1
AVCC = 5.0 V
*2
Reference
value
*3
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
AVCC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
Except the above
*4
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
AVCC = 2.0 V to 5.5 V
VCC = 2.0 V to 5.5 V
Except the above
AVCC = 2.7 V to 5.5 V
VCC = 2.7 V to 5.5 V
Except the above
*4
*5
*5
*4
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. When internal power supply step-down circuit is not used.
5. Conversion time: 62 µs
Rev. 6.00 Aug 04, 2006 page 494 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
15.4.5
LCD Characteristics
Table 15.15 shows the LCD characteristics.
Table 15.15 LCD Characteristics
VCC = 1.8 V to 5.5 V, AVCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C
(including subactive mode) unless otherwise indicated.
Item
Symbol
Applicable Values
Pins
Min Typ
Max
Unit
Segment driver VDS
drop voltage
SEG1 to
SEG40
—
—
0.6
V
Common driver VDC
drop voltage
COM1 to
COM4
—
—
0.3
V
0.5
3.0
9.0
MΩ
2.2
—
5.5
V
LCD power
supply splitresistance
RLCD
Liquid crystal VLCD
display voltage
V1
Test
Conditions
Notes
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
Between V1
and VSS
*2
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: V1 ≥ V2 ≥ V3 ≥ VSS.
Rev. 6.00 Aug 04, 2006 page 495 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Table 15.16 Segment External Expansion AC Characteristics
VCC = 1.8 V to 5.5 V, VSS = AVSS = 0.0 V, Ta = –40°C to +85°C (including subactive mode)
unless otherwise indicated.
Item
Symbol
Applicable Values
Pins
Min
Clock high width
tCWH
CL1, CL2
800.0
—
—
ns
*
Figure 15.8
Clock low width
tCWL
CL2
800.0
—
—
ns
*
Figure 15.8
Clock setup time
tCSU
CL1, CL2
500.0
—
—
ns
*
Figure 15.8
Data setup time
Typ Max
Reference
Test
Unit Conditions Figure
tSU
DO
300.0
—
—
ns
*
Figure 15.8
Data retaining time tDH
DO
300.0
—
—
ns
*
Figure 15.8
M delay time
M
–1000.0
—
1000.0 ns
*
Figure 15.8
CL1, CL2
—
—
170.0
tDM
Clock rise/fall time tCT
Note:
*
When the frame frequency is set at 488 Hz to 30.5 Hz.
Rev. 6.00 Aug 04, 2006 page 496 of 680
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ns
Figure 15.8
Section 15 Electrical Characteristics
15.5
H8/3847S Group Absolute Maximum Ratings
Table 15.17 lists the absolute maximum ratings.
Table 15.17 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Notes
V
*1
Power supply voltage
VCC
–0.3 to +4.3
Analog power supply voltage
AVCC
–0.3 to +4.3
V
Input voltage
Ports other than Port B,
C
Vin
–0.3 to VCC +0.3
V
Port B, C
AVin
–0.3 to AVCC +0.3
V
Topr
–20 to +75 (Regular
specifications)
°C
Operating temperature
–40 to +85 (wide-range
specifications)
+75 (products shipped as
2
chips)*
Storage temperature
Note:
Tstg
–55 to +125
°C
1. Permanent damage may occur to the chip if maximum ratings are exceeded. Normal
operation should be under the conditions specified in Electrical Characteristics.
Exceeding these values can result in incorrect operation and reduced reliability.
2. Power may be applied when the temperature is between –20 and +75°C.
Rev. 6.00 Aug 04, 2006 page 497 of 680
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Section 15 Electrical Characteristics
15.6
H8/3847S Group Electrical Characteristics
15.6.1
Power Supply Voltage and Operating Range
The power supply voltage and operating range are indicated by the shaded region in the figures.
1. Power supply voltage and oscillator frequency range
fW (kHz)
fosc (MHz)
38.4
10.0
32.768
4.0
2.0
1.8
2.7
3.6
1.8
VCC (V)
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Note:
fosc is the oscillator frequency. When external
clocks are used, fosc=1MHz is the minimum.
Rev. 6.00 Aug 04, 2006 page 498 of 680
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3.6
• All operating modes
Section 15 Electrical Characteristics
φ (MHz)
2. Power supply voltage and operating frequency range
5.0
19.2
2.0
16.384
1.0
(0.5)
1.8
2.7
3.6
9.6
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=1MHz.
φSUB (kHz)
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
8.192
4.8
4.096
φ (kHz)
1.8
3.6
625
VCC (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
250
15.625
(7.813)
1.8
2.7
3.6
VCC (V)
• Active (medium-speed) mode (except A/D converter)
• Sleep (medium-speed) mode (except A/D converter)
Note: Figures in parentheses are the minimum operating
frequency of a case external clocks are used.
When using an oscillator, the minimum operating
frequency is φ=15.625kHz.
3. Analog power supply voltage and A/D converter operating range
φ (kHz)
φ (MHz)
5.0
625
500
1.0
0.5
1.8
2.7
3.6
1.8
2.7
3.6
AVCC (V)
AVCC (V)
• Active (high-speed) mode
• Active (medium-speed) mode
• Sleep (high-speed) mode
• Sleep (medium-speed) mode
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Section 15 Electrical Characteristics
15.6.2
DC Characteristics
Table 15.18 lists the DC characteristics.
Table 15.18 DC Characteristics
Values
Item
Symbol Applicable Pins
Input
high
voltage
VIH
Input low VIL
voltage
Output
high
voltage
VOH
Min
Typ
Max
Unit Test Condition
0.9 VCC
—
VCC + 0.3
V
SI1, RXD31, RXD32, UD 0.8 VCC
—
VCC + 0.3
V
OSC1
0.9 VCC
—
VCC + 0.3
V
X1
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
TMIG, SCK1, SCK31,
SCK32, ADTRG
0.9 VCC
—
VCC + 0.3
V
P10 to P17, P20 to P27, 0.8 VCC
P30 to P37, P40 to P43,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
VCC + 0.3
V
PB0 to PB7,
PC0 to PC3
0.8 VCC
—
AVCC + 0.3
RES, WKP0 to WKP7,
IRQ0 to IRQ4, AEVL,
AEVH, TMIC, TMIF,
TMIG, SCK1, SCK31,
SCK32, ADTRG
–0.3
—
0.1 VCC
V
SI1, RXD31, RXD32, UD –0.3
—
0.2 VCC
V
OSC1
–0.3
—
0.1 VCC
V
X1
–0.3
—
0.1 VCC
V
P10 to P17, P20 to P27, –0.3
P30 to P37, P40 to P43,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3,
PB0 to PB7,
PC0 to PC3
—
0.2 VCC
V
P10 to P17, P20 to P27, VCC – 0.3
P30 to P37, P40 to P42,
P50 to P57, P60 to P67,
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
—
V
Rev. 6.00 Aug 04, 2006 page 500 of 680
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–IOH = 0.1 mA
Notes
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Output
low
voltage
VOL
output
leakage
current
| IIL |
Typ
Max
Unit Test Condition
P10 to P17, P40 to P42 —
Min
—
0.5
V
P50 to P57, P60 to P67, —
P70 to P77, P80 to P87,
P90 to P97, PA0 to PA3
—
0.5
IOL = 0.4 mA
P20 to P27, P30 to P37 —
—
0.5
IOL = 0.4 mA
RES,
—
OSC1, X1, P10 to P17,
P20 to P27, P30 to P37,
P40 to P43, P50 to P57,
P60 to P67, P70 to P77,
P80 to P87, P90 to P97,
PA0 to PA3
—
1.0
PB0 to PB7,
PC0 to PC3
—
1.0
—
µA
Notes
IOL = 0.4 mA
VIN = 0.5 V to
VCC – 0.5 V
VIN = 0.5 V to
AVCC – 0.5 V
Pull-up
MOS
current
–Ip
P10 to P17, P30 to P37, 10.0
P50 to P57, P60 to P67
—
300.0
µA
VCC = 3 V, VIN = 0 V
Input
capacitance
CIN
All input pins except
power supply
—
—
15.0
pF
f = 1 MHz, VIN =0 V,
Ta = 25°C
Active
mode
current
dissipation
IOPE1
VCC
—
0.4
*3
mA
Active (high-speed)
mode
VCC = 1.8 V,
fOSC = 2 MHz
—
1.4
*3
Active (high-speed)
mode
VCC = 3 V,
fOSC = 4 MHz
—
3.5
5.5
Active (high-speed)
mode
VCC = 3 V,
fOSC = 10 MHz
*1
*2
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Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Active
mode
current
dissipation
IOPE2
—
0.1
*3
Active (mediumspeed) mode
VCC = 1.8 V,
fOSC = 2 MHz
φOSC/128
—
0.3
*3
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 4 MHz
φOSC/128
—
0.7
1.6
Active (mediumspeed) mode
VCC = 3 V,
fOSC = 10 MHz
φOSC/128
—
0.2
*3
—
0.6
*3
VCC = 3 V,
fOSC = 4 MHz
—
1.4
2.9
VCC = 3 V,
fOSC = 10 MHz
—
8
*3
—
4
*3
VCC = 2.7 V,
LCD on 32 kHz crystal
oscillator
(φSUB = φW/8)
—
14
*3
VCC = 2.7 V,
LCD on 32 kHz crystal
oscillator
(φSUB = φW/2)
—
5.0
12
Sleep
mode
current
dissipation
ISLEEP
Subactive
mode
current
dissipation
ISUB
Subsleep
mode
current
dissipation
ISUBSP
VCC
VCC
VCC
VCC
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Unit Test Condition
mA
µA
µA
VCC = 1.8 V,
fOSC = 2 MHz
Notes
*1
*2
*1
*2
*1
VCC = 1.8 V,
LCD on 32 kHz crystal *2
oscillator
(φSUB = φW/2)
*1
VCC = 2.7 V, LCD on
*2
32 kHz crystal
oscillator (φSUB = φW/2)
Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Min
Typ
Max
Unit Test Condition
Notes
Watch
mode
current
dissipation
IWATCH
—
1.4
*3
µA
*1
*2
—
2.2
*3
VCC = 2.7 V,
Ta = 25°C
32 kHz crystal
oscillator
LCD not used
—
2.8
6
VCC = 2.7 V,
32 kHz crystal
oscillator
LCD not used
—
0.3
*3
—
0.5
*3
Stand-by ISTBY
mode
current
dissipation
VCC
VCC
µA
VCC = 1.8 V,
Ta = 25°C
32 kHz crystal
oscillator
LCD not used
32 kHz crystal
oscillator
not used
VCC = 1.8 V,
Ta = 25°C
*1
*2
32 kHz crystal
oscillator
not used
VCC = 2.7 V,
Ta = 25°C
—
1
5
RAM
VRAM
data
retaining
voltage
VCC
1.5
—
—
V
Except the above
Allowable IOL
output
low
current
(per pin)
All output pins
—
—
0.5
mA
Allowable ∑ IOL
output
low
current
(total)
All output pins
—
—
20.0
mA
Allowable –IOH
output
high
current
(per pin)
All output pins
—
—
0.2
mA
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Section 15 Electrical Characteristics
Values
Item
Symbol Applicable Pins
Allowable ∑ – IOH
output
high
current
(total)
All output pins
Min
Typ
Max
Unit Test Condition
—
—
10.0
mA
Notes
Notes: Connect the TEST pin to VSS.
1. Pin States during Current Dissipation Measurement.
RES Pin Internal State
Only CPU Operates
VCC
Mode
Active (high-speed)
mode
Active (mediumspeed) mode
Sleep mode
Subactive mode
Subsleep mode
VCC
VCC
VCC
Watch mode
VCC
Standby mode
VCC
Only timers operate
Only CPU Operates
Only timers operate,
CPU stops
Only time base
operates, CPU stops
CPU and timers both
stop
Other ConstantPins Voltage
Oscillator Pins
VCC
Halted
System clock oscillator:
Crystal
Subclock oscillator:
Pin X1 = GND
VCC
System clock oscillator:
VCC
Halted
crystal
VCC
Halted
Subclock oscillator:
crystal
VCC
Halted
VCC
Halted
2. Excludes current in pull-up MOS transistors and output buffers.
3. The maximum current consumption value (standard) is 1.1 × typ.
Rev. 6.00 Aug 04, 2006 page 504 of 680
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System clock oscillator:
crystal
Subclock oscillator:
Pin X1 = GND
Section 15 Electrical Characteristics
15.6.3
AC Characteristics
Table 15.19 lists the control signal timing, and tables 15.20 and 15.21 list the serial interface
timing.
Table 15.19 Control Signal Timing
Item
System clock
oscillation
frequency
Applicable
Symbol Pins
fOSC
OSC clock (φOSC) tOSC
cycle time
Values
Typ
Max
Unit
Test Condition
OSC1, OSC2 2
—
10
MHz
VCC = 2.7 V to 3.6 V
2
—
4
VCC = 1.8 V to 3.6 V
OSC1, OSC2 100
—
500
ns
(1000)
VCC = 2.7 V to 3.6 V
250
—
500
(1000)
VCC = 1.8 V to 3.6 V
System clock (φ) tcyc
cycle time
Min
2
—
128
tOSC
—
—
128
µs
Reference
Figure
Figure 15.1
*2
Subclock oscilla- fW
tion frequency
X1, X2
—
32.768 —
or
38.4
kHz
Watch clock (φW) tW
cycle time
X1, X2
—
30.5
or
26.0
—
µs
Figure 15.1
2
—
8
tW
*1
2
—
—
tcyc
OSC1, OSC2 —
20
45
µs
—
80
—
—
0.8
2
—
1.2
3
Subclock (φSUB)
cycle time
tsubcyc
Instruction cycle
time
Oscillation
trc
stabilization time
tsubcyc
Ceramic Oscillator
Parameters
VCC = 2.2 V to 3.6 V
Figure 15.10
Ceramic Oscillator
Parameters
Except the above
ms
Crystal Oscillator
Parameters
VCC = 2.7 V to 3.6 V
Crystal Oscillator
Parameters
VCC = 2.2 V to 3.6 V
Rev. 6.00 Aug 04, 2006 page 505 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Item
Applicable
Symbol Pins
Oscillation
trc
stabilization time
Values
Min
OSC1, OSC2 —
—
X1, X2
External clock
high width
tCPH
OSC1
X1
External clock
low width
External clock
rise time
External clock
fall time
tCPL
tCPr
tCPf
OSC1
Typ
Max
Unit
4.0
—
Crystal Oscillator
Parameters
Except the above
—
50
Except the above
—
—
2
—
4
—
s
40
—
—
100
—
—
—
15.26
or
13.02
—
µs
ns
Test Condition
Reference
Figure
Figure 15.10
VCC = 2.2 V to 3.6 V
Except the above
ns
VCC = 2.7 V to 3.6 V
Figure 15.1
VCC = 1.8 V to 3.6 V
40
—
—
100
—
—
X1
—
15.26
or
13.02
—
µs
OSC1
—
—
10
ns
VCC = 2.7 V to 3.6 V
Figure 15.1
VCC = 1.8 V to 3.6 V
VCC = 2.7 V to 3.6 V
Figure 15.1
VCC = 1.8 V to 3.6 V
—
—
25
X1
—
—
55.0
ns
OSC1
—
—
10
ns
Figure 15.1
VCC = 2.7 V to 3.6 V
Figure 15.1
—
—
25
X1
—
—
55.0
ns
Figure 15.1
10
—
—
tcyc
Figure 15.2
—
tcyc
Figure 15.3
Pin RES low
width
tREL
RES
Input pin high
width
tIH
IRQ0 to IRQ4, 2
WKP0 to
WKP7,
ADTRG,
TMIC
TMIF, TMIG,
AEVL, AEVH
—
Input pin low
width
tIL
IRQ0 to IRQ4, 2
WKP0 to
WKP7,
ADTRG,
TMIC, TMIF,
TMIG, AEVL,
AEVH
—
Rev. 6.00 Aug 04, 2006 page 506 of 680
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VCC = 1.8 V to 3.6 V
tsubcyc
—
tcyc
tsubcyc
Figure 15.3
Section 15 Electrical Characteristics
Item
Applicable
Symbol Pins
UD pin minimum tUDH
modulation width tUDL
UD
Values
Min
Typ
Max
Unit
4
—
—
tcyc
Test Condition
Reference
Figure
Figure 15.4
tsubcyc
Notes: 1. Selected with SA1 and SA0 of system clock control register 2 (SYSCR2).
2. Figures in parentheses are the maximum tOSC rate with external clock input.
Rev. 6.00 Aug 04, 2006 page 507 of 680
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Section 15 Electrical Characteristics
Table 15.20 Serial Interface (SCI1) Timing
Item
Applicable
Symbol Pins
Values
Min
Typ
Max
Unit Test Condition
Reference
Figure
Input clock cycle tScyc
SCK1
4
—
—
tcyc
Figure 15.5
Input clock high
width
tSCKH
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock low
width
tSCKL
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock rise
time
tSCKr
SCK1
—
—
80.0
ns
Figure 15.5
Input clock fall
time
tSCKf
SCK1
—
—
80.0
ns
Figure 15.5
Serial output
data delay time
tSOD
SO1
—
—
350.0
ns
Figure 15.5
Serial input data tSIS
setup time
SI1
400.0
—
—
ns
Figure 15.5
Serial input data tSIH
hold time
SI1
400.0
—
—
ns
Figure 15.5
Rev. 6.00 Aug 04, 2006 page 508 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Table 15.21 Serial Interface (SCI3-1, SCI3-2) Timing
Values
Item
Symbol Min
Typ
Max
Unit
Input clock
Asynchronous tScyc
4
—
—
tcyc or
cycle
Synchronous
6
—
—
tsubcyc
Reference
Test Conditions Figure
Figure 15.6
Input clock pulse width
tSCKW
0.4
—
0.6
tScyc
Figure 15.6
Transmit data delay time
(synchronous)
tTXD
—
—
1
tcyc or tsubcyc
Figure 15.7
Receive data setup time
(synchronous)
tRXS
400.0
—
—
ns
Figure 15.7
Receive data hold time
(synchronous)
tRXH
400.0
—
—
ns
Figure 15.7
Rev. 6.00 Aug 04, 2006 page 509 of 680
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Section 15 Electrical Characteristics
15.6.4
A/D Converter Characteristics
Table 15.22 shows the A/D converter characteristics.
Table 15.22 A/D Converter Characteristics
Item
Applicable
Symbol Pins
Values
Min Typ
Max
Unit
1.8
3.6
V
AVCC +
0.3
V
—
Test Condition
Notes
*1
Analog power AVCC
supply voltage
AVCC
Analog input
voltage
AVIN
AN0 to AN11 – 0.3 —
Analog power
AIOPE
AVCC
—
—
1.2
mA
supply current
AISTOP1
AVCC
—
600
—
µA
*2
Reference
value
*3
AVCC = 3.0 V
AISTOP2
AVCC
—
—
5
µA
Analog input
capacitance
CAIN
AN0 to AN11 —
—
15.0
pF
Allowable
signal source
impedance
RAIN
—
—
10.0
kΩ
Resolution
(data length)
—
—
10
bit
Nonlinearity
error
—
—
±3.5
LSB
—
—
±5.5
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
—
±7.5
Except the above
Quantization
error
—
—
±0.5
LSB
Absolute
accuracy
—
±2
±4
LSB
—
±2.5
±6
AVCC = 2.0 V to 3.6 V
VCC = 2.0 V to 3.6 V
—
±3
±8
Except the above
12.4
—
124
62
—
124
Conversion
time
µs
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
*4
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
*4
AVCC = 2.7 V to 3.6 V
VCC = 2.7 V to 3.6 V
Except the above
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. Conversion time: 62 µs
Rev. 6.00 Aug 04, 2006 page 510 of 680
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Section 15 Electrical Characteristics
15.6.5
LCD Characteristics
Table 15.23 shows the LCD characteristics.
Table 15.23 LCD Characteristics
Applicable Values
Item
Pins
Min
Typ
Max
Unit
Conditions
Segment driver VDS
drop voltage
SEG1 to
SEG40
—
—
0.6
V
Common driver VDC
drop voltage
COM1 to
COM4
—
—
0.3
V
*1
ID = 2 µA
V1 = 2.7 V to 3.6 V
*1
ID = 2 µA
V1 = 2.7 V to 3.6 V
1.5
3.5
7
MΩ
2.2
—
3.6
V
LCD power
supply splitresistance
Symbol
Test
RLCD
Liquid crystal VLCD
display voltage
V1
Notes
Between V1
and VSS
*2
Notes: 1. The voltage drop from power supply pins V1, V2, V3, and VSS to each segment pin or
common pin.
2. When the liquid crystal display voltage is supplied from an external power source,
ensure that the following relationship is maintained: V1 ≥ V2 ≥ V3 ≥ VSS.
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Section 15 Electrical Characteristics
Table 15.24 Segment External Expansion AC Characteristics
Applicable Values
Item
Symbol
Pins
Min
Typ Max
Test
Reference
Unit Conditions Figure
Clock high width
tCWH
CL1, CL2
800.0
—
—
ns
*
Figure 15.8
Clock low width
tCWL
CL2
800.0
—
—
ns
*
Figure 15.8
Clock setup time
tCSU
CL1, CL2
500.0
—
—
ns
*
Figure 15.8
Data setup time
tSU
DO
300.0
—
—
ns
*
Figure 15.8
Data retaining time tDH
DO
300.0
—
—
ns
*
Figure 15.8
M delay time
M
–1000.0
—
1000.0 ns
*
Figure 15.8
CL1, CL2
—
—
170.0
tDM
Clock rise/fall time tCT
Note:
*
When the frame frequency is set at 488 Hz to 30.5 Hz.
Rev. 6.00 Aug 04, 2006 page 512 of 680
REJ09B0145-0600
ns
Figure 15.8
Section 15 Electrical Characteristics
15.7
Absolute Maximum Ratings of H8/38347 Group and H8/38447
Group
Table 15.25 lists the absolute maximum ratings.
Table 15.25 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Note
Power supply voltage
VCC
–0.3 to +7.0
V
*1
CVCC
–0.3 to +4.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Input voltage
Other than ports B, C
Vin
–0.3 to VCC +0.3
V
Ports B, C
AVin
–0.3 to AVCC +0.3
V
2
*
°C
–20 to +75
(regular specifications)
2
–40 to +85*
(wide-range temperature
specifications)
3
+75* (chip shipment
specifications)
Operating temperature
Topr
Storage temperature
Tstg
–55 to +125
°C
Notes: 1. Permanent damage may result if maximum ratings are exceeded. Normal operation
should be under the conditions specified in Electrical Characteristics. Exceeding these
values can result in incorrect operation and reduced reliability.
2. The operating temperature ranges from –20°C to +75°C when programming or erasing
the flash memory.
3. The temperature range in which power may be applied to the device is –20 to +75°C.
Rev. 6.00 Aug 04, 2006 page 513 of 680
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Section 15 Electrical Characteristics
15.8
Electrical Characteristics of H8/38347 Group and H8/38447 Group
15.8.1
Power Supply Voltage and Operating Ranges
The power supply voltage and operating ranges (shaded portions) are shown below.
1. Power Supply Voltage and Oscillation Frequency Range
• H8/38347 Group
16.0
fosc (MHz)
fW (kHz)
38.4
32.768
2.0
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
2.7
5.5
VCC (V)
2.7
5.5
VCC (V)
• All operating modes
• H8/38447 Group
16.0
fW (kHz)
fosc (MHz)
38.4
10.0
32.768
2.0
2.7
4.5 5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
• All operating modes
Note: fosc is the oscillator frequency. When an external clock is used 1 MHz is the minimum
fosc value.
Rev. 6.00 Aug 04, 2006 page 514 of 680
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Section 15 Electrical Characteristics
2. Power Supply Voltage and Operating Frequency Range
• H8/38347 Group
8.0
19.2
φ (MHz)
16.384
1.0
(0.5)*1
2.7
5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
φSUB (kHz)
9.6
8.192
4.8
4.096
1000
φ (kHz)
2.7
5.5
VCC (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
15.625
(7.813)*2
2.7
5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
• H8/38447 Group
8.0
φ (MHz)
19.2
5.0
16.384
1.0
(0.5)*1
2.7
4.5 5.5
VCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode (except CPU)
φSUB (kHz)
9.6
8.192
4.8
4.096
1000
2.7
φ (kHz)
625
5.5
VCC (V)
• Subactive mode
• Subsleep mode (except CPU)
• Watch mode (except CPU)
15.625
(7.813)*2
2.7
4.5 5.5
VCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode (except A/D converter)
Notes 1. The figure in parentheses ( ) indicates the minimum operating frequency when an external clock is
used. When the resonator is used the minimum operating frequency (φ) is 1 MHz.
2. The figure in parentheses ( ) indicates the minimum operating frequency when an external clock is
used. When the resonator is used the minimum operating frequency (φ) is 15.625 kHz.
Rev. 6.00 Aug 04, 2006 page 515 of 680
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Section 15 Electrical Characteristics
3. Analog Power Supply Voltage and A/D Converter Operating Range
• H8/38347 Group
φ (kHz)
φ (MHz)
8.0
1.0
0.5
1000
500
2.7
2.7
5.5
AVCC (V)
5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
• Active (high-speed) mode
• Sleep (high-speed) mode
5.0
φ (kHz)
φ (MHz)
• H8/38447 Group
1.0
(0.5)
1000
625
500
2.7
5.5
AVCC (V)
• Active (high-speed) mode
• Sleep (high-speed) mode
Rev. 6.00 Aug 04, 2006 page 516 of 680
REJ09B0145-0600
2.7
4.5 5.5
AVCC (V)
• Active (medium-speed) mode
• Sleep (medium-speed) mode
Section 15 Electrical Characteristics
15.8.2
DC Characteristics
Table 15.26 lists the DC characteristics.
Table 15.26 DC Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Input high VIH
voltage
Applicable Pins
Min
RES,
WKP0 to WKP7,
IRQ0, to IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK1, SCK32,
SCK31
Typ
Max
Unit
Test Condition
VCC × 0.8 —
VCC + 0.3
V
VCC = 4.0 V to 5.5 V
VCC × 0.9 —
VCC + 0.3
RXD32, UD,
RXD31, SI1
VCC × 0.7 —
VCC + 0.3
VCC × 0.8 —
VCC + 0.3
OSC1
VCC × 0.8 —
VCC + 0.3
Notes
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
VCC × 0.9 —
VCC + 0.3
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P97,
PA0 to PA3
VCC × 0.7 —
VCC + 0.3
VCC × 0.8 —
VCC + 0.3
Other than above
PB0 to PB7,
PC0 to PC3
VCC × 0.7 —
AVCC + 0.3 V
VCC = 4.0 V to 5.5 V
VCC × 0.8 —
AVCC + 0.3
Other than above
EXCL
VCC × 0.9 —
VCC + 0.3
Other than above
V
VCC = 4.0 V to 5.5 V
V
Note: Connect the TEST pin to VSS.
Rev. 6.00 Aug 04, 2006 page 517 of 680
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Section 15 Electrical Characteristics
Values
Item
Symbol
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Input low
voltage
VIL
RES,
WKP0 to WKP7,
IRQ0, to IRQ4,
AEVL, AEVH,
TMIC, TMIF,
TMIG, ADTRG,
SCK1, SCK32,
SCK31
– 0.3
—
VCC × 0.2
V
VCC = 4.0 V to 5.5 V
– 0.3
—
VCC × 0.1
RXD32, UD,
RXD31, SI1
– 0.3
—
VCC × 0.3
– 0.3
—
VCC × 0.2
OSC1
– 0.3
—
VCC × 0.2
– 0.3
—
VCC × 0.1
EXCL
– 0.3
—
VCC × 0.1
V
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P43,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P97,
PA0 to PA3,
PB0 to PB7,
PC0 to PC3
– 0.3
—
VCC × 0.3
V
– 0.3
—
VCC × 0.2
P10, to P17,
P20 to P27,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P97,
PA0 to PA3
VCC – 1.0 —
Output
high
voltage
VOH
—
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
Other than above
VCC = 4.0 V to 5.5 V
Other than above
V
VCC = 4.0 V to 5.5 V
–IOH = 1.0 mA
VCC – 0.5 —
—
VCC = 4.0 V to 5.5 V
–IOH = 0.5 mA
VCC – 0.3 —
Rev. 6.00 Aug 04, 2006 page 518 of 680
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—
–IOH = 0.1 mA
Notes
Section 15 Electrical Characteristics
Values
Item
Symbol
Output low VOL
voltage
Applicable Pins
Min
Typ
Max
Unit
Test Condition
P10 to P17,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P97,
PA0 to PA3
—
—
0.6
V
VCC = 4.0 V to 5.5 V
—
—
0.5
IOL = 0.4 mA
P20 to P27,
P30 to P37
—
—
1.0
VCC = 4.0 V to 5.5 V
—
—
0.6
VCC = 4.0 V to 5.5 V
Notes
IOL = 1.6 mA
IOL = 10 mA
IOL = 1.6 mA
Input/
output
leakage
current
Pull-up
MOS
current
Input
capacitance
| IIL |
–Ip
Cin
—
—
0.5
RES, P43,
OSC1, X1,
P10 to P17,
P20 to P27,
P30 to P37,
P40 to P42,
P50 to P57,
P60 to P67,
P70 to P77,
P80 to P87,
P90 to P97,
PA0 to PA3
—
—
1.0
PB0 to PB7,
PC0 to PC3
—
—
1.0
P10 to P17,
P24*6,
P30 to P37,
P50 to P57,
P60 to P67
20
—
200
—
40
—
All input pins
except power
supply pin
—
—
15.0
IOL = 0.4 mA
µA
VIN = 0.5 V to VCC –
0.5 V
VIN = 0.5 V to AVCC
– 0.5 V
µA
VCC = 5.0 V,
VIN = 0.0 V
VCC = 2.7 V,
VIN = 0.0 V
pF
Reference
value
f = 1 MHz,
VIN = 0.0 V,
Ta = 25°C
Rev. 6.00 Aug 04, 2006 page 519 of 680
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Section 15 Electrical Characteristics
Values
Item
Symbol
Active
IOPE1
mode
current
consumption
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
VCC
—
0.8
—
mA
Active (high-speed)
mode
VCC = 2.7 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
1.2
—
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
1.0
—
—
1.5
—
—
2.0
—
—
2.4
—
—
4.0
7.0
—
4.9
7.0
Rev. 6.00 Aug 04, 2006 page 520 of 680
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Active (high-speed)
mode
VCC = 5 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Active (high-speed)
mode
VCC = 5 V,
fOSC = 4 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Active (high-speed)
mode
VCC = 5 V,
fOSC = 10 MHz
*1 *3 *4
*2 *3 *4
Section 15 Electrical Characteristics
Values
Item
Symbol
Active
IOPE2
mode
current
consumption
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
VCC
—
0.4
—
mA
Active (mediumspeed) mode
VCC = 2.7 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
0.7
—
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
0.5
—
—
1.0
—
—
0.8
—
—
1.2
—
—
1.2
3.0
—
1.7
3.0
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 2 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 4 MHz,
φOSC/128
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Active (mediumspeed) mode
VCC = 5 V,
fOSC = 10 MHz,
φOSC/128
*1 *3 *4
*2 *3 *4
Rev. 6.00 Aug 04, 2006 page 521 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Values
Item
Symbol
Sleep
ISLEEP
mode
current
consumption
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
VCC
—
0.5
—
mA
VCC = 2.7 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
—
0.8
—
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
Subactive ISUB
mode
current
consumption
VCC
—
0.7
—
—
1.2
—
—
1.1
—
—
1.6
—
—
1.9
5.0
—
2.6
5.0
—
12
—
—
15
—
—
18
50
—
30
50
Rev. 6.00 Aug 04, 2006 page 522 of 680
REJ09B0145-0600
VCC = 5 V,
fOSC = 2 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
VCC = 5 V,
fOSC = 4 MHz
*1 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
*2 *3 *4
Approx.
max. value
= 1.1 ×
Typ.
µA
VCC = 5 V,
fOSC = 10 MHz
*1 *3 *4
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/8)
*1 *3 *4
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
*2 *3 *4
Reference
value
*2 *3 *4
Reference
value
*1 *3 *4
*2 *3 *4
Section 15 Electrical Characteristics
Values
Item
Applicable Pins
Min
Typ
Max
Unit
Test Condition
Notes
Subsleep ISUBSP
mode
current
consumption
Symbol
VCC
—
3.8
16
µA
VCC = 2.7 V,
LCD on,
32-kHz crystal
resonator used
(φSUB = φW/2)
*3 *4
Watch
IWATCH
mode
current
consumption
VCC
—
1.8
—
µA
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator used,
LCD not used
Standby
ISTBY
mode
current
consumption
—
VCC
1.8
—
—
3.0
6.0
—
0.3
—
—
—
—
0.3
0.4
0.5
µA
—
Reference
value
*3 *4
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
*1 *3 *4
VCC = 5.0 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
*2 *3 *4
VCC = 2.7 V,
32-kHz crystal
resonator used,
LCD not used
VCC = 2.7 V,
Ta = 25°C,
32-kHz crystal
resonator not used
—
*1 *3 *4
Reference
value
Reference
value
*2 *3 *4
Reference
value
*1 *3 *4
Reference
value
*2 *3 *4
Reference
value
RAM data VRAM
retaining
voltage
VCC
—
1.0
5.0
2.0
—
—
32-kHz crystal
resonator not used
V
*3 *4
*5
Rev. 6.00 Aug 04, 2006 page 523 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Item
Symbol
Allowable output low
current (per pin)
IOL
Allowable output low
current (total)
∑IOL
Allowable output high –IOH
current (per pin)
Allowable output high ∑–IOH
current (total)
Applicable
Pins
Values
Min
Typ
Max
Unit
Output pins
—
except ports 2
and 3
—
2.0
mA
Ports 2 and 3
—
—
10.0
All pins
—
—
0.5
Output pins
—
except ports 2
and 3
—
40.0
Ports 2 and 3
—
—
80.0
All pins
—
—
20.0
All output pins —
—
2.0
—
—
0.2
All output pins —
—
15.0
—
—
10.0
Notes: Connect the TEST pin to VSS.
1. Applies to the mask-ROM version.
2. Applies to the F-ZTAT version.
Rev. 6.00 Aug 04, 2006 page 524 of 680
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Test
Condition
VCC = 4.0 V to
5.5 V
VCC = 4.0 V to
5.5 V
mA
VCC = 4.0 V to
5.5 V
VCC = 4.0 V to
5.5 V
mA
VCC = 4.0 V to
5.5 V
Other than
above
mA
VCC = 4.0 V to
5.5 V
Other than
above
Notes
Section 15 Electrical Characteristics
3. Pin states when current consumption is measured
Mode
RES Pin
Internal State
Other Pins
LCD Power
Supply
Oscillator Pins
Active (high-speed)
mode (IOPE1)
VCC
Only CPU operates
VCC
Stops
System clock:
crystal resonator
Subclock:
Pin X1 = GND
Active (mediumspeed) mode (IOPE2)
Sleep mode
VCC
Only all on-chip timers VCC
operate
Stops
Subactive mode
VCC
Only CPU operates
VCC
Stops
Subsleep mode
VCC
Only all on-chip timers VCC
operate
Stops
Subclock:
crystal resonator
CPU stops
Watch mode
VCC
Standby mode
VCC
Only clock time base
operates
System clock:
crystal resonator
VCC
Stops
VCC
Stops
CPU stops
CPU and timers
both stop
System clock:
crystal resonator
Subclock:
Pin X1 = GND
4. Except current which flows to the pull-up MOS or output buffer
5. Voltage maintained in standby mode
6. Applies to the F-ZTAT version. The specified values for this pin in reference values.
Rev. 6.00 Aug 04, 2006 page 525 of 680
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Section 15 Electrical Characteristics
15.8.3
AC Characteristics
Table 15.27 lists the control signal timing and table 15.28 and 15.29 list the serial interface timing.
Table 15.27 Control Signal Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
System clock
oscillation
frequency
fOSC
OSC clock (φOSC)
cycle time
tOSC
System clock (φ)
cycle time
Applicable
Pins
OSC1,
OSC2
OSC1,
OSC2
tcyc
Values
Min
Typ
Max
Unit
Test Condition
2.0
—
16.0
MHz
2.0
—
16.0
VCC = 4.5 to 5.5 V
2.0
—
10.0
VCC = 2.7 to 5.5 V
62.5
—
500
ns
(1000)
62.5
—
500
(1000)
VCC = 4.5 to 5.5 V
100
—
500
(1000)
VCC = 2.7 to 5.5 V
2
—
128
tOSC
—
—
128
µs
Reference
Figure
*3
*4
Figure
15.1*2 *3
Figure
15.1*2 *4
Subclock oscillation fW
frequency
X1, X2, EXCL —
32.768
or 38.4
—
kHz
Watch clock (φW)
cycle time
tW
X1, X2, EXCL —
30.5 or
26.0
—
µs
Figure
15.1
Subclock (φSUB)
cycle time
tsubcyc
2
—
4
tW
*1
2
—
—
tcyc
tsubcyc
—
20
45
µs
—
80
—
—
0.8
2
—
—
50
—
—
2.0
Instruction cycle
time
Oscillation
stabilization time
trc
trc
OSC1,
OSC2
X1, X2
Rev. 6.00 Aug 04, 2006 page 526 of 680
REJ09B0145-0600
Ceramic resonator Figure
(VCC = 3.0 to 5.5 V) 15.11
Ceramic resonator
other than above
ms
Crystal resonator
Other than above
s
Section 15 Electrical Characteristics
Item
Symbol
External clock high tCPH
width
External clock low
width
External clock rise
time
External clock fall
time
tCPL
tCPr
tCPf
Values
Applicable
Pins
Min
Typ
Max
Unit
OSC1
25
—
—
ns
25
—
—
—
Test Condition
Reference
Figure
Figure
15.1*3
VCC = 4.5 to 5.5 V
VCC = 2.7 to 5.5 V
Figure
15.1*4
40
—
EXCL
—
15.26 or —
13.02
µs
Figure
15.1
OSC1
25
—
—
ns
Figure
15.1*3
25
—
—
VCC = 4.5 to 5.5 V
40
—
—
VCC = 2.7 to 5.5 V
EXCL
—
15.26 or —
13.02
µs
Figure
15.1
OSC1
—
—
6
ns
Figure
15.1*3
—
—
6
VCC = 4.5 to 5.5 V
—
—
10
VCC = 2.7 to 5.5 V
EXCL
—
—
55.0
OSC1
—
—
6
—
—
6
VCC = 4.5 to 5.5 V
VCC = 2.7 to 5.5 V
Figure
15.1*4
Figure
15.1*4
Figure
15.1
ns
Figure
15.1*3
Figure
15.1*4
—
—
10
EXCL
—
—
55.0
10
—
—
tcyc
Figure
15.2
—
—
tcyc
tsubcyc
Figure
15.3
RES pin low
width
tREL
RES
Input pin high
width
tIH
2
IRQ00 to
IRQ04,
WKP0 to
WKP7,
ADTRG,
TMIC,
TMIF, TMIG,
AEVL, AEVH
Figure
15.1
Rev. 6.00 Aug 04, 2006 page 527 of 680
REJ09B0145-0600
Section 15 Electrical Characteristics
Item
Symbol
Input pin low
width
tIL
UD pin minimum
transition width
tUDH
tUDL
Applicable
Pins
Values
Min
Max
Unit
2
IRQ00 to
IRQ04,
WKP0 to
WKP7,
ADTRG,
TMIC,
TMIF, TMIG,
AEVL, AEVH
—
—
tcyc
tsubcyc
Figure
15.3
UD
—
—
tcyc
tsubcyc
Figure
15.4
4
Test Condition
Reference
Figure
Typ
Notes: 1. Determined by the SA1 and SA0 bits in the system control register 2 (SYSCR2).
2. The figure in parentheses ( ) indicates the maximum fosc value when an external clock
is used.
3. Also applies to H8/38347 Group.
4. Also applies to H8/38447 Group.
Table 15.28 Serial Interface (SCI1) Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V unless otherwise indicated
Item
Applicable
Symbol Pins
Values
Min
Typ
Max
Unit
Test Condition
Reference
Figure
Input clock cycle tScyc
SCK1
4
—
—
tcyc
Figure 15.5
Input clock high
width
tSCKH
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock low
width
tSCKL
SCK1
0.4
—
—
tScyc
Figure 15.5
Input clock rise
time
tSCKr
SCK1
—
—
60.0
ns
Figure 15.5*
Input clock fall
time
tSCKf
SCK1
—
—
60.0
ns
Figure 15.5*
Serial output
data delay time
tSOD
SO1
—
—
200.0
ns
Figure 15.5*
Serial input data tSIS
setup time
SI1
200.0
—
—
ns
Figure 15.5*
Serial input data tSIH
hold time
SI1
200.0
—
—
ns
Figure 15.5*
Rev. 6.00 Aug 04, 2006 page 528 of 680
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Section 15 Electrical Characteristics
Table 15.29
Serial Interface (SCI3) Timing
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Item
Symbol
Min
Typ Max Unit
Input clock Asynchronous
cycle
Clocked synchronous
tscyc
4
—
—
6
—
Input clock pulse width
tSCKW
0.4
—
Transmit data delay time
(clocked synchronous)
tTXD
—
Receive data setup time
(clocked synchronous)
tRXS
Receive data hold time
(clocked synchronous)
tRXH
Test
Condition
Reference
Figure
Figure 15.6
—
tcyc or
tsubcyc
0.6
tscyc
Figure 15.6
—
1
tcyc or
tsubcyc
Figure 15.7
200
—
—
ns
Figure 15.7
200
—
—
ns
Figure 15.7
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Section 15 Electrical Characteristics
15.8.4
A/D Converter Characteristics
Table 15.30 shows the A/D converter characteristics.
Table 15.30
A/D Converter Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Values
Applicable
Pins
Min
Typ
Max
Unit
Analog power supply AVCC
voltage
AVCC
2.7
—
5.5
V
Analog input voltage
AN0 to
AN11
– 0.3
—
AVCC + 0.3 V
Analog power supply AIOPE
current
AISTOP1
AVCC
—
—
1.5
mA
AVCC
—
600
—
µA
*2
Reference
value
AISTOP2
AVCC
—
—
5.0
µA
*3
Analog input
capacitance
CAIN
AN0 to
AN11
—
—
15.0
pF
Allowable signal
source impedance
RAIN
—
—
10.0
kΩ
Resolution (data
length)
—
—
10
bit
Nonlinearity error
—
—
±3.5
LSB
—
—
±7.5
Quantization error
—
—
±0.5
LSB
Absolute accuracy
—
±2.0
±4.0
LSB
—
±2.0
±8.0
7.8
—
124
12.4
—
124
Item
Symbol
AVIN
Conversion time
Test
Condition
Reference
Figure
*1
AVCC = 5.0 V
AVCC = 4.0 V
to 5.5 V
AVCC = 2.7 V
to 5.5 V
AVCC = 4.0 V
to 5.5 V
AVCC = 2.7 V
to 5.5 V
µs
*4
*5
Notes: 1. Set AVCC = VCC when the A/D converter is not used.
2. AISTOP1 is the current in active and sleep modes while the A/D converter is idle.
3. AISTOP2 is the current at reset and in standby, watch, subactive, and subsleep modes
while the A/D converter is idle.
4. Also applies to H8/38347 Group.
5. Also applies to H8/38447 Group.
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Section 15 Electrical Characteristics
15.8.5
LCD Characteristics
Table 15.31 shows the LCD characteristics.
Table 15.31 LCD Characteristics
VCC = 2.7 V to 5.5 V, AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, unless otherwise specified
Item
Symbol
Segment driver
step-down voltage
VDS
Common driver
step-down voltage
VDC
LCD power supply
split-resistance
RLCD
Liquid crystal
display voltage
VLCD
Applicable
Pins
Values
Reference
Figure
Min
Typ
Max
Unit
Test Condition
SEG1 to
SEG40
—
—
0.6
V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
COM1 to
COM4
—
—
0.3
V
*1
ID = 2 µA
V1 = 2.7 V to 5.5 V
1.5
3.0
7.0
MΩ
Between V1 and
VSS
2.7
—
5.5
V
V1
*2
Notes: 1. The voltage step-down from power supply pins V1, V2, V3, and VSS to each segment
pin or common pin.
2. When the liquid crystal display voltage is supplied from an external power supply,
ensure that the following relationship is maintained: V1 ≥ V2 ≥ V3 ≥ VSS.
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Section 15 Electrical Characteristics
15.8.6
Flash Memory Characteristics
Table 15.32
Flash Memory Characteristics
Condition:
AVCC = 2.7 V to 5.5 V, VSS = AVSS = 0.0 V, VCC = 2.7 V to 5.5 V (range of
operating voltage when reading), VCC = 3.0 V to 5.5 V (range of operating voltage
when programming/erasing), Ta = –20°C to +75°C (range of operating temperature
when programming/erasing: product with regular specifications, product with widerange temperature specifications)
Values
Item
Symbol
Min
Typ
Max
Unit
Programming time*1*2*4
Test
Conditions
tP
—
7
200
ms/128 bytes
Erase time*1*3*5
tE
—
100
1200
ms/block
Reprogramming count
NWEC
1000*8
10000*9 —
Data retain period
tDRP
10*10
—
—
year
Programming
Wait time after
SWE-bit setting*1
x
1
—
—
µs
Wait time after
PSU-bit setting*1
y
50
—
—
µs
Wait time after
P-bit setting*1*4
z1
28
30
32
µs
1≤n≤6
z2
198
200
202
µs
7 ≤ n ≤ 1000
z3
8
10
12
µs
Additional
programming
Wait time after
P-bit clear*1
α
5
—
—
µs
Wait time after
PSU-bit clear*1
β
5
—
—
µs
Wait time after
PV-bit setting*1
γ
4
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
PV-bit clear*1
η
2
—
—
µs
Wait time after
SWE-bit clear*1
θ
100
—
—
µs
Maximum
programming
count*1*4*5
N
—
—
1000
times
Rev. 6.00 Aug 04, 2006 page 532 of 680
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times
Section 15 Electrical Characteristics
Values
Item
Erase
Symbol
Min
Typ
Max
Unit
Wait time after
SWE-bit setting*1
x
1
—
—
µs
Wait time after
ESU-bit setting*1
y
100
—
—
µs
Wait time after
E-bit setting*1*6
z
10
—
100
ms
Wait time after
E-bit clear*1
α
10
—
—
µs
Wait time after
ESU-bit clear*1
β
10
—
—
µs
Wait time after
EV-bit setting*1
γ
20
—
—
µs
Wait time after
dummy write*1
ε
2
—
—
µs
Wait time after
EV-bit clear*1
η
4
—
—
µs
Wait time after
SWE-bit clear*1
θ
100
—
—
µs
Maximum erase
count*1*6*7
N
—
—
120
times
Test
Conditions
Notes: 1. Set the times according to the program/erase algorithms.
2. Programming time per 128 bytes (Shows the total period for which the P bit in FLMCR1
is set. It does not include the programming verification time.)
3. Block erase time (Shows the total period for which the E bit in FLMCR1 is set. It does
not include the erase verification time.)
4. Maximum programming time (tP (max))
tP (max) = Wait time after P-bit setting (z) × maximum number of writes (N)
5. The maximum number of writes (N) should be set according to the actual set value of
z1, z2, and z3 to allow programming within the maximum programming time (tP (max)).
The wait time after P-bit setting (z1 and z2) should be alternated according to the
number of writes (n) as follows:
1≤n≤6
z1 = 30 µs
7 ≤ n ≤ 1000 z2 = 200 µs
6. Maximum erase time (tE (max))
tE (max) = Wait time after E-bit setting (z) × maximum erase count (N)
7. The maximum number of erases (N) should be set according to the actual set value of z
to allow erasing within the maximum erase time (tE (max)).
8. This minimum value guarantees all characteristics after reprogramming (the guaranteed
range is from 1 to the minimum value).
9. Reference value when the temperature is 25°C (normally reprogramming will be
performed by this count).
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Section 15 Electrical Characteristics
10. This is a data retain characteristic when reprogramming is performed within the
specification range including this minimum value.
Rev. 6.00 Aug 04, 2006 page 534 of 680
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Section 15 Electrical Characteristics
15.9
Operation Timing
Figures 15.1 to 15.8 show timing diagrams.
t OSC , tw
OSC1
x1
EXCL
VIH
VIL
t CPH
t CPL
t CPr
t CPf
Figure 15.1 Clock Input Timing
RES
VIL
tREL
Figure 15.2 RES Low Width
IRQ0 to IRQ4,
WKP0 to WKP7,
ADTRG,
TMIC, TMIF,
TMIG, AEVL,
AEVH
VIH
VIL
t IL
t IH
Figure 15.3 Input Timing
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Section 15 Electrical Characteristics
VIH
UD
VIL
t UDL
t UDH
Figure 15.4 UD Pin Minimum Modulation Width Timing
tscyc
SCK1
VIH or VOH*
VIL or VOL*
tSCKL
tSCKH
tSCKf
tSCKr
tSOD
VOH*
VOL*
SO1
tSIS
tSIH
SI1
Note: * Output timing reference levels
Output high level
VOH = 1/2 VCC + 0.2 V
Output low level
VOL = 0.8 V
See figure 15.9 for the load conditions.
Figure 15.5 SCI1 Input/Output Timing
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Section 15 Electrical Characteristics
t SCKW
SCK 31
SCK 32
t scyc
Figure 15.6 SCK3 Input Clock Timing
t scyc
SCK 31 VIH or VOH *
SCK 32 VIL or VOL *
t TXD
TXD31
TXD32
(transmit data)
*
VOH
VOL
*
t RXS
t RXH
RXD31
RXD32
(receive data)
Note: * Output timing reference levels
Output high
VOH = 1/2 VCC + 0.2 V
Output low
VOL = 0.8 V
Load conditions are shown in figure 15.9.
Figure 15.7 SCI3 Synchronous Mode Input/Output Timing
Rev. 6.00 Aug 04, 2006 page 537 of 680
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Section 15 Electrical Characteristics
tCT
VCC − 0.5 V
CL1
0.4 V
tCWH
tCWH
tCSU
VCC − 0.5 V
CL2
0.4 V
tCSU
tCWL
tCT
VCC − 0.5 V
0.4 V
DO
tSU
M
tDH
0.4 V
tDM
Figure 15.8 Segment Expansion Signal Timing
Rev. 6.00 Aug 04, 2006 page 538 of 680
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Section 15 Electrical Characteristics
15.10
Output Load Circuit
VCC
2.4 kΩ
Output pin
30 pF
12 k Ω
Figure 15.9 Output Load Condition
Rev. 6.00 Aug 04, 2006 page 539 of 680
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Section 15 Electrical Characteristics
15.11
Resonator
LS
CS
RS
OSC1
OSC2
CO
Ceramic Oscillator Parameters
Manufacturer Products Name
Frequency 4 MHz
RS
Manufacturer's Publicly Released Values MURATA
CSTLS
Max. 8.8 ½
4M00G
53/56
CO
Max. 36 pF
Crystal Oscillator Parameters
Manufacturer Products Name
Frequency 4.193 MHz
RS
Manufacturer's Publicly Released Values Nihon Denpa NR-18
Max. 100 ½
Kogyo
Max. 16 pF
CO
Figure 15.10 Resonator Equivalent Circuit
Crystal resonator
Resonating Frequency
Manufacturer
Model
C1, C2
4 MHz
Nihon Denpa Kogyo
NR-18
12pF ± 20%
Resonating Frequency
Manufacturer
Model
C1, C2
2 MHz
MURATA
CSTCC2M00G53-B0
15pF ± 20%
CSTCC2M00G56-B0
47pF ± 20%
CSTLS4M00G53-B0
15pF ± 20%
CSTLS4M00G56-B0
47pF ± 20%
CSTLS10M0G53-B0
15pF ± 20%
CSTLS10M0G56-B0
47pF ± 20%
10 MHz
Ceramic resonator
4 MHz
10 MHz
Figure 15.11 Recommended Resonators
Rev. 6.00 Aug 04, 2006 page 540 of 680
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Section 15 Electrical Characteristics
15.12
Usage Note
Each of the products covered in this manual satisfy the electrical characteristics indicated.
However, the actual electrical characteristics, operating margin and noise margin may differ from
the indicated values due to differences in the manufacturing process, built-in ROM, layout pattern
and other factors.
If a system evaluation test is conducted with the ZTAT or F-ZTAT version, when switching to a
mask ROM version, perform the same evaluation test with the mask ROM version.
Rev. 6.00 Aug 04, 2006 page 541 of 680
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Section 15 Electrical Characteristics
Rev. 6.00 Aug 04, 2006 page 542 of 680
REJ09B0145-0600
Appendix A CPU Instruction Set
Appendix A CPU Instruction Set
A.1
Instructions
Operation Notation
Rd8/16
Rs8/16
Rn8/16
CCR
N
Z
V
C
PC
SP
#xx: 3/8/16
d: 8/16
@aa: 8/16
+
–
×
÷
∧
∨
⊕
→
—
General register (destination) (8 or 16 bits)
General register (source) (8 or 16 bits)
General register (8 or 16 bits)
Condition code register
N (negative) flag in CCR
Z (zero) flag in CCR
V (overflow) flag in CCR
C (carry) flag in CCR
Program counter
Stack pointer
Immediate data (3, 8, or 16 bits)
Displacement (8 or 16 bits)
Absolute address (8 or 16 bits)
Addition
Subtraction
Multiplication
Division
Logical AND
Logical OR
Exclusive logical OR
Move
Logical complement
Condition Code Notation
↔
Symbol
Modified according to the instruction result
*
Not fixed (value not guaranteed)
0
Always cleared to 0
—
Not affected by the instruction execution result
Rev. 6.00 Aug 04, 2006 page 543 of 680
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Appendix A CPU Instruction Set
Table A.1 lists the H8/300L CPU instruction set.
Table A.1
Instruction Set
4
2
— —
— —
4
— —
2
— —
W #xx:16 → Rd
MOV.W Rs, Rd
W Rs16 → Rd16
MOV.W @Rs, Rd
W @Rs16 → Rd16
MOV.W @(d:16, Rs),
Rd
W @(d:16, Rs16) → Rd16
MOV.W @Rs+, Rd
W @Rs16 → Rd16
Rs16+2 → Rs16
MOV.W @aa:16, Rd
W @aa:16 → Rd16
MOV.W Rs, @Rd
W Rs16 → @Rd16
MOV.W Rs, @(d:16,
Rd)
W Rs16 → @(d:16, Rd16)
MOV.W Rs, @–Rd
W Rd16–2 → Rd16
Rs16 → @Rd16
MOV.W Rs, @aa:16
W Rs16 → @aa:16
POP Rd
W @SP → Rd16
SP+2 → SP
2
— —
PUSH Rs
W SP–2 → SP
Rs16 → @SP
2
— —
Rev. 6.00 Aug 04, 2006 page 544 of 680
REJ09B0145-0600
4
— —
2
— —
2
— —
4
— —
2
— —
4
2
— —
— —
4
— —
2
— —
4
— —
↔
MOV.W #xx:16, Rd
↔ ↔
— —
↔
— —
4
↔ ↔ ↔
2
B Rs8 → @aa:16
↔
B Rs8 → @aa:8
MOV.B Rs, @aa:16
↔ ↔ ↔ ↔ ↔ ↔
MOV.B Rs, @aa:8
No. of States
Implied
@@aa
@aa: 8/16
@(d:8, PC)
@(d:16, Rn)
B Rd16–1 → Rd16
Rs8 → @Rd16
@–Rn/@Rn+
MOV.B Rs, @–Rd
@Rn
B Rs8 → @(d:16, Rd16)
#xx: 8/16
MOV.B Rs, @(d:16,
Rd)
Rn
B Rs8 → @Rd16
— —
0 — 4
0 — 6
0 — 4
0 — 6
0 — 6
0 — 6
0 — 6
↔
B @aa:16 → Rd8
MOV.B Rs, @Rd
2
0 — 6
↔ ↔
MOV.B @aa:16, Rd
— —
↔
B @aa:8 → Rd8
2
↔ ↔ ↔
MOV.B @aa:8, Rd
— —
↔
B @Rs16 → Rd8
Rs16+1 → Rs16
4
↔ ↔ ↔ ↔ ↔ ↔
MOV.B @Rs+, Rd
— —
0 — 2
↔
B @(d:16, Rs16)→ Rd8
2
↔
MOV.B @(d:16, Rs),
Rd
— —
↔ ↔ ↔ ↔
B @Rs16 → Rd8
— —
2
↔ ↔ ↔ ↔
MOV.B @Rs, Rd
2
↔
B Rs8 → Rd8
H N Z V C
↔
B #xx:8 → Rd8
MOV.B Rs, Rd
I
↔ ↔ ↔ ↔
MOV.B #xx:8, Rd
Operation
↔ ↔ ↔ ↔
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
0 — 6
0 — 2
0 — 4
0 — 6
0 — 6
0 — 4
0 — 6
0 — 6
0 — 4
0 — 2
0 — 4
0 — 6
0 — 4
0 — 6
0 — 6
Appendix A CPU Instruction Set
W Rd16+Rs16 → Rd16
2
— (1)
ADDX.B #xx:8, Rd
B Rd8+#xx:8 +C → Rd8
↔ ↔ ↔
↔ ↔
—
↔ ↔ ↔ ↔ ↔
2
↔ ↔
—
H N Z
(2)
V C
No. of States
ADD.W Rs, Rd
@(d:8, PC)
@@aa
Implied
—
2
@Rn
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
2
#xx: 8/16
B Rd8+Rs8 → Rd8
Rn
B Rd8+#xx:8 → Rd8
ADD.B Rs, Rd
I
↔ ↔ ↔ ↔ ↔
ADD.B #xx:8, Rd
Operation
↔ ↔ ↔ ↔ ↔
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
2
2
2
2
—
2
— — — — — — 2
ADDS.W #2, Rd
W Rd16+2 → Rd16
2
— — — — — — 2
INC.B Rd
B Rd8+1 → Rd8
2
— —
DAA.B Rd
B Rd8 decimal adjust → Rd8
2
— *
SUB.B Rs, Rd
B Rd8–Rs8 → Rd8
2
—
(2)
2
— 2
* (3) 2
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
↔
2
W Rd16+1 → Rd16
↔
B Rd8+Rs8 +C → Rd8
ADDS.W #1, Rd
↔ ↔ ↔ ↔ ↔ ↔
ADDX.B Rs, Rd
2
B Rd8–#xx:8 –C → Rd8
SUBX.B Rs, Rd
B Rd8–Rs8 –C → Rd8
2
—
SUBS.W #1, Rd
W Rd16–1 → Rd16
2
— — — — — — 2
SUBS.W #2, Rd
W Rd16–2 → Rd16
2
— — — — — — 2
DEC.B Rd
B Rd8–1 → Rd8
2
— —
DAS.B Rd
B Rd8 decimal adjust → Rd8
2
— *
NEG.B Rd
B 0–Rd → Rd
2
—
CMP.B #xx:8, Rd
B Rd8–#xx:8
CMP.B Rs, Rd
B Rd8–Rs8
2
—
CMP.W Rs, Rd
W Rd16–Rs16
2
— (1)
MULXU.B Rs, Rd
B Rd8 × Rs8 → Rd16
2
— — — — — — 14
DIVXU.B Rs, Rd
B Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
2
— — (5) (6) — — 14
AND.B #xx:8, Rd
B Rd8∧#xx:8 → Rd8
— —
— —
2
2
— —
— —
XOR.B Rs, Rd
B Rd8⊕Rs8 → Rd8
2
— —
NOT.B Rd
B Rd → Rd
2
— —
2
2
— 2
↔ ↔ ↔ ↔
B Rd8⊕#xx:8 → Rd8
2
2
2
* — 2
↔ ↔ ↔ ↔
XOR.B #xx:8, Rd
— —
(2)
↔ ↔ ↔ ↔ ↔ ↔ ↔
B Rd8∨Rs8 → Rd8
2
↔ ↔ ↔ ↔ ↔ ↔ ↔
OR.B Rs, Rd
—
(2)
↔ ↔ ↔ ↔ ↔ ↔
B Rd8∨#xx:8 → Rd8
2
↔ ↔ ↔
B Rd8∧Rs8 → Rd8
OR.B #xx:8, Rd
— (1)
—
↔ ↔
AND.B Rs, Rd
2
2
↔
W Rd16–Rs16 → Rd16
SUBX.B #xx:8, Rd
↔ ↔ ↔ ↔ ↔ ↔
SUB.W Rs, Rd
2
2
2
2
0
— 2
0
— 2
0
— 2
0
— 2
0
— 2
0
— 2
0
— 2
Rev. 6.00 Aug 04, 2006 page 545 of 680
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Appendix A CPU Instruction Set
0
Implied
@@aa
@aa: 8/16
@(d:8, PC)
@(d:16, Rn)
@–Rn/@Rn+
@Rn
#xx: 8/16
Rn
No. of States
2
↔
— —
2
↔
2
0
2
↔
— —
↔
2
0
2
2
b0
C
b0
C
b0
C
↔
B
b0
BSET #xx:3, Rd
B (#xx:3 of Rd8) ← 1
BSET #xx:3, @Rd
B (#xx:3 of @Rd16) ← 1
BSET #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 1
BSET Rn, Rd
B (Rn8 of Rd8) ← 1
BSET Rn, @Rd
B (Rn8 of @Rd16) ← 1
BSET Rn, @aa:8
B (Rn8 of @aa:8) ← 1
BCLR #xx:3, Rd
B (#xx:3 of Rd8) ← 0
BCLR #xx:3, @Rd
B (#xx:3 of @Rd16) ← 0
BCLR #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 0
BCLR Rn, Rd
B (Rn8 of Rd8) ← 0
Rev. 6.00 Aug 04, 2006 page 546 of 680
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↔
C
b7
↔
b0
b7
ROTR.B Rd
— —
↔
C
B
B
2
0
↔
0
b7
ROTL.B Rd
— —
2
b0
b7
ROTXR.B Rd
2
0
↔
0
↔
B
— — 0
↔
C
b7
ROTXL.B Rd
2
0
↔
B
— —
2
b0
b7
SHLR.B Rd
2
↔
B
0
↔
C
↔
SHLL.B Rd
— —
↔
B
b7
2
2
b0
↔
SHAR.B Rd
— —
↔
b7
2
↔
0
↔
C
H N Z V C
↔
B
I
↔
SHAL.B Rd
Operation
↔
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
2
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 8
— — — — — — 2
Appendix A CPU Instruction Set
BCLR Rn, @Rd
B (Rn8 of @Rd16) ← 0
BCLR Rn, @aa:8
B (Rn8 of @aa:8) ← 0
BNOT #xx:3, Rd
B (#xx:3 of Rd8) ←
(#xx:3 of Rd8)
BNOT #xx:3, @Rd
B (#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
BNOT #xx:3, @aa:8
B (#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
BNOT Rn, Rd
B (Rn8 of Rd8) ←
(Rn8 of Rd8)
BNOT Rn, @Rd
B (Rn8 of @Rd16) ←
(Rn8 of @Rd16)
BNOT Rn, @aa:8
B (Rn8 of @aa:8) ←
(Rn8 of @aa:8)
B (#xx:3 of Rd8) → Z
BTST #xx:3, @Rd
B (#xx:3 of @Rd16) → Z
BTST #xx:3, @aa:8
B (#xx:3 of @aa:8) → Z
BTST Rn, Rd
B (Rn8 of Rd8) → Z
BTST Rn, @Rd
B (Rn8 of @Rd16) → Z
BTST Rn, @aa:8
B (Rn8 of @aa:8) → Z
B (#xx:3 of Rd8) → C
BLD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BLD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BILD #xx:3, Rd
B (#xx:3 of Rd8) → C
BILD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BILD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BST #xx:3, Rd
B C → (#xx:3 of Rd8)
BST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BIST #xx:3, Rd
B C → (#xx:3 of Rd8)
B C → (#xx:3 of @Rd16)
BIST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
No. of States
Implied
@@aa
@aa: 8/16
@(d:16, Rn)
@–Rn/@Rn+
@Rn
@(d:8, PC)
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — —
4
— — —
4
2
— — —
— — —
4
— — —
4
2
— — —
— — 2
— — 6
— — 6
— — 2
— — 6
— — 6
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
— — — — —
2
6
6
2
6
6
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — —
4
— — — — —
4
— — — — —
↔ ↔ ↔
BIST #xx:3, @Rd
H N Z V C
↔ ↔ ↔ ↔ ↔ ↔
BLD #xx:3, Rd
4
I
↔ ↔ ↔ ↔ ↔ ↔
BTST #xx:3, Rd
#xx: 8/16
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
2
6
6
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Appendix A CPU Instruction Set
B C∧(#xx:3 of Rd8) → C
BIAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BIAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BIOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BIOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BIOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
BXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BIXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
H N Z V C
— — — — —
4
— — — — —
4
— — — — —
2
— — — — —
4
— — — — —
4
— — — — —
2
— — — — —
4
— — — — —
4
— — — — —
2
— — — — —
4
— — — — —
4
— — — — —
2
— — — — —
No. of States
Implied
@@aa
@aa: 8/16
@(d:8, PC)
@(d:16, Rn)
@–Rn/@Rn+
2
I
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BIAND #xx:3, Rd
@Rn
#xx: 8/16
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
2
6
6
2
6
6
2
6
6
2
6
6
2
BIXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BIXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BRA d:8 (BT d:8)
— PC ← PC+d:8
BRN d:8 (BF d:8)
— PC ← PC+2
BHI d:8
— If condition
C∨Z=0
BLS d:8
— is true then
C∨Z=1
2
— — — — — — 4
BCC d:8 (BHS d:8)
— PC ← PC+d:8 C = 0
2
— — — — — — 4
BCS d:8 (BLO d:8)
— else next;
C=1
2
— — — — — — 4
BNE d:8
—
Z=0
2
— — — — — — 4
BEQ d:8
—
Z=1
2
— — — — — — 4
— — — — — — 4
4
— — — — —
4
— — — — —
6
6
2
— — — — — — 4
2
— — — — — — 4
2
— — — — — — 4
BVC d:8
—
V=0
2
BVS d:8
—
V=1
2
— — — — — — 4
BPL d:8
—
N=0
2
— — — — — — 4
BMI d:8
—
N=1
2
— — — — — — 4
BGE d:8
—
N⊕V = 0
2
— — — — — — 4
BLT d:8
—
N⊕V = 1
2
— — — — — — 4
BGT d:8
—
Z ∨ (N⊕V) = 0
2
— — — — — — 4
BLE d:8
—
Z ∨ (N⊕V) = 1
2
— — — — — — 4
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Appendix A CPU Instruction Set
JMP @Rn
— PC ← Rn16
JMP @aa:16
— PC ← aa:16
JMP @@aa:8
— PC ← @aa:8
BSR d:8
— SP–2 → SP
PC → @SP
PC ← PC+d:8
JSR @Rn
— SP–2 → SP
PC → @SP
PC ← Rn16
JSR @aa:16
— SP–2 → SP
PC → @SP
PC ← aa:16
JSR @@aa:8
2
H N Z V C
— — — — — — 4
4
— — — — — — 6
2
— — — — — — 8
2
— — — — — — 6
2
— — — — — — 6
4
SP–2 → SP
PC → @SP
PC ← @aa:8
I
No. of States
Implied
@@aa
@aa: 8/16
@(d:8, PC)
@(d:16, Rn)
@–Rn/@Rn+
@Rn
#xx: 8/16
Operation
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length (bytes) Condition Code
— — — — — — 8
2
— — — — — — 8
SLEEP
— Transit to sleep mode.
2 — — — — — — 2
↔
2
↔
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
↔
RTE
↔
2 — — — — — — 8
↔
— PC ← @SP
SP+2 → SP
↔
RTS
1
0
B CCR → Rd8
2
— — — — — — 2
↔ ↔
↔ ↔
STC CCR, Rd
↔ ↔
2
2
↔ ↔
B Rs8 → CCR
↔ ↔
B #xx:8 → CCR
LDC Rs, CCR
↔ ↔
LDC #xx:8, CCR
2
2
2
NOP
— PC ← PC+2
2 — — — — — — 2
EEPMOV
— if R4L≠0
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next;
4 — — — — — — (4)
↔ ↔ ↔
B CCR⊕#xx:8 → CCR
↔ ↔ ↔
XORC #xx:8, CCR
↔ ↔ ↔
2
↔ ↔ ↔
2
B CCR∨#xx:8 → CCR
↔ ↔ ↔
B CCR∧#xx:8 → CCR
ORC #xx:8, CCR
↔ ↔ ↔
ANDC #xx:8, CCR
2
2
2
Notes: (1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
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Appendix A CPU Instruction Set
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains value prior to
arithmetic operation.
(4) The number of states required for execution is 4n + 9 in the H8/3847R Group and 4n +
8 in the H8/3847S Group, H8/38347 Group and H8/38447 Group (n = value of R4L).
(5) Set to 1 if the divisor is negative; otherwise cleared to 0.
(6) Set to 1 if the divisor is zero; otherwise cleared to 0.
Rev. 6.00 Aug 04, 2006 page 550 of 680
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Appendix A CPU Instruction Set
A.2
Operation Code Map
Table A.2 is an operation code map. It shows the operation codes contained in the first byte of the
instruction code (bits 15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
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XOR
AND
MOV
D
E
F
Note: * The PUSH and POP instructions are identical in machine language to MOV instructions.
OR
C
BILD
8
BVC
SUBX
BIAND
BAND
BIST
BLD
BST
BEQ
MOV
NEG
NOT
LDC
7
B
BIXOR
BXOR
RTE
BNE
AND
ANDC
6
CMP
BIOR
BOR
BSR
BCS
XOR
XORC
5
A
BTST
RTS
BCC
OR
ORC
4
ADDX
BCLR
BLS
ROTR
ROTXR
LDC
3
9
BNOT
BHI
ROTL
ROTXL
STC
2
ADD
BSET
DIVXU
BRN
SHAR
SHLR
SLEEP
1
8
7
6
MULXU
5
SHAL
SHLL
NOP
0
BRA
Low
4
3
2
1
0
High
Table A.2 Operation Code Map
SUB
ADD
MOV
BVS
9
JMP
BPL
DEC
INC
A
C
CMP
MOV
BLT
D
JSR
BGT
SUBX
ADDX
E
Bit-manipulation instructions
BGE
MOV *
EEPMOV
BMI
SUBS
ADDS
B
BLE
DAS
DAA
F
Appendix A CPU Instruction Set
Appendix A CPU Instruction Set
A.3
Number of Execution States
The tables here can be used to calculate the number of states required for instruction execution.
Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
SI = 2, SL = 2
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1, L = M = N = 0
From table A.3:
SI = SJ = SK = 2
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
Rev. 6.00 Aug 04, 2006 page 553 of 680
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Appendix A CPU Instruction Set
Table A.3
Number of Cycles in Each Instruction
Execution Status
Access Location
(instruction cycle)
On-Chip Memory
On-Chip Peripheral Module
2
—
Instruction fetch
SI
Branch address read
SJ
Stack operation
SK
Byte data access
SL
2 or 3*
Word data access
SM
—
Internal operation
SN
Note:
*
1
Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data
Access for details.
Rev. 6.00 Aug 04, 2006 page 554 of 680
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Appendix A CPU Instruction Set
Table A.4
Number of Cycles in Each Instruction
Instruction
Fetch
I
Instruction
Mnemonic
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W Rs, Rd
1
ADDS.W #1, Rd
1
ADDS.W #2, Rd
1
ADDX.B #xx:8, Rd
1
ADDX.B Rs, Rd
1
ADDS
ADDX
AND
ANDC
BAND
Bcc
BCLR
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
ANDC #xx:8, CCR
1
Branch
Stack
Byte Data Word Data Internal
Addr. Read Operation Access
Access
Operation
J
K
L
M
N
BAND #xx:3, Rd
1
BAND #xx:3, @Rd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
BLT d:8
2
BGT d:8
2
BLE d:8
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @Rd
2
2
BCLR #xx:3, @aa: 8
2
2
BCLR Rn, Rd
1
BCLR Rn, @Rd
2
2
BCLR Rn, @aa:8
2
2
Rev. 6.00 Aug 04, 2006 page 555 of 680
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Appendix A CPU Instruction Set
Instruction
Mnemonic
Instruction
Fetch
I
BIAND
BIAND #xx:3, Rd
1
BILD
BIOR
BIST
BIXOR
BLD
BNOT
BOR
BSET
BSR
BST
Branch
Stack
Byte Data Word Data Internal
Addr. Read Operation Access
Access
Operation
J
K
L
M
N
BIAND #xx:3, @Rd
2
1
BIAND #xx:3, @aa:8
2
1
BILD #xx:3, Rd
1
BILD #xx:3, @Rd
2
1
BILD #xx:3, @aa:8
2
1
BIOR #xx:3, Rd
1
BIOR #xx:3, @Rd
2
1
BIOR #xx:3, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @Rd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @Rd
2
1
BIXOR #xx:3, @aa:8
2
1
BLD #xx:3, Rd
1
BLD #xx:3, @Rd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @Rd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @Rd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @Rd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @Rd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @Rd
2
BSET Rn, @aa:8
2
BSR d:8
2
2
2
1
BST #xx:3, Rd
1
BST #xx:3, @Rd
2
2
BST #xx:3, @aa:8
2
2
Rev. 6.00 Aug 04, 2006 page 556 of 680
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Appendix A CPU Instruction Set
Instruction
BTST
Mnemonic
Instruction
Fetch
I
Branch
Stack
Byte Data Word Data Internal
Addr. Read Operation Access
Access
Operation
J
K
L
M
N
BTST #xx:3, Rd
1
BTST #xx:3, @Rd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @Rd
2
1
BTST Rn, @aa:8
2
1
BXOR #xx:3, Rd
1
BXOR #xx:3, @Rd
2
1
BXOR #xx:3, @aa:8
2
1
CMP. B #xx:8, Rd
1
CMP. B Rs, Rd
1
CMP.W Rs, Rd
1
DAA
DAA.B Rd
1
DAS
DAS.B Rd
1
DEC
DEC.B Rd
1
DIVXU
DIVXU.B Rs, Rd
1
EEPMOV
EEPMOV
2
INC
INC.B Rd
1
JMP
JMP @Rn
2
BXOR
CMP
JSR
LDC
MOV
JMP @aa:16
2
JMP @@aa:8
2
JSR @Rn
2
JSR @aa:16
2
JSR @@aa:8
2
LDC #xx:8, CCR
1
LDC Rs, CCR
1
2n+2*1
12
1*2
2
1
2
1
1
1
2
1
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @Rs, Rd
1
1
MOV.B @(d:16, Rs),
Rd
2
1
MOV.B @Rs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B Rs, @Rd
1
1
2
Rev. 6.00 Aug 04, 2006 page 557 of 680
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Appendix A CPU Instruction Set
Instruction
MOV
Mnemonic
Instruction
Fetch
I
Branch
Stack
Byte Data Word Data Internal
Addr. Read Operation Access
Access
Operation
J
K
L
M
N
MOV.B Rs, @(d:16,
Rd)
2
1
MOV.B Rs, @–Rd
1
1
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.W #xx:16, Rd
2
2
MOV.W Rs, Rd
1
MOV.W @Rs, Rd
1
1
MOV.W @(d:16, Rs),
Rd
2
1
MOV.W @Rs+, Rd
1
1
MOV.W @aa:16, Rd
2
1
MOV.W Rs, @Rd
1
1
MOV.W Rs, @(d:16,
Rd)
2
1
MOV.W Rs, @–Rd
1
1
1
MOV.W Rs, @aa:16
2
MULXU
MULXU.B Rs, Rd
1
NEG
NEG.B Rd
1
NOP
NOP
1
NOT
NOT.B Rd
1
OR
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
2
2
12
ORC
ORC #xx:8, CCR
1
ROTL
ROTL.B Rd
1
ROTR
ROTR.B Rd
1
ROTXL
ROTXL.B Rd
1
ROTXR
ROTXR.B Rd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAR
SHAR.B Rd
1
SHLL
SHLL.B Rd
1
SHLR
SHLR.B Rd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
Rev. 6.00 Aug 04, 2006 page 558 of 680
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Appendix A CPU Instruction Set
Instruction
Mnemonic
Instruction
Fetch
I
SUB
SUB.B Rs, Rd
1
SUB.W Rs, Rd
1
SUBS
SUBS.W #1, Rd
1
SUBS.W #2, Rd
1
Branch
Stack
Byte Data Word Data Internal
Addr. Read Operation Access
Access
Operation
J
K
L
M
N
POP
POP Rd
1
1
2
PUSH
PUSH Rs
1
1
2
SUBX
SUBX.B #xx:8, Rd
1
XOR
XORC
SUBX.B Rs, Rd
1
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XORC #xx:8, CCR
1
Notes: 1. n: Initial value in R4L. The source and destination operands are accessed n + 1 times
each.
2. 1 in the H8/3847R Group and 0 in the H8/3847S Group, H8/38347 Group, and
H8/38447 Group.
Rev. 6.00 Aug 04, 2006 page 559 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
Appendix B Internal I/O Registers
B.1
Addresses
Upper Address: H'F0
Lower
Address
Register
Name
H'20
Bit Names
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
ROM
H'21
FLMCR2
FLER
—
—
—
—
—
—
—
H'22
FLPWCR
PDWND —
—
—
—
—
—
—
H'23
EBR
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
FENR
FLSHE
—
—
—
—
—
—
—
H'24
H'25
H'26
H'27
H'28
H'29
H'2A
H'2B
H'2C
H'2D
H'2E
H'2F
Rev. 6.00 Aug 04, 2006 page 560 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
Upper Address: H'FF
Lower
Register
Bit Names
Address
Name
Bit 7
Module
H'90
WEGR
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0 System
control
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
H'91
SPCR
—
—
SPC32
SPC31
SCINV3
SCINV2
SCINV1
SCINV0
SCI
H'92
CWOSR
—
—
—
—
—
—
—
CWOS
Timer A
H'95
ECCSR
OVH
OVL
—
CH2
CUEH
CUEL
CRCH
CRCL
H'96
ECH
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
H'97
ECL
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Asynchronous event
counter
H'98
SMR31
COM31
CHR31
PE31
PM31
STOP31
MP31
CKS311
CKS310
H'99
BRR31
BRR317
BRR316
BRR315
BRR314
BRR313
BRR312
BRR311
BRR310
H'93
H'94
H'9A
SCR31
TIE31
RIE31
TE31
RE31
MPIE31
TEIE31
CKE31
CKE310
H'9B
TDR31
TDR317
TDR316
TDR315
TDR314
TDR313
TDR312
TDR311
TDR310
H'9C
SSR31
TDRE31
RDRF31
OER31
FER31
PER31
TEND31
MPBR31
MPBT31
H'9D
RDR31
RDR317
RDR316
RDR315
RDR314
RDR313
RDR312
RDR311
RDR310
H'A0
SCR1
SNC1
SNC0
MRKON
LTCH
CKS3
CKS2
CKS1
CKS0
H'A1
SCSR1
—
SOL
ORER
—
—
—
MTRF
STF
SCI31
H'9E
H'9F
H'A2
SDRU
SDRU7
SDRU6
SDRU5
SDRU4
SDRU3
SDRU2
SDRU1
SDRU0
H'A3
SDRL
SDRL7
SDRL6
SDRL5
SDRL4
SDRL3
SDRL2
SDRL1
SDRL0
SCI1
H'A4
H'A5
H'A6
H'A7
H'A8
SMR32
COM32
CHR32
PE32
PM32
STOP32
MP32
CKS321
CKS320
H'A9
BRR32
BRR327
BRR326
BRR325
BRR324
BR323
BRR322
BRR321
BRR320
H'AA
SCR32
TIE32
RIE32
TE32
RE32
MPIE32
TEIE32
CKE321
CKE320
H'AB
TDR32
TDR327
TDR326
TDR325
TDR324
TDR323
TDR322
TDR321
TDR320
H'AC
SSR32
TDRE32
RDRF32
OER32
FER32
PER32
TEND32
MPBR32
MPBT32
H'AD
RDR32
RDR327
RDR326
RDR325
RDR324
RDR323
RDR322
RDR321
RDR320
H'B0
TMA
TMA7
TMA6
TMA5
—
TMA3
TMA2
TMA1
TMA0
H'B1
TCA
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
SCI32
H'AE
H'AF
Timer A
Rev. 6.00 Aug 04, 2006 page 561 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
Lower
Register
Bit Names
Address
Name
Bit 7
Module
H'B2
TCSRW
B6WI
TCWE
B4WI
TCSRWE B2WI
WDON
H'B3
TCW
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
H'B4
TMC
TMC7
TMC6
TMC5
—
—
TMC2
H'B5
TCC/
TLC
TCC/
TLC7
TCC6/
TLC6
TCC5/
TLC5
TCC4/
TLC4
TCC3/
TLC3
TCC2/
TLC2
H'B6
TCRF
TOLH
CKSH2
CKSH1
CKSH0
TOLL
H'B7
TCSRF
OVFH
CMFH
OVIEH
CCLRH
H'B8
TCFH
TCFH7
TCFH6
TCFH5
TCFH4
TCFL6
TCFL5
TCFL4
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
BOW1
WRST
TCW1
TCWO
Watchdog
timer
TMC1
TMC0
Timer C
TCC1/
TLC1
TCC0/
TLC0
CKSL2
CKSL1
CKSL0
OVFL
CMFL
OVIEL
CCLRL
TCFH3
TCFH2
TCFH1
TCFH0
TCFL3
TCFL2
TCFL1
TCFL0
H'B9
TCFL
TCFL7
H'BA
OCRFH
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
H'BB
OCRFL
OCRFL7
OCRFL6
OCRFL5
OCRFL4
OCRFL3
OCRFL2
OCRFL1
OCRFL0
H'BC
TMG
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
H'BD
ICRGF
ICRGF7
ICRGF6
ICRGF5
ICRGF4
ICRGF3
ICRGF2
ICRGF1
ICRGFO
H'BE
ICRGR
ICRGR7
ICRGR6
ICRGR5
ICRGR4
ICRGR3
ICRGR2
ICRGR1
ICRGRO
Timer F
Timer G
H'BF
H'C0
LPCR
DTS1
DTS0
CMX
SGX
SGS3
SGS2
SGS1
SGS0
H'C1
LCR
—
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
H'C2
LCR2
LCDAB
—
—
—
CDS3
CDS2
CDS1
CDS0
LCD
controller/
driver
H'C3
H'C4
ADRRH
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
H'C5
ADRRL
ADR1
ADR0
—
—
—
—
—
—
H'C6
AMR
CKS
TRGE
—
—
CH3
CH2
CH1
CH0
H'C7
ADSR
ADSF
—
—
—
—
—
—
—
H'C8
PMR1
IRQ3
IRQ2
IRQ1
IRQ4
TMIG
TMOFH
TMOFL
TMOW
H'C9
PMR2
EXCL
—
POF1
—
—
SO1
SI1
SCK1
A/D
converter
I/O port
H'CA
PMR3
AEVL
AEVH
WDCKS
NCS
IRQ0
RESO
UD
PWM
H'CB
PMR4
NMOD7
NMOD6
NMOD5
NMOD4
NMOD3
NMOD2
NMOD1
NMOD0
H'CC
PMR5
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
H'D0
PWCR
—
—
—
—
—
—
PWCR1
PWCR0
H'D1
PWDRU
—
—
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0 PWM
H'D2
PWDRL
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
H'D4
PDR1
P17
P16
P15
P14
P13
P12
P11
P10
H'D5
PDR2
P27
P26
P25
P24
P23
P22
P21
P20
H'D6
PDR3
P37
P36
P35
P34
P33
P32
P31
P30
H'D7
PDR4
—
—
—
—
P43
P42
P41
P40
H'D8
PDR5
P57
P56
P55
P54
P53
P52
P51
P50
H'CD
H'CE
H'CF
Bit 14
H'D3
Rev. 6.00 Aug 04, 2006 page 562 of 680
REJ09B0145-0600
I/O Port
Appendix B Internal I/O Registers
Lower
Register
Bit Names
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Name
Module
H'D9
PDR6
P67
P66
P65
P64
P63
P62
P61
P60
I/O Port
H'DA
PDR7
P77
P76
P75
P74
P73
P72
P71
P70
H'DB
PDR8
P87
P86
P85
P84
P83
P82
P81
P80
H'DC
PDR9
P97
P96
P95
P94
P93
P92
P91
P90
H'DD
PDRA
—
—
—
—
PA3
PA2
PA1
PA0
H'DE
PDRB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
H'DF
PDRC
—
—
—
—
PC3
PC2
PC1
PC0
H'E0
PUCR1
PUCR17
PUCR16
PUCR15
PUCR14
PUCR13
PUCR12
PUCR11
PUCR10
H'E1
PUCR3
PUCR37
PUCR36
PUCR35
PUCR34
PUCR33
PUCR32
PUCR31
PUCR30
H'E2
PUCR5
PUCR57
PUCR56
PUCR55
PUCR54
PUCR53
PUCR52
PUCR51
PUCR50
H'E3
PUCR6
PUCR67
PUCR66
PUCR65
PUCR64
PUCR63
PUCR62
PUCR61
PUCR60
H'E4
PCR1
PCR17
PCR16
PCR15
PCR14
PCR13
PCR12
PCR11
PCR10
H'E5
PCR2
PCR27
PCR26
PCR25
PCR24
PCR23
PCR22
PCR21
PCR20
H'E6
PCR3
PCR37
PCR36
PCR35
PCR34
PCR33
PCR32
PCR31
PCR30
H'E7
PCR4
—
—
—
—
—
PCR42
PCR41
PCR40
H'E8
PCR5
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
H'E9
PCR6
PCR67
PCR66
PCR65
PCR64
PCR63
PCR62
PCR61
PCR60
H'EA
PCR7
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
H'EB
PCR8
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
H'EC
PCR9
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
H'ED
PCRA
—
—
—
—
PCRA3
PCRA2
PCRA1
PCRA0
I/O Port
H'EE
H'EF
H'F0
SYSCR1
SSBY
STS2
STS1
STS0
LSON
—
MA1
MA0
H'F1
SYSCR2
—
—
—
NESEL
DTON
MSON
SA1
SA0
H'F2
IEGR
—
—
—
IEG4
IEG3
IEG2
IEG1
IEG0
H'F3
IENR1
IENTA
IENS1
IENWP
IEN4
IEN3
IEN2
IEN1
IEN0
H'F4
IENR2
IENDT
IENAD
—
IENTG
IENTFH
IENTFL
IENTC
IENEC
H'F6
IRR1
IRRTA
IRRS1
—
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
H'F7
IRRI2
IRRDT
IRRAD
—
IRRTG
IRRTFH
IRRTFL
IRRTC
IRREC
H'F9
IWPR
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
H'FA
CKSTPR1 S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
H'FB
CKSTPR2 —
System
control
H'F5
H'F8
—
—
—
AECKSTP WDCKSTP PWCKSTP LDCKSTP
H'FC
H'FD
H'FE
H'FF
Legend
SCI: Serial Communication Interface
Rev. 6.00 Aug 04, 2006 page 563 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
B.2
Functions
Register
acronym
Register
name
Address to which the
register is mapped
Name of
on-chip
supporting
module
Timer C
H'B4
TMC—Timer mode register C
Bit
numbers
Bit
Initial bit
values
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
—
—
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
—
—
R/W
R/W
R/W
Clock select
0 0 0 Internal clock: φ/8192
1 Internal clock: φ/2048
1 0 Internal clock: φ/512
1 Internal clock: φ/64
1 0 0 Internal clock: φ/16
1 Internal clock: φ/4
1 0 Internal clock: φ W/4
1 External event (TMIC): Rising or falling edge
Possible types of access
R
Read only
W
Write only
R/W Read and write
Counter up/down control
0 0 TCC is an up-counter
1 TCC is a down-counter
1 * TCC up/down control is determined by input at pin
UD. TCC is a down-counter if the UD input is high,
and an up-counter if the UD input is low.
Auto-reload function select
0 Interval timer function selected
1 Auto-reload function selected
*: Don’t care
Rev. 6.00 Aug 04, 2006 page 564 of 680
REJ09B0145-0600
Names of the
bits. Dashes
(—) indicate
reserved bits.
Full name
of bit
Descriptions
of bit settings
Appendix B Internal I/O Registers
FLMCR1—Flash Memory Control Register 1
Bit
H'F020
Flash Memory
7
6
5
4
3
2
1
0
SWE
ESU
PSU
EV
PV
E
P
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program
0
Program mode cleared (initial value)
1
Transition to program mode
[Setting condition]
When SWE = 1 and PSU = 1
Erase
0
Erase mode cleared (initial value)
1
Transition to erase mode
[Setting condition]
When SWE = 1 and ESU = 1
Program-Verify
0
Program-verify mode cleared (initial value)
1
Transition to program-verify mode
[Setting condition]
When SWE = 1
Erase-Verify
0
Erase-verify mode cleared (initial value)
1
Transition to erase-verify mode
[Setting condition]
When SWE = 1
Program-Setup
0
Program-setup cleared (initial value)
1
Program setup
[Setting condition]
When SWE = 1
Erase-Setup
0
Erase-setup cleared (initial value)
1
Erase setup
[Setting condition]
When SWE = 1
Software write enable bit
0
Writing/erasing disabled (initial value)
1
Writing/erasing enabled
Rev. 6.00 Aug 04, 2006 page 565 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
FLMCR2—Flash Memory Control Register 2
Bit
H'F021
Flash Memory
7
6
5
4
3
2
1
0
FLER
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
Flash memory error
Note: A write to FLMCR2 is prohibited.
FLPWCR—Flash Memory Power Control Register
Bit
H'F022
Flash Memory
7
6
5
4
3
2
1
0
PDWND
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
Power-down Disable
0 When the system transits to sub-active mode,
the flash memory changes to low-power mode
1 When the system transits to sub-active mode,
the flash memory changes to normal mode
Rev. 6.00 Aug 04, 2006 page 566 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
EBR—Erase Block Register
Bit
H'F023
Flash Memory
7
6
5
4
3
2
1
0
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Blocks 7 to 0
0 When a block of EB7 to EB0 is not selected (initial value)
1 When a block of EB7 to EB0 is selected
Note: Set the bit of EBR to H'00 when erasing.
FENR—Flash Memory Enable Register
Bit
H'F02B
Flash Memory
7
6
5
4
3
2
1
0
FLSHE
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
Flash Memory Control Register Enable
0 The flash memory control register cannot be accessed
1 The flash memory control register can be accessed
Rev. 6.00 Aug 04, 2006 page 567 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
WEGR—Wakeup Edge Select Register
Bit
7
6
H'90
5
4
3
2
System control
1
0
WKEGS7 WKEGS6 WKEGS5 WKEGS4 WKEGS3 WKEGS2 WKEGS1 WKEGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
WKPn edge selected
0
1
WKPn pin falling edge detected
WKPn pin rising edge detected
(n = 0 to 7)
Rev. 6.00 Aug 04, 2006 page 568 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
SPCR—Serial Port Control Register
Bit
H'91
7
6
5
4
3
2
SCI
1
0
—
—
SPC32
SPC31
Initial value
1
1
0
0
SCINV3 SCINV2 SCINV1 SCINV0
0
0
0
0
Read/Write
—
—
R/W
R/W
R/W
R/W
R/W
R/W
RXD31 pin input data inversion switch
0
1
RXD31 input data is not inverted
RXD31 input data is inverted
TXD31 pin output data inversion switch
0
1
TXD31 output data is not inverted
TXD31 output data is inverted
RXD32 pin input data inversion switch
0
1
RXD32 input data is not inverted
RXD32 input data is inverted
TXD32 pin output data inversion switch
0
1
TXD32 output data is not inverted
TXD32 output data is inverted
P35TXD31 pin function switch
0
1
Functions as P35 I/O pin
Functions as TXD31 output pin
P42/TXD32pin function switch
0
1
Function as P42 I/O pin
Function as TXD32 output pin
Rev. 6.00 Aug 04, 2006 page 569 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
CWOSR—Subclock Output Select Register
Bit
H'92
Timer A
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
CWOS
Initial value
1
1
1
1
1
1
1
0
Read/Write
R
R
R
R
R
R
R
R/W
TMOW pin clock select
0
1
Rev. 6.00 Aug 04, 2006 page 570 of 680
REJ09B0145-0600
Clock output from TMA is output
φW is output
Appendix B Internal I/O Registers
ECCSR—Event Counter Control/Status Register
Bit
H'95
AEC
7
6
5
4
3
2
1
0
CRCL
OVH
OVL
CH2
CUEH
CUEL
CRCH
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
Counter reset control L
0 ECL is reset
1 ECL reset is cleared
and count-up function
is enabled
Counter reset control H
0 ECH is reset
1 ECH reset is cleared and
count-up function is enabled
Count-up enable L
0 ECL event clock input is disabled.
ECL value is held
1 ECL event clock input is enabled
Count-up enable H
0 ECH event clock input is disabled.
ECH value is held
1 ECH event clock input is enabled
Channel select
0 ECH and ECL are used together as a singlechannel 16-bit event counter
1
ECH and ECL are used as two independent
8-bit event counter channels
Counter overflow L
0 ECL has not overflowed
Clearing condition:
After readng OVL = 1, cleared by writing 0 to OVL
1 ECL has overflowed
Setting condition:
Set when ECL overflows from H'FF to H'00 while CH2 is set to 1
Counter overflow H
0 ECH has not overflowed
Clearing condition:
After readng OVH = 1, cleared by writing 0 to OVH
1
ECH has overflowed
Setting condition:
Set when ECH overflows from H'FF to H'00
Note: * Only a write of 0 for clearing is possible.
Rev. 6.00 Aug 04, 2006 page 571 of 680
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Appendix B Internal I/O Registers
ECH—Event Counter H
Bit
H'96
AEC
7
6
5
4
3
2
1
0
ECH7
ECH6
ECH5
ECH4
ECH3
ECH2
ECH1
ECH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Note: * ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit
event counter (EC).
ECL—Event Counter L
Bit
H'97
AEC
7
6
5
4
3
2
1
0
ECL7
ECL6
ECL5
ECL4
ECL3
ECL2
ECL1
ECL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Note: * ECH and ECL can also be used as the upper and lower halves, respectively, of a 16-bit
event counter (EC).
Rev. 6.00 Aug 04, 2006 page 572 of 680
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Appendix B Internal I/O Registers
SMR31—Serial Mode Register 31
Bit
H'98
SCI31
7
6
5
4
3
2
COM31
CHR31
PE31
PM31
STOP31
MP31
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
CKS311 CKS310
Clock select
0 0 φ clock
0 1 φw/2 clock
1 0 φ/16 clock
1 1 φ/64 clock
Multiprocessor mode
0 Multiprocessor communication
function disabled
1 Multiprocessor communication
function enabled
Stop bit length
0 1 stop bit
1 2 stop bits
Parity mode
0 Even parity
1 Odd parity
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character length
0 8-bit data/5-bit data
1 7-bit data/5-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode
Rev. 6.00 Aug 04, 2006 page 573 of 680
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Appendix B Internal I/O Registers
BRR31—Bit Rate Register 31
Bit
7
6
H'99
5
4
3
2
SCI31
1
0
BRR317 BRR316 BRR315 BRR314 BRR313 BRR312 BRR311 BRR310
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial transmit/receive bit rate
Rev. 6.00 Aug 04, 2006 page 574 of 680
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Appendix B Internal I/O Registers
SCR31—Serial Control Register 31
Bit
H'9A
3
SCI31
7
6
5
4
TIE31
RIE31
TE31
RE31
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
MPIE31 TEIE31 CKE311 CKE310
Clock enable
Bit 0
Bit 1
CKE311 CKE310
0
0
0
1
1
0
1
1
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Description
Clock Source
SCK 3 Pin Function
I/O port
Internal clock
Serial clock output
Internal clock
Clock output
Internal clock
Reserved (Do not specify this combination)
Clock input
External clock
Serial clock input
External clock
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit end interrupt enable
0
1
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupt request disabled (normal receive operation)
[Clearing condition]
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive enable
0
Receive operation disabled (RXD pin is I/O port)
1
Receive operation enabled (RXD pin is receive data pin)
Transmit enable
0
Transmit operation disabled (TXD pin is transmit data pin)
1
Transmit operation enabled (TXD pin is transmit data pin)
Receive interrupt enable
0
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
Rev. 6.00 Aug 04, 2006 page 575 of 680
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Appendix B Internal I/O Registers
TDR31—Transmit Data Register 31
Bit
7
6
H'9B
5
4
3
2
SCI31
1
0
TDR317 TDR316 TDR315 TDR314 TDR313 TDR312 TDR311 TDR310
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for transfer to TSR
Rev. 6.00 Aug 04, 2006 page 576 of 680
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Appendix B Internal I/O Registers
SSR31—Serial Status Register31
Bit
7
H'9C
6
4
5
TDRE31 RDRF31 OER31
Initial value
1
0
*
Read/Write
R/(W)
0
0
*
*
R/(W)
3
FER31
R/(W)
2
R/(W)
0
1
PER31 TEND31 MPBR31 MPBT31
0
*
SCI3
*
R/(W)
1
0
0
R
R
R/W
Multiprocessor bit transfer
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
Multiprocessor bit receive
0
Data in which the multiprocessor bit is 0 has been received
1
Data in which the multiprocessor bit is 1 has been received
Transmit end
0
Transmission in progress
[Clearing conditions] • After reading TDRE31 = 1, cleared by writing 0 to TDRE
• When data is written to TDR31 by an instruction
1
Transmission ended
[Setting conditions]
• When bit TE in serial control register 31 (SCR31) is cleared to 0
• When bit TDRE31 is set to 1 when the last bit of a transmit character is sent
Parity error
0
Reception in progress or completed normally
[Clearing condition] After reading PER31 = 1, cleared by writing 0 to PER31
1
A parity error has occurred during reception
[Setting condition] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM31) in the serial mode register (SMR31)
Framing error
0
Reception in progress or completed normally
[Clearing condition] After reading FER31 = 1, cleared by writing 0 to FER31
1
A framing error has occurred during reception
[Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0
Reception in progress or completed
[Clearing condition] After reading OER31 = 1, cleared by writing 0 to OER31
1
An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF31 set to 1
Receive data register full
0
There is no receive data in RDR31
[Clearing conditions] • After reading RDRF31 = 1, cleared by writing 0 to RDRF31
• When RDR31 data is read by an instruction
1
There is receive data in RDR31
[Setting condition] When reception ends normally and receive data is transferred from RSR31 to RDR31
Transmit data register empty
0
Transmit data written in TDR31 has not been transferred to TSR31
[Clearing conditions] • After reading TDRE31 = 1, cleared by writing 0 to TDRE31
• When data is written to TDR31 by an instruction
1
Transmit data has not been written to TDR31, or transmit data written in TDR31 has been transferred to TSR31
[Setting conditions] • When bit TE in serial control register 31 (SCR31) is cleared to 0
• When data is transferred from TDR31 to TSR31
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Aug 04, 2006 page 577 of 680
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Appendix B Internal I/O Registers
RDR31—Receive Data Register 31
Bit
7
6
H'9D
5
4
3
2
SCI31
1
0
RDR317 RDR316 RDR315 RDR314 RDR313 RDR312 RDR311 RDR310
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Serial receiving data are stored
Rev. 6.00 Aug 04, 2006 page 578 of 680
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Appendix B Internal I/O Registers
SCR1—Serial Control Register 1
Bit
H'A0
SCI1
7
6
5
4
3
2
1
0
SNC1
SNC0
MRKON
LTCH
CKS3
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock select 2 to 0
Bit 2 Bit 1 Bit 0
CKS2 CKS1 CKS0
0
0
0
1
0
0
1
0
0
1
1
0
1
0
0
1
0
1
1
1
0
1
1
1
Prescaler
Division
Ratio
φ/1024
φ/256
φ/64
φ/32
φ/16
φ/8
φ/4
φW/4
Serial Clock Cycle
Clock Cycle
φ = 2.5 MHz
409.6 µs
102.4 µs
25.6 µs
12.8 µs
6.4 µs
3.2 µs
1.6 µs
122 µs
Clock source select
0 Clock source is prescaler S, SCK1 is output pin
1 Clock source is external clock, SCK1 is input pin
LATCH TAIL select
0 HOLD TAIL is output
1 LATCH TAIL is output
Tail mark control
0 Tail mark is not output (synchronous mode)
1 Tail mark is output (SSB mode)
Operating mode select
0 0 8-bit synchronous mode
1 16-bit synchronous mode
1 0 Continuous clock output mode
1 Reserved
Rev. 6.00 Aug 04, 2006 page 579 of 680
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Appendix B Internal I/O Registers
SCSR1—Serial Control Status Register 1
Bit
H'A1
SCI1
7
6
5
4
3
2
1
0
SOL
ORER
MTRF
STF
Initial value
1
0
0
1
1
1
0
0
Read/Write
R/W
R/(W)*
R
R/W
Start flag
0 Read
Write
1 Read
Write
Transfer operation stopped
Invalid
Transfer operation in progress
Starts transfer operation
Tail mark transmission flag
0 Idle state, or 8-bit/16-bit data transfer in progress
1 Tail mark transmission in progress
Overrun error flag
0 [Clearing condition]
After reading ORER = 1, cleared by writing 0 to ORER
1 [Setting condition]
When an external clock is used and the clock is input
after transfer is completed
Extension data bit
0 Read SO1 pin output level is low
Write Changes SO1 pin output to low level
1 Read SO1 pin output level is high
Write Changes SO1 pin output to high level
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Aug 04, 2006 page 580 of 680
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Appendix B Internal I/O Registers
SDRU—Serial Data Register U
Bit
Initial value
Read/Write
H'A2
SCI1
7
6
5
4
3
2
1
0
SDRU7
SDRU6
SDRU5
SDRU4
SDRU3
SDRU2
SDRU1
SDRU0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Used for transmit data setting and receive data storage
8-bit transfer mode: Not used
16-bit transfer mode: Upper 8 bits of data register
SDRL—Serial Data Register L
Bit
Initial value
Read/Write
H'A3
SCI1
7
6
5
4
3
2
1
0
SDRL7
SDRL6
SDRL5
SDRL4
SDRL3
SDRL2
SDRL1
SDRL0
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Used for transmit data setting and receive data storage
8-bit transfer mode: Data register
16-bit transfer mode: Lower 8 bits of data register
Rev. 6.00 Aug 04, 2006 page 581 of 680
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Appendix B Internal I/O Registers
SMR32—Serial Mode Register 32
Bit
H'A8
SCI32
7
6
5
4
3
2
COM32
CHR32
PE32
PM32
STOP32
MP32
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
0
CKS321 CKS320
Clock select
0 0 φ clock
0 1 φw/2 clock
1 0 φ/16 clock
1 1 φ/64 clock
Multiprocessor mode
0 Multiprocessor communication
function disabled
1 Multiprocessor communication
function enabled
Stop bit length
0 1 stop bit
1 2 stop bits
Parity mode
0 Even parity
1 Odd parity
Parity enable
0 Parity bit addition and checking disabled
1 Parity bit addition and checking enabled
Character length
0 8-bit data/5-bit data
1 7-bit data/5-bit data
Communication mode
0 Asynchronous mode
1 Synchronous mode
Rev. 6.00 Aug 04, 2006 page 582 of 680
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Appendix B Internal I/O Registers
BRR32—Bit Rate Register 32
Bit
7
6
H'A9
5
4
3
2
SCI32
1
0
BRR327 BRR326 BRR325 BRR324 BRR323 BRR322 BRR321 BRR3120
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial transmit/receive bit rate
Rev. 6.00 Aug 04, 2006 page 583 of 680
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Appendix B Internal I/O Registers
SCR32—Serial Control Register 32
Bit
H'AA
3
SCI32
7
6
5
4
TIE32
RIE32
TE32
RE32
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
Clock enable
Bit 0
Bit 1
CKE321 CKE320
0
0
0
1
1
0
1
1
Communication Mode
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Asynchronous
Synchronous
Description
Clock Source
SCK 3 Pin Function
I/O port
Internal clock
Serial clock output
Internal clock
Clock output
Internal clock
Reserved (Do not specify this combination)
Clock input
External clock
Serial clock input
External clock
Reserved (Do not specify this combination)
Reserved (Do not specify this combination)
Transmit end interrupt enable
0
1
Transmit end interrupt request (TEI) disabled
Transmit end interrupt request (TEI) enabled
Multiprocessor interrupt enable
0
Multiprocessor interrupt request disabled (normal receive operation)
[Clearing condition]
When data is received in which the multiprocessor bit is set to 1
1
Multiprocessor interrupt request enabled
The receive interrupt request (RXI), receive error interrupt request (ERI), and setting of the
RDRF, FER, and OER flags in the serial status register (SSR), are disabled until data with
the multiprocessor bit set to 1 is received.
Receive enable
0
Receive operation disabled (RXD pin is I/O port)
1
Receive operation enabled (RXD pin is receive data pin)
Transmit enable
0
Transmit operation disabled (TXD pin is transmit data pin)
1
Transmit operation enabled (TXD pin is transmit data pin)
Receive interrupt enable
0
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) disabled
1
Receive data full interrupt request (RXI) and receive error interrupt request (ERI) enabled
Transmit interrupt enable
0
Transmit data empty interrupt request (TXI) disabled
1
Transmit data empty interrupt request (TXI) enabled
Rev. 6.00 Aug 04, 2006 page 584 of 680
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0
MPIE32 TEIE32 CKE321 CKE320
Appendix B Internal I/O Registers
TDR32—Transmit Data Register 32
Bit
7
6
H'AB
5
4
3
2
SCI32
1
0
TDR327 TDR326 TDR325 TDR324 TDR323 TDR322 TDR321 TDR320
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for transfer to TSR
Rev. 6.00 Aug 04, 2006 page 585 of 680
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Appendix B Internal I/O Registers
SSR32—Serial Status Register 32
Bit
7
H'AC
6
4
5
TDRE32 RDRF32 OER32
Initial value
1
0
*
Read/Write
R/(W)
0
0
*
*
R/(W)
3
FER32
R/(W)
2
R/(W)
0
1
PER32 TEND32 MPBR32 MPBT32
0
*
SCI32
*
R/(W)
1
0
0
R
R
R/W
Multiprocessor bit transfer
0
A 0 multiprocessor bit is transmitted
1
A 1 multiprocessor bit is transmitted
Multiprocessor bit receive
0
Data in which the multiprocessor bit is 0 has been received
1
Data in which the multiprocessor bit is 1 has been received
Transmit end
0
Transmission in progress
[Clearing conditions] • After reading TDRE32 = 1, cleared by writing 0 to TDRE32
• When data is written to TDR32 by an instruction
1
Transmission ended
[Setting conditions]
• When bit TE in serial control register 32 (SCR32) is cleared to 0
• When bit TDRE32 is set to 1 when the last bit of a transmit character is sent
Parity error
0
Reception in progress or completed normally
[Clearing condition] After reading PER32 = 1, cleared by writing 0 to PER32
1
A parity error has occurred during reception
[Setting condition] When the number of 1 bits in the receive data plus parity bit does not match the parity
designated by the parity mode bit (PM32) in the serial mode register (SMR32)
Framing error
0
Reception in progress or completed normally
[Clearing condition] After reading FER32 = 1, cleared by writing 0 to FER32
1
A framing error has occurred during reception
[Setting condition] When the stop bit at the end of the receive data is checked for a value of 1 at completion of
reception, and the stop bit is 0
Overrun error
0
Reception in progress or completed
[Clearing condition] After reading OER32 = 1, cleared by writing 0 to OER32
1
An overrun error has occurred during reception
[Setting condition] When the next serial reception is completed with RDRF32 set to 1
Receive data register full
0
There is no receive data in RDR32
[Clearing conditions] • After reading RDRF32 = 1, cleared by writing 0 to RDRF32
• When RDR32 data is read by an instruction
1
There is receive data in RDR32
[Setting condition] When reception ends normally and receive data is transferred from RSR32 to RDR32
Transmit data register empty
0
Transmit data written in TDR32 has not been transferred to TSR32
[Clearing conditions] • After reading TDRE32 = 1, cleared by writing 0 to TDRE32
• When data is written to TDR32 by an instruction
1
Transmit data has not been written to TDR32, or transmit data written in TDR32 has been transferred to TSR32
[Setting conditions] • When bit TE32 in serial control register 32 (SCR32) is cleared to 0
• When data is transferred from TDR32 to TSR32
Note: * Only a write of 0 for flag clearing is possible.
Rev. 6.00 Aug 04, 2006 page 586 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
RDR32—Receive Data Register 32
Bit
7
6
H'AD
5
4
3
2
SCI32
1
0
RDR327 RDR326 RDR325 RDR324 RDR323 RDR322 RDR321 RDR320
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Serial receiving data are stored
Rev. 6.00 Aug 04, 2006 page 587 of 680
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Appendix B Internal I/O Registers
TMA—Timer Mode Register A
Bit
H'B0
Timer A
7
6
5
4
3
2
1
0
TMA7
TMA6
TMA5
—
TMA3
TMA2
TMA1
TMA0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/W
R/W
R/W
—
R/W
R/W
R/W
R/W
Clock output select* Internal clock select
0 0 0 φ/32
Prescaler and Divider Ratio
TMA3 TMA2 TMA1 TMA0 or Overflow Period
0 0 1 φ/16
0
0
0
0
PSS
φ/8192
0 1 0 φ/8
0
0
1
0
PSS
φ/4096
0 1 1 φ/4
0
0
PSS
1
0
φ/2048
1 0 0 φ W/32
0
0
PSS
1
1
φ/512
1 0 1 φ W/16
1
0
0
PSS
0
φ/256
1 1 0 φ W/8
1
0
1
0
PSS
φ/128
1 1 1 φ W/4
1
1
0
PSS
φ/32
0
1
1
1
PSS
φ/8
0
0
0
0
1
PSW
1s
0
0
1
PSW
0.5 s
1
1
PSW
0.25 s
0
0
1
0
1
1
PSW
0.03125 s
1
1
1
0
0
PSW and TCA are reset
1
1
0
1
1
1
1
0
1
1
1
1
Function
Interval
timer
Time
base
(when
using
32.768 kHz)
Note * Values when the CWOS bit in CWOSR is cleared to 0. When the CWOS bit is set to 1,
φw is output regardless of the value of bits TMA7 to TMA5.
Rev. 6.00 Aug 04, 2006 page 588 of 680
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Appendix B Internal I/O Registers
TCA—Timer Counter A
Bit
H'B1
Timer A
7
6
5
4
3
2
1
0
TCA7
TCA6
TCA5
TCA4
TCA3
TCA2
TCA1
TCA0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Rev. 6.00 Aug 04, 2006 page 589 of 680
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Appendix B Internal I/O Registers
TCSRW—Timer Control/Status Register W
Bit
Initial value
Read/Write
H'B2
Watchdog timer
7
6
5
4
3
2
1
0
B6WI
TCWE
B4WI
TCSRWE
B2WI
WDON
B0WI
WRST
1
0
1
0
1
0
1
0
R
R/(W)*
R
R/(W)*
R
R/(W) *
R
R/(W) *
Watchdog timer reset
0 [Clearing conditions]
• Reset by RES pin
• When TCSRWE = 1, and 0 is written in both B0WI and WRST
1 [Setting condition]
When TCW overflows and a reset signal is generated
Bit 0 write inhibit
0 Bit 0 is write-enabled
1 Bit 0 is write-protected
Watchdog timer on
0 Watchdog timer operation is disabled
1 Watchdog timer operation is enabled
Bit 2 write inhibit
0 Bit 2 is write-enabled
1 Bit 2 is write-protected
Timer control/status register W write enable
0 Data cannot be written to bits 2 and 0
1 Data can be written to bits 2 and 0
Bit 4 write inhibit
0 Bit 4 is write-enabled
1 Bit 4 is write-protected
Timer counter W write enable
0 Data cannot be written to TCW
1 Data can be written to TCW
Bit 6 write inhibit
0 Bit 6 is write-enabled
1 Bit 6 is write-protected
Note: * Write is permitted only under certain conditions.
Rev. 6.00 Aug 04, 2006 page 590 of 680
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Appendix B Internal I/O Registers
TCW—Timer Counter W
Bit
H'B3
Watchdog timer
7
6
5
4
3
2
1
0
TCW7
TCW6
TCW5
TCW4
TCW3
TCW2
TCW1
TCW0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
TMC—Timer Mode Register C
Bit
H'B4
Timer C
7
6
5
4
3
2
1
0
TMC7
TMC6
TMC5
TMC2
TMC1
TMC0
Initial value
0
0
0
1
1
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Clock select
0 0 0 Internal clock: φ/8192
0 0 1 Internal clock: φ/2048
0 1 0 Internal clock: φ/512
0 1 1 Internal clock: φ/64
1 0 0 Internal clock: φ/16
1 0 1 Internal clock: φ/4
1 1 0 Internal clock: φw/4
External event (TMIC): Counting
1 1 1
on rising or falling edge
Counter up/down control
0 0 TCC is an up-counter
0 1 TCC is a down-counter
1 * Hardware control of TCC up/down operation by UD pin input
UD pin input high: Down-counter
UD pin input low: Up-counter
Auto-reload function select
0 Interval timer function selected
1 Auto-reload function selected
* Don't care
Rev. 6.00 Aug 04, 2006 page 591 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
TCC—Timer Counter C
Bit
H'B5
Timer C
7
6
5
4
3
2
1
0
TCC7
TCC6
TCC5
TCC4
TCC3
TCC2
TCC1
TCC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Count value
Note: TCC is assigned to the same address as TLC. In a read, the TCC value is read.
TLC—Timer Load Register C
Bit
H'B5
Timer C
7
6
5
4
3
2
1
0
TLC7
TLC6
TLC5
TLC4
TLC3
TLC2
TLC1
TLC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reload value
Note: TLC is assigned to the same address as TCC. In a write, the TLC value is written.
Rev. 6.00 Aug 04, 2006 page 592 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
TCRF—Timer Control Register F
Bit
H'B6
Timer F
7
6
5
4
3
2
1
0
TOLH
CKSH2
CKSH1
CKSH0
TOLL
CKSL2
CKSL1
CKSL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Clock select L
0
*
*
1
1
1
0
0
1
0
1
0
1
1
1
Counting on external event (TMIF)
rising/falling edge
Internal clock φ/32
Internal clock φ/16
Internal clock φ/4
Internal clock φw/4
Toggle output level L
0
1
Low level
High level
Clock select H
0
*
*
1
1
0
0
0
1
1
1
0
1
1
1
Toggle output level H
0
1
16-bit mode, counting on TCFL
overflow signal
Internal clock φ/32
Internal clock φ/16
Internal clock φ/4
Internal clock φw/4
* Don't care
Low level
High level
Rev. 6.00 Aug 04, 2006 page 593 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
TCSRF—Timer Control/Status Register F
Bit
H'B7
Timer F
7
6
5
4
3
2
1
0
OVFH
CMFH
OVIEH
CCLRH
OVFL
CMFL
OVIEL
CCLRL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/W
R/(W)*
R/(W)*
R/W
R/W
Counter clear L
0
TCFL clearing by compare match is disabled
1
TCFL clearing by compare match is enabled
Timer overflow interrupt enable L
0
TCFL overflow interrupt request is disabled
1
TCFL overflow interrupt request is enabled
Compare match flag L
0
[Clearing condition]
After reading CMFL = 1, cleared by writing 0 to CMFL
1
[Setting condition]
Set when the TCFL value matches the OCRFL value
Timer overflow flag L
0
[Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1
[Setting condition]
Set when TCFL overflows from H'FF to H'00
Counter clear H
0
16-bit mode: TCF clearing by compare match is disabled
8-bit mode: TCFH clearing by compare match is disabled
1
16-bit mode: TCF clearing by compare match is enabled
8-bit mode: TCFH clearing by compare match is enabled
Timer overflow interrupt enable H
0
TCFH overflow interrupt request is disabled
1
TCFH overflow interrupt request is enabled
Compare match flag H
0
[Clearing condition]
After reading CMFH = 1, cleared by writing 0 to CMFH
1
[Setting condition]
Set when the TCFH value matches the OCRFH value
Timer overflow flag H
0
[Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1
[Setting condition]
Set when TCFH overflows from H'FF to H'00
Note: * Bits 7, 6, 3, and 2 can only be written with 0, for flag clearing.
Rev. 6.00 Aug 04, 2006 page 594 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
TCFH—8-Bit Timer Counter FH
Bit
H'B8
Timer F
7
6
5
4
3
2
1
0
TCFH7
TCFH6
TCFH5
TCFH4
TCFH3
TCFH2
TCFH1
TCFH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit
timer counter (TCF).
TCFL—8-Bit Timer Counter FL
Bit
H'B9
Timer F
7
6
5
4
3
2
1
0
TCFL7
TCFL6
TCFL5
TCFL4
TCFL3
TCFL2
TCFL1
TCFL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Count value
Note: TCFH and TCFL can also be used as the upper and lower halves, respectively, of a 16-bit
timer counter (TCF).
OCRFH—Output Compare Register FH
Bit
7
6
5
H'BA
4
3
2
Timer F
1
0
OCRFH7 OCRFH6 OCRFH5 OCRFH4 OCRFH3 OCRFH2 OCRFH1 OCRFH0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a
16-bit output compare register (OCRF).
Rev. 6.00 Aug 04, 2006 page 595 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
OCRFL—Output Compare Register FL
Bit
7
6
5
H'BB
4
3
2
Timer F
1
0
OCRFL7 OCRFL6 OCRFL5 OCRFL4 OCRFL3 OCRFL2 OCRFL1 OCRFL0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note: OCRFH and OCRFL can also be used as the upper and lower halves, respectively, of a
16-bit output compare register (OCRF).
Rev. 6.00 Aug 04, 2006 page 596 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
TMG—Timer Mode Register G
Bit
H'BC
Timer G
7
6
5
4
3
2
1
0
OVFH
OVFL
OVIE
IIEGS
CCLR1
CCLR0
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
W
W
W
W
W
W
Clock select
0 0 Internal clock: counting on φ/64
0 1 Internal clock: counting on φ/32
1 0 Internal clock: counting on φ/2
1 1 Internal clock: counting on φw/4
Counter clear
0 0 TCG clearing is disabled
0 1 TCG cleared by falling edge of input capture input signal
1 0 TCG cleared by rising edge of input capture input signal
1 1 TCG cleared by both edges of input capture input signal
Input capture interrupt edge select
0 Interrupt generated on rising edge of input capture input signal
1 Interrupt generated on falling edge of input capture input signal
Timer overflow interrupt enable
0 TCG overflow interrupt request is disabled
1 TCG overflow interrupt request is enabled
Timer overflow flag L
0 [Clearing condition]
After reading OVFL = 1, cleared by writing 0 to OVFL
1 [Setting condition]
Set when TCG overflows from H'FF to H'00
Timer overflow flag H
0 [Clearing condition]
After reading OVFH = 1, cleared by writing 0 to OVFH
1 [Setting condition]
Set when TCG overflows from H'FF to H'00
Note: * Bits 7 and 6 can only be written with 0, for flag clearing.
Rev. 6.00 Aug 04, 2006 page 597 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
ICRGF—Input Capture Register GF
Bit
7
6
H'BD
5
4
3
2
Timer G
1
0
ICRGF7 ICRGF6 ICRGF5 ICRGF4 ICRGF3 ICRGF2 ICRGF1 ICRGF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Stores TCG value at falling edge of input capture signal
ICRGR—Input Capture Register GR
Bit
7
6
H'BE
5
4
3
2
Timer G
1
0
ICRGR7 ICRGR6 ICRGR5 ICRGR4 ICRGR3 ICRGR2 ICRGR1 ICRGR0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Stores TCG value at rising edge of input capture signal
Rev. 6.00 Aug 04, 2006 page 598 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
LPCR—LCD Port Control Register
Bit
H'C0
LCD controller/driver
7
6
5
4
3
2
1
0
DTS1
DTS0
CMX
SGX
SGS3
SGS2
SGS1
SGS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Segment driver select
Bit 4 Bit 3
Bit 2 Bit 1 Bit 0 Function of Pins SEG32 to SEG1
SEG32
SEG24
SEG16
SEG8
SEG40
SGX SGS3 SGS2 SGS1 SGS0 to SEG33 to SEG25 to SEG17 to SEG9 to SEG1
0
0
0
0
0
Port
Port
Port
Port
Port
1
0
0
0
0
SEG
Port
Port
Port
Port
1
0
0
0
SEG
SEG
Port
Port
Port
*
0
1
0
0
SEG
SEG
SEG
Port
Port
*
1
1
0
0
SEG
SEG
SEG
SEG
Port
*
0
1
SEG
SEG
SEG
SEG
SEG
*
*
*
*1
0
0
0
1
0
Port
Port
Port
Port
Port
1
0
0
1
0
Do not use
1
0
1
0
*
1
1
0
*
*
1
1
*
*
*
Note: 1. SEG40 to SEG37 are external expansion pins.
Notes
(Initial value)
*: Don’t care
Expansion signal select
0
SEG40 to SEG37 pin* (Initial value)
1
CL1, CL2, DO and M pin
Note: * Functions as ports when SGS3 to SGS0 are set at "0000".
In the case of the H8/38347 Group and H8/38447 Group the initial values of these bits must not be changed.
Duty select, common function select
Bit 7 Bit 6 Bit 5
Duty Cycle Common Drivers
Notes
DTS1 DTS0 CMX
0
0
COM1
0
Do not use COM4, COM3, and COM2
Static
1
0
0
COM4 to COM1 COM4 to COM2 output the same waveform as COM1
0
1
0
COM2 to COM1 Do not use COM4 and COM3
1/2 duty
1
1
0
COM4 to COM1 COM4 outputs the same waveform as COM3 and COM2 outputs the same waveform as COM1
0
0
1
COM3 to COM1 Do not use COM4
1/3 duty
1
0
1
COM4 to COM1 Do not use COM4
0
1
1
—
COM4 to COM1
1/4 duty
1
1
1
Rev. 6.00 Aug 04, 2006 page 599 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
LCR—LCD Control Register
Bit
H'C1
LCD controller/driver
7
6
5
4
3
2
1
0
PSW
ACT
DISP
CKS3
CKS2
CKS1
CKS0
Initial value
1
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Frame frequency select
Bit 3 Bit 2 Bit 1 Bit 1
CKS3 CKS2 CKS1 CKS0
0
0
0
1
1
1
1
1
1
1
1
*
*
*
0
0
0
0
1
1
1
1
0
0
1
0
0
1
1
0
0
1
1
Display data control
0 Blank data is displayed
1 LCD RAM data is displayed
Display function activate
0 LCD controller/driver operation halted
1 LCD controller/driver operates
LCD drive power supply on/off control
0 LCD drive power supply off
1 LCD drive power supply on
Rev. 6.00 Aug 04, 2006 page 600 of 680
REJ09B0145-0600
0
1
*
0
1
0
1
0
1
0
1
Operating Clock
φw
φw/2
φw/4
φ/2
φ/4
φ/8
φ/16
φ/32
φ/64
φ/128
φ/256
* Don't care
Appendix B Internal I/O Registers
LCR2—LCD Control Register 2
Bit
H'C2
LCD
7
6
5
4
3
2
1
0
LCDAB
Ñ
Ñ
Ñ
CDS3
CDS2
CDS1
CDS0
Initial value
0
1
1
0
0
0
0
0
Read/Write
R/W
Ñ
Ñ
R/W
R/W
R/W
R/W
R/W
Charge/discharge pulse duty cycle select
Bit 3 Bit 2 Bit 1 Bit 0
Duty Cycle
CDS3 CDS2 CDS1 CDS0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
1
0
0
1
1
0
0
1
1
*
*
0
1
0
1
0
1
0
1
*
*
1
1/8
2/8
3/8
4/8
5/8
6/8
0
1/16
1/32
* Don't care
A waveform/B waveform switching control
0 Drive using A waveform
1 Drive using B waveform
Rev. 6.00 Aug 04, 2006 page 601 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
ADRRH—A/D Result Register H
ADRRL—A/D Result Register L
H'C4
H'C5
A/D converter
ADRRH
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR9
ADR8
ADR7
ADR6
ADR5
ADR4
ADR3
ADR2
Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined
R
R
R
R
R
R
R
R
A/D conversion result
ADRRL
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
ADR1
ADR0
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Undefined Undefined
R
R
A/D conversion result
Rev. 6.00 Aug 04, 2006 page 602 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
AMR—A/D Mode Register
Bit
H'C6
A/D converter
7
6
5
4
3
2
1
0
CKS
TRGE
CH3
CH2
CH1
CH0
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
Channel select
Bit 3 Bit 2 Bit 1
CH3 CH2 CH1
0
0
*
0
0
1
0
0
1
0
1
1
1
0
1
1
0
0
1
0
0
1
0
1
1
0
1
1
1
0
1
1
0
1
1
1
1
1
1
Bit 0
CH0
*
0
1
0
1
0
1
0
1
0
1
0
1
Analog Input Channel
No channel selected
AN 0
AN 1
AN 2
AN 3
AN 4
AN 5
AN 6
AN 7
AN 8
AN 9
AN 10
AN 11
* Don't care
External trigger select
0 Disables start of A/D conversion by external trigger
1 Enables start of A/D conversion by rising or falling edge
of external trigger at pin ADTRG
Clock select
Bit 7
CKS Conversion Period
0
62/φ
1
31/φ
Conversion Time
φ = 1 MHz φ = 5 MHz
62 µs
31 µs
12.4 µs
Rev. 6.00 Aug 04, 2006 page 603 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
ADSR—A/D Start Register
Bit
H'C7
A/D converter
7
6
5
4
3
2
1
0
ADSF
—
—
—
—
—
—
—
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
—
—
—
—
—
—
—
A/D status flag
0 Read Indicates completion of A/D conversion
Write Stops A/D conversion
1 Read Indicates A/D conversion in progress
Write Starts A/D conversion
Rev. 6.00 Aug 04, 2006 page 604 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PMR1—Port Mode Register 1
Bit
H'C8
7
6
5
4
3
2
1
0
IRQ3
IRQ2
IRQ1
IRQ4
TMIG
TMOFH
TMOFL
TMOW
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O port
P10/TMOW pin function switch
0 Functions as P10 I/O pin
1 Functions as TMOW output pin
P11/TMOFL pin function switch
0 Functions as P11 I/O pin
1 Functions as TMOFL output pin
P12/TMOFH pin function switch
0 Functions as P12 I/O pin
1 Functions as TMOFH output pin
P13/TMIG pin function switch
0 Functions as P13 I/O pin
1 Functions as TMIG input pin
P14/IRQ4/ADTRG pin function switch
0 Functions as P14 I/O pin
1 Functions as IRQ4/ADTRG input pin
P15/IRQ1/TMIC pin function switch
0 Functions as P15 I/O pin
1 Functions as IRQ1/TMIC input pin
P16/IRQ2 pin function switch
0 Functions as P16 I/O pin
1 Functions as IRQ2 input pin
P17/IRQ3/TMIF pin function switch
0 Functions as P17 I/O pin
1 Functions as IRQ3/TMIF input pin
Rev. 6.00 Aug 04, 2006 page 605 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PMR2—Port Mode Register 2
H'C9
I/O port
• H8/3847R Group and H8/3847S Group
Bit
7
6
5
4
3
2
1
0
—
—
POF1
—
—
SO1
SI1
SCK1
Initial value
1
1
0
1
1
0
0
0
Read/Write
—
—
R/W
—
—
R/W
R/W
R/W
P20/SCK1 pin function switch
0 Functions as P20 I/O pin
1 Functions as SCK1 I/O pin
P21/SI1 pin function switch
0 Functions as P21 I/O pin
1 Functions as SI1 input pin
P22/SO1 pin function switch
0 Functions as P22 I/O pin
1 Functions as SO1 output pin
P22/SO1 pin PMOS control
0 CMOS output
1 NMOS open-drain output
Rev. 6.00 Aug 04, 2006 page 606 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
• H8/38347 Group and H8/38447 Group
Bit
7
6
5
4
3
2
1
0
EXCL
—
POF1
—
—
SO1
SI1
SCK1
Initial value
0
1
0
1
1
0
0
0
Read/Write
R/W
—
R/W
—
—
R/W
R/W
R/W
P20/SCK1 pin function switch
0 Functions as P20 I/O pin
1 Functions as SCK1 I/O pin
P21/SI1 pin function switch
0 Functions as P21 I/O pin
1 Functions as SI1 input pin
P22/SO1 pin function switch
0 Functions as P22 I/O pin
1 Functions as SO1 output pin
P22/SO1 pin PMOS control
0 CMOS output
1 NMOS open-drain output
P31/UD/EXCL pin function switch
0 Functions as P31/UD I/O pin
1 Functions as EXCL input pin
Rev. 6.00 Aug 04, 2006 page 607 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PMR3—Port Mode Register 3
Bit
H'CA
7
6
5
4
3
2
1
0
AEVL
AEVH
WDCKS
NCS
IRQ0
RESO*
UD
PWM
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
I/O port
P30/PWM pin function switch
0 Functions as P30 I/O pin
1 Functions as PWM output pin
P31/UD pin function switch
0 Functions as P31 I/O pin
1 Functions as UD input pin
P32/RESO pin function switch
0 Functions as P32 I/O pin
1 Functions as RESO I/O pin
P43/IRQ0 pin function switch
0 Functions as P43 I/O pin
1 Functions as IRQ0 input pin
TMIG noise canceler select
0 Noise cancellation function not used
1 Noise cancellation function used
Watchdog timer switch
0 φ8192
1 φw/4
P36/AEVH pin function switch
0 Functions as P36 I/O pin
1 Functions as AEVH input pin
P37/AEVL pin function switch
0 Functions as P37 I/O pin
1 Functions as AEVL input pin
Note: * In the H8/38347 Group and H8/38447 Group this bit is reserved and cannot be written to.
Rev. 6.00 Aug 04, 2006 page 608 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PMR4—Port Mode Register 4
Bit
7
6
H'CB
5
4
3
I/O port
2
1
0
NMOD7 NMOD6 NMOD5 NMOD4 NMOD3 NMOD2 NMOD1 NMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0 P2n is CMOS output
1 P2n is NMOS open-drain output
(n = 7 to 0)
PMR5—Port Mode Register 5
Bit
H'CC
I/O port
7
6
5
4
3
2
1
0
WKP7
WKP6
WKP5
WKP4
WKP3
WKP2
WKP1
WKP0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P5n/WKPn/SEGn+1 pin function switch
0 Functions as P5n I/O pin
1 Functions as WKPn input pin
(n = 7 to 0)
Rev. 6.00 Aug 04, 2006 page 609 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PWCR—PWM Control Register
Bit
H'D0
7
6
5
4
3
2
14-bit PWM
1
0
Initial value
1
1
1
1
1
1
0
0
Read/Write
W
W
PWCR1 PWCR0
Clock select
0 The input clock is φ/2 (tφ* = 2/φ)
The conversion period is 16,384/φ, with a minimum modulation width of 1/φ
The input clock is φ/4 (tφ* = 4/φ)
The conversion period is 32,768/φ, with a minimum modulation width of 2/φ
1 The input clock is φ/8 (tφ* = 8/φ)
The conversion period is 65,536/φ, with a minimum modulation width of 4/φ
The input clock is φ/16 (tφ* = 16/φ)
The conversion period is 131,072/φ, with a minimum modulation width of 8/φ
Note: * tφ: Period of PWM input clock
PWDRU—PWM Data Register U
Bit
7
6
H'D1
5
4
3
2
14-bit PWM
1
0
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDUR1 PWDRU0
—
—
Initial value
1
1
0
0
0
0
0
0
Read/Write
—
—
W
W
W
W
W
W
Upper 6 bits of data for generating PWM waveform
PWDRL—PWM Data Register L
Bit
7
6
H'D2
5
4
3
2
14-bit PWM
1
0
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Lower 8 bits of data for generating PWM waveform
Rev. 6.00 Aug 04, 2006 page 610 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PDR1—Port Data Register 1
Bit
H'D4
I/O ports
7
6
5
4
3
2
1
0
P17
P16
P15
P14
P1 3
P1 2
P11
P10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 1 pins
PDR2—Port Data Register 2
Bit
H'D5
I/O ports
7
6
5
4
3
2
1
0
P27
P26
P25
P24
P23
P22
P21
P20
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 2 pins
PDR3—Port Data Register 3
Bit
H'D6
I/O ports
7
6
5
4
3
2
1
0
P3 7
P36
P35
P34
P33
P32
P31
P30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 3 pins
PDR4—Port Data Register 4
Bit
H'D7
I/O ports
7
6
5
4
3
2
1
0
P43
P42
P41
P40
Initial value
1
1
1
1
1
0
0
0
Read/Write
R
R/W
R/W
R/W
Pin P43 state is read
Data for port pins P42 to P40
Rev. 6.00 Aug 04, 2006 page 611 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PDR5—Port Data Register 5
Bit
H'D8
I/O ports
7
6
5
4
3
2
1
0
P5 7
P56
P55
P54
P53
P52
P51
P50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 5 pins
PDR6—Port Data Register 6
Bit
H'D9
I/O ports
7
6
5
4
3
2
1
0
P6 7
P66
P65
P64
P63
P62
P61
P60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 6 pins
PDR7—Port Data Register 7
Bit
H'DA
I/O ports
7
6
5
4
3
2
1
0
P7 7
P76
P75
P74
P73
P72
P71
P70
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 7 pins
PDR8—Port Data Register 8
Bit
H'DB
I/O ports
7
6
5
4
3
2
1
0
P8 7
P86
P85
P84
P83
P82
P81
P80
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 8 pins
Rev. 6.00 Aug 04, 2006 page 612 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PDR9—Port Data Register 9
Bit
H'DC
I/O ports
7
6
5
4
3
2
1
0
P97
P96
P95
P94
P93
P92
P91
P90
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data for port 9 pins
PDRA—Port Data Register A
Bit
H'DD
I/O ports
7
6
5
4
3
2
1
0
PA3
PA2
PA1
PA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
Data for port A pins
PDRB—Port Data Register B
Bit
Read/Write
H'DE
I/O ports
7
6
5
4
3
2
1
0
PB 7
PB 6
PB 5
PB 4
PB 3
PB 2
PB 1
PB 0
R
R
R
R
R
R
R
R
Data for port B pins
PDRC—Port Data Register C
Bit
Read/Write
H'DF
I/O ports
7
6
5
4
3
2
1
0
PC3
PC2
PC1
PC0
R
R
R
R
Data for port C pins
Rev. 6.00 Aug 04, 2006 page 613 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PUCR1—Port Pull-Up Control Register 1
Bit
7
6
5
H'E0
4
3
2
I/O ports
0
1
PUCR17 PUCR16 PUCR15 PUCR14 PUCR13 PUCR12 PUCR11 PUCR10
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 1 input pull-up MOS control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR1 specification is 0.
(Input port specification)
PUCR3—Port Pull-Up Control Register 3
Bit
7
6
5
H'E1
4
3
2
I/O ports
1
0
PUCR3 7 PUCR36 PUCR35 PUCR34 PUCR33 PUCR32 PUCR31 PUCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 3 input pull-up MOS control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR3 specification is 0.
(Input port specification)
Rev. 6.00 Aug 04, 2006 page 614 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PUCR5—Port Pull-Up Control Register 5
Bit
7
6
5
H'E2
4
3
2
I/O ports
0
1
PUCR5 7 PUCR56 PUCR55 PUCR54 PUCR53 PUCR52 PUCR51 PUCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 5 input pull-up MOS control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR5 specification is 0.
(Input port specification)
PUCR6—Port Pull-Up Control Register 6
Bit
7
6
5
H'E3
4
3
2
I/O ports
1
0
PUCR6 7 PUCR66 PUCR65 PUCR64 PUCR63 PUCR62 PUCR61 PUCR60
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Port 6 input pull-up MOS control
0 Input pull-up MOS is off
1 Input pull-up MOS is on
Note: When the PCR6 specification is 0.
(Input port specification)
Rev. 6.00 Aug 04, 2006 page 615 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PCR1—Port Control Register 1
Bit
H'E4
I/O ports
7
6
5
4
3
2
1
0
PCR17
PCR16
PCR15
PCR14
PCR13
PCR1 2
PCR11
PCR10
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 1 input/output select
0 Input pin
1 Output pin
PCR2—Port Control Register 2
Bit
H'E5
I/O ports
7
6
5
4
3
2
1
0
PCR27
PCR26
PCR25
PCR24
PCR23
PCR22
PCR21
PCR20
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 2 input/output select
0 Input pin
1 Output pin
PCR3—Port Control Register 3
Bit
H'E6
I/O ports
7
6
5
4
3
2
1
0
PCR3 7
PCR3 6
PCR3 5
PCR3 4
PCR3 3
PCR32
PCR31
PCR30
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 3 input/output select
0 Input pin
1 Output pin
Rev. 6.00 Aug 04, 2006 page 616 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PCR4—Port Control Register 4
Bit
H'E7
I/O ports
7
6
5
4
3
2
1
0
—
—
—
—
—
PCR42
PCR41
PCR40
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
Port 4 input/output select
0 Input pin
1 Output pin
PCR5—Port Control Register 5
Bit
H'E8
I/O ports
7
6
5
4
3
2
1
0
PCR57
PCR56
PCR55
PCR54
PCR53
PCR52
PCR51
PCR50
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 5 input/output select
0 Input pin
1 Output pin
PCR6—Port Control Register 6
Bit
H'E9
I/O ports
7
6
5
4
3
2
1
0
PCR6 7
PCR6 6
PCR6 5
PCR6 4
PCR6 3
PCR6 2
PCR6 1
PCR6 0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 6 input/output select
0 Input pin
1 Output pin
Rev. 6.00 Aug 04, 2006 page 617 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PCR7—Port Control Register 7
Bit
H'EA
I/O ports
7
6
5
4
3
2
1
0
PCR77
PCR76
PCR75
PCR74
PCR73
PCR72
PCR71
PCR70
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 7 input/output select
0 Input pin
1 Output pin
PCR8—Port Control Register 8
Bit
H'EB
I/O ports
7
6
5
4
3
2
1
0
PCR87
PCR86
PCR85
PCR84
PCR83
PCR82
PCR81
PCR80
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 8 input/output select
0 Input pin
1 Output pin
PCR9—Port Control Register 9
Bit
H'EC
I/O ports
7
6
5
4
3
2
1
0
PCR97
PCR96
PCR95
PCR94
PCR93
PCR92
PCR91
PCR90
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Port 9 input/output select
0 Input pin
1 Output pin
Rev. 6.00 Aug 04, 2006 page 618 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
PCRA—Port Control Register A
Bit
H'ED
I/O ports
7
6
5
4
3
2
—
—
—
—
PCRA 3
PCRA 2
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
W
W
W
W
1
0
PCRA 1 PCRA 0
Port A input/output select
0 Input pin
1 Output pin
Rev. 6.00 Aug 04, 2006 page 619 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
SYSCR1—System Control Register 1
Bit
H'F0
System control
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
LSON
MA1
MA0
Initial value
0
0
0
0
0
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Active (medium-speed)
mode clock select
0 0 φ osc /16
1 φ osc /32
1 0 φ osc /64
1 φ osc/128
Low speed on flag
0 The CPU operates on the system clock (φ)
1 The CPU operates on the subclock (φ SUB)
Standby timer select 2 to 0
0 0 0 Wait time = 8,192 states
1 Wait time = 16,384 states
1 0 Wait time = 32,768 states
1 Wait time = 65,536 states
1 0 0 Wait time = 131,072 states
1 Wait time = 2 states
1 0 Wait time = 8 states
1 Wait time = 16 states
Software standby
0 • When a SLEEP instruction is executed in active mode, a transition is
made to sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to subsleep mode
1 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode or watch mode
• When a SLEEP instruction is executed in subactive mode, a transition
is made to watch mode
Rev. 6.00 Aug 04, 2006 page 620 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
SYSCR2—System Control Register 2
Bit
H'F1
System control
7
6
5
4
3
2
1
0
NESEL
DTON
MSON
SA1
SA0
Initial value
1
1
1
1
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
Subactive mode clock select
Medium speed on flag
0 0 φ W/8
1 φ W/4
1 * φ W/2
*: Don't care
0 Operates in active (high-speed) mode
1 Operates in active (medium-speed) mode
Direct transfer on flag
0 • When a SLEEP instruction is executed in active mode, a transition is
made to standby mode, watch mode, or sleep mode
• When a SLEEP instruction is executed in subactive mode, a transition is
made to watch mode or subsleep mode
1 • When a SLEEP instruction is executed in active (high-speed) mode, a direct
transition is made to active (medium-speed) mode if SSBY = 0, MSON = 1, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in active (medium-speed) mode, a direct
transition is made to active (high-speed) mode if SSBY = 0, MSON = 0, and
LSON = 0, or to subactive mode if SSBY = 1, TMA3 = 1, and LSON = 1
• When a SLEEP instruction is executed in subactive mode, a direct
transition is made to active (high-speed) mode if SSBY = 1, TMA3 = 1, LSON = 0,
and MSON = 0, or to active (medium-speed) mode if SSBY = 1, TMA3 = 1,
LSON = 0, and MSON = 1
Noise elimination sampling frequency select
0 Sampling rate is φ OSC/16
1 Sampling rate is φ OSC/4
Rev. 6.00 Aug 04, 2006 page 621 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
IEGR—IRQ Edge Select Register
Bit
H'F2
System control
7
6
5
4
3
2
1
0
IEG4
IEG3
IEG2
IEG1
IEG0
Initial value
0
1
1
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
IRQ0 edge select
0 Falling edge of IRQ0 pin input is detected
1 Rising edge of IRQ0 pin input is detected
IRQ1 edge select
0 Falling edge of IRQ1, TMIC pin input is detected
1 Rising edge of IRQ1, TMIC pin input is detected
IRQ2 edge select
0 Falling edge of IRQ2 pin input is detected
1 Rising edge of IRQ2 pin input is detected
IRQ3 edge select
0 Falling edge of IRQ3, TMIF pin input is detected
1 Rising edge of IRQ3, TMIF pin input is detected
IRQ4 edge select
0 Falling edge of IRQ4 pin and ADTRG pin is detected
1 Rising edge of IRQ4 pin and ADTRG pin is detected
Rev. 6.00 Aug 04, 2006 page 622 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
IENR1—Interrupt Enable Register 1
Bit
H'F3
System control
7
6
5
4
3
2
1
0
IENTA
IENS1
IENWP
IEN4
IEN3
IEN2
IEN1
IEN0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ4 to IRQ0 interrupt enable
0 Disables IRQ4 to IRQ0 interrupt requests
1 Enables IRQ4 to IRQ0 interrupt requests
Wakeup interrupt enable
0 Disables WKP7 to WKP0 interrupt requests
1 Enables WKP7 to WKP0 interrupt requests
SCI1 interrupt enable
0 Disables SCI1 interrupt requests
1 Enables SCI1 interrupt requests
Timer A interrupt enable
0 Disables timer A interrupt requests
1 Enables timer A interrupt requests
Rev. 6.00 Aug 04, 2006 page 623 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
IENR2—Interrupt Enable Register 2
Bit
7
6
5
4
IENDT
IENAD
—
IENTG
H'F4
3
2
IENTFH IENTFL
1
0
IENTC
IENEC
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
System control
Asynchronous event counter interrupt enable
0 Disables asynchronous event counter
interrupt requests
1 Enables asynchronous event counter
interrupt requests
Timer C interrupt enable
0 Disables timer C interrupt requests
1 Enables timer C interrupt requests
Timer FL interrupt enable
0 Disables timer FL interrupt requests
1 Enables timer FL interrupt requests
Timer FH interrupt enable
0 Disables timer FH interrupt requests
1 Enables timer FH interrupt requests
Timer G interrupt enable
0 Disables timer G interrupt requests
1 Enables timer G interrupt requests
A/D converter interrupt enable
0 Disables A/D converter interrupt requests
1 Enables A/D converter interrupt requests
Direct transition interrupt enable
0 Disables direct transition interrupt requests
1 Enables direct transition interrupt requests
Rev. 6.00 Aug 04, 2006 page 624 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
IRR1—Interrupt Request Register 1
Bit
H'F6
System control
7
6
5
4
3
2
1
0
IRRTA
IRRS1
IRRI4
IRRI3
IRRI2
IRRI1
IRRI0
Initial value
0
0
1
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
IRQ4 to IRQ0 interrupt request flags
0 [Clearing condition]
When IRRIn = 1, it is cleared by writing 0
1 [Setting condition]
When pin IRQn is designated for interrupt
input and the designated signal edge is input
(n = 4 to 0)
SCI1 interrupt request flag
0 [Clearing condition]
When IRRS1 = 1, it is cleared by writing 0
1 [Setting condition]
When SCI1 completes transfer
Timer A interrupt request flag
0 [Clearing condition]
When IRRTA = 1, it is cleared by writing 0
1 [Setting condition]
When the timer A counter value overflows (from H'FF to H'00)
Note: * Bits 7, 6, and 4 to 0 can only be written with 0, for flag clearing.
Rev. 6.00 Aug 04, 2006 page 625 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
IRR2—Interrupt Request Register 2
Bit
H'F7
7
6
5
4
IRRDT
IRRAD
—
IRRTG
3
1
0
IRRTC
IRREC
2
IRRTFH IRRTFL
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/W
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
System control
Asynchronous event counter interrupt request flag
0 [Clearing condition]
When IRREC = 1, it is cleared by writing 0
1 [Setting condition]
When the asynchronous event counter value overflows
Timer C interrupt request flag
0 [Clearing condition]
When IRRTC = 1, it is cleared by writing 0
1 [Setting condition]
When the timer C counter value overflows
(from H'FF to H'00) or underflows (from H'00 to H'FF)
Timer FL interrupt request flag
0 [Clearing condition]
When IRRTFL = 1, it is cleared by writing 0
1 [Setting condition]
When counter FL and output compare register FL
match in 8-bit timer mode
Timer FH interrupt request flag
0 [Clearing condition]
When IRRTFH = 1, it is cleared by writing 0
1 [Setting condition]
When counter FH and output compare register FH match
in 8-bit timer mode, or when 16-bit counters FL and FH
and output compare registers FL and FH match in 16-bit timer mode
Timer G interrupt request flag
0 [Clearing condition]
When IRRTG = 1, it is cleared by writing 0
1 [Setting condition]
When the TMIG pin is designated for TMIG input and
the designated signal edge is input
A/D converter interrupt request flag
0 [Clearing condition]
When IRRAD = 1, it is cleared by writing 0
1 [Setting condition]
When the A/D converter completes conversion and
ADSF is reset
Direct transition interrupt request flag
0 [Clearing condition]
When IRRDT = 1, it is cleared by writing 0
1 [Setting condition]
When a SLEEP instruction is executed while DTON is
set to 1, and a direct transition is made
Note: * Bits 7, 6 and 4 to 0 can only be written with 0, for flag clearing.
Rev. 6.00 Aug 04, 2006 page 626 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
WPR—Wakeup Interrupt Request Register
Bit
H'F9
System control
7
6
5
4
3
2
1
0
IWPF7
IWPF6
IWPF5
IWPF4
IWPF3
IWPF2
IWPF1
IWPF0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Wakeup interrupt request register
0 [Clearing condition]
When IWPFn = 1, it is cleared by writing 0
1 [Setting condition]
When pin WKPn is designated for wakeup input and a
falling edge is input at that pin
(n = 7 to 0)
Note: * All bits can only be written with 0, for flag clearing.
Rev. 6.00 Aug 04, 2006 page 627 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
CKSTPR1—Clock Stop Register 1
Bit
7
6
H'FA
4
5
3
2
System control
1
0
S1CKSTP S31CKSTP S32CKSTP ADCKSTP TGCKSTP TFCKSTP TCCKSTP TACKSTP
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Timer A module standby mode control
0 Timer A is set to module standby mode
1 Timer A module standby mode is cleared
Timer C module standby mode control
0 Timer C is set to module standby mode
1 Timer C module standby mode is cleared
Timer F module standby mode control
0 Timer F is set to module standby mode
1 Timer F module standby mode is cleared
Timer G interrupt enable
0 Timer G is set to module standby mode
1 Timer G module standby mode is cleared
A/D converter module standby mode control
0 A/D converter is set to module standby mode
1 A/D converter module standby mode is cleared
SCI3-2 module standby mode control
0 SCI3-2 is set to module standby mode
1 SCI3-2 module standby mode is cleared
SCI3-1 module standby mode control
0 SCI3-1 is set to module standby mode
1 SCI3-1 module standby mode is cleared
SCI1 module standby mode control
0 SCI1 is set to module standby mode
1 SCI1 module standby mode is cleared
Rev. 6.00 Aug 04, 2006 page 628 of 680
REJ09B0145-0600
Appendix B Internal I/O Registers
CKSTPR2—Clock Stop Register 2
Bit
H'FB
7
6
5
4
3
System control
2
1
0
—
—
—
—
Initial value
1
1
1
1
1
1
1
1
Read/Write
—
—
—
—
R/W
R/W
R/W
R/W
AECKSTP WDCKSTP PWCKSTP LDCKSTP
LCD module standby mode control
0 LCD is set to module standby mode
1 LCD module standby mode is cleared
PWM module standby mode control
0 PWM is set to module standby mode
1 PWM module standby mode is cleared
WDT module standby mode control
0 WDT is set to module standby mode
1 WDT module standby mode is cleared
Asynchronous event counter module standby mode control
0 Asynchronous event counter is set to module standby mode
1 Asynchronous event counter module standby mode is cleared
Rev. 6.00 Aug 04, 2006 page 629 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
C.1
Block Diagrams of Port 1
SBY
(low level
during reset
and in standby
mode)
PUCR1n
VCC
VCC
PDR1n
P1n
PCR1n
VSS
Internal data bus
PMR1n
IRQn−4/n*
PDR1:
PCR1:
PMR1:
PUCR1:
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
* n = 7 to 5
n − 4, n = 4
n
Figure C.1 (a) Port 1 Block Diagram (Pins P17 to P14)
Rev. 6.00 Aug 04, 2006 page 630 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
PUCR13
VCC
PMR13
PDR13
P13
VSS
Internal data bus
VCC
PCR13
Timer G
module
TMIG
Figure C.1 (b) Port 1 Block Diagram (Pin P13)
Rev. 6.00 Aug 04, 2006 page 631 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
Timer F
module
SBY
TMOFH (P12)
TMOFL (P11)
PUCR1n
VCC
PMR1n
PDR1n
P1n
PCR1n
VSS
PDR1:
PCR1:
PMR1:
PUCR1:
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
n= 2, 1
Figure C.1 (c) Port 1 Block Diagram (Pin P12, P11)
Rev. 6.00 Aug 04, 2006 page 632 of 680
REJ09B0145-0600
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
Timer A
module
SBY
TMOW
PUCR10
VCC
VCC
PDR10
P10
PCR10
VSS
PDR1:
PCR1:
PMR1:
PUCR1:
Internal data bus
PMR10
Port data register 1
Port control register 1
Port mode register 1
Port pull-up control register 1
Figure C.1 (d) Port 1 Block Diagram (Pin P10)
Rev. 6.00 Aug 04, 2006 page 633 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
C.2
Block Diagrams of Port 2
SBY
PMR4n
PDR2n
P2n
Internal data bus
VCC
PCR2n
VSS
PDR2: Port data register 2
PCR2: Port control register 2
PMR4: Port mode register 4
n = 7 to 3
Figure C.2 (a-1) Port 2 Block Diagram (Pins P27 to P23, Not Including P24 in the F-ZTAT
Version of the H8/38347 Group and H8/38447 Group)
Rev. 6.00 Aug 04, 2006 page 634 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
Reset signal
(low level during reset)
SBY
PMR44
VCC
PDR24
P24
Internal data bus
VCC
PCR24
VSS
PDR2: Port data register 2
PCR2: Port control register 2
PMR4: Port mode register 4
Figure C.2 (a-2) Port 2 Block Diagram (Pin P24 in the F-ZTAT Version of the H8/38347
Group and H8/38447 Group)
Rev. 6.00 Aug 04, 2006 page 635 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SCI1 module
SO1
SBY
PMR25
PMR42
PMR22
P22
PDR22
VSS
PCR22
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C.2 (b) Port 2 Block Diagram (Pin P22)
Rev. 6.00 Aug 04, 2006 page 636 of 680
REJ09B0145-0600
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
SBY
PMR41
PMR21
P21
PDR21
VSS
Internal data bus
VCC
PCR21
SCI module
SI
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C.2 (c) Port 2 Block Diagram (Pin P21)
Rev. 6.00 Aug 04, 2006 page 637 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SCI module
EXCK
SCK0
SCK1
SBY
PMR40
PMR20
P20
PDR20
VSS
PCR20
PDR2: Port data register 2
PCR2: Port control register 2
PMR2: Port mode register 2
PMR4: Port mode register 4
Figure C.2 (d) Port 2 Block Diagram (Pin P20)
Rev. 6.00 Aug 04, 2006 page 638 of 680
REJ09B0145-0600
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
C.3
Block Diagrams of Port 3
SBY
PUCR3n
VCC
PMR3n
P3n
PDR3n
VSS
Internal data bus
VCC
PCR3n
AEC module
AEVH(P36)
AEVL(P37)
PDR3:
Port data register 3
PCR3:
Port control register 3
PMR3:
Port mode register 3
PUCR3: Port pull-up control register 3
n=7 to 6
Figure C.3 (a) Port 3 Block Diagram (Pin P37 to P36)
Rev. 6.00 Aug 04, 2006 page 639 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
PUCR35
SCINV1
VCC
SCI31 module
VCC
TE31
P35
PDR35
PCR35
VSS
PDR3: Port data register 3
PCR3: Port control register 3
PUCR3: Port pull-up control register 3
SCINV1: Bit 1 of serial port control register (SPCR)
Figure C.3 (b) Port 3 Block Diagram (Pin P35)
Rev. 6.00 Aug 04, 2006 page 640 of 680
REJ09B0145-0600
Internal data bus
TXD31
Appendix C I/O Port Block Diagrams
SBY
PUCR34
VCC
VCC
SCI31 module
RE31
P34
PDR34
PCR34
VSS
Internal data bus
RXD31
SCINV0
PDR3: Port data register 3
PCR3: Port control register 3
PUCR3: Port pull-up control register 3
SCINV0: Bit 0 of serial port control register (SPCR)
Figure C.3 (c) Port 3 Block Diagram (Pin P34)
Rev. 6.00 Aug 04, 2006 page 641 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
PUCR33
SCI31 module
VCC
SCKIE31
SCKOE31
VCC
SCKO31
SCKI31
P33
PCR33
VSS
PDR3: Port data register 3
PCR3: Port control register 3
PUCR3: Port pull-up control register 3
Figure C.3 (d) Port 3 Block Diagram (Pin P33)
Rev. 6.00 Aug 04, 2006 page 642 of 680
REJ09B0145-0600
Internal data bus
PDR33
Appendix C I/O Port Block Diagrams
SBY
RESO
PUCR32
VCC
PMR32
P32
PDR32
VSS
Internal data bus
VCC
PCR32
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure C.3 (e-1) Port 3 Block Diagram (Pin P32, H8/3847R Group and H8/3847S Group)
Rev. 6.00 Aug 04, 2006 page 643 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
PUCR32
VCC
PMR32
P32
PDR32
VSS
Internal data bus
VCC
PCR32
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure C.3 (e-2) Port 3 Block Diagram (Pin P32, H8/38347 Group and H8/38447 Group)
Rev. 6.00 Aug 04, 2006 page 644 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
PUCR31
VCC
PMR31
PDR31
P31
VSS
Internal data bus
VCC
PCR31
Timer C
module
UD
PDR3:
PCR3:
PMR3:
PUCR3:
Port data register 3
Port control register 3
Port mode register 3
Port pull-up control register 3
Figure C.3 (f-1) Port 3 Block Diagram (Pin P31, H8/3847R Group and H8/3847S Group))
Rev. 6.00 Aug 04, 2006 page 645 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
PMR27
PUCR31
VCC
PMR31
PDR31
P31
VSS
Internal data bus
VCC
PCR31
Timer C
module
UD
Subclock
oscillator
Clock
input
PDR3:
PCR3:
PMR2:
PMR3:
PUCR3:
Port data register 3
Port control register 3
Port mode register 2
Port mode register 3
Port pull-up control register 3
Figure C.3 (f-2) Port 3 Block Diagram (Pin P31, H8/38347 Group and H8/38447 Group)
Rev. 6.00 Aug 04, 2006 page 646 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
PWM module
SBY
PWM
PUCR30
VCC
PMR30
P30
PDR30
VSS
Internal data bus
VCC
PCR30
PDR3: Port data register 3
PCR3: Port control register 3
PMR3: Port mode register 3
PUCR3: Port pull-up control register 3
Figure C.3 (g) Port 3 Block Diagram (Pin P30)
Rev. 6.00 Aug 04, 2006 page 647 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
C.4
Block Diagrams of Port 4
Internal data bus
PMR33
P43
IRQ0
PMR3: Port mode register 3
Figure C.4 (a) Port 4 Block Diagram (Pin P43)
Rev. 6.00 Aug 04, 2006 page 648 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
SCINV3
SCI32 module
VCC
TE32
TXD32
P42
PCR42
VSS
Internal data bus
PDR42
PDR4: Port data register 4
PCR4: Port control register 4
SCINV3: Bit 3 of serial port control register (SPCR)
Figure C.4 (b) Port 4 Block Diagram (Pin P42)
Rev. 6.00 Aug 04, 2006 page 649 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
SBY
VCC
SCI32 module
RE32
RXD32
P41
PCR41
VSS
SCINV2
PDR4: Port data register 4
PCR4: Port control register 4
SCINV2: Bit 2 of serial port control register (SPCR)
Figure C.4 (c) Port 4 Block Diagram (Pin P41)
Rev. 6.00 Aug 04, 2006 page 650 of 680
REJ09B0145-0600
Internal data bus
PDR41
Appendix C I/O Port Block Diagrams
SBY
SCI32 module
SCKIE32
SCKOE32
VCC
SCKO32
SCKI32
P40
PCR40
VSS
Internal data bus
PDR40
PDR4: Port data register 4
PCR4: Port control register 4
Figure C.4 (d) Port 4 Block Diagram (Pin P40)
Rev. 6.00 Aug 04, 2006 page 651 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
C.5
Block Diagram of Port 5
SBY
PUCR5n
VCC
VCC
P5n
PDR5n
VSS
PCR5n
Internal data bus
PMR5n
WKPn
PDR5: Port data register 5
PCR5: Port control register 5
PMR5: Port mode register 5
PUCR5: Port pull-up control register 5
n = 7 to 0
Figure C.5 Port 5 Block Diagram
Rev. 6.00 Aug 04, 2006 page 652 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
C.6
Block Diagram of Port 6
SBY
VCC
PDR6n
VCC
PCR6n
P6n
Internal data bus
PUCR6n
VSS
PDR6: Port data register 6
PCR6: Port control register 6
PUCR6: Port pull-up control register 6
n = 7 to 0
Figure C.6 Port 6 Block Diagram
Rev. 6.00 Aug 04, 2006 page 653 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
C.7
Block Diagram of Port 7
SBY
PDR7n
PCR7n
P7n
VSS
PDR7: Port data register 7
PCR7: Port control register 7
n = 7 to 0
Figure C.7 Port 7 Block Diagram
Rev. 6.00 Aug 04, 2006 page 654 of 680
REJ09B0145-0600
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
C.8
Block Diagrams of Port 8
VCC
PDR8n
PCR8n
P8n
Internal data bus
SBY
VSS
PDR8:
Port data register 8
PCR8:
Port control register 8
n= 7 to 0
Figure C.8 Port 8 Block Diagram
Rev. 6.00 Aug 04, 2006 page 655 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
C.9
Block Diagram of Port 9
SBY
PDR9n
PCR9n
P9n
VSS
PDR9: Port data register 9
PCR9: Port control register 9
n = 7 to 0
Figure C.9 Port 9 Block Diagram
Rev. 6.00 Aug 04, 2006 page 656 of 680
REJ09B0145-0600
Internal data bus
VCC
Appendix C I/O Port Block Diagrams
C.10
Block Diagram of Port A
SBY
VCC
PCRAn
PAn
Internal data bus
PDRAn
VSS
PDRA: Port data register A
PCRA: Port control register A
n = 3 to 0
Figure C.10 Port A Block Diagram
Rev. 6.00 Aug 04, 2006 page 657 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
C.11
Block Diagram of Port B
Internal
data bus
PBn
A/D module
DEC
AMR3 to AMR0
VIN
n = 7 to 0
Figure C.11 Port B Block Diagram
Rev. 6.00 Aug 04, 2006 page 658 of 680
REJ09B0145-0600
Appendix C I/O Port Block Diagrams
Block Diagram of Port C
Internal data bus
C.12
PCn
A/D module
DEC
AMR3 to 0
VIN
n = 3 to 0
Figure C.12 Port C Block Diagram
Rev. 6.00 Aug 04, 2006 page 659 of 680
REJ09B0145-0600
Appendix D Port States in the Different Processing States
Appendix D Port States in the Different Processing States
Table D.1
Port
Port States Overview
Reset
Sleep
Subsleep
Standby
Subactive
Active
Retained
Retained
HighRetained
impedance*1
Functions
Functions
P27 to P20 HighRetained
impedance*3
Retained
Highimpedance
Retained
Functions
Functions
P37 to P30 HighRetained
impedance*2
Retained
HighRetained
impedance*1
Functions
Functions
P43 to P40 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P57 to P50 Highimpedance
Retained
Retained
HighRetained
impedance*1
Functions
Functions
P67 to P60 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P77 to P70 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P87 to P80 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
P97 to P90 Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
PA3 to
PA0
Highimpedance
Retained
Retained
Highimpedance
Retained
Functions
Functions
PB7 to
PB0
Highimpedance
HighHighimpedance impedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
PC3 to
PC0
Highimpedance
HighHighimpedance impedance
Highimpedance
Highimpedance
Highimpedance
Highimpedance
P17 to P10 Highimpedance
Watch
Notes: 1. High level output when MOS pull-up is in on state.
2. Reset output from P32 pin only (H8/3847R Group and H8/3847S Group).
3. On-chip pull-up MOS turns on for pin P24 only (F-ZTAT Version of the H8/38347 Group
and H8/38447 Group).
Rev. 6.00 Aug 04, 2006 page 660 of 680
REJ09B0145-0400
Appendix E List of Product Codes
Appendix E List of Product Codes
Table E.1
Product Code Lineup
Product Type
Product Code
Mark Code
H8/3847R H8/3842R Mask
Regular
Group
ROM
products
versions
HD6433842RH
HD6433842R(***)H 100-pin QFP (FP-100B)
HD6433842RF
HD6433842R(***)F 100-pin QFP (FP-100A)
HD6433842RX
HD6433842R(***)X 100-pin TQFP (TFP-100B)
HD6433842RW
HD6433842R(***)W 100-pin TQFP (TFP100G)
Package (Package Code)
HCD6433842R
Widerange
specification
products
HD6433842RD
HD6433842R(***)H 100-pin QFP (FP-100B)
HD6433842RE
HD6433842R(***)F 100-pin QFP (FP-100A)
HD6433842RL
HD6433842R(***)X 100-pin TQFP (TFP-100B)
H8/3843R Mask
Regular
ROM
products
versions
HD6433843RH
Die
HD6433842RWI HD6433842R(***)W 100-pin TQFP (TFP100G)
HD6433843R(***)H 100-pin QFP (FP-100B)
HD6433843RF
HD6433843R(***)F 100-pin QFP (FP-100A)
HD6433843RX
HD6433843R(***)X 100-pin TQFP (TFP-100B)
HD6433843RW
HD6433843R(***)W 100-pin TQFP (TFP100G)
HCD6433843R
Widerange
specification
products
HD6433843RD
HD6433843R(***)H 100-pin QFP (FP-100B)
H8/3844R Mask
Regular
ROM
products
versions
HD6433844RH
HD6433844R(***)H 100-pin QFP (FP-100B)
HD6433844RF
HD6433844R(***)F 100-pin QFP (FP-100A)
Widerange
specification
products
Die
HD6433843RE
HD6433843R(***)F 100-pin QFP (FP-100A)
HD6433843RL
HD6433843R(***)X 100-pin TQFP (TFP-100B)
HD6433843RWI HD6433843R(***)W 100-pin TQFP (TFP100G)
HD6433844RX
HD6433844R(***)X 100-pin TQFP (TFP-100B)
HD6433844RW
HD6433844R(***)W 100-pin TQFP (TFP100G)
HCD6433844R
HD6433844RD
HD6433844R(***)H 100-pin QFP (FP-100B)
HD6433844RE
HD6433844R(***)F 100-pin QFP (FP-100A)
HD6433844RL
HD6433844R(***)X 100-pin TQFP (TFP-100B)
Die
HD6433844RWI HD6433844R(***)W 100-pin TQFP (TFP100G)
Rev. 6.00 Aug 04, 2006 page 661 of 680
REJ09B0145-0600
Appendix E List of Product Codes
Product Type
Product Code
Mark Code
H8/3847R H8/3845R Mask
Regular
Group
ROM
products
versions
HD6433845RH
HD6433845R(***)H 100-pin QFP (FP-100B)
HD6433845RF
HD6433845R(***)F 100-pin QFP (FP-100A)
HD6433845RX
HD6433845R(***)X 100-pin TQFP (TFP-100B)
HD6433845RW
HD6433845R(***)W 100-pin TQFP (TFP100G)
Package (Package Code)
HCD6433845R
Mask
WideROM
range
versions specification
products
HD6433845RD
HD6433845R(***)H 100-pin QFP (FP-100B)
HD6433845RE
HD6433845R(***)F 100-pin QFP (FP-100A)
HD6433845RL
HD6433845R(***)X 100-pin TQFP (TFP-100B)
H8/3846R Mask
Regular
ROM
products
versions
HD6433846RH
HD6433846R(***)H 100-pin QFP (FP-100B)
HD6433846RF
HD6433846R(***)F 100-pin QFP (FP-100A)
Die
HD6433845RWI HD6433845R(***)W 100-pin TQFP (TFP100G)
HD6433846RX
HD6433846R(***)X 100-pin TQFP (TFP-100B)
HD6433846RW
HD6433846R(***)W 100-pin TQFP (TFP100G)
HCD6433846R
Widerange
specification
products
HD6433846RD
HD6433846R(***)H 100-pin QFP (FP-100B)
H8/3847R Mask
Regular
ROM
products
versions
HD6433847RH
Die
HD6433846RE
HD6433846R(***)F 100-pin QFP (FP-100A)
HD6433846RL
HD6433846R(***)X 100-pin TQFP (TFP-100B)
HD6433846RWI HD6433846R(***)W 100-pin TQFP (TFP100G)
HD6433847R(***)H 100-pin QFP (FP-100B)
HD6433847RF
HD6433847R(***)F 100-pin QFP (FP-100A)
HD6433847RX
HD6433847R(***)X 100-pin TQFP (TFP-100B)
HD6433847RW
HD6433847R(***)W 100-pin TQFP (TFP100G)
HCD6433847R
Widerange
specification
products
HD6433847RD
HD6433847R(***)H 100-pin QFP (FP-100B)
ZTAT
Regular
versions products
HD6473847RH
HD6473847RH
100-pin QFP (FP-100B)
HD6473847RF
HD6473847RF
100-pin QFP (FP-100A)
HD6473847RX
HD6473847RX
100-pin TQFP (TFP-100B)
HD6473847RW
HD6473847RW
100-pin TQFP(TFP-100G)
HD6473847RD
HD6473847RH
100-pin QFP (FP-100B)
HD6473847RE
HD6473847RF
100-pin QFP (FP-100A)
HD6473847RL
HD6473847RX
100-pin TQFP (TFP-100B)
Widerange
specification
products
Die
HD6433847RE
HD6433847R(***)F 100-pin QFP (FP-100A)
HD6433847RL
HD6433847R(***)X 100-pin TQFP (TFP-100B)
HD6433847RWI HD6433847R(***)W 100-pin TQFP(TFP-100G)
HD6473847RWI HD6473847RW
Rev. 6.00 Aug 04, 2006 page 662 of 680
REJ09B0145-0400
100-pin TQFP (TFP100G)
Appendix E List of Product Codes
Product Type
Product Code
Mark Code
H8/3847S H8/3844S Mask
Regular
Group
ROM
products
versions
HD6433844SH
HD6433844S(***)H 100-pin QFP (FP-100B)
HD6433844SX
HD6433844S(***)X 100-pin TQFP (TFP-100B)
HD6433844SW
HD6433844S(***)W 100-pin TQFP (TFP100G)
Package (Package Code)
HCD6433844S
Widerange
specification
products
HD6433844SD
HD6433844S(***)H 100-pin QFP (FP-100B)
HD6433844SL
HD6433844S(***)X 100-pin TQFP (TFP-100B)
HD6433844SWI
HD6433844S(***)W 100-pin TQFP (TFP100G)
H8/3845S Mask
Regular
ROM
products
versions
HD6433845SH
HD6433845S(***)H 100-pin QFP (FP-100B)
HD6433845SX
HD6433845S(***)X 100-pin TQFP (TFP-100B)
HD6433845SW
HD6433845S(***)W 100-pin TQFP (TFP100G)
Die
HCD6433845S
Widerange
specification
products
HD6433845SD
HD6433845S(***)H 100-pin QFP (FP-100B)
HD6433845SL
HD6433845S(***)X 100-pin TQFP (TFP-100B)
HD6433845SWI
HD6433845S(***)W 100-pin TQFP (TFP100G)
H8/3846S Mask
Regular
ROM
products
versions
HD6433846SH
HD6433846S(***)H 100-pin QFP (FP-100B)
HD6433846RX
HD6433846S(***)X 100-pin TQFP (TFP-100B)
HD6433846SW
HD6433846S(***)W 100-pin TQFP (TFP100G)
Die
HCD6333846S
Widerange
specification
products
HD6433846SD
HD6433846S(***)H 100-pin QFP (FP-100B)
HD6433846SL
HD6433846S(***)X 100-pin TQFP (TFP-100B)
HD6433846SWI
HD6433846S(***)W 100-pin TQFP (TFP100G)
H8/3847S Mask
Regular
ROM
products
versions
HD6433847SH
HD6433847S(***)H 100-pin QFP (FP-100B)
Widerange
specification
products
Die
HD6433847SX
HD6433847S(***)X 100-pin TQFP (TFP-100B)
HD6433847SW
HD6433847S(***)W 100-pin TQFP (TFP100G)
HCD6433847S
HD6433847SD
HD6433847S(***)H 100-pin QFP (FP-100B)
HD6433847SL
HD6433847S(***)X 100-pin TQFP (TFP-100B)
HD6433847SWI
HD6433847S(***)W 100-pin TQFP (TFP100G)
Die
Rev. 6.00 Aug 04, 2006 page 663 of 680
REJ09B0145-0600
Appendix E List of Product Codes
Product Type
H8/38347 H8/38342 Mask
Regular
Group
ROM
products
versions
Widerange
specification
products
H8/38343 Mask
Regular
ROM
products
versions
Widerange
specification
products
H8/38344 Mask
Regular
ROM
products
versions
Widerange
specification
products
F-ZTAT Regular
versions products
Widerange
specification
products
Product Code
Mark Code
Package (Package Code)
HD64338342H
38342H
100-pin QFP (FP-100B)
HD64338342W
38342W
100-pin TQFP (TFP100G)
HD64338342X
38342X
100-pin TQFP (TFP-100B)
HCD64338342
Die
HD64338342HW 38342H
100-pin QFP (FP-100B)
HD64338342WW 38342W
100-pin TQFP (TFP100G)
HD64338342XW 38342X
100-pin TQFP (TFP-100B)
HD64338343H
38343H
100-pin QFP (FP-100B)
HD64338343W
38343W
100-pin TQFP (TFP100G)
HD64338343X
38343X
100-pin TQFP (TFP-100B)
HCD64338343
Die
HD64338343HW 38343H
100-pin QFP (FP-100B)
HD64338343WW 38343W
100-pin TQFP (TFP100G)
HD64338343XW 38343X
100-pin TQFP (TFP-100B)
HD64338344H
38344H
100-pin QFP (FP-100B)
HD64338344W
38344W
100-pin TQFP (TFP100G)
HD64338344X
38344X
100-pin TQFP (TFP-100B)
HCD64338344
Die
HD64338344HW 38344H
100-pin QFP (FP-100B)
HD64338344WW 38344W
100-pin TQFP (TFP100G)
HD64338344XW 38344X
100-pin TQFP (TFP-100B)
HD64F38344H
F38344H
100-pin QFP (FP-100B)
HD64F38344W
F38344W
100-pin TQFP (TFP100G)
HD64F38344X
F38344X
100-pin TQFP (TFP-100B)
HD64F38344HW F38344H
100-pin QFP (FP-100B)
HD64F38344W
W
100-pin TQFP (TFP100G)
F38344W
HD64F38344XW F38344X
Rev. 6.00 Aug 04, 2006 page 664 of 680
REJ09B0145-0400
100-pin TQFP (TFP-100B)
Appendix E List of Product Codes
Product Type
H8/38347 H8/38345 Mask
Regular
Group
ROM
products
versions
Mask
WideROM
range
versions specification
products
H8/38346 Mask
Regular
ROM
products
versions
Widerange
specification
products
H8/38347 Mask
Regular
ROM
products
versions
Widerange
specification
products
F-ZTAT Regular
versions products
Widerange
specification
products
Product Code
Mark Code
Package (Package Code)
HD64338345H
38345H
100-pin QFP (FP-100B)
HD64338345W
38345W
100-pin TQFP (TFP100G)
HD64338345X
38345X
100-pin TQFP (TFP-100B)
HCD64338345
Die
HD64338345HW 38345H
100-pin QFP (FP-100B)
HD64338345WW 38345W
100-pin TQFP (TFP100G)
HD64338345XW 38345X
100-pin TQFP (TFP-100B)
HD64338346H
38346H
100-pin QFP (FP-100B)
HD64338346W
38346W
100-pin TQFP (TFP100G)
HD64338346X
38346X
100-pin TQFP (TFP-100B)
HCD64338346
Die
HD64338346HW 38346H
100-pin QFP (FP-100B)
HD64338346WW 38346W
100-pin TQFP (TFP100G)
HD64338346XW 38346X
100-pin TQFP (TFP-100B)
HD64338347H
38347H
100-pin QFP (FP-100B)
HD64338347W
38347W
100-pin TQFP (TFP100G)
HD64338347X
38347X
100-pin TQFP (TFP-100B)
HCD64338347
Die
HD64338347HW 38347H
100-pin QFP (FP-100B)
HD64338347WW 38347W
100-pin TQFP (TFP100G)
HD64338347XW 38347X
100-pin TQFP (TFP-100B)
HD64F38347H
F38347H
100-pin QFP (FP-100B)
HD64F38347W
F38347W
100-pin TQFP (TFP100G)
HD64F38347X
F38347X
100-pin TQFP (TFP-100B)
HCD64F38347
Die
HD64F38347HW F38347H
100-pin QFP (FP-100B)
HD64F38347W
W
100-pin TQFP (TFP100G)
F38347W
HD64F38347XW F38347X
100-pin TQFP (TFP-100B)
Rev. 6.00 Aug 04, 2006 page 665 of 680
REJ09B0145-0600
Appendix E List of Product Codes
Product Type
H8/38447 H8/38442 Mask
Regular
Group
ROM
products
versions
Widerange
specification
products
H8/38443 Mask
Regular
ROM
products
versions
Widerange
specification
products
H8/38444 Mask
Regular
ROM
products
versions
Widerange
specification
products
F-ZTAT Regular
versions products
Widerange
specification
products
Product Code
Mark Code
Package (Package Code)
HD64338442H
38442H
100-pin QFP (FP-100B)
HD64338442W
38442W
100-pin TQFP (TFP100G)
HD64338442X
38442X
100-pin TQFP (TFP-100B)
HCD64338442
Die
HD64338442HW 38442H
100-pin QFP (FP-100B)
HD64338442WW 38442W
100-pin TQFP (TFP100G)
HD64338442XW 38442X
100-pin TQFP (TFP-100B)
HD64338443H
38443H
100-pin QFP (FP-100B)
HD64338443W
38443W
100-pin TQFP (TFP100G)
HD64338443X
38443X
100-pin TQFP (TFP-100B)
HCD64338443
Die
HD64338443HW 38443H
100-pin QFP (FP-100B)
HD64338443WW 38443W
100-pin TQFP (TFP100G)
HD64338443XW 38443X
100-pin TQFP (TFP-100B)
HD64338444H
38444H
100-pin QFP (FP-100B)
HD64338444W
38444W
100-pin TQFP (TFP100G)
HD64338444X
38444X
100-pin TQFP (TFP-100B)
HCD64338444
Die
HD64338444HW 38444H
100-pin QFP (FP-100B)
HD64338444WW 38444W
100-pin TQFP (TFP100G)
HD64338444XW 38444X
100-pin TQFP (TFP-100B)
HD64F38444H
F38444H
100-pin QFP (FP-100B)
HD64F38444W
F38444W
100-pin TQFP (TFP100G)
HD64F38444X
F38444X
100-pin TQFP (TFP-100B)
HD64F38444HW F38444H
100-pin QFP (FP-100B)
HD64F38444W
W
100-pin TQFP (TFP100G)
F38444W
HD64F38444XW F38444X
Rev. 6.00 Aug 04, 2006 page 666 of 680
REJ09B0145-0400
100-pin TQFP (TFP-100B)
Appendix E List of Product Codes
Product Type
H8/38447 H8/38445 Mask
Regular
Group
ROM
products
versions
Mask
WideROM
range
versions specification
products
H8/38446 Mask
Regular
ROM
products
versions
Widerange
specification
products
H8/38447 Mask
Regular
ROM
products
versions
Widerange
specification
products
F-ZTAT Regular
versions products
Widerange
specification
products
Product Code
Mark Code
Package (Package Code)
HD64338445H
38445H
100-pin QFP (FP-100B)
HD64338445W
38445W
100-pin TQFP (TFP100G)
HD64338445X
38445X
100-pin TQFP (TFP-100B)
HCD64338445
Die
HD64338445HW 38445H
100-pin QFP (FP-100B)
HD64338445WW 38445W
100-pin TQFP (TFP100G)
HD64338445XW 38445X
100-pin TQFP (TFP-100B)
HD64338446H
38446H
100-pin QFP (FP-100B)
HD64338446W
38446W
100-pin TQFP (TFP100G)
HD64338446X
38446X
100-pin TQFP (TFP-100B)
HCD64338446
Die
HD64338446HW 38446H
100-pin QFP (FP-100B)
HD64338446WW 38446W
100-pin TQFP (TFP100G)
HD64338446XW 38446X
100-pin TQFP (TFP-100B)
HD64338447H
38447H
100-pin QFP (FP-100B)
HD64338447W
38447W
100-pin TQFP (TFP100G)
HD64338447X
38447X
100-pin TQFP (TFP-100B)
HCD64338447
Die
HD64338447HW 38447H
100-pin QFP (FP-100B)
HD64338447WW 38447W
100-pin TQFP (TFP100G)
HD64338447XW 38447X
100-pin TQFP (TFP-100B)
HD64F38447H
F38447H
100-pin QFP (FP-100B)
HD64F38447W
F38447W
100-pin TQFP (TFP100G)
HD64F38447X
F38447X
100-pin TQFP (TFP-100B)
HCD64F38447
Die
HD64F38447HW F38447H
100-pin QFP (FP-100B)
HD64F38447W
W
100-pin TQFP (TFP100G)
F38447W
HD64F38447XW F38447X
100-pin TQFP (TFP-100B)
Note: For mask ROM versions, (***) is the ROM code.
Rev. 6.00 Aug 04, 2006 page 667 of 680
REJ09B0145-0600
Appendix F Package Dimensions
Appendix F Package Dimensions
Dimensional drawings of H8/3847R Group, H8/3847S Group, H8/38347 Group, and H8/38447
Group packages FP-100A (only H8/3847R Group), FP-100B, TFP-100B and TFP-100G are
shown in following figures F.1, F.2, F.3, and F.4, respectively.
JEITA Package Code
P-QFP100-14x20-0.65
RENESAS Code
PRQP0100JE-B
Previous Code
FP-100A/FP-100AV
MASS[Typ.]
1.7g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
80
51
81
50
bp
Reference
Symbol
c
c1
HE
ZE
Terminal cross section
31
100
Dimension in Millimeters
Min
D
*2
E
b1
Nom
E
14
A2
2.70
HD
24.4
24.8
25.2
HE
18.4
18.8
19.2
A1
0.00
0.20
0.30
bp
0.24
0.32
0.40
A
1
30
θ
A1
L
L1
Detail F
*3
y
bp
M
x
θ
0.17
0.22
0.15
0˚
10˚
0.65
x
0.13
y
0.15
ZD
0.58
ZE
0.83
L
Rev. 6.00 Aug 04, 2006 page 668 of 680
REJ09B0145-0400
0.12
e
L1
Figure F.1 FP-100A Package Dimensions
0.30
c1
c
A2
A
c
F
e
3.10
b1
ZD
Max
20
1.0
1.2
2.4
1.4
Appendix F Package Dimensions
JEITA Package Code
P-QFP100-14x14-0.50
RENESAS Code
PRQP0100KA-A
Previous Code
FP-100B/FP-100BV
MASS[Typ.]
1.2g
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
HD
*1
D
75
51
76
50
bp
Reference
Symbol
c
c1
HE
Dimension in Millimeters
Min
Nom
Max
14
D
E
14
A2
2.70
*2
E
b1
ZE
Terminal cross section
1
2
5
16.0
16.3
15.7
16.0
16.3
A1
0.00
0.12
0.25
bp
0.17
0.22
0.27
A1
θ
*3
bp
x
θ
L
e
L1
x
Detail F
M
0.20
0.12
c1
c
A2
A
c
F
y
3.05
b1
ZD
e
15.7
HE
A
26
100
HD
0.17
0˚
8˚
0.5
0.08
y
0.10
ZD
1.0
ZE
L
L1
0.22
0.15
1.0
0.3
0.5
0.7
1.0
Figure F.2 FP-100B Package Dimensions
Rev. 6.00 Aug 04, 2006 page 669 of 680
REJ09B0145-0600
Appendix F Package Dimensions
JEITA Package Code
P-TQFP100-14x14-0.50
RENESAS Code
PTQP0100KA-A
Previous Code
TFP-100B/TFP-100BV
MASS[Typ.]
0.5g
HD
*1
D
75
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
51
76
50
bp
Reference
Symbol
c
c1
HE
Dimension in Millimeters
Min
D
Nom
Max
14
E
14
A2
1.00
*2
E
b1
Terminal cross section
HD
15.8
16.0
16.2
HE
15.8
16.0
16.2
A1
0.00
0.10
0.20
bp
0.17
0.22
0.27
ZE
A
26
100
1.20
b1
ZD
0.12
c1
Index mark
θ
F
A1
L
L1
Detail F
*3
y
bp
x
M
θ
0˚
e
Figure F.3 TFP-100B Package Dimensions
8˚
0.5
x
0.08
y
0.10
ZD
L
L1
Rev. 6.00 Aug 04, 2006 page 670 of 680
REJ09B0145-0400
0.22
0.15
1.00
ZE
e
0.17
c
A2
25
A
1
c
0.20
1.00
0.4
0.5
1.0
0.6
Appendix F Package Dimensions
JEITA Package Code
P-TQFP100-12x12-0.40
RENESAS Code
PTQP0100LC-A
Previous Code
TFP-100G/TFP-100GV
MASS[Typ.]
0.4g
HD
*1
D
75
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
51
76
50
Reference
Symbol
HE
b1
26
Terminal cross section
ZE
100
Dimension in Millimeters
Min
Nom
E
12
A2
1.00
HD
13.8
14.0
14.2
HE
13.8
14.0
14.2
A1
0.00
0.10
0.20
bp
0.13
0.18
0.23
1.20
A
1
ZD
2
5
Index mark
F
c
A2
A
y
A1
bp
L
L1
M x
Detail F
0.12
θ
0.17
0˚
8˚
0.4
e
0.07
x
y
0.10
1.2
ZD
1.2
ZE
L
L1
0.22
0.15
c1
θ
e
0.16
b1
c
*3
Max
12
D
c
c1
*2
E
bp
0.4
0.5
0.6
1.0
Figure F.4 TFP-100G Package Dimension
Rev. 6.00 Aug 04, 2006 page 671 of 680
REJ09B0145-0600
Appendix G Specifications of Chip Form
Appendix G Specifications of Chip Form
The specifications of the chip form of the HCD6433847R, HCD6433846R, HCD6433845R,
HCD6433844R, HCD6433843R, and HCD6433842R are shown in figure G.1.
X-direction 6.10 ± 0.05
Y-direction 6.23 ± 0.05
0.28 ± 0.22
Maximum plain
X-direction 6.10 ± 0.25
Y-direction 6.23 ± 0.25
Max 0.03
(Unit: mm)
Figure G.1 Chip Sectional Figure
The specifications of the chip form of the HCD6433847S, HCD6433846S, HCD6433845S, and
HCD6433844S are shown in figure G.2.
X-direction 3.55 ± 0.05
Y-direction 3.45 ± 0.05
0.28 ± 0.22
Maximum plain
X-direction 3.55 ± 0.25
Y-direction 3.45 ± 0.25
Max 0.03
(Unit: mm)
Figure G.2 Chip Sectional Figure
Rev. 6.00 Aug 04, 2006 page 672 of 680
REJ09B0145-0400
Appendix G Specifications of Chip Form
The specifications of the chip form of the HCD64F38347 and HCD64F38447 are shown in figure
G.3.
X-direction 4.35 ± 0.05
Y-direction 4.83 ± 0.05
Pattern side
0.28 ± 0.22
Chip back
Maximum plain
X-direction 4.35 ± 0.25
Y-direction 4.83 ± 0.25
Max 0.03
(Unit: mm)
Figure G.3 Chip Sectional Figure
The specifications of the chip form of the H8/38347 Group (Mask ROM version) and H8/38447
Group (Mask ROM Version) are shown in figure G.4.
X-direction 3.55 ± 0.05
Y-direction 3.77 ± 0.05
Pattern side
0.28 ± 0.22
Chip back
Maximum plain
X-direction 3.55 ± 0.25
Y-direction 3.77 ± 0.25
Max 0.03
(Unit: mm)
Figure G.4 Chip Sectional Figure
Rev. 6.00 Aug 04, 2006 page 673 of 680
REJ09B0145-0600
Appendix H Form of Bonding Pads
Appendix H Form of Bonding Pads
The form of the bonding pads for the HCD6433847R, HCD6433846R, HCD6433845R,
HCD6433844R, HCD6433843R, and HCD6433842R is shown in figure H.1.
5 to 8 µm
90 µm
Bonding area
Metal Layer
90 µm
5 to 8 µm
Figure H.1 Bonding Pad Form
Rev. 6.00 Aug 04, 2006 page 674 of 680
REJ09B0145-0400
Appendix H Form of Bonding Pads
The form of the bonding pads for the HCD6433847S, HCD6433846S, HCD6433845S, and
HCD6433844S is shown in figure H.2.
2.5 µm
75 µm
Bonding area
Metal Layer
75 µm
2.5 µm
Figure H.2 Bonding Pad Form
Rev. 6.00 Aug 04, 2006 page 675 of 680
REJ09B0145-0600
Appendix H Form of Bonding Pads
The form of the bonding pads for the HCD64F38347, HCD64F38447, H8/38347 Group (Mask
ROM version), and H8/38447 Group (Mask ROM version) is shown in figure H.3.
Metal Layer
5 µm
65 µm
Bonding area
65 µm
Figure H.3 Bonding Pad Form
Rev. 6.00 Aug 04, 2006 page 676 of 680
REJ09B0145-0400
5 µm
Appendix I Specifications of Chip Tray
Appendix I Specifications of Chip Tray
The specifications of the chip tray for the HCD6433847R, HCD6433846R, HCD6433845R,
HCD6433844R, HCD6433843R, and HCD6433842R are shown in figure I.1.
51
Chip orientation
Chip
6.23
Type code
51
6.10
Chip-tray code name
Manufactured by DAINIPPON INK
AND CHEMICALS, INCORPORATED
Code name: CT054
Characteristic engraving: TCT066066-041
8.7 ± 0.1
6.6 ± 0.05
X
X'
8.1 ± 0.15
6.6 ± 0.05
0.4 ± 0.1
1.8 ± 0.1
4.0 ± 0.1
8.7 ± 0.1
8.1 ± 0.1
Cross-sectional view: X to X'
(Unit: mm)
Figure I.1 Specifications of Chip Tray
Rev. 6.00 Aug 04, 2006 page 677 of 680
REJ09B0145-0600
Appendix I Specifications of Chip Tray
The specifications of the chip tray for the HCD6433847S, HCD6433846S, HCD6433845S, and
HCD6433844S are shown in figure I.2.
51
Chip orientation
Type
code
Chip
Base
type code
3.45
51
3.55
Chip-tray code name
Manufactured by DAINIPPON INK
AND CHEMICALS, INCORPORATED
Code name: CT065
Characteristic engraving: TCT4040-060
4.9 ± 0.1
4.0 ± 0.05
X
X'
5.9 ± 0.1
4.0 ± 0.05
0.6 ± 0.1
1.8 ± 0.1
4.0 ± 0.1
4.9 ± 0.1
5.9 ± 0.1
Cross-sectional view: X to X'
(Unit: mm)
Figure I.2 Specifications of Chip Tray
Rev. 6.00 Aug 04, 2006 page 678 of 680
REJ09B0145-0400
Appendix I Specifications of Chip Tray
The specifications of the chip tray for the HCD64F38347 and HCD64F38447 are shown in figure
I.3.
51
Chip orientation
Type
code
4.83
Chip
51
4.35
Chip-tray code name
Code name: CT037
Characteristic engraving: 2CT049049-070
5.4 ± 0.1
4.9 ± 0.05
X'
X
6.6 ± 0.1
4.9 ± 0.05
0.7 ± 0.1
1.8 ± 0.1
4.0 ± 0.1
5.4 ± 0.1
6.6 ± 0.1
Cross-sectional view: X to X'
(Unit: mm)
Figure I.3 Specifications of Chip Tray
Rev. 6.00 Aug 04, 2006 page 679 of 680
REJ09B0145-0600
Appendix I Specifications of Chip Tray
The specifications of the chip tray for the H8/38347 Group (Mask ROM version) and H8/38447
Group (Mask ROM version) are shown in figure I.4.
51
Chip orientation
Type
code
Chip
3.77
51
3.55
Chip-tray code name
Code name: CT127
Characteristic engraving: 2CT040040-063
5.5 ± 0.1
4.0 ± 0.05
X'
X
6.25 ± 0.1
4.0 ± 0.05
0.63 ± 0.05
1.8 ± 0.1
4.0 ± 0.1
5.5 ± 0.1
6.25 ± 0.1
Cross-sectional view: X to X'
Figure I.4 Specifications of Chip Tray
Rev. 6.00 Aug 04, 2006 page 680 of 680
REJ09B0145-0400
(Unit: mm)
Renesas 8-Bit Single-Chip Microcomputer
Hardware Manual
H8/3847R Group, H8/3847S Group, H8/38347 Group,
H8/38447 Group
Publication Date: 1st Edition, September, 1999
Rev.6.00, August 04, 2006
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
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Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
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Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
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Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
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Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
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1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
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Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
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Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/3847R Group, H8/3847S Group,
H8/38347 Group, H8/38447 Group
Hardware Manual