GSI GS74116AGX-10 256k x 16 4mb asynchronous sram Datasheet

GS74116AGP/X
TSOP, FP-BGA
Commercial Temp
Industrial Temp
8, 10, 12 ns
3.3 V VDD
Center VDD and VSS
256K x 16
4Mb Asynchronous SRAM
Features
FP-BGA 256K x 16 Bump Configuration (Package X)
• Fast access time: 8, 10, 12 ns
• CMOS low power operation: 130/105/95 mA at minimum
cycle time
• Single 3.3 V power supply
• All inputs and outputs are TTL-compatible
• Byte control
• Fully static operation
• Industrial Temperature Option: –40° to 85°C
• Package line up
GP: RoHS-compliant 400 mil, 44-pin TSOP Type II
package
X: 6 mm x 10 mm Fine Pitch Ball Grid Array package
GX: RoHS-compliant 6 mm x 10 mm Fine Pitch Ball Grid
Array package
• RoHS-compliant TSOP-II, and FP-BGA packages available
1
2
3
4
5
6
A
LB
OE
A0
A1
A2
NC
B
DQ16
UB
A3
A4
CE
DQ1
C
DQ14 DQ15
A5
A6
DQ2
DQ3
D
VSS
DQ13
A17
A7
DQ4
VDD
E
VDD
DQ12
NC
A16
DQ5
VSS
F
DQ11 DQ10
A8
A9
DQ7
DQ6
G
DQ9
NC
A10
A11
WE
DQ8
H
NC
A12
A13
A14
A15
NC
Description
The GS74116A is a high speed CMOS Static RAM organized
as 262,144 words by 16 bits. Static design eliminates the need
for external clocks or timing strobes. The GS operates on a
single 3.3 V power supply and all inputs and outputs are TTLcompatible. The GS74116A is available in a 6 x 10 mm Fine
Pitch BGA package and 400 mil TSOP Type-II packages.
Description
A0–A17
Address input
DQ1–DQ16
Data input/output
CE
Chip enable input
LB
Lower byte enable input
(DQ1 to DQ8)
UB
Upper byte enable input
(DQ9 to DQ16)
WE
Write enable input
OE
Output enable input
VDD
+3.3 V power supply
VSS
Ground
NC
No connect
Rev: 1.10 1/2013
TSOP-II 256K x 16 Pin Configuration (Package GP)
A4
A3
A2
A1
A0
CE
DQ1
DQ2
DQ3
DQ4
VDD
Pin Descriptions
Symbol
6 x 10 mm Substrate
Top View
VSS
DQ5
DQ6
DQ7
DQ8
WE
A15
A14
A13
A12
A16
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Top view
44 pin
TSOP II
16
17
18
19
20
21
22
1/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
OE
UB
LB
DQ16
DQ15
DQ14
DQ13
VSS
VDD
DQ12
DQ11
DQ10
DQ9
NC
A8
A9
A10
A11
A17
© 2001, GSI Technology
GS74116AGP/X
Block Diagram
A0
Address
Input
Buffer
Row
Decoder
Memory Array
Column
Decoder
A17
CE
WE
Control
OE
_____
UB
I/O Buffer
DQ1
DQ16
Truth Table
CE
OE
WE
LB
UB
DQ1 to DQ8
DQ9 to DQ16
VDD Current
H
X
X
X
X
Not Selected
Not Selected
ISB1, ISB2
L
L
Read
Read
L
H
Read
High Z
H
L
High Z
Read
L
L
Write
Write
L
H
Write
Not Write, High Z
H
L
Not Write, High Z
Write
L
L
L
X
H
L
L
H
H
X
X
High Z
High Z
L
X
X
H
H
High Z
High Z
IDD
Note:
X: “H” or “L”
Rev: 1.10 1/2013
2/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
Absolute Maximum Ratings
Parameter
Symbol
Rating
Unit
Supply Voltage
VDD
–0.5 to +4.6
V
Input Voltage
VIN
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Output Voltage
VOUT
–0.5 to VDD +0.5
(≤ 4.6 V max.)
V
Allowable power dissipation
PD
0.7
W
Storage temperature
TSTG
–55 to 150
oC
Note:
Permanent device damage may occur if Absolute Maximum Ratings are exceeded. Functional operation shall be restricted to Recommended
Operating Conditions. Exposure to higher than recommended voltages for extended periods of time could affect device reliability.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Supply Voltage for -8/-10/-12
VDD
3.0
3.3
3.6
V
Input High Voltage
VIH
2.0
—
VDD +0.3
V
Input Low Voltage
VIL
–0.3
—
0.8
V
Ambient Temperature,
Commercial Range
TAc
0
—
70
o
C
Ambient Temperature,
Industrial Range
TAI
–40
—
85
o
C
Notes:
1. Input overshoot voltage should be less than VDD +2 V and not exceed 20 ns.
2. Input undershoot voltage should be greater than –2 V and not exceed 20 ns.
Capacitance
Parameter
Symbol
Test Condition
Max
Unit
Input Capacitance
CIN
VIN = 0 V
5
pF
Output Capacitance
COUT
VOUT = 0 V
7
pF
Notes:
1. Tested at TA = 25°C, f = 1 MHz
2. These parameters are sampled and are not 100% tested.
Rev: 1.10 1/2013
3/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
DC I/O Pin Characteristics
Parameter
Symbol
Test Conditions
Min
Max
Input Leakage Current
IIL
VIN = 0 to VDD
– 1 uA
1 uA
Output Leakage Current
ILO
Output High Z
VOUT = 0 to VDD
–1 uA
1 uA
Output High Voltage
VOH
IOH = –4 mA
2.4
—
Output Low Voltage
VOL
ILO = +4 mA
—
0.4 V
Power Supply Currents
Parameter
Symbol
Test Conditions
0 to 70°C
–40 to 85°C
Unit
8 ns
10 ns
12 ns
8 ns
10 ns
12 ns
IDD
CE ≤ VIL
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
IOUT = 0 mA
130
105
90
140
115
100
mA
Standby
Current
ISB1
CE ≥ VIH
All other inputs
≥ VIH or ≤ VIL
Min. cycle time
30
25
25
40
35
35
mA
Standby
Current
ISB2
CE ≥ VDD – 0.2V
All other inputs
≥ VDD – 0.2 V or ≤ 0.2 V
Operating
Supply
Current
Rev: 1.10 1/2013
10
4/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
20
mA
© 2001, GSI Technology
GS74116AGP/X
AC Test Conditions
Output Load 1
Parameter
Conditions
Input high level
VIH = 2.4 V
Input low level
VIL = 0.4 V
50Ω
Input rise time
tr = 1 V/ns
VT = 1.4 V
Input fall time
tf = 1 V/ns
Input reference level
1.4 V
Output Load 2
Output reference level
1.4 V
3.3 V
Output load
Fig. 1& 2
DQ
Rev: 1.10 1/2013
589Ω
DQ
Notes:
1. Include scope and jig capacitance.
2. Test conditions as specified with output loading as shown in Fig. 1
unless otherwise noted.
3. Output load 2 for tLZ, tHZ, tOLZ and tOHZ
5/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
30pF1
5pF1
434Ω
© 2001, GSI Technology
GS74116AGP/X
AC Characteristics
Read Cycle
Parameter
Symbol
Read cycle time
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
tRC
8
—
10
—
12
—
ns
Address access time
tAA
—
8
—
10
—
12
ns
Chip enable access time (CE)
tAC
—
8
—
10
—
12
ns
Byte enable access time (UB, LB)
tAB
—
3.5
—
4
—
5
ns
Output enable to output valid (OE)
tOE
—
3.5
—
4
—
5
ns
Output hold from address change
tOH
3
—
3
—
3
—
ns
Chip enable to output in low Z (CE)
tLZ*
3
—
3
—
3
—
ns
Output enable to output in low Z (OE)
tOLZ*
0
—
0
—
0
—
ns
Byte enable to output in low Z (UB, LB)
tBLZ*
0
—
0
—
0
—
ns
Chip disable to output in High Z (CE)
tHZ*
—
4
—
5
—
6
ns
Output disable to output in High Z (OE)
tOHZ*
—
3.5
—
4
—
5
ns
Byte disable to output in High Z (UB, LB)
tBHZ*
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Read Cycle 1: CE = OE = VIL, WE = VIH, UB and, or LB = VIL
tRC
Address
tAA
tOH
Data Out
Rev: 1.10 1/2013
Previous Data
Data valid
6/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
Read Cycle 2: WE = VIH
tRC
Address
tAA
CE
tAC
tHZ
tLZ
tAB
UB, LB
tBHZ
tBLZ
OE
tOE
Data Out
tOHZ
Data valid
tOLZ
High impedance
Write Cycle
Parameter
Symbol
Write cycle time
-8
-10
-12
Unit
Min
Max
Min
Max
Min
Max
tWC
8
—
10
—
12
—
ns
Address valid to end of write
tAW
5.5
—
7
—
8
—
ns
Chip enable to end of write
tCW
5.5
—
7
—
8
—
ns
Byte enable to end of write
tBW
5.5
—
7
—
8
—
ns
Data set up time
tDW
4
—
4.5
—
6
—
ns
Data hold time
tDH
0
—
0
—
0
—
ns
Write pulse width
tWP
5.5
—
7
—
8
—
ns
Address set up time
tAS
0
—
0
—
0
—
ns
Write recovery time (WE)
tWR
0
—
0
—
0
—
ns
Write recovery time (CE)
tWR1
0
—
0
—
0
—
ns
Output Low Z from end of write
tWLZ*
3
—
3
—
3
—
ns
Write to output in High Z
tWHZ*
—
3.5
—
4
—
5
ns
* These parameters are sampled and are not 100% tested.
Rev: 1.10 1/2013
7/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
Write Cycle 1: WE control
tWC
Address
tAW
tWR
OE
tCW
CE
tBW
UB, LB
tAS
tWP
WE
tDW
tDH
Data valid
Data In
tWHZ
tWLZ
Data Out
High impedance
Write Cycle 2: CE control
tWC
Address
tAW
tWR1
OE
tAS
tCW
CE
tBW
UB, LB
tWP
WE
tDW
Data valid
Data In
Data Out
Rev: 1.10 1/2013
tDH
High impedance
8/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
Write Cycle 3: UB, LB control
tWC
Address
tAW
tWR1
OE
tAS
tCW
CE
tBW
UB, LB
tWP
WE
tDW
Data valid
Data In
Data Out
Rev: 1.10 1/2013
tDH
High impedance
9/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
44-Pin, 400 mil TSOP-II
D
c
22
e
B
y
L
L1
A1
A
A2
1
A
HE
23
E
44
Dimension in inch Dimension in mm
Symbol min nom max min nom max
Detail A
Rev: 1.10 1/2013
Q
A
—
—
0.047
—
—
1.20
A1
0.002
—
—
0.05
—
—
A2
0.037
0.039
0.041
0.95
1.00
1.05
B
0.01
0.014
0.018
0.25
0.35
0.45
c
—
0.006
—
—
0.15
—
D
0.721
0.725
0.729
18.31
18.41
18.51
E
0.396
0.400
0.404
10.06
10.16
10.26
e
—
0.031
—
—
0.80
—
HE
0.455
0.463
0.471
11.56
11.76
11.96
L
0.016
0.020
0.024
0.40
0.50
0.60
L1
—
0.031
—
—
0.80
—
y
—
—
0.004
—
—
0.10
Q
0o
—
5o
0o
—
5o
Notes:
1. Dimension D& E do not include interlead flash.
2. Dimension B does not include dambar protrusion/intrusion.
3. Controlling dimension: mm
10/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
6 mm x 10 mm FP-BGA
Symbol
D
E
Pin A1
Index
Top View
A
Unit: mm
A
1.10±0.10
A1
0.20~0.30
fb
f0.30~0.40
c
0.36(TYP)
D
10.0±0.05
D1
5.25
E
6.0±0.05
E1
3.75
e
0.75(TYP)
aaa
0.10
c
A1
Pin A1
Index
Side View
aaa
A B C D E F G H
1
2
3
4
5
6
fb Solder Ball
e
E1
e
D1
Bottom View
Rev: 1.10 1/2013
11/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
Ordering Information
Part Number*
Package
Access Time
Temp. Range
GS74116AGP-8
RoHS-compliant 400 mil TSOP-II
8 ns
Commercial
GS74116AGP-10
RoHS-compliant 400 mil TSOP-II
10 ns
Commercial
GS74116AGP-12
RoHS-compliant 400 mil TSOP-II
12 ns
Commercial
GS74116AGP-8I
RoHS-compliant 400 mil TSOP-II
8 ns
Industrial
GS74116AGP-10I
RoHS-compliant 400 mil TSOP-II
10 ns
Industrial
GS74116AGP-12I
RoHS-compliant 400 mil TSOP-II
12 ns
Industrial
GS74116AX-8
Fine Pitch BGA
8 ns
Commercial
GS74116AX-10
Fine Pitch BGA
10 ns
Commercial
GS74116AX-12
Fine Pitch BGA
12 ns
Commercial
GS74116AX-8I
Fine Pitch BGA
8 ns
Industrial
GS74116AX-10I
Fine Pitch BGA
10 ns
Industrial
GS74116AX-12I
Fine Pitch BGA
12 ns
Industrial
GS74116AGX-8
RoHS-compliant Fine Pitch BGA
8 ns
Commercial
GS74116AGX-10
RoHS-compliant Fine Pitch BGA
10 ns
Commercial
GS74116AGX-12
RoHS-compliant Fine Pitch BGA
12 ns
Commercial
GS74116AGX-8I
RoHS-compliant Fine Pitch BGA
8 ns
Industrial
GS74116AGX-10I
RoHS-compliant Fine Pitch BGA
10 ns
Industrial
GS74116AGX-12I
RoHS-compliant Fine Pitch BGA
12 ns
Industrial
Note:
Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. For example: GS74116AGP-8T
Rev: 1.10 1/2013
12/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
GS74116AGP/X
4Mb Asynchronous Datasheet Revision History
Rev. Code: Old;
New
74116A_r1
Types of Changes
Format or Content
Format/Content
Page #/Revisions/Reason
• Created new datasheet
74116A_r1; 74116A_r1_01
Content
• Added 6 ns and 7 ns speed bins
• Updated power numbers
• Changed FPBGA package size from 7.2 x 11.65 mm to 6 x 10 mm
• Changed package designator from “U” to “X” for FPBGA
• Changed D3 on FPBGA pinout to A17 and E3 to NC
74116A_r1_01; 74116A_r1_02
Content
• Updated Recommended Operating Conditions on page 4
• Updated Read Cycle and Write Cycle AC Characteristics tables
74116A_r1_02; 74116A_r1_03
Content
• Removed 6 ns speed bin from entire document
74116A_r1_03; 74116A_r1_04
Content
• Removed 7 ns speed bin from entire document
74116A_r1_04; 74116A_r1_05
Content/Format
• Updated format
• Added Pb-free information for TSOP
74116A_r1_05; 74116A_r1_06
Content/Format
• Added Pb-free information for FP-BGA
74116A_r1_06; 74116A_r1_07
Content
• Changed Pb-free references to RoHS-compliant
• Added RoHS-compliant SOJ part
• Added status to Ordering Information table
74116A_r1_07; 74116A_r1_08
Content
• Removed status from Ordering Information table (all parts MP)
74116A_r1_08; 74116A_r1_09
Content
• Removed SOJ references (part is EOL)
• (Rev1.09a: Changed 6 x 10 mm Ball Pitch reference on page 1 to 6 x 10
mm Substrate)
74116A_r1_09; 74116A_r1_10
Content
• Removed TSOP-II 5/6 RoHS-compliant references (part is EOL)
Rev: 1.10 1/2013
13/13
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
© 2001, GSI Technology
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GS74116AX-12I GS74116AGP-12 GS74116AGP-8 GS74116AGP-8I GS74116AGX-10 GS74116AX-12
GS74116AX-10 GS74116AGX-12I GS74116AGP-12I GS74116AX-8I GS74116AX-10I GS74116AGX-10I
GS74116AGP-10I GS74116AGX-12 GS74116AGX-8 GS74116AGP-10 GS74116AX-8 GS74116AGX-8I
GS74116AGX-12E GS74116AX-8E GS74116AGP-8E GS74116AX-12E GS74116AGX-10E GS74116AGP-10E
GS74116AGX-8E GS74116AGP-12E GS74116AX-10E
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