Lyontek LY62L5128GL-70LL 512k x 8 bit low power cmos sram Datasheet

®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
REVISION HISTORY
Revision
Rev. 1.0
Rev. 1.1
Rev. 1.2
Rev. 1.3
Rev. 1.4
Rev. 1.5
Rev. 1.6
Rev. 1.7
Rev. 1.8
Rev. 1.9
Rev. 1.10
Rev. 1.11
Rev. 1.12
Description
Initial Issue
Adding PKG type : 32 P-DIP
Revised Test Condition of ISB1/IDR
Deleted L Spec.
Added SL Spec.
Revised VTERM to VT1 and VT2
Revised Test Condition of ICC
Revised ISB/IDR
Adding PKG type : 44 TSOP-II
Added ISB1/IDR values when TA = 25℃ and TA = 40℃
Revised FEATURES & ORDERING INFORMATION
Lead free and green package available to Green package
available
Added packing type in ORDERING INFORMATION
Deleted TSOLDER in ABSOLUTE MAXIMUN RATINGS
Added PKG type : 32 TSOP-II
Deleted PKG type : 32 TSOP-II
Revised PACKAGE OUTLINE DIMENSION in page
10/11/12/13
Revised ORDERING INFORMATION in page 15
Revised PACKAGE OUTLINE DIMENSION in page 9
Added PKG type : 32 TSOP-II
Revised ORDERING INFORMATION in page 16
Deleted PKG type : 44 TSOP-II
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
0
Issue Date
Jul.25.2004
May.14.2007
Nov.8.2007
Mar.21.2008
Jul.14.2008
Mar.30.2009
Jun.22.2009
Jul.17.2009
May.7.2010
Aug.30.2010
Nov.1.2010
Mar.9.2011
Feb.21.2012
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
FEATURES
GENERAL DESCRIPTION
„ Fast access time : 45/55/70ns
„ Low power consumption:
Operating current : 40/30/20mA (TYP.)
Standby current : 2μA (TYP.) LL-version
1μA (TYP.) SL-version
„ Single 2.7V ~ 3.6V power supply
„ All inputs and outputs TTL compatible
„ Fully static operation
„ Tri-state output
„ Data retention voltage : 1.5V (MIN.)
„ Green package available
„ Package : 32-pin 450 mil SOP
32-pin 8mm x 20mm TSOP-I
32-pin 8mm x 13.4mm STSOP
36-ball 6mm x 8mm TFBGA
32-pin 600 mil P-DIP
32-pin 400 mil TSOP-II
The LY62L5128 is a 4,194,304-bit low power CMOS
static random access memory organized as 524,288
words by 8 bits. It is fabricated using very high
performance, high reliability CMOS technology. Its
standby current is stable within the range of
operating temperature.
The LY62L5128 is well designed for very low power
system applications, and particularly well suited for
battery back-up nonvolatile memory application.
The LY62L5128 operates from a single power
supply of 2.7V ~ 3.6V and all inputs and outputs are
fully TTL compatible
PRODUCT FAMILY
Product
Family
LY62L5128
LY62L5128(E)
LY62L5128(I)
Operating
Temperature
0 ~ 70℃
-20 ~ 80℃
-40 ~ 85℃
Vcc Range
Speed
2.7 ~ 3.6V
2.7 ~ 3.6V
2.7 ~ 3.6V
45/55/70ns
45/55/70ns
45/55/70ns
FUNCTIONAL BLOCK DIAGRAM
PIN DESCRIPTION
Vcc
Vss
A0-A18
DECODER
DQ0-DQ7
I/O DATA
CIRCUIT
CE#
WE#
OE#
CONTROL
CIRCUIT
Power Dissipation
Standby(ISB1,TYP.) Operating(Icc,TYP.)
2µA(LL)/1µA(SL)
40/30/20mA
2µA(LL)/1µA(SL)
40/30/20mA
2µA(LL)/1µA(SL)
40/30/20mA
512Kx8
MEMORY ARRAY
SYMBOL
DESCRIPTION
A0 - A18
Address Inputs
DQ0 – DQ7
Data Inputs/Outputs
CE#
Chip Enable Inputs
WE#
Write Enable Input
OE#
Output Enable Input
VCC
Power Supply
VSS
Ground
NC
No Connection
COLUMN I/O
PIN CONFIGURATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
1
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
1
32
Vcc
A16
2
31
A15
A14
3
30
A17
A12
4
29
WE#
A7
5
28
A13
A6
6
27
A8
A5
7
A4
8
A3
9
A2
10
A1
11
LY62L5128
A18
26
A9
25
A11
24
OE#
23
A10
22
CE#
A0
12
21
DQ7
DQ0
13
20
DQ6
DQ1
14
19
DQ5
DQ2
15
18
DQ4
Vss
16
17
DQ3
A11
A9
A8
A13
WE#
A17
A15
Vcc
A18
A16
A14
A12
A7
A6
A5
A4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
LY62L5128
TSOP-I/STSOP
SOP/P-DIP
1
32
VCC
A16
2
31
A15
A14
3
30
A17
A12
4
29
WE#
A7
5
28
A13
A6
6
27
A8
A5
7
26
A9
A4
8
25
A11
A3
9
24
OE#
A2
10
23
A10
A1
11
22
CE#
LY62L5128
A18
A
A0
A1
NC
A3
A6
A8
B
DQ4
A2
WE#
A4
A7
DQ0
C
DQ5
NC
A5
D
Vss
Vcc
E
Vcc
Vss
A0
12
21
DQ7
F
DQ6
A17
DQ2
DQ0
13
20
DQ6
G
DQ7 OE# CE# A16
A15 DQ3
DQ1
14
19
DQ5
A13
A14
DQ2
15
18
DQ4
VSS
16
17
DQ3
5
6
H
A18
A9
A10
1
2
A11
A12
3
4
TFBGA
DQ1
TSOP-II
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
2
OE#
A10
CE#
DQ7
DQ6
DQ5
DQ4
DQ3
Vss
DQ2
DQ1
DQ0
A0
A1
A2
A3
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
ABSOLUTE MAXIMUN RATINGS*
PARAMETER
Voltage on VCC relative to VSS
Voltage on any other pin relative to VSS
SYMBOL
VT1
VT2
Operating Temperature
TA
Storage Temperature
Power Dissipation
DC Output Current
TSTG
PD
IOUT
RATING
-0.5 to 4.6
-0.5 to VCC+0.5
0 to 70(C grade)
-20 to 80(E grade)
-40 to 85(I grade)
-65 to 150
1
50
UNIT
V
V
℃
℃
W
mA
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress
rating only and functional operation of the device or any other conditions above those indicated in the operational sections of this
specification is not implied. Exposure to the absolute maximum rating conditions for extended period may affect device reliability.
TRUTH TABLE
MODE
Standby
Output Disable
Read
Write
Note:
CE#
H
L
L
L
OE#
X
H
L
X
WE#
X
H
H
L
I/O OPERATION
High-Z
High-Z
DOUT
DIN
H = VIH, L = VIL, X = Don't care.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
3
SUPPLY CURRENT
ISB,ISB1
ICC,ICC1
ICC,ICC1
ICC,ICC1
®
LY62L5128
Rev. 1.12
512K X 8 BIT LOW POWER CMOS SRAM
DC ELECTRICAL CHARACTERISTICS
SYMBOL
TEST CONDITION
PARAMETER
Supply Voltage
VCC
*1
Input High Voltage
VIH
*2
Input Low Voltage
VIL
Input Leakage Current
ILI
VCC ≧ VIN ≧ VSS
Output Leakage
VCC ≧ VOUT ≧ VSS,
ILO
Current
Output Disabled
Output High Voltage
VOH IOH = -1mA
Output Low Voltage
VOL
IOL = 2mA
Cycle time = Min.
- 45
CE# = VIL and CE2 = VIH,
ICC
- 55
II/O = 0mA
- 70
Other pins at VIL or VIH
Average Operating
Power supply Current
Cycle time = 1µs
CE#≦0.2V and CE2≧VCC-0.2V,,
ICC1
II/O = 0mA
Other pins at 0.2V or VCC-0.2V
CE# = VIH or CE2 = VIL,
ISB
other pins at VIL or VIH
LL
LLE/LLI
CE# ≧VCC-0.2V
Standby Power
*5
SL
25℃
Supply Current
or CE2≦0.2V
*5
SLE
ISB1
Others at 0.2V or
*5
40℃
SLI
VCC - 0.2V
SL
SLE/SLI
MIN.
2.7
2.2
- 0.2
-1
*4
MAX.
3.6
VCC+0.3
0.6
1
UNIT
V
V
V
µA
-1
-
1
µA
2.2
-
2.7
40
0.4
50
V
V
mA
-
30
40
mA
-
20
30
mA
-
4
5
mA
-
0.3
1.25
mA
-
2
2
15
20
µA
µA
-
1
3
µA
-
1
3
µA
-
1
1
10
12
µA
µA
Notes:
1. VIH(max) = VCC + 3.0V for pulse width less than 10ns.
2. VIL(min) = VSS - 3.0V for pulse width less than 10ns.
3. Over/Undershoot specifications are characterized, not 100% tested.
4. Typical values are included for reference only and are not guaranteed or tested.
Typical values are measured at VCC = VCC(TYP.) and TA = 25℃
5. This parameter is measured at VCC = 3.0V
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
4
TYP.
3.0
-
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
CAPACITANCE (TA = 25℃, f = 1.0MHz)
PARAMETER
Input Capacitance
Input/Output Capacitance
SYMBOL
CIN
CI/O
MIN.
-
MAX
6
8
UNIT
pF
pF
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
0.2V to VCC - 0.2V
3ns
1.5V
CL = 30pF + 1TTL, IOH/IOL = -1mA/2mA
AC ELECTRICAL CHARACTERISTICS
(1) READ CYCLE
PARAMETER
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
Output Enable to Output in Low-Z
Chip Disable to Output in High-Z
Output Disable to Output in High-Z
Output Hold from Address Change
(2) WRITE CYCLE
PARAMETER
Write Cycle Time
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
Write Recovery Time
Data to Write Time Overlap
Data Hold from End of Write Time
Output Active from End of Write
Write to Output in High-Z
SYM.
tRC
tAA
tACE
tOE
tCLZ*
tOLZ*
tCHZ*
tOHZ*
tOH
SYM.
tWC
tAW
tCW
tAS
tWP
tWR
tDW
tDH
tOW*
tWHZ*
LY62L5128-45
MIN.
MAX.
45
45
45
25
10
5
15
15
10
-
LY62L5128-55
MIN.
MAX.
55
55
55
30
10
5
20
20
10
-
LY62L5128-70
MIN.
MAX.
70
70
70
35
10
5
25
25
10
-
UNIT
LY62L5128-45
MIN.
MAX.
45
40
40
0
35
0
20
0
5
15
LY62L5128-55
MIN.
MAX.
55
50
50
0
45
0
25
0
5
20
LY62L5128-70
MIN.
MAX.
70
60
60
0
55
0
30
0
5
25
UNIT
*These parameters are guaranteed by device characterization, but not production tested.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2)
tRC
Address
tAA
Dout
tOH
Previous Data Valid
Data Valid
READ CYCLE 2 (CE# and OE# Controlled) (1,3,4,5)
tRC
Address
tAA
CE#
tACE
OE#
tOE
tOH
tOHZ
tCHZ
tOLZ
tCLZ
Dout
High-Z
Data Valid
Notes :
1.WE# is high for read cycle.
2.Device is continuously selected OE# = low, CE# = low.
3.Address must be valid prior to or coincident with CE# = low,; otherwise tAA is the limiting parameter.
4.tCLZ, tOLZ, tCHZ and tOHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
5.At any given temperature and voltage condition, tCHZ is less than tCLZ , tOHZ is less than tOLZ.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
6
High-Z
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
WRITE CYCLE 1 (WE# Controlled) (1,2,3,5,6)
tWC
Address
tAW
CE#
tCW
tAS
tWP
tWR
WE#
tWHZ
Dout
TOW
High-Z
(4)
tDW
(4)
tDH
Data Valid
Din
WRITE CYCLE 2 (CE# Controlled) (1,2,5,6)
tWC
Address
tAW
CE#
tAS
tWR
tCW
tWP
WE#
tWHZ
Dout
High-Z
(4)
tDW
tDH
Data Valid
Din
Notes :
1.WE#, CE# must be high during all address transitions.
2.A write occurs during the overlap of a low CE#, low WE#.
3.During a WE# controlled write cycle with OE# low, tWP must be greater than tWHZ + tDW to allow the drivers to turn off and data to be
placed on the bus.
4.During this period, I/O pins are in the output state, and input signals must not be applied.
5.If the CE# low transition occurs simultaneously with or after WE# low transition, the outputs remain in a high impedance state.
6.tOW and tWHZ are specified with CL = 5pF. Transition is measured ±500mV from steady state.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
7
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
DATA RETENTION CHARACTERISTICS
PARAMETER
VCC for Data Retention
Data Retention Current
Chip Disable to Data
Retention Time
Recovery Time
tRC* = Read Cycle Time
SYMBOL
TEST CONDITION
MIN.
VDR
CE# ≧ VCC - 0.2V or CE2 ≦ 0.2V
1.5
LL
LLE/LLI
VCC = 1.5V
SL 25℃
CE# ≧ VCC - 0.2V
IDR
SLE
or CE2 ≦ 0.2V
40℃
Other pins at 0.2V or VCC-0.2V SLI
SL
SLE/SLI
See Data Retention
0
tCDR
Waveforms (below)
tR
tRC*
DATA RETENTION WAVEFORM
VDR ≧ 1.5V
Vcc
Vcc(min.)
Vcc(min.)
tCDR
CE#
VIH
tR
CE# ≧ Vcc-0.2V
VIH
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
8
TYP.
1.0
1.0
MAX.
3.6
12
16
UNIT
V
µA
µA
0.5
2.5
µA
0.5
2.5
0.5
0.5
8
10
µA
µA
µA
-
-
ns
-
-
ns
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
PACKAGE OUTLINE DIMENSION
32 pin 450 mil SOP Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
E1
e
L
L1
S
y
Θ
INCH.(BASE)
0.120(MAX)
0.004(MIN)
0.116(MAX)
0.016(TYP)
0.008(TYP)
0.817(MAX)
0.445±0.006
0.555±0.025
0.050(TYP)
0.033±0.017
0.055±0.008
0.026(MAX)
0.004(MAX)
o
o
0 -10
MM(REF)
3.048(MAX)
0.102(MIN)
2.946(MAX)
0.406(TYP)
0.203(TYP)
20.75(MAX)
11.303±0.152
14.097±0.635
1.270(TYP)
0.838±0.432
1.397±0.203
0.660(MAX)
0.101(MAX)
o
o
0 -10
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
9
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
32 pin 8mm x 20mm TSOP-I Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
Θ
INCH(BASE)
0.047 (MAX)
0.004 ±0.002
0.039 ±0.002
0.009 ±0.002
0.006 ±0.002
0.724 ±0.008
0.315 ±0.008
0.020 (TYP)
0.787 ±0.008
0.024 ±0.004
0.0315 ±0.004
0.003 (MAX)
o
o
0 ~5
MM(REF)
1.20 (MAX)
0.10 ±0.05
1.00 ±0.05
0.22 ±0.05
0.155 ±0.055
18.40 ±0.20
8.00 ±0.20
0.50 (TYP)
20.00 ±0.20
0.60 ±0.10
0.08 ±0.10
0.08 (MAX)
o
o
0 ~5
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
10
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
UNIT
SYM.
A
A1
A2
b
c
D
E
e
HD
L
L1
y
Θ
INCH(BASE)
0.049 (MAX)
0.004 ±0.002
0.039 ±0.002
0.009 ±0.002
0.006 ±0.002
0.465 ±0.008
0.315 ±0.008
0.020 (TYP)
0.528±0.008
0.02 ±0.008
0.031 ±0.005
0.003 (MAX)
o
o
0 ~5
MM(REF)
1.25 (MAX)
0.10 ±0.05
1.00 ±0.05
0.22 ±0.05
0.155 ±0.055
11.80 ±0.20
8.00 ±0.20
0.50 (TYP)
13.40 ±0.20.
0.50 ±0.20
0.8 ±0.125
0.076 (MAX)
o
o
0 ~5
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
11
®
LY62L5128
Rev. 1.12
512K X 8 BIT LOW POWER CMOS SRAM
36 ball 6mm × 8mm TFBGA Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
12
®
LY62L5128
512K X 8 BIT LOW POWER CMOS SRAM
Rev. 1.12
32 pin 600 mil P-DIP Package Outline Dimension
UNIT
SYM.
A1
A2
B
D
E
E1
e
eB
L
S
Q1
INCH(BASE)
MM(REF)
0.015(MIN)
0.155±0.005
0.018±0.005
1.650±0.01
0.600±0.010
0.545±0.005
0.100(TYP)
0.650±0.020
0.158±0.043
0.075±0.010
0.070±0.005
0.381(MIN)
3.937±0.127
0.457±0.127
41.910±0.254
15.240±0.254
13.843±0.127
2.540(TYP)
16.510±0.508.
4.013±1.092
1.905±0.254
1.778±0.127
Note : D/E1/S dimension do not include mold flash.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
13
®
LY62L5128
Rev. 1.12
512K X 8 BIT LOW POWER CMOS SRAM
32-pin 400mil TSOP-Ⅱ Package Outline Dimension
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
14
®
LY62L5128
Rev. 1.12
512K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
15
®
LY62L5128
Rev. 1.12
512K X 8 BIT LOW POWER CMOS SRAM
THIS PAGE IS LEFT BLANK INTENTIONALLY.
Lyontek Inc. reserves the rights to change the specifications and products without notice.
5F, No. 2, Industry E. Rd. IX, Science-Based Industrial Park, Hsinchu 300, Taiwan.
TEL: 886-3-6668838
FAX: 886-3-6668836
16
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