AD AD5686BCPZ-RL7 Quad, 16-/12-bit nanodac with spi interface Datasheet

Quad, 16-/12-Bit nanoDAC+
with SPI Interface
AD5686/AD5684
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
High relative accuracy (INL): ±2 LSB maximum @ 16 bits
Tiny package: 3 mm × 3 mm, 16-lead LFCSP
Total unadjusted error (TUE): ±0.1% of FSR maximum
GND
VREF
AD5686/AD5684
VLOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
SCLK
VOUTA
BUFFER
INTERFACE LOGIC
SYNC
SDIN
SDO
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
VOUTB
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
VOUTC
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
VOUTD
BUFFER
LDAC RESET
POWER-ON
RESET
GAIN
×1/×2
RSTSEL
GAIN
POWERDOWN
LOGIC
10797-001
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
High drive capability: 20 mA, 0.5 V from supply rails
User selectable gain of 1 or 2 (GAIN pin)
Reset to zero scale or midscale (RSTSEL pin)
1.8 V logic compatibility
50 MHz SPI with readback or daisy chain
Low glitch: 0.5 nV-sec
Robust 4 kV HBM and 1.5 kV FICDM ESD rating
Low power: 1.8 mW at 3 V
2.7 V to 5.5 V power supply
−40°C to +105°C temperature range
VDD
Figure 1.
APPLICATIONS
Digital gain and offset adjustment
Programmable attenuators
Process control (PLC I/O cards)
Industrial automation
Data acquisition systems
Table 1. Quad nanoDAC+ Devices
GENERAL DESCRIPTION
The AD5686/AD5684, members of the nanoDAC+™ family, are
low power, quad, 16-/12-bit buffered voltage output DACs.
The devices include a gain select pin giving a full-scale output
of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from
a single 2.7 V to 5.5 V supply, are guaranteed monotonic by
design, and exhibit less than 0.1% FSR gain error and 1.5 mV
offset error performance. The devices are available in a 3 mm
× 3 mm LFCSP and a TSSOP package.
The AD5686/AD5684 also incorporate a power-on reset circuit
and a RSTSEL pin that ensures that the DAC outputs power up
to zero scale or midscale and remain at that level until a valid
write takes place. Each part contains a per-channel power-down
feature that reduces the current consumption of the device to
4 µA at 3 V while in power-down mode.
The AD5686/AD5684 employ a versatile SPI interface that
operates at clock rates up to 50 MHz, and all devices contain
a VLOGIC pin intended for 1.8 V/3 V/5 V logic.
Rev. A
Interface
SPI
SPI
I2 C
I2 C
Reference
Internal
External
Internal
External
16-Bit
AD5686R
AD5686
AD5696R
AD5696
14-Bit
AD5685R
AD5695R
12-Bit
AD5684R
AD5684
AD5694R
AD5694
PRODUCT HIGHLIGHTS
1.
2.
3.
High Relative Accuracy (INL).
AD5686 (16-bit): ±2 LSB maximum
AD5684 (12-bit): ±1 LSB maximum
Excellent DC Performance.
Total unadjusted error: ±0.1% of FSR maximum
Offset error: ±1.5 mV maximum
Gain error: ±0.1% of FSR maximum
Two Package Options.
3 mm × 3 mm, 16-lead LFCSP
16-lead TSSOP
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Technical Support
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AD5686/AD5684
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Serial Interface ............................................................................ 19
Applications ....................................................................................... 1
Standalone Operation ................................................................ 20
Functional Block Diagram .............................................................. 1
Write and Update Commands .................................................. 20
General Description ......................................................................... 1
Daisy-Chain Operation ............................................................. 20
Product Highlights ........................................................................... 1
Readback Operation .................................................................. 21
Revision History ............................................................................... 2
Power-Down Operation ............................................................ 21
Specifications..................................................................................... 3
Load DAC (Hardware LDAC Pin) ........................................... 22
AC Characteristics ........................................................................ 5
LDAC Mask Register ................................................................. 22
Timing Characteristics ................................................................ 6
Hardware Reset (RESET) .......................................................... 23
Daisy-Chain and Readback Timing Characteristics................ 7
Reset Select Pin (RSTSEL) ........................................................ 23
Absolute Maximum Ratings ............................................................ 9
Applications Information .............................................................. 24
ESD Caution .................................................................................. 9
Microprocessor Interfacing ....................................................... 24
Pin Configurations and Function Descriptions ......................... 10
AD5686/AD5684 to ADSP-BF531 Interface .......................... 24
Typical Performance Characteristics ........................................... 11
AD5686/AD5684 to SPORT Interface .................................... 24
Terminology .................................................................................... 16
Layout Guidelines....................................................................... 24
Theory of Operation ...................................................................... 18
Galvanically Isolated Interface ................................................. 25
Digital-to-Analog Converter .................................................... 18
Outline Dimensions ....................................................................... 26
Transfer Function ....................................................................... 18
Ordering Guide .......................................................................... 27
DAC Architecture ....................................................................... 18
REVISION HISTORY
6/13—Rev. 0 to Rev. A
Changes to Pin GAIN and Pin RSTSEL Descriptions; Table 7......10
7/12—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
AD5686/AD5684
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; all specifications TMIN to TMAX, unless otherwise noted. RL = 2 kΩ; CL = 200 pF.
Table 2.
Parameter
STATIC PERFORMANCE 2
AD5686
Resolution
Relative Accuracy
Min
A Grade 1
Typ
Max
16
Min
B Grade1
Typ
Max
Unit
Test Conditions/Comments
±1
±1
±2
±3
±1
Bits
LSB
LSB
LSB
Gain = 2
Gain = 1
Guaranteed monotonic by design
±0.12
16
±2
±2
±8
±8
±1
±0.12
0.4
+0.1
+0.01
±2
±1
4
±4
±0.2
0.4
+0.1
+0.01
±1
±1
1.5
±1.5
±0.1
Gain Error
±0.02
±0.2
±0.02
±0.1
Total Unadjusted Error
±0.01
±0.25
±0.01
±0.1
Differential Nonlinearity
AD5684
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
12
12
±1
±1
Bits
LSB
LSB
mV
mV
% of
FSR
% of
FSR
% of
FSR
% of
FSR
µV/°C
±1
±1
ppm
Of FSR/°C
0.15
0.15
mV/V
DAC code = midscale; VDD = 5 V ± 10%
±2
±2
µV
±3
±2
±3
±2
µV/mA
µV
Due to single channel, full-scale
output change
Due to load current change
Due to powering down (per channel)
±0.25
Offset Error Drift3
Gain Temperature
Coefficient3
DC Power Supply Rejection
Ratio3
DC Crosstalk3
OUTPUT CHARACTERISTICS 3
Output Voltage Range
0
0
Capacitive Load Stability
VREF
2 × VREF
±0.2
0
0
Gain = 2
Gain = 1
Gain = 1
Gain = 2, see Figure 23
RL = ∞
RL = 1 kΩ
80
80
80
80
µV/mA
Short-Circuit Current 5
Load Impedance at Rails 6
40
25
40
25
mA
Ω
Power-Up Time
2.5
2.5
µs
See Figure 23
Coming out of power-down mode;
VDD = 5 V
90
180
90
180
µA
µA
V
V
kΩ
kΩ
VREF = VDD = VLOGIC =5.5 V, gain = 1
VREF = VDD = VLOGIC =5.5 V, gain = 2
Gain = 1
Gain = 2
Gain = 2
Gain = 1
1
REFERENCE INPUT
Reference Current
Reference Input Range
Reference Input Impedance
2
10
V
V
All 1s loaded to DAC register
nF
nF
kΩ
µV/mA
Resistive Load 4
Load Regulation
2
10
VREF
2 × VREF
Guaranteed monotonic by design
All 0s loaded to DAC register
1
1
1
VDD
VDD/2
16
32
1
1
VDD
VDD/2
16
32
Rev. A | Page 3 of 28
5 V ± 10%, DAC code = midscale;
−30 mA ≤ IOUT ≤ +30 mA
3 V ± 10%, DAC code = midscale;
−20 mA ≤ IOUT ≤ +20 mA
AD5686/AD5684
Parameter
Data Sheet
Min
A Grade 1
Typ
Max
Min
B Grade1
Typ
Max
Unit
Test Conditions/Comments
±2
0.3 × VLOGIC
µA
V
V
pF
Per pin
0.4
V
V
pF
ISINK = 200 μA
ISOURCE = 200 μA
5.5
3
5.5
5.5
V
µA
V
V
0.7
4
6
mA
µA
µA
3
LOGIC INPUTS
Input Current
Input Low Voltage (VINL)
Input High Voltage (VINH)
Pin Capacitance
LOGIC OUTPUTS (SDO)3
Output Low Voltage, VOL
Output High Voltage, VOH
Floating State Output
Capacitance
POWER REQUIREMENTS
VLOGIC
ILOGIC
VDD
±2
0.3 × VLOGIC
0.7 × VLOGIC
0.7 × VLOGIC
2
2
0.4
VLOGIC − 0.4
VLOGIC − 0.4
4
1.8
4
5.5
3
5.5
5.5
2.7
VREF + 1.5
1.8
2.7
VREF + 1.5
IDD
Normal Mode 7
All Power-Down Modes 8
0.59
1
0.7
4
6
0.59
1
Gain = 1
Gain = 2
VIH = VDD, VIL = GND, VDD = 2.7 V to 5.5 V
−40°C to +85°C
−40°C to +105°C
Temperature range, A and B grade: −40°C to +105°C.
DC specifications tested with the outputs unloaded, unless otherwise noted. Upper dead band = 10 mV and exists only when VREF = VDD with gain = 1 or when VREF/2 =
VDD with gain = 2. Linearity calculated using a reduced code range of 256 to 65,280 (AD5686) or 12 to 4080 (AD5684).
3
Guaranteed by design and characterization; not production tested.
4
Channel A and Channel B can have a combined output current of up to 30 mA. Similarly, Channel C and Channel D can have a combined output current of up to
30 mA up to a junction temperature of 110°C.
5
VDD = 5 V. The device includes current limiting that is intended to protect the device during temporary overload conditions. Junction temperature can be exceeded
during current limit. Operation above the specified maximum operation junction temperature may impair device reliability.
6
When drawing a load current at either rail, the output voltage headroom with respect to that rail is limited by the 25 Ω typical channel resistance of the output
devices. For example, when sinking 1 mA, the minimum output voltage = 25 Ω × 1 mA = 25 mV (see Figure 23).
7
Interface inactive. All DACs active. DAC outputs unloaded.
8
All DACs powered down.
1
2
Rev. A | Page 4 of 28
Data Sheet
AD5686/AD5684
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; VREF = 2.5 V; 1.8 V ≤ VLOGIC ≤ 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless
otherwise noted. 1
Table 3.
Parameter 2
Output Voltage Settling Time
AD5686
AD5684
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Multiplying Bandwidth
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Total Harmonic Distortion 4
Output Noise Spectral Density
Output Noise
SNR
SFDR
SINAD
Min
Typ
Max
Unit
Test Conditions/Comments 3
5
5
0.8
0.5
0.13
500
0.1
0.2
0.3
−80
100
6
90
83
80
8
7
µs
µs
V/µs
nV-sec
nV-sec
kHz
nV-sec
nV-sec
nV-sec
dB
nV/√Hz
µV p-p
dB
dB
dB
¼ to ¾ scale settling to ±2 LSB
¼ to ¾ scale settling to ±2 LSB
Guaranteed by design and characterization; not production tested.
See the Terminology section.
3
Temperature range is −40°C to +105°C, typical @ 25°C.
4
Digitally generated sine wave @ 1 kHz.
1
2
Rev. A | Page 5 of 28
1 LSB change around major carry
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
DAC code = midscale, 10 kHz; gain = 2
0.1 Hz to 10 Hz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
At ambient, BW = 20 kHz, VDD = 5 V, fOUT = 1 kHz
AD5686/AD5684
Data Sheet
TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 2.
VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge Setup Time
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
SYNC Falling Edge to SCLK Fall Ignore
LDAC Pulse Width Low
SCLK Falling Edge to LDAC Rising Edge
SCLK Falling Edge to LDAC Falling Edge
RESET Minimum Pulse Width Low
RESET Pulse Activation Time
Power-Up Time2
2
2.7 V ≤ VLOGIC ≤ 5.5 V
Min
Max
20
10
10
10
5
5
10
20
10
15
20
20
30
30
4.5
Maximum SCLK frequency is 50 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Time to exit power-down to normal mode of AD5686/AD5684 operation, 32nd clock edge to 90% of DAC midscale value, with output unloaded.
t9
t1
SCLK
t8
t3
t4
t2
t7
SYNC
t5
SDIN
t6
DB23
DB0
t12
t10
LDAC1
t11
LDAC2
RESET
VOUT
t13
t14
10797-002
1
1.8 V ≤ VLOGIC < 2.7 V
Min
Max
33
16
16
15
8
8
15
20
16
25
30
20
30
30
4.5
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
1ASYNCHRONOUS LDAC UPDATE MODE.
2SYNCHRONOUS LDAC UPDATE MODE.
Figure 2. Serial Write Operation
Rev. A | Page 6 of 28
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
μs
Data Sheet
AD5686/AD5684
DAISY-CHAIN AND READBACK TIMING CHARACTERISTICS
All input signals are specified with tR = tF = 1 ns/V (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. See Figure 4
and Figure 5. VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ 5.5 V; VREF = 2.5 V. All specifications TMIN to TMAX, unless otherwise noted.
Table 5.
1.8 V ≤ VLOGIC < 2.7 V
Max
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
Min
66
33
33
33
5
5
15
60
60
15
10
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYNC Rising Edge to SCLK Rising Edge
t12
15
10
ns
1
Min
40
20
20
20
5
5
10
30
30
2.7 V ≤ VLOGIC ≤ 5.5 V
Max
Parameter 1
SCLK Cycle Time
SCLK High Time
SCLK Low Time
SYNC to SCLK Falling Edge
Data Setup Time
Data Hold Time
SCLK Falling Edge to SYNC Rising Edge
Minimum SYNC High Time
Minimum SYNC High Time
SDO Data Valid from SCLK Rising Edge
SCLK Falling Edge to SYNC Rising Edge
36
25
Maximum SCLK frequency is 25 MHz or 15 MHz at VDD = 2.7 V to 5.5 V, 1.8 V ≤ VLOGIC ≤ VDD. Guaranteed by design and characterization; not production tested.
Circuit and Timing Diagrams
200µA
VOH (MIN)
CL
20pF
200µA
10797-003
TO OUTPUT
PIN
IOL
IOH
Figure 3. Load Circuit for Digital Output (SDO) Timing Specifications
SCLK
24
48
t11
t8
t12
t4
SYNC
SDIN
t6
DB23
DB0
INPUT WORD FOR DAC N
DB23
DB0
t10
INPUT WORD FOR DAC N + 1
DB23
SDO
UNDEFINED
DB0
INPUT WORD FOR DAC N
Figure 4. Daisy-Chain Timing Diagram
Rev. A | Page 7 of 28
10797-004
t5
AD5686/AD5684
Data Sheet
t1
SCLK
24
1
t8
t4
t3
24
1
t7
t2
t9
SYNC
t6
t5
DB23
DB0
DB23
INPUT WORD SPECIFIES
REGISTER TO BE READ
SDO
DB23
DB0
NOP CONDITION
t10
DB0
DB23
UNDEFINED
DB0
SELECTED REGISTER DATA
CLOCKED OUT
Figure 5. Readback Timing Diagram
Rev. A | Page 8 of 28
10797-005
SDIN
Data Sheet
AD5686/AD5684
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter
VDD to GND
VLOGIC to GND
VOUT to GND
VREF to GND
Digital Input Voltage to GND
Operating Temperature Range
Storage Temperature Range
Junction Temperature
16-Lead TSSOP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
16-Lead LFCSP, θJA Thermal
Impedance, 0 Airflow (4-Layer Board)
Reflow Soldering Peak
Temperature, Pb Free (J-STD-020)
ESD
HBM 1
FICDM
1
Rating
−0.3 V to +7 V
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VLOGIC + 0.3 V
−40°C to +105°C
−65°C to +150°C
125°C
112.6°C/W
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
70°C/W
260°C
4 kV
1.5 kV
Human body model (HBM) classification.
Rev. A | Page 9 of 28
AD5686/AD5684
Data Sheet
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
13 RESET
14 RSTSEL
16 VOUTB
15 VREF
AD5686/AD5684
VOUTA 1
11 SYNC
VDD 3
10 SCLK
9 VLOGIC
16
RSTSEL
VOUTB 2
15
RESET
14
SDIN
13
SYNC
VOUTA 3
AD5686/
AD5684
GND 4
GAIN 8
LDAC 7
SDO 6
VOUTD 5
VOUTC 4
VREF 1
NOTES
1. THE EXPOSED PAD MUST BE TIED TO GND.
10797-006
TOP VIEW
(Not to Scale)
Figure 6. 16-Lead LFCSP Pin Configuration
TOP VIEW
(Not to Scale)
12
SCLK
VOUTC 6
11
VLOGIC
VOUTD 7
10
GAIN
SDO 8
9
LDAC
VDD 5
10797-007
12 SDIN
GND 2
Figure 7. 16-Lead TSSOP Pin Configuration
Table 7. Pin Function Descriptions
LFCSP
1
2
3
Pin No.
TSSOP
3
4
5
Mnemonic
VOUTA
GND
VDD
4
5
6
6
7
8
VOUTC
VOUTD
SDO
7
9
LDAC
8
10
GAIN
9
10
11
12
VLOGIC
SCLK
11
13
SYNC
12
14
SDIN
13
15
RESET
14
16
RSTSEL
15
16
17
1
2
N/A
VREF
VOUTB
EPAD
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Power Supply Input. These parts can be operated from 2.7 V to 5.5 V, and the supply should be
decoupled with a 10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Serial Data Output. Can be used to daisy-chain a number of AD5686/AD5684 devices together or
can be used for readback. The serial data is transferred on the rising edge of SCLK and is valid on
the falling edge of the clock.
LDAC can be operated in two modes, asynchronously and synchronously. Pulsing this pin low allows
any or all DAC registers to be updated if the input registers have new data. This allows all DAC outputs
to be simultaneously updated. This pin can also be tied permanently low.
Span Set Pin. When this pin is tied to GND, all four DAC outputs have a span from 0 V to VREF. When
this pin is tied to VLOGIC, all four DAC outputs have a span from 0 V to 2 × VREF.
Digital Power Supply. Voltage ranges from 1.8 V to 5.5 V.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock
input. Data can be transferred at rates of up to 50 MHz.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC
goes low, data is transferred in on the falling edges of the next 24 clocks.
Serial Data Input. These devices have a 24-bit input shift register. Data is clocked into the register on
the falling edge of the serial clock input.
Asynchronous Reset Input. The RESET input is falling edge sensitive. When RESET is low, all LDAC
pulses are ignored. When RESET is activated, the input register and the DAC register are updated with
zero scale or midscale, depending on the state of the RSTSEL pin.
Power-On Reset Pin. Tying this pin to GND powers up all four DACs to zero scale. Tying this pin to
VLOGIC powers up all four DACs to midscale.
Reference Input Voltage.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Exposed Pad. The exposed pad must be tied to GND.
Rev. A | Page 10 of 28
Data Sheet
AD5686/AD5684
1.0
8
0.8
6
0.6
4
0.4
2
0.2
0
–2
0
–0.2
–4
–0.4
–6
–0.6
V = 5V
–8 DD
TA = 25°C
REFERENCE = 2.5V
–10
0
10000
20000
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–0.8
30000
40000
50000
60000
CODE
–1.0
0
625
1250
3125
3750 4096
Figure 11. AD5684 DNL
10
10
8
8
6
6
4
4
ERROR (LSB)
2
0
–2
–4
2
INL
0
DNL
–2
–4
–6
–6
0
625
1250
1875
2500
3125
3750 4096
CODE
0.8
8
0.6
6
0.4
4
ERROR (LSB)
10
0.2
0
–0.2
2
110
DNL
–2
–4
–0.6
–6
V = 5V
–0.8 DD
TA = 25°C
REFERENCE = 2.5V
–1.0
0
10000
20000
–8
60000
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
10797-121
50000
INL
0
–0.4
CODE
60
Figure 12. INL Error and DNL Error vs. Temperature
1.0
40000
10
TEMPERATURE (°C)
Figure 9. AD5684 INL
30000
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
–40
10797-120
–10
–8
10797-124
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–8
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VREF (V)
Figure 10. AD5686 DNL
Figure 13. INL Error and DNL Error vs. VREF
Rev. A | Page 11 of 28
4.5
5.0
10797-125
INL (LSB)
2500
CODE
Figure 8. AD5686 INL
DNL (LSB)
1875
10797-123
DNL (LSB)
10
10797-118
INL (LSB)
TYPICAL PERFORMANCE CHARACTERISTICS
Data Sheet
10
0.10
8
0.08
6
0.06
4
0.04
ERROR (% of FSR)
2
INL
0
DNL
–2
–4
–6
GAIN ERROR
0
FULL-SCALE ERROR
–0.02
–0.04
–0.06
VDD = 5V
–0.08 T = 25°C
A
REFERENCE = 2.5V
–0.10
2.7
3.2
3.7
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–10
2.7
3.2
3.7
4.2
4.7
10797-126
–8
0.02
5.2
SUPPLY VOLTAGE (V)
4.2
4.7
10797-129
ERROR (LSB)
AD5686/AD5684
5.2
SUPPLY VOLTAGE (V)
Figure 14. INL Error and DNL Error vs. Supply Voltage
Figure 17. Gain Error and Full-Scale Error vs. Supply Voltage
1.5
0.10
0.08
1.0
0.04
0.5
ERROR (mV)
FULL-SCALE ERROR
0.02
0
GAIN ERROR
–0.02
ZERO-CODE ERROR
0
OFFSET ERROR
–0.5
–0.04
–0.06
–1.0
40
60
80
100
120
TEMPERATURE (°C)
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
–1.5
2.7
10797-127
VDD = 5V
–0.08 T = 25°C
A
REFERENCE = 2.5V
–0.10
–40
–20
0
20
3.2
3.7
4.2
4.7
10797-130
ERROR (% of FSR)
0.06
5.2
SUPPLY VOLTAGE (V)
Figure 15. Gain Error and Full-Scale Error vs. Temperature
Figure 18. Zero-Code Error and Offset Error vs. Supply Voltage
0.10
1.2
0.8
0.6
0.4
ZERO-CODE ERROR
0.2
OFFSET ERROR
0
–40
–20
0
20
40
60
80
100
120
TEMPERATURE (°C)
10797-128
ERROR (mV)
1.0
Figure 16. Zero-Code Error and Offset Error vs. Temperature
VDD = 5V
0.09 TA = 25°C
REFERENCE = 2.5V
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
–40
–20
0
20
40
60
80
TEMPERATURE (°C)
Figure 19. TUE vs. Temperature
Rev. A | Page 12 of 28
100
120
10797-131
TOTAL UNADJUSTED ERROR (% of FSR)
VDD = 5V
1.4 T = 25°C
A
REFERENCE = 2.5V
AD5686/AD5684
0.10
1.0
0.08
0.8
0.06
0.6
0.04
0.4
0.02
0.2
0
–0.02
–0.2
–0.04
–0.4
–0.06
–0.6
V = 5V
–0.08 T DD= 25°C
A
REFERENCE = 2.5V
–0.10
2.7
3.2
3.7
SOURCING 5V
SOURCING 2.7V
–0.8
4.2
4.7
5.2
SUPPLY VOLTAGE (V)
–1.0
0
5
10
15
20
25
30
LOAD CURRENT (mA)
Figure 20. TUE vs. Supply Voltage, Gain = 1
Figure 23. Headroom/Footroom vs. Load Current
0
7
VDD = 5V
6 TA = 25°C
GAIN = 2
REFERENCE = 2.5V
5
–0.01
–0.02
0xFFFF
–0.03
4
0xC000
VOUT (V)
–0.04
–0.05
–0.06
3
0x4000
1
–0.08
0
–1
30000
40000
50000
60000 65535
CODE
–2
–0.06
–0.04
–0.02
0
0.02
0.04
0.06
LOAD CURRENT (A)
Figure 21. TUE vs. Code
25
0x0000
10797-138
VDD = 5V
–0.09 T = 25°C
A
REFERENCE = 2.5V
–0.10
0
10000
20000
0x8000
2
–0.07
10797-133
TOTAL UNADJUSTED ERROR (% of FSR)
SINKING 5V
0
10797-200
∆VOUT (V)
SINKING 2.7V
10797-132
TOTAL UNADJUSTED ERROR (% of FSR)
Data Sheet
Figure 24. Source and Sink Capability at 5 V
5
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
VDD = 3V
TA = 25°C
4 REFERENCE = 2.5V
GAIN = 1
20
0xFFFF
3
VOUT (V)
10
2
0x8000
1
0x4000
0
0x0000
5
0
540
560
580
600
IDD (mA)
620
640
Figure 22. IDD Histogram
–2
–0.06
–0.04
–0.02
0
0.02
0.04
LOAD CURRENT (A)
Figure 25. Source and Sink Capability at 3 V
Rev. A | Page 13 of 28
0.06
10797-139
–1
10797-135
HITS
0xC000
15
AD5686/AD5684
Data Sheet
3
CH A
CH B
CH C
CH D
SYNC
1.4
1.2
2
VOUT (V)
CURRENT (mA)
1.0
0.8
0.6
GAIN = 2
FULL-SCALE
GAIN = 1
1
0.4
10
60
0
–5
10797-140
0
–40
110
TEMPERATURE (°C)
5
10
TIME (µs)
Figure 26. Supply Current vs. Temperature
Figure 29. Exiting Power-Down to Midscale
2.5008
4.0
3.5
0
10797-143
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
0.2
DAC A
DAC B
DAC C
DAC D
3.0
2.5003
VOUT (V)
VOUT (V)
2.5
2.0
2.4998
1.5
CHANNEL B
TA = 25°C
VDD = 5.25V
REFERENCE = 2.5V
CODE = 7FFF TO 8000
ENERGY = 0.227206nV-sec
2.4993
40
80
160
320
TIME (µs)
2.4988
10797-141
VDD = 5V
0.5 TA = 25°C
REFERENCE = 2.5V
¼ TO ¾ SCALE
0
10
20
0
6
8
10
12
Figure 30. Digital-to-Analog Glitch Impulse
0.003
6
0.06
CH A
CH B
CH C
CH D
VDD
CH B
CH C
CH D
5
0.03
3
0.02
2
0.01
1
0
0
VDD (V)
4
VOUT AC-COUPLED (V)
0.002
0.04
0.001
0
TA = 25°C
REFERENCE = 2.5V
–0.01
–5
–10
0
5
10
TIME (µs)
–1
15
–0.002
0
5
10
15
20
TIME (µs)
Figure 31. Analog Crosstalk, Channel A
Figure 28. Power-On Reset to 0 V
Rev. A | Page 14 of 28
25
10797-145
–0.001
10797-142
VOUT (V)
4
TIME (µs)
Figure 27. Settling Time, 5 V
0.05
2
10797-144
1.0
Data Sheet
AD5686/AD5684
4.0
T
0nF
0.1nF
10nF
0.22nF
4.7nF
3.9
3.8
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
VOUT (V)
3.7
1
3.6
3.5
3.4
3.3
3.2
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
802mV
BANDWIDTH (dB)
–80
–100
–120
–140
FREQUENCY (Hz)
Figure 33. Total Harmonic Distortion @ 1 kHz
1.620
1.625
1.630
–20
–30
–40
–50
–160
VDD = 5V
TA = 25°C
REFERENCE = 2.5V, ±0.1V p-p
–60
10k
10797-149
THD (dBV)
–60
2000 4000 6000 8000 10000 12000 14000 16000 18000 20000
1.615
–10
–40
0
1.610
0
–20
–180
1.605
Figure 34. Settling Time vs. Capacitive Load
VDD = 5V
TA = 25°C
REFERENCE = 2.5V
0
1.600
TIME (ms)
Figure 32. 0.1 Hz to 10 Hz Output Noise Plot
20
1.595
10797-150
A CH1
100k
FREQUENCY (Hz)
1M
10M
10797-151
M1.0s
3.0
1.590
10797-146
CH1 10µV
3.1
Figure 35. Multiplying Bandwidth, Reference = 2.5 V, ±0.1 V p-p, 10 kHz to
10 MHz
Rev. A | Page 15 of 28
AD5686/AD5684
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a
straight line passing through the endpoints of the DAC transfer
function. A typical INL vs. code plot is shown in Figure 8.
Output Voltage Settling Time
The output voltage setting time is the amount of time it takes
for the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge
of SYNC.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of ±1 LSB maximum
ensures monotonicity. These DACs are guaranteed monotonic
by design. A typical DNL vs. code plot can be seen in Figure 10.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-sec,
and is measured when the digital input code is changed by
1 LSB at the major carry transition (0x7FFF to 0x8000) (see
Figure 30).
Zero-Code Error
Zero-code error is a measurement of the output error when
zero code (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5686/AD5684 because the output of the DAC cannot go
below 0 V due to a combination of the offset errors in the DAC
and the output amplifier. Zero-code error is expressed in mV. A
plot of zero-code error vs. temperature can be seen in Figure 16.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in
percent of full-scale range (% of FSR). A plot of full-scale error
vs. temperature can be seen in Figure 15.
Gain Error
Gain error is a measurement of the span error of the DAC. It is
the deviation in slope of the DAC transfer characteristic from
the ideal expressed as % of FSR.
Offset Error Drift
Offset error drift is a measurement of the change in offset error
with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measurement of the difference between VOUT
(actual) and VOUT (ideal) expressed in mV in the linear region of
the transfer function. It can be negative or positive.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC,
but is measured when the DAC output is not updated. It is
specified in nV-sec and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Noise Spectral Density
Noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density (nV/√Hz). It is measured by loading the DAC
to midscale and measuring noise at the output. It is measured in
nV/√Hz.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC
in response to a change in the output of another DAC. It is
measured with a full-scale output change on one DAC (or soft
power-down and power-up) while monitoring another DAC
kept at midscale. It is expressed in μV.
DC crosstalk due to load current change is a measurment of
the impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in μV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in
nV-sec.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in mV/V. VREF is held at 2.5 V, and VDD is varied by
±10%.
Rev. A | Page 16 of 28
Data Sheet
AD5686/AD5684
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa). Then execute a
software LDAC and monitor the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-sec.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to
the output of one DAC in response to a digital code change
and subsequent analog output change of another DAC. It is
measured by loading the attack channel with a full-scale code
change (all 0s to all 1s and vice versa) using the write to and
update commands while monitoring the output of another
channel that is at midscale. The energy of the glitch is
expressed in nV-sec.
Multiplying Bandwidth
The amplifiers within the DAC have a finite bandwidth. The
multiplying bandwidth is a measure of this. A sine wave on the
reference (with full-scale code loaded to the DAC) appears on
the output.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and its
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Rev. A | Page 17 of 28
AD5686/AD5684
Data Sheet
THEORY OF OPERATION
DIGITAL-TO-ANALOG CONVERTER
The AD5686/AD5684 are quad, 16-/12-bit, serial input, voltage
output DACs. The parts operate from supply voltages of 2.7 V to
5.5 V. Data is written to the AD5686/AD5684 in a 24-bit word
format via a 3-wire serial interface. The AD5686/AD5684
incorporate a power-on reset circuit to ensure that the DAC
output powers up to a known output state. The devices also
have a software power-down mode that reduces the typical
current consumption to typically 4 µA.
The resistor string structure is shown in Figure 37. It is a string
of resistors, each of Value R. The code loaded to the DAC register
determines the node on the string where the voltage is to be
tapped off and fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the
string to the amplifier. Because the DAC is a string of resistors,
it is guaranteed monotonic.
VREF
R
TRANSFER FUNCTION
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
R
D
VOUT = VREF × Gain  N 
 2 
R
DAC ARCHITECTURE
The DAC architecture consists of a string DAC followed by an
output amplifier. Figure 36 shows a block diagram of the DAC
architecture.
VREF
RESISTOR
STRING
REF (–)
GND
VOUTX
GAIN
(GAIN = 1 OR 2)
Figure 37. Resistor String Structure
Output Amplifiers
The output buffer amplifier can generate rail-to-rail voltages on
its output, which gives an output range of 0 V to VDD. The actual
range depends on the value of VREF, the GAIN pin, offset error,
and gain error. The GAIN pin selects the gain of the output.
•
•
10797-052
DAC
REGISTER
R
If this pin is tied to GND, all four outputs have a gain of 1,
and the output range is 0 V to VREF.
If this pin is tied to VDD, all four outputs have a gain of 2,
and the output range is 0 V to 2 × VREF.
These amplifiers are capable of driving a load of 1 kΩ in parallel
with 2 nF to GND. The slew rate is 0.8 V/µs with a ¼ to ¾ scale
settling time of 5 µs.
REF (+)
INPUT
REGISTER
R
10797-053
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register as follows:
0 to 4095 for the 12-bit device.
0 to 65,535 for the 16-bit device.
N is the DAC resolution.
VREF is the value of the external reference.
Gain is the gain of the output amplifier and is set to 1 by default.
The gain can be set to ×1 or ×2 using the gain select pin. When
this pin is tied to GND, all four DAC outputs have a span of 0 V
to VREF. When this pin is tied to VDD, all four DAC outputs have
a span of 0 V to 2 × VREF.
TO OUTPUT
AMPLIFIER
Figure 36. Single DAC Channel Architecture Block Diagram
Rev. A | Page 18 of 28
Data Sheet
AD5686/AD5684
SERIAL INTERFACE
Table 8. Command Bit Definitions
The AD5686/AD5684 have a 3-wire serial interface (SYNC,
SCLK, and SDIN) that is compatible with SPI, QSPI™, and
MICROWIRE® interface standards as well as most DSPs. See
Figure 2 for a timing diagram of a typical write sequence. The
AD5686/AD5684 contain an SDO pin to allow the user to daisychain multiple devices together (see the Daisy-Chain Operation
section) or for readback.
C3
0
0
0
Command Bits
C2 C1 C0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
1
1
…
1
Input Shift Register
The input shift register of the AD5686/AD5684 is 24 bits wide.
Data is loaded MSB first (DB23). The first four bits are the
command bits, C3 to C0 (see Table 8), followed by the 4-bit
DAC address bits, DAC A, DAC B, DAC C, andDAC D (see
Table 9), and finally the bit data-word.
For the AD5686, the data-word comprises 16-bit input code(see
Figure 38). For the AD5684, the data-word comprises 12-bit input
code, followed by zero or four don’t care bits (see Figure 39).
These data bits are transferred to the input register on the 24
falling edges of SCLK and are updated on the rising edge
of SYNC.
0
1
1
1
1
0
0
0
…
1
1
0
0
1
1
0
0
1
…
1
Description
No operation
Write to Input Register n (dependent on LDAC)
Update DAC Register n with contents of Input
Register n
Write to and update DAC Channel n
Power down/power up DAC
Hardware LDAC mask register
Software reset (power-on reset)
Reserved
Set up DCEN register (daisy-chain enable)
Set up readback register (readback enable)
Reserved
Reserved
Reserved
1
0
1
0
1
0
1
0
…
1
Table 9. Address Bits and Selected DACs
Address Bits
DAC C DAC B
0
0
0
1
1
0
0
0
0
1
1
1
DAC D
0
0
0
1
0
1
Commands can be executed on individual DAC channels,
combined DAC channels, or on all DACs, depending on the
address bits selected (see Table 9).
1
DAC A
1
0
0
0
1
1
Any combination of DAC channels can be selected using the address bits.
DB23 (MSB)
C3
C2
Selected DAC Channel 1
DAC A
DAC B
DAC C
DAC D
DAC A and DAC B
All DACs
DB0 (LSB)
C1
C0 DAC DAC DAC DAC D15 D14 D13 D12 D11 D10
D
C
B
A
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
COMMAND BITS
10797-054
DATA BITS
ADDRESS BITS
Figure 38. AD5686 Input Shift Register Contents
DB23 (MSB)
C3
C2
DB0 (LSB)
C1
C0 DAC DAC DAC DAC D11 D10
A
D
C
B
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
X
X
X
X
COMMAND BITS
10797-056
DATA BITS
ADDRESS BITS
Figure 39. AD5684 Input Shift Register Contents
Rev. A | Page 19 of 28
AD5686/AD5684
Data Sheet
STANDALONE OPERATION
AD5686/
AD5684
68HC11*
The write sequence begins by bringing the SYNC line low. Data
from the SDIN line is clocked into the 24-bit input shift register
on the falling edge of SCLK. After the last of 24 data bits is
clocked in, SYNC should be brought high. The programmed
function is then executed, that is, an LDAC-dependent change
in DAC register contents and/or a change in the mode of
operation. If SYNC is taken high at a clock before the 24th
clock, it is considered a valid frame and invalid data may be
loaded to the DAC. SYNC must be brought high for a minimum
of 20 ns (single channel, see t8 in Figure 2) before the next write
sequence so that a falling edge of SYNC can initiate the next
write sequence. SYNC should be idle at rails between write
sequences for even lower power operation of the part.
The SYNC line is kept low for 24 falling edges of SCLK, and the
DAC is updated on the rising edge of SYNC.
MOSI
SDIN
SCK
SCLK
PC7
SYNC
PC6
LDAC
SDO
MISO
SDIN
AD5686/
AD5684
SCLK
SYNC
LDAC
SDO
After data is transferred into the input register of the addressed
DAC, all DAC registers and outputs can be updated by
taking LDAC low while the SYNC line is high.
SDIN
AD5686/
AD5684
SCLK
WRITE AND UPDATE COMMANDS
SYNC
Write to Input Register n (Dependent on LDAC)
LDAC
*ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 40. Daisy-Chaining the AD5686/AD5684
Update DAC Register n with Contents of Input Register n
Command 0010 loads the DAC registers/outputs with the
contents of the selected input registers and updates the DAC
outputs directly.
Write to and Update DAC Channel n (Independent of
LDAC)
Command 0011 allows the user to write to the DAC registers
and update the DAC outputs directly.
DAISY-CHAIN OPERATION
For systems that contain several DACs, the SDO pin can be
used to daisy-chain several devices together. This function
is enabled through a software executable daisy-chain enable
(DCEN) command. Command 1000 is reserved for this DCEN
function (see Table 8). The daisy-chain mode is enabled by
setting Bit DB0 in the DCEN register. The default setting is
standalone mode, where DB0 = 0. Table 10 shows how the state
of the bit corresponds to the mode of operation of the device.
Table 10. Daisy-Chain Enable (DCEN) Register
DB0
0
1
Description
Standalone mode (default)
DCEN mode
10797-057
SDO
Command 0001 allows the user to write to each DAC’s
dedicated input register individually. When LDAC is low,
the input register is transparent (if not controlled by the
LDAC mask register).
The SCLK pin is continuously applied to the input shift register
when SYNC is low. If more than 24 clock pulses are applied, the
data ripples out of the input shift register and appears on the
SDO line. This data is clocked out on the rising edge of SCLK
and is valid on the falling edge. By connecting the SDO line to
the SDIN input on the next DAC in the chain, a daisy-chain
interface is constructed. Each DAC in the system requires 24
clock pulses. Therefore, the total number of clock cycles must
equal 24 × N, where N is the total number of devices that are
updated. If SYNC is taken high at a clock that is not a multiple
of 24, it is considered a valid frame and invalid data may be
loaded to the DAC. When the serial transfer to all devices is
complete, SYNC is taken high. This latches the input data in
each device in the daisy chain and prevents any further data
from being clocked into the input shift register. The serial clock
can be continuous or a gated clock. A continuous SCLK source
can be used only if SYNC can be held low for the correct
number of clock cycles. In gated clock mode, a burst clock
containing the exact number of clock cycles must be used,
and SYNC must be taken high after the final clock to latch the data.
Rev. A | Page 20 of 28
Data Sheet
AD5686/AD5684
READBACK OPERATION
Table 11. Modes of Operation
Readback mode is invoked through a software executable
readback command. If the SDO output is disabled via the daisychain mode disable bit in the control register, it is automatically
enabled for the duration of the read operation, after which it is
disabled again. Command 1001 is reserved for the readback
function. This command, in association with selecting one
of the address bits, DAC A to DAC D, selects the register to
read. Note that only one DAC register can be selected during
readback. The remaining three address bits must be set to
Logic 0. The remaining data bits in the write sequence are
don’t care bits. If more than one or no bits are selected, DAC
Channel A is read back by default. During the next SPI write,
the data appearing on the SDO output contains the data from
the previously addressed register.
Operating Mode
Normal Operation
Power-Down Modes
1 kΩ to GND
100 kΩ to GND
Three-State
2.
PDx0
0
0
1
1
1
0
1
Any or all DACs (DAC A to DAC D) can be powered down
to the selected mode by setting the corresponding bits. See
Table 12 for the contents of the input shift register during the
power-down/power-up operation.
When both Bit PDx1 and Bit PDx0 (where x is the channel
selected) in the input shift register are set to 0, the parts work
normally with their normal power consumption of 0.59 mA at
5 V. However, for the three power-down modes, the supply
current falls to 4 μA at 5 V. Not only does the supply current
fall, but the output stage is also internally switched from the
output of the amplifier to a resistor network of known values.
This has the advantage that the output impedance of the part is
known while the part is in power-down mode. There are three
different power-down options (see Table 11). The output is
connected internally to GND through either a 1 kΩ or a 100 kΩ
resistor, or it is left open-circuited (three-state). The output stage
is illustrated in Figure 41.
For example, to read back the DAC register for Channel A, the
following sequence should be implemented:
1.
PDx1
0
Write 0x900000 to the AD5686/AD5684 input register.
This configures the part for read mode with the DAC
register of Channel A selected. Note that all data bits,
DB15 to DB0, are don’t care bits.
Follow this with a second write, a NOP condition,
0x000000. During this write, the data from the register
is clocked out on the SDO line. DB23 to DB20 contain
undefined data, and the last 16 bits contain the DB19 to
DB4 DAC register contents.
AMPLIFIER
DAC
VOUTX
POWER-DOWN OPERATION
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
10797-058
The AD5686/AD5684 provide three separate power-down
modes (see Table 11). Command 0100 is designated for the powerdown function (see Table 8). These power-down modes are
software programmable by setting eight bits, Bit DB7 to Bit DB0,
in the input shift register. Two bits are associated with each DAC
channel. Table 11 shows how the state of the two bits corresponds
to the mode of operation of the device.
Figure 41. Output Stage During Power-Down
The bias generator, output amplifier, resistor string, and other
associated linear circuitry are shut down when the power-down
mode is activated. However, the contents of the DAC registers
are unaffected when in power-down. The DAC registers can be
updated while the device is in power-down mode. The time
required to exit power-down is typically 4.5 µs for VDD = 5 V.
Table 12. 24-Bit Input Shift Register Contents for Power-Down/Power-Up Operation 1
DB23
0
DB22
1
DB21
0
DB20
0
Command bits (C3 to C0)
1
DB19 to DB16
X
Address bits
(don’t care)
DB15
to
DB8
X
DB7
PDD1
DB6
PDD0
Power-Down
Select DAC D
X = don’t care.
Rev. A | Page 21 of 28
DB5
PDC1
DB4
PDC0
Power-Down
Select DAC C
DB3
PDB1
DB2
PDB0
Power-Down
Select DAC B
DB1
PDA1
DB0
(LSB)
PDA0
Power-Down
Select DAC A
AD5686/AD5684
Data Sheet
LOAD DAC (HARDWARE LDAC PIN)
LDAC MASK REGISTER
The AD5686/AD5684 DACs have double buffered interfaces
consisting of two banks of registers: input registers and DAC
registers. The user can write to any combination of the input
registers. Updates to the DAC register are controlled by the
LDAC pin.
Command 0101 is reserved for the software LDAC function.
Address bits are ignored. Writing to the DAC using Command
0101 loads the 4-bit LDAC register (DB3 to DB0). The default
for each channel is 0; that is, the LDAC pin works normally.
Setting the bits to 1 forces this DAC channel to ignore transitions
on the LDAC pin, regardless of the state of the hardware LDAC
pin. This flexibility is useful in applications where the user
wishes to select which channels respond to the LDAC pin.
OUTPUT
AMPLIFIER
VREF
16-/12-BIT
DAC
LDAC
DAC
REGISTER
VOUTX
The LDAC register gives the user extra flexibility and control
over the hardware LDAC pin (see Table 13). Setting the LDAC
bits (DB3 to DB0) to 0 for a DAC channel means that this
channel’s update is controlled by the hardware LDAC pin.
INPUT
REGISTER
Load LDAC Register
INTERFACE
LOGIC
SDO
10797-059
SCLK
SYNC
SDIN
Table 13. LDAC Overwrite Definition
LDAC Bits
(DB3 to DB0)
0
1
Figure 42. Simplified Diagram of Input Loading Circuitry for a Single DAC
Instantaneous DAC Updating (LDAC Held Low)
LDAC is held low while data is clocked into the input register
using Command 0001. Both the addressed input register and
the DAC register are updated on the rising edge of SYNC and
the output begins to change (see Table 14).
1
LDAC Pin
LDAC Operation
1 or 0
X1
Determined by the LDAC pin.
DAC channels are updated and
override the LDAC pin. DAC
channels see LDAC as 1.
X = don’t care.
Deferred DAC Updating (LDAC Is Pulsed Low)
LDAC is held high while data is clocked into the input register
using Command 0001. All DAC outputs are asynchronously
updated by taking LDAC low after SYNC has been taken
high. The update now occurs on the falling edge of LDAC.
Table 14. Write Commands and LDAC Pin Truth Table1
Command
0001
Description
Write to Input Register n (dependent on LDAC)
0010
Update DAC Register n with contents of Input
Register n
0011
Write to and update DAC Channel n
Hardware LDAC
Pin State
VLOGIC
GND2
Input Register
Contents
Data update
Data update
DAC Register Contents
No change (no update)
Data update
VLOGIC
No change
Updated with input register contents
GND
VLOGIC
GND
No change
Data update
Data update
Updated with input register contents
Data update
Data update
A high to low hardware LDAC pin transition always updates the contents of the DAC register with the contents of the input register on channels that are not masked
(blocked) by the LDAC mask register.
2
When LDAC is permanently tied low, the LDAC mask bits are ignored.
1
Rev. A | Page 22 of 28
Data Sheet
AD5686/AD5684
HARDWARE RESET (RESET)
RESET SELECT PIN (RSTSEL)
RESET is an active low reset that allows the outputs to be
cleared to either zero scale or midscale. The clear code value is
user selectable via the RESET select pin. It is necessary to
keep RESET low for a minimum of 30 ns to complete the
operation (see Figure 2). When the RESET signal is returned
high, the output remains at the cleared value until a new value
is programmed. The outputs cannot be updated with a new
value while the RESET pin is low. There is also a software
executable reset function that resets the DAC to the poweron reset code. Command 0110 is designated for this software
reset function (see Table 8). Any events on LDAC or RESET
during power-on reset are ignored.
The AD5686/AD5684 contain a power-on reset circuit that
controls the output voltage during power-up. By connecting
the RSTSEL pin low, the output powers up to zero scale. Note
that this is outside the linear region of the DAC. By connecting
the RSTSEL pin high, VOUT powers up to midscale. The output
remains powered up at this level until a valid write sequence
is made to the DAC.
Rev. A | Page 23 of 28
AD5686/AD5684
Data Sheet
APPLICATIONS INFORMATION
MICROPROCESSOR INTERFACING
LAYOUT GUIDELINES
Microprocessor interfacing to the AD5686/AD5684 is via a
serial bus that uses a standard protocol that is compatible with
DSP processors and microcontrollers. The communications
channel requires a 3- or 4-wire interface consisting of a clock
signal, a data signal, and a synchronization signal. The devices
require a 24-bit data-word with data valid on the rising edge
of SYNC.
In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to
ensure the rated performance. The PCB on which the AD5686/
AD5684 are mounted should be designed so that the AD5686/
AD5684 lie on the analog plane.
AD5686/AD5684 TO ADSP-BF531 INTERFACE
The SPI interface of the AD5686/AD5684 is designed to be
easily connected to industry-standard DSPs and microcontrollers. Figure 43 shows the AD5686/AD5684 connected
to the Analog Devices, Inc., Blackfin® DSP. The Blackfin has an
integrated SPI port that can be connected directly to the SPI
pins of the AD5686/AD5684.
AD5686/
AD5684
ADSP-BF531
PF9
PF8
SYNC
SCLK
SDIN
LDAC
RESET
10797-164
SPISELx
SCK
MOSI
Figure 43. ADSP-BF531 Interface
AD5686/AD5684 TO SPORT INTERFACE
The Analog Devices ADSP-BF527 has one SPORT serial
port. Figure 44 shows how one SPORT interface can be used
to control the AD5686/AD5684.
The AD5686/AD5684 should have ample supply bypassing
of 10 µF in parallel with 0.1 µF on each supply, located as close
to the package as possible, ideally right up against the device.
The 10 µF capacitors are the tantalum bead type. The 0.1 µF
capacitor should have low effective series resistance (ESR)
and low effective series inductance (ESI), such as the common
ceramic types, which provide a low impedance path to ground
at high frequencies to handle transient currents due to internal
logic switching.
In systems where there are many devices on one board, it is
often useful to provide some heat sinking capability to allow
the power to dissipate easily.
The AD5686/AD5684 LFCSP models have an exposed pad
beneath the device. Connect this pad to the GND supply for the
part. For optimum performance, use special considerations to
design the motherboard and to mount the package. For
enhanced thermal, electrical, and board level performance,
solder the exposed pad on the bottom of the package to the
corresponding thermal land pad on the PCB. Design thermal
vias into the PCB land pad area to further improve heat
dissipation.
The GND plane on the device can be increased (as shown in
Figure 45) to provide a natural heat sinking effect.
AD5686/
AD5684
AD5686/
AD5684
ADSP-BF527
LDAC
RESET
GND
PLANE
BOARD
Figure 44. SPORT Interface
Figure 45. Pad Connection to Board
Rev. A | Page 24 of 28
10797-166
GPIO0
GPIO1
SYNC
SCLK
SDIN
10797-165
SPORT_TFS
SPORT_TSCK
SPORT_DTO
Data Sheet
AD5686/AD5684
CONTROLLER
In many process control applications, it is necessary to
provide an isolation barrier between the controller and
the unit being controlled to protect and isolate the controlling
circuitry from any hazardous common-mode voltages that may
occur. iCoupler® products from Analog Devices provide voltage
isolation in excess of 2.5 kV. The serial loading structure of the
AD5686/AD5684 makes the part ideal for isolated interfaces
because the number of interface lines is kept to a minimum.
Figure 46 shows a 4-channel isolated interface to the AD5686/
AD5684 using an ADuM1400. For more information, visit
http://www.analog.com/icouplers.
SERIAL
CLOCK IN
SERIAL
DATA OUT
ADuM14001
VOA
VIA
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
ENCODE
DECODE
VIB
VOB
VIC
SYNC OUT
LOAD DAC
OUT
1
VOC
VID
VOD
ADDITIONAL PINS OMITTED FOR CLARITY.
Figure 46. Isolated Interface
Rev. A | Page 25 of 28
TO
SCLK
TO
SDIN
TO
SYNC
TO
LDAC
10797-167
GALVANICALLY ISOLATED INTERFACE
AD5686/AD5684
Data Sheet
OUTLINE DIMENSIONS
PIN 1
INDICATOR
0.30
0.23
0.18
0.50
BSC
13
PIN 1
INDICATOR
16
1
12
1.75
1.60 SQ
1.45
EXPOSED
PAD
9
TOP VIEW
0.80
0.75
0.70
4
5
8
0.50
0.40
0.30
BOTTOM VIEW
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
SEATING
PLANE
0.25 MIN
08-16-2010-E
3.10
3.00 SQ
2.90
COMPLIANT TO JEDEC STANDARDS MO-220-WEED-6.
Figure 47. 16-Lead Lead Frame Chip Scale Package [LFCSP_WQ]
3 mm × 3 mm Body, Very Very Thin Quad
(CP-16-22)
Dimensions shown in millimeters
5.10
5.00
4.90
16
9
4.50
4.40
4.30
6.40
BSC
1
8
PIN 1
1.20
MAX
0.15
0.05
0.65
BSC
0.30
0.19
COPLANARITY
0.10
0.20
0.09
SEATING
PLANE
8°
0°
COMPLIANT TO JEDEC STANDARDS MO-153-AB
Figure 48. 16-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-16)
Dimensions shown in millimeters
Rev. A | Page 26 of 28
0.75
0.60
0.45
Data Sheet
AD5686/AD5684
ORDERING GUIDE
Model 1
AD5686ACPZ-RL7
AD5686BCPZ-RL7
AD5686ARUZ
AD5686ARUZ-RL7
AD5686BRUZ
AD5686BRUZ-RL7
AD5684BCPZ-RL7
AD5684ARUZ
AD5684ARUZ-RL7
AD5684BRUZ
AD5684BRUZ-RL7
EVAL-AD5686RSDZ
EVAL-AD5684RSDZ
1
Resolution
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
16 Bits
12 Bits
12 Bits
12 Bits
12 Bits
12 Bits
Temperature Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
±8 LSB INL
±2 LSB INL
±8 LSB INL
±8 LSB INL
±2 LSB INL
±2 LSB INL
±1 LSB INL
±2 LSB INL
±2 LSB INL
±1 LSB INL
±1 LSB INL
Z = RoHS Compliant Part.
Rev. A | Page 27 of 28
Package
Description
16-Lead LFCSP_WQ
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead LFCSP_WQ
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Lead TSSOP
16-Bit Evaluation Board
12-Bit Evaluation Board
Package
Option
CP-16-22
CP-16-22
RU-16
RU-16
RU-16
RU-16
CP-16-22
RU-16
RU-16
RU-16
RU-16
Branding
DJH
DJJ
DJP
AD5686/AD5684
Data Sheet
NOTES
©2012–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D10797-0-6/13(A)
Rev. A | Page 28 of 28
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