MP172 700 V Non-Isolated Off-Line Regulator Up to 120 mA Output Current The Future of Analog IC Technology DESCRIPTION FEATURES MP172 is a primary-side regulator that provides accurate constant voltage (CV) regulation without an opto-coupler. It supports buck, boost, buck-boost, and flyback topologies. It has an integrated 700 V MOSFET to simplify the structure and reduce costs. These features make it an ideal regulator for off-line, low-power applications, such as home appliances and standby power. MP172 is a green-mode-operation regulator. Both the peak current and the switching frequency decrease as the load decreases. This feature provides excellent efficiency at light load and improves the overall average efficiency. MP172 has various protection features including thermal shutdown (TSD), VCC undervoltage lockout (UVLO), overload protection (OLP), short-circuit protection (SCP), and openloop protection. MP172 is available in a small TSOT23-5 package and SOIC-8 package. Primary-Side CV Control, Supporting Buck, Boost, Buck-Boost, and Flyback Topologies Integrated 700 V MOSFET and Current Source < 30 mW No-Load Power Consumption Up to 3 W Output Power Maximum DCM Output Current Less than 80 mA Maximum CCM Output Current Less than 120 mA Low VCC Operating Current Frequency Foldback Limited Maximum Frequency Peak-Current Compression Internally Biased VCC TSD, UVLO, OLP, SCP, Open-Loop Protection APPLICATIONS Home Appliances, White Goods, and Consumer Electronics Industrial Controls Standby Power All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For MPS green status, please visit the MPS website under Quality Assurance. “MPS” and “The Future of Analog IC Technology” are registered trademarks of Monolithic Power Systems, Inc. TYPICAL APPLICATION DRAIN L D2 VCC C2 MP172 FB R1 C3 R2 SOURCE Input SOURCE VOUT D1 N MP172 Rev. 1.0 9/30/2015 L1 C1 C4 GND www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 1 MP172– NON-ISOLATED OFF-LINE REGULATOR ORDERING INFORMATION Part Number Package Top Marking MP172GJ* MP172GS** TSOT23-5 SOIC-8 See Below See Below * For Tape & Reel, add suffix –Z (e.g. MP172GJ–Z). ** For Tape & Reel, add suffix –Z (e.g. MP172GS–Z). TOP MARKING (TSOT23-5) APK: product code of MP172GJ; Y: year code; TOP MARKING (SOIC-8) MP172: part number; LLLLLLLL: lot number; MPS: MPS prefix: Y: year code; WW: week code: PACKAGE REFERENCE TOP VIEW VCC 1 FB 2 SOURCE 3 5 DRAIN 8 NC VCC 1 FB 2 4 TSOT23-5 MP172 Rev. 1.0 9/30/2015 TOP VIEW SOURCE 7 DRAIN SOURCE 3 6 NC SOURCE 4 5 NC SOIC-8 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 2 MP172– NON-ISOLATED OFF-LINE REGULATOR ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance DRAIN to SOURCE (TJ=+25°C) .-0.3 V to 700 V All other pins ................................-0.3 V to 6.5 V (2) Continuous power dissipation ..... (TA = +25°C) TSOT23-5 .................................................... 1 W SOIC-8 ......................................................... 1 W Junction temperature ................................150°C Lead temperature .....................................260°C Storage temperature ................ -60°C to +150°C TSOT23-5.............................. 100 ..... 55... °C/W SOIC-8.................................... 96 ...... 45... °C/W Recommended Operating Conditions (3) Operating junction temp (TJ). ... -40°C to +125°C Operating VCC range ...................5.5 V to 5.7 V MP172 Rev. 1.0 9/30/2015 (4) θJA θJC NOTES: 1) Exceeding these ratings may damage the device. 2) The maximum allowable power dissipation is a function of the maximum junction temperature TJ(MAX), the junction-toambient thermal resistance θJA, and the ambient temperature TA. The maximum allowance continuous power dissipation at any ambient temperature is calculated by PD(MAX)=(TJ(MAX)TA)/θJA. Exceeding the maximum allowance power dissipation will produce an excessive die temperature, causing the regulator to go into thermal shutdown. Internal thermal shutdown circuit protects the device from permanent damage. 3) The device is not guaranteed to function outside of its operating conditions. 4) Measured on JESD51-7, 4-layer PCB. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 3 MP172– NON-ISOLATED OFF-LINE REGULATOR ELECTRICAL CHARACTERISTICS VCC = 5.5 V, TJ = -40°C~125°C, min and max are guaranteed by characterization, typical is tested under 25°C, unless otherwise specified. Parameter Symbol Condition Start-up Current Source and Internal MOSFET (DRAIN) Internal regulator supply current Iregulator VCC = 4 V; VDrain = 100 V VCC = 5.8 V; VDrain = 400 DRAIN leakage current ILeak V Breakdown voltage On resistance Supply Voltage Management (VCC) VCC level (increasing) where the internal regulator stops VCC level (decreasing) where the internal regulator turns on VCC regulator on and off hysteresis VCC level (decreasing) where the IC stops VCC level (decreasing) where the protection phase ends Internal IC consumption V(BR)DSS TJ = 25°C Ron TJ = 25°C Typ Max Units 2.2 4.1 6 mA 10 17 μA 700 SCP threshold Leading-edge blanking for SCP 20 Ω 5.7 6 V VCCON 5.1 5.5 5.8 V 130 250 VCCstop 3 3.4 3.6 V VCCpro 2 2.5 2.8 V 720 μA 16 200 24 µA μA 210 232 mA ICC ICCLATCH ILimit ISCP (1) 16 5.4 fs = 36 kHz, D = 64% VCC = 5.3 V TJ = 25°C 188 τLEB1 Leading-edge blanking V VCCOFF ICC Internal IC consumption (no switching) Internal IC consumption, latch-off phase Internal Current Sense Peak current limit Min mV 350 TJ = 25°C 330 τLEB2 400 ns 510 180 mA ns Feedback Input (FB) Minimum off time Maximum on time Primary MOSFET feedback turn-on threshold OLP feedback trigger threshold τminoff τmanon 7.5 10 12.5 μs 13 18 23 μs VFB 2.45 2.55 2.65 V VFB_OLP 1.64 1.74 1.84 V OLP delay time τOLP Open-loop detection Thermal Shutdown VOLD Thermal shutdown threshold (1) Thermal shutdown recovery hysteresis (1) fs = 36 kHz 175 0.4 0.5 ms 0.6 V 150 °C 30 °C NOTE: 1) This parameter is guaranteed by design. MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 4 MP172– NON-ISOLATED OFF-LINE REGULATOR TYPICAL CHARACTERISTICS 5.73 2.56 5.72 2.55 5.71 2.54 5.70 2.53 710 -40 -25-10 5 20 35 50 65 80 95 110125 5.69 -40 -25-10 5 20 35 50 65 80 95 110125 2.52 -40 -25-10 5 20 35 50 65 80 95 110125 5.50 2.60 1.8 2.55 1.6 810 800 790 780 770 760 750 740 730 720 5.49 5.48 2.50 5.47 2.45 5.46 5.45 2.40 5.44 5.43 5.42 -40 -25-10 5 20 35 50 65 80 95 110125 1.0 0.8 0.6 2.30 -40 -25-10 5 20 35 50 65 80 95 110125 0.4 -40 -25-10 5 20 35 50 65 80 95 110125 405 215.0 1.2 2.35 410 220.0 1.4 10.0 9.9 400 210.0 395 390 205.0 385 200.0 9.8 9.7 9.6 380 195.0 375 190.0 -40 -25-10 5 20 35 50 65 80 95 110125 MP172 Rev. 1.0 9/30/2015 370 -40 -25-10 5 20 35 50 65 80 95 110125 9.5 9.4 -40 -25-10 5 20 35 50 65 80 95 110125 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 5 MP172– NON-ISOLATED OFF-LINE REGULATOR TYPICAL PERFORMANCE CHARACTERISTICS VIN = 230 VAC, VOUT = 5 V, IOUT = 120 mA, L = 1 mH, COUT = 47 μF, TA = +25°C, unless otherwise noted. VDS 100V/div. VDS 100V/div. VDS 100V/div. IL 100mA/div. IL 100mA/div. IL 100mA/div. VDS 100V/div. VDS 100V/div. VDS 100V/div. IL 200mA/div. IL 200mA/div. VDS 100V/div. IL 100mA/div. MP172 Rev. 1.0 9/30/2015 VRIPPLE 50mV/div. IL 100mA/div. VRIPPLE 100mV/div. IOUT 100mA/div. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 6 MP172– NON-ISOLATED OFF-LINE REGULATOR PIN FUNCTIONS Pin # TSOT23-5 1 2 3,4 5 MP172 Rev. 1.0 9/30/2015 Pin # SOIC8 1 2 3,4 7 5,6,8 Name VCC FB SOURCE DRAIN NC Description Control circuit power supply. Regulator feedback. Internal power MOSFET source and ground reference for VCC and FB. Internal power MOSFET drain and high-voltage current source input. No connection. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 7 MP172– NON-ISOLATED OFF-LINE REGULATOR FUNCTIONAL BLOCK DIAGRAM VCC DRAIN Start-Up Unit Power Management Driving Signal Management Feedback Control Peak Current Limitation FB Protection Unit SOURCE Figure 1—Functional block diagram MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 8 MP172– NON-ISOLATED OFF-LINE REGULATOR OPERATION MP172 is a green-mode-operation regulator: The peak current and the switching frequency both decrease with a decreasing load. As a result, it offers excellent light-load efficiency and improves overall average efficiency. Also, the regulator incorporates multiple features and operates with a minimum number of external components. The MP172 acts as a fully integrated regulator when used in buck topology (see Typical Application on page 1). Start-Up and Under-Voltage Lockout The internal high-voltage regulator self-supplies the IC from DRAIN. When VCC voltage reaches VCCOFF, the IC starts switching, and the internal high-voltage regulator turns off. The internal highvoltage regulator turns on to charge the external VCC capacitor when the VCC voltage falls below VCCON. A small capacitor (in the low μF range) maintains the VCC voltage and thus lowers the capacitor cost. The IC stops switching when the VCC voltage drops blow VCCstop. Under fault conditions—such as OLP, SCP, and TSD—the IC stops switching and an internal current source discharges the VCC capacitor. The internal high-voltage regulator will not charge the VCC capacitor until the VCC voltage drops below VCCpro. The re-start time can be estimated using Equation (1). VCC VCCpro VCCOFF VCCPRO restart C VCC (1) I I CCLATCH regulator 18 us 10 us 128 Switching cycle 128 Switching cycle Figure 2— min off at start-up Constant Voltage (CV) Operation The MP172 regulates the output voltage by monitoring the sampling capacitor. At the beginning of each cycle, the integrated MOSFET turns on while the feedback voltage drops below the 2.55 V reference voltage, which indicates insufficient output voltage. The peak current limitation determines the on period. After the on period elapses, the integrated MOSFET turns off. The sampling capacitor (C3) voltage is charged to the output voltage when the freewheeling diode (D1) turns on. This way, the sampling capacitor (C3) samples and holds the output voltage for output regulation. The sampling capacitor (C3) voltage decreases when the L1 inductor current falls below the output current. When the feedback voltage falls below the 2.55 V reference voltage, a new switching cycle begins. Figure 3 shows this operation in continuous conduction mode (CCM). MOSFET Diode IL Ipeak Io Vo Soft Start (SS) The IC stops operation when the VCC voltage drops below VCCstop; the IC begins operation when VCC charges to VCCOFF. Every time the chip starts operation, there is a soft-start period. The soft start prevents the inductor current from overshooting by limiting the minimum off time. MP172 adopts a 2 phase minimum off time limit soft start. Each soft-start phase retains 128 switching cycles. During the soft start, the off time limit gradually shortens from 48 μs to 18 μs and finally reaches the normal operation off time limit (see Figure 2). MP172 Rev. 1.0 9/30/2015 48us Driver V FB 2.55V Figure 3— VFB vs. VO Equation (2) determines the output voltage: Vo 2.55V R1 R2 R2 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. (2) 9 MP172– NON-ISOLATED OFF-LINE REGULATOR Frequency Foldback and Peak Current Compression The MP172 remains highly efficient at light-load conditions by reducing the switching frequency automatically. Under light-load or no-load conditions, the output voltage drops very slowly, which increases the MOSFET off time. Thus, the frequency decreases along with the load. The switching frequency is determined with Equation (3) and Equation (4): fs (Vin Vo ) Vo , for CCM 2L(Ipeak Io ) Vin (3) fs 2(Vin VO ) Io Vo , for DCM LI2peak Vin (4) As the peak current limit decreases from 210 mA, the off time increases. In standby mode, the frequency and the peak current are both minimized, allowing for a smaller dummy load. As a result, the peak current compression helps reduce no-load consumption. The peak current limit can be estimated from Equation (5) where τoff is the off time of the power module: IPeak 210mA (0.8mA / s) ( off 10s) (5) FB Comparator + EA + + Vramp + Vramp V ref 2.55V Ipeak Figure 4—EA and ramp compensation MP172 has an internal error amplifier (EA) compensation loop. It samples the feedback voltage 6 µs after the MOSFET turns off and regulates the output based on the 2.55 V reference voltage. MP172 Rev. 1.0 9/30/2015 The maximum output power of the MP172 is limited by the maximum switching frequency and the peak current limit. If the load current is too large, the output voltage drops, causing the FB voltage to drop. When the FB voltage drops below VFB_OLP, it is considered an error flag, and the timer starts. If the timer reaches 170 ms (fS = 36 kHz), OLP occurs. This timer duration avoids triggering OLP when the power supply starts up or the load transitions. The power supply should start up in less than 170 ms (fS = 36 kHz). The OLP delay time is calculated using Equation (6): Delay 170ms 36kHz fs (6) Thermal Shutdown (TSD) M + - Over-Load Protection (OLP) Short-Circuit Protection (SCP) The MP172 monitors the peak current and shuts down when the peak current rises above the SCP threshold through short-circuit protection. The power supply resumes operation with the removal of the fault. EA Compensation VFB Ramp Compensation An internal ramp compensation circuit improves the load regulation. As shown in Figure 4, a voltage sinking source is added to pull down the reference voltage of the feedback comparator. The ramp compensation is relative to the MOSFET off time, and increases exponentially as the off time increases. The compensation is about 1mV/µs under min off time switching condition. To prevent thermal induced damage, the MP172 stops switching when the junction temperature exceeds 150°C. During thermal shutdown (TSD), the VCC capacitor is discharged to VCCpro, and the internal high-voltage regulator re-charges. The MP172 recovers when the junction temperature drops below 120°C. Open-Loop Detection If VFB is less than 0.5 V, the IC stops switching, and a re-start cycle begins. During a soft start, the open-loop detection is blanked. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 10 MP172– NON-ISOLATED OFF-LINE REGULATOR Leading-Edge Blanking An internal leading-edge blanking (LEB) unit avoids premature switching pulse termination due to a turn-on spike. A turn-on spike is caused by parasitic capacitance and reverse recovery of the freewheeling diode. During the blanking time, the current comparator is disabled and cannot turn off the external MOSFET. Figure 5 shows the leading-edge blanking. IDS 350ns ILIMIT t Figure 5—Leading-edge blanking MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 11 MP172– NON-ISOLATED OFF-LINE REGULATOR APPLICATION INFORMATION Table 1—Common topologies using MP172 Topology Circuit Schematic DRAIN 5 High-side buck SOURCE VCC 1 MP172 FB 2 4 Features SOURCE 3 1. 2. 3. 4. No isolation Positive output Low cost Direct feedback 1. 2. 3. 4. No isolation Negative output Low cost Direct feedback 1. 2. 3. 4. No isolation Positive output Low cost Direct feedback 1. 2. 3. 4. Isolation Positive output Low cost Indirect feedback Vin Vo DRAIN 1 5 MP172 High-side buck-boost SOURCE 2 3 4 VCC FB SOURCE Vin Vo DRAIN Boost 5 1 MP172 Vin SOURCE 2 3 4 VCC FB Vo SOURCE T * Vin * Flyback DRAIN 1 5 MP172 SOURCE MP172 Rev. 1.0 9/30/2015 4 2 3 VCC FB SOURCE * www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 12 MP172– NON-ISOLATED OFF-LINE REGULATOR Topology Options The MP172 can be used in common topologies such as buck, boost, buck-boost, and flyback (see Table 1). Component selection below is based on the typical application of MP173 (see it on page 1). Component Selection Input Capacitor The input capacitor supplies the DC input voltage for the converter. Figure 6 shows the typical DC bus voltage waveform of a half-wave rectifier and a full-wave rectifier. Vin VDC(max) DC input voltage VDC(min) AC input voltage t Vin VDC(max) VDC( min) maximum power using Equation (7) and Equation (8): V (7) Po max Vo (Ipeak o min off ) , for CCM 2L 1 2 1 , for DCM (8) Po max LIpeak 2 min off For mass production, tolerance on the parameters (such as peak current limitation and the minimum off time) should be taken into consideration. Freewheeling Diode Select a diode with a maximum reverse-voltage rating greater than the maximum input voltage and a current rating determined by the output current. The reverse recovery of the freewheeling diode affects the efficiency and circuit operation during a CCM condition, so use an ultra-fast diode such as the EGC10JH. Output Capacitor DC input voltage The output capacitor is required to maintain the DC output voltage. Estimate the output voltage ripple using Equation (9) and Equation (10): AC input voltage t VCCM _ ripple Figure 6—Input voltage waveform Typically, the use of a half-wave rectifier requires an input capacitor rated at 3 µF/W for the universal input condition. When using a full-wave rectifier, an input capacitor is chosen between 1.5~2 µF/W for the universal input condition. A half-wave rectifier is recommended for a < 2 W output application, otherwise use a full-wave rectifier. Under very low input voltage, the inductor current ramps up slowly; it may not reach the current limit during τmanon, so the MOSFET on time should be less than the minimum value of τmanon. Inductor The MP172 has a minimum off-time limit that determines the maximum power output. A power inductor with a larger inductance increases the maximum power. Using a very small inductor may cause failure at full load. Estimate the MP172 Rev. 1.0 9/30/2015 VDCM _ ripple i i RESR , for CCM 8fsCo I o fsCo (9) 2 I I pk o Ipk RESR , for DCM (10) I pk It is recommended to use ceramic, tantalum, or low ESR electrolytic capacitors to reduce the output voltage ripple. Feedback Resistors The resistor divider determines the output voltage. Choose appropriate R1 and R2 values to maintain VFB at 2.55 V. An excessively large value for R2 should be avoided. Sampling Capacitor The sampling capacitor (C3) samples and holds the output voltage for feedback. With R1 and R2 fixed, a small sampling capacitor result in poor regulation at light loads, and large sampling capacitor affect the circuit operation. Roughly estimate an optimal capacitor value using Equation (11): www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 13 MP172– NON-ISOLATED OFF-LINE REGULATOR C Vo C 1 Vo o CFB o 2 R1 R2 Io R1 R2 Io (11) Dummy Load A dummy load is required to maintain the load regulation. This ensures there is sufficient inductor energy to charge the sample and hold capacitor to detect the output voltage. Normally a 3 mA dummy load is needed and can be adjusted according to the regulated voltage. There is a compromise between small, no-load consumption and good, no-load regulation, especially for applications that require 30 mW noload consumption. Use a Zener to reduce noload consumption if no-load regulation is not a concern. Auxiliary VCC Supply R3 D3 C2 SOURCE C3 L1 VOUT Figure 7—Auxiliary VCC supply circuit For applications with VO above 7 V, the MP172 achieves the 30 mW no-load power requirement. In order to do this, the chip requires an external VCC supply to reduce overall power consumption (see Figure 7). This auxiliary VCC supply is derived from the resistor connected between C2 and C3. C3 should be set larger than the value recommended above. D3 is used in case VCC interferes with FB. R3 is determined using Equation (12): R3 Vo VFW 5.8V IS (12) Where IS is the VCC consumption under a noload condition, and VFW is the forward voltage drop of D3. Because IS varies in different applications, R3 should be adjusted to meet the application’s specific IS. In a particular configuration, IS is measured at about 200 µA. MP172 Rev. 1.0 9/30/2015 FR1 L1 C1 C2 Table 2—Recommended capacitance Surge 500 V 1000 V 2000 V Voltage 1 μF 2.2 μF 3.3 μF C1 1 μF 2.2 μF 3.3 μF C2 R1 R2 SOURCE L Figure 8—Half-wave rectifier D2 FB An appropriate input capacitor value should be chosen to obtain good surge performance. Figure 8 shows the half-wave rectifier. Table 2 shows the capacitance required under normal conditions for different surge voltages. FR1 is a 20 Ω/2 W fused resistor, and L1 is 1 mH for this recommendation. N VCC MP172 Surge Performance PCB Layout Guidelines Efficient PCB layout is critical for reliable operation, good EMI, and thermal performance. Please follow the guidelines below to optimize performance. 1) Minimize the loop area formed by the input capacitor, IC, freewheeling diode, inductor, and output capacitor. 2) Place the power inductor far away from the input filter while keeping the loop area to the inductor at a minimum (see example below). 3) Place a capacitor valued at several hundred pF between FB and SOURCE as close to the IC as possible. 4) Connect the exposed pads or large copper area with DRAIN to improve thermal performance. www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 14 MP172– NON-ISOLATED OFF-LINE REGULATOR Top layer Bottom layer Design Example Table 3 shows a design example for the following application guideline specifications: Table 3—Design example 85 VAC to 265 VAC VIN 5V VOUT 120 mA IOUT The detailed application schematic is shown in Figure 9. The typical performance and circuit waveforms have been shown in the “Typical Performance Characteristics” section. For additional device applications, please refer to the related evaluation board datasheets. MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 15 MP172– NON-ISOLATED OFF-LINE REGULATOR TYPICAL APPLICATION CIRCUITS Figure 9 shows a typical application example of a 5 V, 120 mA non-isolated power supply using the MP172. D1 SRGC10JH R1 41.2 K C1 22 nF 8 RF1 L 39 85 VAC~265VAC NC VCC 1 L1 D2 SRGC10JH U1 7 1 mH 6 C3 C4 2.2 µF/400 V 2.2 µF/400 V 5 DRAIN FB 2 NC SOURC E 3 NC SOURC E 4 C2 2.2 µF C7 470 pF R2 39.2 K 5 V/120 mA L2 1 mH Vout MP172GS D3 STTH1R06 600 V/1 A C5 C6 1 µF 47 µF R3 1.2 K D4 N SRJC10JH GND GND Figure 9—Typical application at 5 V, 120 mA MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 16 MP172– NON-ISOLATED OFF-LINE REGULATOR FLOW CHART Power On Vcc Decrease to VCCPRO Internal High Voltage Regulator On Shut Down Internal High Voltage Regulator Y Y N VCC>VCCOFF N Soft Start Shuts Down Internal High Voltage Regulator VCC>VCCSTOP Stop Operation Y Y Fault Logic N High? Monitor VCC Y VCC>VCCOFF N VCC<VCCON N TSD, SCP and Open-Loop Monitor Y Internal High Voltage Regulator On Monitor FB Voltage Open-Loop Logic High N < VFB Y Turn On the MOSFET < VFB_OLP N N < VOLD Y Y Counts to 6144 Switching Cycle? N Y OLP Fault Logic High Y Count Switching Cycle OLP Fault Logic High? N Reset Counter UVLO, SCP, OLP, OTP and Open-Loop Protections are Auto Restart Figure 10—Control flow chart MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 17 MP172– NON-ISOLATED OFF-LINE REGULATOR Normal Operation Start Up 16µA Discharge Current Unplug from Main Input VCCOFF VCC VCCON VCCSTOP VCCPRO Start-Up Blanking Time Driver Pluses Driver Internal Regulator Supply Current On and Off Fault Flag Open-Loop Fault Over-Load Over-Load Fault Fault Counter<6144 Counter=6144 Short Circuit Fault Thermal Shutdown Fault Figure 11—Signal evolution in the presence of a fault MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 18 MP172– NON-ISOLATED OFF-LINE REGULATOR PACKAGE INFORMATION TSOT23-5 0.95 BSC 0.60 TYP 2.80 3.00 5 4 1.20 TYP 1.50 1.70 1 2.60 3.00 2.60 TYP 3 TOP VIEW RECOMMENDED LAND PATTERN 0.90 1.30 1.45 MAX 0.09 0.20 SEATING PLANE 0.30 0.50 0.95 BSC 0.00 0.15 SEE DETAIL "A" FRONT VIEW SIDE VIEW NOTE: GAUGE PLANE 0.25 BSC 0o-8o 0.30 0.55 DETAIL “A” MP172 Rev. 1.0 9/30/2015 1) ALL DIMENSIONS ARE IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR . 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION . 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.10 MILLIMETERS MAX. 5) DRAWING CONFORMS TO JEDEC MO -178, VARIATION AA . 6) DRAWING IS NOT TO SCALE . www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 19 MP172– NON-ISOLATED OFF-LINE REGULATOR PACKAGE INFORMATION SOIC-8 0.189(4.80) 0.197(5.00) 8 0.050(1.27) 0.024(0.61) 5 0.063(1.60) 0.150(3.80) 0.157(4.00) PIN 1 ID 1 0.228(5.80) 0.244(6.20) 0.213(5.40) 4 TOP VIEW RECOMMENDED LAND PATTERN 0.053(1.35) 0.069(1.75) SEATING PLANE 0.004(0.10) 0.010(0.25) 0.013(0.33) 0.020(0.51) 0.0075(0.19) 0.0098(0.25) SEE DETAIL "A" 0.050(1.27) BSC SIDE VIEW FRONT VIEW 0.010(0.25) x 45o 0.020(0.50) GAUGE PLANE 0.010(0.25) BSC 0o-8o 0.016(0.41) 0.050(1.27) DETAIL "A" NOTE: 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH , PROTRUSIONS OR GATE BURRS. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSIONS. 4) LEAD COPLANARITY(BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) DRAWING CONFORMS TO JEDEC MS-012, VARIATION AA. 6) DRAWING IS NOT TO SCALE. NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP172 Rev. 1.0 9/30/2015 www.MonolithicPower.com MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2015 MPS. All Rights Reserved. 20