March, 2004 Application Note 9034 Power MOSFET Avalanche Guideline Sungmo Young, Application Engineer Introduction The Power MOSFET is a very popular switching device used in switching power supplies and DC-DC converters. Their operation frequency is being continuously increased to reduce size and increase power density. This causes high di/dt, intensifies the negative effect from parasitic inductances, and results in high voltage spike between the Power MOSFET drain and source during device turn off. The spike is worst at power on due to empty bulk capacitors and small inductance because the transformer primary side inductance almost reaches the level of leakage inductance. Fortunately, the Power MOSFET is equipped to withstand a certain level of stress, unnecessitating expensive protection circuits. This note presents an effective way to determine the applicability of a Power MOSFET in an application. The designers can balance between cost and reliability. 1. A Rating System: Single Pulse UIS SOA The Fairchild Power Discrete Group has introduced a rating system that specifies the Power MOSFET capability for single pulse Unclamped Inductive Switching (UIS).[1] This system enables easy determination and/or estimation of device feasibility in any application with simple parameters : the peak current through the Power MOSFET during avalanche (IAS), the junction temperature at the start of the UIS pulse (Tj), and the time the Power MOSFET remains in avalanche (tAV). By plotting IAS and tAV on a graph the user can check the UIS capability of the device. The application specific part of Fairchild UltraFET and PowerTrench provide such rating chart, and a part of QFETTM datasheets will soon be updated. IAS VDS tAV Figure 1. UIS Waveforms ©2004 Fairchild Semiconductor Corporation 1 Rev. A, March 2004 2. Over-Voltage Conditions The over-voltage conditions in actual applications can be classified into two different groups. One is when the drain-source voltage of Power MOSFET exceeds the specified absolute maximum rating but is still short of the breakdown voltage of the device. This is not an avalanche situation and the device feasibility can be determined through junction temperature analysis. Another is when the device breaks down and goes into avalanche mode. The Rating System is a great tool for avalanche mode analysis. 3. Avalanche Mode Analysis When the Power MOSFET avalanches, the drain-source voltage is clamped to its effective breakdown voltage and the current is commutated through a parasitic antiparallel diode. Figure 2 shows typical avalanche waveforms in switching power supplies. The drain-source voltage is over 1kV and a commutating current is observed. Figure 2. Device Breakdown, 800V Rated MOSFET The UIS Rating System is very useful in dealing with avalanche situations. There are three areas in the UIS SOA graph as indicated in Figure 3 : (1) above and right of the 25°C line, (2) below and left of the maximum junction temperature line, (3) in between the two lines. (1) and (2) are easy to determine: the device is within the UIS rating ((2)), or beyond the rating ((1)). But the junction temperature of the Power MOSFET at the start of the UIS pulse is required to determine (3). The junction temperature analysis methods will be discussed later in detail. IAS , AVALANCHE CURRENT (A) This UIS Rating System can also be applied to repetitive pulses through superposition technique. Each UIS pulse is evaluated separately just as in single pulse. Usually, the last pulse in a series of power pulses occurs at the highest junction temperature and is therefore the worst stress. If the Power MOSFET is within the specified UIS rating for the last pulse, it is certainly within the UIS ratings for previous pulses which occurred at a lower junction temperature.[2] (1) 100 STARTING T (3) (2) o J = 25 C 10 STARTING T 1 0.01 0.1 o J = 150 C 1 10 100 tAV , TIME IN AVALANCHE (ms) Figure 3. UIS Capability, FDP050AN06A0 ©2004 Fairchild Semiconductor Corporation 2 Rev. A, March 2004 4. Junction Temperature Analysis Generally, breakdown of the Power MOSFET seldom occurs even if the drain-source voltage exceeds the absolute maximum rating. The BVDSS of the Power MOSFET has a positive temperature coefficient as shown in Figure 4. It reaches about 990V at 120°C in this example. Therefore, a greater voltage is required to cause device breakdown at higher temperature. In many cases, the ambient temperature during the Power MOSFET operation is over 25°C and the power loss causes the junction temperature of the Power MOSFET to rise above the ambient temperature. BVDSS, (Normalized) Drain-Source Breakdown Voltage 1.2 1.1 1.0 ※ Notes : 1. VGS = 0 V 2. ID = 250 µ A 0.9 0.8 -100 -50 0 50 100 150 200 o TJ, Junction Temperature [ C] Figure 4. Normalized BVDSS vs Tj, FQA11N90C Also, note that the BVDSS in Figure 4 is measured at 250µA of the drain current. In a real breakdown, the drain current reaches a much higher level and the breakdown voltage is even higher than the above value. Figure 5. Waveforms from Switching Power Supply, 600V rated MOSFET ©2004 Fairchild Semiconductor Corporation 3 Rev. A, March 2004 For practical purposes, an actual breakdown voltage in applications is chosen as 1.3 times the rated low current breakdown voltage[1]. Figure 5 is an example of this non-breakdown but over the absolute maximum rating. The peak drain-source voltage is 668V but there is no breakdown yet. Even though the abnormal voltage spike did not cause a device breakdown, the junction temperature of the Power MOSFET should be kept below the specified maximum junction temperature to ensure reliability. The steady state junction temperature can be expressed as (1) T J = P D R ΘJC + T C where TJ: junction temperature TC: case temperature PD: power dissipated in the junction RΘJC: steady state thermal resistance from junction to case In many applications, however, the power dissipated in the Power MOSFET is pulsed rather than DC. When a power pulse is applied to the device, the peak junction temperature varies depending on peak power and pulse width. Thermal resistance at a given time is called transient thermal resistance and is expressed as Z ΘJC ( t ) = r ( t ) × R ΘJC (2) Zθ JC(t), Thermal Response where r(t) is a time dependent factor regarding thermal capacity. For very short pulses, r(t) is quite small, but for long pulses it is nearly 1 and transient thermal resistance approaches the steady state thermal resistance. Most Fairchild Power MOSFET datasheets have a graph similar to that of Figure 6. D=0.5 -1 ※ Notes : 1. Zθ JC(t) = 0.42 ℃/W Max. 2. Duty Factor, D=t1/t2 3. TJM - TC = PDM * Zθ JC(t) 0.2 10 0.1 0.05 0.02 0.01 -2 10 single pulse -5 10 -4 -3 10 -2 10 10 -1 10 0 10 1 10 t1, Square Wave Pulse Duration [sec] Figure 6. Transient Thermal Response, FQA11N90C From this curve, the junction temperature can be obtained as follows: T J = P D Z ΘJC ( t ) + T C ©2004 Fairchild Semiconductor Corporation (3) 4 Rev. A, March 2004 For example, the calculation of the temperature rise resulting from single 2kW power pulse applied to FQA11N90C during 1µs can be expressed as follows: T = P D Z ΘJC ( 1µs ) = 2000 × 1.49 × 10 –3 ≈ 3°C The applied power is substantial but the temperature rise is only 3 degrees. Note that a power dissipation rating specified in the datasheet is a steady state power rating, and in a relatively short time the Power MOSFET can handle even greater power pulse. In the above example, however, transient thermal resistance of 1µs is not available in Figure 6. In cases where the given time is too short and out of the graph range, the single pulse transient thermal resistance is known to be proportionate to the square root of time. So ZΘJC(1µs) becomes 1µs Z ΘJC ( 1µs ) = Z ΘJC ( 10µs ) × -------------10µs = 4.72 × 10 –3 × 0.1 = 1.49 × 10 –3 where ZΘJC(10µs): taken from Figure 6 The above thermal response is based on a rectangular power pulse. It is possible to obtain a response for arbitrary shapes. However, since the mathematical solution would be very complex, it would be easiest to convert it to an equivalent rectangular pulse. Some examples for triangular and sine wave power pulses are shown in Figure 7. P P 0.7P 0.7P 0.71t 0.91t t t Figure 7. Conversion of Power Pulses The equation (3) can also be applied to applications that have repetitive pulses. The transient thermal resistance for repetitive pulses can be approximated as follows[3] t t Z ΘJC ( t ) = ----1- + 1 – ----1- r ( t 1 + t 2 ) + r ( t 1 ) – r ( t 2 ) R ΘJC t2 t 2 t1 t = ----- R ΘJC + 1 – ----1- Z ΘJC ( t 1 + t 2 ) + Z ΘJC ( t 1 ) – Z ΘJC ( t 2 ) t2 t 2 (4) where t1: pulse width of the power pulse t2: period of the power pulse ©2004 Fairchild Semiconductor Corporation 5 Rev. A, March 2004 Assume a situation where the drain-source voltage of a Power MOSFET applied to a switching power supply exceeds its maximum rating specified in the datasheet during delay time to protection activation while conducting short circuit test. The specific conditions are as follows: FQA9N90C switching device, 100ns tAV, 9.2µs period, and 20ms delay time. In this case, the transient thermal resistance becomes Z ΘJC ( t ) = 0.01 × Z ΘJC ( 20ms ) + ( 1 – 0.01 ) × Z ΘJC ( 9.3µs ) + Z ΘJC ( 100ns ) – Z ΘJC ( 9.2µs ) = 0.00274 If a 5kW power loss is assumed during avalanche, the resulting junction temperature rise will be ∆T = 5kW × 0.00274°C ⁄ W = 13.7°C This is an additional junction temperature rise caused by avalanche. Therefore, the system designer should first calculate the junction temperature of a normal operation, and then add the above value to obtain the transient junction temperature during avalanche. This temperature should be kept below the maximum allowable junction temperature with some safety margin according to the designer’s choice. 5. Conclusions The system designers are frequently forced to determine the applicability of a Power MOSFET to their application. This can be done by using the avalanche mode analysis and/or junction temperature analysis which are very practical. References [1] “Single Pulse Unclamped Inductive Switching: A Rating System”, Fairchild Application Note AN-7514 [2] “A Combined Single Pulse and Repetitive UIS Rating System”, Fairchild Application Note AN-7515 [3] Rudy Severns, 1984, “Safe Operating Area and Thermal Design for MOSPOWER Transistors”, MOSPOWER Applications Handbook, Siliconix ©2004 Fairchild Semiconductor Corporation 6 Rev. A, March 2004 TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx™ FACT Quiet Series™ ActiveArray™ FAST Bottomless™ FASTr™ CoolFET™ FPS™ CROSSVOLT™ FRFET™ DOME™ GlobalOptoisolator™ EcoSPARK™ GTO™ E2CMOSTM HiSeC™ EnSignaTM I2C™ FACT™ ImpliedDisconnect™ Across the board. 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