Sample & Buy Product Folder Support & Community Tools & Software Technical Documents LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 LMV951 1-V, 2.7-MHz, Zero Crossover Rail-to-Rail Input and Output Amplifier With Shutdown 1 Features 3 Description • • • • • • • • The LMV951 amplifier is capable of operating at supply voltages from 0.9 V to 3 V with specified specs at 1-V and 1.8-V single supply. 1 • • (Typical 1-V Supply, Unless Otherwise Noted) Ensured 1-V, 380-µA Single-Supply Operation Shutdown to 50-nA Supply Current Wide 2.7-MHz Bandwidth Rail-to-Rail Input With Zero Crossover No Input IBIAS Current Reversal Over VCM Range 1000-pF Output Drive Capability High-Output Drive Capability – Sink Current: 35 mA – Source Current: 45 mA Rail-to-Rail Buffered Output – At 600-Ω Load, 32 mV from Either Rail – At 2-kΩ Load, 12 mV from Either Rail Temperature Range −40°C to 125°C Contrary to a conventional rail-to-rail output amplifier, the LMV951 has a buffered output stage, providing an open-loop gain which is relatively unaffected by resistive output loading. At 1-V supply voltage, the LMV951 is able to source and sink in excess of 35 mA and offers a gain bandwidth product of 2.7 MHz. In shutdown mode, the LMV951 consumes less than 50 nA of supply current. Device Information(1) 2 Applications • • • The input common-mode range extends to both power supply rails without the offset transition zone and input bias current reversal inherent to most railto-rail input amplifiers. PART NUMBER Battery Operated Systems Battery Monitoring Supply Current Monitoring PACKAGE LMV951 BODY SIZE (NOM) SOT (6) 2.90 mm × 1.60 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. space space Simplified Schematic Offset Voltage Change vs Common Mode + ABOVE V GENERATOR 1.4 5 1.2 SHUTDOWN + INTERNAL GAIN STAGE IN- IN+ 125°C 6 1 OUTPUT 4 VOS ( mV) V 1 25°C 0.8 3 2 V - -40°C 0.6 + - BELOW V GENERATOR V = 3V 0.4 0 0.5 1 1.5 2 2.5 3 VCM (V) 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 3 6.1 6.2 6.3 6.4 6.5 6.6 6.7 3 3 4 4 4 5 7 Absolute Maximum Ratings ...................................... ESD Ratings.............................................................. Recommended Operating Conditions....................... Thermal Information .................................................. Electrical Characteristics: 1 V ................................... Electrical Characteristics: 1.8 V ................................ Typical Characteristics .............................................. Detailed Description ............................................ 15 7.1 Overview ................................................................. 15 7.2 Functional Block Diagram ....................................... 15 7.3 Feature Description................................................. 15 7.4 Device Functional Modes........................................ 15 8 Application and Implementation ........................ 18 8.1 Application Information............................................ 18 8.2 Typical Applications ................................................ 18 9 Power Supply Recommendations...................... 21 10 Layout................................................................... 21 10.1 Layout Guidelines ................................................. 21 10.2 Layout Example .................................................... 21 11 Device and Documentation Support ................. 22 11.1 11.2 11.3 11.4 11.5 11.6 Device Support .................................................... Documentation Support ....................................... Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 22 22 22 22 22 22 12 Mechanical, Packaging, and Orderable Information ........................................................... 22 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (April 2013) to Revision D • Added Pin Configuration and Functions section, ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section .............................. 1 Changes from Revision B (April 2013) to Revision C • 2 Page Page Changed layout of National Data Sheet to TI format ........................................................................................................... 18 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 5 Pin Configuration and Functions DDC Package 6-Pin SOT Top View 1 6 OUTPUT V 5 - 2 + SHUTDOWN - 3 +IN + V 4 -IN Pin Functions PIN NAME NO. I/O DESCRIPTION +IN 3 I Noninverting Input -IN 4 I Inverting Input Output 1 O Output Shutdown 5 I Shutdown Input V+ 6 P Positive Supply Voltage V- 2 P Negative Supply Voltage 6 Specifications 6.1 Absolute Maximum Ratings See (1) (2) MIN Supply Voltage (V+ – V−) VIN Differential (V+) + 0.3 Voltage at Input and Output Pin Current at Input Pin Junction Temperature (3) –40 Mounting Temperature, Infrared or Convection (20 s) Storage temperature (1) (2) (3) –60 MAX UNIT 3.1 V ±0.3 V (V−) − 0.3 V ±10 mA 150 °C 235 °C 150 °C Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Recommended Operating Conditions indicate conditions for which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC Board. 6.2 ESD Ratings VALUE V(ESD) (1) (2) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) (2) ±2000 Machine model ±200 UNIT V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC) Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 3 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com 6.3 Recommended Operating Conditions Temperature Range (1) Supply Voltage (1) MIN MAX UNIT –40 125 °C 0.9 3 V The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC Board. 6.4 Thermal Information LMV951 THERMAL METRIC (1) DDC (SOT) UNIT 6 PINS RθJA (1) (2) Junction-to-ambient thermal resistance (2) 170 °C/W For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. The maximum power dissipation is a function of TJ(MAX), RθJA. The maximum allowable power dissipation at any ambient temperature is PD = TJ(MAX) - TA)/RθJA. All numbers apply for packages soldered directly onto a PC Board. 6.5 Electrical Characteristics: 1 V Unless otherwise specified, all limits specified for at TA = 25°C, V+ = 1, V− = 0 V, VCM = 0.5 V, Shutdown = 0 V, and RL = 1 MΩ. (1) PARAMETER VOS Input Offset Voltage TC VOS Input Offset Average Drift IB Input Bias Current IOS Input Offset Current TEST CONDITIONS TA = 25°C AV At the temperature extremes 0.2 67 At the temperature extremes 55 TA = 25°C 76 At the temperature extremes 73 1 V ≤ V ≤ 1.8 V, VCM = 0.5 V TA = 25°C 70 At the temperature extremes 67 1 V ≤ V+ ≤ 3 V, VCM = 0.5 V TA = 25°C 68 At the temperature extremes 65 Power Supply Rejection Ratio CMRR ≥ 67 dB 90 At the temperature extremes 85 VOUT = 0.1 V to 0.9 V RL = 2 kΩ to 0.5 V TA = 25°C 90 At the temperature extremes 86 TA = 25°C 50 At the temperature extremes 62 TA = 25°C 25 At the temperature extremes 36 TA = 25°C 70 At the temperature extremes 85 TA = 25°C 35 At the temperature extremes 40 Output Voltage Swing High RL = 2 kΩ to 0.5 V VOUT RL = 600 Ω to 0.5 V Output Voltage Swing Low RL = 2 kΩ to 0.5 V (2) (3) 4 92 dB 85 1.2 TA = 25°C Large Signal Voltage Gain dB 85 1.2 VOUT = 0.1 V to 0.9 V RL = 600 Ω to 0.5 V nA nA 0 At the temperature extremes mV 77 0 CMRR ≥ 55 dB UNIT μV/°C 80 85 TA = 25°C RL = 600 Ω to 0.5 V (1) 2.8 32 Common-Mode Rejection Ratio Input Common-Mode Voltage Range 1.5 0.15 + VCM MAX (2) 3 TA = 25°C 0.1 V ≤ VCM ≤ 1 V PSRR TYP (3) At the temperature extremes 0 V ≤ VCM ≤ 1 V CMRR MIN (2) V 106 112 dB 25 12 32 mV from rail 10 Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions is very limited selfheating of the device. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 Electrical Characteristics: 1 V (continued) Unless otherwise specified, all limits specified for at TA = 25°C, V+ = 1, V− = 0 V, VCM = 0.5 V, Shutdown = 0 V, and RL = 1 MΩ.(1) PARAMETER IOUT Output Short-Circuit Current TEST CONDITIONS (4) MIN (2) TYP (3) 45 Sourcing VO = 0 V, VIN(DIFF) = ±0.2 V TA = 25°C 20 At the temperature extremes 15 Sinking VO = 1 V, VIN(DIFF) = ±0.2 V TA = 25°C 20 At the temperature extremes 13 IS TA = 25°C Shutdown Mode VSD >0.6 V 0.01 At the temperature extremes Slew Rate GBWP Gain Bandwidth Product en Input-Referred Voltage Noise in Input-Referred Current Noise THD Total Harmonic Distortion f = 1 kHz, AV = 1, RL = 1 kΩ ISD Shutdown Pin Current VSD Shutdown Pin Voltage Range 1 μA 3 (5) SR (4) (5) See 480 520 Supply Current UNIT mA 35 370 Active Mode VSD <0.4 V MAX (2) 1.4 V/μs 2.7 MHz f = 1 kHz 25 nV/√Hz f = 1 kHz 0.2 pA/√Hz 0.02% Active Mode, VSD = 0 V .001 1 Shutdown Mode, VSD = 1 V .001 1 Active Mode Shutdown Mode 0 0.4 0.65 1 µA V The short-circuit test is a momentary test, the short-circuit duration is 1.5 ms. Number specified is the average of the positive and negative slew rates. 6.6 Electrical Characteristics: 1.8 V Unless otherwise specified, all limits specified for at TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = 0.9 V, Shutdown = 0 V, and RL = 1 MΩ. (1) PARAMETER VOS Input Offset Voltage TC VOS Input Offset Average Drift IB Input Bias Current IOS Input Offset Current CMRR PSRR VCM AV (1) (2) (3) Common-Mode Rejection Ratio Power Supply Rejection Ratio Input Common-Mode Voltage Range TEST CONDITIONS MIN (2) TA = 25°C TYP (3) MAX (2) 1.5 2.8 At the temperature extremes 3 36 At the temperature extremes 80 85 0.2 TA = 25°C 82 At the temperature extremes 80 TA = 25°C 70 At the temperature extremes 67 1 V ≤ V+ ≤ 3 V, VCM = TA = 25°C 0.5 V At the temperature extremes 68 0 V ≤ VCM ≤ 1.8 V 1 V ≤ V+ ≤ 1.8V, VCM = 0.5 V CMRR ≥ 82 dB nA nA 93 dB 92 dB 85 65 –0.2 2 –0.2 2 CMRR ≥ 80 dB At the temperature extremes VOUT = 0.2 to 1.6 V RL = 600 Ω to 0.9 V TA = 25°C 86 At the temperature extremes 83 VOUT = 0.2 to 1.6 V RL = 2 kΩ to 0.9 V TA = 25°C 86 At the temperature extremes 83 Large Signal Voltage Gain mV μV/°C 0.15 TA = 25°C UNIT V 110 116 dB Electrical table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions is very limited selfheating of the device. All limits are specified by testing or statistical analysis. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 5 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Electrical Characteristics: 1.8 V (continued) Unless otherwise specified, all limits specified for at TA = 25°C, V+ = 1.8 V, V− = 0 V, VCM = 0.9 V, Shutdown = 0 V, and RL = 1 MΩ.(1) PARAMETER RL = 600 Ω to 0.9 V Output Voltage Swing High RL = 2 kΩ to 0.9 V VOUT RL = 600 Ω to 0.9 V Output Voltage Swing Low Output Short-Circuit Current (4) IS Supply Current TYP (3) TA = 25°C 50 33 At the temperature extremes 60 TA = 25°C 25 At the temperature extremes 34 TA = 25°C 35 44 TA = 25°C 50 At the temperature extremes 35 Sinking TA = 25°C VO = 1.8 V, VIN(DIFF) = At the temperature extremes ±0.2 V 45 Sourcing VO = 0 V, VIN(DIFF) = ±0.2 V 17 85 en Input-Referred Voltage Noise f = 1 kHz in Input-Referred Current Noise f = 1 kHz THD Total Harmonic Distortion f = 1 kHz, AV = 1, RL = 1 kΩ ISD Shutdown Pin Current VSD Shutdown Pin Voltage Range mA 80 780 880 At the temperature extremes Gain Bandwidth Product mV from rail 54 0.3 2.2 1.4 V/μs 2.8 MHz 25 nV/√Hz 0.2 pA/Hz 0.02% Active Mode, VSD = 0 V .001 1 Shutdown Mode, VSD = 1.8 V .001 1 Active Mode Shutdown Mode μA 10 (5) Slew Rate 6 See 13 570 TA = 25°C GBWP UNIT 25 Active Mode VSD <0.5 TA = 25°C V At the temperature extremes SR MAX (2) 105 At the temperature extremes Shutdown Mode VSD >1.3 V (4) (5) 80 At the temperature extremes TA = 25°C RL = 2 kΩ to 0.9 V IOUT MIN (2) TEST CONDITIONS 0 0.5 1.45 1.8 µA V The short-circuit test is a momentary test, the short-circuit duration is 1.5 ms. Number specified is the average of the positive and negative slew rates. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 6.7 Typical Characteristics Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. 1.6 120 100 SUPPLY CURRENT (nA) SUPPLY CURRENT (mA) 1.4 1.2 1 125°C 0.8 25°C 0.6 -40°C 0.4 1.2 1.6 2.4 2 60 125°C 40 25°C 2.8 0 0.8 3.2 1.2 1.6 2 2.4 2.8 3.2 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 1. Supply Current vs Supply Voltage Figure 2. Supply Current vs Supply Voltage in Shutdown Mode 0.5 0.8 + 125°C V = 1V 25°C 25°C 125°C 0.4 SUPPLY CURRENT (mA) SUPPLY CURRENT (mA) -40°C 20 0.2 0.8 80 0.3 -40°C 0.2 0.1 + V = 1.8V 0.6 0.4 -40°C 0.2 0 0 0 0.2 0.4 0.6 0.8 0.3 0 1 0.6 0.9 1.2 1.5 1.8 SHUTDOWN VOLTAGE (V) SHUTDOWN VOLTAGE (V) Figure 3. Supply Current vs Shutdown Voltage Figure 4. Supply Current vs Shutdown Voltage 2 2 + V = 3V 25°C 1.8 125°C 25°C 1.2 VOS (mV) SUPPLY CURRENT (mA) 125°C 1.6 -40°C 0 1.6 1.4 -40°C 0.4 1.2 0 1 + V = 1V 0 0.5 1 1.5 2 2.5 3 0 0.2 0.4 0.6 0.8 SHUTDOWN VOLTAGE (V) VCM (V) Figure 5. Supply Current vs Shutdown Voltage Figure 6. VOS vs VCM 1 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 7 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. 1.4 1.6 125°C 1.2 125°C VOS ( mV) VOS (mV) 1.5 25°C 1.4 1.3 1 25°C 0.8 -40°C 0.6 -40°C + + V = 3V V = 1.8V 0.4 1.2 0.3 0 0.6 0.9 1.2 1.5 1.8 0.5 0 1 VCM (V) 1.5 2 2.5 3 VCM (V) Figure 7. VOS vs VCM Figure 8. VOS vs VCM 1.9 40 + 125°C V = 1V 125°C 25°C 35 IBIAS (nA) VOS (mV) 1.5 1.1 25°C -40°C 30 25 0.7 -40°C 0.3 20 1.2 0.8 1.6 2 2.4 2.8 3.2 0 0.2 0.4 Figure 9. VOS vs Supply Voltage 1 + + V = 3V V = 1.8V 40 0.8 Figure 10. IBIAS vs VCM 46 41 0.6 VCM (V) SUPPLY VOLTAGE (V) 43 125°C 125°C IBIAS (nA) IBIAS (nA) 39 -40°C 38 40 25°C -40°C 37 37 25°C 34 36 31 35 0 8 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0 0.5 1 1.5 2 2.5 VCM (V) VCM (V) Figure 11. IBIAS vs VCM Figure 12. IBIAS vs VCM Submit Documentation Feedback 3 Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. 160 200 140 170 -40°C -40°C 140 25°C ISINK (mA) ISOURCE (mA) 120 100 80 125°C 25°C 110 80 60 125°C 50 40 20 0.8 1.2 1.6 2.4 2.8 2 SUPPLY VOLTAGE (V) 20 0.8 3.2 1.2 1.6 2 Figure 13. Sourcing Current vs Supply Voltage 2.8 3.2 Figure 14. Sinking Current vs Supply Voltage 60 50 + + V = 1V V = 1V 50 40 -40°C -40°C 40 ISINK (mA) ISOURCE (mA) 2.4 SUPPLY VOLTAGE (V) 25°C 30 125°C 30 25°C 20 20 125°C 10 10 0 0 0 0.2 0.4 0.6 0.8 1 0 0.2 0.4 0.6 0.8 1 VOUT VOUT (V) Figure 15. Sourcing Current vs Output Voltage Figure 16. Sinking Current vs Output Voltage 120 100 + + V = 1.8V V = 1.8V -40°C 90 25°C ISINK (mA) ISOURCE (mA) 75 50 125°C -40°C 60 25°C 30 25 125°C 0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 0 0.3 0.6 0.9 1.2 1.5 1.8 VOUT (V) VOUT (V) Figure 17. Sourcing Current vs Output Voltage Figure 18. Sinking Current vs Output Voltage Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 9 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. 160 210 + + V = 3V V = 3V 140 180 -40°C 150 100 ISINK (mA) ISOURCE (mA) 120 25°C 80 125°C 60 -40°C 120 25°C 90 40 60 20 30 0 125°C 0.5 0 1 2 1.5 2.5 0 0 3 0.5 1 VOUT (V) Figure 19. Sourcing Current vs Output Voltage 2.5 3 Figure 20. Sinking Current vs Output Voltage 40 50 RL = 2 k: RL = 2 k: 40 30 VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) 2 1.5 VOUT (V) 125°C 20 25°C 10 125°C 20 10 -40°C -40°C 0 0.8 1.2 1.6 2 2.4 2.8 0 0.8 3.2 25°C 30 1.2 1.6 2 2.4 2.8 3.2 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 21. Positive Output Swing vs Supply Voltage Figure 22. Negative Output Swing vs Supply Voltage 140 70 RL = 600: 120 60 50 125°C VOUT FROM RAIL (mV) VOUT FROM RAIL (mV) RL = 600: 25°C 40 -40°C 30 100 125°C 25°C 80 60 40 -40°C 20 0.8 10 1.2 1.6 2 2.4 2.8 20 0.8 3.2 1.2 1.6 2 2.4 2.8 3.2 SUPPLY VOLTAGE (V) SUPPLY VOLTAGE (V) Figure 23. Positive Output Swing vs Supply Voltage Figure 24. Negative Output Swing vs Supply Voltage Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. 100 100 100 100 10 k: 20 pF 50 pF 60 80 60 60 40 40 80 PHASE 2 k: 20 20 20 pF 0 0 -20 -40 -20 50 pF + V = 1V 100 pF RL = 2 k: 200 pF -60 1k 100k 10k 1M GAIN (dB) 200 pF GAIN PHASE (°) GAIN (dB) 40 40 GAIN 10 k: 20 20 0 0 600: -20 V = 1V -40 -40 CL = 20 pF -60 100M 10M -60 1k 100k 10k 1M Figure 25. Open Loop Gain and Phase With Capacitive Load 100 100 10 k: 20 pF PHASE 60 80 80 50 pF 60 60 40 40 80 PHASE 2 k: 20 pF 20 0 0 -20 100 pF 1M 10M 20 20 0 0 -40 -40 CL = 20 pF -60 100M -60 1k 100k 10k 1M 10M -60 100M FREQUENCY (Hz) Figure 27. Open Loop Gain and Phase With Capacitive Load Figure 28. Open Loop Gain and Phase With Resistive Load 100 100 100 100 20 pF PHASE -20 2 k: + V = 1.8V FREQUENCY (Hz) 80 10 k: -20 -40 200 pF 100k 40 GAIN 600: -20 50 pF + -40 V = 1.8V RL = 2 k: -60 1k 10k GAIN (dB) 20 PHASE (°) 200 pF GAIN 60 600: 100 pF 40 -60 100M Figure 26. Open Loop Gain and Phase With Resistive Load 100 100 GAIN (dB) 10M FREQUENCY (Hz) FREQUENCY (Hz) 80 -20 2 k: + -40 60 600: 100 pF PHASE (°) 80 PHASE PHASE (°) 80 10 k: 80 80 60 60 60 40 40 80 2 k: PHASE 50 pF 600: 60 20 20 pF 20 0 0 50 pF -20 -20 200 pF 100k 1M 10M 10 k: 20 20 0 0 600: -20 100 pF + -40 V = 3V RL = 2 k: -60 1k 10k 40 GAIN 2 k: + -40 -40 V = 3V PHASE (°) 200 pF GAIN GAIN (dB) 40 PHASE (°) GAIN (dB) 100 pF -20 -40 CL = 20 pF -60 100M -60 1k 10k 100k 1M 10M -60 100M FREQUENCY (Hz) FREQUENCY (Hz) Figure 29. Open Loop Gain and Phase With Capacitive Load Figure 30. Open Loop Gain and Phase With Resistive Load Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 11 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) 10 mV/DIV 200 mV/DIV Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. INPUT = 20 mVPP f = 500 kHz INPUT = 0.8 VPP f = 100 kHz + + V = 1V V = 1V 2 PV/DIV 500 ns/DIV Figure 32. Large Signal Transient Response, AV = +1 10 mV/DIV 200 mV/DIV Figure 31. Small Signal Transient Response, AV = +1 INPUT = 0.8 VPP f = 100 kHz INPUT = 20 mVPP f = 500 kHz + + V = 1.8V V = 1.8V 500 ns/DIV 2 PV/DIV Figure 34. Large Signal Transient Response, AV = +1 10 mV/DIV 200 mV/DIV Figure 33. Small Signal Transient Response, AV = +1 INPUT = 20 mVPP f = 500 kHz INPUT = 0.8 VPP f = 100 kHz + + V = 3V V = 3V 500 ns/DIV 2 PV/DIV Figure 35. Small Signal Transient Response, AV = +1 12 Figure 36. Large Signal Transient Response, AV = +1 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 Typical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. 100 100 + + V = 1V V = 1.8V 75 PHASE MARGIN (°) PHASE MARGIN (°) 75 600: 50 2 k: 10 k: 25 0 10 100 1000 600: 50 2 k: 10 k: 25 0 10 10000 100 CAPACITIVE LOAD (pF) Figure 37. Phase Margin vs Capacitive Load (Stability) 100 1000 10000 CAPACITIVE LOAD (pF) Figure 38. Phase Margin vs Capacitive Load (Stability) 120 + V = 3V 1.8V 100 1V 600: +PSRR 80 PSRR (dB) PHASE MARGIN (°) 75 50 2 k: 3V 60 -PSRR 40 10 k: 1V, 1.8V, 3V 25 20 0 10 100 1000 0 100 10000 1k CAPACITIVE LOAD (pF) Figure 39. Phase Margin vs Capacitive Load (Stability) 110 10k 100k 1M FREQUENCY (Hz) Figure 40. PSRR vs Frequency 140 + V = 1.8V CMRR (dB) 90 + V = 3V VOLTAGE NOISE (nV/ Hz) 100 + V = 1V 80 70 60 50 120 V+ = 1.8V 80 1k 10k 100k 40 0 10 1M + V = 3V 60 20 40 100 + V = 1V 100 + V = 1V 100 1k 10k 100k FREQUENCY (Hz) FREQUENCY (Hz) Figure 41. CMRR vs Frequency Figure 42. Input Referenced Voltage Noise vs Frequency Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 13 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Typical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, V+ = 1 V, V− = 0 V, VCM = V+/2 = VO. 0.16 0.18 + + V = 1.8V V = 1V 0.14 0.15 600: 0.12 600: 0.1 THD+N (%) THD+N (%) 0.12 0.09 0.08 0.06 0.06 100 k: 0.04 100 k: 0.03 0.02 0 0 10 100 1k 10k 100k 10 100 FREQUENCY (Hz) Figure 43. THD+N vs Frequency 0.14 1k 10k 100k FREQUENCY (Hz) Figure 44. THD+N vs Frequency 1000 + V = 3V + V = 1V 0.12 100 OUTPUT IMPEDANCE (:) THD+N (%) 0.1 600: 0.08 0.06 100 k: 0.04 10 1 0.1 0.02 0 10 14 100 1k 10k 100k 0.01 100 1k 10k 100k 1M 10M FREQUENCY (Hz) FREQUENCY (Hz) Figure 45. THD+N vs Frequency Figure 46. Closed Loop Output Impedance vs Frequency Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 7 Detailed Description 7.1 Overview The LMV951 device is low-voltage operational amplifier that utilizes an internal charge pump which allows for full rail-to-rail input and output operation from 1-V to 3-V supplies. An internal switching frequency from 10 MHz to 15 MHz is used for generating the internal voltages. 7.2 Functional Block Diagram + ABOVE V GENERATOR 5 SHUTDOWN V + 6 INTERNAL GAIN STAGE IN- IN+ 1 OUTPUT 4 3 2 V - - BELOW V GENERATOR 7.3 Feature Description 7.3.1 Battery Operated Systems The maximum operating voltage is 3 V and the operating characteristics are ensured down to 1 V which makes the LMV951 an excellent choice for battery operated systems using one or two NiCd or NiMH cells. The LMV951 is also functional at 0.9 V making it an appropriate choice for a single cell alkaline battery. 7.3.2 Small Size The small footprint of the LMV951 package is ideal for high density board systems. By using the small 6-pin SOT package, the amplifier can be placed closer to the signal source, reducing noise pickup and increasing signal integrity. 7.4 Device Functional Modes 7.4.1 Shutdown Capability While in shutdown mode, the LMV951 typically consumes less than 50 nA of supply current making it ideal for power conscious applications. Full functionality is restored within 3 μs of enable. The output is in a high impedance state during shutdown. Voltages may be applied to the inputs and output during shutdown provided they are within the legal V+ to V- range. 7.4.2 Rail-to-Rail Input The bipolar input stage provides rail-to-rail input operation with no input bias current reversal and a constant input offset voltage over the entire input common-mode range. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 15 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Device Functional Modes (continued) The input contains protection diodes between the inputs to limit the differential voltage (voltage between the input pins). The LMV951 should NOT be used for comparator applications as the diodes will clamp the inputs together. These diodes may also cause issues with follower configurations during shutdown as crosstalk may occur between the input pins through these diodes. 7.4.3 Rail-to-Rail Output The CMOS output stage provides a gain that is virtually independent of resistive loads and an output drive current in excess of 35 mA at 1 V. A further benefit of the output stage is that the LMV951 is stable in positive unity gain at capacitive loads in excess of 1000 pF. The internal charge pumps are used to provide the needed headroom for the internal gate drive circuitry and does not enable the output to swing beyond the rails. The output swing is still bound by the V+ and V- rails. 7.4.4 Driving Capacitive Load The unity gain follower is the most sensitive op amp configuration to capacitive loading. The LMV951 can drive up to 10,000 pF in this configuration without oscillation. If the application requires a phase margin greater than those shown in the datasheet graphs, a snubber network is recommended. The snubber offers the advantage of reducing the output signal ringing while maintaining the output swing which ensures a wider dynamic range; this is especially important at lower supply voltages. VCC - V + VOUT + - V + VIN VEE RS RL CL CS - Figure 47. Snubber Network to Improve Phase Margin Table 1 gives recommended values for some common values of large capacitors. For these values RL = 2 kΩ. Table 1. Recommended Values for Snubbing Network 16 CL RS CS 500 pF 330Ω 6800 pF 680 pF 270Ω 8200 pF 1000 pF 220Ω .015 μF Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 25 mV/DIV 25 mV/DIV www.ti.com + + V = 1V V = 1V 1 Ps/DIV 1 Ps/DIV Figure 48. 1000 pF and No Snubber Figure 49. 1000 pF With Snubber Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 17 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information The unique internal charge pumps allows the LMV951 to fully function at supply voltages as low as 0.9 V. This opens up new possibilities for unique low-voltage circuits that are not possible with standard amplifiers. 8.2 Typical Applications 8.2.1 Two Wire Line Transmission The circuit shown in Figure 50 can drive a long cable using only two wires; a combined single signal and power wire and ground. The robust output stage and low operating voltage of the LMV951 makes it an excellent choice for driving long cables. R3 1 k: R1 10 k: C2 10 PF C6 .01 PF + V + C1 1 PF SENSOR C3 20 PF CABLE 3V 3V 3V R4 1 k: R5 10 k: R2 10 k: - V + A1 - V C4 1 PF R6 10 k: SD + A2 - C5 10 PF C6 .01 PF OUTPUT - V SD Figure 50. Two Wire Line Driver 8.2.1.1 Design Requirements When many sensors are located remotely from the control area the wiring becomes a significant expense. Using only two wires helps minimize the wiring expense in a large project such as an industrial plant. It is desired to both provide a buffered signal from the sensor as well as provide power to the sensor amplifier. 8.2.1.2 Detailed Design Procedure TI recommends a power supply of 3 V to power this system. A1 and A2 are set up as unity gain buffers. Configuring A1 with the required gain is simple if a gain of greater than one is required. C1 along with R1 and R2 are used to ensure the correct DC operating point at the input of A1. C4 along with R5 and R6 are used to set up the correct DC operating point for A2. C1, C3, and C4 have been selected to give about a 20% droop with a 1-kHz square wave input. 8.2.1.3 Application Curves Figure 51 shows a 25-kHz signal after passing though 1000 ft of twisted-pair cable. Figure 52 shows a 200 kHz signal after passing through 50 ft of twisted-pair cable. 18 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 200 mV/DIV 200 mV/DIV Typical Applications (continued) INPUT = 1 VPP INPUT = 1 VPP 5 Ps/DIV 1 Ps/DIV Figure 51. 25 kHz Through 1000 ft Figure 52. 200 kHz Through 50 ft 8.2.2 Bridge Configuration Amplifier R7 10 k: C4 .1 PF + V A2 A1 R2 100 k: - RL - V VL R5 100 k: + V + VIN C1 1 PF 5V C3 .01 PF C2 .01 PF - - R1 100 k: + + V V R6 100 k: SD SD R3 100 k: R4 100 k: Figure 53. Bridge Amplifier Some applications may benefit from doubling the voltage across the load. With V+ = 1 V a bridge configuration can provide a 2-VPP output to the load with a resistance as low as 300 Ω. The output stage of the LMV951 enables it to drive a load of 120 Ω and still swing at least 70% of the supply rails. The bridge configuration shown in Figure 53 enables the amplifier to maintain a low dropout voltage thus maximizing its dynamic range. It has been configured in a gain of 1 and uses the fewest number of parts. Resistor values have been selected to keep the current consumption to a minimum and voltage errors due to bias currents negligible. Using the selected resistor values makes this circuit quite practical in a battery operated design. R1, R2 and R5, R6 set up a virtual ground that is half of V+. The accuracy of the resistor values will establish how well the two virtual grounds match. Any errors in the virtual grounds will show as current across RL when there is no input signal. Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 19 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com Typical Applications (continued) AC coupling the input signal sets the DC bias point of this signal to the virtual ground of the circuit. Using the large resistor values with a 1-µF capacitor (C1) sets the frequency rolloff of this circuit below 10 Hz. • C2 and C3 are .01-μF ceramic capacitors that must be located as close as possible to pin 6, the V+ pin. As covered in the power supply bypassing section these capacitors must have low ESR and a self resonant frequency above 15 MHz. • C4 is a 1 μF tantalum or electrolytic capacitor that should also be located close to the supply pin. • To use the shutdown feature tie pin 5 of the two parts together and connect through a 470-kΩ resistor to V+. Add a switch between pin 5 and ground. Closing the switch keeps the parts in the active mode, opening the switch sets the parts in the shutdown mode without adding any additional current to V+. 8.2.3 Virtual Ground Circuit 1V R1 + + V VIRTUAL GROUND R2 SD V - C1 .01 PF C2 1 PF Figure 54. Virtual Ground Circuit Figure 54 shows the LMV951 being used in a system establishing a virtual ground. Having a buffered output stage gives this part the ability to handle load currents higher than 35 mA at 1 V. R3 and R4 are used to set the voltage of the virtual ground. To maintain low noise the values should be from 1 kΩ to 10 kΩ. C1 and C2 provide the recommended bypassing for the LMV951. These capacitors must be placed as close as possible to pins 2 and 6. 20 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 LMV951 www.ti.com SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 9 Power Supply Recommendations As in any high performance IC, proper power supply bypassing is necessary for optimizing the performance of the LMV951. The internal 15-MHz voltage generator needs proper supply bypassing for optimum operation. A surface mount ceramic .01-µF capacitor must be located as close as possible to the V+ and V− pins (pins 2 and 6). This capacitor needs to have low ESR and a self resonant frequency above 15 MHz. A small tantalum or electrolytic capacitor with a value from 1 µF to 10 µF must also be located close to the LMV951. 10 Layout 10.1 Layout Guidelines • • • • The V+ pin must be bypassed to ground with a low-ESR capacitor. The optimum placement is closest to the V+ and ground pins. Take care to minimize the loop area formed by the bypass capacitor connection between V+ and ground. The ground pin should be connected to the PCB ground plane at the pin of the device. The feedback components should be placed as close to the device as possible minimizing strays. 10.2 Layout Example Figure 55. Layout Recommendation Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 21 LMV951 SNOSAI3D – OCTOBER 2006 – REVISED SEPTEMBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Device Support 11.1.1 Development Support LMV951 PSPICE Model, http://www.ti.com/lit/zip/snom029 TINA-TI SPICE-Based Analog Simulation Program, http://www.ti.com/tool/tina-ti DIP Adapter Evaluation Module, http://www.ti.com/tool/dip-adapter-evm TI Universal Operational Amplifier Evaluation Module, http://www.ti.com/tool/opampevm TI Filterpro Software, http://www.ti.com/tool/filterpro WEBENCH® Amplifier Designer, http://www.ti.com/lsds/ti/analog/webench/amplifiers.page 11.2 Documentation Support 11.2.1 Related Documentation For additional applications, see the following: AN-31 Op Amp Circuit Collection, SNLA140 11.3 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.4 Trademarks E2E is a trademark of Texas Instruments. WEBENCH is a registered trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.5 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.6 Glossary SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 22 Submit Documentation Feedback Copyright © 2006–2015, Texas Instruments Incorporated Product Folder Links: LMV951 PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LMV951MK/NOPB ACTIVE SOT DDC 6 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AS3A LMV951MKX/NOPB ACTIVE SOT DDC 6 3000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 AS3A (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Aug-2015 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LMV951MK/NOPB SOT DDC 6 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 LMV951MKX/NOPB SOT DDC 6 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Aug-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMV951MK/NOPB SOT DDC 6 1000 210.0 185.0 35.0 LMV951MKX/NOPB SOT DDC 6 3000 210.0 185.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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