LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 LMH1982 Multi-Rate Video Clock Generator with Genlock Check for Samples: LMH1982 FEATURES DESCRIPTION • The LMH1982 is a multi-rate video clock generator ideal for use in a wide range of 3-Gbps (3G), highdefinition (HD), and standard-definition (SD) video applications, such as video synchronization, serial digital interface (SDI) serializer and deserializer (SerDes), video conversion, video editing, and other broadcast and professional video systems. 1 2 • • • • • • • • • Two Simultaneous LVDS Output Clocks with Selectable Frequencies and Hi-Z Capability: – SD Clock: 27 MHz or 67.5 MHz – HD Clock: 74.25 MHz, 74.25/1.001 MHz, 148.5 MHz or 148.5/1.001 MHz Low-Jitter Output Clocks May Be Directly Connected to an FPGA Serializer to Meet SMPTE SDI Jitter Specifications Top of Frame (TOF) Pulse with Programmable Output Format Timing and Hi-Z Capability Two reference ports (A and B) with H and V sync inputs Supports Cross-Locking of Input and Output Timing External Loop Filter Allows Control of Loop Bandwidth, Jitter Transfer, and Lock Time Characteristics Free Run or Holdover Operation on Loss of Reference User-Defined Free Run Control Voltage Input I2C Interface and Control Registers 3.3V and 2.5V Supplies APPLICATIONS • • • • • • Video Genlock and Synchronization FPGA SDI SerDes Recovered Clock Generation Triple Rate 3G/HD/SD-SDI SerDes Video Capture, Conversion, Editing and Distribution Video Displays and Projectors Broadcast and Professional Video Equipment The LMH1982 can generate two simultaneous SD and HD clocks and a Top of Frame (TOF) pulse. In genlock mode, the device's phase locked loops (PLLs) can synchronize the output signals to H sync and V sync input signals applied to either of the reference ports. The input reference can have analog timing from Texas Instrument's LMH1981 multi-format video sync separator or digital timing from an SDI deserializer and should conform to the major SD and HD standards. When a loss of reference occurs, the device can default to free run operation where the output timing accuracy will be determined by the external bias on the free run control voltage input. The LMH1982 can replace discrete PLLs and fieldprogrammable gate array (FPGA) PLLs with multiple voltage controlled crystal oscillators (VCXOs). Only one 27.0000 MHz VCXO and loop filter are externally required for genlock mode. The external loop filter as well as programmable PLL parameters can provide narrow loop bandwidths to minimize jitter transfer. HD clock output jitter as low as 40 ps peak-to-peak can help designers using FPGA SerDes meet stringent SDI output jitter specifications. The LMH1982 is offered in a space-saving 5 mm x 5 mm 32-pin WQFN package and provides low total power consumption of about 250 mW (typical). 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2008–2013, Texas Instruments Incorporated LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Typical Video Genlock Block Diagram VC LOOP FILTER VCXO 27 MHz ANALOG REF. IN LMH1981 MULTI-FORMAT VIDEO SYNC SEPARATOR H sync V sync REF_A TX 27 or 67.5 MHz LMH1982 MULTI-RATE CLOCK GENERATOR H sync OPTIONAL BACK-UP REFERENCE INPUTS V sync GENLOCKED 3G-SDI OUT TOF LPF VCXO TOF SD_CLK FPGA with SerDes TRIPLE-RATE SDI HD_CLK REF_B RX_1 74.25, 74.176, 148.5 or 148.35 MHz ASYNCHRONOUS 3G-SDI IN WRITE/READ DATA and TIMING/CLOCK SIGNALS FRAME BUFFER Functional Block Diagram LOOP FILTER 27 MHz VCXO VC_FREERUN VCXO LPF 27 SWITCH 67.5 GENLOCK HREF_A VREF_A HREF_B REFERENCE SELECTION and INPUT POLARITY PLL 1 with EXT. VCXO and LPF H 27 MHz PLL 2,3,4 with INTEGRATED VCOs 3 REFERENCE DETECT LVDS 74.25 148.5 MUX LVDS SD_CLK SD_CLK HD_CLK HD_CLK OUTPUT RESET V VREF_B MUX 74.176 148.35 PLL LOCK DETECT TOF CLK H REF_SEL V OUTPUT TOF TIMING GENERATION TOF_OUT NO_LOCK NO_REF 2 I C INTERFACE and CONTROL REGISTERS SDA 2 SCL 2 I C_ENABLE RESET Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Typical Loop Filter Topology LPF VC CP CS LMH1982 VCXO OUT RS VCXO Connection Diagram VDD LPF GND VCXO VDD VDD GND TOF 32 31 30 29 28 27 26 25 Top View VC_FREERUN 1 24 SD_CLK GND 2 23 SD_CLK VDD 3 22 GND HREF_A 4 21 VDD VREF_A 5 20 HD_CLK REF_SEL 6 19 HD_CLK HREF_B 7 18 GND VREF_B 8 17 NO_LOCK 16 NO_REF 15 RESET 14 GENLOCK 13 12 SCL 2 11 SDA I C_ENABLE 10 GND DVDD 9 DAP Figure 1. 32-Pin WQFN Package See Package Number RTV0032A Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 3 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Pin Descriptions (1) Pin No. Pin Name I/O – DAP – Supply Die Attach Pad (Connect to GND) 1 VC_FREERUN I Analog Free Run Control Voltage Input 2, 10, 18, 22, 26, 30 GND – Supply Ground 3, 21, 27, 28, 32 VDD – Supply 3.3V Supply 1 4 HREF_A I LVCMOS H sync Input, Reference A 5 VREF_A I LVCMOS V sync Input, Reference A 6 REF_SEL I LVCMOS Reference Select 2, 3 7 HREF_B I LVCMOS H sync Input, Reference B 8 VREF_B I LVCMOS V sync Input, Reference B 9 DVDD – Supply Pin Description 2.5V Supply 4 I/O 2 I C I2C Data 5 SCL I 2 I C I2C Clock 5 13 I C_ENABLE I LVCMOS I2C Enable 14 GENLOCK I LVCMOS Mode Select 6 11 SDA 12 (1) Signal Level 2 15 RESET I LVCMOS Device Reset 16 NO_REF O LVCMOS Reference Status Flag 17 NO_LOCK O LVCMOS Lock Status Flag 19, 20 HD_CLK, HD_CLK O LVDS HD Clock Output 23, 24 SD_CLK, SD_CLK O LVDS SD Clock Output 25 TOF O LVCMOS Top of Frame Pulse 29 VCXO I LVCMOS VCXO Clock Input 31 LPF O Analog VCXO PLL Loop Filter Notes 1. Refer to section Power Supply Sequencing. 2. To control reference selection via the REF_SEL pin instead of the I2C interface (default), program I2C_RSEL = 0 (register 00h). 3. To override reference control via pin 6 and instead use pin 6 as an logic input for output initialization, program PIN6_OVRD = 1 (register 02h); accordingly, the TOF_INIT bit (register 0Ah) will be ignored and reference selection must be controlled via I2C. 4. Must be ≤ VDD +0.3V. Refer to section Power Supply Sequencing. 5. SDA and SCL pins each require a 4.7 kΩ (typ) pull-up resistor to the VDD supply. 6. To control mode selection via the GENLOCK pin instead of the I2C interface (default), program I2C_GNLK = 0 (register 00h). These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings ESD Tolerance (3) (1) (2) Human Body Model Machine Model Supply Voltage, VDD 2000V 200V 3.6V Supply Voltage, DVDD 2.75V DVDD ≤ VDD +0.3V −0.3V to VDD +0.3V Input Voltage Range (any input) −65°C to +150°C Storage Temperature Range Lead Temperature (Soldering 10 sec.) 300°C Junction Temperature, TJMAX 150°C Thermal Resistance (θJA) (1) (2) (3) 4 33°C/W Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which operation of the device is intended to be functional. For specifications and test conditions, see the Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications. Human Body Model, applicable std. MIL-STD-883, Method 3015.7. Machine Model, applicable std. JESD22-A115-A (ESD MM std. of JEDEC)Field-Induced Charge-Device Model, applicable std. JESD22-C101-C (ESD FICDM std. of JEDEC). Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Operating Ratings VDD 3.3V ± 5% DVDD 2.5V ± 5% Input Voltage 0V to VDD Temperature Range, TA 0°C to 70°C Electrical Characteristics Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, DVDD = 2.5V, Boldface limits apply at the temperature extremes. Parameter IVDD VDD Supply Current IDVDD DVDD Supply Current IVDD VDD Supply Current IDVDD DVDD Supply Current Test Conditions Min (1) Typ (2) Max (1) Units Default register settings, no input reference, 27 MHz VCXO and loop filter connected, 100Ω differential load on SD_CLK and HD_CLK outputs; no load on all other outputs 47 mA 39 mA VDD = 3.465V, DVDD = 2.75V, Genlock mode, 1080p/59 output timing, HD_CLK = 148.35 MHz, SD_CLK = 67.5 MHz, 100Ω differential load on SD_CLK and HD_CLK outputs; no load on all other outputs 57 70 mA 44 60 mA Free Run Voltage Control Input (Pin 1) VIL VIH Low Analog Input Voltage (3) 0 V High Analog Input Voltage (3) VDD V Reference Inputs (Pins 4, 5, 7, 8) VIL Low Input Voltage IIN = ±10 μA 0 0.3 VDD V VIH High Input Voltage IIN = ±10 µA 0.7 VDD VDD V H-V Sync Timing Offset Input timing offset measured from H sync to V sync pulse leading edges (4) 2.0 μs ΔTHV Digital Control Inputs (Pins 6, 13, 14, 15) VIL Low Input Voltage IIN = ±10 µA 0 0.3 VDD V VIH High Input Voltage IIN = ±10 µA 0.7 VDD VDD V V I2C Interface (Pins 11, 12) VIL Low Input Voltage 0 0.3 VDD VIH High Input Voltage 0.7 VDD VDD V IIN Input Current VIN between 0.1 VDD and 0.9 VDD −10 +10 μA IOL Low Output Sink Current VOL = 0V or 0.4V 3 mA Status Flag Outputs (Pin 16, 17) VOL Low Output Voltage IOUT = +10 mA VOH High Output Voltage IOUT = −10 mA 0.4 V VDD −0.4V V Top of Frame Output (Pin 25) (1) (2) (3) (4) VOL Low Output Voltage IOUT = +10 mA VOH High Output Voltage IOUT = −10 mA IOZ Output Hi-Z Leakage Current TOF output in Hi-Z mode, output pin connected to VDD or GND 0.4 V VDD −0.4V V 0.4 10 |μA| Limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation using Statistical Quality Control (SQC) methods. Typical values represent the most likely parametric norm as determined at the time of characterization. Actual typical values may vary over time and will also depend on the application and configuration. The typical values are not tested and are not ensured on shipped production material. The input voltage to VC_FREERUN (pin 1) should also be within the input range of the external VCXO. The input voltage should be clean from noise that may significantly modulate the VCXO control voltage and consequently produce output jitter during free run operation. ΔTHV is a required specification that allows for proper frame decoding and subsequent output initialization (alignment). For interlace formats, the H-V sync timing offset must be within ΔTHV for all even fields and be outside ΔTHV for odd fields. For progressive formats, the H-V sync timing offset must be within ΔTHV for all frames. See sections Reference Frame Decoder and Output Frame Line Offset. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 5 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, DVDD = 2.5V, Boldface limits apply at the temperature extremes. Parameter Test Conditions Min (1) Typ (2) Max (1) Units tR Rise Time 15 pF load 1.5 ns tF Fall Time 15 pF load 1.5 ns TOF Output Delay Time Specified for any SD or HD format generated from 27 MHz TOF clock outputs initialized (7), 15 pF load 2 ns 27 MHz TIE Peak-to-Peak HD_CLK = Hi-Z Output Jitter (8) HD_CLK = 74.176 MHz 23 ps 40 ps 67.5 MHz TIE Peak-toPeak Output Jitter (8) HD_CLK = Hi-Z 40 ps HD_CLK = 74.176 MHz 50 ps 74.176 MHz TIE Peak-toPeak Output Jitter (8) SD_CLK = Hi-Z 55 ps SD_CLK = 27 MHz 65 ps 74.25 MHz TIE Peak-toPeak Output Jitter (8) SD_CLK = Hi-Z 40 ps SD_CLK = 27 MHz 50 ps 148.35 MHz TIE Peak-toPeak Output Jitter (8) SD_CLK = Hi-Z 60 ps SD_CLK = 27 MHz 70 ps 148.5 MHz TIE Peak-toPeak Output Jitter (8) SD_CLK = Hi-Z 45 ps SD_CLK = 27 MHz 55 ps 27 MHz Output Delay Time (9) SD_CLK = 27 MHz, Any valid output timing, outputs initialized (7) 4 ns 67.5 MHz Output Delay Time (9) SD_CLK = 67.5 MHz, 525i output timing (6) , outputs initialized (7) 6 ns 74.176 MHz Output Delay Time (10) HD_CLK = 74.176 MHz, 1080i/59 output timing (11), outputs initialized (12) 4.5 ns 74.25 MHz Output Delay Time (10) HD_CLK = 74.25 MHz, 1080i/50 output timing (11), outputs initialized (12) -0.6 ns 148.35 MHz Output Delay Time (10) HD_CLK = 148.35 MHz, 1080p/59 output timing (11), outputs initialized 1.5 ns 148.5 MHz Output Delay Time (10) HD_CLK = 148.5 MHz, 1080p/50 output timing (11), outputs initialized (12) 4.5 ns Differential Signal Output Voltage (13) 100Ω differential load tD_TOF (5) (6) , Clock Outputs (Pins 19, 20, 23, 24) JitterSD JitterHD tD_SD tD_HD VOD (5) (6) (7) (8) (9) (10) (11) (12) (13) 6 (12) 247 350 454 mV tD_TOF is measured from the TOF pulse (leading negative edge) to the 27 MHz SD_CLK output (positive edge) using 50% levels. For any SD and HD output formats, the TOF pulse can be generated using 27 MHz as the TOF clock by programming TOF_CLK = 0, SD_FREQ = 0, and the alternative output counter values shown in Table 1. See section HD Format TOF Generation using a 27 MHz TOF Clock. Output initialization refers to the initial alignment of the output frame clock and TOF signals to the input reference frame. See section Programming The Output Initialization Sequence. The SD and HD clock output jitter is based on VCXO clock (pin 29) with 20 ps peak-to-peak using a time interval error (TIE) jitter measurement. The typical TIE peak-to-peak jitter was measured on the LMH1982 evaluation bench board using TDSJIT3 jitter analysis software on a Tektronix DSA70604 oscilloscope and 1 GHz active differential probe. TDSJIT3 Clock TIE Measurement Setup: 10-12 bit error rate (BER), >1 Meg samples recorded using multiple acquisitions Oscilloscope Setup: 20 mV/div vertical scale, 100 µs/div horizontal scale, and 25 GS/s sampling rate tD_SD is measured from the VCXO clock input (pin 29) to the SD_CLK output (pins 23, 24) using positive edges and 50% levels. The measurement is taken at the leading edge of the TOF pulse (), where the input and output clocks are phase aligned at the start of frame. tD_HD is measured from the VCXO clock input (pin 29) to the HD_CLK output (pins 19, 20) using positive edges and 50% levels. The measurement is taken at the leading edge of the TOF pulse (11), where the input and output clocks are phase aligned at the start of frame. For any SD and HD output formats, the TOF pulse can be generated using 27 MHz as the TOF clock by programming TOF_CLK = 0, SD_FREQ = 0, and the alternative output counter values shown in Table 1. See section HD Format TOF Generation using a 27 MHz TOF Clock. Output initialization refers to the initial alignment of the output frame clock and TOF signals to the input reference frame. See section Programming The Output Initialization Sequence. This parameter is specified for the SD_CLK output only. This parameter is ensured by design for the HD_CLK output. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Electrical Characteristics (continued) Unless otherwise specified, all limits are specified for TA = 25°C, VDD = 3.3V, DVDD = 2.5V, Boldface limits apply at the temperature extremes. Parameter Test Conditions VOS Common Signal Output Voltage (13) 100Ω differential load |VOD| |Change to VOD| for Complementary Output States (13) |VOS| Min (1) 1.125 Typ (2) 1.250 Max (1) Units 1.375 V 100Ω differential load 50 |mV| |Change to VOS| for Complementary Output States (13) 100Ω differential load 50 |mV| IOS Output Short Circuit Current Differential clock output pins connected to GND 24 |mA| IOZ Output Hi-Z Leakage Current Output clock in Hi-Z mode, differential clock output pins connected to VDD or GND 10 |µA| 1 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 7 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Typical Performance Characteristics Test conditions: VDD = 3.3V, DVDD = 2.5V, Genlock mode, outputs initialized. H sync and V sync signals to REF_A inputs are from the LMH1981 sync separator, which receives an analog video reference signal from a Tektronix TG700 AVG7/AWVG7 (SD/HD) video signal generator. See Note section below for register settings (in decimal): NTSC TOF Pulse PAL TOF Pulse NTSC 500 mV/DIV PAL 500 mV/DIV H sync 2.0V/DIV H sync 2.0V/DIV V sync 2.0V/DIV V sync 2.0V/DIV TOF 2.0V/DIV TOF 2.0V/DIV TOF_OFFSET = 262 TOF_OFFSET = 312 100 Ps/DIV 100 Ps/DIV Figure 2. Figure 3. 1080i/50 TOF Pulse 1080p/24 TOF Pulse 1080i50 500 mV/DIV 1080p24 500 mV/DIV H sync 2.0V/DIV H sync 2.0V/DIV V sync 2.0V/DIV V sync 2.0V/DIV TOF 2.0V/DIV TOF 2.0V/DIV TOF_OFFSET = 562 TOF_OFFSET = 1124 40.0 Ps/DIV 40.0 Ps/DIV Figure . Figure 4. 525i TOF Output Delay Using 27 MHz TOF Clock 1080i/50 TOF Output Delay Using 74.25 MHz TOF Clock SD_CLK 27 MHz 500 mV/DIV HD_CLK 74.25 MHz 500 mV/DIV H sync 2.0V/DIV TOF 2.0V/DIV H sync 2.0V/DIV tOD = 2 ns TOF 2.0V/DIV 10.0 ns/DIV 10.0 ns/DIV Figure 5. 8 tOD = 3.5 ns Figure 6. (1) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1716, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1716, TOF_LPFM = 525, REF_LPFM = 525, TOF_OFFSET = 262; all other register settings are default (2) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1728, SD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1728, TOF_LPFM = 625, REF_LPFM = 625, TOF_OFFSET = 312; all other register settings are default (3) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 960, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 960, TOF_LPFM = 1125, REF_LPFM = 1125, TOF_OFFSET = 562; all other register settings are default (4) GNLK = 1, REF_DIV_SEL = 1, FB_DIV = 1000, SD_FREQ = 0, HD_FREQ = 0, TOF_CLK = 0, TOF_PPL = 1000, TOF_LPFM = 1125, REF_LPFM = 1125, TOF_OFFSET = 1124; all other register settings are default Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Supported Standards and Timing Formats Table 1 lists the known supported standard timing formats and includes the relevant parameters that can be used to configure the LMH1982 for the input reference and output timing. For the related programming instructions, see sections INPUT REFERENCE and OUTPUT CLOCKS AND TOF. Table 1. Input Reference and Output Timing Parameters INPUT TIMING PARAMETERS (1) (2) (3) (1) (1) (2) OUTPUT TIMING PARAMETERS (2) Format PLL 1 Reference Divider1 (3) PLL 1 Feedback Divider PLL 1 Phase Comparison Frequency (kHz) Total Lines per Frame Counter Clock Frequency (MHz) Total Clocks per Line Counter Total Lines per Frame Counter Frame Rate (Hz) NTSC, 525i 1 1716 15.7343 525 27.0 1716 525 29.97 PAL, 625i 1 1728 15.625 625 27.0 1728 625 25 525p 1 [5] 858 [4290] 31.4685 [6.2937] 525 [105] 27.0 858 525 59.94 625p 1 [5] 864 [4320] 31.25 [6.25] 625 [125] 27.0 864 625 50 720p/60 1 [5] 600 [3000] 45.0 [9.0] 750 [150] 74.25 (27.0) 1650 (600) 750 (750) 60 720p/59.94 5 3003 8991.0090 750 74.176 (27.0) 1650 (3003) 750 (150) 59.94 720p/50 1 [5] 720 [3600] 37.5 [7.5] 750 [150] 74.25 (27.0) 1980 (720) 750 (750) 50 720p/30 1 [5] 1200 [6000] 22.5 [4.5] 750 [150] 74.25 (27.0) 3300 (1200) 750 (150) 30 720p/29.97 5 6006 4.4955 750 74.176 (27.0) 3300 (6006) 750 (150) 29.97 720p/25 1 [5] 1440 [7200] 18.75 [3.75] 750 [150] 74.25 (27.0) 3960 (1440) 750 (750) 25 720p/24 1 [5] 1500 [7500] 18.0 [3.6] 750 [150] 74.25 (27.0) 4125 (1500) 750 (750) 24 720p/23.98 2 3003 8991.0090 750 74.176 (27.0) 4125 (3003) 750 (375) 23.98 1080p/60 1 [5] 400 [2000] 67.5 [13.5] 1125 [225] 148.5 (27.0) 2200 (400) 1125 (1125) 60 1080p/59.94 5 2002 13.4865 1125 148.35 (27.0) 2200 (2002) 1125 (225) 59.94 1080p/50 1 [5] 480 [2400] 56.25 [11.25] 1125 [225] 148.5 (27.0) 2640 (480) 1125 (1125) 50 1080p/30 1 [5] 800 [4000] 33.75 [6.75] 1125 [225] 74.25 (27.0) 2200 (800) 1125 (1125) 30 1080p/29.97 5 4004 6.7433 1125 74.176 (27) 2200 (4004) 1125 (225) 29.97 1080p/25 1 [5] 960 [4800] 28.125 [5.625] 1125 [225] 74.25 (27.0) 2640 (960) 1125 (1125) 25 1080p/24 1 [5] 1000 [5000] 27.0 [5.4] 1125 [225] 74.25 (27.0) 2750 (1000) 1125 (1125) 24 1080p/23.98 1 [5] 1001 [5005] 26.9730 [5.3946] 1125 [225] 74.176 (27.0) 2750 (1001) 1125 (1125) 23.98 For some input reference formats, an alternative set of values for PLL 1 dividers and total lines per frame (REF_LPFM) is also shown in brackets “[ ]”. This alternative set of values may be programmed if a lower PLL 1 phase comparison frequency is desired. The corresponding counter values for REF_LPFM needs to be programmed for proper reference frame and output timing generation. See section Reference Frame Timing. For any output HD format, an alternative set of counter values for total clocks per line (TOF_PPL) and total lines per frame (TOF_LPFM) is shown in parenthesis “( )”. This alternative set of values can be programmed to generate any HD format TOF pulse using the 27 MHz SD_CLK instead of using the native 74.xx or 148.xx MHz HD_CLK. See section HD Format TOF Generation using a 27 MHz TOF Clock. The PLL 1 reference divider value is not the same as the programming value for REF_DIV_SEL. See Table 3. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 9 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Table 1. Input Reference and Output Timing Parameters (1)(2) (continued) INPUT TIMING PARAMETERS OUTPUT TIMING PARAMETERS (2) PLL 1 Reference Divider1 (3) PLL 1 Feedback Divider PLL 1 Phase Comparison Frequency (kHz) Total Lines per Frame Counter Clock Frequency (MHz) Total Clocks per Line Counter Total Lines per Frame Counter Frame Rate (Hz) 1080i/60 1 [5] 800 [4000] 33.75 [6.75] 1125 [225] 74.25 (27.0) 2200 (800) 1125 (1125) 30 1080i/59.94 5 4004 6.7433 1125 74.176 (27.0) 2200 (4004) 1125 (225) 29.97 1080i/50 1 [5] 960 [4800] 28.125 [5.625] 1125 [225] 74.25 (27.0) 2640 (960) 1125 (1125) 25 48 kHz AES sample clock 2 1125 24.0 96 27.0 1125 96 250 Format 10 (1) Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 APPLICATION INFORMATION FUNCTIONAL OVERVIEW The LMH1982 is an analog phase locked loop (PLL) clock generator that can output simultaneous SD and HD video clocks synchronized or “genlocked” to H sync and V sync input reference timing. The LMH1982 features an output Top of Frame (TOF) pulse generator with programmable timing that can also be synchronized to the reference frame. Two reference ports are provided to allow a secondary input to be selected. The clock generator uses a two-stage PLL architecture. The first stage is a VCXO-based PLL (PLL 1) that requires an external 27 MHz VCXO and loop filter. In Genlock mode, PLL 1 can phase lock the VCXO clock to the input reference after programming the PLL divider ratio. The use of a VCXO provides a low phase noise clock source even when the LMH1982 is configured with a low loop bandwidth, which is necessary to attenuate input timing jitter for minimum jitter transfer. The combination of the external VCXO, external loop filter, and programmable PLL parameters can provide flexibility for the system designer to optimize the loop bandwidth and loop response for the application. The second stage consists of three PLLs (PLL 2, 3, 4) with integrated VCOs and loop filters. These PLLs will attempt to continually track the reference VCXO clock phase from PLL 1 regardless of the device mode. The second stage PLLs have pre-configured divider ratios to provide frequency multiplication or translation from the VCXO clock frequency. The VCO PLLs use a high loop bandwidth to assure PLL stability, so the VCXO must provide a stable low-jitter clock reference to ensure optimal output jitter performance. Any unused clock output can be put in Hi-Z mode, which can be useful for reducing power dissipation as well as reducing jitter or phase noise on the active clock output. The TOF pulse can be programmed to indicate the start (top) of frame and even provide format cross-locking. The output format registers should be programmed to specify the output timing (output clocks and TOF pulse), the output timing offset relative to the reference, and the output initialization (alignment) to the reference frame. If unused, the TOF output can also be put in Hi-Z mode. When a loss of reference occurs during genlock, PLL 1 can default to either Free run or Holdover operation. When free run is selected, the output frequency accuracy will be determined by the external bias on the free run control voltage input pin, VC_FREERUN. When Holdover is selected, the loop filter can hold the control voltage to maintain short-term output phase accuracy for a brief period in order to allow the application to select the secondary input reference and re-lock the outputs. These options in combination with proper PLL 1 loop response design can provide flexibility to manage output clock behavior during loss and re-acquisition of the reference. The reference status and PLL lock status flags can provide real-time status indication to the application system. The loss of reference and lock detection thresholds can also be configured. Table 2. LMH1982 PLL and Clock Summary PLL Output Clock Frequency (MHz) Input Reference Divider Ratio (reduced) Output Port PLL 1 H sync Programmable 27 SD_CLK PLL 2 VCXO clock 11/4 or 11/2 74.25 or 148.5 HD_CLK PLL 3 VCXO clock 250/91 or 500/91 74.25/1.001 (74.176) or 148.5/1.001 (148.35) HD_CLK PLL 4 VCXO clock 5/2 67.5 SD_CLK GENERAL INFORMATION For normal operation, the RESET pin must be set high; otherwise, the device cannot be programmed and will not function properly. To reset the control registers to their default values, toggle RESET low for at least 10 µs and then set high. The LMH1982 can be configured by programming the control registers via the I2C interface. The I2C slave addresses are DCh for write sequences and DDh for read sequences. The I2C_ENABLE pin must be set low or tied to GND to allow I2C communication; otherwise, the LMH1982 will not acknowledge read/write sequences. For I2C interface control register map and definitions, refer to section I2C INTERFACE CONTROL REGISTER DEFINITIONS. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 11 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com 148.35 MHz PLL Initialization Sequence The following programming sequence is required to initialize PLL 3 and generate a correct 148.35 MHz output once it is selected as the HD_CLK; otherwise, the clock may have duty cycle errors, frequency errors, and/or high jitter. This PLL initialization sequence must be programmed after switching from another HD clock frequency or Hi-Z mode, as well as after a device reset or power cycle condition. Each programming step below represents a separate write sequence. 1. Program HD_FREQ = 11b and HD_HIZ = 0 (register 08h) to select 148.35 MHz and enable the HD_CLK output. 2. Program a value of 1 to the following register parameters (a single write sequence is valid for this step): – FB_DIV = 1 (register 04h-05h) – TOF_RST = 1 (register 09h-0Ah) – REF_LPFM = 1 (register 0Fh-10h) – EN_TOF_RST = 1 (register 0Ah) 3. Wait at least 2 cycles of the 27 MHz VCXO clock, then program EN_TOF_RST = 0. After this sequence is completed, the 148.35 MHz clock will operate correctly and normal device configuration can resume. All other output clocks do not require this initialization sequence for proper clock operation. Enabling Genlock Mode Upon device power up or reset, the default mode of operation is Free Run mode. To enable Genlock mode, set GNLK = 1 (register 00h). Refer to section Genlock Mode. Output Disturbance While Output Alignment Mode Enabled When the output alignment mode is enabled (EN_TOF_RST = 1) for a longer period than is required by the output initialization sequence, the output signals can be abruptly phase-aligned to the reference on every output frame. Continual alignment can cause excessive phase “jumps” or jitter on the output clock edge coinciding with the TOF pulse; this effect is unavoidable and can be caused by slight differences in the internal counter reset timing for the TOF generation and also large input jitter. The characteristic of the output jitter can also vary in severity from process variation, part variation, and the selected clock reference frequency. This output jitter can only be inhibited by setting EN_TOF_RST = 0 immediately following the output initialization and before the subsequent output frame. Power Supply Sequencing The VDD (3.3V) and DVDD (2.5V) power supply pins are isolated by internal ESD structures that may become forward biased when DVDD is higher than VDD. Exposure to this condition, when prolonged and excessive, can trigger latch-up and/or reduce the reliability of the device. Therefore, the LMH1982 has a recommended power supply sequence. On device power-up, the VDD supply must be brought up before the DVDD supply. On power-down, the DVDD supply must be brought down before the VDD supply. The starting points and ramp rates of the supplies should be considered to determine the relative timing of the power-up and power-down sequences such that DVDD does not exceed VDD +0.3V as shown in the Absolute Maximum Ratings. To minimize the potential for latch-up, a Schottky diode can be externally connected between the DVDD supply (anode) and VDD supply (cathode). If DVDD is brought up first, the Schottky will ensure that VDD is within about 0.3V of DVDD until VDD is brought up. Additionally, the device input pins (except for SDA and SCL inputs) should not be driven prior to power-up due to the same reasons provided above for the power pins. Otherwise, a small series resistor should be used on each input pin to protect the device by limiting the current whenever the internal ESD structures become forward biased. Once both supplies are powered up in the proper sequence, the device has a power on reset sequence that will reset all registers to their default values. 12 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Evaluating the LMH1982 For information about SDI jitter performance using the LMH1982 with the LMH1981 sync separator, please refer to the following application notes: • AN-1893: Demonstrating SMPTE-compliant SDI Output Jitter using the LMH1982 and Virtex-5 GTP Transmitter (SNLA110) • AN-1841: LMH1982 Evaluation Board User Guide (SNVA343) The LMH1982SQEEVAL Evaluation Board can be ordered from Texas Instrument's website. MODES OF OPERATION The mode of operation describes the operation of PLL 1, which can operate in either Free Run mode or Genlock mode depending on the GNLK bit setting. If desired, the GENLOCK input pin can be instead used to control the mode of operation by initially setting I2C_GNLK = 0 (register 00h). Free Run Mode The LMH1982 will enter Free Run mode when GNLK is set to 0. In Free Run mode, the VCXO will be freerunning and independent of the input reference, and the output clocks will maintain phase lock to the VCXO clock reference. Therefore, the output clocks will have the same accuracy as the VCXO clock reference. The LMH1982 provides the designer with the option to define the VCXO's free run control voltage by external biasing of the VC_FREERUN input (pin 1). The analog bias voltage applied to the VC_FREERUN input will be connected to the LPF output (pin 31) though an internal switch (non-buffered, low impedance), as shown in the Functional Block Diagram. The resultant voltage at the LPF output will drive the control input of the VCXO to set its free run output frequency. Thus, the pull range of the VCXO imparts the same pull range on the free run output clocks. If VC_FREERUN is left floating, the VCXO control voltage will be pulled to GND potential as the residual charge stored across the loop filter will discharge through any existing leakage path. Genlock Mode The LMH1982 will enter Genlock mode when GNLK is set to 1. In Genlock mode, PLL 1 can be phase locked to the reference H sync input of the selected port; once the VCXO clock reference is locked and stable, the output clocks and TOF pulse can be aligned and phase locked to the reference. The LMH1982 supports cross-locking, which allows the outputs to be frame-locked to a reference format that is different from the output format. To genlock the outputs, the following programming sequence is suggested: 1. Program the output clock frequency for the desired output format. Refer to section Programming The Output Clock Frequencies. 2. Program the output TOF timing for the desired output format. Refer to section Programming The Output Format Timing. It is required to complete this step for proper output clock initialization (alignment) even if the TOF pulse is not required. 3. Program the PLL 1 divider registers for the input reference format. Refer to section Programming the PLL 1 Dividers. 4. Program GNLK = 1 to enable Genlock mode. See below. 5. Program the output initialization to the desired reference frame. Refer to section Programming The Output Initialization Sequence. NOTE When Genlock mode is enabled, the LMH1982 will attempt to phase lock the PLLs to the input reference regardless of input timing stability. Timing errors or instability on the inputs will cause the PLLs and outputs to also have instability. If output stability is a consideration during periods of input uncertainty, it is suggested to gate off the input signals from the LMH1982 until they are completely stable. Input signal gating can be achieved externally using a discrete or FPGA logic buffer with Hi-Z (tri-state) output and a pull-up or pull-down resistor, depending on the input pulse signal polarity. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 13 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Genlock Mode State Diagram Figure 7 shows the Genlock mode state diagram for different input reference and PLL lock conditions. It also includes Free Run and Holdover states for the loss of reference operation, specified by the HOLDOVER bit (register 00h). Each state indicates the NO_REF and NO_LOCK status flag output conditions. Reference & lock lost FREE RUN NO_REF = 1 NO_LOCK = 1 Reg. 00h[3] = 0 Reference valid & no lock PLL LOCKED NO_REF = 0 NO_LOCK = 0 Locked Lock lost Reference & lock lost HOLDOVER NO_REF = 1 NO_LOCK = 1 Reg. 00h[3] = 1 PLL LOCKING NO_REF = 0 NO_LOCK = 1 Reference valid & no lock Figure 7. Genlock Mode State Diagram Loss of Reference (LOR) By configuring the HOLDOVER bit, the LMH1982 can default to either Free Run or Holdover operation when a loss of reference (LOR) occurs in Genlock mode. If HOLDOVER = 0 when a LOR occurs, the LMH1982 will default to Free run operation (section Free Run during LOR) until a reference is reapplied. If HOLDOVER = 1 when a LOR occurs, the LMH1982 will default to Holdover operation (section Holdover during LOR) until a reference is reapplied. When the input reference is reapplied, the LMH1982 will immediately attempt to phase lock the output clocks to the reference. Free Run during LOR Free Run mode (GNLK = 0) differs from Free Run operation due to LOR in Genlock mode (GNLK = 1) in the following way: • In Free Run mode, the outputs will free run regardless of the presence or loss of reference. • In Genlock mode, the outputs will free run only during LOR; once a reference is present, free run operation will cease as the PLLs will immediately attempt to phase lock the output clocks to the reference. Holdover during LOR In Holdover operation, the LPF output is put into high impedance mode, which allows the loop filter to temporarily hold the residual charge stored across it (i.e. the control voltage) immediately after LOR is indicated by the NO_REF status flag. Holdover operation can help to temporarily sustain the output clock accuracy upon LOR. The duration that the residual control voltage level can be sustained within a tolerable level depends primarily on the charge leakage on the loop filter. A typical VCXO has an input impedance of several tens of kΩ, which will be the dominant leakage path seen by the loop filter. As the leakage current discharges the residual control voltage to GND, the output frequencies of the VCXO and LMH1982 will drift accordingly. If a longer time constant is required, a precision op amp with low input bias current and rail-to-rail input and output (e.g. LMP7701) can be used to buffer the control voltage. The buffer will isolate the relatively low input impedance of the VCXO and reduce the charge leakage on the loop filter during Holdover. 14 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 The output frequency accuracy will degrade as the VCXO accuracy drifts with the decaying control voltage. Moreover, because the H_ERROR setting (register 00h) affects the reference error threshold for LOR indication, a higher setting for H_ERROR may result in reduced output accuracy upon LOR indication compared to when H_ERROR = 0. For more information on programming H_ERROR, see section Programming the Loss of Reference (LOR) Threshold. LPF (PIN 31) LMH1982 CS LMP7701 (OPTIONAL) + - VC CP RS VCXO (PIN 29) 27 MHZ VCXO LOOP FILTER OUT Figure 8. Loop Filter with Optional Op Amp to Isolate VCXO's Low Input Impedance INPUT REFERENCE The LMH1982 features two reference ports (A and B) with H sync and V sync inputs which are used for phase locking the outputs in Genlock mode. The reference port can be selected by programming RSEL (register 00h). If desired, REF_SEL input can be used instead to select the reference port by initially setting I2C_RSEL = 0 (register 00h). The reference signals should be 3.3V LVCMOS signals within the input voltage range specified in Electrical Characteristics . The H sync and V sync input signals may have analog timing, such as from the LMH1981 multiformat analog video sync separator, or digital timing, such as from an FPGA SDI deserializer. Programming the PLL 1 Dividers To genlock the outputs to the reference, it is necessary to phase lock the VCXO clock (PLL 1) to the H sync input signal by programming the PLL dividers. The PLL divider values for each supported input reference format are given in Table 1. The divider values can be determined by reducing the following ratio to its lowest integer factors: fVCXO / fHSYNC = Feedback Divider / Reference Divider where • • • • fVCXO = 27 MHz VCXO frequency fHSYNC = H sync input frequency Feedback Divider = 1 to 8191 (0 is invalid) Reference Divider = 1, 2 or 5 (1) Table 3 shows the selection table with compatible PLL 1 reference divider values to program REF_DIV_SEL (register 03h). The PLL 1 feedback divider value can be directly programmed to FB_DIV (register 04h-05h). Table 3. PLL 1 Reference Divider Selection REF_DIV_SEL Register 03h Reference Divider 0h 2 1h 1 2h 5 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 15 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Some supported input formats in Table 1 have two sets of compatible divider values: reduced dividers and nonreduced dividers. See Examples 2A and 2B below. Because the loop response of PLL 1 is dependent on the feedback divider value, a lower loop bandwidth and phase comparison frequency can be achieved by programming the non-reduced divider set (see LOOP RESPONSE ). Examples: 1) For 1080i/59.94 input reference, the dividers are: • Reference divider = 5 (REF_DIV_SEL = 2h) • Feedback divider = 4004 (FB_DIV = FA4h) 2A) For 1080i/50 input reference, the reduced dividers are: • Reference divider = 1 (REF_DIV_SEL = 1h) • Feedback divider = 960 (FB_DIV = 3C0h) 2B) For 1080i/50 input reference, the non-reduced (alternative) dividers are: • Reference divider = 5 (REF_DIV_SEL = 2h) • Feedback divider = 4800 (FB_DIV = 12C0h) Reference Frame Decoder The LMH1982 features an internal frame decoder to determine the reference frame timing from only the H and V sync input timing, which eliminates an extra input pin for an odd/even field timing. The reference frame timing is required to allow for output frame initialization (output TOF and clock alignment) to the reference frame. To allow for proper frame decoding and subsequent output initialization, the H sync and V sync inputs must comply with the H-V sync timing offset specification, ΔTHV. For interlace formats, the H-V sync timing offset must be within ΔTHV for even fields and be outside ΔTHV for odd fields. Compliance with this specification will ensure the internal frame counters are reset only once per frame. For progressive formats, the H-V timing offset must be within ΔTHV for all frames. Since the LMH1982 was designed for compatibility with the LMH1981 sync separator, its H and V sync pulses will comply with the ΔTHV specification for any input reference format. For digital timing from an FPGA SDI deserializer, the recovered H and V sync pulses may be co-timed and be within ΔTHV for both odd and even fields. This will cause the internal frame counters to reset twice per frame and thus preclude proper frame decoding and output initialization. As a simple work-around, the designer may choose to configure the FPGA to gate the V sync signal, allowing only the even field V pulses and gating off the odd field V pulses. OUTPUT CLOCKS AND TOF The LMH1982 has simultaneous LVDS output SD and HD clocks and an output TOF pulse. For proper output format timing generation and subsequent output initialization, it is highly recommended to follow the programming sequence below: 1. Program the output clock frequencies (section Programming The Output Clock Frequencies). 2. Program the output format timing (section Output Frame Timing). 3. Program the output initialization sequence (section Programming The Output Initialization Sequence). Programming The Output Clock Frequencies The SD clock frequency can be selected from Table 4 and programmed to SD_FREQ (register 08h). PLL 1 and PLL 4 are used to generate the two SD clock rates but only one SD clock can be selected at a time. If the SD_CLK output is not needed, it can be put in Hi-Z mode by setting SD_HIZ = 1 (register 08h). If 27 MHz is selected, the VCXO clock is directly converted from a 3.3V single-ended clock at the VCXO input (pin 29) to an LVDS clock at the SD_CLK output port (pins 23 and 24). If 67.5 MHz is selected, the VCXO clock is used as an input reference for PLL 4 to generate this SD clock frequency. In some FPGA SD-SDI SerDes applications, the 67.5 MHz frequency may be required as an SD reference clock instead of the standard 27 MHz frequency. 16 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Table 4. SD Clock Frequency Selection SD_CLK (MHz) SD_FREQ Register 08h PLL# 27 0 1 67.5 1 4 The HD clock frequency can be selected from Table 5 and programmed to HD_FREQ (register 08h). PLL 2 and PLL 3 are used to generate the four different HD clock rates but only one HD clock can be selected at a time. If the HD_CLK output is not needed, it can be put in Hi-Z mode by setting HD_HIZ = 1 (register 08h). NOTE If 148.35 MHz is selected, it is required to follow the programming sequence described in section 148.35 MHz PLL Initialization Sequence. Table 5. HD Clock Frequency Selection HD_CLK (MHz) HD_FREQ Register 08h PLL# 74.25 0h 2 74.25/1.001 1h 3 148.5 2h 2 148.5/1.001 3h 3 Programming The Output Format Timing When PLL 1 is stable and locked to the input reference, the output format timing should be specified. The functional block diagram for TOF generation and output initialization is shown in Figure 9. For proper output generation and initialization, the reference format and output format timings must be fully and correctly programmed to the output format registers 09h–12h, which specify the following: • Output TOF Clock • Output Frame Timing • Reference Frame Timing • Input-Output Frame Rate Ratio • Output Frame Line Offset Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 17 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com TOF Generation Blocks TOF_HIZ 08h[5] TOF Output Enable and Polarity Select TOF output TOF_CLK 0Ch[5] POL_TOF 0Ah[6] TOF_PPL 0Bh-0Ch TOF_LPFM 0Dh-0Eh COUNTER 5 Output Format Pixels per Line COUNTER 6 Output Format Lines per Frame SEL SD_CLK 0 HD_CLK 1 2:1 MUX TOF Clock Select REF CLK RST4 RST4 (to PLLs 2, 3, 4) TOF/CLK Alignment Blocks FB_DIV 04h-05h VCXO input (pin 29) PLL 1 Feedback Divider RST4 H_FB REF_LPFM 0Fh-10h TOF_RST 09h-0Ah COUNTER 3 Reference Format Lines per Frame COUNTER 4 TOF Reset RST3 RST4 (Output Alignment Signal) RST3 EN_TOF_RST 0Ah[7] TOF_RST 09h-0Ah Selected VREF input COUNTER 1 TOF Reset and Initialization Reference Frame Decoder TOF_OFFSET 11h-12h COUNTER 2 TOF Offset RST2 RST1 TOF_INIT 0Ah[5] 0 REF_SEL input (pin 6) 1 2:1 MUX Init Signal Select H_FB (from PLL 1 Feedback Divider block) SEL PIN 6_OVRD 02h[5] Figure 9. Functional Block Diagram – TOF Generation and Output Initialization Circuitry 18 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Output TOF Clock The TOF pulse is derived from a counter chain, which receives either output clock (SD_CLK or HD_CLK) from a 2:1 MUX block, as shown in Figure 9. The TOF clock from the MUX can be selected by programming TOF_CLK (register 0Ch). To select SD_CLK as the TOF clock, set TOF_CLK = 0; otherwise, set TOF_CLK = 1 to select HD_CLK. The selected TOF clock frequency is determined by the SD_FREQ or HD_FREQ register setting. The TOF output delay time (tD_TOF) for any output format generated from a TOF clock of 27 MHz is specified in Electrical Characteristics. The TOF output delay time for 525i and 1080i/50 generated using 27 MHz and 74.25 MHz, respectively, are shown in Typical Performance Characteristics. The TOF pulse width can be determined by: TOF pulse width = (1 / fTOF_CLK) x TOF_PPL where • • fTOF_CLK = Nominal TOF Clock Frequency TOF_PPL = Output Format Total Pixels per Line (2) Output Frame Timing The TOF pulse is specified by programming TOF_CLK, TOF_PPL (register 0Bh-0Ch) and TOF_LPFM (register 0Dh-0Eh). These registers configure the 2:1 MUX and output pixel and line counters in the TOF Generation blocks shown in Figure 9. The output frame or TOF pulse rate is determined by: TOF rate = fTOF_CLK / (TOF_PPL x TOF_LPFM) where • • • fTOF_CLK = Nominal TOF Clock Frequency TOF_PPL = Output Format Total Pixels per Line TOF_LPFM = Output Format Total Lines per Frame (3) Example: If the output format is 625i, then: TOF rate = 27 MHz / (1728 x 625) = 25 Hz where • • • fTOF_CLK = 27 MHz (SD_FREQ = 0) TOF_PPL = 1728 TOF_LPFM = 625 (4) HD Format TOF Generation using a 27 MHz TOF Clock Any HD format TOF pulse can be generated using either: Option 1) its native HD clock frequency, or Option 2) the 27 MHz SD clock frequency. Using for HD output formats can result in TOF output delay being offset by more than one TOF clock period, even after output initialization. This is because the very short period of the HD native clock yields little timing margin for the reset signals to propagate through the internal logic in Figure 9. For example, using a TOF clock of 148.5 MHz gives less than 6.7 ns (< 1 clock cycle) for all the logic to completely synchronize and ensure proper output initialization. To ensure proper output initialization, is recommended for HD output formats, especially 1080p at 50, 59.94, and 60 Hz. This is because the longer period of the 27 MHz clock provides ample timing margin for the internal logic to reset. The output parameters for programming the HD output formats using the 27 MHz clock are shown in Table 1. To illustrate both TOF clock options, an example is given below for 1080p/59.94, which has a native pixel clock frequency of 148.5/1.001 MHz and frame rate of 60/1.001 Hz: Option 1) 1080p/59.94 TOF generation using 148.35 MHz TOF rate = 148.5/1.001 MHz / (2200 x 1125) = 60/1.001 Hz where • • fTOF_CLK = 148.35 MHz (TOF_CLK = 1, HD_FREQ = 3h) TOF_PPL = 2200 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 19 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 • www.ti.com TOF_LPFM = 1125 (5) Option 2) 1080p/59.94 TOF generation using 27 MHz TOF rate = 27 MHz / 2002 x 225) = 60/1.001 Hz where • • • fTOF_CLK = 27 MHz (TOF_CLK = 0, SD_FREQ = 0) TOF_PPL = 2002 TOF_LPFM = 225 (6) As an example, Figure 10 shows a timing illustration for 1080p/59 TOF and clock outputs for . Once the outputs are initialized, the SD clock and TOF pulse will have a fixed delay, and the SD clock and HD clock will have a fixed timing offset relative to each other. Therefore, the timing offset between the TOF pulse and HD clock, or tTOF-HD, will also be fixed and can be determined by: tTOF-HD = tD_TOF + tD_SD - tD_HD where • • • tD_TOF = TOF Output Delay Time referenced to SD_CLK tD_SD = SD_CLK Output Delay Time tD_HD = HD_CLK Output Delay Time (7) VCXO 27 MHz 3.3 VPP tD_SD = 4 ns SD_CLK 27 MHz 350 mVPP tD_HD = 1.5 ns HD_CLK 148.35 MHz 350 mVPP tD_TOF = 2 ns TOF 59.94 Hz 3.3 VPP tTOF-HD = 4.5 ns Figure 10. Timing Illustration Showing 1080p/59.94 TOF and CLK Output Delays Using Option 2 Reference Frame Timing The reference format frame timing is generated internally and used for resetting the internal counters for output initialization. The reference frame rate should be specified by programming the reference format total lines per frame to REF_LPFM (register 0Fh-10h) as well as the PLL 1 dividers. See Table 1 for programming the parameter values according to each reference format. The reference frame rate is determined by: REF rate = (fVCXO x R_DIV) / (FB_DIV x REF_LPFM) where • • • • fVCXO = 27 MHz Nominal VCXO Clock Frequency R_DIV = Reference Divider (not REF_DIV_SEL) FB_DIV = Feedback Divider REF_LPFM = Reference Format Total Lines per Frame (8) Input-Output Frame Rate Ratio The input-output frame rate ratio is also used for resetting the internal counters for output initialization. The ratio is the Input Frame Rate / Output Frame Rate, in which the numerator and denominator values are reduced to lowest integer factors. The numerator value of this reduced ratio should be programmed to TOF_RST (register 09h-0Ah), and the denominator value is discarded. 20 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Example: If the input reference is 525i with a frame rate of 30/1.001 Hz and the output format is 625i with a frame rate of 25 Hz, then: Frame rate ratio = (30/1.001) / 25 = 1200 / 1001 Therefore, the numerator, 1200, should be programmed to TOF_RST. Output Frame Line Offset The output clock and TOF pulse can be aligned to any line of the reference frame by programming TOF_OFFSET (register 11h-12h) and subsequently programming the output initialization sequence. The line offset value should be directly programmed to TOF_OFFSET to delay or advance the outputs' alignment relative to the decoded reference frame timing (see section Reference Frame Decoder). The TOF_OFFSET value must be greater than zero but less than or equal to the programmed value for REF_LPFM (i.e. 0 < TOF_OFFSET ≤ REF_LPFM). If no line offset is required, then program TOF_OFFSET equal to REF_LPFM instead of zero (invalid value). Example: If an input reference with PAL timing comes from the LMH1981, the H and V pulses will be aligned to within ΔTHV which occurs on line 313 of the reference. In this case, TOF_OFFSET can be set to 312d (138h) so the output frame will align to Line 1 of the PAL reference (start of frame) after the outputs are initialized. This example is illustrated in Figure 11. PAL 500 mV/DIV H sync 2.0V/DIV V sync 2.0V/DIV TOF 2.0V/DIV TOF_OFFSET = 312 100 Ps/DIV Figure 11. PAL Reference and Output TOF Pulse (TOF_OFFSET = 312) NOTE If the alternative set of divider and REF_LPFM values are programmed per (1) for a lower PLL 1 phase comparison frequency, then the output frame cannot be offset to any horizontal line of the reference. Instead, the output frame can only be aligned to the reference in 5 lines steps per 1 step of the TOF_OFFSET value, up to a maximum of reference's total lines per frame divided by 5 (i.e. REF_LPFM). This is because the phase comparison frequency (H_FB signal in Figure 9) will be lower than the H sync input frequency by 5x due to the use of the alternative divider values. Programming The Output Initialization Sequence Before programming the output initialization (alignment) sequence, the following prerequisites must be met: 1. PLL 1 must be stable and locked to the input reference. 2. The desired output clock and TOF pulse timing must be fully specified to the output format registers. (1) For some input reference formats, an alternative set of values for PLL 1 dividers and total lines per frame (REF_LPFM) is also shown in brackets “[ ]”. This alternative set of values may be programmed if a lower PLL 1 phase comparison frequency is desired. The corresponding counter values for REF_LPFM needs to be programmed for proper reference frame and output timing generation. See section Reference Frame Timing. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 21 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com To ensure that the output clock and TOF pulse are properly aligned and subsequently phase locked to the reference frame, the output initialization sequence should be programmed accordingly. During the output frame immediately prior to the frame the initialization is to occur: 1. Set EN_TOF_RST = 1(register 0Ah) to enable output alignment mode. 2. Toggle TOF_INIT (register 0Ah) from 0 to 1 to reset the internal counters. On the next frame, the output clock and TOF pulse will be initialized (aligned) to the reference frame with line offset programmed to TOF_OFFSET. 3. Immediately after the initialization and before the next output frame occurs, clear EN_TOF_RST and TOF_INIT to 0. Otherwise, the output clock will be continually aligned on every output frame while EN_TOF_RST = 1. Continual alignment which may cause excessive jitter on the output clock (from PLL 2, 3, or 4) due to slight differences in the delay paths of the internal logic. This occurrence of excessive clock jitter can be avoided by disabling output alignment mode (EN_TOF_RST = 0) immediately after the initialization sequence. TOF Output Delay Considerations Due to the following conditions, the TOF pulse may be delayed or offset by more than one TOF clock period (tD_TOF > 1 pixel) even after output initialization: 1. The delay paths of the internal logic used to generate and align the TOF pulse is greater than one period of the TOF clock. This can occur for HD format TOF pulses generated using the 148 MHz native pixel clock. For HD format TOF generation, it is recommended to use the 27 MHz SD clock as the TOF clock instead of the native HD pixel clock as shown in section Output Frame Timing. 2. The H sync and/or V sync input pulses have excessive jitter equal to or larger than half of a pixel period of the selected output clock. Input sync jitter less than 3 ns peak-to-peak is recommended. 3. PLL 1 is not completely phase locked or stable when the output initialization is performed. The VCXO clock phase error with respect to the H sync input should less than one period of the selected TOF clock. Output Clock Initialization without TOF For applications that do not require the TOF pulse, it is still necessary to program all output format registers prior to the output initialization sequence. This is because the output initialization circuitry relies on the full and correct specification of the output format. If the TOF output is not needed, it can be put in Hi-Z mode by setting TOF_HIZ = 1 (register 08h). Output Behavior Upon Loss Of Reference After loss of reference (LOR), the LMH1982 will maintain the TOF pulse without the input reference according to the terminal counts of the reference clock; however, output frequency accuracy will be determined by the VCXO, which may be in Free Run or Holdover operation. To disable output alignment to an arbitrary reference frame when the reference is reapplied, set EN_TOF_RST = 0 before the reference returns. After PLL 1 has re-locked to the reference, the outputs can be initialized to the desired reference frame. REFERENCE AND PLL LOCK STATUS The LMH1982 features a reference detector and PLL lock detector that can be used to indicate genlock status of the input reference and device PLLs. Genlock status can be sampled via the NO_REF and NO_LOCK status flag output pins and the REF_VALID, SD_LOCK, and HD_LOCK status bits (register 01h). Both the reference and PLL lock detectors may be programmed for their respective detection thresholds according to the needs of the application system. See Table 7 for a summary of the genlock status bits and status outputs for different conditions. The NO_REF and NO_LOCK outputs are derived from the genlock status bits and given by the following two logic equations: NO_REF = REF_VALID NO_LOCK = (REF_VALID) (SD_LOCK) (HD_LOCK) 22 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Reference Detection In Genlock mode, a valid reference will be indicated by NO_REF = 0 when all the criteria below are met. Otherwise, a loss of reference (LOR) will be indicated by NO_REF = 1. • An H sync signal is applied to the input reference and conforms to one of the standard formats in Table 1. A V sync signal is not used in reference detection. • The PLL divide registers are programmed according to the input reference format. • The control voltage of the VCXO is not within about 500 mV of the GND or VDD supplies. Programming the Loss of Reference (LOR) Threshold The reference detector's error threshold can be programmed to H_ERROR (register 00h), which determines the maximum number of missing H sync pulses before indicating an LOR. The LOR threshold will be the H_ERROR value multiplied by the PLL 1 reference divider value, as shown in Table 6. Table 6. LOR Threshold Selection REF_DIV_SEL Register 03h Reference Divider LOR Threshold 0h 2 2 x H_ERROR 1h 1 1 x H_ERROR 2h 5 5 x H_ERROR If H_ERROR = 0, then the device will react after the first missing pulse. When the LOR threshold is exceeded, the NO_REF output will indicate LOR, and the device will default to either Free Run or Holdover operation for as long as the reference is lost. As the LOR threshold value is increased, the accuracy for counting the actual number of missing H pulses may diminish due to frequency drifting by PLL 1. NOTE If the input reference is missing H pulses periodically, e.g. every vertical interval period, the PLL may not indicate a valid reference nor achieve lock regardless of the H_ERROR value programmed. This is because periodically missing pulses will translate to a lower average frequency than expected. When the average input frequency falls outside of the absolute pull range (APR) of the VCXO, the PLL will not be able to frequency lock to the input reference. PLL Lock Detection In Genlock mode, PLL lock will be indicated by NO_LOCK = 0 when all the criteria below are met. Otherwise, a loss of lock will be indicated by NO_LOCK = 1. • A valid reference is indicated (REF_VALID = 1). • PLL 1 or PLL 4 is phase locked to the input reference (SD_LOCK = 1). • PLL 2 or PLL 3 is phase locked to the VCXO clock reference (HD_LOCK = 1). PLLs 2, 3, and 4 have high loop bandwidths, which allow them to achieve lock quickly and concurrently while PLL 1 achieves lock. Because PLL 1 has a much lower loop bandwidth, it will dictate the overall lock indication time. Programming the PLL Lock Threshold PLL 1's lock detector threshold can be programmed to LOCK_CTRL (register 01h), which determines the maximum phase error between PLL 1's phase detector (PD) inputs before indicating an unlock or lock condition. The PD inputs are the reference signal (H sync input / reference divider) and the feedback signal (VCXO clock / feedback divider). The lock detector will indicate loss of lock when the phase error between the PD inputs is greater than the lock threshold for three consecutive phase comparison periods. Conversely, it will indicate valid lock when the phase error is less than the lock threshold for three consecutive phase comparison periods. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 23 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com A larger value for LOCK_CTRL will yield shorter lock indication time (although not actual lock time) at the expense of higher output phase error when lock is initially indicated, whereas a smaller value will yield the opposite effect. PLL Lock Status Instability It is possible for excessive jitter on the H input to indicate lock instability through the NO_LOCK output, even if the VCXO and output clocks are properly phase locked and no system-level errors are occurring (e.g. bit errors). To reduce the probability of false loss of lock indication or lock status instability, LOCK_CTRL can be increased to improve the lock detector’s ability to tolerate a larger amount of input phase jitter or phase error. This can help to ensure the NO_LOCK output and SD_LOCK bit are stable when the reference signal has large input jitter. Table 7. Summary of Genlock Status Bits and Flag Outputs (1) Mode Control Bits Register 00h Status Bits Register 01h Status Flag Outputs GNLK HOLD-OVER NO_REF 1 (pin 16) NO_LOCK 2 (pin 17) HD_LOCK bit 2 SD_LOCK bit 1 REF_VALID bit 0 Genlock mode, Reference valid, PLLs locking 1 X 0 1 0 0 1 Genlock mode, Reference valid, PLLs locked 1 X 0 0 1 1 1 Genlock mode, Reference lost, Free Run operation 1 0 1 1 1 0 0 Genlock mode, Reference lost, Holdover operation 1 1 1 1 1 0 0 Conditions (1) Status flag output logic equations: 1. NO_REF = REF_VALID 2. NO_LOCK = (REF_VALID) (SD_LOCK) (HD_LOCK) LOOP RESPONSE The overall loop response of the LMH1982 is determined by the design of the VCXO PLL (PLL 1). Because the integrated VCO PLLs use the VCXO clock as the input reference to phase lock the output clocks, the ability of PLL 1 to attenuate the input jitter is critical to output jitter performance, especially low-frequency jitter that occurs at the video line and field rates. The loop response of the LMH1982 can be characterized by PLL 1's loop bandwidth and damping factor. The loop response is primarily determined by the loop filter components and the loop gain. A passive secondorder loop filter consisting of RS, CS, and CP components can provide sufficient input jitter attenuation for most applications, although a higher order passive filter or active filter may also be used. The loop gain is a function of the VCXO gain and programmable PLL parameters. A lower loop bandwidth will provide higher input jitter attenuation (reduced jitter transfer) for improved output jitter performance; however, increased lock time (or settling time) and larger external component values are a couple trade-offs to a lower loop bandwidth. Loop Response Design Equations The following equations can be used to design the loop response of PLL 1. 24 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 The -3 dB loop bandwidth, BW, can be approximated by: BW = ICP1 * RS * KVCO / FB_DIV where (9) ICP1 = Nominal VCXO PLL charge pump current (in amps) programmed by setting ICP1 (register 13h). For example: ICP1 = 250 µA: ICP1 = 08h (default value) ICP1 = 0 µA: ICP1 = 00h (min) ICP1 = 62.5 µA; ICP1 = 02h (practical min) ICP1 = 968.75 µA; ICP1 = 1Fh (max) ICP1 step size = 31.25 µA RS = Nominal value of series resistor (in ohms) KVCO = Nominal 27 MHz VCXO gain (in Hz/V) KVCO = Pull_range * 27 MHz/Vin_range For the recommended VCXO (Mftr: CTS, P/N: 357LB3C027M0000): KVCO = 100 ppm * 27 MHz/(3.0V- 0.3V) = 1000 Hz/V FB_DIV = Feedback Divider value For example: FB_DIV =1716 for NTSC timing Note that this BW approximation does not take into account the effects of the damping factor or the second pole introduced by Cp. At frequencies far above the −3 dB loop bandwidth, the closed-loop frequency response of PLL 1 will roll off at about −40 dB/decade, which is useful attenuating input jitter at frequencies above the loop bandwidth. Near the −3 dB corner frequency, the roll-off characteristic will depend on other factors, such as damping factor and filter order. To prevent output jitter due to the modulation of the VCXO by the PLL’s phase comparison frequency: BW ≤ (27 MHz / FB_DIV) / 20 PLL 1's damping factor, DF, can be approximated by: DF = (RS / 2) * sqrt (ICP1 * CS * KVCO / FB_DIV) where • CS = Nominal value of the series capacitor (in farads) (10) A typical design target for DF is between 0.707 to 1, which can often yield a good trade-off between reference spur attenuation and lock time. DF is related to the phase margin, which is a measure of the PLL stability. A secondary parallel capacitor, CP, is needed to filter the reference spurs introduced by the PLL which may modulate the VCXO input voltage and also cause output jitter. The following relationship should be used to determine CP: CP = CS / 20 (11) The PLL loop gain, K, can be calculated as: K = ICP1 * KVCO / FB_DIV (12) Therefore, the BW and DF can be expressed in terms of K: BW = RS * K DF = (RS/2) * sqrt (CS * K) Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 25 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com Loop Response Optimization Tips The need to support various input reference formats will usually require a diverse range of PLL divider values, which can each yield a different loop response assuming all other PLL parameters are kept the same. Typically, it is desired to design and optimize the loop response across all supported input formats without modification to the loop filter circuit. This requires that the loop gain, K, be kept constant across all supported divider values because K affects both BW and DF equations. To keep a narrow range for K, the ratio (ICP1 / feedback divider) should be kept relatively constant. This can be achieved by programming ICP1, so that ICP1 is scaled with FB_DIV for each supported input format. It is suggested to start designing the loop filter component values from the BW and DF equations with initial assumptions of FB_DIV = 1716 (NTSC) and ICP1 = 250 µA (default setting). Once reasonable component values are achieved under these initial assumptions, it is necessary to check that K can be maintained over the expected range of FB_DIV by adjusting ICP1. The usable current range of ICP1 is limited to a practical minimum of 94 µA (ICP1 = 3d) to a maximum of 969 µA (ICP1 = 31d), which should provide adequate range to maintain a narrow range for K assuming the suggested initial values for FB_DIV and ICP1 were followed. If a narrow range for K cannot be maintained within the usable range of ICP1, then the loop filter design may need to be modified. Some trial-and-error and iterative calculations may be necessary to find an optimal loop filter. In some loop filter designs, the calculated ICP1 current that is required for a target K value may be near or below the practical minimum of the ICP1 current range. In this scenario, it may also be possible to leverage the programmable reference and feedback dividers by scaling up the values in proportion (i.e. same reduced divider ratio). This would allow ICP1 to be scaled up by the same proportion to be within the usable ICP1 current range and maintain the same K value, since ICP1 and FB_DIV would be scaled by the same factor. For example, by scaling the divider values by a factor of 5x, ICP1 can also be scaled up by 5x such that its within the usable current range. This technique of scaling FB_DIV and ICP1 assumes that the input format has an alternative set of compatible divider values as shown in Table 1. Loop Filter Capacitors It is suggested to use tantalum capacitors for CS and CP instead of ceramic capacitors in the PLL loop filter, which is a sensitive analog circuit. Ferroelectric ceramics, such as X7R, X5R, Y5V, Y5U, etc., exhibit piezoelectric effects that generate electrical noise in response to mechanical vibration and shock. This electrical noise can modulate the VCXO control voltage and consequently induce clock jitter at high amplitudes when the board and ceramic components are subjected to vibration or shock. Tantalum capacitors can be used to mitigate this effect. Lock Time Considerations The LMH1982 lock time or settling time is determined by the loop response of PLL 1, which has a much lower loop bandwidth compared to the integrated PLLs used to derive the other output clock frequencies. Generally, the lock time is inversely proportional to the loop bandwidth; however, if the loop response is not designed or programmed for sufficient PLL stability, the lock time may not be predicted from the loop bandwidth alone. Therefore, any parameter that affects the loop response can also affect the overall lock time. One way to reduce lock time is to widen the loop bandwidth by programming a larger or maximum value for ICP1 while PLL 1 is locking; after PLL 1 is locked, ICP1 can be reduced to provide a narrower loop bandwidth while maintaining a reasonable damping factor. VCXO Considerations The recommended VCXO manufacturer part number is CTS 357LB3C027M0000, which has an absolute pull range (APR) of ±50 ppm and operating temperature range of -20°C to +70°C. A VCXO with a tighter APR can provide better output frequency accuracy in Free Run operation; however, the APR must be wider than the worst-case input frequency error in order to achieve phase lock. Free Run Output Jitter The input voltage to VC_FREERUN (pin 1) should have sufficient filtering to minimize noise over the frequency bands of interest (i.e. SMPTE SDI jitter frequency bands) which can cause VCXO input voltage modulation and thus free run output clock jitter. 26 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 I2C INTERFACE PROTOCOL The protocol of the I2C interface begins with the start pulse followed by a byte comprised of a seven-bit slave device address and a read/write bit as the LSB. Therefore, the address of the LMH1982 for write sequences is DCh (1101 1100) and the address for read sequences is DDh (1101 1101). Figure 12, Figure 13, and Figure 14 show a write and read sequence across the I2C interface. Write Sequence The write sequence begins with a start condition, which consists of the master pulling SDA low while SCL is held high. The slave device address is sent next. The address byte is made up of an address of seven bits (7:1) and the read/write bit (0). Bit 0 is low to indicate a write operation. Each byte that is sent is followed by an acknowledge (ACK) bit. When SCL is high the master will release the SDA line. The slave must pull SDA low to acknowledge. The address of the register to be written to is sent next. Following the register address and the ACK bit, the data byte for the register is sent. When more than one data byte is sent, it is automatically incremented into the next address location. See Figure 12. Note that each data byte is followed by an ACK bit. Figure 12. LMH1982 Write Sequence Read Sequence Read sequences are comprised of two I2C transfers. The first is the address access transfer, which consists of a write sequence that transfers only the address to be accessed. The second is the data read transfer, which starts at the address accessed in the first transfer and increments to the next address per data byte read until a stop condition is encountered. The address access transfer shown in Figure 13 consists of a start pulse, the slave device address including the read/write bit (a zero, indicating a write), then its ACK bit. The next byte is the address to be accessed, followed by the ACK bit and the stop bit to indicate the end of the address access transfer. The subsequent read data transfer shown in Figure 14 consists of a start pulse, the slave device address including the read/write bit (a one, indicating a read) and the ACK bit. The next byte is the data read from the initial access address. Subsequent read data bytes will correspond to the next increment address locations. Each data byte is separated from the other data bytes by an ACK bit. SCL SDA A7 S t a r t 1 1 0 1 1 2 1 I C Slave Address $DC 0 0 0 W r I t e A C K A6 A5 A4 A3 A2 A1 A0 0 Address A C K S t o p Figure 13. LMH1982 Read Sequence – Address Access Transfer Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 27 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com SCL SDA D7 S t a r t 1 1 0 1 1 1 0 2 I C Slave Address $DD 1 0 R e a d A C K D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 0 0 A C K Data Byte 1 Data Byte n A C K S t o p Figure 14. LMH1982 Read Sequence – Data Read Transfer I2C Enable Control Pin When the active low input I2C_ENABLE = 0, the LMH1982 will enable I2C communication via its fixed slave address; otherwise, the LMH1982 will not respond. For applications with multiple LMH1982 devices on the same I2C bus, the I2C enable function can be useful for writing data to a specific device(s) and for reading data from an individual device to prevent bus contention. For single chip applications, the I2C_ENABLE input can be tied to GND to keep the I2C interface enabled. I2C INTERFACE CONTROL REGISTER DEFINITIONS Table 8. I2C Interface Control Register Map (1) Register Address Default Data D7 D6 D5 D4 D3 00h A3h GNLK_I2C GNLK RSEL_I2C RSEL HOLDOVER 01h 86h (1) 28 02h 00h RSV RSV 03h 01h RSV RSV RSV 04h B4h 05h 06h 0 0 0 06h 00h RSV RSV RSV RSV 07h 00h RSV RSV RSV RSV 08h 04h RSV RSV TOF_HIZ HD_HIZ 09h 01h 0Ah 00h 0Bh B4h 06h 0Dh 0Dh REF_27 RSV D1 D0 H_ERROR [2:0] LOCK_CTRL [7:3] PIN6_ OVRD 0Ch D2 HD_LOCK SD_LOCK REF_VALID POL_HA POL_VA POL_HB POL_VB RSV RSV REF_DIV_SEL [1:0] FB_DIV [7:0] FB_DIV [12:8] ICP4 [3:0] RSV RSV HD_FREQ [3:2] RSV RSV SD_HIZ SD_FREQ TOF_RST [7:0] EN_TOF_ RST POL_TOF TOF_INIT 0 0 TOF_CLK TOF_RST [12:8] TOF_PPL [7:0] TOF_PPL [12:8] TOF_LPFM [7:0] 0Eh 02h 0Fh 0Dh 0 0 0 10h 02h 11h 00h 12h 00h 0 0 0 13h 88h RSV RSV RSV 14h 88h 0 TOF_LPFM [11:8] REF_LPFM [7:0] 0 0 0 0 REF_LPFM [11:8] TOF_OFFSET [7:0] 0 ICP2 [7:4] TOF_OFFSET [11:8] ICP1 [4:0] ICP3 [3:0] When writing to registers containing reserved bits (RSV), make sure the RSV bits are programmed with their original default data shown in column 2 of Table 8; otherwise, improper device operation may result. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Genlock And Input Reference Control Registers Register 00h Bits 2-0: H Input Error Max Count (H_ERROR) The H_ERROR bits control the reference detector's error threshold, which determines the maximum number of missing H sync pulses before indicating a LOR. See section Programming the Loss of Reference (LOR) Threshold. Bit 3: Holdover on Loss of Reference (HOLDOVER) The HOLDOVER bit controls the operating mode when a loss of reference occurs. See section Loss of Reference (LOR). Bit 4: Reference Select (RSEL) The RSEL bit selects either REF_A or REF_B inputs as the reference to genlock the outputs when I2C_RSEL = 1. RSEL = 0: Select REF_A inputs. RSEL = 1: Select REF_B inputs. If PIN6_OVRD = 1 (register 02h), then reference selection must be controlled by programming RSEL, regardless of I2C_RSEL. When PIN6_OVRD = 0 and I2C_RSEL = 0, then reference selection is controlled using the REF_SEL input pin and the RSEL bit is ignored. Bit 5: Reference Select Control via I2C (I2C_RSEL) By programming I2C_RSEL, reference selection can be controlled either via I2C or the REF_SEL input pin. I2C_RSEL = 1: Control reference selection by programming RSEL. I2C_RSEL = 0: Control reference selection via the REF_SEL input pin. NOTE If PIN6_OVRD = 1, then reference selection must be controlled by programming RSEL regardless of I2C_RSEL. Bit 6: Mode Select (GNLK) The GNLK bit selects the operating mode when I2C_GNLK = 1. See section MODES OF OPERATION. GNLK = 0: Selects Free Run mode. GNLK = 1: Selects Genlock mode. If I2C_GNLK = 0, then the operating mode will be controlled using the GENLOCK input pin and the GNLK bit will be ignored. Bit 7: Mode Select via I2C (I2C_GNLK) By programming I2C_GNLK, mode selection can be controlled either via I2C or the GENLOCK input pin. I2C_GNLK = 1: Control mode selection by programming GNLK. I2C_GNLK = 0: Control mode selection via the GENLOCK input pin. Genlock Status And Lock Control Register Register 01h Bit 0: Reference Status (REF_VALID) REF_VALID is a read-only bit and indicates the presence or loss of reference on the selected reference port in Genlock mode. The NO_REF output flag is an inverted copy of REF_VALID. See section Reference Detection. REF_VALID = 0: Indicates loss of reference (LOR). REF_VALID = 1: Indicates valid reference. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 29 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com In Free Run mode, REF_VALID will be set to 0 to indicate the absence of any input pulses at the selected HREF port. Bit 1: SD Clock PLL Lock Status (SD_LOCK) SD_LOCK is a read-only bit and indicates PLL lock status of the selected SD clock. See section PLL Lock Detection. SD_LOCK = 0: Indicates loss of lock. SD_LOCK = 1: Indicates valid lock. Bit 2: HD Clock PLL Lock Status (HD_LOCK) HD_LOCK is a read-only bit and indicates PLL lock status of the selected HD clock. See section PLL Lock Detection. HD_LOCK = 0: Indicates loss of lock. HD_LOCK = 1: Indicates valid lock. Bits 7-3: Lock Control (LOCK_CTRL) LOCK_CTRL controls the phase error threshold of PLL 1's lock detector. A larger value for LOCK_CTRL will yield shorter lock indication time (although not actual lock time) at the expense of higher output phase error when lock is initially indicated, whereas a smaller value will yield the opposite effect. See section Programming the PLL Lock Threshold. Input Control Register Register 02h Bit 0: VREF_B Input Signal Polarity (POL_VB) This bit should be programmed to match the input signal polarity at the VREF_B input pin. POL_VB = 0: Negative polarity or active low signal. POL_VB = 1: Positive polarity or active high signal. Bit 1: HREF_B Input Signal Polarity (POL_HB) This bit should be programmed to match the input signal polarity at the HREF_B input pin. The positive edge of the output clock will be phase locked to the active edge of the H sync input signal. POL_HB = 0: Negative polarity or active low signal. POL_HB = 1: Positive polarity or active high signal. Bit 2: VREF_A Input Signal Polarity (POL_VA) This bit should be programmed to match the input signal polarity at the VREF_A input pin. POL_VA = 0: Negative polarity or active low signal. POL_VA = 1: Positive polarity or active high signal. Bit 3: HREF_A Input Signal Polarity (POL_HA) This bit should be programmed to match with the input signal polarity at HREF_A input pin. The positive edge of the output clock will be phase locked to the active edge of the H sync input signal. POL_HA = 0: Negative polarity or active low signal. POL_HA = 1: Positive polarity or active high signal. Bit 4: 27 MHz Reference Control (27M_REF) Instead of an H sync signal, a 27 MHz clock signal can be applied to the selected HREF input to phase lock the output clocks. If a 27 MHz clock is used as a reference, then a value of 1 should be programmed to 27M_REF, REF_DIV_SEL, and FB_DIV. 27M_REF = 0: H sync input signal. 30 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 27M_REF = 1: 27 MHz clock input signal. Also, set REF_DIV_SEL =1 and FB_DIV = 1 NOTE Because the loop gain, K, for 27 MHz clock input is much larger than for an H sync input (due to the large difference in FB_DIV), the loop filter design will be necessarily different between the 27 MHz input and H sync inputs. Alternatively, it's possible to use an external counter circuit to divide the 27 MHz clock to a lower frequency (e.g. like H sync) input, so only one loop filter design could support both types of inputs. Bit 5: Pin 6 Override (PIN6_OVRD) The PIN6_OVRD bit can be programmed to override the default reference selection capability on pin 6 and instead use pin 6 as an logic pulse input to initialize or reset the internal counters for output initialization. PIN6_OVRD = 0: Allows a logic level input to be applied to pin 6 for reference selection if RSEL_I2C = 0 (register 00h). If RSEL_I2C = 1, then pin 6 is ignored and reference selection is controlled via I2C; additionally, outputs must be initialized via I2C by programming TOF_INIT and EN_TOF_RST (register 0Ah). PIN6_OVRD = 1: Allows an TOF Init pulse to be applied to pin 6 for output initialization if EN_TOF_RST = 1. If EN_TOF_RST = 0, then any TOF Init pulse received at pin 6 will be ignored. Additionally, reference selection must be controlled via I2C, regardless of I2C_RSEL. Bits 7-6: Reserved (RSV) These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 8. PLL 1 Divider Register Register 03h Bits 1-0: Reference Divider Selection (REF_DIV_SEL) REF_DIV_SEL selects the reference divider value according to the selection table in Table 2. See section Programming the PLL 1 Dividers. The reference divider value is the denominator of PLL 1's divider ratio: Feedback divider value / Reference divider value = 27 MHz / Hsync input frequency The numerator and denominator values of the divider ratio should be reduced to their lowest factors to be compatible with the range of divider values offered by REF_DIV_SEL and FB_DIV. These registers must be programmed correctly to phase lock the 27 MHz VCXO PLL and output clocks to the input reference. See Table 1 for the suggested divider settings for the supported timing formats. Bits 7-3: Reserved (RSV) These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 8. Register 04h Bits 7-0: Feedback Divider (FB_DIV) This register contains the 8 LSBs of FB_DIV. The feedback divider value is the numerator of PLL 1's divider ratio. FB_DIV should be programmed using the feedback divider value after the divide ratio has been reduced to its lowest factors. Refer to the description for register 03h, and see Table 1 for the suggested divider settings for the supported timing format. Register 05h Bits 4-0: Feedback Divider (FB_DIV) This register contains the 5 MSBs of FB_DIV. See the description for register 04h. Bits 7-5: These non-programmable bits contain zeros. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 31 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com PLL 4 Charge Pump Current Control Register Register 06h Bits 3-0: Charge Pump Current Control for PLL 4 (ICP4) ICP4 can be programmed to specify charge pump current for PLL 4, which generates the 67.5 MHz SD clock. NOTE Bit 3 is inverted internally, so the default ICP4 value of 0000b (0h) actually yields an effective value of 1000b (8h), which is the mid-scale setting. The PLL 4 charge pump current increases linearly with the effective value. Reducing the effective value of the charge pump current will lower its loop bandwidth at the expense of reduced PLL stability. An effective value of 0 (ICP4 = 1000b) should not be programmed since this corresponds to 0 µA nominal current and will cause PLL 4 to lose phase lock. Bits 7-4: Reserved (RSV) These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 8. Register 07h Bits 7-0: Reserved (RSV) This register is reserved. If necessary, only write the default data (00h) to register 07h as specified in Table 8. Output Clock And TOF Control Register Register 08h Bit 0: SD Clock Output Frequency Select (SD_FREQ) This bit sets the clock frequency of the SD_CLK output pair. SD_FREQ = 0: Selects 27 MHz from PLL 1. SD_FREQ = 1: Selects 67.5 MHz from PLL 4. Bit 1: SD Clock Output Mode (SD_HIZ) Set the SD_HIZ bit to 1 to put the SD_CLK output pair in high-impedance (Hi-Z) mode; otherwise, the SD_CLK output will be enabled. Bit 3-2: HD Clock Output Frequency Select (HD_FREQ) These bits set the clock frequency of the HD_CLK output pair. HD_FREQ = 0h: Selects 74.25 MHz from PLL 2. HD_FREQ = 1h: Selects 74.176 MHz from PLL 3. HD_FREQ = 2h: Selects 148.5 MHz from PLL 2. HD_FREQ = 3h: Selects 148.35 MHz from PLL 3. NOTE When selecting the 148.35 MHz clock, you must also program the PLL 3 initialization sequence as described in section 148.35 MHz PLL Initialization Sequence. 32 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 Bit 4: HD Clock Output Mode (HD_HIZ) Set the HD_HIZ bit to 1 to put the HD_CLK output pair in high-impedance (Hi-Z) mode; otherwise, the HD_CLK output will be enabled. Bit 5: Top of Frame Output Mode (TOF_HIZ) Set the TOF_HIZ bit to 1 to put the TOF output pin in high-impedance (Hi-Z) mode; otherwise, the output will be enabled. Bits 7-6: Reserved (RSV) These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 8. TOF Configuration Registers Register 09h Bits 7-0: TOF Reset (TOF_RST) This register contains the 8 LSBs of TOF_RST. When PLL 1 is phase locked to the reference, both H sync and V sync inputs are used to reset the frame-based counters used for output TOF generation. The numerator value of the reduced frame rate ratio should be programmed to TOF_RST. See section Input-Output Frame Rate Ratio. Once TOF_RST is programmed, the outputs must be properly initialized by either programming TOF_INIT or otherwise using an external TOF Init pulse (when PIN6_OVRD = 1). Register 0Ah Bits 4-0: TOF Reset (TOF_RST) This register contains the 5 MSBs of TOF_RST. See the description for register 09h. Bit 5: Output Initialization (TOF_INIT) After enabling output alignment mode (EN_TOF_RST = 1), the TOF_INIT bit should be programmed to reset the internal counters and initialize (align) the outputs to the desired reference frame. The output initialization is triggered by programming a positive bit transition (0 to 1) to TOF_INIT. See section Programming The Output Initialization Sequence. Bit 6: TOF Pulse Output Polarity (POL_TOF) This bit should be programmed to the desired TOF pulse polarity at the TOF output. POL_TOF = 0: Negative polarity or active low signal. POL_TOF = 1: Positive polarity or active high signal. Bit 7: Output Alignment Mode (EN_TOF_RST) This bit must be set (EN_TOF_RST = 1) to enable output alignment mode prior to initialization per section Programming The Output Initialization Sequence. It is recommended to clear this bit (EN_TOF_RST = 0) immediately after the output initialization sequence has been programmed to prevent excessive output jitter, as described in section Output Disturbance While Output Alignment Mode Enabled. Register 0Bh Bits 7-0: Total Pixels per Line for the Output Format (TOF_PPL) This register contains the 8 LSBs of TOF_PPL. TOF_PPL should be programmed with total pixels per line for the desired output format. TOF_PPL is used in specifying the output frame rate. This should be specified prior to programming the output initialization sequence. See section Output Frame Timing. Register 0Ch Bits 4-0: MSBs of Total Pixels per Line for the Output Format (TOF_PPL) This register contains the 5 MSBs of TOF_PPL. See the description for register 0Bh. Bit 5: Output Clock Select for Output Top of Frame (TOF_CLK) Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 33 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com This bit should be programmed to select the output TOF clock reference according to the desired output format. The selected TOF clock frequency is used in specifying the output frame rate. Any output format, including HD, can use 27 MHz as the TOF clock to generate its TOF pulse by programming the output counter values corresponding to the 27 MHz SD clock as shown in Table 1. See sections Output TOF Clock and Output Frame Timing. TOF_CLK = 0: Selects the SD_CLK output as the output clock reference, where the SD frequency is set by SD_FREQ. TOF_CLK = 1: Selects the HD_CLK output as the output clock reference. Bit 7-6: These non-programmable bits contain zeros. Register 0Dh Bits 7-0: LSBs of Total Lines per Frame for the Output Format (TOF_LPFM) This register contains the 8 LSBs of TOF_LPFM. TOF_LPFM should be programmed with the total lines per frame for the desired output format. TOF_LPFM is used in specifying the output frame rate. This should be specified prior to programming the output initialization sequence. See section Output Frame Timing. Register 0Eh Bits 3-0: MSBs of Total Lines per Frame for the Output Format (TOF_LPFM) This register contains the 4 MSBs of TOF_LPFM. See the description for register 0Dh. Bit 7-5: These non-programmable bits contain zeros. Register 0Fh Bits 7-0: LSBs of Total Lines per Frame for the Input Reference Format (REF_LPFM) This register contains the 8 LSBs of REF_LPFM. REF_LPFM should be programmed with the total lines per frame for the input reference format. REF_LPFM is used in specifying the reference frame rate. This should be specified prior to programming the output initialization sequence (section Reference Frame Timing). Register 10h Bits 3-0: MSBs of Total Lines per Frame for the Input Reference Format (REF_LPFM) This register contains the 4 MSBs of REF_LPFM. See the description for register 0Fh. Bit 7-4: These non-programmable bits contain zeros. Register 11h Bits 7-0: LSBs of Output Frame Offset (TOF_OFFSET) This register contains the 8 LSBs of TOF_OFFSET. TOF_OFFSET should be programmed with the desired line offset to delay or advance the output timing relative to the reference frame. This should be specified prior to programming the output initialization sequence. See section Output Frame Line Offset. Register 12h Bits 3-0: MSBs of Line Offset for the Output Top of Frame (TOF_OFFSET) This register contains the 4 MSBs of TOF_OFFSET. See the description for register 11h. Bit 7-4: These bits contain zeros (non-programmable) PLL 1, 2, 3 Charge Pump Current Control Registers Register 13h Bits 4-0: PLL 1 Charge Pump Current Control (ICP1) ICP1 can be programmed to specify the charge pump current for PLL 1, which generates 27 MHz from the VCXO output. The PLL 1 charge pump current, or ICP1, is one of the loop gain parameters can be programmed to set and optimize PLL 1's loop response. For more information on setting the loop response, see section LOOP RESPONSE . 34 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 To minimize lock time, using a large or maximum ICP1 can result in faster PLL settling time due to a wider loop bandwidth. Once phase lock has been achieved, using a lower ICP1 (that yields sufficient stability) can provide good input jitter rejection due to a narrower loop bandwidth; this can be helpful to minimize low-frequency input jitter from being transferred to the output clocks. NOTE An ICP1 value ≤ 2 corresponds to an ICP1 current ≤ 62.5 µA. A low ICP1 setting or low damping factor (DF) can cause reduced PLL stability and performance (e.g. wander, loss of lock) due to loop filter charge leakage and other secondary factors; therefore, it is not recommended to use an ICP1 value less than 2d nor use an insufficient DF setting. ICP1 register range = 0 to 31d; 0 to 2d are not recommended ICP1 current = ICP1 x 31.25 µA (nominal current step) Examples: ICP1 = 8d (default) gives ICP1 = 250 µA nominal ICP1 = 31d (max) gives ICP1 = 968.75 µA nominal Bits 7-5: Reserved (RSV) These RSV bits are reserved. When writing to this register, only write the default data to the RSV bits as specified in Table 8. Register 14h Bits 3-0: PLL 3 Charge Pump Current Control (ICP3) ICP3 can be programmed to specify the charge pump current for PLL 3, which generates the 74.176 and 148.35 MHz HD clock outputs. Reducing the value of ICP3 will reduce the PLL 3 charge pump current and lower its loop bandwidth at the expense of reduced PLL stability. An ICP3 value of 0 should not be programmed since this corresponds to 0 µA nominal current, which will cause PLL 3 to lose phase lock or otherwise be unstable. ICP3 register range = 0 to 15d Bit 7-4: PLL 2 Charge Pump Current Control (ICP2) ICP2 can be programmed to specify the charge pump current for PLL 2, which generates the 74.25 and 148.5 MHz HD clock outputs. Reducing the value of ICP2 will reduce the PLL 2 charge pump current and lower its loop bandwidth at the expense of reduced PLL stability. An ICP2 value of 0 should not be programmed since this corresponds to 0 µA nominal current, which will cause PLL 2 to lose phase lock or otherwise be unstable. ICP2 register range = 0 to 15d Reserved Registers Register 15h-1Fh This register is reserved. Do not program any data to these registers. Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 35 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com TYPICAL SYSTEM BLOCK DIAGRAMS LOOP FILTER VC VCXO 27 MHz ANALOG REF. IN LMH1981 MULTI-FORMAT VIDEO SYNC SEPARATOR H sync V sync REF_A TX 27 or 67.5 MHz LMH1982 MULTI-RATE CLOCK GENERATOR H sync OPTIONAL BACK-UP REFERENCE INPUTS V sync GENLOCKED 3G-SDI OUT TOF LPF VCXO TOF SD_CLK FPGA with SerDes TRIPLE-RATE SDI HD_CLK REF_B RX_1 74.25, 74.176, 148.5 or 148.35 MHz ASYNCHRONOUS 3G-SDI IN WRITE/READ DATA and TIMING/CLOCK SIGNALS FRAME BUFFER Figure 15. Analog Reference Genlock for Triple-Rate SDI Video VC LOOP FILTER VCXO 27 MHz H sync OPTIONAL BACK-UP REFERENCE INPUTS V sync REF_A LMH1982 MULTI-RATE CLOCK GENERATOR TX 27 or 67.5 MHz H sync V sync GENLOCKED 3G-SDI OUT TOF LPF VCXO TOF SD_CLK FPGA with SerDes TRIPLE-RATE SDI RX_1 REF_B HD_CLK 74.25, 74.176, 148.5, or 148.35 MHz RECOVERED SYNC TIMING FROM SDI REF. IN ASYNCHRONOUS 3G-SDI IN RX_2 SDI REF. IN WRITE/READ DATA and TIMING/CLOCK SIGNALS FRAME BUFFER Figure 16. SDI Reference Genlock for Triple-Rate SDI Video 36 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 LMH1982 www.ti.com SNLS289C – APRIL 2008 – REVISED MARCH 2013 VC LOOP FILTER VCXO 27 MHz H sync UNUSED INPUTS V sync REF_A LPF VCXO TOF SD_CLK LMH1982 MULTI-RATE CLOCK GENERATOR LOOPED 3G-SDI OUT TOF TX 27 or 67.5 MHz FPGA with SerDes TRIPLE-RATE SDI H sync V sync 3G-SDI IN HD_CLK REF_B RX_1 74.25, 74.176, 148.5 or 148.35 MHz RECOVERED SYNC TIMING FROM 3G-SDI IN Figure 17. Triple-Rate SDI Loop-through LOOP FILTER VC VCXO 27 MHz ANALOG REF. IN (1) H sync LMH1981 MULTI-FORMAT VIDEO SYNC SEPARATOR V sync REF_A LPF VCXO TOF SD_CLK LMH1982 MULTI-RATE CLOCK GENERATOR TOF TX 27 or 67.5 MHz FPGA with SerDes TRIPLE-RATE SDI H sync V sync RX_1 REF_B GENLOCKED 3G-SDI OUT (1,2) or LOOPED 3G-SDI OUT (3) HD_CLK 74.25, 74.176, 148.5 or 148.35 MHz RX_2 3G-SDI IN (1,2,3) SDI REF. IN (2) FRAME BUFFER* RECOVERED SYNC TIMING FROM SDI REF. IN (2) or 3G-SDI IN (3) * FOR GENLOCK APPLICATION (1,2) APPLICATION KEY (1) VIDEO FOR ANALOG GENLOCK (2) VIDEO FOR SDI GENLOCK (3) VIDEO FOR SDI LOOP-THROUGH Figure 18. Combined Genlock or Loop-Through for Triple-Rate SDI Video Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 37 LMH1982 SNLS289C – APRIL 2008 – REVISED MARCH 2013 www.ti.com REVISION HISTORY Changes from Revision B (March 2013) to Revision C • 38 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 37 Submit Documentation Feedback Copyright © 2008–2013, Texas Instruments Incorporated Product Folder Links: LMH1982 PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) (4) LMH1982SQ/NOPB ACTIVE WQFN RTV 32 1000 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 L1982SQ LMH1982SQE/NOPB ACTIVE WQFN RTV 32 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 L1982SQ LMH1982SQX/NOPB ACTIVE WQFN RTV 32 4500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM 0 to 70 L1982SQ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. 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Addendum-Page 1 Samples PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LMH1982SQ/NOPB WQFN RTV 32 LMH1982SQE/NOPB WQFN RTV LMH1982SQX/NOPB WQFN RTV SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 1000 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 32 4500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 21-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LMH1982SQ/NOPB WQFN RTV 32 1000 210.0 185.0 35.0 LMH1982SQE/NOPB WQFN RTV 32 250 210.0 185.0 35.0 LMH1982SQX/NOPB WQFN RTV 32 4500 367.0 367.0 35.0 Pack Materials-Page 2 MECHANICAL DATA RTV0032A SQA32A (Rev B) www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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