TI1 LP3996-Q1 Dual linear regulator with 300 ma and 150 ma outputs and power-on-reset Datasheet

LP3996-Q1
www.ti.com
SNVSA17 – OCTOBER 2013
Dual Linear Regulator with 300 mA and 150 mA Outputs and Power-On-Reset
Check for Samples: LP3996-Q1
FEATURES
DESCRIPTION
•
•
The LP3996-Q1 is a dual low dropout regulator with
power-on-reset circuit. The first regulator can source
150 mA, while the second is capable of sourcing 300
mA and has a power-on-reset function included.
1
2
•
•
•
•
•
2 LDO Outputs with Independent Enable
1.5% Accuracy at Room Temperature, 3% Over
Temperature
Power-On-Reset Function with Adjustable
Delay
Thermal Shutdown Protection
Stable with Ceramic Capacitors
Qualified for Automotive Applications
AEC-Q100 Test Guidance with the Following
Results:
– Device Temperature Grade 1: –40°C to
125°C
– Device HBM ESD Classification Level H2
– Device CDM ESD Classification Level C4B
The LP3996-Q1 provides 1.5% accuracy requiring an
ultra low quiescent current of 35 µA. Separate enable
pins allow each output of the LP3996-Q1 to be shut
down, drawing virtually zero current.
The device is designed to be stable with small
footprint ceramic capacitors down to 1 µF. An
external capacitor may be used to set the POR delay
time as required.
The LP3996-Q1 is available in fixed output voltages
and comes in a 10-pin, 3 mm x 3 mm package.
KEY SPECIFICATIONS
•
•
•
•
•
APPLICATIONS
•
•
•
•
Cellular Handsets
PDAs
Wireless Network Adaptors
Automotive
Input Voltage Range 2.0V to 6.0V
Low Dropout Voltage 210 mV at 300 mA
Ultra-Low IQ (Enabled) 35 µA
Virtually Zero IQ (Disabled) <10 nA
Package Available in Lead-Free Option
10-pin 3 mm x 3 mm
Typical Application Circuit
470 k:
LP3996-Q1
VIN
VOUT1
VOUT1
EN1
EN1
VOUT2
VOUT2
EN2
EN2
POR
POR
CBYP
SET
VIN
1 PF
10 nF
1 PF
GND
1 PF
Sets delay
for POR
1
2
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2013, Texas Instruments Incorporated
LP3996-Q1
SNVSA17 – OCTOBER 2013
www.ti.com
Functional Block Diagram
VOUT1
LDO1
VIN
EN1
LDO2
VOUT2
EN2
POR
POR
CBYP
1 PA
+
-
VREF
GND
SET
Pin Functions
Pin No
2
Symbol
Name and Function
1
VIN
Voltage Supply Input. Connect a 1 µF capacitor between this pin and GND.
2
EN1
Enable Input to Regulator 1. Active high input.
High = On. Low = OFF.
3
EN2
Enable Input to Regulator 2. Active high input.
High = On. Low = OFF.
4
CBYP
5
SET
Set Delay Input. Connect a capacitor between this pin and GND to set the POR delay time. If left open,
there will be no delay.
6
GND
Common Ground pin. Connect externally to exposed pad.
7
N/C
No Connection. Do not connect to any other pin.
8
POR
Power-On Reset Output. Open drain output. Active low indicates under-voltage output on Regulator 2.
A pull-up resistor is required for correct operation.
9
VOUT2
Output of Regulator 2. 300 mA maximum current output. Connect a 1 µF capacitor between this pin
and GND.
10
VOUT1
Output of Regulator 1. 150 mA maximum current output. Connect a 1 µF capacitor between this pin
and GND.
Pad
GND
Internal Voltage Reference Bypass. Connect a 10 nF capacitor from this pin to GND to reduce output
noise and improve line transient and PSRR.
This pin may be left open.
Common Ground. Connect to Pin 6.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
LP3996-Q1
www.ti.com
SNVSA17 – OCTOBER 2013
Connection Diagram
VOUT1
10
VOUT2
9
POR
N/C
GND
8
7
6
GND
1
2
3
4
5
VIN
EN1
EN2
CBYP
SET
Top View
Figure 1. WSON-10 Package
See Package Number DSC0010A
Table 1. Additional Device Information (1)
VOUT1/VOUT2 (V)
1.8/3.3
(1)
ORDER NUMBER
SUPPLIED AS
LP3996QSD-1833/NOPB
1000 Units, Tape-and-Reel
LP3996QSDX-1833/NOPB
4500 Units, Tape-and-Reel
For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
3
LP3996-Q1
SNVSA17 – OCTOBER 2013
www.ti.com
ABSOLUTE MAXIMUM RATINGS (1) (2)
Input Voltage to GND
–0.3V to 6.5V
VOUT1, VOUT2, EN1 and EN2 Voltage to GND
–0.3V to (VIN + 0.3V) with 6.5V
(max)
POR to GND
–0.3V to 6.5V
Junction Temperature (TJ-MAX)
150°C
Lead/Pad Temp (3)
235°C
Storage Temperature
–65°C to 150°C
Continuous Power Dissipation Internally Limited (4)
ESD Rating (5)
(1)
(2)
(3)
(4)
(5)
Human Body Model
2.0kV
Machine Model
200V
All Voltages are with respect to the potential at the GND pin.
Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under
which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured
performance limits and associated test conditions, see the Electrical Characteristics tables.
For detailed soldering specifications and information, please refer to Texas Instruments Application Note AN-1187, Leadless Leadframe
Package.
Internal thermal shutdown circuitry protects the device from permanent damage.
The human body model is 100 pF discharged through a 1.5 kΩ resistor into each pin. The machine model is a 200 pF capacitor
discharged directly into each pin.
RECOMMENDED OPERATING CONDITIONS (1) (2)
Input Voltage
2.0V to 6.0V
EN1, EN2, POR Voltage
0 to (VIN + 0.3V) to 6.0V (max)
Junction Temperature
–40°C to 125°C
Ambient Temperature TA Range (3)
(1)
(2)
(3)
–40°C to 85°C
Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under
which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured
performance limits and associated test conditions, see the Electrical Characteristics tables.
All Voltages are with respect to the potential at the GND pin.
The maximum ambient temperature (TA(max)) is dependant on the maximum operating junction temperature (TJ(max-op) = 125°C), the
maximum power dissipation of the device in the application (PD(max)), and the junction to ambient thermal resistance of the part/package
in the application (θJA), as given by the following equation: TA(max) = TJ(max-op) - (θJA × PD(max)).
THERMAL PROPERTIES (1)
Junction-To-Ambient Thermal Resistance (2)
θJA WSON-10 Package
(1)
(2)
4
55°C/W
Absolute Maximum Ratings are limits beyond which damage can occur. Recommended Operating Conditions are conditions under
which operation of the device is ensured. Recommended Operating Conditions do not imply ensured performance limits. For ensured
performance limits and associated test conditions, see the Electrical Characteristics tables.
Junction-to-ambient thermal resistance is dependant on the application and board layout. In applications where high maximum power
dissipation is possible; special care must be paid to thermal dissipation issues in board design.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
LP3996-Q1
www.ti.com
SNVSA17 – OCTOBER 2013
ELECTRICAL CHARACTERISTICS (1) (2)
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0 µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
SYMBOL
PARAMETER
VIN
Input Voltage
ΔVOUT
Output Voltage Tolerance
VDO
IQ
(1)
(2)
(3)
(4)
CONDITIONS
See (3)
IOUT = 1mA
MIN
MAX
2
6
–2.5
–3.75
+2.5
+3.75
VOUT ≤ 1.5V
–2.75
–4
+2.75
+4
VIN = (VOUT(NOM) + 1.0V) to 6.0V
Load Regulation Error
Quiescent Current
LIMIT
1.5V < VOUT ≤ 3.3V
Line Regulation Error
Dropout Voltage (4)
TYP
0.03
0.3
IOUT = 1 mA to 150 mA
(LDO 1)
85
155
IOUT = 1 mA to 300 mA
(LDO 2)
26
85
IOUT = 1 mA to 150 mA
(LDO 1)
110
220
IOUT = 1 mA to 300 mA
(LDO 2)
210
550
LDO 1 ON, LDO 2 ON
IOUT1= IOUT2 = 0 mA
35
100
LDO 1 ON, LDO 2 OFF
IOUT1 = 150 mA
45
110
LDO 1 OFF, LDO 2 ON
IOUT2 = 300 mA
45
110
LDO 1 ON, LDO 2 ON
IOUT1 = 150 mA, IOUT2 = 300 mA
70
170
VEN1 = VEN2 = 0.4V
0.5
10
UNITS
V
%
%/V
µV/mA
mV
µA
nA
All Voltages are with respect to the potential at the GND pin.
Min and Max limits are specified by design, test or statistical analysis. Typical numbers are not ensured, but do represent the most likely
norm.
VIN(MIN) = VOUT(NOM) +0.5V, or 2.0V, whichever is higher.
Dropout voltage is voltage difference between input and output at which the output voltage drops to 100 mV below its nominal value.
This parameter only for output voltages above 2.0V
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
5
LP3996-Q1
SNVSA17 – OCTOBER 2013
www.ti.com
ELECTRICAL CHARACTERISTICS(1)(2) (continued)
Unless otherwise noted, VEN = 950 mV, VIN = VOUT + 1.0V, or 2.0V, whichever is higher, where VOUT is the higher of VOUT1 and
VOUT2. CIN = 1 µF, IOUT = 1 mA, COUT1 = COUT2 = 1.0 µF.
Typical values and limits appearing in normal type apply for TA = 25°C. Limits appearing in boldface type apply over the full
junction temperature range for operation, −40 to +125°C.
SYMBOL
ISC
PARAMETER
Short Circuit Current Limit
IOUT
Maximum Output Current
Power Supply Rejection Ratio (5)
PSRR
Output noise Voltage (5)
en
TSHUTDOWN
Thermal Shutdown
CONDITIONS
TYP
LIMIT
MIN
MAX
LDO 1
420
750
LDO 2
550
840
LDO 1
150
LDO 2
300
f = 1kHz, IOUT =
1mA to 150 mA
CBYP = 10 nF
LDO1
58
LDO2
70
f = 20 kHz, IOUT
= 1mA to 150
mA
CBYP = 10 nF
LDO1
45
LDO2
60
BW = 10 Hz to
100kHz
CBYP = 10 nF
VOUT = 0.8V
36
VOUT = 3.3V
75
UNITS
mA
mA
dB
µVRMS
Temperature
160
Hysteresis
20
VEN = 0.0V
0.005
0.1
2
5
°C
Enable Control Characteristics
IEN
Input Current at VEN1 or VEN2
VEN = 6V
VIL
Low Input Threshold at VEN1 or
VEN2
VIH
High Input Threshold at VEN1 or
VEN2
0.4
0.95
µA
V
V
POR Output Characteristics
VTH
Low Threshold % 0f VOUT2 (NOM)
Flag ON
High Threshold % 0f VOUT2 (NOM)
Flag OFF
88
IPOR
Leakage Current
Flag OFF, VPOR = 6.5V
30
nA
VOL
Flag Output Low Voltage
ISINK = 250 µA
20
mV
µs
96
%
Timing Characteristics
TON
Turn On Time (5)
To 95% Level
CBYP = 10 nF
300
Transient
Response
Line Transient Response
|δVOUT| (5)
Trise = Tfall = 10 µs
δVIN = 1VCBYP = 10 nF
20
Load Transient Response
|δVOUT| (5)
Trise = Tfall = 1
µs
LDO 1
IOUT = 1 mA to 150
mA
175
LDO 2
IOUT = 1 mA to 300
mA
150
mV
(pk - pk)
SET Input Characteristics
ISET
SET Pin Current Source
VSET = 0V
1.3
µA
VTH(SET)
SET Pin Threshold Voltage
POR = High
1.25
V
(5)
6
This electrical specification is specified by design.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
LP3996-Q1
www.ti.com
SNVSA17 – OCTOBER 2013
OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS
SYMBOL
COUT
PARAMETER
CONDITIONS
NOM
Capacitance (1)
Output Capacitance
1.0
ESR
(1)
LIMIT
MIN
MAX
UNITS
0.7
5
µF
500
mΩ
The Capacitor tolerance should be 30% or better over temperature. The full operating conditions for the application should be
considered when selecting a suitable capacitor to ensure that the minimum value of capacitance is always met. Recommended
capacitor is X7R. However, depending on the application, X5R, Y5V and Z5U can also be used. (See Capacitor sections in
APPLICATION HINTS.)
Transient Test Conditions
Figure 2. PSRR Input Signal
VOUT
tr
VOUT ± tolerance
tr
VIN
trise = tfall = 10 Ps
Line Step = 1V
ILOAD(LDO1) = 150 mA
ILOAD(LDO2) = 300 mA
VOUT(NOM) + 1V
Figure 3. Line Transient Input Test Signal
VOUT
tr
VOUT ± tolerance
tr
VIN
Load Step LDO1 = 1 mA to 150 mA
Load Step LDO2 = 1 mA to 300 mA
Load Rise Time = Fall = 1 Ps
Figure 4. Load Transient Input Signal
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
7
LP3996-Q1
SNVSA17 – OCTOBER 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN. Typical Performance Characteristics are identical to
the commercial grade product and are reproduced here as information only.
8
Output Voltage Change vs Temperature
Ground Current vs Load Current, LDO1
Figure 5.
Figure 6.
Ground Current vs Load Current, LDO2
Ground Current vs VIN. ILOAD = 1mA
Figure 7.
Figure 8.
Dropout Voltage vs ILOAD, LDO1
Dropout Voltage vs ILOAD, LDO2
Figure 9.
Figure 10.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
LP3996-Q1
www.ti.com
SNVSA17 – OCTOBER 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN. Typical Performance Characteristics are identical to
the commercial grade product and are reproduced here as information only.
Short Circuit Current, LDO1
Short Circuit Current, LDO2
Figure 11.
Figure 12.
Power Supply Rejection Ratio, LDO1
Power Supply Rejection Ratio, LDO2
Figure 13.
Figure 14.
Enable Start-up Time, CBYP=0
Enable Start-up Time, CBYP=10nF
Figure 15.
Figure 16.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
9
LP3996-Q1
SNVSA17 – OCTOBER 2013
www.ti.com
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN. Typical Performance Characteristics are identical to
the commercial grade product and are reproduced here as information only.
10
Line Transient, CBYP=10nF
Line Transient, CBYP=0
Figure 17.
Figure 18.
Load Transient, LDO1
Load Transient, LDO2
Figure 19.
Figure 20.
Noise Density LDO1
Noise Density, LDO2
Figure 21.
Figure 22.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
LP3996-Q1
www.ti.com
SNVSA17 – OCTOBER 2013
TYPICAL PERFORMANCE CHARACTERISTICS (continued)
Unless otherwise specified, CIN = 1.0 µF Ceramic, COUT1 = COUT2 = 1.0 µF Ceramic, CBYP = 10 nF, VIN = VOUT2(NOM) + 1.0V, TA
= 25°C, VOUT1(NOM) = 3.3V, VOUT2(NOM) = 3.3V, Enable pins are tied to VIN. Typical Performance Characteristics are identical to
the commercial grade product and are reproduced here as information only.
Power-on-Reset Start-up Operation
Power-on-Reset Shutdown Operation
Figure 23.
Figure 24.
POR Delay Time
Figure 25.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
11
LP3996-Q1
SNVSA17 – OCTOBER 2013
www.ti.com
APPLICATION HINTS
Operation Description
The LP3996-Q1 is a low quiescent current, power management IC, designed specifically for portable applications
requiring minimum board space and smallest components. The LP3996-Q1 contains two independently
selectable LDOs. The first is capable of sourcing 150 mA at factory-programmed outputs between 0.8V and
3.3V. The second can source 300 mA at factory-programmed output voltages of 0.8V to 3.3V. In addition, LDO2
contains a power-good flag circuit which monitors the output voltage and indicates when it is within 8% of its
nominal value. The flag will also act as a power-on-reset signal and, by adding an external capacitor, a delay
may be programmed for the POR output.
Input Capacitor
An input capacitor is required for stability. It is recommended that a 1.0 µF capacitor be connected between the
LP3996-Q1 input pin and ground (this capacitance value may be increased without limit).
This capacitor must be located a distance of not more than 1 cm from the input pin and returned to a clean
analog ground. Any good quality ceramic, tantalum, or film capacitor may be used at the input.
Important: Tantalum capacitors can suffer catastrophic failures due to surge current when connected to a lowimpedance source of power (like a battery or a very large capacitor). If a tantalum capacitor is used at the input,
it must be ensured by the manufacturer to have a surge current rating sufficient for the application.
There are no requirements for the ESR (Equivalent Series Resistance) on the input capacitor, but tolerance and
temperature coefficient must be considered when selecting the capacitor to ensure the capacitance will remain
approximately 1.0 µF over the entire operating temperature range.
Output Capacitor
The LP3996-Q1 is designed specifically to work with very small ceramic output capacitors. A 1.0 µF ceramic
capacitor (temperature types Z5U, Y5V or X7R) with ESR between 5 mΩ to 500 mΩ, is suitable in the LP3996Q1 application circuit.
For this device the output capacitor should be connected between the VOUT pin and ground.
It is also possible to use tantalum or film capacitors at the device output, COUT (or VOUT), but these are not as
attractive for reasons of size and cost (see Capacitor Characteristics).
The output capacitor must meet the requirement for the minimum value of capacitance and also have an ESR
value that is within the range 5 mΩ to 500 mΩ for stability.
No-Load Stability
The LP3996-Q1 will remain stable and in regulation with no external load. This is an important consideration in
some circuits, for example CMOS RAM keep-alive applications.
12
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
LP3996-Q1
www.ti.com
SNVSA17 – OCTOBER 2013
Capacitor Characteristics
The LP3996-Q1 is designed to work with ceramic capacitors on the output to take advantage of the benefits they
offer. For capacitance values in the range of 0.47 µF to 4.7 µF, ceramic capacitors are the smallest and least
expensive, and have the lowest ESR values, thus making them best for eliminating high frequency noise. The
ESR of a typical 1.0 µF ceramic capacitor is in the range of 20 mΩ to 40 mΩ, which easily meets the ESR
requirement for stability for the LP3996-Q1.
For both input and output capacitors, careful interpretation of the capacitor specification is required to ensure
correct device operation. The capacitor value can change greatly, depending on the operating conditions and
capacitor type.
CAP VALUE (% OF NOM. 1 uF)
In particular, the output capacitor selection should take account of all the capacitor parameters, to ensure that the
specification is met within the application. The capacitance can vary with DC bias conditions as well as
temperature and frequency of operation. Capacitor values will also show some decrease over time due to aging.
The capacitor parameters are also dependant on the particular case size, with smaller sizes giving poorer
performance figures in general. As an example, Figure 26 shows a typical graph comparing different capacitor
case sizes in a Capacitance vs. DC Bias plot. As shown in the graph, increasing the DC Bias condition can result
in the capacitance value falling below the minimum value given in the recommended capacitor specifications
table (0.7 µF in this case). Note that the graph shows the capacitance out of spec for the 0402 case size
capacitor at higher bias voltages. It is therefore recommended that the capacitor manufacturers’ specifications for
the nominal value capacitor are consulted for all conditions, as some capacitor sizes (that is, 0402) may not be
suitable in the actual application.
0603, 10V, X5R
100%
80%
60%
0402, 6.3V, X5R
40%_
20%
_
0
1.0
2.0
_
3.0
_
4.0
_
5.0
_
DC BIAS (V)
Figure 26. Graph Showing a Typical Variation in Capacitance vs DC Bias
The ceramic capacitor’s capacitance can vary with temperature. The capacitor type X7R, which operates over a
temperature range of –55°C to +125°C, will only vary the capacitance to within ±15%. The capacitor type X5R
has a similar tolerance over a reduced temperature range of –55°C to +85°C. Many large value ceramic
capacitors larger than 1 µF are manufactured with Z5U or Y5V temperature characteristics. Their capacitance
can drop by more than 50% as the temperature varies from 25°C to 85°C. Therefore X7R is recommended over
Z5U and Y5V in applications where the ambient temperature will change significantly above or below 25°C.
Tantalum capacitors are less desirable than ceramic for use as output capacitors because they are more
expensive when comparing equivalent capacitance and voltage ratings in the 0.47 µF to 4.7 µF range.
Another important consideration is that tantalum capacitors have higher ESR values than equivalent size
ceramics. This means that while it may be possible to find a tantalum capacitor with an ESR value within the
stable range, it would have to be larger in capacitance (which means bigger and more costly) than a ceramic
capacitor with the same ESR value. It should also be noted that the ESR of a typical tantalum will increase about
2:1 as the temperature goes from 25°C down to –40°C, so some guard band must be allowed.
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
13
LP3996-Q1
SNVSA17 – OCTOBER 2013
www.ti.com
Enable Control
The LP3996-Q1 features active high enable pins for each regulator, EN1 and EN2, which turns the
corresponding LDO off when pulled low. The device outputs are enabled when the enable lines are set to high.
When not enabled the regulator output is off and the device typically consumes 2 nA.
If the application does not require the Enable switching feature, one or both enable pins should be tied to VIN to
keep the regulator output permanently on.
To ensure proper operation, the signal source used to drive the enable inputs must be able to swing above and
below the specified turn-on / off voltage thresholds listed in the Electrical Characteristics section under VIL and
VIH.
Power-On-Reset
The POR pin is an open-drain output which will be set to Low whenever the output of LDO2 falls out of regulation
to approximately 90% of its nominal value. An external pull-up resistor, connected to VOUT or VIN, is required on
this pin. During start-up, or whenever a fault condition is removed, the POR flag will return to the High state after
the output reaches approximately 96% of its nominal value. By connecting a capacitor from the SET pin to GND,
a delay to the rising condition of the POR flag may be introduced. The delayed signal may then be used as a
Power-on-Reset for a microprocessor within the user's application.
The duration of the delay is determined by the time to charge the delay capacitor to a threshold voltage of 1.25V
at 1.2 µA from the SET pin as in the formula below.
VTH(SET) X CSET
tDELAY =
ISET
(1)
A 0.1 µF capacitor will introduce a delay of approximately 100 ms.
Bypass Capacitor
The internal voltage reference circuit of the LP3996-Q1 is connected to the CBYP pin via a high value internal
resistor. An external capacitor, connected to this pin, forms a low-pass filter which reduces the noise level on
both outputs of the device. There is also some improvement in PSSR and line transient performance. Internal
circuitry ensures rapid charging of the CBYP capacitor during start-up. A 10 nF, high quality ceramic capacitor
with either NPO or COG dielectric is recommended due to their low leakage characteristics and low noise
performance.
Safe Area of Operation
Due consideration should be given to operating conditions to avoid excessive thermal dissipation of the LP3996Q1 or triggering its thermal shutdown circuit. When both outputs are enabled, the total power dissipation will be
PD(LDO1) + PD(LDO2) Where PD = (VIN - VOUT) x IOUT for each LDO.
In general, device options which have a large difference in output voltage will dissipate more power when both
outputs are enabled, due to the input voltage required for the higher output voltage LDO. In such cases,
especially at elevated ambient temperature, it may not be possible to operate both outputs at maximum current
at the same time.
14
Submit Documentation Feedback
Copyright © 2013, Texas Instruments Incorporated
Product Folder Links: LP3996-Q1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
LP3996QSD-1833/NOPB
ACTIVE
WSON
DSC
10
1000
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L275B
LP3996QSDX-1833/NOPB
ACTIVE
WSON
DSC
10
4500
Green (RoHS
& no Sb/Br)
CU SN
Level-1-260C-UNLIM
-40 to 125
L275B
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
18-Oct-2013
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF LP3996-Q1 :
• Catalog: LP3996
NOTE: Qualified Version Definitions:
• Catalog - TI's standard catalog product
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
LP3996QSD-1833/NOPB
LP3996QSDX-1833/NOP
B
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
WSON
DSC
10
1000
178.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
WSON
DSC
10
4500
330.0
12.4
3.3
3.3
1.0
8.0
12.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
12-Oct-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
LP3996QSD-1833/NOPB
WSON
DSC
10
1000
210.0
185.0
35.0
LP3996QSDX-1833/NOPB
WSON
DSC
10
4500
210.0
185.0
35.0
Pack Materials-Page 2
IMPORTANT NOTICE
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale
supplied at the time of order acknowledgment.
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily
performed.
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide
adequate design and operating safeguards.
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the
third party, or a license from TI under the patents or other intellectual property of TI.
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered
documentation. Information of third parties may be subject to additional restrictions.
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.
TI is not responsible or liable for any such statements.
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use
of any TI components in safety-critical applications.
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and
requirements. Nonetheless, such components are subject to these terms.
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties
have executed a special agreement specifically governing such use.
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and
regulatory requirements in connection with such use.
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.
Products
Applications
Audio
www.ti.com/audio
Automotive and Transportation
www.ti.com/automotive
Amplifiers
amplifier.ti.com
Communications and Telecom
www.ti.com/communications
Data Converters
dataconverter.ti.com
Computers and Peripherals
www.ti.com/computers
DLP® Products
www.dlp.com
Consumer Electronics
www.ti.com/consumer-apps
DSP
dsp.ti.com
Energy and Lighting
www.ti.com/energy
Clocks and Timers
www.ti.com/clocks
Industrial
www.ti.com/industrial
Interface
interface.ti.com
Medical
www.ti.com/medical
Logic
logic.ti.com
Security
www.ti.com/security
Power Mgmt
power.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Microcontrollers
microcontroller.ti.com
Video and Imaging
www.ti.com/video
RFID
www.ti-rfid.com
OMAP Applications Processors
www.ti.com/omap
TI E2E Community
e2e.ti.com
Wireless Connectivity
www.ti.com/wirelessconnectivity
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2013, Texas Instruments Incorporated