ON LC898124EP1XC Optical image stabilization (ois) / open-auto focus (af) controller & driver Datasheet

LC898124EP1XC
Advance Information
Optical Image Stabilization (OIS) /
Open-Auto Focus (AF)
Controller & Driver
integrating an on-chip 32-bit DSP
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LC898124EP1XC is a system LSI integrating an on-chip 32-bit DSP,
a EEPROM and peripherals including analog circuits for Optical
Image Stabilization (OIS) / Auto Focus (AF) control and constant
current drivers.
Features
 On-chip 32-bit DSP
 Built-in software for digital servo filter
 Built-in software for Gyro filter
WLCSP27, 3.89x1.30, 0.4P
 Memory
 EEPROM
 ROM
 SRAM
 Peripherals
 AD converter : input 4 ch
 DA converter : Output 2 ch
 2-wire Serial I/F circuit (with clock stretch function)
 Hall Bias circuit x2 ch
 Hall Amp x2 ch
 OSC (Oscillator)
 LDO (Low Drop-Out regulator)
 Digital Gyro I/F for various types of gyro (SPI Bus)
 Interrupt I/F

Driver
 OIS
Constant current linear driver (x2 ch, Ifull = 160 mA)
 OP-AF(bidirection)
Constant current linear driver (x1 ch, Ifull = 130 mA)
 Package
 WLCSP27 (3.89 mm x 1.30 mm), thickness Max. 0.33 mm, with back coat
 Pb-Free and Halogen Free compliance
 Power supply voltage
 AD/DA/VGA/LDO/OSC
 Driver
: AVDD30 = 2.6 V to 3.3 V
: VM = 2.6 V to 3.3 V
This document contains information on a new product. Specifications and information
herein are subject to change without notice.
ORDERING INFORMATION
See detailed ordering and shipping information on page 10 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
July 2016 - Rev. P1
1
Publication Order Number :
LC898124EP1XC/D
LC898124EP1XC
Block Diagram
LPDSP32
DAC
AOUT0 AOUT1
Work RAM: DMA0
DMA0
Program
Data
DAC
IOUT0 IOUT1
Program ROM
HLXBO
Work RAM: DMA1
Work RAM: DMB
HLYBO
DMA1
Program RAM
DMB
DMIO
1.8V
E2PROM I/F
Hall
X
I2C
(slave)
SCL
SCL
SDA
SDA
HOST
CPU
(master)
OPINPX
OPINMX
EEPROM
SCL2(NC)
SDA2(NC)
DAC Ctrl
Hall
Y
OPINPY
OPINMY
DGSSB
DGSCLK
SPI
(master)
(D-Gyro I/F)
Port
DGDATA
EIRQ
LDO
INT
Digital
Gyro
(slave)
CMOS
Sensor
MON1
OUT1
OUT2
OUT3
Current Linear
Ctrl
ADC Ctrl
OUT4
H-Bridge
Driver
OUT5
OUT6
ADC
MON1
SW0
SW1
SW2
MON2
SW3
AIN0
VM
PGND
System Ctrl
AIN1
AIN2
AIN3
SW4
POR
OSC
AVDD30
AVSS
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2
Clock Divider
LDO
LDOPO(DVDD15)
LC898124EP1XC
Application Diagram
Camera Module
Lens
Hall
Sensor
VCM
OIS/OP-AF
Actuator
Position
(OIS)
OIS/AF Driver
EEPROM
I 2C
AP/ISP
CMOS
Sensor
LC898124EP1XC
Digital
Gyro
SPI
Digital
Gyro
Package Dimensions
unit : mm
WLCSP27, 3.89x1.30, 0.4P
CASE 567NJ
ISSUE O
D
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
A B
PIN A1
REFERENCE
E
DIE
COAT
0.05 C
2X
0.05 C
2X
TOP VIEW
DETAIL A
DIM
A
A1
b
D
E
e
MILLIMETERS
MIN
MAX
0.33
0.04 REF
0.12
0.22
3.89 BSC
1.30 BSC
0.40 BSC
DETAIL A
A
0.13 C
RECOMMENDED
SOLDERING FOOTPRINT*
0.08 C
27X
A1
SIDE VIEW
NOTE 3
e
b
C
e
0.05 C A B
0.03 C
C
SEATING
PLANE
A1
PACKAGE
OUTLINE
0.40
PITCH
B
27X
0.17
0.40
PITCH
A
1
2
3
4
5
6
7
8
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
9
BOTTOM VIEW
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3
LC898124EP1XC
Pin Assign
bottom view
C
OUT4
OUT3
OUT2
OUT1
OPINPX
HLXBO
MON2
EIRQ
DGDATA
B
VM
PGND
OPINPY
OPINMY
OPINMX
HLYBO
SDA2
SDA
DGSCLK
A
OUT5
OUT6
AVSS
AVDD30
LDPO
MON1
SCL2
SCL
DGSSB
1
2
3
4
5
6
7
8
9
Driver
VDD/VSS
Internal VDD Output
1.8 V I/O
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LC898124EP1XC
Pin Description
No.
Pin
I/O
I/O Spec
Primary Function
Sub Functions
2-wire serial Data
Interrupt Input
2-wire serial Clock
1
MON1
B
Servo Monitor Analog In/Out
2
MON2
B
3
SCL
B
OD
4
SDA
B
OD
5
SDA2
B
Servo Monitor Analog In/Out
2-wire serial HOST I/F Clock
Slave
2-wire serial HOST I/F Data
Slave
NC
6
SCL2
B
NC
7
DGSSB
B
Digital Gyro Data I/F Chip
Select Out (3/4-wire Master)
3/4-wie I/F Chip Select In
(Read only)
8
DGSCLK
B
Digital Gyro Data I/F Clock
Out (3/4-wire Master)
9
EIRQ
B
DGDATA
B
3/4-wire I/F Clock In
(Read only)
Digital Gyro Data I/F Data
In (4-wire Master)
Digital Gyro Data I/F Data
Out (4-wire Master)
10
OD
Init
Z
Z
Z
Z
Z
Z
Interrupt Input
Digital Gyro Data I/F Data
(3-wire Master)
Z
Z
Z
Z
3/4-wire I/F Data In (Read only)
11
HLXBO
O
OIS Hall X Bias Output
Z
12
HLYBO
O
OIS Hall Y Bias Output
Z
13
OPINMX
I
OIS Hall X Opamp Input Minus
Z
14
OPINPX
I
OIS Hall X Opamp Input Plus
-
15
OPINMY
I
OIS Hall Y Opamp Input Minus
-
16
OPINPY
I
OIS Hall Y Opamp Input Plus
-
17
OUT1
O
OIS Driver Output
Z
18
OUT2
O
OIS Driver Output
Z
19
OUT3
O
OIS Driver Output
Z
20
OUT4
O
OIS Driver Output
Z
21
OUT5
O
Open-AF Driver Output
Z
22
OUT6
O
Open-AF Driver Output
Z
23
AVDD30
P
Analog Power (2.6 V to 3.3 V)
-
24
AVSS
P
Analog GND
-
25
VM
P
Driver Power (2.6 V to 3.3 V)
-
26
PGND
P
Driver GND
27
LDPO
P
Internal LDO Power Output
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LC898124EP1XC
Electrical Characteristics
Absolute Maximum Rating at AVSS = 0 V, PGND = 0 V (Note 1)
Parameter
Power supply voltage
Input / Output voltage
Input voltage
Storage temperature
Symbol
VAD30 max
VM max
VAI30,VAO30
VMI30,VMO30
Conditions
Ta  25C
Ta  25C
Ta  25C
Ta  25C
V18*1
Ta  25C
Ratings
0.3 to +4.6
0.3 to +4.6
0.3 to VAD30+0.3
0.3 to VM30+0.3
Tstg
Topr1
Operating temperature
Topr2
Unit
V
V
V
V
0.3 to +1.98
V
55 to +125
C
30 to +85
C
30 to +70
C
Read for EEPROM
Program &Erase for
EEPROM
*1:DGSSB, DGSCLK, DGDATA, EIRQ
Note 1 : Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are
exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
Allowable Operating Ratings at Ta = 30 to 85C, AVSS = 0 V, PGND = 0 V (Note 2)
3.0V Power Supply (AVDD30)
Parameter
Power supply voltage
Input voltage range
Symbol
VAD30
VINA
Min
2.6
0
Typ
2.8
-
Max
3.3
VAD30
Unit
V
V
3.0V Power Supply (VM)
Parameter
Power supply voltage
Input voltage range
Symbol
VM30
VINM
Min
2.6
0
Typ
2.8
-
Max
3.3
VM30
Unit
V
V
Note 2 : Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended
exposure to stresses beyond the Recommended Operating Ranges limits may affect device reliability.
D.C. Characteristics [Input/Output] at Ta = 30 to 85C, AVSS = 0 V, PGND = 0 V, AVDD30 = 2.6 to 3.3 V (Note 3)
Parameter
High-level input voltage
Low-level input voltage
High-level input voltage
Symbol
VIH
VIL
VIH
Low-level input voltage
VIL
High-level input voltage
VIH
Low-level input voltage
High-level output
voltage
VIL
Low-level output voltage
High-level output
voltage
Low-level output voltage
Low-level output voltage
Conditions
CMOS
schmitt
Min
1.26
0.4
0..4
0.75AV
DD30
CMOS
schmitt
IOH = 1 mA
VOL
IOL = 1 mA
VOH
IOH = 2 mA
VOL
VOL
IOL = 2 mA
IOL = 2 mA
Max
1.4
CMOS
schmitt
VOH
Typ
1.51
Unit
V
V
V
V
V
0.25AVDD30
V
1.89
V
0.2
V
AVDD
30-0.3
V
0.3
0.2
AVDD
30
Applicable pins
DGSSB,DGSCLK
DGDATA,EIRQ
SCL,SDA
MON1,MON2,
DGSSB,DGSCLK
DGDATA
DGSSB,DGSCLK
DGDATA,EIRQ
MON1,MON2
V
V
SCL,SDA,
V
MON1,MON2
Analog input voltage
VAI
AVSS
Pull Up resistor
Rup
50
250
kΩ
Pull Down resistor
Rdn
50
220
kΩ
DGSSB,DGSCLK
DGDATA
MON1,MON2
DGSSB,DGSCLK
DGDATA,EIRQ
MON1,MON2
Note 3 : Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise
noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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LC898124EP1XC
Driver output at Ta = 25C, VSS = 0 V, PGND = 0 V, AVDD = VM = 2.8 V
Parameter
Output Current
OUT1 to OUT4
Output Current
OUT5, OUT6
Symbol
Ifull
Condition
Min
Typ
Max
Unit
Full code
160
mA
Full Code
OP-AF (bidirection)
130
mA
Non-volatile Memory Characteristics
Item
Endurance
Data retention
Write time
Symbol
EN
RT
Condition
Min
Typ
Max
1000
Unit
Cycles
Years
20
ms
10
tWT
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7
Applicable circuit
EEPROM
LC898124EP1XC
AC Characteristics
Power Sequence
tR
tOFF
2.6V
AVDD30
VM
Vbot
10%
Item
Symbol
Rise time
tR
Wait time
tW
Botom Voltage
Vbot
Min
Typ
Max
Units
3
ms
100
ms
0.2
V
Injection order between AVDD30 and VM is below.
tVMrd
tAVfd
2.6V
2.6V
AVDD30
VM  AVDD + 0.5V
(VM  3.3V)
VM
tVMrd > 0ms
tAVfd > 0ms
SDA, SCL tolerate 3V input at the time of power off.
The data in the EEPROM may be rewritten unintentionally if you do not keep specifications.
And it is forbidden to power off during EEPROM access. The data in the EEPROM may be rewritten
unintentionally.
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LC898124EP1XC
2-wire serial Interface Timing
The communication protocol is compatible with I2C (Fast mode Plus).
This circuit has clock stretch function.
SDA
SCL
Symbol
Pin
name
Fscl
SCL
tHD,STA
SCL
SDA
0.26
s
SCL clock Low period
tLOW
SCL
0.5
s
SCL clock High period
tHIGH
SCL
0.26
s
0.26
s
Item
SCL clock frequency
START condition hold time
Setup time for repetition
START condition
tSU,STA
Data hold time
tHD,DAT
Data setup time
tSU,DAT
SDA, SCL rising time
tr
SDA, SCL falling time
tf
STOP condition setup time
Bus free time between
STOP and START
tSU,STO
tBUF
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
Min
0 (*1)
Typ
Max
Units
1000
kHz
0.9
50
s
ns
120
ns
120
ns
0.26
s
0.5
s
(*1) Although the I2C specification defines a condition that 300 ns of hold time is required internally,
This LSI is designed for a condition with typ. 40 ns of hold time. If SDA signal is unstable around
falling point of SCL signal, please implement an appropriate treatment on board, such as inserting
a resistor.
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LC898124EP1XC
ORDERING INFORMATION
Device
LC898124EP1XC-MH
Package
Shipping (Qty / Packing)
WLCSP27, 3.89x1.30, 0.4P
(Pb-Free / Halogen Free)
4000 / Tape & Reel
† For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel
Packaging Specifications Brochure, BRD8011/D. http://www.onsemi.com/pub_link/Collateral/BRD8011-D.PDF
Development product sample is a product that intend to verify whether it is matched the customer's application spec. We kindly
ask you to evaluate surely and enough prior mass-production. Please contact our sales, if there are any problems.
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