MP3908 Current Mode PWM Controller with Synchronous Secondary Gate Drive The Future of Analog IC Technology DESCRIPTION FEATURES The MP3908 is a flexible current-mode PWM controller optimized for power-supply applications. The MP3908 features resistorprogrammable dead-time control to optimize efficiency for a broad number of different configurations, and a synchronous secondary gate drive. The MOSFET drivers are capable of driving >10A MOSFETs. It has an operational current of typically 270µA and can accommodate off-line, Telecom and non-isolated applications. Under-voltage lockout, soft-start, slope compensation and peak current limiting are all included. In a boost application, with an output voltage of less than 28V, the current sense pin can connect directly to the drain of the external switch. This eliminates the requirement for an additional current sensing element and its associated efficiency loss. • • • • • • • • • • • • • While designed for boost applications, the MP3908 can also be used for other topologies including Forward, Flyback and Sepic. The 10V gate driver compliance minimizes the power loss of the external MOSFET while allowing the use of a wide variety of standard threshold devices. An externally programmable delay following the turn off of the synchronous rectifier allows the incorporation of secondary side synchronous rectifier • Programmable Dead-Time Synchronous Secondary Gate Drive Current Mode Control 10V MOSFET Gate Drivers Drives >10A MOSFETs Soft-Start Cycle-by-Cycle Current Limiting Slope Current Compensation Lossless Current Sense (VISENSE<28V) 50µA Shutdown Current 270uA typical Operating Current 250KHz Constant Frequency Operation Applicable to Boost, SEPIC, Flyback and Forward Topologies Available in a 10-Pin MSOP Package APPLICATIONS • • • • • PoE PD Power Supplies TV CCFL Power Generation Telecom Isolated Power Brick Modules Off-line Controller “MPS” and “The Future of Analog IC Technology” are Registered Trademarks of Monolithic Power Systems, Inc. The MP3908 is available in space saving 10-pin MSOP package. TYPICAL APPLICATION Efficiency vs. Output Current 8 95 VCC 5 DELAY GND 7 T1 90 2 1 MP3908 EN MAIN ISENSE CSS SYNC COMP 3 FB 4 9 6 10 EFFICIENCY (%) ADJ 85 80 75 70 65 60 0 1 2 3 4 5 6 OUTPUT CURRENT (A) MP3908 Rev.0.9 8/29/2008 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 1 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER ABSOLUTE MAXIMUM RATINGS (1) PACKAGE REFERENCE VCC ............................................. –0.3V to +10V VCC Maximum Current ............................ 30mA ISENSE ....................................... –0.3V to +28V FB .............................................. –0.3V to +1.3V COMP............................................ –0.3V to +3V CSS, ENABLE ............................... –0.3V to +5V Junction Temperature...............................125°C Lead Temperature ....................................260°C Storage Temperature ..............–65°C to +150°C TOP VIEW 1 10 2 9 3 8 4 7 5 6 Recommended Operating Conditions (2) VCC Current ................................. 1mA to 25mA Operating Temperature .............–40°C to +85°C Part Number* MP3908DK * Package MSOP10 Temperature –40°C to +85°C For Tape & Reel, add suffix –Z (eg. MP3908DK–Z) For RoHS compliant packaging, add suffix –LF (eg. MP3908DK–LF–Z) Thermal Resistance (3) θJA θJC MSOP10 ................................ 150 ..... 65... °C/W Notes: 1) Exceeding these ratings may damage the device. 2) The device is not guaranteed to function outside of its operating conditions. 3) Measured on approximately 1” square of 1 oz copper. ELECTRICAL CHARACTERISTICS VCC = 10V, TA = +25°C, unless otherwise noted. Parameter VCC Undervoltage Lockout VCC On/Off Voltage Hysteresis Shutdown Current Quiescent Current (Operation) Symbol Condition Internal Divider (IQ) IS IQ Main Gate Driver Impedance (Sourcing) Main Gate Driver Impedance (Sinking) Synchronous Gate Driver Impedance (Sourcing) Synchronous Gate Driver Impedance (Sinking) Delay after Synchronous Gate Error Amplifier Transconductance Maximum Comp Current Error Amplifier Translator Gain (4) Switching Frequency Thermal Shutdown Maximum Duty Cycle Minimum On Time ISENSE Limit FB Voltage FB Bias Current Min EN/SS = 0V, VIN = 9V Output not switching, VFB = 1V, VCC = 9V Max 4.7 Units V V µA 270 320 µA VCC = 9V, VGATE = 5V 16 Ω VCC = 9V, IGATE = 5mA 5.0 Ω VCC = 9V, VSYNCGATE = 5V 16 Ω VCC = 9V, IGATE = 5mA 5.0 Ω RDELAY=100kΩ VFB connected to VCOMP/RUN. Force ±10µA to VCOMP/RUN. Sourcing and Sinking 50 ns AET fS 0.26 0.28 220 76 tON VFB IFB Typ 4.5 1 50 165 0.794 Current flowing out of part 0.38 40 0.32 260 150 81 200 190 0.818 50 0.46 0.36 300 86 215 0.847 mA/V µA V/V KHz °C % ns mV V nA Note: 4) Guaranteed by design. MP3908 Rev.0.9 8/29/2008 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 2 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER ELECTRICAL CHARACTERISTICS (continued) VCC = 10V, TA = +25°C, unless otherwise noted. Parameter ISENSE Bias Current Enable On Threshold Enable Hysteresis Soft Start Current Symbol Condition ISENSE Current flowing out of part VEN High-to-Low VEN ISS Min 1.15 Typ 50 1.25 50 4 Max Units nA 1.35 V mV µA PIN FUNCTIONS Pin # 1 2 3 4 5 6 7 8 9 10 Name Description Capacitor Soft Start. A charging current of 5µA is enabled when the ENABLE pin is CSS taken above 1.2V. The rise time of the capacitor allows output current soft start. Full output current is allowed when the voltage is above 2.7V. This pin serves two functions. Below 0.6V, the part is in sleep mood, drawing 10µA ENABLE (typ). The second threshold of 1.2V can be used as a precise under-voltage lock out (UVLO) and enables full operation.. COMP Compensation. Feedback forces this pin voltage to the 0.8V internal reference potential. Do not allow FB this pin to rise above 1.2V in the application. External resistor determines delay between the Synchronous Gate Drive pin going low RDELAY to the Main Gate drive going high. Current Sense. Do not connect this pin directly to the drain of the external MOSFET if the voltage swing exceeds 27V in the particular application. During normal operation, ISENSE this pin will sense the voltage across the external MOSFET or sense resistor if one is used, limiting the peak inductor current on a cycle-by-cycle basis. GND Ground. VCC Input Supply. Decouple this pin as close as possible to the GND pin. MAIN GATE This pin drives the external MAIN MOSFET device. This pin drives the external SYNCHRONOUS MOSFET device. The Sync Gate is SYNC GATE disabled at the end of switching period if Main Gate is not turned on the next cycle. MP3908 Rev.0.9 8/29/2008 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 3 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER OPERATION RDLY RDELAY VIN VCC VOUT CSS Enable Slope Compensation Oscillator + -- Internal Bias 9.9V 1.2V Vref = 0.8V ENABLE FB COMP Delay + -- Turn Off EA + -IMAX ITRP MAIN S Q R Q Driver Gates Off PGND Rsense Clamp ISENSE EA Translator S Q VCC R SGND Rdson sensing SYNC Optional Filter Figure 1—Functional Block Diagram The MP3908 uses a constant frequency, peak current mode architecture to regulate the feedback voltage. The operation of the MP3908 can be understood with the block diagram of Figure 1. At the beginning of each cycle the main external N-Channel MOSFET is turned on, forcing the current in the inductor to increase. The current through the FET can either be sensed through a sensing resistor or across the external FET directly. This voltage is then compared to a voltage related to the COMP/RUN node voltage. The voltage at the COMP/RUN pin is an amplified voltage of the difference between the 0.8V reference and the feedback node voltage. MP3908 Rev. 0.9 8/29/2008 When the voltage at the ISENSE node rises above the voltage set by the COMP/RUN pin, the external main FET is turned off and the synchronous FET, if used, is turned on. The inductor current then flows to the output capacitor through the Schottky diode. The inductor current is controlled by the COMP/RUN voltage, which itself is controlled by the output voltage. The peak inductor current is internally limited by the IMAX clamp voltage that limits the voltage applied to the ITRP comparator input. Thus the output voltage controls the inductor current to satisfy the load. This current mode architecture improves transient response and control loop stability over a voltage mode architecture. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 4 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER APPLICATION INFORMATION COMPONENT SELECTION Setting the Output Voltage Set the output voltage by selecting the resistive voltage divider ratio. If we use 10kΩ for the lowside resistor (R2) of the voltage divider, we can determine the high-side resistor (R1) by the equation: R1 = R2 × ( VOUT − VREF ) VREF Where VOUT is the output voltage. For R2=10kΩ, VOUT=25V and VREF=0.8V, then R1=301kΩ. An external resistor tied from the RDELAY pin to ground programs an internal time delay circuit that sets a delay from the turn off of the synchronous MOSFET drive pin output to the turn on of the main MOSFET drive pin output. This delay is adjustable to program the required time interval required by the circuitry to turn off the synchronous MOSFET from the time that the Synchronous output drive signal goes low. This path may include active devices as well as an isolating transformer used to electrically isolate the secondary side output. Efficiency losses can be quite significant if an overlap occurs between the main and synchronous switching MOSFETs if the delay is not carefully determined and accounted for. The RDELAY pin has an internal resistance of approximately 50kOhms that should be added to any external resistance used to approximate the delay interval. Shorting the pin directly to ground will result in approximately 30nSec delay as a result of this internal resistance. A graph is provided in the applications section of this data sheet to illustrate the typical delay time generated versus the resistor value selected Selecting the Inductor and Current Sensing Resistor The inductor is required to transfer the energy between the input source and the output capacitors. A larger value inductor results in less ripple current that results in lower peak inductor current, and therefore reduces the stress on the power MOSFET. However, the larger value inductor has a larger physical size, higher series resistance, and/or lower saturation current. A good rule of thumb is to allow the peak-to-peak ripple current to be approximately 30-50% of the maximum input current. Make sure that the peak inductor current is below 80% of the IC’s maximum current limit at the operating duty cycle to prevent loss of regulation. Make sure that the inductor does not saturate under the worst-case load transient and startup conditions. The required inductance value can be calculated by : L= VIN(MIN) × (VOUT - VIN(MIN) ) VOUT × f SW × ∆I IIN(MAX ) = VOUT × ILOAD (MAX ) VIN(MIN) × η ∆I = (30% − 50%)IIN(MAX) Where ILOAD (MAX) is the maximum load current, ∆I is the peak-to-peak inductor ripple current and η is the efficiency. For a typical design, boost converter efficiency can reach 85%~95%. For VIN (MIN)=10V, VOUT=25V, ILOAD (MAX)=2A, the ripple percentage being 30%, η=95% and fSW=330kHz, then L=10µH. In this case, use a 8.8µH inductor (i.e. Sumida CDRH127/LDNP100MC). The switch current is usually used for the peak current mode control. In order to avoid hitting the current limit, the voltage across the sensing resistor RSENSE should be less than 80% of the worst case current limit voltage, 200mV. R SENSE = 0 . 8 × 0. 2 IL(PEAK ) Where IL (PEAK) is the peak value of the inductor current. MP3908 Rev.0.9 8/29/2008 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 5 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER For IL (PEAK)=5.3A, RSENSE=30mΩ. In cases where the RDS(ON) of the power MOSFET is used as the sensing resistor, be sure that the RDS(ON) is lower than the value calculated above, 30mΩ Another factor to take into consideration is the temperature coefficient of the MOSFET RDS(ON). As the temperature increases, the RDS(ON) also increases.. Device vendors will usually provide an RDS(ON) vs. temperature curve and the temperature coefficient in the datasheet. Generally, the MOSFET on resistance will double from 25°C to 125°C. Selecting the Input Capacitor An input capacitor (C1) is required to supply the AC ripple current to the inductor, while limiting noise at the input source. A low ESR capacitor is required to keep the noise to the IC at a minimum. Ceramic capacitors are preferred, but tantalum or low-ESR electrolytic capacitors may also suffice. The capacitance can be calculated as: C1 ≈ ∆I 8 × ∆VIN(RIPPLE) × f SW Where ∆I is the peak-to-peak inductor ripple current and ∆VIN(RIPPLE) is the input voltage ripple. When using ceramic capacitors, take into account the vendor specified voltage and temperature coefficients for the particular dielectric being used. For example, 2.2uF capacitance is sufficient to achieve less then 1% input voltage ripple. Meanwhile, it requires an adequate ripple current rating. Use a capacitor with RMS current rating greater than the inductor ripple current (see Selecting the Inductor to determine the inductor ripple current). In addition, a smaller high quality ceramic 0.1µF~1µF capacitor may be placed to absorb the high frequency noise. If using this technique, it is recommended that the larger capacitor be a tantalum or electrolytic type. Selecting the Output Capacitor Typically, a boost converter has significant output voltage ripple because the current through the output diode is discontinuous. During the diode off state, all of the load current is supplied by the output capacitor. Low ESR capacitors are preferred to keep the output voltage ripple to a minimum. The characteristics of the output capacitor also affect the stability of the regulation control system. Ceramic, tantalum or low ESR electrolytic capacitors are recommended. In the case of ceramic capacitors, the impedance of the capacitor at the switching frequency is dominated by the capacitance, and so the output voltage ripple is mostly independent of the ESR. The output voltage ripple is estimated to be: VRIPPLE ⎛ V ⎞ ⎜1 - IN ⎟ × ILOAD ⎜ V ⎟ OUT ⎠ ⎝ ≈ C2 × f SW Where VRIPPLE is the output ripple voltage, VIN and VOUT are the DC input and output voltages respectively, ILOAD is the load current, fSW is the switching frequency and C2 is the output capacitor. In the case of tantalum or low-ESR electrolytic capacitors, the ESR dominates the impedance at the switching frequency. Therefore, the output ripple is calculated as: VRIPPLE(pk _ pk ) ≈ ILOAD × R ESR × VOUT VIN where RESR is the equivalent series resistance of the output capacitors. For the application shown in page 1, use ceramic capacitor as an example. For VIN(MIN)=10V, VOUT=25V, ILOAD(MAX)=2A, and VRIPPLE=1% of the output voltage, the capacitance C2=14.5µF. Please note that the ceramic capacitance could dramatically decrease as the voltage across the capacitor increases. As a result, larger capacitance is recommended. In this example, place four 4.7µF ceramic capacitors in parallel. The voltage rating is also chosen as 50V. In the meantime, the RMS current rating of the output capacitor needs to be sufficient to handle MP3908 Rev.0.9 8/29/2008 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 6 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER the large ripple current. The RMS current is given by: IRIPPLE(RMS) ≈ (I IN(MAX) 2 ) − 2 × ILOAD × IIN(MAX) × VIN 2 + ILOAD VOUT 2 IRIPPLE(RMS) ≈ D(1 − D) × IINMAX < 0.5 × IINMAX For IIN(MAX)=5.3A, ILOAD=2A, VIN=12V and VOUT=25V, IRIPPLE(RMS)=2.64A. Make sure that the output capacitor can handle such an RMS current. In addition, a smaller high quality ceramic 0.1µF~1uF capacitor needs to be placed at the output to absorb the high frequency noise during the commutation between the power MOSFET and the output diode. Basically, the high frequency noise is caused by the parasitic inductance of the trace and the parasitic capacitors of devices. The ceramic capacitor should be placed as close as possible to the power MOSFET and output diode in order to minimize the parasitic inductance and maximize the absorption. Selecting the Power MOSFET The MP3908 is capable of driving a wide variety of N-Channel power MOSFETS. The critical parameters of selection of a MOSFET are: 1. Maximum drain to source voltage, VDS(MAX) 2. Maximum current, ID(MAX) 3. On-resistance, RDS(ON) 4. Gate source charge QGS and gate drain charge QGD 5. Total gate charge, QG Ideally, the off-state voltage across the MOSFET is equal to the output voltage. Considering the voltage spike when it turns off, VDS(MAX) should be greater than 1.5 times of the output voltage. The maximum current through the power MOSFET happens when the input voltage is minimum and the output power is maximum. The maximum RMS current through the MOSFET is given by IRMS(MAX) = IIN(MAX) × D MAX Where: MP3908 Rev.0.9 8/29/2008 D MAX ≈ VOUT − VIN(MIN) VOUT The current rating of the MOSFET should be greater than 1.5 times IRMS, The on resistance of the MOSFET determines the conduction loss, which is given by: 2 Pcond = IRMS × R DS (on) × k Where k is the temperature coefficient of the MOSFET. If the RDS(ON) of the MOSFET is used as the current sensing resistor, make sure the voltage drop across the device does not exceed the current limit value of 190mV. The switching loss is related to QGD and QGS1 which determine the commutation time. QGS1 is the charge between the threshold voltage and the plateau voltage when a driver charges the gate, which can be read in the chart of VGS vs. QG of the MOSFET datasheet. QGD is the charge during the plateau voltage. These two parameters are needed to estimate the turn on and turn off loss. PSW = Q GS1 × R G × VDS × IIN × f SW + VDR − VTH Q GD × R G × VDS × IIN × f SW VDR − VPLT Where VTH is the threshold voltage, VPLT is the plateau voltage, RG is the gate resistance, VDS is the drain-source voltage. Please note that the switching loss is the most difficult part in the loss estimation. The formula above provides a simple physical expression. If more accurate estimation is required, the expressions will be much more complex. For extended knowledge of the power loss estimation, readers should refer to the book “Power MOSFET Theory and Applications” written by Duncan A. Grant and John Gowar. The total gate charge, QG, is used to calculate the gate drive loss. The expression is PDR = Q G × VDR × f SW where VDR is the drive voltage. For the application in page 1, a FDS6630 or equivalent MOSFET is chosen. Read from the datasheet: RDS(ON)=28mΩ, k = 0.5, QGD=0.9nC, www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 7 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER QGS1=1nC, VTH=1.7V, VPLT=3V and QG=5nC @ 10V. The MP3908 has its gate driving resistance of around 20Ω at VDR=10V and VGATE = 5V. Based on the loss calculation above, the conduction loss is around 0.629W. The switching loss is around 0.171W, and the gate drive loss is 0.015W. Selecting the Output Diode The output rectifier diode supplies current to the inductor when the MOSFET is off. To reduce losses due to diode forward voltage and recovery time, use a Schottky diode. The diode should be rated for a reverse voltage greater than the output voltage used. Considering the voltage spike during the commutation period, the voltage rating of the diode should be set as 1.5 times the output voltage. For high output voltages (150V or above), a Schottky diode might not be practical. A high-speed ultra-fast recovery silicon rectifier is recommended. Observation of the boost converter circuit shows that the average current through the diode is the average load current, and the peak current through the diode is the peak current through the inductor. The average current rating must be greater than 1.5 times of the maximum load current, and the peak current rating must be greater than the peak inductor current. For the application in page 1, a Vishay SS16 Schottky diode or equivalent part is chosen. Boost Converter: Compensation Design The output of the transconductance error amplifier (COMP) is used to compensate the regulation control system. The system uses two poles and one zero to stabilize the control loop. The poles are fP1, which is set by the output capacitor (C2) and load resistance and fP2, which starts from origin. The zero (fZ1) is set by the compensation capacitor (C3) and the compensation resistor (R3). These parameters are determined by the equations: MP3908 Rev.0.9 8/29/2008 fP1 = 1 π × C2 × R LOAD f Z1 = 1 2 × π × C3 × R3 Where RLOAD is the load resistance. The DC mid-band loop gain is: A VDC = 0.5 × GEA × VIN × R LOAD × VREF × R3 × A ET 2 VOUT × R SENSE where VREF is the voltage reference, 0.8V. AET is the gain of error amplifier translator and GEA is the error amplifier transconductance. The ESR zero in this example locates at very high frequency. Therefore, it is not taken into design consideration. There is also a right-half-plane zero (fRHPZ) that exists in continuous conduction mode (inductor current does not drop to zero on each cycle) step-up converters. The frequency of the right half plane zero is: 2 fRHPZ = VIN × R LOAD 2 × π × L × VOUT 2 The right-half-plane zero increases the gain and reduces the phase simultaneously, which results in smaller phase margin and gain margin. The worst case happens at the condition of minimum input voltage and maximum output power. In order to achieve system stability, fz1 is placed close to fP1 to cancel the pole. R3 is adjusted to change the voltage gain. Make sure the bandwidth is about 1/10 of the lower one of the ESR zero and the right-half-plane zero. 1 1 = π × C2 × R LOAD 2 × π × C3 × R3 2 R3 = VOUT × 2 × π × C2 × fc × R SENSE GEA × VREF × VIN × A ET Based on these equations, R3 and C3 can be solved. For the application in page 1, fp1 = 1.35KHz, ESR zero is much higher than the switching frequency and fRHPZ=45.8KHz. Set fz1 to 3.18KHz and make the crossover frequency 8.5kHz, then R3=5kΩ and C3=10nF. Choose 5kΩ and 10nF. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 8 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER In cases where the ESR zero is in a relatively low frequency region and results in insufficient gain margin, an optional capacitor (C5) (shown in flat page) should be added. Then a pole, formed by C5 and R3, should be placed at the ESR zero to cancel the adverse effect. C5 = MP3908 Rev.0.9 8/29/2008 1 2 × π × R3 × f ESRz Layout Consideration High frequency switching regulators require very careful layout for stable operation and low noise. Keep the high current path as short as possible between the MOSFET drain, output diode, output capacitor and GND pin for minimal noise and ringing. The VCC capacitor must be placed close to the VCC pin for best decoupling. All feedback components must be kept close to the FB pin to prevent noise injection on the FB pin trace. The ground return of the input and output capacitors should be tied closed to the GND pin. See the MP3908 demo board layout for reference. www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 9 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER TYPICAL APPLICATION CIRCUITS D6 SYNC 1 4 2 3 T2 36V to 72V VIN R6 51k R2 300k PGND EN D4 11V 8 VCC R3 20k 2N7002 GND DELAY MP3908 2 1 EN ISENSE CSS COMP 3 C4 NS R5 10k C5 10nF Np1 SYNC FB 4 7 NS R12, 5 9 2 R13, 1k 6 C8 10 330pF R31 NS R14 0 R7 910k 7, 8, 9 Np2 1 T1 8:1:4 Q2 Si7450 R16 0.05 R19 3k 5V@5A Q5 D2 R23 1.5k R20 VCC 10 R21 976 U2 PC817B R17 200 R15 470k R24 NS C16 C17 10nF 470pF VCC Q7 TLV431/1.24V R33 0 C18 1000pF/2000V R26 33.2k R25 10k SYNC Q4 NS GND D8 NS Q3 NS VOUT + 10, 11, 12 3 D1 R11 200V 499k D3 C7 4.7uF D7 15V 5 R10 30k VCC R35 1k R4 82.5k Q1 R8 R9 30k 30k R32 0 Q8 5 R1 1k R18, 5 R34, 330 D5 R28 10k R29 NS Q6 2N3904 C15 33nF R30 100k R27 10k R22 204 Figure 2—MP3908 Isolated Synchronous Flyback Application MP3908 Rev.0.9 8/29/2008 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 10 MP3908 – HIGH EFFICIENCY BOOST CONTROLLER PACKAGE INFORMATION MSOP10 0.114(2.90) 0.122(3.10) 6 10 0.114(2.90) 0.122(3.10) PIN 1 ID (NOTE 5) 0.007(0.18) 0.011(0.28) 0.187(4.75) 0.199(5.05) 5 1 0.0197(0.50)BSC BOTTOM VIEW TOP VIEW GAUGE PLANE 0.010(0.25) 0.030(0.75) 0.037(0.95) 0.043(1.10)MAX SEATING PLANE 0.002(0.05) 0.006(0.15) FRONT VIEW 0o-6o 0.016(0.40) 0.026(0.65) 0.004(0.10) 0.008(0.20) SIDE VIEW NOTE: 0.181(4.60) 0.040(1.00) 0.012(0.30) 1) CONTROL DIMENSION IS IN INCHES. DIMENSION IN BRACKET IS IN MILLIMETERS. 2) PACKAGE LENGTH DOES NOT INCLUDE MOLD FLASH, PROTRUSION OR GATE BURR. 3) PACKAGE WIDTH DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. 4) LEAD COPLANARITY (BOTTOM OF LEADS AFTER FORMING) SHALL BE 0.004" INCHES MAX. 5) PIN 1 IDENTIFICATION HAS THE HALF OR FULL CIRCLE OPTION. 6) DRAWING MEETS JEDEC MO-817, VARIATION BA. 7) DRAWING IS NOT TO SCALE. 0.0197(0.50)BSC RECOMMENDED LAND PATTERN NOTICE: The information in this document is subject to change without notice. Please contact MPS for current specifications. Users should warrant and guarantee that third party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not assume any legal responsibility for any said applications. MP3908 Rev. 0.9 8/29/2008 www.MonolithicPower.com MPS Proprietary Information. Unauthorized Photocopy and Duplication Prohibited. © 2008 MPS. All Rights Reserved. 11