Renesas HD6433567U 8-bit single-chip microcomputer Datasheet

REJ09B0303-0300
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
8
H8/3577 Group, H8/3567 Group
Hardware Manual
Renesas 8-Bit Single-Chip Microcomputer
H8 Family/H8/300 Series
H8/3577
H8/3574
H8/3567
H8/3564
H8/3567U
H8/3564U
Rev. 3.00
Revision Date: Mar 17, 2006
HD6433577
HD6473577
HD6433574
HD6433567
HD6473567
HD6433564
HD6433567U
HD6473567U
HD6433564U
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 3.00 Mar 17, 2006 page ii of xxiv
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 3.00 Mar 17, 2006 page iii of xxiv
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Main Revisions for This Edition
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
5. Contents
6. Overview
7. Description of Functional Modules
•
CPU and System-Control Modules
•
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
8. List of Registers
9. Electrical Characteristics
10. Appendix
Rev. 3.00 Mar 17, 2006 page iv of xxiv
Preface
The H8/3577 Group and H8/3567 Group comprise single-chip microcomputers built around the
H8/300 CPU and equipped with on-chip supporting functions required for system configuration.
Versions are available with PROM (ZTAT™) or mask ROM as on-chip ROM.
On-chip supporting functions include a16-bit free-running timer (FRT), 8-bit timer (TMR),
watchdog timer (WDT), two PWM timers (PWM and PWMX), a serial communication interface
2
(SCI), I C bus interface (IIC), A/D converter (ADC), and I/O ports.
The H8/3577 Group comprises 64-pin models with the above supporting functions on-chip. The
H8/3567 Group comprises the 42-pin H8/3567 and H8/3564 with fewer PWM, ADC, and I/O port
channels, and the 64-pin H8/3567U and H8/3564U with on-chip universal serial bus (USB) hubs
and function.
Use of the H8/3577 Group or H8/3567 Group enables compact, high-performance systems to be
implemented easily. The comprehensive timer functions and their interconnectability (timer
connection facility) make these groups ideal for applications such as PC monitor systems.
This manual describes the hardware of the H8/3577 Group and H8/3567 Group. Refer to the
H8/300 Series Programming Manual for a detailed description of the instruction set.
Note: ZTAT (Zero Turn-Around Time) is a trademark of Renesas Technology Corp.
Rev. 3.00 Mar 17, 2006 page v of xxiv
On-Chip Supporting Modules
Group
H8/3577 Group
H8/3567 Group
Product names
H8/3577, H8/3574
H8/3567, H8/3564,
H8/3567U, H8/3564U
Universal serial bus (USB)
—
—/Available
(H8/3567U, H8/3564U)
8-bit PWM timer (PWM)
×16
×8
14-bit PWM timer (PWMX)
×2
×2
16-bit free-running timer (FRT)
×1
×1
8-bit timer (TMR)
×4
×4
Timer connection
Available
Available
Watchdog timer (WDT)
×1
×1
Serial communication interface (SCI)
×1
×1
I C bus interface (IIC)
×2
×2
A/D converter
×8
×4
2
Rev. 3.00 Mar 17, 2006 page vi of xxiv
Main Revisions in This Edition
Item
Page
Revision (See Manual for Details)
All
—
• Notification of change in company name amended
(Before) Hitachi, Ltd. → (After) Renesas Technology Corp.
• Product naming convention amended
(Before) H8/3577 Series → (After) H8/3577 Group
(Before) H8/3567 Series → (After) H8/3567 Group
5.2.1 System Control
Register (SYSCR)
84
Bit table amended
Bit
...
...
7.3.5 Operation when 155
OUT Token Is
Received (Endpoints 0
and 2)
4
...
INTM0
...
Initial value
0
Read/Write
R
Figure amended
Clear EP2TS bit
to 0 in TSFR
Figure 7.3 (2)
Operation when OUT
Token Is Received
(EP2-OUT: Initial FIFO
Full) (cont)
7.3.9 USB Module
Startup Sequence
164
Description amended
8. After DPLL operation stabilization time, HSRST bit is
cleared to 0 by firmware
Initial Operation
Procedures:
Figure 7.5 USB Hub
Initial Operation
Procedure
165
Figure 7.6 USB
Function Initial
Operation Procedure
166
Figure amended
Clear FONLY
bit to 0 in
USBCR
Figure amended
(Wait for USB
operating clock
oscillation
stabilization
time (10 ms))
Clear FPLLRST
bit to 0 in
USBCR
Rev. 3.00 Mar 17, 2006 page vii of xxiv
Item
Page
Revision (See Manual for Details)
7.3.9 USB Module
Startup Sequence
167
Figure amended
Figure 7.6 USB
Function Initial
Operation Procedure
(cont)
Set EPIVLD
bit to 1 in
USBCSR0
Figure 7.9 USB
Function Standalone
Mode Upstream
Disconnection/
Reconnection
172
12.2.8 Timer
Connection Register S
(TCONRS)
296
2
16.3.1 I C Bus Data
Format
Figure amended
Set EPIVLD
bit to 1 in
USBCSR0
Table amended
Bit 7
TMRX/Y
Accessible Registers
H'FFF0
H'FFF1
H'FFF2
H'FFF3
H'FFF4
0
TCRX
(Initial value) (TMRX)
TCSRX
(TMRX)
TICRR
(TMRX)
TICRF
(TMRX)
TCNTX TCORC TCORAX TCORBX
(TMRX) (TMRX) (TMRX) (TMRX)
1
TCSRY
(TMRY)
TCORAY TCORBY TCNTY TISR
(TMRY) (TMRY) (TMRY) (TMRY)
TCRY
(TMRY)
447
Newly added
579
Table amended
Table 16.4
2
Description of I C Bus
Data Format Symbols
B.1 Addresses
Register
Address Name
B.3 Functions
H'FFE2
ADDRBH
H'FFE3
ADDRBL
H'FFE4
ADDRCH
H'FFE5
ADDRCL
H'FFE6
ADDRDH
H'FFE7
ADDRDL
587
Bit table added
606
Bit table added
UTESTR0, UTESTR1
UTESTR2
Rev. 3.00 Mar 17, 2006 page viii of xxiv
...
Module
Name
Bus
Width
A/D
8
H'FFF5
H'FFF6
H'FFF7
Item
Page
Revision (See Manual for Details)
Appendix G Package
Dimensions
703
Figure replaced
Figure G.2 FP-64A
Package Dimensions
704
Figure replaced
Figure G.3 DP-42S
Package Dimensions
705
Figure replaced
Figure G.4 FP-44A
Package Dimensions
706
Figure replaced
Figure G.1 DP-64S
Package Dimensions
Rev. 3.00 Mar 17, 2006 page ix of xxiv
Rev. 3.00 Mar 17, 2006 page x of xxiv
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
1
Overview........................................................................................................................... 1
Internal Block Diagrams ................................................................................................... 6
Pin Arrangement and Functions........................................................................................ 8
1.3.1 Pin Arrangement .................................................................................................. 8
1.3.2 List of Pin Functions............................................................................................ 14
1.3.3 Pin Functions ....................................................................................................... 22
Section 2 CPU ...................................................................................................................... 29
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Overview...........................................................................................................................
2.1.1 Features................................................................................................................
2.1.2 Address Space......................................................................................................
2.1.3 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
2.2.1 General Registers .................................................................................................
2.2.2 Control Registers .................................................................................................
2.2.3 Initial Register Values..........................................................................................
Data Formats.....................................................................................................................
2.3.1 Data Formats in General Registers ......................................................................
2.3.2 Memory Data Formats .........................................................................................
Addressing Modes ............................................................................................................
2.4.1 Addressing Modes ...............................................................................................
2.4.2 Effective Address Calculation .............................................................................
Instruction Set ...................................................................................................................
2.5.1 Data Transfer Instructions....................................................................................
2.5.2 Arithmetic Operations..........................................................................................
2.5.3 Logic Operations..................................................................................................
2.5.4 Shift Operations ...................................................................................................
2.5.5 Bit Manipulations.................................................................................................
2.5.6 Branching Instructions .........................................................................................
2.5.7 System Control Instructions.................................................................................
2.5.8 Block Data Transfer Instruction...........................................................................
Basic Operational Timing .................................................................................................
2.6.1 Access to On-Chip Memory (RAM, ROM).........................................................
2.6.2 Access to On-Chip Peripheral Modules...............................................................
CPU States ........................................................................................................................
2.7.1 Overview..............................................................................................................
2.7.2 Reset State............................................................................................................
29
29
30
30
31
31
31
33
33
34
35
36
36
38
42
44
46
47
47
49
53
55
57
58
58
59
60
60
61
Rev. 3.00 Mar 17, 2006 page xi of xxiv
2.8
2.7.3 Program Execution State......................................................................................
2.7.4 Program Halt State...............................................................................................
2.7.5 Exception-Handling State ....................................................................................
Application Notes .............................................................................................................
2.8.1 Notes on Bit Manipulation...................................................................................
2.8.2 Notes on Use of the EEPMOV Instruction
(Cannot Be Used in the H8/3577 Group and H8/3567 Group) ............................
61
61
61
62
62
64
Section 3 MCU Operating Modes .................................................................................. 65
3.1
3.2
3.3
Overview...........................................................................................................................
3.1.1 Operating Mode Selection ...................................................................................
3.1.2 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
3.2.1 Mode Control Register (MDCR) .........................................................................
3.2.2 System Control Register (SYSCR) ......................................................................
3.2.3 Serial Timer Control Register (STCR) ................................................................
Address Map .....................................................................................................................
65
65
65
66
66
67
68
69
Section 4 Exception Handling ......................................................................................... 73
4.1
4.2
4.3
4.4
4.5
Overview...........................................................................................................................
4.1.1 Exception Handling Types and Priority...............................................................
4.1.2 Exception Handling Operation.............................................................................
4.1.3 Exception Sources and Vector Table ...................................................................
Reset..................................................................................................................................
4.2.1 Overview..............................................................................................................
4.2.2 Reset Sequence ....................................................................................................
4.2.3 Interrupts after Reset............................................................................................
Interrupts ...........................................................................................................................
Stack Status after Exception Handling..............................................................................
Note on Stack Handling ....................................................................................................
73
73
73
74
75
75
75
76
77
78
79
Section 5 Interrupt Controller .......................................................................................... 81
5.1
5.2
Overview...........................................................................................................................
5.1.1 Features................................................................................................................
5.1.2 Block Diagram .....................................................................................................
5.1.3 Pin Configuration.................................................................................................
5.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
5.2.1 System Control Register (SYSCR) ......................................................................
5.2.2 IRQ Enable Register (IER) ..................................................................................
5.2.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL).....................................
Rev. 3.00 Mar 17, 2006 page xii of xxiv
81
81
82
83
83
84
84
85
86
5.3
5.4
5.5
5.2.4 IRQ Status Register (ISR)....................................................................................
Interrupt Sources...............................................................................................................
5.3.1 External Interrupts ...............................................................................................
5.3.2 Internal Interrupts.................................................................................................
5.3.3 Interrupt Exception Vector Table ........................................................................
Interrupt Operation............................................................................................................
5.4.1 Interrupt Operation ..............................................................................................
5.4.2 Interrupt Control Mode 0 .....................................................................................
5.4.3 Interrupt Exception Handling Sequence ..............................................................
5.4.4 Interrupt Response Times ....................................................................................
Usage Notes ......................................................................................................................
5.5.1 Contention between Interrupt Generation and Disabling.....................................
5.5.2 Instructions that Disable Interrupts ......................................................................
5.5.3 Interrupts during Execution of EEPMOV Instruction..........................................
87
88
88
89
89
92
92
94
96
97
98
98
99
99
Section 6 Bus Controller ................................................................................................... 101
6.1
6.2
Overview...........................................................................................................................
Register Descriptions ........................................................................................................
6.2.1 Bus Control Register (BCR) ................................................................................
6.2.2 Wait State Control Register (WSCR) ..................................................................
101
101
101
102
Section 7 Universal Serial Bus Interface (USB)......................................................... 103
7.1
7.2
Overview...........................................................................................................................
7.1.1 Features................................................................................................................
7.1.2 Block Diagram .....................................................................................................
7.1.3 Pin Configuration.................................................................................................
7.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
7.2.1 USB Data FIFO....................................................................................................
7.2.2 Endpoint Size Register 1 (EPSZR1) ....................................................................
7.2.3 Endpoint Data Registers 0I, 0O, 1, 2 (EPDR0I, EPDR0O, EPDR1, EPDR2) .....
7.2.4 FIFO Valid Size Registers 0I, 0O, 1, 2 (FVSR0I, FVSR0O, FVSR1, FVSR2)...
7.2.5 Endpoint Direction Register (EPDIR) .................................................................
7.2.6 Packet Transmit Enable Register (PTTER) .........................................................
7.2.7 USB Interrupt Enable Register (USBIER)...........................................................
7.2.8 USB Interrupt Flag Register (USBIFR) ...............................................................
7.2.9 Transfer Success Flag Register (TSFR) ...............................................................
7.2.10 Transfer Fail Flag Register (TFFR) .....................................................................
7.2.11 USB Control/Status Register 0 (USBCSR0)........................................................
7.2.12 Endpoint Stall Register (EPSTLR) ......................................................................
7.2.13 Endpoint Reset Register (EPRSTR).....................................................................
103
103
104
105
105
107
107
108
109
110
111
112
113
115
118
121
124
128
129
Rev. 3.00 Mar 17, 2006 page xiii of xxiv
7.3
7.2.14 Device Resume Register (DEVRSMR) ...............................................................
7.2.15 Interrupt Source Select Register 0 (INTSELR0)..................................................
7.2.16 Interrupt Source Select Register 1 (INTSELR1)..................................................
7.2.17 Hub Overcurrent Control Register (HOCCR)......................................................
7.2.18 USB Control Register (USBCR)..........................................................................
7.2.19 USB PLL Control Register (UPLLCR) ...............................................................
7.2.20 USB Port Control Register (UPRTCR)................................................................
7.2.21 USB Test Registers 2, 1, 0 (UTESTR2, UTESTR1, UTESTR0).........................
7.2.22 Module Stop Control Register (MSTPCR) ..........................................................
7.2.23 Serial Timer Control Register (STCR) ................................................................
Operation ..........................................................................................................................
7.3.1 USB Compound Device Configuration ...............................................................
7.3.2 Functions of USB Hub Block ..............................................................................
7.3.3 Functions of USB Function .................................................................................
7.3.4 Operation when SETUP Token Is Received (Endpoint 0)...................................
7.3.5 Operation when OUT Token Is Received (Endpoints 0 and 2) ...........................
7.3.6 Operation when IN Token Is Received (Endpoints 0, 1, and 2) ..........................
7.3.7 Suspend/Resume Operations................................................................................
7.3.8 USB Module Reset and Operation-Halted States ................................................
7.3.9 USB Module Startup Sequence............................................................................
7.3.10 USB Module Slave CPU Interrupts .....................................................................
131
131
133
133
135
139
141
142
143
143
145
145
145
146
148
153
155
159
159
162
175
Section 8 I/O Ports .............................................................................................................. 177
8.1
8.2
8.3
8.4
8.5
Overview...........................................................................................................................
Port 1.................................................................................................................................
8.2.1 Overview..............................................................................................................
8.2.2 Register Configuration.........................................................................................
8.2.3 Pin Functions .......................................................................................................
8.2.4 MOS Input Pull-Up Function...............................................................................
Port 2 [H8/3577 Group Only] ...........................................................................................
8.3.1 Overview..............................................................................................................
8.3.2 Register Configuration.........................................................................................
8.3.3 Pin Functions .......................................................................................................
8.3.4 MOS Input Pull-Up Function...............................................................................
Port 3 [H8/3577 Group Only] ...........................................................................................
8.4.1 Overview..............................................................................................................
8.4.2 Register Configuration.........................................................................................
8.4.3 Pin Functions .......................................................................................................
8.4.4 MOS Input Pull-Up Function...............................................................................
Port 4.................................................................................................................................
8.5.1 Overview..............................................................................................................
Rev. 3.00 Mar 17, 2006 page xiv of xxiv
177
180
180
181
182
185
186
186
187
189
191
192
192
192
194
194
195
195
8.5.2 Register Configuration.........................................................................................
8.5.3 Pin Functions .......................................................................................................
8.6 Port 5.................................................................................................................................
8.6.1 Overview..............................................................................................................
8.6.2 Register Configuration.........................................................................................
8.6.3 Pin Functions .......................................................................................................
8.7 Port 6.................................................................................................................................
8.7.1 Overview..............................................................................................................
8.7.2 Register Configuration.........................................................................................
8.7.3 Pin Functions .......................................................................................................
8.8 Port 7.................................................................................................................................
8.8.1 Overview..............................................................................................................
8.8.2 Register Configuration.........................................................................................
8.8.3 Pin Functions .......................................................................................................
8.9 Port C [H8/3567 Group Version with On-Chip USB Only] .............................................
8.9.1 Overview..............................................................................................................
8.9.2 Register Configuration.........................................................................................
8.9.3 Pin Functions .......................................................................................................
8.10 Port D [H8/3567 Group Version with On-Chip USB Only] .............................................
8.10.1 Overview..............................................................................................................
8.10.2 Register Configuration.........................................................................................
8.10.3 Pin Functions .......................................................................................................
195
197
199
199
199
201
202
202
202
203
206
206
206
207
208
208
208
210
211
211
211
213
Section 9 8-Bit PWM Timers........................................................................................... 215
9.1
9.2
9.3
Overview...........................................................................................................................
9.1.1 Features................................................................................................................
9.1.2 Block Diagram .....................................................................................................
9.1.3 Pin Configuration.................................................................................................
9.1.4 Register Configuration.........................................................................................
Register Descriptions ........................................................................................................
9.2.1 PWM Register Select (PWSL).............................................................................
9.2.2 PWM Data Registers (PWDR0 to PWDR15) ......................................................
9.2.3 PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)....................
9.2.4 PWM Output Enable Registers A and B (PWOERA and PWOERB) .................
9.2.5 Peripheral Clock Select Register (PCSR) ............................................................
9.2.6 Port 1 Data Direction Register (P1DDR).............................................................
9.2.7 Port 2 Data Direction Register (P2DDR).............................................................
9.2.8 Port 1 Data Register (P1DR)................................................................................
9.2.9 Port 2 Data Register (P2DR)................................................................................
9.2.10 Module Stop Control Register (MSTPCR) ..........................................................
Operation ..........................................................................................................................
215
215
216
217
217
218
218
220
220
221
222
222
223
223
223
224
225
Rev. 3.00 Mar 17, 2006 page xv of xxiv
9.3.1
Correspondence between PWM Data Register Contents
and Output Waveform.......................................................................................... 225
Section 10 14-Bit PWM Timer ........................................................................................ 227
10.1 Overview...........................................................................................................................
10.1.1 Features................................................................................................................
10.1.2 Block Diagram .....................................................................................................
10.1.3 Pin Configuration.................................................................................................
10.1.4 Register Configuration.........................................................................................
10.2 Register Descriptions ........................................................................................................
10.2.1 PWM D/A Counter (DACNT) .............................................................................
10.2.2 D/A Data Registers A and B (DADRA and DADRB).........................................
10.2.3 PWM D/A Control Register (DACR) ..................................................................
10.2.4 Module Stop Control Register (MSTPCR) ..........................................................
10.3 Bus Master Interface .........................................................................................................
10.4 Operation ..........................................................................................................................
227
227
228
229
229
230
230
231
232
234
235
238
Section 11 16-Bit Free-Running Timer......................................................................... 243
11.1 Overview...........................................................................................................................
11.1.1 Features................................................................................................................
11.1.2 Block Diagram .....................................................................................................
11.1.3 Input and Output Pins ..........................................................................................
11.1.4 Register Configuration.........................................................................................
11.2 Register Descriptions ........................................................................................................
11.2.1 Free-Running Counter (FRC) ..............................................................................
11.2.2 Output Compare Registers A and B (OCRA, OCRB) .........................................
11.2.3 Input Capture Registers A to D (ICRA to ICRD) ................................................
11.2.4 Output Compare Registers AR and AF (OCRAR, OCRAF) ...............................
11.2.5 Output Compare Register DM (OCRDM) ...........................................................
11.2.6 Timer Interrupt Enable Register (TIER) ..............................................................
11.2.7 Timer Control/Status Register (TCSR) ................................................................
11.2.8 Timer Control Register (TCR) .............................................................................
11.2.9 Timer Output Compare Control Register (TOCR) ..............................................
11.2.10 Module Stop Control Register (MSTPCR) ..........................................................
11.3 Operation ..........................................................................................................................
11.3.1 FRC Increment Timing ........................................................................................
11.3.2 Output Compare Output Timing ..........................................................................
11.3.3 FRC Clear Timing................................................................................................
11.3.4 Input Capture Input Timing .................................................................................
11.3.5 Timing of Input Capture Flag (ICFA to ICFD) Setting .......................................
11.3.6 Setting of Output Compare Flags A and B (OCFA, OCFB)................................
Rev. 3.00 Mar 17, 2006 page xvi of xxiv
243
243
244
245
246
247
247
247
248
249
250
250
252
255
257
260
260
260
262
263
263
266
267
11.3.7 Setting of FRC Overflow Flag (OVF) .................................................................
11.3.8 Automatic Addition of OCRA and OCRAR/OCRAF .........................................
11.3.9 ICRD and OCRDM Mask Signal Generation ......................................................
11.4 Interrupts ...........................................................................................................................
11.5 Sample Application...........................................................................................................
11.6 Usage Notes ......................................................................................................................
268
268
269
270
271
272
Section 12 8-Bit Timers .....................................................................................................
12.1 Overview...........................................................................................................................
12.1.1 Features................................................................................................................
12.1.2 Block Diagram .....................................................................................................
12.1.3 Pin Configuration.................................................................................................
12.1.4 Register Configuration.........................................................................................
12.2 Register Descriptions ........................................................................................................
12.2.1 Timer Counter (TCNT)........................................................................................
12.2.2 Time Constant Register A (TCORA)...................................................................
12.2.3 Time Constant Register B (TCORB) ...................................................................
12.2.4 Timer Control Register (TCR) .............................................................................
12.2.5 Timer Control/Status Register (TCSR) ................................................................
12.2.6 Serial Timer Control Register (STCR) ................................................................
12.2.7 System Control Register (SYSCR) ......................................................................
12.2.8 Timer Connection Register S (TCONRS)............................................................
12.2.9 Input Capture Register (TICR) [TMRX Additional Function] ............................
12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]...................
12.2.11 Input Capture Registers R and F (TICRR, TICRF)
[TMRX Additional Functions].............................................................................
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function].....................
12.2.13 Module Stop Control Register (MSTPCR) ..........................................................
12.3 Operation ..........................................................................................................................
12.3.1 TCNT Incrementation Timing .............................................................................
12.3.2 Compare-Match Timing.......................................................................................
12.3.3 TCNT External Reset Timing ..............................................................................
12.3.4 Timing of Overflow Flag (OVF) Setting .............................................................
12.3.5 Operation with Cascaded Connection..................................................................
12.4 Interrupt Sources...............................................................................................................
12.5 8-Bit Timer Application Example.....................................................................................
12.6 Usage Notes ......................................................................................................................
12.6.1 Contention between TCNT Write and Clear........................................................
12.6.2 Contention between TCNT Write and Increment ................................................
12.6.3 Contention between TCOR Write and Compare-Match ......................................
12.6.4 Contention between Compare-Matches A and B.................................................
279
279
279
280
281
282
283
283
284
285
286
290
294
295
295
296
296
297
297
298
299
299
300
302
302
303
304
305
306
306
307
308
309
Rev. 3.00 Mar 17, 2006 page xvii of xxiv
12.6.5 Switching of Internal Clocks and TCNT Operation............................................. 309
Section 13 Timer Connection...........................................................................................
13.1 Overview...........................................................................................................................
13.1.1 Features................................................................................................................
13.1.2 Block Diagram .....................................................................................................
13.1.3 Input and Output Pins ..........................................................................................
13.1.4 Register Configuration.........................................................................................
13.2 Register Descriptions ........................................................................................................
13.2.1 Timer Connection Register I (TCONRI) .............................................................
13.2.2 Timer Connection Register O (TCONRO) ..........................................................
13.2.3 Timer Connection Register S (TCONRS)............................................................
13.2.4 Edge Sense Register (SEDGR) ............................................................................
13.2.5 Module Stop Control Register (MSTPCR) ..........................................................
13.3 Operation ..........................................................................................................................
13.3.1 PWM Decoding (PDC Signal Generation) ..........................................................
13.3.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation) ........................
13.3.3 Measurement of 8-Bit Timer Divided Waveform Period ....................................
13.3.4 IHI Signal and 2fH Modification .........................................................................
13.3.5 IVI Signal Fall Modification and IHI Synchronization .......................................
13.3.6 Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
13.3.7 HSYNCO Output .................................................................................................
13.3.8 VSYNCO Output .................................................................................................
13.3.9 CBLANK Output .................................................................................................
313
313
313
314
315
316
316
316
318
320
323
325
327
327
328
330
332
334
336
339
340
341
Section 14 Watchdog Timer (WDT) .............................................................................. 343
14.1 Overview...........................................................................................................................
14.1.1 Features................................................................................................................
14.1.2 Block Diagram .....................................................................................................
14.1.3 Register Configuration.........................................................................................
14.2 Register Descriptions ........................................................................................................
14.2.1 Timer Counter (TCNT)........................................................................................
14.2.2 Timer Control/Status Register (TCSR0) ..............................................................
14.2.3 System Control Register (SYSCR) ......................................................................
14.2.4 Notes on Register Access.....................................................................................
14.3 Operation ..........................................................................................................................
14.3.1 Watchdog Timer Operation .................................................................................
14.3.2 Interval Timer Operation .....................................................................................
14.3.3 Timing of Setting of Overflow Flag (OVF) .........................................................
14.4 Interrupts ...........................................................................................................................
14.5 Usage Notes ......................................................................................................................
Rev. 3.00 Mar 17, 2006 page xviii of xxiv
343
343
344
345
345
345
346
348
349
349
349
350
351
352
352
14.5.1 Contention between Timer Counter (TCNT) Write and Increment ..................... 352
14.5.2 Changing Value of CKS2 to CKS0...................................................................... 353
14.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 353
Section 15 Serial Communication Interface (SCI) .................................................... 355
15.1 Overview...........................................................................................................................
15.1.1 Features................................................................................................................
15.1.2 Block Diagram .....................................................................................................
15.1.3 Pin Configuration.................................................................................................
15.1.4 Register Configuration.........................................................................................
15.2 Register Descriptions ........................................................................................................
15.2.1 Receive Shift Register (RSR) ..............................................................................
15.2.2 Receive Data Register (RDR) ..............................................................................
15.2.3 Transmit Shift Register (TSR) .............................................................................
15.2.4 Transmit Data Register (TDR).............................................................................
15.2.5 Serial Mode Register (SMR)................................................................................
15.2.6 Serial Control Register (SCR)..............................................................................
15.2.7 Serial Status Register (SSR) ................................................................................
15.2.8 Bit Rate Register (BRR) ......................................................................................
15.2.9 Serial Interface Mode Register (SCMR)..............................................................
15.2.10 Module Stop Control Register (MSTPCR) ..........................................................
15.3 Operation ..........................................................................................................................
15.3.1 Overview..............................................................................................................
15.3.2 Operation in Asynchronous Mode .......................................................................
15.3.3 Multiprocessor Communication Function............................................................
15.3.4 Operation in Synchronous Mode .........................................................................
15.4 SCI Interrupts....................................................................................................................
15.5 Usage Notes ......................................................................................................................
355
355
357
358
358
359
359
359
360
360
360
363
367
371
380
381
382
382
384
395
403
412
413
Section 16 I2C Bus Interface (IIC) .................................................................................. 417
16.1 Overview...........................................................................................................................
16.1.1 Features................................................................................................................
16.1.2 Block Diagram .....................................................................................................
16.1.3 Input/Output Pins .................................................................................................
16.1.4 Register Configuration.........................................................................................
16.2 Register Descriptions ........................................................................................................
2
16.2.1 I C Bus Data Register (ICDR) .............................................................................
16.2.2 Slave Address Register (SAR) .............................................................................
16.2.3 Second Slave Address Register (SARX) .............................................................
2
16.2.4 I C Bus Mode Register (ICMR) ...........................................................................
2
16.2.5 I C Bus Control Register (ICCR) .........................................................................
417
417
418
420
421
422
422
425
427
428
430
Rev. 3.00 Mar 17, 2006 page xix of xxiv
2
16.2.6 I C Bus Status Register (ICSR)............................................................................
16.2.7 Serial Timer Control Register (STCR) ................................................................
16.2.8 DDC Switch Register (DDCSWR) ......................................................................
16.2.9 Module Stop Control Register (MSTPCR) ..........................................................
16.3 Operation ..........................................................................................................................
2
16.3.1 I C Bus Data Format ............................................................................................
16.3.2 Master Transmit Operation ..................................................................................
16.3.3 Master Receive Operation....................................................................................
16.3.4 Slave Receive Operation......................................................................................
16.3.5 Slave Transmit Operation ....................................................................................
16.3.6 IRIC Setting Timing and SCL Control ................................................................
2
16.3.7 Automatic Switching from Formatless Mode to I C Bus Format ........................
16.3.8 Noise Canceler .....................................................................................................
16.3.9 Sample Flowcharts...............................................................................................
16.3.10 Initialization of Internal State ..............................................................................
16.4 Usage Notes ......................................................................................................................
436
441
442
445
446
446
448
450
452
455
457
458
459
459
463
465
Section 17 A/D Converter ................................................................................................. 471
17.1 Overview...........................................................................................................................
17.1.1 Features................................................................................................................
17.1.2 Block Diagram .....................................................................................................
17.1.3 Pin Configuration.................................................................................................
17.1.4 Register Configuration.........................................................................................
17.2 Register Descriptions ........................................................................................................
17.2.1 A/D Data Registers A to D (ADDRA to ADDRD)..............................................
17.2.2 A/D Control/Status Register (ADCSR) ...............................................................
17.2.3 A/D Control Register (ADCR) ............................................................................
17.2.4 Module Stop Control Register (MSTPCR) ..........................................................
17.3 Interface to Bus Master .....................................................................................................
17.4 Operation ..........................................................................................................................
17.4.1 Single Mode (SCAN = 0) ....................................................................................
17.4.2 Scan Mode (SCAN = 1).......................................................................................
17.4.3 Input Sampling and A/D Conversion Time .........................................................
17.4.4 External Trigger Input Timing.............................................................................
17.5 Interrupts ...........................................................................................................................
17.6 Usage Notes ......................................................................................................................
471
471
472
473
474
474
474
475
478
479
480
481
481
483
485
486
486
487
Section 18 RAM .................................................................................................................. 493
18.1 Overview........................................................................................................................... 493
18.1.1 Block Diagram ..................................................................................................... 493
18.1.2 Register Configuration......................................................................................... 494
Rev. 3.00 Mar 17, 2006 page xx of xxiv
18.2 System Control Register (SYSCR) ................................................................................... 494
18.3 Operation .......................................................................................................................... 494
Section 19 ROM .................................................................................................................. 495
19.1 Overview........................................................................................................................... 495
19.2 Operation .......................................................................................................................... 495
19.3 Writer Mode (H8/3577, H8/3567, H8/3567U).................................................................. 496
19.3.1 Writer Mode Setup............................................................................................... 496
19.3.2 Socket Adapter Pin Assignments and Memory Map ........................................... 497
19.4 PROM Programming ........................................................................................................ 502
19.4.1 Programming and Verification............................................................................. 502
19.4.2 Notes on Programming ........................................................................................ 507
19.4.3 Reliability of Programmed Data .......................................................................... 508
Section 20 Clock Pulse Generator ..................................................................................
20.1 Overview...........................................................................................................................
20.1.1 Block Diagram .....................................................................................................
20.1.2 Register Configuration.........................................................................................
20.2 Register Descriptions ........................................................................................................
20.2.1 Standby Control Register (SBYCR) ....................................................................
20.3 Oscillator...........................................................................................................................
20.3.1 Connecting a Crystal Resonator...........................................................................
20.3.2 External Clock Input ............................................................................................
20.4 Duty Adjustment Circuit...................................................................................................
20.5 Medium-Speed Clock Divider ..........................................................................................
20.6 Bus Master Clock Selection Circuit ..................................................................................
20.7 Universal Clock Pulse Generator [H8/3567 Group Version with On-Chip USB] ...........
20.7.1 Block Diagram .....................................................................................................
20.7.2 Registers...............................................................................................................
509
509
509
509
510
510
511
511
513
516
516
516
516
516
517
Section 21 Power-Down State ......................................................................................... 521
21.1 Overview...........................................................................................................................
21.1.1 Register Configuration.........................................................................................
21.2 Register Descriptions ........................................................................................................
21.2.1 Standby Control Register (SBYCR) ....................................................................
21.2.2 Module Stop Control Register (MSTPCR) ..........................................................
21.3 Medium-Speed Mode........................................................................................................
21.4 Sleep Mode .......................................................................................................................
21.4.1 Sleep Mode ..........................................................................................................
21.4.2 Clearing Sleep Mode............................................................................................
21.5 Module Stop Mode ...........................................................................................................
521
524
524
524
526
526
528
528
528
528
Rev. 3.00 Mar 17, 2006 page xxi of xxiv
21.5.1 Module Stop Mode ..............................................................................................
21.5.2 Usage Note...........................................................................................................
21.6 Software Standby Mode....................................................................................................
21.6.1 Software Standby Mode.......................................................................................
21.6.2 Clearing Software Standby Mode ........................................................................
21.6.3 Setting Oscillation Settling Time after Clearing Software Standby Mode ..........
21.6.4 Software Standby Mode Application Example....................................................
21.6.5 Usage Note...........................................................................................................
21.7 Hardware Standby Mode ..................................................................................................
21.7.1 Hardware Standby Mode .....................................................................................
21.7.2 Hardware Standby Mode Timing.........................................................................
528
529
530
530
530
531
531
532
533
533
534
Section 22 Electrical Characteristics.............................................................................. 535
22.1 Absolute Maximum Ratings .............................................................................................
22.2 DC Characteristics ............................................................................................................
22.3 AC Characteristics ............................................................................................................
22.3.1 Clock Timing .......................................................................................................
22.3.2 Control Signal Timing .........................................................................................
22.3.3 Timing of On-Chip Supporting Modules.............................................................
22.4 A/D Conversion Characteristics........................................................................................
22.5 USB Function Pin Characteristics.....................................................................................
22.6 Usage Notes ......................................................................................................................
535
536
540
541
543
545
552
553
556
Appendix A CPU Instruction Set .................................................................................... 559
A.1
A.2
A.3
Instruction Set List ............................................................................................................ 559
Operation Code Map......................................................................................................... 567
Number of States Required for Execution ........................................................................ 569
Appendix B Internal I/O Registers ................................................................................. 575
B.1
B.2
B.3
Addresses .......................................................................................................................... 575
Register Selection Conditions ........................................................................................... 580
Functions........................................................................................................................... 586
Appendix C I/O Port Block Diagrams........................................................................... 673
C.1
C.2
C.3
C.4
C.5
C.6
C.7
Port 1 Block Diagrams......................................................................................................
Port 2 Block Diagrams......................................................................................................
Port 3 Block Diagram .......................................................................................................
Port 4 Block Diagrams......................................................................................................
Port 5 Block Diagrams......................................................................................................
Port 6 Block Diagrams......................................................................................................
Port 7 Block Diagram .......................................................................................................
Rev. 3.00 Mar 17, 2006 page xxii of xxiv
673
678
682
683
688
691
696
C.8
C.9
Port 8 Block Diagrams...................................................................................................... 697
Port D Block Diagram....................................................................................................... 699
Appendix D Pin States ....................................................................................................... 700
D.1
Port States in Each Mode .................................................................................................. 700
Appendix E Timing of Transition to and Recovery
from Hardware Standby Mode................................................................. 701
E.1
E.2
Timing of Transition to Hardware Standby Mode ............................................................ 701
Timing of Recovery from Hardware Standby Mode......................................................... 701
Appendix F Product Code Lineup .................................................................................. 702
Appendix G Package Dimensions .................................................................................. 703
Rev. 3.00 Mar 17, 2006 page xxiii of xxiv
Rev. 3.00 Mar 17, 2006 page xxiv of xxiv
Section 1 Overview
Section 1 Overview
1.1
Overview
The H8/3577 Group and H8/3567 Group comprise single-chip microcomputers (MCUs) built
around the H8/300 CPU and equipped with on-chip supporting functions required for system
configuration.
On-chip supporting functions required for system configuration include ROM and RAM, a 16-bit
free-running timer (FRT), 8-bit timer (TMR), watchdog timer (WDT), two PWM timers (PWM
2
and PWMX), serial communication interface (SCI), I C bus interface (IIC), A/D converter (ADC),
and I/O ports. The H8/3577 Group comprises 64-pin MCUs, and the H8/3567 Group 42-pin
MCUs, but the H8/3567 Group also includes a 64-pin variation with on-chip universal serial bus
(USB) hubs and function.
The on-chip ROM is either PROM (ZTAT) or mask ROM, with a capacity of 56 or 32 kbytes.
There is only one operating mode: single-chip mode.
The features of the H8/3577 Group and H8/3567 Group are shown in table 1.1.
Rev. 3.00 Mar 17, 2006 page 1 of 706
REJ09B0303-0300
Section 1 Overview
Table 1.1
Features
Item
Specifications
CPU
•
General-register architecture
 Sixteen 8-bit general registers (also usable as eight 16-bit registers)
•
High-speed operation suitable for realtime control
 Maximum operating frequency: 20 MHz/5 V (HD6433564-10:
10 MHz/5 V)
 High-speed arithmetic operations
8/16-bit register-register add/subtract: 0.1 µs (20-MHz operation)
8 × 8-bit register-register multiply: 0.7 µs (20-MHz operation)
16 ÷ 8-bit register-register divide: 0.7 µs (20-MHz operation)
•
Instruction set suitable for high-speed operation
 2-byte or 4-byte instruction length
 Register-register basic operations
 Memory-register data transfer by MOV instruction
•
Instructions with special features
 Multiply instructions (8 bits × 8 bits)
 Divide instructions (16 bits ÷ 8 bits)
 Bit-accumulator instructions
 Bit position specifiable by means of register indirect specification
16-bit free-running
timer (FRT),
1 channel
8-bit timer (TMR),
2 channels
(TMR0, TMR1)
•
One 16-bit free-running counter (usable for external event counting)
•
Two output compare outputs
•
Four input capture inputs (with buffer operation capability)
Each channel has:
•
One 8-bit up-counter (usable for external event counting)
•
Two timer constant registers
•
The two channels can be connected
Rev. 3.00 Mar 17, 2006 page 2 of 706
REJ09B0303-0300
Section 1 Overview
Item
Specifications
Timer connection
and 8-bit timer
(TMR), 2 channels
(TMRX, TMRY)
Input/output and FRT, TMR1, TMRX, TMRY can be interconnected
•
Measurement of input signal or frequency-divided waveform pulse width
and cycle (FRT, TMR1)
•
Output of waveform obtained by modification of input signal edge (FRT,
TMR1)
•
Determination of input signal duty cycle (TMRX)
•
Output of waveform synchronized with input signal (FRT, TMRX, TMRY)
•
Automatic generation of cyclical waveform (FRT, TMRY)
Watchdog timer
(WDT), 1 channel
•
Watchdog timer or interval timer function selectable
8-bit PWM timer
(PWM)
•
Maximum of 16 (H8/3577 Group) or 8 (H8/3567 Group) outputs
•
Pulse duty cycle settable from 0 to 100%
•
Resolution: 1/256
•
1.25 MHz maximum carrier frequency (20-MHz operation)
•
Maximum of 2 outputs
•
Resolution: 1/16384
•
312.5 kHz maximum carrier frequency (20-MHz operation)
Serial communication interface
(SCI), 1 channel
(SCI0)
•
Asynchronous mode or synchronous mode selectable
•
Multiprocessor communication function
A/D converter
•
Resolution: 10 bits
•
Input: 8 channels (H8/3577 Group)
14-bit PWM timer
(PWMX)
4 channels (H8/3567 Group)
I/O ports
•
High-speed conversion : 6.7 µs minimum conversion time (20-MHz
operation)
•
Single or scan mode selectable
•
Sample-and-hold function
•
A/D conversion can be activated by external trigger or timer trigger
•
Input/output pins: 43 (H8/3577 Group, H8/3567 Group models with onchip USB) or 27 (H8/3567 Group)
•
Input-only pins: 8 (H8/3577 Group) or 4 (H8/3567 Group)
Rev. 3.00 Mar 17, 2006 page 3 of 706
REJ09B0303-0300
Section 1 Overview
Item
Specifications
Memory
•
PROM or mask ROM
•
High-speed static RAM
Product Code
ROM
RAM
H8/3577, H8/3567, H8/3567U
56 kbytes
2 kbytes
H8/3574, H8/3564, H8/3564U
32 kbytes
2 kbytes
•
Four external interrupt pins (NMI, IRQ0 to IRQ2)
•
26 internal interrupt sources (H8/3567U Group: 30 sources)
•
Medium-speed mode
•
Sleep mode
•
Module stop mode
•
Software standby mode
•
Hardware standby mode
Clock pulse
generator
•
Built-in duty correction circuit
Packages
•
64-pin plastic DIP (DP-64S)
•
64-pin plastic QFP (FP-64A)
•
42-pin plastic DIP (DP-42S)
•
44-pin plastic QFP (FP-44A)
•
Conforms to Philips I C bus interface standard
•
Single master mode/slave mode
•
Arbitration lost condition can be identified
•
Supports two slave addresses
Interrupt controller
Power-down state
2
I C bus interface
(IIC), 2 channels
Universal serial
•
bus interface (USB)
[H8/3567U,
•
H8/3564U]
2
Comprises five downstream hubs and one function
(four sets of downstream pins)
Three-endpoint monitor device class function
EP0: For USB control
EP1, EP2: For monitor control
•
Supports 12 Mbps high-speed transfer mode
•
Built-in 12 MHz clock pulse generator and 4X multiplication circuit
•
Built-in bus driver/receiver (requires 3.3 V analog power supply)
Rev. 3.00 Mar 17, 2006 page 4 of 706
REJ09B0303-0300
Section 1 Overview
Item
Specifications
Product lineup
Product Code
Group
H8/3577
Mask ROM
Version
HD6433577
HD6433574
H8/3567
HD6433567
ZTAT
Version
HD6473577
—
HD6473567
ROM/RAM
(Bytes)
Packages
56 k/2 k
DP-64S, FP-64A
32 k/2 k
56 k/2 k
DP-42S, FP-44A
HD6433564-20
—
32 k/2 k
HD6433564-10
—
32 k/2 k
DP-42S
56 k/2 k
DP-64S, FP-64A
HD6433567U
HD6433564U
HD6473567U
—
32 k/2 k
Rev. 3.00 Mar 17, 2006 page 5 of 706
REJ09B0303-0300
Rev. 3.00 Mar 17, 2006 page 6 of 706
REJ09B0303-0300
Port 6
10-bit A/D converter
IIC × 2 channels
SCI × 1 channel
14-bit PWM
Internal address bus
8-bit timer × 4 channels
Timer connection
(TMR0, TMR1, TMRX,
TMRY)
16-bit FRT
Port 1
AN7/ P77
AN6/ P76
AN5/ P75
AN4/ P74
AN3/ P73
AN2/ P72
AN1/ P71
AN0/ P70
Port 4
8-bit PWM
WDT0
Internal data bus
RAM
ROM
Port 2
HSYNCO/TMO1/ TMOX/P67
CSYNCI/TMRI1/ FTOB/P66
HSYNCI/TMCI1/ FTID/P65
CLAMPO/TMO0/ FTIC/P64
VFBACKI/TMRI0/ FTIB/P63
VSYNCI/ TMIY/FTIA/ P62
VSYNCO/FTOA/P61
HFBACKI/TMCI0/TMIX/ FTCI/P60
Clock pulse generator
Interrupt controller
Port 3
SDA0/ P47
φ/ P46
P45
P44
P43
IRQ0/ P42
IRQ1/ P41
ADTRG/ IRQ2/ P40
H8/300 CPU
AVCC
AVSS
P52/ SCK0/ SCL0
P51/ RXD0
P50/ TXD0
P17/ PW7
P16/ PW6
P15/ PW5
P14/ PW4
P13/ PW3
P12/ PW2
P11/ PW1/ PWX1
P10/ PW0/ PWX0
P27/ PW15/ CBLANK
P26/ PW14
P25/ PW13
P24/ PW12/ SCL1
P23/ PW11/ SDA1
P22/ PW10
P21/ PW9
P20/ PW8
P37
P36
P35
P34
P33
P32
P31
P30
1.2
MD1
MD0
EXTAL
XTAL
STBY
RES
NMI
VCL, VCC
VSS
Section 1 Overview
Internal Block Diagrams
Figures 1.1 and 1.2 show internal block diagrams of the H8/3577 Group and H8/3567 Group.
Port 5
Peripheral address bus
Peripheral data bus
Bus controller
Port 7
Figure 1.1 Internal Block Diagram of H8/3577 Group
Port 4
Port 6
10-bit A/D converter
IIC × 2 channels
Port 1
AN3/P73
AN2/P72
AN1/P71
AN0/P70
SCI × 1 channel
14-bit PWM
Internal address bus
8-bit timer × 4 channels
Timer connection
(TMR0, TMR1, TMRX,
TMRY)
16-bit FRT
8-bit PWM
WDT0
Bus controller
USB
Port C
RAM
H8/300 CPU
Internal data bus
ROM
Interrupt controller
Clock pulse generator
HSYNCO/TMO1/ TMOX/P67
CSYNCI/TMRI1/FTOB/P66
HSYNCI/TMCI1/FTID/P65
CLAMPO/TMO0/FTIC/P64
VFBACKI/TMRI0/FTIB/P63
VSYNCI/TMIY/FTIA/P62
VSYNCO/FTOA/P61
HFBACKI/TMCI0/TMIX/FTCI/P60
TEST
EXTAL
XTAL
STBY
RES
NMI
VCL, VCC
VSS
When on-chip
USB is provided
Port D
SDA0/P47
φ/P46
P45
P44
P43
IRQ0/P42
IRQ1/P41
ADTRG/IRQ2/P40
DrVCC
DrVSS
EXTAL12
XTAL12
When on-chip
USB is provided
AVCC
AVSS
P52/SCK0/SCL0
P51/RXD0
P50/TXD0
P17/PW7/SCL1
P16/PW6/SDA1
P15/PW5/CBLANK
P14/PW4
P13/PW3
P12/PW2
P11/PW1/PWX1
P10/PW0/PWX0
PC7/OCP5
PC6/OCP4
PC5/OCP3
PC4/OCP2
PC3/ENP5
PC2/ENP4
PC1/ENP3
PC0/ENP2
USD–
USD+
PD7/DS5D–
PD6/DS5D+
PD5/DS4D–
PD4/DS4D+
PD3/DS3D–
PD2/DS3D+
PD1/DS2D–
PD0/DS2D+
Section 1 Overview
Port 5
Peripheral address bus
Peripheral data bus
Port 7
Figure 1.2 Internal Block Diagram of H8/3567 Group
Rev. 3.00 Mar 17, 2006 page 7 of 706
REJ09B0303-0300
Section 1 Overview
1.3
Pin Arrangement and Functions
1.3.1
Pin Arrangement
The pin arrangements of the H8/3577 Group are shown in figures 1.3 and 1.4, and those of the
H8/3567 Group in figures 1.5 to 1.8.
ADTRG/IRQ2/P40
IRQ1/P41
IRQ0/P42
P43
P44
P45
φ/P46
SDA0/P47
TxD0/P50
RxD0/P51
SCL0/SCK0/P52
RES
NMI
VCC/VCL
STBY
VSS
XTAL
EXTAL
MD1
MD0
AVSS
AN0/P70
AN1/P71
AN2/P72
AN3/P73
AN4/P74
AN5/P75
AN6/P76
AN7/P77
AVCC
HFBACKI/TMIX/TMCI0/FTCI/P60
VSYNCO/FTOA/P61
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P37
P36
P35
P34
P33
P32
P31
P30
P10/PW0/PWX0
P11/PW1/PWX1
P12/PW2
P13/PW3
P14/PW4
P15/PW5
P16/PW6
P17/PW7
VSS
P20/PW8
P21/PW9
P22/PW10
P23/PW11/SDA1
P24/PW12/SCL1
P25/PW13
P26/PW14
P27/PW15/CBLANK
VCC
P67/TMOX/TMO1/HSYNCO
P66/FTOB/TMRI1/CSYNCI
P65/FTID/TMCI1/HSYNCI
P64/FTIC/TMO0/CLAMPO
P63/FTIB/TMRI0/VFBACKI
P62/FTIA/TMIY/VSYNCI
Figure 1.3 H8/3577 Group Pin Arrangement (DP-64S: Top View)
Rev. 3.00 Mar 17, 2006 page 8 of 706
REJ09B0303-0300
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P10/PW0/PWX0
P11/PW1/PWX1
P12/PW2
P13/PW3
P14/PW4
P15/PW5
P16/PW6
P17/PW7
VSS
P20/PW8
P21/PW9
P22/PW10
P23/PW11/SDA1
P24/PW12/SCL1
P25/PW13
P26/PW14
Section 1 Overview
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
P27/PW15/CBLANK
VCC
P67/TMOX/TMO1/HSYNCO
P66/FTOB/TMRI1/CSYNCI
P65/FTID/TMCI1/HSYNCI
P64/FTIC/TMO0/CLAMPO
P63/FTIB/TMRI0/VFBACKI
P62/FTIA/TMIY/VSYNCI
P61/FTOA/VSYNCO
P60/FTCI/TMCI0/TMIX/HFBACKI
AVCC
P77/AN7
P76/AN6
P75/AN5
P74/AN4
P73/AN3
TxD0/P50
RxD0/P51
SCL0/SCK0/P52
RES
NMI
VCC/VCL
STBY
VSS
XTAL
EXTAL
MD1
MD0
AVSS
AN0/P70
AN1/P71
AN2/P72
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P30
P31
P32
P33
P34
P35
P36
P37
ADTRG/IRQ2/P40
IRQ1/P41
IRQ0/P42
P43
P44
P45
φ/P46
SDA0/P47
Figure 1.4 H8/3577 Group Pin Arrangement (FP-64A: Top View)
Rev. 3.00 Mar 17, 2006 page 9 of 706
REJ09B0303-0300
Section 1 Overview
ADTRG/IRQ2/P40
IRQ1/P41
IRQ0/P42
φ/P46
SDA0/P47
SCL0/SCK0/P52
RES
NMI
VCC
VCC/VCL
STBY
XTAL
EXTAL
TEST
VSS/AVSS
AN0/P70
AN1/P71
AN2/P72
AN3/P73
AVCC
HFBACKI/TMIX/TMCI0/FTCI/P60
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
P45
P44
P43
P51/RxD0
P50/TxD0
P10/PW0/PWX0
P11/PW1/PWX1
P12/PW2
P13/PW3
P14/PW4
VSS
P15/PW5/CBLANK
P16/PW6/SDA1
P17/PW7/SCL1
P61/FTOA/VSYNCO
P62/FTIA/TMIY/VSYNCI
P63/FTIB/TMRI0/VFBACKI
P67/TMOX/TMO1/HSYNCO
P66/FTOB/TMRI1/CSYNCI
P65/FTID/TMCI1/HSYNCI
P64/FTIC/TMO0/CLAMPO
Figure 1.5 H8/3567 Group Pin Arrangement (No USB; DP-42S: Top View)
Rev. 3.00 Mar 17, 2006 page 10 of 706
REJ09B0303-0300
33
32
31
30
29
28
27
26
25
24
23
P10/PW0/PWX0
P11/PW1/PWX1
P12/PW2
P13/PW3
P14/PW4
VSS
P15/PW5/CBLANK
P16/PW6/SDA1
P17/PW7/SCL1
P61/FTOA/VSYNCO
P62/FTIA/TMIY/VSYNCI
Section 1 Overview
34
35
36
37
38
39
40
41
42
43
44
22
21
20
19
18
17
16
15
14
13
12
P63/FTIB/TMRI0/VFBACKI
P67/TMOX/TMO1/HSYNCO
P66/FTOB/TMRI1/CSYNCI
P65/FTID/TMCI1/HSYNCI
P64/FTIC/TMO0/CLAMPO
NC
P60/FTCI/TMCI0/TMIX/HFBACKI
AVCC
P73/AN3
P72/AN2
P71/AN1
SCL0/SCK0/P52
RES
NMI
VCC
VCC/VCL
STBY
XTAL
EXTAL
TEST
VSS/AVSS
AN0/P70
1
2
3
4
5
6
7
8
9
10
11
TxD0/P50
RxD0/P51
P43
P44
P45
NC
ADTRG/IRQ2/P40
IRQ1/P41
IRQ0/P42
φ/P46
SDA0/P47
Figure 1.6 H8/3567 Group Pin Arrangement (No USB; FP-44A: Top View)
Rev. 3.00 Mar 17, 2006 page 11 of 706
REJ09B0303-0300
Section 1 Overview
ADTRG/IRQ2/P40
IRQ1/P41
IRQ0/P42
φ/P46
SDA0/P47
SCL0/SCK0/P52
RES
NMI
VCC
VCL/VCC
STBY
XTAL
EXTAL
TEST
VSS/AVSS
AN0/P70
AN1/P71
AN2/P72
AN3/P73
AVCC
DrVCC
USD+
USD−
PD0/DS2D+
PD1/DS2D−
PD2/DS3D+
PD3/DS3D−
PD4/DS4D+
PD5/DS4D−
PD6/DS5D+
PD7/DS5D−
DrVSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P45
P44
P43
P51/RxD0
P50/TxD0
P10/PW0/PWX0
P11/PW1/PWX1
P12/PW2
P13/PW3
P14/PW4
VSS
P15/PW5/CBLANK
P16/PW6/SDA1
P17/PW7/SCL1
P61/FTOA/VSYNCO
P62/FTIA/TMIY/VSYNCI
P63/FTIB/TMRI0/VFBACKI
P67/TMOX/TMO1/HSYNCO
P66/FTOB/TMRI1/CSYNCI
P65/FTID/TMCI1/HSYNCI
P64/FTIC/TMO0/CLAMPO
P60/FTCI/TMCI0/TMIX/HFBACKI
EXTAL12
XTAL12
PC7/OCP5
PC6/OCP4
PC5/OCP3
PC4/OCP2
PC3/ENP5
PC2/ENP4
PC1/ENP3
PC0/ENP2
Figure 1.7 H8/3567 Group Pin Arrangement (USB On-Chip; DP-64S: Top View)
Rev. 3.00 Mar 17, 2006 page 12 of 706
REJ09B0303-0300
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P13/PW3
P14/PW4
VSS
P15/PW5/CBLANK
P16/PW6/SDA1
P17/PW7/SCL1
P61/FTOA/VSYNCO
P62/FTIA/TMIY/VSYNCI
P63/FTIB/TMRI0/VFBACKI
P67/TMOX/TMO1/HSYNCO
P66/FTOB/TMRI1/CSYNCI
P65/FTID/TMCI1/HSYNCI
P64/FTIC/TMO0/CLAMPO
P60/FTCI/TMCI0/TMIX/HFBACKI
EXTAL12
XTAL12
Section 1 Overview
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PC7/OCP5
PC6/OCP4
PC5/OCP3
PC4/OCP2
PC3/ENP5
PC2/ENP4
PC1/ENP3
PC0/ENP2
DrVSS
DS5D−/PD7
DS5D+/PD6
DS4D−/PD5
DS4D+/PD4
DS3D−/PD3
DS3D+/PD2
DS2D−/PD1
VCC
VCL/VCC
STBY
XTAL
EXTAL
TEST
VSS/AVSS
AN0/P70
AN1/P71
AN2/P72
AN3/P73
AVCC
DrVCC
USD+
USD−
PD0/DS2D+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
PW2/P12
PWX1/PW1/P11
PWX0/PW0/P10
TxD0/P50
RxD0/P51
P43
P44
P45
ADTRG/IRQ2/P40
IRQ1/P41
IRQ0/P42
φ/P46
SDA0/P47
SCL0/SCK0/P52
RES
NMI
Figure 1.8 H8/3567 Group Pin Arrangement (USB On-Chip; FP-64A: Top View)
Rev. 3.00 Mar 17, 2006 page 13 of 706
REJ09B0303-0300
Section 1 Overview
1.3.2
List of Pin Functions
H8/3577 Group pin functions are listed in table 1.2, and H8/3567 Group pin functions in tables 1.3
and 1.4.
Table 1.2
List of H8/3577 Group Pin Functions
Pin No.
Pin Name
DP-64S
FP-64A
Single-Chip Mode
PROM Writer Mode
1
57
P40/IRQ2/ADTRG
EA16
2
58
P41/IRQ1
EA15
3
59
P42/IRQ0
PGM
4
60
P43
NC
5
61
P44
NC
6
62
P45
NC
7
63
P46/φ
NC
8
64
P47/SDA0
NC
9
1
P50/TxD0
NC
10
2
P51/RxD0
NC
11
3
P52/SCK0/SCL0
NC
12
4
RES
VPP
13
5
NMI
EA9
14
6
VCL, VCC (ZTAT)
VCC
15
7
STBY
VSS
16
8
VSS
VSS
17
9
XTAL
NC
18
10
EXTAL
NC
19
11
MD1
VSS
20
12
MD0
VSS
21
13
AVSS
VSS
22
14
P70/AN0
NC
23
15
P71/AN1
NC
24
16
P72/AN2
NC
25
17
P73/AN3
NC
Rev. 3.00 Mar 17, 2006 page 14 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
Pin Name
DP-64S
FP-64A
Single-Chip Mode
PROM Writer Mode
26
18
P74/AN4
NC
27
19
P75/AN5
NC
28
20
P76/AN6
NC
29
21
P77/AN7
NC
30
22
AVCC
VCC
31
23
P60/FTCI/TMCI0/HFBACKI/TMIX
NC
32
24
P61/FTOA/VSYNCO
NC
33
25
P62/FTIA/VSYNCI/TMIY
NC
34
26
P63/FTIB/TMRI0/VFBACKI
VCC
35
27
P64/FTIC/TMO0/CLAMPO
VCC
36
28
P65/FTID/TMCI1/HSYNCI
NC
37
29
P66/FTOB/TMRI1/CSYNCI
NC
38
30
P67/TMO1/TMOX/HSYNCO
NC
39
31
VCC
VCC
40
32
P27/PW15/CBLANK
CE
41
33
P26/PW14
EA14
42
34
P25/PW13
EA13
43
35
P24/PW12/SCL1
EA12
44
36
P23/PW11/SDA1
EA11
45
37
P22/PW10
EA10
46
38
P21/PW9
OE
47
39
P20/PW8
EA8
48
40
VSS
VSS
49
41
P17/PW7
EA7
50
42
P16/PW6
EA6
51
43
P15/PW5
EA5
52
44
P14/PW4
EA4
53
45
P13/PW3
EA3
54
46
P12/PW2
EA2
55
47
P11/PW1/PWX1
EA1
Rev. 3.00 Mar 17, 2006 page 15 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
Pin Name
DP-64S
FP-64A
Single-Chip Mode
PROM Writer Mode
56
48
P10/PW0/PWX0
EA0
57
49
P30
EO0
58
50
P31
EO1
59
51
P32
EO2
60
52
P33
EO3
61
53
P34
EO4
62
54
P35
EO5
63
55
P36
EO6
64
56
P37
EO7
Rev. 3.00 Mar 17, 2006 page 16 of 706
REJ09B0303-0300
Section 1 Overview
Table 1.3
List of H8/3567 Group Pin Functions (No USB)
Pin No.
Pin Name
DP-42S
FP-44A
Single-Chip Mode
PROM Writer Mode
1
40
P40/IRQ2/ADTRG
EA16
2
41
P41/IRQ1
CE
3
42
P42/IRQ0
PGM
4
43
P46/φ
EA11
5
44
P47/SDA0
VCC
6
1
P52/SCK0/SCL0
VCC
7
2
RES
VPP
8
3
NMI
EA9
9
4
VCC
VCC
10
5
VCL, VCC (ZTAT)
VCC
11
6
STBY
VSS
12
7
XTAL
NC
13
8
EXTAL
NC
14
9
TEST
VSS
15
10
AVSS/VSS
VSS
16
11
P70/AN0
EA12
17
12
P71/AN1
EA13
18
13
P72/AN2
EA14
19
14
P73/AN3
EA15
20
15
AVCC
VCC
21
16
P60/FTCI/TMCI0/HFBACKI/TMIX
EO0
—
17
NC
NC
22
18
P64/FTIC/TMO0/CLAMPO
EO4
23
19
P65/FTID/TMCI1/HSYNCI
EO5
24
20
P66/FTOB/TMRI1/CSYNCI
EO6
25
21
P67/TMO1/TMOX/HSYNCO
EO7
26
22
P63/FTIB/TMRI0/VFBACKI
EO3
27
23
P62/FTIA/VSYNCI/TMIY
EO2
28
24
P61/FTOA/VSYNCO
EO1
Rev. 3.00 Mar 17, 2006 page 17 of 706
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Section 1 Overview
Pin No.
Pin Name
DP-42S
FP-44A
Single-Chip Mode
PROM Writer Mode
29
25
P17/PW7/SCL1
EA7
30
26
P16/PW6/SDA1
EA6
31
27
P15/PW5/CBLANK
EA5
32
28
VSS
VSS
33
29
P14/PW4
EA4
34
30
P13/PW3
EA3
35
31
P12/PW2
EA2
36
32
P11/PW1/PWX1
EA1
37
33
P10/PW0/PWX0
EA0
38
34
P50/TxD0
NC
39
35
P51/RxD0
NC
40
36
P43
EA8
41
37
P44
OE
42
38
P45
EA10
—
39
NC
NC
Rev. 3.00 Mar 17, 2006 page 18 of 706
REJ09B0303-0300
Section 1 Overview
Table 1.4
List of H8/3567 Group Pin Functions (USB On-Chip)
Pin No.
Pin Name
DP-64S
FP-64A
Single-Chip Mode
PROM Writer Mode
1
57
P40/IRQ2/ADTRG
EA16
2
58
P41/IRQ1
CE
3
59
P42/IRQ0
PGM
4
60
P46/φ
EA11
5
61
P47/SDA0
VCC
6
62
P52/SCK0/SCL0
VCC
7
63
RES
VPP
8
64
NMI
EA9
9
1
VCC
VCC
10
2
VCL, VCC (ZTAT)
VCC
11
3
STBY
VSS
12
4
XTAL
NC
13
5
EXTAL
NC
14
6
TEST
VSS
15
7
AVSS/VSS
VSS
16
8
P70/AN0
EA12
17
9
P71/AN1
EA13
18
10
P72/AN2
EA14
19
11
P73/AN3
EA15
20
12
AVCC
VCC
21
13
DrVCC
VCC
22
14
USD+
NC
23
15
USD–
NC
24
16
PD0/DS2D+
NC
25
17
PD1/DS2D–
NC
26
18
PD2/DS3D+
NC
27
19
PD3/DS3D–
NC
28
20
PD4/DS4D+
NC
29
21
PD5/DS4D–
NC
Rev. 3.00 Mar 17, 2006 page 19 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
Pin Name
DP-64S
FP-64A
Single-Chip Mode
PROM Writer Mode
30
22
PD6/DS5D+
NC
31
23
PD7/DS5D–
NC
32
24
DrVSS
VSS
33
25
PC0/ENP2
NC
34
26
PC1/ENP3
NC
35
27
PC2/ENP4
NC
36
28
PC3/ENP5
NC
37
29
PC4/OCP2
NC
38
30
PC5/OCP3
NC
39
31
PC6/OCP4
NC
40
32
PC7/OCP5
NC
41
33
XTAL12
NC
42
34
EXTAL12
NC
43
35
P60/FTCI/TMCI0/HFBACKI/TMIX
EO0
44
36
P64/FTIC/TMO0/CLAMPO
EO4
45
37
P65/FTID/TMCI1/HSYNCI
EO5
46
38
P66/FTOB/TMRI1/CSYNCI
EO6
47
39
P67/TMO1/TMOX/HSYNCO
EO7
48
40
P63/FTIB/TMRI0/VFBACKI
EO3
49
41
P62/FTIA/VSYNCI/TMIY
EO2
50
42
P61/FTOA/VSYNCO
EO1
51
43
P17/PW7/SCL1
EA7
52
44
P16/PW6/SDA1
EA6
53
45
P15/PW5/CBLANK
EA5
54
46
VSS
VSS
55
47
P14/PW4
EA4
56
48
P13/PW3
EA3
57
49
P12/PW2
EA2
58
50
P11/PW1/PWX1
EA1
59
51
P10/PW0/PWX0
EA0
Rev. 3.00 Mar 17, 2006 page 20 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
Pin Name
DP-64S
FP-64A
Single-Chip Mode
PROM Writer Mode
60
52
P50/TxD0
NC
61
53
P51/RxD0
NC
62
54
P43
EA8
63
55
P44
OE
64
56
P45
EA10
Rev. 3.00 Mar 17, 2006 page 21 of 706
REJ09B0303-0300
Section 1 Overview
1.3.3
Pin Functions
Table 1.5 summarizes the functions of the H8/3577 Group and H8/3567 Group pins.
Table 1.5
Pin Functions
Pin No.
H8/3567
Group
(No USB)
H8/3577
Group
H8/3567
Group (USB
On-Chip)
Type
Symbol
DP64S
FP64A
DP42S
FP44A
DP64S
FP64A
I/O
Name and Function
Power
VCC
39
31
9
4
9
1
Input
Power: For connection to the
power supply (5 V).
VCL/VCC
14
6
10
5
10
2
Input
Internal step-up power: For
connection to an external
capacitor. In the ZTAT
version, connect this pin to
the power supply (5 V).
Clock
Operating
mode
control
System
control
VSS
16,
48
8,
40
32
28
15,
54
7,
46
Input
Ground: For connection to
the power supply (0 V).
Connect all VSS pins to the
system power supply (0 V).
XTAL
17
9
12
7
12
4
Input
For connection of a crystal
resonator or external clock
input.
EXTAL
18
10
13
8
13
5
Input
For connection examples, see
section 20, Clock Pulse
Generator.
φ
7
63
4
43
4
60
Output
System clock: Supplies the
system clock to external
devices.
—
—
—
—
Input
Mode pins: These pins set
the operating mode. Connect
all three pins—MD1, MD0, and
TEST—to the power supply
(5 V).
MD1
19
11
MD0
20
12
TEST
—
—
14
9
14
6
RES
12
4
7
2
7
63
Input
Reset input: When this pin is
driven low, the chip goes to
the reset state.
STBY
15
7
11
6
11
3
Input
Standby: When this pin is
driven low, a transition is
made to hardware standby
mode.
Rev. 3.00 Mar 17, 2006 page 22 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
H8/3567
Group
(No USB)
H8/3577
Group
H8/3567
Group (USB
On-Chip)
Type
Symbol
DP64S
FP64A
DP42S
FP44A
DP64S
FP64A
I/O
Name and Function
Interrupts
NMI
13
5
8
3
8
64
Input
Nonmaskable interrupt:
Requests a nonmaskable
interrupt.
IRQ0 to
IRQ2
3 to
1
59 to
57
3 to
1
42 to
40
3 to
1
59 to Input
57
Interrupt request 0 to 2:
These pins request a
maskable interrupt.
31
23
21
16
43
35
Input
FRT counter clock input:
Pin that inputs an external
clock signal to the freerunning counter (FRC).
FTOA
32
24
28
24
50
42
Output
FRT output compare A
output: The output compare
A output pin.
FTOB
37
29
24
20
46
38
Output
FRT output compare B
output: The output compare
B output pin.
FTIA
33
25
27
23
49
41
Input
FRT input capture A input:
The input capture A input pin.
FTIB
34
26
26
22
48
40
Input
FRT input capture B input:
The input capture B input pin.
FTIC
35
27
22
18
44
36
Input
FRT input capture C input:
The input capture C input pin.
FTID
36
28
23
19
45
37
Input
FRT input capture D input:
The input capture D input pin.
TMO0
35
27
22
18
44
36
Output
TMO1
38
30
25
21
47
39
Compare-match output:
Compare-match output pins
for TMR0, TMR1, and TMRX.
TMOX
38
30
25
21
47
39
Input
Counter external clock
input: Pins that input an
external clock to the TMR0
and TMR1 counters.
Input
Counter external reset
input: TMR0 and TMR1
counter reset input pins.
16-bit free- FTCI
running timer
(FRT)
8-bit timer
(TMR0,
TMR1,
TMRX,
TMRY)
TMCI0
31
23
21
16
43
35
TMCI1
36
28
23
19
45
37
TMRI0
34
26
26
22
48
40
TMRI1
37
29
24
20
46
38
Rev. 3.00 Mar 17, 2006 page 23 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
H8/3567
Group
(No USB)
H8/3577
Group
H8/3567
Group (USB
On-Chip)
Type
Symbol
DP64S
FP64A
DP42S
FP44A
DP64S
FP64A
I/O
Name and Function
8-bit timer
(TMR0,
TMR1,
TMRX,
TMRY)
TMIX
31
23
21
16
43
35
Input
TMIY
33
25
27
23
49
41
Counter external clock
input/reset input: Pins with a
dual function of TMRX and
TMRY counter clock input and
reset input.
Serial communication
interface
(SCI0)
TxD0
9
1
38
34
60
52
Output
Transmit data: Data output
pins.
RxD0
10
2
39
35
61
53
Input
Receive data: Data input
pins.
SCK0
11
3
6
1
6
62
Input/
output
Serial clock: Clock
input/output pins.
The SCK0 output type is
NMOS push-pull.
A/D
converter
AN7 to
AN4
29 to 21 to
26
18
—
—
—
—
Input
Analog 7 to 0: Analog input
pins.
AN3 to
AN0
25 to 17 to
22
14
19 to 14 to
16
11
19 to 11 to Input
16
8
ADTRG
1
57
1
40
1
57
Input
A/D conversion external
trigger input: Pin for input of
an external trigger to start A/D
conversion.
AVCC
30
22
20
15
20
12
Input
Analog power: The A/D
converter reference power
supply pin.
When the A/D converter is not
used, connect this pin to the
system power supply (+5 V).
AVSS
21
13
15
Rev. 3.00 Mar 17, 2006 page 24 of 706
REJ09B0303-0300
10
15
7
Input
Analog ground: The A/D
converter ground pin.
Connect this pin to the system
power supply (0 V).
Section 1 Overview
Pin No.
H8/3567
Group
(No USB)
H8/3577
Group
Type
Symbol
DP64S
PWM timer
(PWM)
PW15 to
PW8
PW7 to
PW0
14-bit
PWM timer
(PWMX)
Timer
connection
2
I C bus
interface
(IIC)
FP64A
H8/3567
Group (USB
On-Chip)
DP42S
FP44A
DP64S
FP64A
I/O
Name and Function
40 to 32 to
47
39
—
—
—
—
Output
PWM timer output: PWM
timer pulse output pins.
49 to 41 to
56
48
29 to 25 to
31
27
51 to 43 to
53
45
33 to 29 to
37
33
55 to 47 to
59
51
Output
PWMX timer output: PWM
D/A pulse output pins.
Input
Timer connection input:
Timer connection
synchronization signal input
pins.
Output
Timer connection output:
Timer connection
synchronization signal output
pins.
Input/
Output
I2C clock input/output
(channels 0 and 1): I2C clock
input/output pins.
PWX0
56
48
37
33
59
51
PWX1
55
47
36
32
58
50
VSYNCI
33
25
27
23
49
41
HSYNCI
36
28
23
19
45
37
CSYNCI
37
29
24
20
46
38
VFBACKI
34
26
26
22
48
40
HFBACKI
31
23
21
16
43
35
VSYNCO
32
24
28
24
50
42
HSYNCO
38
30
25
21
47
39
CLAMPO
35
27
22
18
44
36
CBLANK
40
32
31
27
53
45
SCL0
11
3
6
1
6
62
SCL1
43
35
29
25
51
43
These pins have a bus drive
function.
The SCL0 output type is
NMOS open-drain.
SDA0
8
64
5
44
5
61
SDA1
44
36
30
26
52
44
Input/
Output
I2C data input/output
(channels 0 and 1): I2C data
input/output pins.
These pins have a bus drive
function.
The SDA0 output type is
NMOS open-drain.
Rev. 3.00 Mar 17, 2006 page 25 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
H8/3577
Group
H8/3567
Group
(No USB)
H8/3567
Group (USB
On-Chip)
Type
Symbol
DP64S
FP64A
DP42S
FP44A
DP64S
FP64A
Universal
serial bus
(USB)
USD+
—
—
—
—
22
14
23
15
USD–
DS2D+
24
16
DS2D–
—
—
—
—
25
17
DS3D+
26
18
DS3D–
27
19
DS4D+
28
20
DS4D–
29
21
DS5D+
30
22
DS5D–
31
23
I/O
Name and Function
Input/
Output
Upstream data input/output:
USB upstream data input/
output pins.
Input/
Output
Upstream data input/output
2 to 5: USB hub downstream
data input/output pins.
ENP2 to
ENP5
—
—
—
—
33 to 25 to Output
36
28
Power supply control IC
power output enable signal
output: Output pins to USB
port power supply control IC
enable input
OCP2 to
OCP5
—
—
—
—
37 to 29 to Input
40
32
Overcurrent detection
signal input: Input pins for
overcurrent detection signal
from USB port power supply
control IC
XTAL12
—
—
—
—
41
33
Input
EXTAL12
—
—
—
—
42
34
Input
USB clock input: For
connection of a 12 MHz
crystal resonator or external
clock input. Quadrupled to
48 MHz inside the chip.
DrVCC
—
—
—
—
21
13
Input
Bus driver power: For
connection of the bus
driver/receiver power supply
(3.3 V).
DrVSS
—
—
—
—
32
24
Input
Bus driver ground: For
connection of the bus
driver/receiver power supply
(0 V).
Rev. 3.00 Mar 17, 2006 page 26 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
H8/3567
Group
(No USB)
H8/3577
Group
Type
Symbol
DP64S
FP64A
I/O ports
P17 to
P10
49 to 41 to
56
48
DP42S
FP44A
H8/3567
Group (USB
On-Chip)
DP64S
FP64A
I/O
29 to 25 to
31
27
51 to 43 to Input/
53
45
Output
33 to 29 to
37
33
55 to 47 to
59
51
Name and Function
Port 1: Eight input/output
pins. The direction of each pin
can be selected in the port 1
data direction register
(P1DDR).
P27 to
P20
40 to 32 to
47
39
—
—
—
—
Input/
Output
Port 2: Eight input/output
pins. The direction of each pin
can be selected in the port 2
data direction register
(P2DDR).
P37 to
P30
64 to 56 to
57
49
—
—
—
—
Input/
Output
Port 3: Eight input/output
pins. The direction of each pin
can be selected in the port 3
data direction register
(P3DDR).
P47 to
P40
8 to
1
5,
4
44, 43
5,
4
61, 60 Input/
56 to Output
Port 4: Eight input/output
pins. The direction of each pin
(except P46) can be selected
in the port 4 data direction
register (P4DDR). P47 is an
NMOS push-pull output.
P52 to
P50
P67 to
P60
64 to
57
11 to 3 to
9
1
38 to 30 to
31
23
38 to
42 to 36
40
42 to
3 to 40
1
64 to 54
62
59 to
3 to 57
1
6
1
6
62
39
35
61
53
38
34
60
52
Input/
Output
Port 5: Three input/output
pins. The direction of each pin
can be selected in the port 5
data direction register
(P5DDR). P52 is an NMOS
push-pull output.
25 to 21 to
22
18
47 to 39 to Input/
44
36
Output
26 to 22 to
28
24
48 to 40 to
50
42
Port 6: Eight input/output
pins. The direction of each pin
can be selected in the port 6
data direction register
(P6DDR).
21
16
43
35
—
—
—
P77 to
P74
29 to 21 to
26
18
—
P73 to
P70
25 to 17 to
22
14
19 to 14 to
16
11
19 to 11 to
16
8
Input
Port 7: Eight (H8/3577
Group) or four (H8/3567
Group) input pins.
Rev. 3.00 Mar 17, 2006 page 27 of 706
REJ09B0303-0300
Section 1 Overview
Pin No.
H8/3577
Group
H8/3567
Group
(No USB)
H8/3567
Group (USB
On-Chip)
DP64S
FP64A
DP42S
FP44A
DP64S
PC7 to
PC0
—
—
—
—
40 to 32 to Input/
33
25
Output
Port C: Eight input/output
pins. The direction of each pin
can be selected in the port C
data direction register
(PCDDR).
PD7 to
PD0
—
—
—
—
31 to 23 to Input/
24
16
Output
Port D: Eight input/output
pins. The direction of each pin
can be selected in the port D
data direction register
(PDDDR). These pins are
driven by DrVCC (3.3 V).
Type
Symbol
I/O ports
Rev. 3.00 Mar 17, 2006 page 28 of 706
REJ09B0303-0300
FP64A
I/O
Name and Function
Section 2 CPU
Section 2 CPU
2.1
Overview
The H8/300 CPU has sixteen 8-bit general registers, which can also be paired as eight 16-bit
registers. Its concise instruction set is designed for high-speed operation.
2.1.1
Features
Features of the H8/300 CPU are listed below.
• General-register architecture
Sixteen 8-bit general registers, also usable as eight 16-bit general registers
• Instruction set with 55 basic instructions, including:
 Multiply and divide instructions
 Powerful bit-manipulation instructions
• Eight addressing modes
 Register direct (Rn)
 Register indirect (@Rn)
 Register indirect with displacement (@(d:16, Rn))
 Register indirect with post-increment or pre-decrement (@Rn+/@–Rn)
 Absolute address (@aa:8/@aa:16)
 Immediate (#xx:8/#xx:16)
 Program-counter relative (@(d:8, PC))
 Memory indirect (@@aa:8)
• 64-kbyte address space
• High-speed operation
 All frequently used instructions are executed in two to four states
 High-speed arithmetic and logic operations
8- or 16-bit register-register add or subtract: 0.1 µs (operating at φ = 20 MHz)
8 × 8-bit multiply:
0.7 µs (operating at φ = 20 MHz)
16 ÷ 8-bit divide:
0.7 µs (operating at φ = 20 MHz)
• Low-power operation modes
SLEEP instruction for transfer to low-power operation
Rev. 3.00 Mar 17, 2006 page 29 of 706
REJ09B0303-0300
Section 2 CPU
2.1.2
Address Space
The H8/300 CPU supports an address space of up to 64 kbytes for storing program code and data.
See section 3.3, Address Map, for details of the memory map.
2.1.3
Register Configuration
Figure 2.1 shows the register structure of the H8/300 CPU. There are two groups of registers: the
general registers and control registers.
General registers (Rn)
7
0 7
0
R0H
R0L
R1H
R1L
R2H
R2L
R3H
R3L
R4H
R4L
R5H
R5L
R6H
R6L
R7H
(SP)
R7L
Control registers (CR)
15
0
PC
CCR
7 6 5 4 3 2 1 0
I UHUNZ VC
Carry flag
Overflow flag
Zero flag
Negative flag
Legend:
SP: Stack pointer
PC: Program counter
CCR: Condition code register
Figure 2.1 CPU Registers
Rev. 3.00 Mar 17, 2006 page 30 of 706
REJ09B0303-0300
Half-carry flag
Interrupt mask bit
User bit
User bit
Section 2 CPU
2.2
Register Descriptions
2.2.1
General Registers
All the general registers can be used as both data registers and address registers.
When used as data registers, they can be accessed as 16-bit registers (R0 to R7), or the high bytes
(R0H to R7H) and low bytes (R0L to R7L) can be accessed separately as 8-bit registers.
When used as address registers, the general registers are accessed as 16-bit registers (R0 to R7).
R7 also functions as the stack pointer (SP), used implicitly by hardware in exception processing
and subroutine calls. When it functions as the stack pointer, as indicated in figure 2.2, SP (R7)
points to the top of the stack.
Lower address side [H'0000]
Unused area
SP (R7)
Stack area
Upper address side [H'FFFF]
Figure 2.2 Stack Pointer
2.2.2
Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
Program Counter (PC)
This 16-bit register indicates the address of the next instruction the CPU will execute. All
instructions are fetched 16 bits (1 word) at a time, so the least significant bit of the PC is ignored
(always regarded as 0).
Rev. 3.00 Mar 17, 2006 page 31 of 706
REJ09B0303-0300
Section 2 CPU
Condition Code Register (CCR)
This 8-bit register contains internal status information, including the interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. These bits can be read
and written by software (using the LDC, STC, ANDC, ORC, and XORC instructions). The N, Z,
V, and C flags are used as branching conditions for conditional branching (Bcc) instructions.
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, interrupts are masked. This bit is set to 1
automatically at the start of exception handling. The interrupt mask bit may be read and written by
software. For further details, see section 5, Interrupt Controller.
Bit 6—User Bit (U): Can be used freely by the user.
Bit 5—Half-Carry Flag (H): When the ADD.B, ADDX.B, SUB.B, SUBX.B, CMP.B, or NEG.B
instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and is cleared to 0
otherwise.
The H flag is used implicitly by the DAA and DAS instructions.
When the ADD.W, SUB.W, or CMP.W instruction is executed, the H flag is set to 1 if there is a
carry or borrow at bit 11, and is cleared to 0 otherwise.
Bit 4—User Bit (U): Can be used freely by the user.
Bit 3—Negative Flag (N): Indicates the most significant bit (sign bit) of the result of an
instruction.
Bit 2—Zero Flag (Z): Set to 1 to indicate a zero result, and cleared to 0 to indicate a non-zero
result.
Bit 1—Overflow Flag (V): Set to 1 when an arithmetic overflow occurs, and cleared to 0 at other
times.
Bit 0—Carry Flag (C): Set to 1 when a carry occurs, and cleared to 0 otherwise. Used by:
• Add instructions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift/rotate carry
The carry flag is also used as a bit accumulator by bit manipulation instructions.
Some instructions leave some or all of the flag bits unchanged.
Rev. 3.00 Mar 17, 2006 page 32 of 706
REJ09B0303-0300
Section 2 CPU
Refer to the H8/300 Series Programming Manual for the action of each instruction on the flag
bits.
2.2.3
Initial Register Values
In reset exception handling, the program counter (PC) is initialized by a vector address (H'0000)
load, and the I bit in the CCR is set to 1. The other CCR bits and the general registers are not
initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer should be
initialized by software, by the first instruction executed after a reset.
2.3
Data Formats
The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
1-bit data is handled by bit manipulation instructions, and is accessed by being specified as bit n (n
= 0, 1, 2, ... 7) in the operand data (byte).
Byte data is handled by all arithmetic and logic instructions except ADDS and SUBS. Word data
is handled by the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits),
and DIVXU (16 bits ÷ 8 bits) instructions.
With the DAA and DAS decimal adjustment instructions, byte data is handled as two 4-bit BCD
data units.
Rev. 3.00 Mar 17, 2006 page 33 of 706
REJ09B0303-0300
Section 2 CPU
2.3.1
Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2.3.
Data Type
Register No.
Data Format
7
1-bit data
RnH
7
0
6
5
4
3
2
1
0
don’t care
7
1-bit data
RnL
Byte data
RnH
Byte data
RnL
Word data
Rn
4-bit BCD data
RnH
don’t care
7
7
0
MSB
LSB
don’t care
0
6
5
3
2
1
0
don’t care
7
0
MSB
LSB
15
0
MSB
LSB
7
4
3
Upper digit
0
Lower digit
don’t care
7
4-bit BCD data
4
RnL
don’t care
4
Upper digit
Legend:
RnH: Upper byte of general register
RnL: Lower byte of general register
MSB: Most significant bit
LSB: Least significant bit
Figure 2.3 General Register Data Formats
Rev. 3.00 Mar 17, 2006 page 34 of 706
REJ09B0303-0300
0
3
Lower digit
Section 2 CPU
2.3.2
Memory Data Formats
Figure 2.4 indicates the data formats in memory. For access by the H8/300L CPU, word data
stored in memory must always begin at an even address. When word data beginning at an odd
address is accessed, the least significant bit is regarded as 0, and the word data beginning at the
preceding address is accessed. The same applies to instruction codes.
Data Type
Address
Data Format
7
1-bit data
Address n
7
Byte data
Address n
MSB
Even address
MSB
Word data
Odd address
Byte data (CCR) on stack
Word data on stack
0
6
5
4
3
2
1
0
LSB
Upper 8 bits
Lower 8 bits
LSB
Even address
MSB
CCR
LSB
Odd address
MSB
CCR*
LSB
Even address
MSB
Odd address
LSB
Legend:
CCR: Condition code register
Note: * Ignored on return
Figure 2.4 Memory Data Formats
When the stack is accessed using R7 as an address register, word access should always be
performed. The CCR is stored as word data with the same value in the upper 8 bits and the lower 8
bits. On return, the lower 8 bits are ignored.
Rev. 3.00 Mar 17, 2006 page 35 of 706
REJ09B0303-0300
Section 2 CPU
2.4
Addressing Modes
2.4.1
Addressing Modes
The H8/300 CPU supports the eight addressing modes listed in table 2.1. Each instruction uses a
subset of these addressing modes.
Table 2.1
Addressing Modes
No.
Address Modes
Symbol
1
Register direct
Rn
2
Register indirect
@Rn
3
Register indirect with displacement
@(d:16, Rn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@Rn+
@–Rn
5
Absolute address
@aa:8 or @aa:16
6
Immediate
#xx:8 or #xx:16
7
Program-counter relative
@(d:8, PC)
8
Memory indirect
@@aa:8
1. Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand.
Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
2. Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand in memory.
3. Register Indirect with Displacement—@(d:16, Rn): The instruction has a second word
(bytes 3 and 4) containing a displacement which is added to the contents of the specified
general register to obtain the operand address in memory.
This mode is used only in MOV instructions. For the MOV.W instruction, the resulting
address must be even.
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4. Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
•
Register indirect with post-increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
The register field of the instruction specifies a 16-bit general register containing the address
of the operand. After the operand is accessed, the register is incremented by 1 for MOV.B
or 2 for MOV.W, and the result of the addition is stored in the register. For MOV.W, the
original contents of the 16-bit general register must be even.
•
Register indirect with pre-decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
The register field of the instruction specifies a 16-bit general register which is decremented
by 1 or 2 to obtain the address of the operand in memory. The register retains the
decremented value. The size of the decrement is 1 for MOV.B or 2 for MOV.W. For
MOV.W, the original contents of the register must be even.
5. Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory.
The absolute address may be 8 bits long (@aa:8) or 16 bits long (@aa:16). The MOV.B and bit
manipulation instructions can use 8-bit absolute addresses. The MOV.B, MOV.W, JMP, and
JSR instructions can use 16-bit absolute addresses.
For an 8-bit absolute address, the upper 8 bits are assumed to be 1 (H'FF). The address range is
H'FF00 to H'FFFF (65280 to 65535).
6. Immediate—#xx:8 or #xx:16: The second byte (#xx:8) or the third and fourth bytes (#xx:16)
of the instruction code are used directly as the operand. Only MOV.W instructions can be used
with #xx:16.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data. Some
bit manipulation instructions contain 3-bit immediate data in the second or fourth byte of the
instruction, specifying a bit number.
7. Program-Counter Relative—@(d:8, PC): This mode is used in the Bcc and BSR
instructions. An 8-bit displacement in byte 2 of the instruction code is sign-extended to 16 bits
and added to the program counter contents to generate a branch destination address, and the PC
contents to be added are the start address of the next instruction, so that the possible branching
range is –126 to +128 bytes (–63 to +64 words) from the branch instruction. The displacement
should be an even number.
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8. Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address. This specifies an
operand in memory, and a branch is performed with the contents of this operand as the branch
address.
The upper 8 bits of the absolute address are assumed to be 0 (H'00), so the address range is
from H'0000 to H'00FF (0 to 255). Note that with the H8/300 Series, the lower end of the
address area is also used as a vector area. See section 4, Exception Handling, for details on the
vector area.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at the
address preceding the specified address. See 2.3.2, Memory Data Formats, for further information.
2.4.2
Effective Address Calculation
Table 2.2 shows how effective addresses are calculated in each of the addressing modes.
Arithmetic and logic instructions use register direct addressing (1). The ADD.B, ADDX, SUBX,
CMP.B, AND, OR, and XOR instructions can also use immediate addressing (6).
Data transfer instructions can use all addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute
addressing (5) to specify a byte operand, and 3-bit immediate addressing (6) to specify a bit
position in that byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct
addressing (1) to specify the bit position.
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Table 2.2
No.
1
Effective Address Calculation
Addressing Mode and
Instruction Format
Effective Address
Calculation Method
Effective Address (EA)
3
Register direct, Rn
0
rm
15
87
op
2
43
rm
rn
3
76 43
15
0
15
0
15
0
15
0
15
0
0
rm
Register indirect with
displacement, @(d:16, Rn)
15
rn
Operand is contents of
registers indicated by rm/rn
Contents (16 bits) of
register indicated by rm
op
0
0
Register indirect, @Rn
15
3
76
op
43
15
0
Contents (16 bits) of
register indicated by rm
0
rm
disp
disp
4
Register indirect with
post-increment, @Rn+
15
76
op
43
15
0
Contents (16 bits) of
register indicated by rm
0
rm
1 or 2
Register indirect with
pre-decrement, @–Rn
15
76
op
43
rm
15
0
Contents (16 bits) of
register indicated by rm
0
Incremented or
decremented by 1 if
operand is byte size, 1 or 2
and by 2 if word size
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Section 2 CPU
No.
5
Addressing Mode and
Instruction Format
Effective Address
Calculation Method
Effective Address (EA)
Absolute address
@aa:8
15
87
op
15
87
0
H'FF
0
abs
@aa:16
15
15
0
0
op
abs
6
Immediate
#xx:8
15
Operand is 1- or 2-byte
immediate data
87
op
0
IMM
#xx:16
15
0
op
IMM
7
Program-counter relative
@(d:8, PC)
87
15
op
15
0
disp
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REJ09B0303-0300
0
PC contents
15
Sign
extension
disp
0
Section 2 CPU
No.
Addressing Mode and
Instruction Format
8
Memory indirect, @@aa:8
15
87
op
Effective Address
Calculation Method
Effective Address (EA)
0
abs
15
87
H'00
0
abs
15
0
Memory contents
(16 bits)
Legend:
rm, rn: Register field
op:
Operation field
disp: Displacement
IMM: Immediate data
abs: Absolute address
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Section 2 CPU
2.5
Instruction Set
The H8/300 Series can use a total of 55 instructions, which are grouped by function in table 2.3.
Table 2.3
Instruction Set
Function
Instructions
Number
Data transfer
MOV, PUSH* , POP*
Arithmetic operations
ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,
SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG
14
Logic operations
AND, OR, XOR, NOT
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR,
ROTXL, ROTXR
8
Bit manipulation
14
Branch
BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST
2
Bcc* , JMP, BSR, JSR, RTS
System control
RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP
8
Block data transfer
(Cannot be used in the
H8/3577 Group and
H8/3567 Group)
EEPMOV
1
1
1
1
5
Total: 55
Notes: 1. PUSH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn. The same applies to machine language.
2. Bcc is a conditional branch instruction.
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Tables 2.4 to 2.11 show the function of each instruction. The notation used is defined next.
Notation
Rd
General register (destination)
Rs
General register (source)
Rn
General register
(EAd), <Ead>
Destination operand
(EAs), <Eas>
Source operand
CCR
Condition code register
N
N (negative) flag of CCR
Z
Z (zero) flag of CCR
V
V (overflow) flag of CCR
C
C (carry) flag of CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
AND logical
∨
OR logical
⊕
Exclusive OR logical
→
Move
~
Logical negation (logical complement)
:3
3-bit length
:8
8-bit length
:16
16-bit length
( ), < >
Contents of operand indicated by effective address
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2.5.1
Data Transfer Instructions
Table 2.4 describes the data transfer instructions. Figure 2.5 shows their object code formats.
Table 2.4
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general
register and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:16, @–Rn, and @Rn+
addressing modes are available for word data. The @aa:8 addressing
mode is available for byte data only.
The @–R7 and @R7+ modes require a word-size specification.
POP
W
@SP+ → Rn
Pops a general register from the stack. Equivalent to MOV.W @SP+,
Rn.
PUSH
W
Rn → @–SP
Pushes general register onto the stack. Equivalent to MOV.W Rn,
@–SP.
Notes: *
Size: Operand size
B: Byte
W: Word
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15
8
7
0
op
rm
15
8
rn
0
rm
8
Rm→Rn
7
op
15
MOV
rn
@Rm←→Rn
7
0
op
rm
rn
@(d:16, Rm)←→Rn
disp
15
8
7
0
op
rm
15
8
op
7
0
rn
15
@Rm+→Rn, or
Rn →@–Rm
rn
abs
8
@aa:8←→Rn
7
0
op
rn
@aa:16←→Rn
abs
15
8
op
7
0
rn
15
IMM
8
#xx:8→Rn
7
0
op
rn
#xx:16→Rn
IMM
15
8
op
7
0
1
1
1
rn
PUSH, POP
@SP+ → Rn, or
Rn → @–SP
Legend:
op:
Operation field
rm, rn: Register field
disp: Displacement
abs:
Absolute address
IMM: Immediate data
Figure 2.5 Data Transfer Instruction Codes
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Section 2 CPU
2.5.2
Arithmetic Operations
Table 2.5 describes the arithmetic instructions.
Table 2.5
Arithmetic Instructions
Instruction
Size*
Function
ADD
B/W
Rd ± Rs → Rd, Rd + #IMM → Rd
SUB
ADDX
Performs addition or subtraction on data in two general registers, or
addition on immediate data and data in a general register. Immediate
data cannot be subtracted from data in a general register. Word data
can be added or subtracted only when both words are in general
registers.
B
SUBX
INC
Performs addition or subtraction with carry on data in two general
registers, or addition or subtraction with carry on immediate data and
data in a general register.
B
DEC
ADDS
Rd ± 1 → Rd, Rd ± 2 → Rd
Adds or subtracts 1 or 2 to or from a general register
B
DAS
MULXU
Rd ± 1 → Rd
Increments or decrements a general register
W
SUBS
DAA
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction
result in a general register by referring to the CCR
B
Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result
DIVXU
B
Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general
registers, providing an 8-bit quotient and 8-bit remainder
CMP
B/W
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general
register or with immediate data, and indicates the result in the CCR.
Word data can be compared only between two general registers.
NEG
B
0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a
general register
Notes: *
Size: Operand size
B: Byte
W: Word
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Section 2 CPU
2.5.3
Logic Operations
Table 2.6 describes the four instructions that perform logic operations.
Table 2.6
Logic Operation Instructions
Instruction
Size*
Function
AND
B
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data
OR
B
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data
XOR
B
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data
NOT
B
~ Rd → Rd
Obtains the one’s complement (logical complement) of general
register contents
Notes: *
2.5.4
Size: Operand size
B: Byte
Shift Operations
Table 2.7 describes the eight shift instructions.
Table 2.7
Shift Instructions
Instruction
Size*
Function
SHAL
B
Rd shift → Rd
SHAR
SHLL
Performs an arithmetic shift operation on general register contents
B
SHLR
ROTL
Performs a logical shift operation on general register contents
B
ROTR
ROTXL
ROTXR
Notes: *
Rd shift → Rd
Rd rotate → Rd
Rotates general register contents
B
Rd rotate → Rd
Rotates general register contents through the C (carry) bit
Size: Operand size
B: Byte
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Section 2 CPU
Figure 2.6 shows the instruction code format of arithmetic, logic, and shift instructions.
15
8
7
op
0
rm
15
8
7
0
op
15
7
op
0
rm
8
op
0
0
rm
8
rn
7
rn
15
ADD, ADDX, SUBX,
CMP (#XX:8)
7
op
15
MULXU, DIVXU
IMM
8
op
rn
7
rn
15
ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
rn
8
15
ADD, SUB, CMP,
ADDX, SUBX (Rm)
rn
AND, OR, XOR (Rm)
0
IMM
8
AND, OR, XOR (#xx:8)
7
op
0
rn
SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
Legend:
op:
Operation field
rm, rn: Register field
IMM: Immediate data
Figure 2.6 Arithmetic, Logic, and Shift Instruction Codes
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Section 2 CPU
2.5.5
Bit Manipulations
Table 2.8 describes the bit-manipulation instructions. Figure 2.7 shows their object code formats.
Table 2.8
Bit-Manipulation Instructions
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BNOT
B
~ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit number
is specified by 3-bit immediate data or the lower three bits of a general
register.
BTST
B
~ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory and sets or clears
the Z flag accordingly. The bit number is specified by 3-bit immediate
data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIAND
B
C ∧ [~ (<bit-No.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIOR
B
C ∨ [~ (<bit-No.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
Notes: *
Size: Operand size
B: Byte
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Section 2 CPU
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory,
and stores the result in the C flag.
BIXOR
B
C ⊕ [~(<bit-No.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general register
or memory, and stores the result in the C flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag.
BILD
B
~ (<bit-No.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or memory to
the C flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
BIST
B
~ C → (<bit-No.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
Copies the inverse of the C flag to a specified bit in a general register
or memory.
The bit number is specified by 3-bit immediate data.
Notes: *
Size: Operand size
B: Byte
Certain precautions are required in bit manipulation. See 2.8.1, Notes on Bit Manipulation, for
details.
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BSET, BCLR, BNOT, BTST
15
8
7
op
0
IMM
15
8
7
op
0
rm
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
Operand: register direct (Rn)
Bit No.: register direct (Rm)
rn
7
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
op
rn
0
0
0
0 Operand: register indirect (@Rn)
op
rm
0
0
0
0 Bit No.:
op
op
15
8
15
8
7
0
7
abs
IMM
15
8
0
Operand: absolute (@aa:8)
0
0
7
0 Bit No.:
immediate (#xx:3)
0
op
abs
op
register direct (Rm)
0
op
op
immediate (#xx:3)
rm
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
register direct (Rm)
BAND, BOR, BXOR, BLD, BST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Legend:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes
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BIAND, BIOR, BIXOR, BILD, BIST
15
8
7
op
0
IMM
15
8
7
op
op
15
8
Operand: register direct (Rn)
Bit No.: immediate (#xx:3)
rn
0
rn
0
0
0
0 Operand: register indirect (@Rn)
IMM
0
0
0
0 Bit No.:
7
0
op
abs
op
immediate (#xx:3)
IMM
0
Operand: absolute (@aa:8)
0
0
0 Bit No.:
immediate (#xx:3)
Legend:
op:
Operation field
rm, rn: Register field
abs:
Absolute address
IMM: Immediate data
Figure 2.7 Bit Manipulation Instruction Codes (cont)
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2.5.6
Branching Instructions
Table 2.9 describes the branching instructions. Figure 2.8 shows their object code formats.
Table 2.9
Branching Instructions
Instruction
Size
Function
Bcc
—
Branches to the designated address if condition cc is true. The
branching conditions are given below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear (high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address
BSR
—
Branches to a subroutine at a specified address
JSR
—
Branches to a subroutine at a specified address
RTS
—
Returns from a subroutine
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15
8
op
7
0
cc
15
disp
8
7
op
0
rm
15
Bcc
8
0
0
0
7
0
JMP (@Rm)
0
op
JMP (@aa:16)
abs
15
8
7
0
op
abs
15
8
JMP (@@aa:8)
7
0
op
disp
15
8
7
op
0
rm
15
BSR
8
0
0
0
7
0
JSR (@Rm)
0
op
JSR (@aa:16)
abs
15
8
7
op
0
abs
15
8
7
op
Legend:
op: Operation field
cc: Condition field
rm: Register field
disp: Displacement
abs: Absolute address
Figure 2.8 Branching Instruction Codes
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JSR (@@aa:8)
0
RTS
Section 2 CPU
2.5.7
System Control Instructions
Table 2.10 describes the system control instructions. Figure 2.9 shows their object code formats.
Table 2.10 System Control Instructions
Instruction
Size*
Function
RTE
—
Returns from an exception-handling routine
SLEEP
—
Causes a transition from active mode to a power-down mode. See
section 21, Power-Down State, for details.
LDC
B
Rs → CCR, #IMM → CCR
Moves immediate data or general register contents to the condition
code register
STC
B
CCR → Rd
ANDC
B
CCR ∧ #IMM → CCR
Copies the condition code register to a specified general register
Logically ANDs the condition code register with immediate data
ORC
B
CCR ∨ #IMM → CCR
Logically ORs the condition code register with immediate data
XORC
B
CCR ⊕ #IMM → CCR
Logically exclusive-ORs the condition code register with immediate
data
NOP
—
PC + 2 → PC
Only increments the program counter
Notes: *
Size: Operand size
B: Byte
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Section 2 CPU
15
8
7
0
op
15
8
RTE, SLEEP, NOP
7
0
op
15
rn
8
7
op
LDC, STC (Rn)
0
IMM
Legend:
op: Operation field
rn: Register field
IMM: Immediate data
Figure 2.9 System Control Instruction Codes
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ANDC, ORC,
XORC, LDC (#xx:8)
Section 2 CPU
2.5.8
Block Data Transfer Instruction
Table 2.11 describes the block data transfer instruction. Figure 2.10 shows its object code format.
Table 2.11 Block Data Transfer Instruction
Instruction
Size
Function
EEPMOV
(Cannot be
used in the
H8/3577
Group and
H8/3567
Group)
—
If R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until
R4L = 0
else next;
Block transfer instruction. Transfers the number of data bytes
specified by R4L from locations starting at the address indicated by
R5 to locations starting at the address indicated by R6. After the
transfer, the next instruction is executed.
Certain precautions are required in using the EEPMOV instruction. See 2.8.2, Notes on Use of the
EEPMOV Instruction, for details.
15
8
7
0
op
op
Legend:
op: Operation field
Figure 2.10 Block Data Transfer Instruction Code
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Section 2 CPU
2.6
Basic Operational Timing
CPU operation is synchronized by a system clock (φ). The period from a rising edge of φ to the
next rising edge is called one state. A bus cycle consists of two states or three states. The cycle
differs depending on whether access is to on-chip memory or to on-chip peripheral modules.
2.6.1
Access to On-Chip Memory (RAM, ROM)
Access to on-chip memory takes place in two states. The data bus width is 16 bits, allowing access
in byte or word size. Figure 2.11 shows the on-chip memory access cycle.
Bus cycle
T1 state
T2 state
φ or φSUB
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.11 On-Chip Memory Access Cycle
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Section 2 CPU
2.6.2
Access to On-Chip Peripheral Modules
On-chip peripheral modules are accessed in three states. The data bus width is either 8 or 16 bits,
so access in both byte and word size is supported.
There are two categories of on-chip peripheral modules: 8-bit and 16-bit. To access word data
from an 8-bit module, two instructions must be used. The upper byte is accessed first, followed by
the lower byte. Accessing word data from a 16-bit module requires only one instruction.
There are two types of registers: byte and word. The word register refers to registers were, as with
a 16-bit counter, attempting to access the two bytes separately will cause problems. For word
registers containing 8-bit modules, a circuit with a temporary register is available to allow normal
access to the upper byte first, followed by the lower byte. Note that word registers containing only
16-bit modules do not have such a circuit. Therefore, only word access may be used with such
registers.
Figure 2.12 shows the access timing for on-chip peripheral modules.
Bus cycle
T1 state
T2 state
T3 state
φ
Internal address bus
Address
Internal read signal
Internal data bus
(read access)
Read data
Internal write signal
Internal data bus
(write access)
Write data
Figure 2.12 On-Chip Peripheral Module Access Cycle
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Section 2 CPU
2.7
CPU States
2.7.1
Overview
There are four CPU states: the reset state, program execution state, program halt state, and
exception-handling state. The program execution state includes active (high-speed or mediumspeed) mode. In the program halt state there are a sleep (high-speed or medium-speed) mode and
standby mode. These states are shown in figure 2.13. Figure 2.14 shows the state transitions.
CPU state
Reset state
The CPU is initialized
Program
execution state
Active
(high speed) mode
The CPU executes successive program
instructions at high speed,
synchronized by the system clock
Active
(medium speed) mode
The CPU executes successive
program instructions at
reduced speed, synchronized
by the system clock
Program halt state
A state in which some
or all of the chip
functions are stopped
to conserve power
Sleep (high-speed)
mode
Low-power
modes
Sleep (medium-speed)
mode
Standby mode
Exceptionhandling state
A transient state in which the CPU changes
the processing flow due to a reset or an interrupt
Note: See section 21, Power-Down Modes, for details on the modes and their transitions.
Figure 2.13 CPU Operation States
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Section 2 CPU
Reset cleared
Reset state
Exception-handling state
Reset occurs
Reset
occurs
Reset
occurs
Interrupt
source
Program halt state
Exception- Exceptionhandling
handling
request
complete
Program execution state
SLEEP instruction executed
Figure 2.14 State Transitions
2.7.2
Reset State
The CPU is initialized in the reset state.
2.7.3
Program Execution State
In the program execution state the CPU executes program instructions in sequence.
There are two active modes (high-speed and medium-speed) when the CPU is in the program
execution state.
2.7.4
Program Halt State
In the program halt state there are three modes: two sleep modes (high speed and medium speed)
and standby mode. See section 21, Power-Down Modes for details on these modes.
2.7.5
Exception-Handling State
The exception-handling state is a transient state occurring when exception handling is started by a
reset or interrupt and the CPU changes its normal processing flow. In exception handling caused
by an interrupt, SP (R7) is referenced and the PC and CCR values are saved on the stack.
For details on interrupt handling, see section 4, Exception Handling.
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Section 2 CPU
2.8
Application Notes
2.8.1
Notes on Bit Manipulation
The BSET, BCLR, BNOT, BST, and BIST instructions read one byte of data, modify the data,
then write the data byte again. Special care is required when using these instructions in cases
where two registers are assigned to the same address, in the case of registers that include writeonly bits, and when the instruction accesses an I/O port.
Order of Operation
Operation
1
Read
Read byte data at the designated address
2
Modify
Modify a designated bit in the read data
3
Write
Write the altered byte data to the designated address
As in the examples above, P17 and P16 are input pins, with a low-level signal input at P17 and a
high-level signal at P16. The remaining pins, P15 to P10, are output pins that output low-level
signals. In this example, the BCLR instruction is used to change pin P10 to an input port.
[A: Prior to executing BCLR]
P17
P16
P15
P14
P13
P12
P11
P10
Input/output
Input
Input
Output
Output
Output
Output
Output
Output
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
DDR
0
0
1
1
1
1
1
1
DR
1
0
0
0
0
0
0
0
[B: BCLR instruction executed]
BCLR
#0
,
P1DDR
The BCLR instruction is executed designating DDR.
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Section 2 CPU
[C: After executing BCLR]
P17
P16
P15
P14
P13
P12
P11
P10
Input/output
Output
Output
Output
Output
Output
Output
Output
Input
Pin state
Low
level
High
level
Low
level
Low
level
Low
level
Low
level
Low
level
Low
level
DDR
1
1
1
1
1
1
1
0
DR
1
0
0
0
0
0
0
0
[D: Explanation of how BCLR operates]
When the BCLR instruction is executed, first the CPU reads P1DDR. Since P1DDR is a writeonly register, the CPU reads an undefined value. In this example, the DDR value is H'FF, but the
data read by the CPU is undefined; it is taken to be H'FF.
Next, the CPU clears bit 0 in the read data to 0, changing the data to H'FE.
Finally, this value (H'FE) is written to DDR and BCLR instruction execution ends.
As a result of this operation, bit 0 in DDR becomes 0, making P10 an input port. However, bits 7
and 6 in DDR change to 1, so that P17 and P16 change from input pins to output pins.
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Section 2 CPU
2.8.2
Notes on Use of the EEPMOV Instruction (Cannot Be Used in the H8/3577 Group
and H8/3567 Group)
• The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
R5 →
← R6
R5 + R4L →
← R6 + R4L
• When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution of
the instruction.
R5 →
R5 + R4L →
← R6
H'FFFF
Not allowed
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← R6 + R4L
Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Overview
3.1.1
Operating Mode Selection
The H8/3577 Group and H8/3567 Group operate in the single-chip mode. The operating mode is
specified by the setting of the mode pins (MD1 to MD0 or TEST).
Table 3.1 lists the MCU operating modes.
Table 3.1
MCU Operating Mode Selection
• H8/3577 Group
MCU Operating Mode
MD1
MD0
Description
Mode 0
0
0
—
Mode 1
0
1
—
Mode 2
1
0
—
Mode 3
1
1
Single-chip mode
• H8/3567 Group
MCU Operating Mode
TEST
Description
Mode 0
0
—
Mode 3
1
Single-chip mode
The H8/3577 Group and H8/3567 Group support the use of mode 3 only. Therefore, the mode pins
must be set for mode 3 as indicated above.
3.1.2
Register Configuration
The H8/3577 Group and H8/3567 Group have a mode control register (MDCR) that indicates the
inputs at the mode pins (MD1 and MD0 or TEST), a system control register (SYSCR) that controls
the operation of the MCU, and a serial timer control register (STCR) that controls the operation of
the supporting modules. Table 3.2 summarizes these registers.
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Section 3 MCU Operating Modes
Table 3.2
MCU Registers
Name
Abbreviation
R/W
Initial Value
Address*
Mode control register
MDCR
R
H'03
H'FFC5
System control register
SYSCR
R/W
H'09
H'FFC4
Serial timer control register
STCR
R/W
H'00
H'FFC3
Note:
Lower 16 bits of the address.
*
3.2
Register Descriptions
3.2.1
Mode Control Register (MDCR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
Initial value
EXPE
0*
0
0
0
0
0
MDS1
1*
MDS0
1*
Read/Write
R
—
—
—
—
—
R
R
Note:
*
Determined by pins MD1 and MD0 or TEST pin.
MDCR is an 8-bit read-only register that indicates the operating mode setting and the current
operating mode of the MCU.
Bit 7—Expanded Mode Enable (EXPE): This bit should not be set to 1.
Bits 6 to 2—Reserved: These bits cannot be modified and are always read as 0.
Bits 1 and 0—Mode Select 1 and 0 (MDS1, MDS0): These bits indicate the input levels at pins
MD1, MD0, and TEST (the current operating mode). Bits MDS1 and MDS0 correspond to MD1
and MD0 (H8/3577 Group). Alternately, bits MDS1 and MDS0 both correspond to the TEST pin
(H8/3567 Group). MDS1 and MDS0 are read-only bits—they cannot be written to. The mode pin
(MD1, MD0, and TEST) input levels are latched into these bits when MDCR is read.
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Section 3 MCU Operating Modes
3.2.2
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
SYSCR is a readable/writable register that performs selection of system pin functions, reset source
monitoring, interrupt control mode selection, NMI detected edge selection, supporting module
register access control, and RAM address space control.
Only bits 7, 6, 3, 1, and 0 are described here. For a detailed description of these bits, refer also to
the description of the relevant modules (watchdog timer, RAM, etc.). For information on bits 5, 4,
and 2, see section 5.2.1, System Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Chip Select 2 Enable (CS2E): This bit should not be set to 1.
Bit 6—IOS Enable (IOSE): This bit should not be set to 1.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow as well as by external reset input. XRST is a
read-only bit. It is set to 1 by an external reset and cleared to 0 by watchdog timer overflow.
Bit 3
XRST
Description
0
A reset is generated by watchdog timer overflow
1
A reset is generated by an external reset
(Initial value)
Bit 1—Host Interface Enable (HIE): Enables or disables CPU access to on-chip supporting
function registers.
This bit controls CPU access to the 8-bit timer (channel X and Y) data registers and control
registers (TCRX/TCRY, TCSRX/TCSRY, TICRR/TCORAY, TICRF/TCORBY,
TCNTX/TCNTY, TCORC/TISR, TCORAX, and TCORBX), and the timer connection control
registers (TCONRI, TCONRO, TCONRS, and SEDGR).
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Section 3 MCU Operating Modes
Bit 1
HIE
Description
0
In areas H'FFF0 to H'FFF7 and H'FFFC to H'FFFF, CPU access to 8-bit timer
(channels X and Y) data registers and control registers, and timer connection control
registers, is permitted
(Initial value)
1
In areas H'FFF0 to H'FFF7 and H'FFFC to H'FFFF, CPU access to 8-bit timer
(channels X and Y) data registers and control registers, and timer connection control
registers, is not permitted
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
3.2.3
(Initial value)
Serial Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
—
IICX1
IICX0
IICE
—
USBE
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode,
selects the TCNT input clock and controls USB. For details of functions other than register access
control, see the descriptions of the relevant modules. If a module controlled by STCR is not used,
do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: Do not write 1 to this bit.
2
2
Bits 6 and 5—I C Control (IICX1, IICX0): These bits control the operation of the I C bus
2
interface. For details, see section 16, I C Bus Interface.
2
2
Bit 4—I C Master Enable (IICE): Controls CPU access to the I C bus interface data registers
and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and
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Section 3 MCU Operating Modes
control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL),
and the SCI control registers (SMR, BRR, and SCMR).
Bit 4
IICE
Description
0
Addresses H'FFD8 and H'FFD9, and H'FFDE and H'FFDF, are used for SCI0 control
register access
(Initial value)
1
Addresses H'FF88 and H'FF89, and H'FF8E and H'FF8F, are used for IIC1 data
register and control register access
Addresses H'FFA0 and H'FFA1, and H'FFA6 and H'FFA7, are used for PWMX data
register and control register access
Addresses H'FFD8 and H'FFD9, and H'FFDE and H'FFDF, are used for IIC0 data
register and control register access
Bit 3—Reserved: Do not write 1 to this bit.
Bit 2—USB enable (USBE): This bit controls CPU access to the USB data register and control
register.
Bit 2
USBE
Description
0
Prohibition of the above register access
1
Permission of the above register access
(Initial value)
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12, 8-Bit
Timers.
3.3
Address Map
Address maps are shown in figure 3.1 and figure 3.2.
The on-chip ROM capacity is 56 kbytes (H8/3577, H8/3567, H8/3567U) or 32 kbytes (H8/3574,
H8/3564, H8/3564U). Do not try access to reserved areas and the addresses where no memory and
no I/O register exists.
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Section 3 MCU Operating Modes
H'0000
On-chip ROM
H'DFFF
H'E080
Reserved area
H'E880
On-chip RAM
H'EFFF
H'F000
Reserved area
H'F7FF
H'F800
H'FE4F
H'FE50
H'FEFF
H'FF00
H'FF7F
H'FF80
H'FFFF
Internal I/O register 3
(H8/3567U only)
Internal I/O register 2
On-chip RAM
(128 bytes)
Internal I/O register 1
Figure 3.1 H8/3577, H8/3567, and H8/3567U Address Map
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Section 3 MCU Operating Modes
H'0000
On-chip ROM
H'7FFF
Reserved area
H'DFFF
H'E080
Reserved area
H'E880
H'EFFF
H'F000
On-chip RAM
Reserved area
H'F7FF
H'F800
Internal I/O register 3
(H8/3564U only)
H'FE4F
H'FE50
H'FEFF
H'FF00
H'FF7F
H'FF80
H'FFFF
Internal I/O register 2
On-chip RAM
(128 bytes)
Internal I/O register 1
Figure 3.2 H8/3574, H8/3564, and H8/3564U Address Map
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Section 3 MCU Operating Modes
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
Overview
4.1.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, or interrupt. Exception
handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they
are accepted and processed in order of priority.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows.
Interrupt
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued.*
Low
Note:
4.1.2
*
Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
Exception Handling Operation
Exceptions originate from various sources. Trap instructions and interrupts are handled as follows:
1. The program counter (PC) and condition-code register (CCR) are pushed onto the stack.
2. The interrupt mask bits are updated.
3. A vector address corresponding to the exception source is generated, and program execution
starts from that address.
For a reset exception, steps 2 and 3 above are carried out.
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Section 4 Exception Handling
4.1.3
Exception Sources and Vector Table
The exception sources are classified as shown in figure 4.1. Different vector addresses are
assigned to different exception sources.
Table 4.2 lists the exception sources and their vector addresses.
Reset
Exception
sources
External interrupts: NMI, IRQ2 to IRQ0
Interrupts
Internal interrupts: interrupt sources in
on-chip supporting modules
Figure 4.1 Exception Sources
Table 4.2
Exception Vector Table
Exception Source
Vector Number
Vector Address*
Reset
0
H'0000 to H'0001
Reserved for system use
1
H'0002 to H'0003
2
H'0004 to H'0005
3
H'0006 to H'0007
NMI
4
H'0008 to H'0009
IRQ0
5
H'000A to H'000B
IRQ1
6
H'000C to H'000D
External interrupt
IRQ2
Reserved
Internal interrupt*
Note:
*
7
H'000E to H'000F
8
H'0010 to H'0011
9
H'0012 to H'0013
10
H'0014 to H'0015
11
H'0016 to H'0017
12
H'0018 to H'0019
13

53
H'001A to H'001B

H'006A to H'006B
For details on internal interrupt vectors, see section 5.3.3, Interrupt Exception Vector
Table.
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Section 4 Exception Handling
4.2
Reset
4.2.1
Overview
A reset has the highest exception priority.
When the RES pin goes low, all processing halts and the MCU enters the reset state. A reset
initializes the internal state of the CPU and the registers of on-chip supporting modules.
Reset exception handling begins when the RES pin changes from low to high.
MCUs can also be reset by overflow of the watchdog timer. For details, see section 14, Watchdog
Timer.
4.2.2
Reset Sequence
The MCU enters the reset state when the RES pin goes low.
To ensure that the chip is reset, hold the RES pin low for at least 20 ms when powering on. To
reset the chip during operation, hold the RES pin low for at least 20 states. For pin states in a reset,
see Appendix D.1, Port States in Each Processing State.
When the RES pin goes high after being held low for the necessary time, the chip starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit is set to 1 in CCR.
2. The reset exception vector address is read and transferred to the PC, and program execution
starts from the address indicated by the PC.
Figure 4.2 shows an example of the reset sequence.
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Section 4 Exception Handling
Vector Internal
Fetch of first program
fetch
processing instruction
φ
RES
Internal
address bus
(1)
(3)
Internal read
signal
Internal write
signal
High
Internal data
bus
(1)
(2)
(3)
(4)
(2)
(4)
Reset exception vector address ((1) = H'0000)
Start address (contents of reset exception vector address)
Start address ((3) = (2))
First program instruction
Figure 4.2 Reset Sequence
4.2.3
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.W #xx:16, SP).
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Section 4 Exception Handling
4.3
Interrupts
Interrupt exception handling can be requested by four external sources (NMI and IRQ2 to IRQ0),
and internal sources in the on-chip supporting modules. Figure 4.3 shows the interrupt sources and
the number of interrupts of each type.
The on-chip supporting modules that can request interrupts include the watchdog timer (WDT),
16-bit free-running timer (FRT), 8-bit timer (TMR), serial communication interface (SCI), A/D
2
converter (ADC), I C bus interface (IIC). Each interrupt source has a separate vector address.
NMI is the highest-priority interrupt. Interrupts are controlled by the interrupt controller.
For details on interrupts, see section 5, Interrupt Controller.
External
interrupts
Interrupts
Internal
interrupts
NMI (1)
IRQ2 to IRQ0 (3)
WDT* (1)
FRT (7)
TMR (10)
SCI (4)
ADC (1)
IIC (3)
USB (4)
Notes: Numbers in parentheses are the numbers of interrupt sources.
* When the watchdog timer is used as an interval timer, it generates an interrupt request
at each counter overflow.
Figure 4.3 Interrupt Sources and Number of Interrupts
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Section 4 Exception Handling
4.4
Stack Status after Exception Handling
Figure 4.4 shows the stack after completion of interrupt exception handling.
SP
CCR
CCR*
PC
(16 bits)
Interrupt control mode 0
Note: * Ignored on return.
Figure 4.4 Stack Status after Exception Handling
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Section 4 Exception Handling
4.5
Note on Stack Handling
In word access, the least significant bit of the address is always assumed to be 0. The stack is
always accessed by word access. Care should be taken to keep an even value in the stack pointer
(general register R7). Use the PUSH and POP (or MOV.W Rn, @–SP and MOV.W @SP+, Rn)
instructions to push and pop registers on the stack.
Setting the stack pointer to an odd value can cause programs to crash. Figure 4.5 shows an
example of damage caused when the stack pointer contains an odd address.
PCH
SP
PCL
SP
R1L
H'FECC
PCL
H'FECD
H'FECF
SP
BSR instruction
H'FECF set in SP
PCH:
PCL:
R1L:
SP:
MOV.B R1L, @–R7
PC is improperly stored
beyond top of stack
PCH is lost
Upper byte of program counter
Lower byte of program counter
General register
Stack pointer
Figure 4.5 Example of Damage Caused by Setting an Odd Address in R7
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Section 4 Exception Handling
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Overview
5.1.1
Features
The MCUs control interrupts by means of an interrupt controller. The interrupt controller has the
following features:
• Independent vector addresses
 All interrupt sources are assigned independent vector addresses, making it unnecessary for
the source to be identified in the interrupt handling routine.
• Four external interrupt pins
 NMI is the highest-priority interrupt, and is accepted at all times. A rising or falling edge at
the NMI pin can be selected for the NMI interrupt.
 Falling edge, rising edge, or both edge detection, or level sensing, at pins IRQ2 to IRQ0 can
be selected for interrupts IRQ2 to IRQ0.
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Section 5 Interrupt Controller
5.1.2
Block Diagram
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
SYSCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
ISCR
IER
Interrupt
request
Vector
number
Priority
determination
I
Internal interrupt
requests
WOVI to IICI1
USB-related
interrupts
Interrupt controller
Legend:
ISCR:
IER:
ISR:
SYSCR:
IRQ sense control register
IRQ enable register
IRQ status register
System control register
Figure 5.1 Block Diagram of Interrupt Controller
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CCR
Section 5 Interrupt Controller
5.1.3
Pin Configuration
Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1
Interrupt Controller Pins
Name
Symbol
I/O
Function
Nonmaskable interrupt
NMI
Input
Nonmaskable external interrupt; rising or
falling edge can be selected
External interrupt
requests 2 to 0
IRQ2 to IRQ0
Input
Maskable external interrupts; rising, falling, or
both edges, or level sensing, can be selected
5.1.4
Register Configuration
Table 5.2 summarizes the registers of the interrupt controller.
Table 5.2
Interrupt Controller Registers
Name
Abbreviation
R/W
Initial Value
Address
System control register
SYSCR
R/W
H'09
H'FFC4
IRQ sense control register H
ISCRH
R/W
H'00
H'FEEC
IRQ sense control register L
ISCRL
R/W
H'00
H'FEED
IRQ enable register
IER
R/W
H'F8
H'FFC2
IRQ status register
ISR
R/(W)*
H'00
H'FEEB
Note:
*
Only 0 can be written, for flag clearing.
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Section 5 Interrupt Controller
5.2
Register Descriptions
5.2.1
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
SYSCR is an 8-bit readable/writable register, bit 2 of which selects the detected edge for NMI.
Only bits 5, 4, and 2 are described here; for details on the other bits, see section 3.2.2, System
Control Register (SYSCR).
SYSCR is initialized to H'09 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): The INTM1 and 0 bits must
not be set to 1.
Bit 5
Bit 4
INTM1
INTM0
Interrupt
Control Mode
Description
0
0
0
Interrupts are controlled by I bit
1
1
Cannot be used in H8/3577 Group and H8/3567 Group
0
2
Cannot be used in H8/3577 Group and H8/3567 Group
1
3
Cannot be used in H8/3577 Group and H8/3567 Group
1
(Initial value)
Bit 2—NMI Edge Select (NMIEG): Selects the input edge for the NMI pin.
Bit 2
NMIEG
Description
0
Interrupt request generated at falling edge of NMI input
1
Interrupt request generated at rising edge of NMI input
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(Initial value)
Section 5 Interrupt Controller
5.2.2
IRQ Enable Register (IER)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
IRQ2E
IRQ1E
IRQ0E
Initial value
1
1
1
1
1
0
0
0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
IER is a register that controls enabling and disabling of interrupt requests IRQ2 to IRQ0.
IER is initialized to H'F8 by a reset and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 1.
Bits 2 to 0—IRQ2 to IRQ0 Enable (IRQ2E to IRQ0E): These bits select whether IRQ2 to
IRQ0 are enabled or disabled.
Bit n
IRQnE
Description
0
IRQn interrupt disabled
1
IRQn interrupt enabled
(Initial value)
Note: n = 2 to 0
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Section 5 Interrupt Controller
5.2.3
IRQ Sense Control Registers H and L (ISCRH, ISCRL)
• ISCRH
Bit
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
5
4
3
2
1
0
• ISCRL
Bit
7
6
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
ISCRH and ISCRL are 8-bit readable/writable registers that select rising edge, falling edge, or
both edge detection, or level sensing, for the input at pins IRQ2 to IRQ0.
Each of the ISCR registers is initialized to H'00 by a reset and in hardware standby mode.
ISCRH Bits 7 to 0, ISCRL Bits 7 and 6—Reserved: Do not write 1 to this bit.
ISCRL Bits 5 to 0—IRQ2 Sense Control A and B (IRQ2SCA, IRQ2SCB) to IRQ0 Sense
Control A and B (IRQ0SCA, IRQ0SCB)
ISCRL Bits 5 to 0
IRQ2SCB to
IRQ0SCB
IRQ2SCA to
IRQ0SCA
0
0
Interrupt request generated at IRQ2 to IRQ0 input low level
(Initial value)
1
Interrupt request generated at falling edge of IRQ2 to IRQ0 input
0
Interrupt request generated at rising edge of IRQ2 to IRQ0 input
1
Interrupt request generated at both falling and rising edges of
IRQ2 to IRQ0 input
1
Description
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Section 5 Interrupt Controller
5.2.4
IRQ Status Register (ISR)
Bit
Initial value
Read/Write
Note:
7
6
5
4
3
2
1
0
—
—
—
—
—
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
0
0
R
R/(W)*
R/(W)*
R/(W)*
R
R
R
R
Only 0 can be written, to clear the flag.
*
ISR is an 8-bit readable/writable register that indicates the status of IRQ2 to IRQ0 interrupt
requests.
ISR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 3—Reserved
Bits 2 to 0—IRQ2 to IRQ0 Flags (IRQ2F to IRQ0F): These bits indicate the status of IRQ2 to
IRQ0 interrupt requests.
Bit n
IRQnF
0
1
Description
[Clearing conditions]
(Initial value)
•
Cleared by reading IRQnF when set to 1, then writing 0 in IRQnF
•
When interrupt exception handling is executed when low-level detection is set
(IRQnSCB = IRQnSCA = 0) and IRQn input is high
•
When IRQn interrupt exception handling is executed when falling, rising, or bothedge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
[Setting conditions]
•
When IRQn input goes low when low-level detection is set (IRQnSCB = IRQnSCA =
0)
•
When a falling edge occurs in IRQn input when falling edge detection is set
(IRQnSCB = 0, IRQnSCA = 1)
•
When a rising edge occurs in IRQn input when rising edge detection is set
(IRQnSCB = 1, IRQnSCA = 0)
•
When a falling or rising edge occurs in IRQn input when both-edge detection is set
(IRQnSCB = IRQnSCA = 1)
Note: n = 2 to 0
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Section 5 Interrupt Controller
5.3
Interrupt Sources
Interrupt sources comprise external interrupts (NMI and IRQ2 to IRQ0) and internal interrupts.
5.3.1
External Interrupts
There are four external interrupt sources: NMI, and IRQ2 to IRQ0. NMI, and IRQ2 to IRQ0 can be
used to restore the H8/3577 Group and H8/3567 Group chip from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode and the status of the CPU interrupt mask bits. The
NMIEG bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a
falling edge on the NMI pin.
The vector number for NMI interrupt exception handling is 4.
IRQ2 to IRQ0 Interrupts: Interrupts IRQ2 to IRQ0 are requested by an input signal at pins IRQ2
to IRQ0. Interrupts IRQ2 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ2 to IRQ0.
• Enabling or disabling of interrupt requests IRQ2 to IRQ0 can be selected with IER.
• The status of interrupt requests IRQ2 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
A block diagram of interrupts IRQ2 to IRQ0 is shown in figure 5.2.
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/level
detection circuit
S
Q
R
IRQn input
Clear signal
Note: n: 2 to 0
Figure 5.2 Block Diagram of Interrupts IRQ2 to IRQ0
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IRQn interrupt
request
Section 5 Interrupt Controller
Figure 5.3 shows the timing of IRQnF setting.
φ
IRQn
input pin
IRQnF
Figure 5.3 Timing of IRQnF Setting
The vector numbers for IRQ2 to IRQ0 interrupt exception handling are 7 to 5.
Detection of IRQ2 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. Therefore, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR bit to 0 and use the pin as an I/O pin for another function.
As interrupt request flags IRQ2F to IRQ0F are set when the setting condition is met, regardless of
the IER setting, only the necessary flags should be referenced.
5.3.2
Internal Interrupts
There are 26 sources (30 sources in the version with an on-chip USB) for internal interrupts from
on-chip supporting modules.
For each on-chip supporting module there are flags that indicate the interrupt request status, and
enable bits that select enabling or disabling of these interrupts. If any one of these is set to 1, an
interrupt request is issued to the interrupt controller.
5.3.3
Interrupt Exception Vector Table
Table 5.3 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority.
Priorities within a module are fixed as shown in table 5.3.
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Section 5 Interrupt Controller
Table 5.3
Interrupt Exception Handling Sources, Vector Addresses, and Interrupt
Priorities
Interrupt Source
Origin of Interrupt
Source
Vector
Number
Vector
Address
Priority
NMI
External pin
4
H'0008
High
IRQ0
5
H'000A
IRQ1
6
H'000C
IRQ2
7
H'000E
Reserved
—
8
to
12
H'0010
to
H'0018
WOVI0 (interval timer)
Watchdog timer 0
13
H'001A
ADI (A/D conversion end)
A/D
14
H'001C
ICIA (input capture A)
Free-running timer
15
H'001E
ICIB (input capture B)
16
H'0020
ICIC (input capture C)
17
H'0022
ICID (input capture D)
18
H'0024
OCIA (output compare A)
19
H'0026
OCIB (output compare B)
20
H'0028
FOVI (overflow)
21
H'002A
CMIA0 (compare-match A)
22
H'002C
CMIB0 (compare-match B)
23
H'002E
OVI0 (overflow)
24
H'0030
25
H'0032
CMIB1 (compare-match B)
26
H'0034
OVI1 (overflow)
27
H'0036
CMIA1 (compare-match A)
8-bit timer channel 0
8-bit timer channel 1
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Low
Section 5 Interrupt Controller
Origin of Interrupt
Source
Vector
Number
Vector
Address
Priority
8-bit timer channels
Y, X
28
H'0038
High
29
H'003A
OVIY (overflow)
30
H'003C
ICIX (input capture X)
31
H'003E
Interrupt Source
CMIAY (compare-match A)
CMIBY (compare-match B)
Reserved
—
32
to
35
H'0040
to
H'0046
ERI0 (receive error 0)
SCI channel 0
36
H'0048
RXI0 (reception completed 0)
37
H'004A
TXI0 (transmit data empty 0)
38
H'004C
TEI0 (transmission end 0)
39
H'004E
Reserved
—
40
to
43
H'0050
to
H'0056
IICI0 (1-byte transmission/
reception completed)
IIC channel 0
44
H'0058
45
H'005A
DDCSWI (format switch)
IICI1 (1-byte transmission/
reception completed)
IIC channel 1
46
H'005C
Reserved
—
47
to
49
H'005E
to
H'0062
USBIA
USB
50
H'0064
USBIB
51
H'0066
USBIC
52
H'0068
USBID
53
H'006A
Low
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Section 5 Interrupt Controller
5.4
Interrupt Operation
5.4.1
Interrupt Operation
NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In
the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for
each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request. Interrupt
sources for which the enable bits are set to 1 are controlled by the interrupt controller.
Table 5.4 shows the interrupt control modes.
Table 5.4
Interrupt Control Modes
SYSCR
Interrupt Control Mode
INTM1
INTM0
Interrupt Mask Bits
Description
0
0
0
I
Interrupt mask control is
performed by the I bit
Figure 5.4 shows a block diagram of the priority decision circuit.
I
Interrupt
source
Interrupt
acceptance
control
Default priority
determination
Vector
number
Figure 5.4 Block Diagram of Interrupt Control Operation
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Section 5 Interrupt Controller
Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance control is
performed by means of the I bit in CCR.
Table 5.5 shows the interrupts selected in each interrupt control mode.
Table 5.5
Interrupts Selected in Each Interrupt Control Mode
Interrupt Mask Bits
Interrupt Control Mode
I
Selected Interrupts
0
0
All interrupts
1
NMI interrupts
Default Priority Determination: The priority is determined for the selected interrupt, and a
vector number is generated.
Interrupt sources with a lower priority than the accepted interrupt source are held pending.
Table 5.6 shows operations and control signal functions in each interrupt control mode.
Table 5.6
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt Control
Mode
0
Interrupt Acceptance
Control
Setting
INTM1
INTM0
0
0
Determination
I
O
IM
O
Legend:
O: Interrupt operation control performed
IM: Used as interrupt mask bit
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Section 5 Interrupt Controller
5.4.2
Interrupt Control Mode 0
Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by
means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and
disabled when set to 1.
Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If a number of interrupt requests are generated at the same time, the interrupt request with the
highest priority according to the priority system shown in table 5.3 is selected.
3. The I bit is then referenced. If the I bit is cleared to 0, the interrupt request is accepted. If the I
bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held pending.
4. When an interrupt request is accepted, interrupt exception handling starts after execution of the
current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This disables all interrupts except NMI.
7. A vector address is generated for the accepted interrupt, and execution of the interrupt
handling routine starts at the address indicated by the contents of that vector address.
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Section 5 Interrupt Controller
Program execution state
No
Interrupt generated?
Yes
Yes
NMI?
No
Hold pending
IRQ0?
No
Yes
IRQ1?
Yes
No
IICI1*?
Yes
No
I = 0?
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Note: * The built-in USB version is USBID.
Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance
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(1)
(2) (4)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
Internal
data bus
(2)
(1)
(4)
(3)
Internal
operation
(1)
(5)
Stack
(7)
(6)
(9)
(8)
Vector fetch
Internal
operation
Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.)
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP-2
SP-4
Saved CCR
Vector address
Interrupt handling routine start address (vector address contents)
First instruction of interrupt handling routine
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Instruction
prefetch
(10)
(9)
Interrupt handling
routine instruction
prefetch
5.4.3
Interrupt level determination
Wait for end of instruction
Interrupt
acceptance
Section 5 Interrupt Controller
Interrupt Exception Handling Sequence
Figure 5.6 shows the interrupt exception handling sequence.
Figure 5.6 Interrupt Exception Handling
Section 5 Interrupt Controller
5.4.4
Interrupt Response Times
Table 5.7 shows interrupt response times—the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine.
Table 5.7
Interrupt Response Times
Number of States
No.
Item
1
Interrupt priority determination*
2
Number of wait states until executing instruction ends*
3
PC, CCR stack save
4
4
Vector fetch
2
5
3
Instruction fetch*
6
Internal processing*
Total
Notes: 1.
2.
3.
4.
Normal Mode
1
3
2
1 to 13
4
4
4
18 to 30
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions. Except EEPMOV instruction.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
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Section 5 Interrupt Controller
5.5
Usage Notes
5.5.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
In other words, when an interrupt enable bit is cleared to 0 by an instruction such as BCLR or
MOV, if an interrupt is generated during execution of the instruction, the interrupt concerned will
still be enabled on completion of the instruction, and so interrupt exception handling for that
interrupt will be executed on completion of the instruction. However, if there is an interrupt
request of higher priority than that interrupt, interrupt exception handling will be executed for the
higher-priority interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.7 shows an example in which the CMIEA bit in 8-bit timer register TCR is cleared to 0.
TCR write cycle by CPU
CMIA exception handling
φ
Internal
address bus
TCR address
Internal
write signal
CMIEA
CMFA
CMIA
interrupt signal
Figure 5.7 Contention between Interrupt Generation and Disabling
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
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Section 5 Interrupt Controller
5.5.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts, including NMI, are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.5.3
Interrupts during Execution of EEPMOV Instruction
With the EEPMOV instruction, an interrupt request (including NMI) issued during the transfer is
not accepted until the move is completed. The EEPMOV instruction cannot be used in the
H8/3577 Group and H8/3567 Group.
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Section 5 Interrupt Controller
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Section 6 Bus Controller
Section 6 Bus Controller
6.1
Overview
As the H8/3577 Group and H8/3567 Group do not have external expansion functions, they do not
incorporate a bus controller function.
However, from the viewpoint of maintaining software compatibility with similar products, care
must be taken not to set inappropriate values in the bus controller related control registers.
6.2
Register Descriptions
6.2.1
Bus Control Register (BCR)
Bit
7
6
5
4
3
BRSTRM BRSTS1 BRSTS0
2
1
0
ICIS1
ICIS0
—
IOS1
IOS0
Initial value
1
1
0
1
0
1
1
1
Read/Write
R/W
R/W
R
R/W
R
R/W
R/W
R/W
Bits 7 and 6—Idle Cycle Insert 1 and 0 (ICIS1, ICIS0): Do not write 0 to these bits.
Bit 5—Burst ROM Enable (BRSTRM): Do not write 1 to this bit.
Bit 4—Burst Cycle Select 1 (BRSTS1): Do not write 0 to this bit.
Bit 3—Burst Cycle Select 0 (BRSTS0): Do not write 1 to this bit.
Bit 2—Reserved: Do not write 0 to this bit.
Bits 1 and 0—IOS Select 1 and 0 (IOS1, IOS0): Do not write 0 to these bits.
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Section 6 Bus Controller
6.2.2
Wait State Control Register (WSCR)
Bit
7
6
5
4
3
2
1
0
RAMS
RAM0
ABW
AST
WMS1
WMS0
WC1
WC0
Initial value
0
0
1
1
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit 7—RAM Select (RAMS)/Bit 6—RAM Area Setting (RAM0): Reserved bits.
Bit 5—Bus Width Control (ABW): Do not write 0 to this bit.
Bit 4—Access State Control (AST): Do not write 0 to this bit.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1, WMS0): Do not write 1 to these bits.
Bits 1 and 0—Wait Count 1 and 0 (WC1, WC0): Do not write 0 to these bits.
Rev. 3.00 Mar 17, 2006 page 102 of 706
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Section 7 Universal Serial Bus Interface (USB)
Section 7 Universal Serial Bus Interface (USB)
It is built in the H8/3567U and H8/3564U Group and not in the H8/3577, H8/3574, H8/3567 and
H8/3564 Group.
7.1
Overview
The H8/3567U and H8/3564U have an on-chip universal serial bus (USB) comprising hubs and a
function. The universal serial bus is an interface for personal computer peripherals whose
standardization is being promoted by a core group of companies, including Intel Corporation.
The USB is provided with a number of device classes to handle the great variety of personal
computer peripheral devices. The USB in the H8/3567U and H8/3564U are targeted at the hub
device class and HID (Human Interface Device) class (mainly a monitor device class).
7.1.1
Features
• Compound device conforming to USB standard*
 Apart from initial settings and power-down mode settings, USB hubs decode and execute
hub class commands automatically, independently of CPU operations
 USB function decodes and executes standard commands
Device class commands are decoded and executed by the CPU (firmware creation required)
• Five downstream hubs and one function
 One down stream is connected internally to the USB function
 Internal downstream disconnection function
(Only power-down mode USB hubs operable)
 Four sets of downstream external pins
 Automatic control of downstream port external power supply control IC (individual port
control)
• Three-endpoint monitor device class function
 EP0: USB control endpoint (dedicated to control transfer)
 EP1, EP2: Monitor control endpoints (dedicated to interrupt transfer)
 EP0I, EP0O, and EP2 can use a maximum 16-byte FIFO (maximum packet size of 8
bytes), and EP1 can use a maximum 32-byte FIFO (maximum packet size of 16 bytes)
• Supports 12 Mbps high-speed transfer mode
• Built-in 12 MHz clock pulse generator and frequency division/multiplication circuit
• Built-in bus driver/receiver
 Driven by DrVSS/DrVCC (3.3 V)
Rev. 3.00 Mar 17, 2006 page 103 of 706
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Section 7 Universal Serial Bus Interface (USB)
Note: * The USB function conforms to USB Standard 1.1 and the USB hub to USB Standard
1.0.
7.1.2
Block Diagram
Figure 7.1 shows a block diagram of the USB.
Internal
data bus
Module data bus
Bus I/F
FIFO control
EPDR2 FVSR2
EPSZR1
EPDR1 FVSR1
EPDR0I FVSR0I
EPDR0O FVSR0O
Address
bus
Data
bus
Bus
driver/
receiver
Registers
EPSTLR
PTTER
EPDIR
USBIER
EPRSTR
USBIFR
DEVRSMR
TSFR
INTSELR0
TFFR
USBCSR0 INTSELR1
HOCCR
USBCR
UPLLCR
UPRTCR
UTESTR0
UTESTR1
UTESTR2
Internal
interrupts
Interrupt I/F
USB operating
clock
Clock
selection
FIFO
64 bytes
Connection
selection
USD+
USD−
φ
(XTAL12,
EXTAL12)
PLL
DrVCC
DrVSS
USB hub core
Connection
selection
Bus driver/
receiver
Power supply control
IC Control
DS2D+
DS2D−
Legend:
EPDR2:
EPDR1:
EPDR0I:
EPDR0O:
FVSR2:
FVSR1:
FVSR0I:
FVSR0O:
EPSZR1:
PTTER:
USBIER:
USBIFR:
TSFR:
TFFR:
USBCSR0:
EPSTLR:
EPDIR:
Endpoint data register 2
Endpoint data register 1
Endpoint data register 0I
Endpoint data register 0O
FIFO valid size register 2
FIFO valid size register 1
FIFO valid size register 0I
FIFO valid size register 0O
Endpoint size register 1
Packet transmit enable register
USB interrupt enable register
USB interrupt flag register
Transfer success flag register
Transfer fail flag register
USB control/status register 0
Endpoint stall register
Endpoint direction register
USB function core
DS3D+ DS4D+ DS5D+
DS3D− DS4D− DS5D−
EPRSTR:
DEVRSMR:
INTSELR0:
INTSELR1:
HOCCR:
USBCR:
UPLLCR:
UPRTCR:
UTESTR0:
UTESTR1:
UTESTR2:
USD+:
USD–:
DS2D+:
DS2D–:
DS3D+:
DS3D–:
ENP2, ENP3
ENP4, ENP5
Endpoint reset register
Device resume register
Interrupt source select register 0
Interrupt source select register 1
Hub overcurrent control register
USB control register
USB PLL control register
USB port control register
USB test register 0
USB test register 1
USB test register 2
Upstream data + pin
Upstream data − pin
Downstream 2 data + pin
Downstream 2 data − pin
Downstream 3 data + pin
Downstream 3 data − pin
OCP2, OCP3
OCP4, OCP5
DS4D+:
DS4D–:
DS5D+:
DS5D–:
XTAL12:
EXTAL12:
DrVCC:
DrVSS:
OCP2:
OCP3:
OCP4:
OCP5:
ENP2:
ENP3:
ENP4:
ENP5:
Figure 7.1 Block Diagram of USB
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Downstream 4 data + pin
Downstream 4 data − pin
Downstream 5 data + pin
Downstream 5 data − pin
USB clock oscillator pin
USB clock oscillator pin
Bus driver power supply pin
Bus driver ground pin
Overcurrent detection pin 2
Overcurrent detection pin 3
Overcurrent detection pin 4
Overcurrent detection pin 5
Power supply output enable pin 2
Power supply output enable pin 3
Power supply output enable pin 4
Power supply output enable pin 5
Section 7 Universal Serial Bus Interface (USB)
7.1.3
Pin Configuration
Table 7.1 shows the pins used by the USB.
Table 7.1
USB Pins
Name
Abbreviation
I/O
Function
Upstream data + pin
USD+
Input/output
USB hub/function data input/output
Upstream data – pin
USD–
Input/output
Downstream 2 data + pin
DS2D+
Input/output
Downstream 2 data – pin
DS2D–
Input/output
Downstream 3 data + pin
DS3D+
Input/output
Downstream 3 data – pin
DS3D–
Input/output
Downstream 4 data + pin
DS4D+
Input/output
USB hub repeater input/output (port 2)
USB hub repeater input/output (port 3)
USB hub repeater input/output (port 4)
Downstream 4 data – pin
DS4D–
Input/output
Downstream 5 data + pin
DS5D+
Input/output
Downstream 5 data – pin
DS5D–
Input/output
Overcurrent detection pins
2 to 5
OCP2 to
OCP5
Input
Power supply control IC overcurrent
detection signal input
Power supply output enable ENP2 to
control pins 2 to 5
ENP5
Output
Power supply control IC power output
enable signal output
USB clock oscillator pin
XTAL12
Input
12 MHz crystal oscillation
USB clock oscillator pin
EXTAL12 Input
USB hub repeater input/output (port 5)
Bus Driver power supply pin DrVCC
Input
Bus driver/receiver, port D power supply
Bus Driver ground pin
Input
Bus driver/receiver, port D ground
7.1.4
DrVSS
Register Configuration
The USB register configuration is shown in table 7.2. Registers relating to USB hub initialization
and status display are USBCR, USBCSR0, HOCCR, and UPLLCR, as well as some bits in the test
registers; the other registers relate to the USB function.
When USBCR, USBCSR0, HOCCR, and UPLLCR are all in the initial state, the USB module is
completely disabled, and ports C and D function as I/O ports.
When accessing a USB register, the USBE bit in STCR must be set to 1.
Rev. 3.00 Mar 17, 2006 page 105 of 706
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Section 7 Universal Serial Bus Interface (USB)
Table 7.2
USB Registers
Name
Abbreviation
R/W
Initial Value
Address
Endpoint data register 2
EPDR2
R or W*
H'00
H'FDE1
FIFO valid size register 2
FVSR2
R
H'0010
H'FDE2
Endpoint size register 1
EPSZR1
R/W
H'44
H'FDE4
1
Endpoint data register 1
EPDR1
W
H'00
H'FDE5
FIFO valid size register 1
FVSR1
R
H'0010
H'FDE6
Endpoint data register 0O
EPDR0O
R
H'00
H'FDE9
FIFO valid size register 0O
FVSR0O
R
H'0000
H'FDEA
Endpoint data register 0I
EPDR0I
W
H'00
H'FDED
FIFO valid size register 0I
FVSR0I
R
H'0010
H'FDEE
Packet transmit enable register
PTTER
2
R/(W)*
H'00
H'FDF0
USB interrupt enable register
USBIER
R/W
H'00
H'FDF1
USB interrupt flag register
USBIFR
H'00
H'FDF2
Transfer success flag register
TSFR
R/(W)*
3
R/(W)*
H'00
H'FDF3
TFFR
3
R/(W)*
H'00
H'FDF4
Transfer fail flag register
3
USB control/status register 0
USBCSR0
R/W
H'00
H'FDF5
Endpoint stall register
EPSTLR
R/W
H'00
H'FDF6
Endpoint direction register
EPDIR
R/W
H'FC
H'FDF7
EPRSTR
2
R/(W)*
H'00
H'FDF8
Device resume register
DEVRSMR
2
R/(W)*
H'00
H'FDF9
Interrupt source select register 0
INTSELR0
R/W
H'00
H'FDFA
Interrupt source select register 1
INTSELR1
R/W
H'00
H'FDFB
Hub overcurrent control register
HOCCR
R/W
H'00
H'FDFC
USB control register
USBCR
R/W
H'7F
H'FDFD
USB PLL control register
UPLLCR
R/W
H'01
H'FDFE
USB port control register
UPRTCR
R/W
H'00
H'FDC0
USB test register 0
UTESTR0
R/W
H'00
H'FDC1
USB test register 1
UTESTR1
R/W
H'00
H'FDC2
USB test register 2
UTESTR2
R/W
H'FF
H'FDFF
Other test registers
—
—
—
H'FDC3 to
H'FDE0
Endpoint reset register
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Section 7 Universal Serial Bus Interface (USB)
Name
Abbreviation
R/W
Initial Value
Address
Serial timer control register
STCR
R/W
H'00
H'FFC3
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Notes: 1. Write-only or read-only depending on the transfer direction set in the endpoint direction
register.
2. Only 1 can be written.
3. Only 0 can be written after reading 1 to clear the flags.
7.2
Register Descriptions
In the USB protocol, the host transmits a token to initiate a single data transfer (a transaction). A
transaction consists of a token packet, data packet, and handshake packet. The token packet
contains the address endpoint of the transfer target device and the transfer type, the data packet
contains data, and the handshake packet contains information relating to transfer setup/non-setup.
In data transfer from the host to a slave, the host transmits an OUT token or SETUP token,
followed by data (an OUT or SETUP transaction). In data transfer from a slave to the host, the
host transmits an IN token and waits for data from the slave (an IN transaction). In the following
descriptions, these host-based IN and OUT operations may be referred to as “input” and “output.”
Also, items relating to host input transfer may be designated “IN” (IN transaction, IN-FIFO,
EP0in, etc.), while items relating to host output transfer are designated “OUT” (OUT transaction,
OUT-FIFO, EP0out, etc.).
Where an explicit expression such as “transmitted by the host” or “received by the host” is not
used, the terms “transmission” and “reception” refer to transmission and reception from the
standpoint of the USB module and slave CPU.
7.2.1
USB Data FIFO
The FIFO, together with EPDR, functions as an intermediary role in data transfer between the H8
CPU (slave) and the USB function. The USB function uses the FIFO to execute data transfer to
and from the USB host (host).
The H8/3567U and H8/3564U have an on-chip 64-byte FIFO. This FIFO is divided into four 16byte FIFOs, used for endpoint 0 host input transfer and host output transfer (control transfer),
endpoint 1 host input transfer (interrupt transfer), and endpoint 2 host input transfer or host output
transfer. If endpoint 2 is not used, a 32-byte length can be selected for the endpoint 1 FIFO. The
maximum data packet size is set at half the number of FIFO bytes.
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Section 7 Universal Serial Bus Interface (USB)
In host input transfer, all the data to be transmitted from the slave is written to the FIFO before
slave transmission is started. In host output transfer, the slave reads all the data from the FIFO
after host output transfer is completed.
7.2.2
Endpoint Size Register 1 (EPSZR1)
Bit
7
6
EP1SZ3
5
4
3
2
1
0
EP1SZ2 EP1SZ1 EP1SZ0 EP2SZ3 EP2SZ2 EP2SZ1
EP2SZ0
Initial value
0
1
0
0
0
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
EPSZR1 specifies the number of FIFO bytes used for each USB function endpoint 1 and 2 host
input transfer/host output transfer. The number of bytes in the endpoint 0 FIFO is fixed at 16. Both
host input (EP0in) and host output (EP0out) can be selected for endpoint 0, host input for endpoint
1, and host input and host output for endpoint 2.
With the H8/3567U and H8/3564U, when endpoints 1 and 2 are both used, set a 16-byte size for
the respective FIFOs. When only endpoint 1 is used, set a 16- or 32-byte size. If the 32-byte size is
selected, set 0 as the endpoint 2 FIFO size.
EPSZR1 is initialized to H'44 by a system reset or a function soft reset.
EPSZR1
Bits 7 to 4
EP1 FIFO size
EPSZR1
Bits 3 to 0
EP2 FIFO size
Bit 7
Bit 3
Bit 6
Bit 2
Bit 5
Bit 1
Bit 4
Bit 0
SZ3
SZ2
SZ1
SZ0
Operating Mode
0
0
0
0
FIFO size = 0 bytes (settable for EP2 only)
1
Setting prohibited
0
Setting prohibited
1
Setting prohibited
0
FIFO size = 16 bytes
1
FIFO size = 32 bytes (settable for EP1 only)
0
Setting prohibited
1
Setting prohibited
—
Setting prohibited
1
1
0
1
1
—
—
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(Initial value)
Section 7 Universal Serial Bus Interface (USB)
7.2.3
Endpoint Data Registers 0I, 0O, 1, 2 (EPDR0I, EPDR0O, EPDR1, EPDR2)
Bit
Initial value
Read/
Write
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
0
0
0
0
0
0
0
0
EPDR0I
W
W
W
W
W
W
W
W
EPDR0O
R
R
R
R
R
R
R
R
EPDR1
W
EPDR2
Note:
7
*
W
W
W
W
W
W
W
*
*
*
*
*
*
*
R or W R or W R or W R or W R or W R or W R or W R or W*
Write-only or read-only depending on the transfer direction set in the endpoint direction
register.
The EPDR registers play an intermediary role in data transfer between the CPU and FIFO for each
host input transfer/host output transfer involving the respective USB function endpoints. EPDR0I
and EPDR1 are used for host input transfer, and so are write-only registers; if read, the contents of
the read data are not guaranteed. EPDR0O is used for host output transfer, and so is a read-only
register; it cannot be written to.
For EPDR2, the endpoint transfer direction is determined by the endpoint direction register.
EPDR2 is a write-only register when designated for host input transfer, and a read-only register
when designated for host output transfer. If EPDR2 is read when functioning as a write-only
register, the contents of the read data are not guaranteed. When EPDR2 is functioning as a readonly register, it cannot be written to.
Data written to EPDR0I, EPDR1, or EPDR2 (when a write-only register) is stored in the FIFO,
and is made valid by setting the EPTE bit in the packet transmit enable register (PTTER). Valid
data is transferred to the USB function, and transferred to the host, in accordance with a USB
function request.
Data transferred from the host is stored in the FIFO by the USB function, and becomes valid when
all the data packet bytes have been received and an ACK handshake is transmitted. When
EPDR0O or EPDR2 (when a read-only register) is read, the contents are stored in the FIFO, and
when the data is valid it is read in the order in which it was transferred.
The EPDR registers are initialized to H'00 by a system reset or a function soft reset.
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Section 7 Universal Serial Bus Interface (USB)
7.2.4
FIFO Valid Size Registers 0I, 0O, 1, 2 (FVSR0I, FVSR0O, FVSR1, FVSR2)
FVSR0IH, FVSR0OH, FVSR1H, FVSR2H FVSR0IL, FVSR0OL, FVSR1L, FVSR2L
Bit
7
6
5
4
3
2
1
0
7
6
5
—
—
—
—
—
—
N9
N8
N7
N6
N5
Initial value
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
Note:
*
4
3
N4 N3
0/1* 0
R
R
2
1
0
N2
N1
N0
0
0
0
R
R
R
The initial value of bit N4 is 0 in FVSR0O, and 1 in the other FVSR registers.
The FVSR registers indicate the number of valid data bytes in the FIFO for each host input/host
output involving the respective USB function endpoints. In host input transfer, the FVSR register
indicates the number of bytes that the slave CPU can write to the FIFO (the FIFO size minus the
number of bytes written to the FIFO by the slave CPU but not read (transmitted) by the USB
function). In host output transfer, the FVSR register indicates the number of bytes received and
written to the FIFO by the USB function but not read by the slave CPU.
In host input transfer, the FVSR value is decremented by the number of bytes written when the
slave CPU writes to EPDR and sets the EPTE bit in PTTER, and is incremented by the number of
bytes read when the USB function reads the FIFO and receives an ACK handshake from the host.
In host output transfer, the FVSR value is incremented by the number of bytes written when the
USB function writes to the FIFO and transmits an ACK handshake, and is decremented by 1 each
time the slave CPU reads EPDR.
If a transfer error occurs, data retransfer may be necessary. In this case, the FVSR value is not
changed and the FIFO for the relevant channel is rewound.
In the USB protocol, for each endpoint DATA0 and DATA1 packets are transmitted and received
alternately when data transfer is performed. This toggling between DATA0 and DATA1 also
serves as an indicator of whether or not data transfer has been performed normally. If
DATA0/DATA1 toggling is not performed normally in host output transfer, the USB function will
abort processing of that transaction and the FVSR value will not change.
Since the FVSR registers are 2-byte registers and the H8’s FIFOs are 16 or 32 bytes in length, the
FIFO status can be indicated in the lower byte alone. Only the lower byte of the FVSR registers
should be read.
The upper byte of the FVSR registers cannot be accessed directly. When the lower byte is read,
the upper byte is transferred to a temporary register, and when the upper byte is read, the contents
of this temporary register are read. When a word read is used on an FVSR register, the operation is
Rev. 3.00 Mar 17, 2006 page 110 of 706
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Section 7 Universal Serial Bus Interface (USB)
automatically divided into two byte accesses, with the upper byte read first, followed by the lower
byte. Caution is required in this case, since the upper byte value that is read is the value at the
point when the lower byte was read previously.
FVSR0I and FVSR1 are automatically initialized to H'0010 and H'0000, respectively, when a
SETUP token is received.
The FVSR registers are initialized by a system reset or a function soft reset. The initial value
depends on the transfer direction and FIFO size determined by EPDIR and EPSZR.
7.2.5
Endpoint Direction Register (EPDIR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
EP2DIR
EP1DIR
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
R
R
R
R
R/W
R/W
R
R
EPDIR controls the data transfer direction for USB function endpoints other than endpoint 0.
With the H8/3567U and H8/3564U, EP1 should be designated for host input transfer and EP2 for
host input transfer or host output transfer.
EPDIR is initialized to H'FC by a system reset or a function soft reset.
Bit 3—Endpoint 2 Data Transfer Direction Control Flag (EP2DIR): Switches the endpoint 2
data transfer direction.
Bit 3
EP2DIR
Description
0
Endpoint 2 is designated for host output transfer
1
Endpoint 2 is designated for host input transfer
(Initial value)
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Section 7 Universal Serial Bus Interface (USB)
Bit 2—Endpoint 1 Data Transfer Direction Control Flag (EP1DIR): Switches the endpoint 1
data transfer direction. This bit must not be cleared to 0.
Bit 2
EP1DIR
Description
0
Setting prohibited
1
Endpoint 1 is designated for host input transfer
7.2.6
Packet Transmit Enable Register (PTTER)
Bit
Initial value
Read/Write
Note:
(Initial value)
*
7
6
5
4
3
2
1
0
—
—
—
—
EP2TE
EP1TE
EP0ITE
—
0
0
0
0
0
0
0
0
R
R/(W)*
R/(W)*
R/(W)*
R
R
R
R
Only 1 can be written.
PTTER contains control bits (EPTE) that control the FIFO valid size registers for USB function
host input transfer.
In the USB protocol, communication is carried out using packets. The minimum unit of data
transfer is a transaction, and a transaction is made up of a token packet, data packet, and
handshake packet.
In host input transfer, the USB function receives an IN token (packet). If operation has not stalled,
in response to this token the USB function must transmit a data packet or, if there is no data, a
NAK handshake.
When EPTE is set to 1 after the data to be transmitted by the USB function has been written to the
FIFO by the slave CPU, the FVSR contents are updated. This enables transmission of the data
written to the FIFO. This EPTE-bit data transmission control prevents data transmission from
being done while the slave CPU is writing data to the FIFO. The EPTE can only be written with 1,
and are always read as 0.
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Section 7 Universal Serial Bus Interface (USB)
Bit 3—Endpoint 2 Packet Transmit Enable (EP2TE): Updates endpoint 2 FVSR2 when the
EP2DIR bit is set to 1.
Bit 3
EP2TE
Description
0
Normal read value
(1)
(Initial value)
[1 write]
Endpoint 2 IN-FIFO FVSR2 is updated
Bit 2—Endpoint 1 Packet Transmit Enable (EP1TE): Updates endpoint 1 FVSR1.
Bit 2
EP1TE
Description
0
Normal read value
(1)
(Initial value)
[1 write]
Endpoint 1 IN-FIFO FVSR1 is updated
Bit 1—Endpoint 0I Packet Transmit Enable (EP0ITE): Updates endpoint 0 FVSR0I.
Bit 1
EP0ITE
Description
0
Normal read value
(1)
[1 write]
(Initial value)
Endpoint 0 IN-FIFO FVSR0I is updated
7.2.7
USB Interrupt Enable Register (USBIER)
Bit
7
6
5
4
3
2
1
0
—
—
BRSTE
SOFE
SPNDE
TFE
TSE
SETUPE
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
USBIER contains enable bits that enable interrupts from the USB function to the slave CPU.
USBIER is initialized to H'00 by a system reset or a function soft reset.
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Section 7 Universal Serial Bus Interface (USB)
Bit 5—Bus Reset Interrupt Enable (BRSTE): Enables or disables bus request interrupts to the
internal CPU.
Bit 5
BRSTE
Description
0
USB function bus request interrupts disabled
1
USB function bus request interrupts enabled
(Initial value)
Bit 4—SOF Interrupt Enable (SOFE): Enables or disables SOF (Start of Frame) interrupts to
the internal CPU.
Bit 4
SOFE
Description
0
USB function SOF interrupts disabled
1
USB function SOF interrupts enabled
(Initial value)
Bit 3—Suspend Interrupt Enable (SPNDE): Enables or disables suspend OUT interrupts and
suspend IN interrupts to the internal CPU.
Bit 3
SPNDE
Description
0
USB function suspend OUT interrupts and suspend IN interrupts disable
(Initial value)
1
USB function suspend OUT interrupts and suspend IN interrupts enabled
Bit 2—Transfer Failed Interrupt Enable (TFE): Enables or disables transfer failed interrupts to
the internal CPU.
Bit 2
TFE
Description
0
USB function transfer failed interrupts disabled
1
USB function transfer failed interrupts enabled
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(Initial value)
Section 7 Universal Serial Bus Interface (USB)
Bit 1—Transfer Successful Interrupt Enable (TSE): Enables or disables transfer successful
interrupts to the internal CPU.
Bit 1
TSE
Description
0
USB function transfer successful interrupts disabled
1
USB function transfer successful interrupts enabled
(Initial value)
Bit 0—Setup Interrupt Enable (SETUPE): Enables or disables setup interrupts to the internal
CPU.
Bit 0
SETUPE
Description
0
USB function setup interrupts disabled
1
USB function setup interrupts enabled
7.2.8
USB Interrupt Flag Register (USBIFR)
Bit
Initial value
Read/Write
Note:
(Initial value)
*
7
6
5
4
3
TS
TF
—
BRSTF
SOFF
0
0
0
0
0
0
0
0
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
2
1
0
SPNDOF SPNDIF SETUPF
Only 0 can be written, after reading 1, to clear the flag.
USBIFR contains interrupt flags that generate interrupts from the USB function to the slave CPU.
The USB module has four interrupt sources (USBIA, USBIB, USBIC, and USBID). USBIA is a
dedicated setup interrupt. A single transfer successful interrupt or transfer failed interrupt can be
assigned to USBIB and USBIC. All other interrupts (all transfer successful interrupts and transfer
failed interrupts, bus reset interrupts, SOF interrupts, and suspend OUT and suspend IN interrupts)
are assigned to USBID.
USBIFR is initialized to H'00 by a system reset or a function soft reset.
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Section 7 Universal Serial Bus Interface (USB)
Bit 7—Transfer Successful Interrupt Status (TS): Status flag that indicates that transfer has
ended normally at a USB function endpoint.
When the TSE bit is 1, USBID interrupt request is sent to the slave CPU, but if a setting has been
made for the source that set TS to 1 to request USBIB or USBIC interrupt, has priority for
processing in accordance with the priority order in the slave CPU’s interrupt controller (INTC).
TS is a read-only flag.
Bit 7
TS
Description
0
All bits in transfer success flag register (TSFR) are 0
1
At least one bit in transfer success flag register (TSFR) is 1
(Initial value)
Bit 6—Transfer Failed Interrupt Status (TF): Status flag that indicates that transfer has ended
abnormally at a USB function endpoint.
When the TFE bit is 1, USBID interrupt request is sent to the slave CPU, but if a setting has been
made for the source that set TF to 1 to request USBIB or USBIC interrupt, has priority for
processing in accordance with the priority order in the slave CPU’s interrupt controller (INTC).
TF is a read-only flag.
Bit 6
TF
Description
0
All bits in transfer fail flag register (TFFR) are 0
1
At least one bit in transfer fail flag register (TFFR) is 1
(Initial value)
Bit 4—Bus Reset Interrupt Flag (BRSTF): Status flag that indicates that the USB function has
detected a bus reset from upstream.
When the BRSTE bit is 1, USBID interrupt request is sent to the slave CPU.
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Section 7 Universal Serial Bus Interface (USB)
Bit 4
BRSTF
Description
0
[Clearing condition]
(Initial value)
When 0 is written to BRSTF after reading BRSTF = 1
1
[Setting condition]
When USB function detects a bus reset from upstream
Bit 3—SOF Interrupt Flag (SOFF): Status flag that indicates that the USB function has detected
SOF (Start of Frame).
When the SOFE bit is 1, USBID interrupt request is sent to the slave CPU.
Bit 3
SOFF
Description
0
[Clearing condition]
(Initial value)
When 0 is written to SOFF after reading SOFF = 1
1
[Setting condition]
When USB function detects SOF (Start of Frame)
Bit 2—Suspend OUT Interrupt Flag (SPNDOF): Status flag that indicates that the USB
function has detected a change in the bus status, and has switched from the suspend state to the
normal state.
When the SPNDE bit is 1, USBID interrupt request is sent to the slave CPU.
Bit 2
SPNDOF
Description
0
[Clearing condition]
(Initial value)
When 0 is written to SPNDOF after reading SPNDOF = 1
1
[Setting condition]
When USB function switches from suspend state to normal state
Bit 1—Suspend IN Interrupt Flag (SPNDIF): Status flag that indicates that the USB function
has detected a bus idle state lasting longer that the specified time, and has switched from the
normal state to the suspend state.
When the SPNDE bit is 1, USBID interrupt request is sent to the slave CPU.
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Section 7 Universal Serial Bus Interface (USB)
Bit 1
SPNDIF
Description
0
[Clearing condition]
(Initial value)
When 0 is written to SPNDIF after reading SPNDIF = 1
1
[Setting condition]
When USB function switches from normal state to suspend state
Bit 0—Setup Interrupt Flag (SETUPF): Status flag that indicates that USB function endpoint 0
has received a SETUP token.
When the SETUPE bit is 1, USBIA interrupt request is sent to the slave CPU.
Bit 0
SETUPF
Description
0
[Clearing condition]
(Initial value)
When 0 is written to SETUPF after reading SETUPF = 1
1
[Setting condition]
When USB function endpoint 0 receives SETUP token
7.2.9
Transfer Success Flag Register (TSFR)
Bit
Initial value
Read/Write
Note:
*
7
6
5
4
3
2
1
0
—
—
—
—
EP2TS
EP1TS
EP0ITS
EP0OTS
0
0
0
0
0
0
0
0
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R
Only 0 can be written, after reading 1, to clear the flag.
TSFR contains status flags (EPTS flags) that indicate that a USB function endpoint host input/host
output transaction has ended normally. The condition for a normal end of a transaction is reception
of an ACK handshake in host input transfer, or transmission of an ACK handshake in host output
transfer.
When at least one EPTS flag is set to 1, the TS flag in USBIFR is also set at the same time. The
TS flag generates an interrupt to the slave CPU. The EPTS flags must be cleared to 0 in the
interrupt handling routine. When all the EPTS flags are cleared, the TS flag is automatically
cleared to 0. Only 0 can be written to the EPTS flags, after first reading 1.
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Section 7 Universal Serial Bus Interface (USB)
When the USB function receives a SETUP token, the EP0ITS and EP0OTS flags are
automatically cleared to 0.
TSFR is initialized to H'00 by a system reset or a function soft reset.
Bit 3—Endpoint 2 Transfer Success Flag (EP2TS): Indicates that an endpoint 2 host input
transfer or host output transfer has ended normally.
Bit 3
EP2TS
0
Description
Endpoint 2 is in transfer standby state
(Initial value)
[Clearing condition]
When 0 is written to EP2TS after reading EP2TS = 1
1
Endpoint 2 host input transfer (IN transaction) or host output transfer (OUT
transaction) has ended normally
[Setting conditions]
•
ACK handshake established after IN token reception and data transfer (ACK
reception)
•
ACK handshake established after OUT token reception and data transfer (ACK
transmission)
Bit 2—Endpoint 1 Transfer Success Flag (EP1TS): Indicates that an endpoint 1 host input
transfer has ended normally.
Bit 2
EP1TS
Description
0
Endpoint 1 is in transfer standby state
(Initial value)
[Clearing condition]
When 0 is written to EP1TS after reading EP1TS = 1
1
Endpoint 1 host input transfer (IN transaction) has ended normally
[Setting condition]
ACK handshake established after IN token reception and data transfer (ACK
reception)
Bit 1—Endpoint 0 Host Input Transfer Success Flag (EP0ITS): Indicates that an endpoint 0
host input transfer has ended normally.
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Section 7 Universal Serial Bus Interface (USB)
Bit 1
EP0ITS
Description
0
Endpoint 0 is in host input transfer standby state
(Initial value)
[Clearing conditions]
1
•
When 0 is written to EP0ITS after reading EP0ITS = 1
•
When endpoint 0 receives a SETUP token
Endpoint 0 host input transfer (IN transaction) has ended normally
[Setting condition]
ACK handshake established after IN token reception and data transfer (ACK
reception)
Bit 0—Endpoint 0 Host Output Transfer Success Flag (EP0OTS): Indicates that an endpoint 0
host output transfer has ended normally.
Host output transfers to endpoint 0 include OUT transactions and SETUP transactions. These
operations are the same in terms of data transfer, but differ as regards flag handling.
Most commands transferred in SETUP transactions are processed within the USB function, in
which case the EP0OTS flag is not set and the EP0OTF flag is.
In the case of a command that cannot be processed within the USB function, the EP0OTS flag is
set.
Bit 0
EP0OTS
Description
0
Endpoint 0 is in host output transfer standby state
(Initial value)
[Clearing conditions]
1
•
When 0 is written to EP0OTS after reading EP0OTS = 1
•
When endpoint 0 receives a SETUP token
Endpoint 0 host output transfer (OUT transaction or SETUP transaction) has ended
normally
[Setting conditions]
•
ACK handshake established after OUT token reception and data transfer (ACK
transmission)
•
When command received after SETUP token reception requires processing by
the slave CPU
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Section 7 Universal Serial Bus Interface (USB)
7.2.10
Transfer Fail Flag Register (TFFR)
Bit
Initial value
Read/Write
Note:
*
7
6
5
4
3
2
1
0
—
—
—
—
EP2TF
EP1TF
EP0ITF
EP0OTF
0
0
0
0
0
0
0
0
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R
Only 0 can be written, after reading 1, to clear the flag.
TFFR contains status flags (EPTF flags) that indicate that a USB function endpoint host input/host
output transaction has not ended normally. The condition for an abnormal end of a transaction is
NAK handshake reception, or NAK handshake transmission when there is no transfer data (FVSR
= FIFO size (FIFO empty)), in host input transfer, or, in host output transfer, NAK handshake
transmission due to a FIFO full condition, etc., or any of various communication errors
(DATA0/DATA1 toggle error, bit stuffing error, bit count error, CRC error, transfer of a number
of bytes exceeding MaxPktSz, etc.) during data transfer.
When at least one EPTF flag is set to 1, the TF flag in USBIFR is also set at the same time. The
TF flag generates an interrupt to the slave CPU. The EPTF flags must be cleared to 0 in the
interrupt handling routine. When all the EPTF flags are cleared, the TF flag is automatically
cleared to 0. Only 0 can be written to the EPTF flags, after first reading 1.
When the USB function receives a SETUP token, the EP0ITF and EP0OTF flags are
automatically cleared to 0.
TFFR is initialized to H'00 by a system reset or a function soft reset.
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Section 7 Universal Serial Bus Interface (USB)
Bit 3—Endpoint 2 Transfer Fail Flag (EP2TF): Indicates that an endpoint 2 host input transfer
or host output transfer has not ended normally.
Bit 3
EP2TF
Description
0
Endpoint 2 is in transfer standby state
(Initial value)
[Clearing condition]
When 0 is written to EP2TF after reading EP2TF = 1
1
Endpoint 2 host input transfer (IN transaction) or host output transfer (OUT
transaction) has ended abnormally
[Setting conditions]
•
ACK handshake not established after IN token reception and data transfer
•
Data transfer not possible due to FIFO empty condition after IN token reception
•
Data transfer not possible due to FIFO full condition after OUT token reception
(NAK transmission)
•
Data transfer errors after OUT token reception
Bit 2—Endpoint 1 Transfer Fail Flag (EP1TF): Indicates that an endpoint 1 host input transfer
has not ended normally.
Bit 2
EP1TF
Description
0
Endpoint 1 is in transfer standby state
(Initial value)
[Clearing condition]
When 0 is written to EP1TF after reading EP1TF = 1
1
Endpoint 1 host input transfer (IN transaction) has ended abnormally
[Setting conditions]
•
ACK handshake not established after IN token reception and data transfer
•
Data transfer not possible due to FIFO empty condition after IN token reception
(NAK transmission)
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Section 7 Universal Serial Bus Interface (USB)
Bit 1—Endpoint 0 Host Input Transfer Fail Flag (EP0ITF): Indicates that an endpoint 0 host
input transfer has not ended normally.
Bit 1
EP0ITF
Description
0
Endpoint 0 is in host input transfer standby state
(Initial value)
[Clearing conditions]
1
•
When 0 is written to EP0ITF after reading EP0ITF = 1
•
When endpoint 0 receives a SETUP token
Endpoint 0 host input transfer (IN transaction) has ended abnormally
[Setting conditions]
•
ACK handshake not established after IN token reception and data transfer
•
Data transfer not possible due to FIFO empty condition after IN token reception
(NAK transmission)
Bit 0—Endpoint 0 Host Output Transfer Fail Flag (EP0OTF): Indicates that an endpoint 0
host output transfer has not ended normally.
Host output transfers to endpoint 0 include OUT transactions and SETUP transactions. These
operations are the same in terms of data transfer, but differ as regards flag handling.
Most commands transferred in SETUP transactions are processed within the USB function, in
which case the EP0OTS flag is not set and the EP0OTF flag is.
In the case of a command that cannot be processed within the USB function, the EP0OTS flag is
set.
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Section 7 Universal Serial Bus Interface (USB)
Bit 0
EP0OTF
Description
0
Endpoint 0 is in host output transfer standby state
(Initial value)
[Clearing conditions]
1
•
When 0 is written to EP0OTF after reading EP0OTF = 1
•
When endpoint 0 receives a SETUP token
Endpoint 0 host output transfer (OUT transaction or SETUP transaction) has ended
abnormally
[Setting conditions]
7.2.11
•
Transfer not possible due to FIFO full condition after OUT token reception (NAK
transmission)
•
Data transfer not possible because EP0OTC = 0 after OUT token reception
(NAK transmission)
•
Communication error after OUT token reception
•
When command received after SETUP token reception can be processed within
the USB function
USB Control/Status Register 0 (USBCSR0)
Bit
7
6
5
4
3
DP5CNCT DP4CNCT DP3CNCT DP2CNCT EP0STOP
2
1
0
EPIVLD
EP0OTC
CKSTOP
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
USBCSR0 contains flags that indicate the USB hubs’ downstream port connection status, and bits
that control the operation of the USB function.
USBCSR0 is initialized to H'00 by a system reset, and bits 3 to 0 are also cleared to 0 by a
function soft reset.
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Section 7 Universal Serial Bus Interface (USB)
Bits 7 to 4—Downstream Port Connect 5 to 2 (DP5CNCT, DP4CNCT, DP3CNCT,
DP2CNCT): Read-only status flags that indicate the connection status of the USB hubs’ external
downstream ports.
Bits 7 to 4
DP5CNCT to
DP2CNCT
Description
0
Cable is not connected to downstream port
(Initial value)
[Clearing conditions]
•
System reset
•
Downstream port disconnect
•
USB hub upstream port disconnect
(Total downstream disconnect by software in reconnect process)
1
Cable is connected to downstream port, and power is being supplied
[Setting condition]
Downstream port connect
Bit 3—Endpoint 0 Stop (EP0STOP): Bit that protects the contents of the USB function endpoint
0 FIFO. Setting EP0STOP to 1 enables the data transferred to the EP0 OUT-FIFO by a SETUP
transaction to be protected.
Bit 3
EP0STOP
Description
0
EP0 OUT-FIFO, IN-FIFO operational
(Initial value)
[Clearing conditions]
1
•
System reset
•
Function soft reset
EP0 OUT-FIFO reading stopped
•
FVSR0O contents are not changed by an EPDR0O read
EP0 IN-FIFO writing and transfer stopped
•
FIFO contents are not changed by an EPDR0I write
•
FVSR0I contents are not changed by setting EP0ITE
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Section 7 Universal Serial Bus Interface (USB)
Bit 2—Endpoint Information Valid (EPIVLD): This bit makes the USB function block
operational.
Part of the process that makes the USB function block operational includes an endpoint
information setting. After a system reset or function soft reset, the USB function block does not
have any endpoint information. Endpoint information for the USB function in the H8/3567U and
H8/3564U (see section 7.3.9, USB Module Startup Sequence) can be set by sequential writes to
EPDR0I. When all the data has been written, the written endpoint information is made valid by
setting the EPIVLD bit to 1. Writing 0 to the EPIVLD bit has no effect.
Bit 2
EPIVLD
Description
0
Endpoint information (EPINFO) has not been set
(Initial value)
[Clearing conditions]
1
•
System reset
•
Function soft reset
Endpoint information (EPINFO) has been set
Bit 1—Endpoint 0O Transfer Control (EP0OTC): Controls USB function endpoint 0 control
transfer. Clearing EP0OTC to 0 disables writes to the EP0 OUT-FIFO. A change of data transfer
direction within a control transfer can be reported by means of the transfer fail interrupt caused by
this action. In control transfer, a command is received in the SETUP transaction (command stage),
then data transfer is performed in an OUT or IN transaction (data stage), and finally a transfer
equivalent to a handshake is carried out in an IN or OUT transaction (status stage).
When a SETUP token is received, EP0OTC is set to 1, FVSR is initialized, and command data can
be received. On completion of command data reception, EP0OTC is cleared to 0 and the contents
of the EP0O-FIFO are protected. If the command cannot be processed automatically by the USB
function core, the EP0OTS flag is set and the slave CPU must decode the command.
If command decoding shows that an OUT transaction will follow as the data stage, the slave CPU
must set EP0OTC to 1 in preparation for an OUT transaction. If the command stage is followed by
an IN transaction data stage, the slave CPU leaves EP0OTC cleared to 0. When the host CPU
begins an OUT transaction as the status stage, the EP0OTF flag is set and a transfer fail interrupt
is generated, enabling the slave CPU to recognize the end of the data stage. In response to this
interrupt, the slave CPU sets EP0OTC to 1 and receives retransferred status stage data.
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Section 7 Universal Serial Bus Interface (USB)
Bit 1
EP0OTC
Description
0
EP0 OUT-FIFO writing stopped
•
(Initial value)
Subsequent writes to EP0 OUT-FIFO are invalid
[Clearing conditions]
1
•
System reset
•
Function soft reset
•
Command data reception in SETUP transaction (EP0OTS flag setting)
EP0 OUT-FIFO operational
[Setting conditions]
•
SETUP token reception
•
When 1 is written to EP0OTC after reading EP0OTC = 0
Bit 0—Clock Stop (CKSTOP): Controls the USB function operating clock. When the USB
function is placed in the suspend state due to a bus idle condition, this bit should be set to 1 after
the necessary processing is completed. The clock supply to the USB function is then stopped,
reducing power consumption.
When the CKSTOP bit is set to 1, writes to USB module registers are invalid. If these registers are
read, the contents of the read data are not guaranteed, but there are no read-related status changes
(such as decrementing of FVSR).
If a bus idle condition of the specified duration or longer is detected, the suspend IN interrupt flag
is set, and when a change in the bus status is subsequently detected the suspend OUT interrupt flag
is set. When the suspend OUT interrupt flag is set, the CKSTOP bit is simultaneously cleared to 0.
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Section 7 Universal Serial Bus Interface (USB)
Bit 0
CKSTOP
Description
0
Clock is supplied to USB function
(Initial value)
[Clearing conditions]
1
•
System reset
•
Function soft reset
•
Suspend OUT interrupt flag setting
Clock supply to USB function is stopped
[Setting condition]
When 1 is written to CKSTOP after reading CKSTOP = 0 in the function suspend
state
7.2.12
Endpoint Stall Register (EPSTLR)
Bit
7
6
5
4
3
—
—
—
—
Initial value
0
0
0
0
0
Read/Write
R
R
R
R
R/W
2
1
0
—
EP0STL
0
0
0
R/W
R
R/W
EP2STL EP1STL
EPSTLR contains bits (EPSTL) that place the USB function endpoints in the stall state.
When an EPSTL bit is set to 1, the corresponding endpoint sends a STALL handshake in reply to
the start of a transaction through reception of a token from the host.
When the USB function receives a SETUP token, the EP0STL bit is automatically cleared to 0.
EPSTLR is initialized to H'00 by a system reset or a function soft reset.
Bit 3—Endpoint 2 Stall (EP2STL): Places endpoint 2 in the stall state.
Bit 3
EP2STL
Description
0
Endpoint 2 is operational
1
Endpoint 2 is in stall state
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(Initial value)
Section 7 Universal Serial Bus Interface (USB)
Bit 2—Endpoint 1 Stall (EP1STL): Places endpoint 1 in the stall state.
Bit 2
EP1STL
Description
0
Endpoint 1 is operational
1
Endpoint 1 is in stall state
(Initial value)
Bit 0—Endpoint 0 Stall (EP0STL): Places endpoint 0 in the stall state. Writing 0 to the EP0STL
bit has no effect.
Bit 0
EP0STL
Description
0
Endpoint 0 is operational
(Initial value)
[Clearing condition]
When endpoint 0 receives a SETUP token
1
Endpoint 0 is in stall state
[Setting condition]
When 1 is written to EP0STL after reading EP0STL = 0
7.2.13
Endpoint Reset Register (EPRSTR)
Bit
Initial value
Read/Write
Note:
*
7
6
5
4
—
—
—
—
0
0
0
0
0
0
0
0
R
R/(W)*
R/(W)*
R/(W)*
R
R
R
R
3
2
1
EP2RST EP1RST EP0IRST
0
—
Only 1 can be written.
EPRSTR contains control bits (EPRST) that reset the pointer of the FIFO for a USB function
endpoint host input transfer.
When an EPRST bit is set to 1, the corresponding FIFO valid size register (FVSR) is initialized.
The EPRST bits can only be written with 1, and are always read as 0.
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Section 7 Universal Serial Bus Interface (USB)
Bit 3—Endpoint 2 Reset (EP2RST): Initializes the endpoint 2 FIFO.
Bit 3
EP2RST
Description
0
Normal read value
(1)
[1 write]
(Initial value)
EP2DIR = 0: FVSR2 is initialized to H'0000
EP2DIR = 1: FVSR2 is initialized to H'0010
Bit 2—Endpoint 1 Reset (EP1RST): Initializes the endpoint 1 FIFO.
Bit 2
EP1RST
Description
0
Normal read value
(1)
[1 write]
(Initial value)
EP1 FIFO size = 16 bytes: FVSR1 is initialized to H'0010
EP1 FIFO size = 32 bytes: FVSR1 is initialized to H'0020
Bit 1—Endpoint 0I Reset (EP0IRST): Initializes the endpoint 0I FIFO.
Bit 1
EP0IRST
Description
0
Normal read value
(1)
[1 write]
FVSR0I is initialized to H'0010
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(Initial value)
Section 7 Universal Serial Bus Interface (USB)
7.2.14
Device Resume Register (DEVRSMR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
DVR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R/(W)*
Note:
Only 1 can be written.
*
DEVRSMR contains a bit (DVR) that control remote wakeup of the USB function suspend state.
When 1 is written to the DVR bit, the suspend state is cleared.
The DVR bit can only be written with 1, and is always read as 0.
1 can be written to the DVR bit even if the CKSTOP bit is set to 1 in USBCSR0.
Bit 0—Device Resume (DVR): Clears the suspend state.
Bit 0
DVR
Description
0
Normal read value
(1)
[1 write]
(Initial value)
Suspend state is cleared (remote wakeup)
7.2.15
Interrupt Source Select Register 0 (INTSELR0)
Bit
7
6
5
4
3
2
1
0
TSELB
EPIBS2
EPIBS1
EPIBS0
TSELC
EPICS2
EPICS1
EPICS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
INTSELR0 contains bits that select the USB function USBIB and USBIC interrupt sources.
INTSELR0 is initialized to H'00 by a system reset or a function soft reset.
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Section 7 Universal Serial Bus Interface (USB)
Bit 7—Transfer Select B (TSELB): Together with bits EPIBS2 to EPIBS0, selects USBIB
interrupt source.
Bit 7
TSELB
Description
0
USBIB interrupt is requested by a TS interrupt; the endpoint constituting the TS
interrupt source is specified by bits EPIBS2 to EPIBS0
(Initial value)
1
USBIB interrupt is requested by a TF interrupt; the endpoint constituting the TF
interrupt source is specified by bits EPIBS2 to EPIBS0
Bits 6 to 4—Interrupt B Endpoint Select 2 to 0 (EPIBS2 to EPIBS0): Together with the
TSELB bit, these bits select USBIB interrupt source.
Bit 6
Bit 5
Bit 4
EPIBS2
EPIBS1
EPIBS0
Description
0
0
0
Endpoint not selected
1
1
—
1
Endpoint 1 selected
0
Endpoint 2 selected
1
Setting prohibited
—
Setting prohibited
(Initial value)
Bit 3—Transfer Select C (TSELC): Together with bits EPICS2 to EPICS0, selects USBIC
interrupt source.
Bit 3
TSELC
Description
0
USBIC interrupt is requested by a TS interrupt; the endpoint constituting the TS
interrupt source is specified by bits EPICS2 to EPICS0
(Initial value)
1
USBIC interrupt is requested by a TF interrupt; the endpoint constituting the TF
interrupt source is specified by bits EPICS2 to EPICS0
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Section 7 Universal Serial Bus Interface (USB)
Bits 2 to 0—Interrupt C Endpoint Select 2 to 0 (EPICS2 to EPICS0): Together with the
TSELC bit, these bits select USBIC interrupt source.
Bit 2
Bit 1
Bit 0
EPICS2
EPICS1
EPICS0
Description
0
0
0
Endpoint not selected
1
Endpoint 1 selected
0
Endpoint 2 selected
1
Setting prohibited
—
Setting prohibited
1
1
7.2.16
—
(Initial value)
Interrupt Source Select Register 1 (INTSELR1)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DTCBE
DTCCE
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R/W
R/W
Register INTSELR1 is not used in this model.
Do not write 1 to the bits in INTSELR1.
7.2.17
Hub Overcurrent Control Register (HOCCR)
Bit
7
6
5
4
3
2
1
0
—
—
PCSP
OCDSP
HOC5E
HOC4E
HOC3E
HOC2E
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
The USB hub downstream ports are connected to the USB connector as data (D+/D–). The power
supply (VBUS) connected to the USB connector is generated by connecting a power supply
control IC externally.
HOCCR contains bits that control the power supply control IC control input/output.
HOCCR is initialized to H'00 by a system reset.
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Section 7 Universal Serial Bus Interface (USB)
Bit 5—Power Supply Enable Control Polarity (PCSP): This bit is set according to the polarity
of the power supply control IC output enable inputs.
The power supply control IC output enable inputs are connected to H8 pins ENP5 to ENP2.
Bit 5
PCSP
Description
0
Power supply control IC requires low-level input for enabling
1
Power supply control IC requires high-level input for enabling
(Initial value)
Bit 4—Overcurrent Detection Polarity (OCDSP): This bit is set according to the polarity of the
power supply control IC overcurrent detection outputs.
The power supply control IC overcurrent detection outputs are connected to H8 pins OCP5 to
OCP2.
Bit 4
OCDSP
Description
0
Power supply control IC outputs low level in case of overcurrent detection
(Initial value)
1
Power supply control IC outputs high level in case of overcurrent detection
Bits 3 to 0—Overcurrent Detection Control Enable 5 to 2 (HOC5E to HOC2E): These pins
select whether or not power supply control IC control is performed for each USB hub downstream
port.
If any of the four downstream ports are not used, the corresponding D+/D- pins should be pulled
down as specified. Leave the corresponding HOCE bit cleared to 0, disabling the corresponding
output enable pin and overcurrent detection pin. Disabled pins can be used as general port pins
(port C).
Bit 3
HOC5E
Description
0
Pins ENP5 and OCP5 are general ports (PC7, PC3)
1
Pins ENP5 and OCP5 have output enable and overcurrent detection functions
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(Initial value)
Section 7 Universal Serial Bus Interface (USB)
Bit 2
HOC4E
Description
0
Pins ENP4 and OCP4 are general ports (PC6, PC2)
1
Pins ENP4 and OCP4 have output enable and overcurrent detection functions
(Initial value)
Bit 1
HOC3E
Description
0
Pins ENP3 and OCP3 are general ports (PC5, PC1)
1
Pins ENP3 and OCP3 have output enable and overcurrent detection functions
(Initial value)
Bit 0
HOC2E
Description
0
Pins ENP2 and OCP2 are general ports (PC4, PC0)
1
Pins ENP2 and OCP2 have output enable and overcurrent detection functions
7.2.18
(Initial value)
USB Control Register (USBCR)
Bit
7
6
FADSEL
FONLY
5
4
3
2
1
0
FNCSTP UIFRST HPLLRST HSRST FPLLRST FSRST
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
USBCR contains bits (FADSEL, FONLY, FNCSTP) that control USB function and USB hub
internal connection, and reset control bits for sequential enabling of the operation of each part
according to the USB module start-up sequence.
USBCR is initialized to H'7F by a system reset [in an H8/3567U and H8/3564U reset (by RES
input or the watchdog timer), and in hardware standby mode]. It is not initialized in software
standby mode.
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Section 7 Universal Serial Bus Interface (USB)
Bit 7—USB Function I/O Analog/Digital Select (FADSEL): Selects the USB function data
input/output method when the FONLY bit is set to 1 so that the USB hub block is disabled and
only the USB function block operates.
Bit 7
FADSEL
Description
0
USD+ and USD– pins are used for USB function block data input/output
(Initial value)
1
USB function block data input/output is implemented by multiplexing Philips
transceiver/receiver (PDIUSB11A) compatible control input/output with port C pins
Port C
Philips PDIUSB11A
PC7
Input
VP
Differential input (+)
PC6
Input
VM
Differential input (–)
PC5
Input
RCV
Data input
PC4
Output
VPO
Differential output (+)
PC3
Output
VMO
Differential output (–)
PC2
Output
OE
Output enable
PC1
Output
SUSPEND
Suspend setting
PC0
Output
SPEED
Speed setting
High level fixed output for 12 Mbps specification
Bit 6—USB Function Select (FONLY): Selects enabling/disabling of the USB hub block. When
the USB hub block is enabled, the USB function block is connected internally to USB hub
downstream port 1. When the USB hub block is disabled, the USB function block is directly
connected to the upstream port, and the USB operating clock selected/divided/multiplied in
accordance with UPLLCR settings is not supplied to the USB hub block.
Bit 6
FONLY
Description
0
USB function block is connected internally to USB hub downstream port 1
USB hub block is enabled
1
USB function block is directly connected to upstream port
USB hub block is disabled
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(Initial value)
Section 7 Universal Serial Bus Interface (USB)
Bit 5—USB Function Stop/Suspend (FNCSTP): With the H8/3567U and H8/3564U, it is
possible to disconnect the USB function block from the USB hub block’s downstream port 1, and
set a power-down state in which the USB operating clock supply is halted. Register accesses by
the CPU are still possible in this state.
The FNCSTP bit is used when disconnecting the USB function block and switching the
microcomputer block to power-down mode when the system’s power supply is cut, or when
reconnecting the USB function block when recovering from power-down mode or in the event of a
power-on reset.
When the FNCSTP bit is set to 1, the USB operating clock selected/divided/multiplied in
accordance with UPLLCR settings is not supplied to the USB function block.
Bit 5
FNCSTP
Description
0
For USB function block, USB hub downstream port 1 internal connection is set to
connected state
1
For USB function block, USB hub downstream port 1 internal connection is set to
disconnected state, and power-down state is set
(Initial value)
Bit 4—USB Interface Soft reset (UIFRST): Resets the EPSZR1, USBIER, EPDIR, INTSELR0,
and INTSELR1 registers. When UIFRST is set to 1, the EPSZR1, USBIER, EPDIR, INTSELR0,
and INTSELR1 registers are initialized.
Bit 4
UIFRST
Description
0
EPSZR1, USBIER, EPDIR, INTSELR0, and INTSELR1 are placed in operational
state
1
EPSZR1, USBIER, EPDIR, INTSELR0, and INTSELR1 are placed in reset state
(Initial value)
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Section 7 Universal Serial Bus Interface (USB)
Bit 3—Hub Block PLL Soft reset (HPLLRST): Resets the USB bus clock circuit (DPLL) in the
hub.
When HPLLRST is set to 1, the DPLL circuit in the hub is reset, and bus clock synchronous
operation halts. HPLLRST is cleared to 0 after PLL operation stabilizes.
Bit 3
HPLLRST
Description
0
Hub DPLL is placed in operational state
1
Hub DPLL is placed in reset state
(Initial value)
Bit 2—Hub Block Internal State Soft reset (HSRST): Resets the internal state of the USB hub
block.
When HSRST is set to 1, the internal state of the USB hub block, excluding the internal USB bus
clock circuit (DPLL), is initialized. HSRST is cleared to 0 after DPLL operation stabilizes.
Bit 2
HSRST
Description
0
Internal state of USB hub block is set to operational state
1
Internal state of USB hub block is set to reset state (excluding DPLL) (Initial value)
Bit 1—Function Block PLL Soft reset (FPLLRST): Resets the USB bus clock circuit (DPLL)
in the function.
When FPLLRST is set to 1, the DPLL circuit in the function is reset, and bus clock synchronous
operation halts. FPLLRST is cleared to 0 after PLL operation stabilizes.
Bit 1
FPLLRST
Description
0
Function DPLL is placed in operational state
1
Function DPLL is placed in reset state
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REJ09B0303-0300
(Initial value)
Section 7 Universal Serial Bus Interface (USB)
Bit 0—Function Block Internal State Reset (FSRST): Resets the internal state of the USB
function block.
When FSRST is set to 1, the internal state of the USB function block, excluding the internal bus
clock circuit (DPLL), is initialized. FSRST is cleared to 0 after DPLL operation stabilizes.
The state in which FSRST = 1 and UIFRST = 1 is called a function soft reset.
Bit 0
FSRST
Description
0
Internal state of USB function block is set to operational state
1
Internal state of USB function block is set to reset state (excluding DPLL)
(Initial value)
7.2.19
USB PLL Control Register (UPLLCR)
Bit
7
6
5
—
—
—
4
3
2
1
Initial value
0
0
0
0
0
0
0
1
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
CKSEL2 CKSEL1 CKSEL0 PFSEL1
0
PFSEL0
UPLLCR contains bits that control the method of generating the USB function and USB hub
operating clock.
UPLLCR is initialized to H'01 by a system reset [in an H8/3567U and H8/3564U reset (by RES
input or the watchdog timer), and in hardware standby mode]. It is not initialized in software
standby mode.
Bits 4 to 2—Clock Source Select 2 to 0 (CKSEL2 to CKSEL0): These bits select the source of
the clock supplied to the USB operating clock generator (PLL).
CKSEL0 selects either the USB clock pulse generator (XTAL12) or the system clock pulse
generator (XTATL) as as the clock source. When selected as a clock source, the USB clock pulse
generator starts operating. It operates with CKSEL2=1, CKSEL0=1.
When CKSEL2 = 1 and CKSEL1 = 1, the PLL operates.
When CKSEL1 is cleared to 0, a clock is not input to the PLL, and PLL operation halts. The 48
MHz signal from the USB clock pulse generator can be input directly as the USB operating clock.
Rev. 3.00 Mar 17, 2006 page 139 of 706
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Section 7 Universal Serial Bus Interface (USB)
When CKSEL2 is cleared to 0, a clock is not input to the PLL, and PLL operation halts.
Bit 4
Bit 3
Bit 2
CKSEL2
CKSEL1
CKSEL0
0
1
Description
0
0
PLL operation halted, clock input halted
—
—
PLL operation halted, clock input halted
0
0
Setting prohibited
1
PLL operation halted
(Initial value)
USB clock pulse generator (XTAL12: 48 MHz) used
directly instead of PLL output
1
0
PLL operates with system clock pulse generator (XTAL)
as clock source
1
PLL operates with USB clock pulse generator (XTAL12)
as clock source
Bits 1 and 0—PLL Frequency Select 1 and 0 (PFSEL1, PFSEL0): These bits select the
frequency of the clock supplied to the USB operating clock pulse generator (PLL).
The PLL generates the 48 MHz USB operating clock using the frequency selected with these bits
as the clock source frequency.
Bit 1
Bit 0
PFSEL1
PFSEL0
Description
0
0
PLL input clock is 8 MHz
1
PLL input clock is 12 MHz
0
PLL input clock is 16 MHz
1
PLL input clock is 20 MHz
1
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REJ09B0303-0300
(Initial value)
Section 7 Universal Serial Bus Interface (USB)
7.2.20
USB Port Control Register (UPRTCR)
Bit
7
6
5
4
3
2
1
0
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
DSPSEL2 DSPSEL1 DSPSEL0 PCNMD2 PCNMD1 PCNMD0
UPRTCR is a test register. Its initial settings should not be changed.
UPRTCR is initialized to H'00 by a system reset (reset of this LSI by a RES input or by the
watchdog timer, and in hardware standby mode). It is not initialized in software standby mode.
Bits 5 to 3—Downstream Port Select 2 to 0 (DSPSEL2 to DSPSEL0): These bits select the
downstream port to be tested.
Bit 5
Bit 4
Bit 3
DSPSEL2
DSPSEL1
DSPSEL0
Description
0
0
0
Downstream port 2 selected
1
Downstream port 3 selected
1
0
Downstream port 4 selected
1
Downstream port 5 selected
—
Downstream port 1 selected
1
—
(Initial value)
Bits 2 to 0—Port Connection Mode Select 2 to 0 (PCNMD2 to PCNMD0): These bits set ports
C and D to the normal operating mode or a test operating mode. The PCNMD bits must be set to
B'000.
Bit 2
Bit 1
Bit 0
PCNMD2
PCNMD1
PCNMD0
Description
0
0
0
User mode
1
Digital upstream mode
1
0
Digital downstream mode
1
Digital upstream/downstream mode
0
Upstream transceiver/receiver monitor mode
1
Downstream transceiver/receiver monitor mode
—
Reserved
1
0
1
(Initial value)
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Section 7 Universal Serial Bus Interface (USB)
7.2.21
USB Test Registers 2, 1, 0 (UTESTR2, UTESTR1, UTESTR0)
UTESTR2, UTESTR1, and UTESTR0 are test registers. Their initial settings should not be
changed.
UTESTR1 and UTESTR0 are initialized to H'00 by a system reset [in an H8/3567U or H8/3564U
reset (by RES input or the watchdog timer), and in standby mode]. They are not initialized in
software standby mode.
UTESTR2 is initialized to H'FF by a system reset [in an H8/3567U or H8/3564U reset (by RES
input or the watchdog timer), and in standby mode]. It is not initialized in software standby mode.
UTESTR0
Bit
7
6
5
4
3
2
1
0
TEST15
TEST14
TEST13
TEST12
TEST11
TEST10
TEST9
TEST8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
UTESTR1
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UTESTR2
Bit
7
6
5
4
3
2
1
0
TESTA
TESTB
TESTC
TESTD
TESTE
TESTF
TESTG
TESTH
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 7 Universal Serial Bus Interface (USB)
7.2.22
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
When the MSTP1 bit is set to 1, the USB module stops operating and enters module stop mode at
the end of the bus cycle. However, when USB clocks (XTAL12, EXTAL12) are selected as USB
operating clocks, the USB module does not stop operating. For details, see section 21.5, Module
Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 1—Module Stop (MSTP1): Specifies module stop mode for the USB module.
MSTPCRL
Bit 1
MSTP1
Description
0
USB module stop mode cleared
1
USB module stop mode set
7.2.23
(Initial value)
Serial Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
—
IICX1
IICX0
IICE
—
USBE
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode,
selects the TCNT input clock and controls USB. For details of functions other than register access
control, see the descriptions of the relevant modules. If a module controlled by STCR is not used,
do not write 1 to the corresponding bit.
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Section 7 Universal Serial Bus Interface (USB)
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: Do not write 1 to this bit.
2
2
Bits 6 and 5—I C Control (IICX1, IICX0): These bits control the operation of the I C bus
2
interface. For details, see section 16, I C Bus Interface.
2
2
Bit 4—I C Master Enable (IICE): Controls CPU access to the I C bus interface data registers
and control registers (ICCR, ICSR, ICDR/SARX, and ICMR/SAR), the PWMX data registers and
control registers (DADRAH/DACR, DADRAL, DADRBH/DACNTH, and DADRBL/DACNTL),
and the SCI control registers (SMR, BRR, and SCMR).
Bit 4
IICE
Description
0
Addresses H'FFD8 and H'FFD9, and H'FFDE and H'FFDF, are used for SCI0 control
register access
(Initial value)
1
Addresses H'FF88 and H'FF89, and H'FF8E and H'FF8F, are used for IIC1 data
register and control register access
Addresses H'FFA0 and H'FFA1, and H'FFA6 and H'FFA7, are used for PWMX data
register and control register access
Addresses H'FFD8 and H'FFD9, and H'FFDE and H'FFDF, are used for IIC0 data
register and control register access
Bit 3—Reserved: Do not write 1 to this bit.
Bit 2—USB enable (USBE): This bit controls CPU access to the USB data register and control
register.
Bit 2
USBE
Description
0
Prohibition of the above register access
1
Permission of the above register access
(Initial value)
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12, 8-Bit
Timers.
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Section 7 Universal Serial Bus Interface (USB)
7.3
Operation
USB is an interface for peripherals of the personal computers standardized by Intel and others and
the standard is defined by the USB Specification. Operation of the USB hubs and USB function in
this model is based on the definitions of the USB Specification. This section gives only a brief
overview of the USB bus specifications, and focuses on operations by the slave CPU.
7.3.1
USB Compound Device Configuration
A USB compound device is a USB device incorporating USB hubs and a USB function. The
H8/3567U and H8/3564U incorporate a compound device with a configuration in which the USB
function is internally connected to one downstream port of a USB hub with five downstream ports.
With a USB compound device, it is usual for the USB function to be constantly connected to the
USB hub. With the H8/3567U and H8/3564U, however, the internally connected USB function is
not constantly connected to the USB hub. After release from an H8 reset, the USB function can be
connected or disconnected under program control. Therefore, the device is not identified as a
compound device in the hub descriptor wHub Characteristics.
There are two power feed modes for a USB device: bus feed and self-feed. The H8/3567 Group
use the self-feed method.
With the H8/3567U and H8/3564U a setting can be made to disconnect the USB function block
and operate the USB hub block alone. In this case, it is possible to place the slave CPU in software
standby mode, and operate it in power-down mode.
7.3.2
Functions of USB Hub Block
The USB hub block implements the functions described in section 11 of the USB Specification.
There are five downstream ports; downstream port 1 can be connected to the USB function block
internally, while downstream ports 2 to 5 are connected to external pins. Downstream ports 2 to 5
have their respective overcurrent detection pins (OCP2 to OCP5) and power supply output enable
pins (ENP2 to ENP5), making it is possible to control enabling/disabling of the power supply
control IC connected to the VBUS, and report overcurrent detection to the host, on an individual
port basis.
As exchanges with the USB host are all executed automatically within the USB hub, USB hub
block exchanges with the slave CPU are limited to the following cases:
Rev. 3.00 Mar 17, 2006 page 145 of 706
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Section 7 Universal Serial Bus Interface (USB)
1. USB module reset or operation halt
a. Slave CPU system reset
(Internal reset by RES or STBY input, or WDT0)
b. Module stop condition initiated by slave CPU
(USB module stopped by means of MSTPCR)
c. USB module reset by means of HPLLRST or HSRST bit in USBCR
2. Downstream port overcurrent detection and power supply output enable control
a. Overcurrent detection and power supply output enable for individual ports by bits HOC5E
to HOC2E in HOCCR.
(When a downstream port itself is not used, DSD+/DSD- pins require pullup/pulldown as
specified.)
7.3.3
Functions of USB Function
The USB function block has three endpoints.
By using a combination of endpoint 2 enabling/disabling and IN/OUT mode with endpoint 1
MaxPacketSize, the three alternates shown below can be selected for the USB function block.
Twice the MaxPacketSize value is set for the number of FIFO bytes.
As the command that selects the alternate is a USB standard command, it is not possible to notify
the slave CPU of the alternate selected. It is therefore necessary to ensure that the selected
alternate is the same for the H8 firmware and the host CPU device driver.
Endpoint 0
Endpoint 1
Endpoint 2
Configuration Interface Alternate IN/OUT FIFO
IN/OUT FIFO
IN/OUT FIFO
1
0
0
IN/OUT 16 bytes
each
IN
16 bytes
IN
16 bytes
1
IN/OUT 16 bytes
each
IN
16 bytes
OUT
16 bytes
2
IN/OUT 16 bytes
each
IN
32 bytes
None
None
The USB function supports control transfer by means of endpoint 0 and input transfer by means of
endpoints 1 and 2.
A control transfer consists of a number of transactions. The command transmitted from the host in
the SETUP transaction is first decoded by the USB function core.
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Section 7 Universal Serial Bus Interface (USB)
When a SETUP token is received, FVSR is initialized and EP0OTC is set to 1, and command
reception is enabled. If the received command is a USB standard command (other than
GetDescriptor or SetDescriptor), the EP0OTF flag is set and the slave CPU is notified of the fact
that a USB standard command has been received. In this case, the remaining transactions in the
control transfer are processed within the USB function without intervention by the slave CPU.
If the received command is a GetDescriptor or SetDescriptor command, or a command specific to
a device class, the EP0OTS flag is set. The slave CPU must read the command from the FIFO,
then decode and execute it. The remaining transactions in the control transfer must also be
processed by the slave CPU using the FIFO, etc.
Input transfers consist of individual IN or OUT transactions. These must all be processed by the
slave CPU using the FIFO, etc.
When processing by the slave CPU is necessary as described above, the communication
processing load is shared between the USB function and the slave CPU. The roles of the USB
function and the slave CPU, and the flag and bits used in the interface, are shown in table 7.3.
Table 7.3
Role Sharing between USB Function and Slave CPU
Item/Description
1
D+/D– signal analog ↔ digital conversion
Operating
Hardware
Related Registers/
Flags/Bits
Port block
—
USB function core
2
Serial ↔ parallel conversion/bit stuffing
USB function core
SOFF
SETUPF
PID determination/addition, CRC
determination/addition
3
Token packet determination/notifying slave CPU of
SETUP
USB function core
4
Handshake packet determination/generation
USB function core
DAT0/1 PID toggling, FIFO rewinding,
ACK/NAK detection/return
FVSR, EPTE
ACK handshake detection and slave CPU
notification/ACK handshake return
TS, EPTS
Data error detection and slave CPU
notification/NAK handshake return
TF, EPTF
STALL handshake return
EPSTL
5
Data packet reception/regeneration/transfer to slave
CPU
USB function core
FIFO
6
USB command decoding and execution
USB function core
FIFO
Slave CPU
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Section 7 Universal Serial Bus Interface (USB)
Processing of electrical signals on the USB bus line and processing of signal bit streams is
performed by the bus driver/receiver in the port block and the USB function core block. The
token/acknowledgment type and data bytes are extracted and, conversely, acknowledgment and
data bytes are converted to bit stream electrical signals (items 1 and 2).
When a SETUP token is received, if a GetDescriptor or SetDescriptor command, or a command
specific to a device class, is received, the EP0OTS flag is set and the slave CPU is notified (item
3). The command itself is transferred using the FIFO, and must be decoded and executed by the
slave CPU (item 6). The remaining transactions in the control transfer must also be processed by
the slave CPU using the FIFO, etc. (items 4 and 5).
Reception of an IN or OUT token in control transfer or interrupt transfer is not reported to the
CPU, and the operation continues with data transfer. In the case of an IN transaction, the transmit
data is prepared in the FIFO beforehand, and if the EPTE bit is set transmission is started, or if
not, a NAK handshake is performed. When an IN transaction ends, normal or abnormal
termination of the transfer is confirmed by means of the host handshake, and is reported to the
slave CPU by means of TS/TF/EPTS/EPTF. In the case of an OUT transaction, an ACK
handshake is performed when all the data has been received in the FIFO, or a NAK handshake if it
was not possible to receive all the data. With both IN transactions and OUT transactions, a STALL
handshake is performed if the endpoint is placed in the stall state by means of EPSTL.
7.3.4
Operation when SETUP Token Is Received (Endpoint 0)
The group of transactions initiated when the host issues a SETUP token is called a control transfer.
A control transfer consists of three stages: setup, data, and status. Control transfers are of two
kinds: control write transfers and control read transfers. The type of transfer (read or write) and the
number of transfer bytes in the data stage are determined by the 8-byte command transferred OUT
in the setup stage.
The setup stage consists of a setup transaction, the data stage may have no transaction or one or
more data transactions, and the status stage consists of a single data transaction. The packets
contained in each transaction are shown in the table 7.4.
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Section 7 Universal Serial Bus Interface (USB)
Table 7.4
Packets in Each Transaction
Stage
Token Phase
Data Phase
Handshake Phase*
Setup stage
SETUP token
packet
OUT data packet
(8 bytes)
(host → slave)
ACK
handshake packet
(slave → host)
Data stage
OUT token packet
OUT data packet
(host → slave)
ACK/NAK/STALL
handshake packet
(slave → host)
Status stage
IN token packet
IN data packet
2
(0 bytes)*
(slave → host)
ACK
handshake packet
(host → slave)
NAK/STALL
handshake packet
(slave → host)
—
IN data packet
(slave → host)
ACK
handshake packet
(host → slave)
NAK/STALL
handshake packet
(slave → host)
—
OUT token packet
OUT data packet
(host → slave)
ACK/NAK/STALL
handshake packet
(slave → host)
IN token packet
IN data packet
2
(0 bytes)*
(slave → host)
ACK
handshake packet
(host → slave)
NAK/STALL
handshake packet
(slave → host)
—
Control write
transfer
Control read
transfer
Data stage
Status stage
No data stage Status stage
IN token packet
1
Notes: 1. This phase is present only if a data packet transfer was executed in the data phase.
2. When all the data in the FIFO has been transferred and the FIFO is empty, the EPTE
bit is cleared to 0. If an IN transaction is then started, a NAK handshake is returned.
A 0-byte data packet is transferred by setting the EPTE bit to 1 when the FIFO is empty.
Figure 7.2 shows the operation of the USB function core and the H8 firmware when the USB
function receives a SETUP token (setup transaction). For other cases, see section 7.3.5, Operation
when OUT Token Is Received, and section 7.3.6, Operation when IN Token Is Received.
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
SETUP token packet
output
SETUP token packet
reception
OUT data packet
(8 bytes) output
ACK handshake
packet reception
OUT data packet
(8 bytes) reception
Core interface
Slave CPU
Automatic setting
of various flags*1
USBIA (SETUP)
interrupt request
Start of USBIA
interrupt handling
Data write to EP0O
FIFO
Read USBIFR*2
Command data
decoding
Determination of
necessity of
decoding by slave
CPU
Record in user
memory etc. that
this is state in
which decoding is
performed by
EP0OTS interrupt
occurring next
ACK transmission
to host
Clear SETUPF bit
to 0 in USBIFR
NAK transmission
to slave CPU
FVSR0O not
updated
End of USBIA
interrupt handling
USBID (EP0OTF)
interrupt request
Start of USBID
interrupt handling
Read USBIFR
Confirm TF interrupt
Read TFFR
Confirm EP0OTF
interrupt
Confirm that command decoding by
slave CPU is not
necessary, and
amend record in
user memory, etc.
Clear EP0OTF bit
to 0 in TFFR
End of USBID
interrupt handling
Notes: 1. Bit EP0OTC set to 1 in USBCSR0, FVSR0I and FVSR0O initialized, bits EP0ITS and EP0OTS cleared to 0 in
TSFR, bits EP0ITF and EP0OTF cleared to 0 in TFFR, bit EP0STL cleared to 0 in EPSTLR.
2. As the USBIA interrupt is assigned only to the SETUP interrupt, there is no need for processing to determine the
interrupt source.
Figure 7.2 (1) Operation when SETUP Token Is Received
(Decoding by Slave CPU Not Required)
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
Core interface
SETUP token packet
output
SETUP token packet
reception
Automatic setting of
various flags*1
OUT data packet
(8 bytes) output
ACK handshake
packet reception
OUT data packet
(8 bytes) reception
Slave CPU
USBIA (SETUP)
interrupt request
Start of USBIA
interrupt handling
Data write to EP0O
FIFO
Read USBIFR*2
Command data
decoding
Determination of
necessity of
decoding by slave
CPU
Record in user
memory etc. that
this is state in which
decoding is
performed by
EP0OTS interrupt
occurring next
ACK transmission to
host
Clear SETUPF bit to
0 in USBIFR
ACK transmission to
slave CPU
Update FVSR0O
End of USBIA
interrupt handling
Clear EP0OTC bit to
0 in USBCSR0
USBID (EP0OTS)
interrupt request
Start of USBID
interrupt handling
Read USBIFR
Confirm TS interrupt
Read TSFR
Confirm EP0OTS
interrupt
Decode execution
determined from
record status in user
memory, etc.
Continued on next page
Notes: 1. Bit EP0OTC set to 1 in USBCSR0, FVSR0I and FVSR0O initialized, bits EP0ITS and EP0OTS cleared to 0 in
TSFR, bits EP0ITF and EP0OTF cleared to 0 in TFFR, bit EP0STL cleared to 0 in EPSTLR.
2. As the USBIA interrupt is assigned only to the SETUP interrupt, there is no need for processing to determine the
interrupt source.
Figure 7.2 (2) Operation when SETUP Token Is Received
(Decoding by Slave CPU Required)
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
Core interface
Slave CPU
Continued from previous page
Read FVSR0O
Confirm presence of
8 bytes of data in
EP0O FIFO
Update FVSR0O
Read 8 bytes of data
in EP0O FIFO from
EPDR0O
Determine instruction
by data decoding
If instruction is
Control-OUT, set
EP0OTC bit to 1 in
USBCSR0 (write 1
after reading 0)
Clear EP0OTS bit to
0 in TSFR
End of USBID
interrupt handling
Figure 7.2 (2) Operation when SETUP Token Is Received
(Decoding by Slave CPU Required) (cont)
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Section 7 Universal Serial Bus Interface (USB)
7.3.5
Operation when OUT Token Is Received (Endpoints 0 and 2)
Figure 7.3 shows the operation of the USB function core and the H8 firmware when the USB
function receives an OUT token (OUT transaction). OUT transactions are used in the data stage
and status stage of a control transfer, and in an input transfer.
USB host
USB function core
OUT token packet
output
OUT token packet
reception
OUT data packet
(8 bytes) output
OUT data packet
(8 bytes) reception
ACK handshake
packet reception
ACK transmission to
host
ACK transmission to
slave CPU
Core interface
Slave CPU
Data write to EP2
FIFO
Update FVSR2
USBID (EP2TS)
interrupt request*
Start of USBID
interrupt handling
Read USBIFR
Confirm TS interrupt
Read TSFR
Confirm EP2TS
interrupt
Read FVSR2
Confirm amount of
readable data
(8 bytes)
Update FVSR2
Read data (8 bytes)
in EP2 FIFO from
EPDR2
Clear EP2TS bit to 0
in TSFR
End of USBID
interrupt handling
Note: * When the EP2TS interrupt is set for USBIB or USBIC by the INTSELR0 setting, that interrupt request is generated.
When an USBIB or USBIC interrupt is generated, there is no need for processing to determine the interrupt source.
(A register read is necessary in order to write 0 after reading 1.)
Figure 7.3 (1) Operation when OUT Token Is Received (EP2-OUT: Initial FIFO Empty)
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
OUT token packet
output
OUT token packet
reception
OUT data packet
(8 bytes) output
OUT data packet
(8 bytes) reception
NAK handshake
packet reception
NAK transmission
to host
NAK transmission
to slave CPU
Core interface
Slave CPU
Data write not
possible because
EP2 FIFO is full
USBID (EP2TF)
interrupt request*1
Start of USBID
interrupt handling
Read USBIFR
Confirm TF interrupt
Read TFFR
Confirm EP2TF
interrupt
Read FVSR2
Confirm amount of
readable data
(16 bytes)
Retransmission
OUT token packet
output
OUT token packet
reception
Update FVSR2
Read data (16 bytes)
in EP2 FIFO from
EPDR2
OUT data packet
(8 bytes) output
OUT data packet
(8 bytes) reception
Data write to EP2
FIFO
Clear EP2TF bit to
0 in TFFR
ACK handshake
packet reception
ACK transmission
to host
ACK transmission
to slave CPU
End of USBID
interrupt handling
Update FVSR2
Continued on next page
Note: 1. When the EP2TF interrupt is set for USBIB or USBIC by the INTSELR0 setting, that interrupt request is generated.
When an USBIB or USBIC interrupt is generated, there is no need for processing to determine the interrupt source.
(A register read is necessary in order to write 0 after reading 1.)
Figure 7.3 (2) Operation when OUT Token Is Received (EP2-OUT: Initial FIFO Full)
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
Core interface
Slave CPU
Continued from previous page
USBID (EP2TS)
interrupt request*2
Start of USBID
interrupt handling
Read USBIFR
Confirm TS interrupt
Read TSFR
Confirm EP2TS
interrupt
Read FVSR2
Confirm amount of
readable data
(8 bytes)
Update FVSR2
Read data (8 bytes)
in EP2 FIFO from
EPDR2
Clear EP2TS bit
to 0 in TSFR
End of USBID
interrupt handling
Note: 2. When the EP2TS interrupt is set for USBIB or USBIC by the INTSELR0 setting, that interrupt request is generated.
When an USBIB or USBIC interrupt is generated, there is no need for processing to determine the interrupt source.
(A register read is necessary in order to write 0 after reading 1.)
Figure 7.3 (2) Operation when OUT Token Is Received
(EP2-OUT: Initial FIFO Full) (cont)
7.3.6
Operation when IN Token Is Received (Endpoints 0, 1, and 2)
Figure 7.4 shows the operation of the USB function core and the H8 firmware when the USB
function receives an IN token (IN transaction). IN transactions are used in the data stage and status
stage of a control transfer, and in an input transfer.
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
IN token packet
output
IN token packet
reception
NAK handshake
packet reception
NAK transmission
to host
NAK transmission
to slave CPU
Core interface
Slave CPU
Data read not
possible because
EP2 FIFO is empty
USBID (EP2TF)
interrupt request*1
Start of USBID
interrupt handling
Read USBIFR
Confirm TF interrupt
Read TFFR
Confirm EP2TF
interrupt
Read FVSR2
Confirm amount of
data writable
(16 bytes)
Data write to EP2
FIFO
Write amount of
data writable in
EP2 FIFO into
EPDR2
Update FVSR2
Data transmission
enabled
Set EP2TE bit to 1
in PTTER
Retransmission
IN token packet
output
IN token packet
reception
IN data packet
reception
IN data packet
transmission
ACK handshake
packet transmission
ACK reception
ACK transmission
to slave CPU
Data read from EP2
FIFO
Clear EP2TF bit to
0 in TFFR
End of USBID
interrupt handling
Update FVSR2
Continued on next page
Note: 1. When the EP2TF interrupt is set for USBIB or USBIC by the INTSELR0 setting, that interrupt request is generated.
When an USBIB or USBIC interrupt is generated, there is no need for processing to determine the interrupt source.
(A register read is necessary in order to write 0 after reading 1.)
Figure 7.4 (1) Operation when IN Token Is Received (EP2-IN: Initial FIFO Empty)
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
Core interface
Slave CPU
Continued from previous page
USBID (EP2TS)
interrupt request*2
Start of USBID
interrupt handling
Read USBIFR
Confirm TS interrupt
Read TSFR
Confirm EP2TS
interrupt
Read FVSR2
Confirm amount of
data writable
Data write to EP2
FIFO
Update FVSR2
Data transmission
enabled
Write amount of
data writable in EP2
FIFO into EPDR2
Set EP2TE bit to 1
in PTTER
Clear EP2TSF bit
to 0 in TSFR
End of USBID
interrupt handling
Note: 2. When the EP2TS interrupt is set for USBIB or USBIC by the INTSELR0 setting, that interrupt request is generated.
When an USBIB or USBIC interrupt is generated, there is no need for processing to determine the interrupt source.
(A register read is necessary in order to write 0 after reading 1.)
Figure 7.4 (1) Operation when IN Token Is Received (EP2-IN: Initial FIFO Empty) (cont)
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Section 7 Universal Serial Bus Interface (USB)
USB host
USB function core
IN token packet
output
IN token packet
reception
IN data packet
(8 bytes) reception
IN data packet
(8 bytes)
transmission
ACK handshake
packet transmission
Core interface
Slave CPU
Data read from EP2
FIFO
ACK reception
ACK transmission
to slave CPU
Update FVSR2
USBID (EP2TS)
interrupt request*
Start of USBID
interrupt handling
Read USBIFR
Confirm TS interrupt
Read TSFR
Confirm EP2TS
interrupt
Read FVSR2
Confirm amount of
data writable
(8 bytes)
Data write to EP2
FIFO
Write amount of
data writable in EP2
FIFO into EPDR2
Update FVSR2
Data transmission
enabled
Set EP2TE bit to 1
in PTTER
Clear EP2TS bit to
0 in TSFR
End of USBID
interrupt handling
Note: * When the EP2TS interrupt is set for USBIB or USBIC by the INTSELR0 setting, that interrupt request is generated.
When an USBIB or USBIC interrupt is generated, there is no need for processing to determine the interrupt source.
(A register read is necessary in order to write 0 after reading 1.)
Figure 7.4 (2) Operation when IN Token Is Received (EP2-IN: Initial FIFO Full)
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Section 7 Universal Serial Bus Interface (USB)
7.3.7
Suspend/Resume Operations
If the USB data line is idle for a period longer than that stipulated in the USB Specification, the
H8/3567 Group’s USB hubs and USB function automatically enter the suspend state.
The suspend state is automatically cleared (i.e. operation is resumed) when the upstream side
(host) restarts data transmission, but operation can also be forcibly resumed by the USB function
(remote wakeup).
Changes in the suspend/resume state can be ascertained by means of the SPNDIF and SPNDOF
flags. Remote wakeup is executed by setting the DVR bit.
7.3.8
USB Module Reset and Operation-Halted States
A reset or operation-halted state can be set for the USB module by means of a number of control
bits. For information on sequential setting of these bits when starting up the USB module, see
section 7.3.9, USB Module Startup Sequence.
There are several kinds of USB module reset and operation-halted state, as listed below. In the
hardware standby and reset, the entire USB module is initialized. In the descriptions of individual
bits in the register descriptions, this initialization condition is not indicated, and only “(Initial
value)” is shown.
1. Hardware standby state
2. Reset state
3. Module stop state
4. Software standby state
5. USB function stop state
6. USB function only state
7. USB bus reset state
8. USB suspend state
Hardware Standby State: When the H8/3567 Group’s STBY pin is driven low, the chip enters
the hardware standby state. In the hardware standby state, all the H8/3567 Group’s initializable
registers and internal states are initialized, and all H8/3567 Group pins go to the high-impedance
state. XTAL-EXTAL system clock oscillation and XTAL12-EXTAL12 USB clock oscillation
both halt.
Reset State: When the H8/3567 Group’s RES pin is driven low, the chip enters the reset state. In
the reset state, all the H8/3567 Group’s initializable registers and internal states are initialized, and
all H8/3567 Group pins go to the input state. XTAL-EXTAL system clock oscillation is enabled.
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Section 7 Universal Serial Bus Interface (USB)
Module Stop State: When bit 1 of MSTPCR is set to 1, the USB module enters the module stop
state. In the module stop state, supply of system clock to the USB module is stopped. However,
when USB clocks (XTAL12, EXTAL12) are selected as USB operating clocks, the USB module
does not stop the operation. When setting the USB module stop state, return the value of UPLLCR
to the initial state. Also, it is recommended to return the value of USBCR to the initial state to
prepare for cancellation of the module stop state. As bit 1 of MSTPCR is initialized to 1 by a
transition to hardware standby mode or a reset, the USB module is in the module stop state after
reset release.
Software Standby State: When a SLEEP instruction is executed after setting the SSBY bit to 1 in
SBYCR, the chip enters the software standby state. In the software standby state the USB module
does not enter the reset or operation-halted state. However, since the USB function cannot fulfill
its role when the slave CPU halts due to a transition to the software standby state, operation of the
USB function must be halted before the software standby state setting is made. Set the FNCSTP
bit to 1 in USBCR to disconnect the USB function from the bus (see USB Function Stop State
below).
In the software standby state, XTAL-EXTAL system clock oscillation halts. If the system clock
has been set as the USB operating clock by means of the CKSEL bits in UPLLCR, the USB hubs
cannot operate, either, since the clock is halted. If the USB clock (XTAL12-EXTAL12) has been
set as the USB operating clock, the hub block alone can operate.
USB Function Stop State: When the FNCSTP bit is set to 1 in USBCR, the USB function stop
state is entered. In the USB function stop state, the USB function is disconnected from the bus. If
the FONLY bit has been cleared to 0 in USBCR, internal connection between the USB function
and USB hub is also cut. If the FONLY bit has been set to 1, the USB function is connected to the
upstream port USD+/USD– pins. If the FNCSTP bit and FSRST bits are both set to 1, the
USD+/USD– pins go to the high-impedance state.
The USB operating clock supply to the USB function block is halted.
Clearing the USB function stop state requires execution of the USB function block related
sequence described in section 7.3.9, USB Module Startup Sequence. When setting the USB
function stop state, it is recommended that the UIFRST, FPLLRST, and FSRST bits be set to 1 in
USBCR in preparation for reduced current dissipation and release. As a result, the following
registers are initialized.
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Section 7 Universal Serial Bus Interface (USB)
Registers
UIFRST/FSRS
EPDR2, EPDR1, EPDR0O, EPDR0I
FSRST
FVSR2, FVSR1, FVSR0O, FVSR0I
FSRST
EPSZR1
UIFRST
USBIER
UIFRST
USBIFR, TSFR, TFFR
FSRST
USBCSR0
FSRST
EPSTLR
FSRST
EPDIR
UIFRST
INTSELR0, INTSELR1
UIFRST
Notes
Bits 3 to 0 only
USB Function Only State: When the FONLY bit is set to 1 in USBCR, the USB function only
state is entered. In the USB function stop state, the USB function is connected to the upstream
port, and the USB operating clock supply to the USB hub block is halted.
It is recommended that USB hub block operation be halted by setting the HSRST bit to 1. This
will place the downstream ports in the high-impedance state and enable port D, which also has a
downstream port function, to operate as a general I/O port. HOCCR should be initialized to H'00.
USB Bus Reset State: When a new device is connected to the USB bus, or when error recovery is
executed, the USD+/USD– pin signals go to the bus reset state for a given period.
In the USB function, the bus reset interrupt flag is set to 1 when a USB bus reset is detected. A bus
reset initializes the USB hub internal state to the default state. Control registers that select the USB
function internal state and USB function operating state are not initialized by a USB bus reset.
These registers must be initialized by setting the FSRST bit to 1.
Registers initialized by the UIFRST bit are not initialized by a USB bus reset.
USB Suspend State: If the USB bus remains idle for longer than a certain time, the USB hub
block and USB function block enter the suspend state. In the suspend state, some operating clocks
are halted internally and current dissipation is reduced.
When the USB function enters the suspend state, or when the suspend state is cleared by a change
in the USD+/USD– pin signals, the suspend IN interrupt flag or suspend OUT interrupt flag,
respectively, is set to 1.
The remote wakeup from the suspend state can be executed by write 1 to the DVR bit in
DEVRSMR.
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Section 7 Universal Serial Bus Interface (USB)
7.3.9
USB Module Startup Sequence
Component Elements: The USB module has a number of component elements requiring startup
in a fixed sequence by firmware (an H8 program) to ensure normal operation and correct
recognition by the USB host.
The USB components that need to be considered are as follows:
a. USB clock pulse generator (12 MHz), USB operating clock generation PLL (48 MHz)
b. USB bus clock synchronization DPLL (12 MHz)
c. EPINFO—Endpoint configuration information
d. Slave CPU, core interface
e. USB hub core, USB function core
a. USB clock pulse generator (12 MHz), USB operating clock generation PLL (48 MHz)
The USB clock pulse generator is connected to XTAL12-EXTAL12 and generates a 12 MHz
USB clock. The USB operating clock PLL, multiplies the clock input from the USB clock
pulse generator or system clock pulse generator to give a 48 MHz clock. The input clock
frequency must be 8, 12, 16, or 20 MHz.
As USB clock pulse generator oscillation has not started when a system reset is released, an
oscillation stabilization period 10 ms that includes the USB operating clock PLL must be
provided by firmware. Oscillation is started when XTAL12-EXTAL12 is set as the USB clock
source with the CKSEL bits in UPLLCR. The PLL multiplication factor is selected with the
PFSEL bits in UPLLCR. While waiting for oscillation to stabilize 10 ms, the UIFRST,
HPLLRST, HSRST, FPLLRST, and FSRST bits are set to 1 in USBCR, placing the USB bus
clock synchronization DPLL, USB hub core, USB function core, etc., in the reset state.
b. USB bus clock synchronization DPLL (12 MHz)
USB data transfer is performed at a maximum rate of 12 Mbps. The bit data sampling timing
can be controlled by adjusting the phase during reception of the synchronization pattern that
precedes a packet, using the 48 MHz USB operating clock. This mechanism is called the USB
bus clock synchronization DPLL.
A USB bus clock synchronization DPLL operation stabilization period must be provided by
firmware. While waiting for operation to stabilize, the HSRST and FSRST bits are set to 1 in
USBCR, placing the USB hub core, USB function core, etc., in the reset state.
An operation stabilization period of at least ten 48 MHz clock cycles is recommended.
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Section 7 Universal Serial Bus Interface (USB)
c. EPINFO—Endpoint configuration information
The USB function core block can handle both bulk transfer and isochronous transfer, but for
reasons related to the CPU interface specifications and the data transfer capability of the CPU
itself, the H8 handles only control transfer and interrupt transfer processing.
Information comprising settings for the number of endpoints, supported transfer types,
maximum packet byte length, etc. (EPINFO) is written to the USB function block by firmware
each time the USB function is initialized. In the H8/3567U and H8/3564U, three alternates are
provided, and EPINFO is written for all three. However, since firmware has no way of
knowing which alternate the host has selected, the module will not operate normally if the
choice of alternate is changed during operation. The same alternate must be designated in the
host driver software and the slave firmware.
Table 7.5 shows the endpoint configuration information to be written to the USB function
block. Write all 65 one-byte values to EPDR01 in the order A1, A2, .... A5, B1, B2, .... M4,
M5.
Table 7.5
Endpoint Configuration Information
1
2
3
4
5
A
H'00
H'00
H'11
H'00
H'00
B
H'14
H'38
H'10
H'00
H'01
C
H'24
H'38
H'10
H'00
H'02
D
H'14
H'78
H'10
H'00
H'01
E
H'24
H'70
H'10
H'00
H'02
F
H'14
H'B8
H'20
H'00
H'01
G
H'35
H'20
H'10
H'00
H'03
H
H'45
H'20
H'10
H'00
H'04
I
H'55
H'20
H'10
H'00
H'05
J
H'65
H'20
H'10
H'00
H'06
K
H'36
H'20
H'10
H'00
H'03
L
H'46
H'20
H'10
H'00
H'04
M
H'56
H'20
H'10
H'00
H'05
d. Slave CPU, core interface
These are the basic parts that execute firmware. The slave CPU begins operating immediately
after reset release, whereas core interface access is enabled when the module stop state is
cleared.
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Section 7 Universal Serial Bus Interface (USB)
e. USB hub core, USB function core
These are the central parts of the USB interface. Implementation of the USB bus interface is
made possible by normal operation of component elements a to d.
Initial Operation Procedures: The initial operation procedures for the USB hubs and USB
function are shown in figures 7.5 and 7.6.
When the USB module is used as a compound device, these two initial operation procedures must
be executed, first for the USB hubs, then for the USB function. Clear the UIFRST bit to 0 before
executing the USB function block procedure.
The compound device initial operation procedure is summarized below.
1. H8 is in power-off or hardware standby state
2. Power-on, STBY pin high-level application, etc., is performed, and finally high level is applied
to RES pin and H8 starts operating
3. USBE bit in STCR is set to 1 by firmware
4. USB module is released from module stop state by firmware
5. FONLY bit is cleared to 0 by firmware
6. HOCCR and PLLCR are set by firmware; wait for USB operating clock oscillation to stabilize
7. After elapse of 10 ms oscillation stabilization time, HPLLRST bit is cleared to 0 by firmware
8. After DPLL operation stabilization time, HSRST bit is cleared to 0 by firmware
a. USB host (upstream port) performs USB hub block bus reset
b. USB host performs USB hub block configuration
c. → Start of USB hub block operation
9. UIFRST bit is cleared to 0 and USB function related registers are set by firmware
10. FNCSTP bit is cleared to 0 and USB function is connected to USB hub by firmware
11. FPLLRST bit is cleared to 0 by firmware
12. After DPLL operation stabilization time, FSRST bit is cleared to 0 by firmware
13. EPINFO is written to USB function core by firmware, and finally EPIVLD bit is set to 1
14. Wait for bus reset interrupt
a. USB host (USB hub block) performs USB function block bus reset
b. USB host performs USB function block configuration
c. → Start of USB function block operation
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Section 7 Universal Serial Bus Interface (USB)
External event
USB operating
clock PLL
Slave CPU
Core interface
USB function core
USB hub core
Power-on reset
STBY = 0
RESET = 0
Standby
release
STBY = 1
Clock
oscillation
Reset release
RESET = 1
System
operation
Set USBE bit
to 1 in STCR
USB module
stop release
Start of
operation
System clock
oscillation
HOCCR
USBCR
UPLLCR
access OK
Clear FONLY
bit to 0 in
USBCR
Connect
USB hub to
upstream port
HOCCR setting
UPLLCR setting
Downstream
port control
setting
USB operating
clock oscillation
Start of USB
operating clock
supply
Wait for USB
operating clock
oscillation
stabilization
time (10 ms)
Clear HPLLRST
bit to 0 in
USBCR
USBCR
HPLLRST = 0
Start of DPLL
block operation
Wait for DPLL
block operation
stabilization
Clear HSRST
bit to 0 in
USBCR
USBCR
HSRST = 0
Internal state
reset release
Bus reset
by host
Configuration
by host
Start of USB
hub operation
Figure 7.5 USB Hub Initial Operation Procedure
Rev. 3.00 Mar 17, 2006 page 165 of 706
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Section 7 Universal Serial Bus Interface (USB)
External event
USB operating
clock PLL
Slave CPU
Core interface
USB function core
Power-on reset
STBY = 0
RESET = 0
Standby
release
STBY = 1
Clock
oscillation
Reset release
RESET = 1
System
operation
Set USBE bit
to 1 in STCR
Start of
operation
Compound device
USB module
stop release
System clock
oscillation
HOCCR
USBCR
UPLLCR
access OK
UPLLCR
setting
USB operating
clock oscillation
Clear UIFRST
bit to 0 in
USBCR
USB function
related register
access OK
USB function
related register
settings
USB function
operation
setting
Clear FNCSTP
bit to 0 in
USBCR
USB function
connection
Start of USB
operating clock
supply
(Wait for USB
operating clock
oscillation
stabilization
time (10 ms))
Clear FPLLRST
bit to 0 in
USBCR
USBCR
FPLLRST = 0
Start of DPLL
block operation
Wait for DPLL
block operation
stabilization
Clear FSRST
bit to 0 in
USBCR
USBCR
FSRST = 0
Internal state
reset release
Continued on next page
Figure 7.6 USB Function Initial Operation Procedure
Rev. 3.00 Mar 17, 2006 page 166 of 706
REJ09B0303-0300
USB hub core
Section 7 Universal Serial Bus Interface (USB)
External event
USB operating
clock PLL
Slave CPU
Core interface
USB function core
USB hub core
Continued from previous page
EPINFO write
to EPDR0I
EPINFO
transfer to core
EPINFO
recording
Set EPIVLD
bit to 1 in
USBCSR0
End of EPINFO
transfer
End of EPINFO
recording
Bus reset
interrupt
handling
(no action)
Bus reset
interrupt
request
Bus reset
by host
Configuration
by host
Start of USB
function
operation
Figure 7.6 USB Function Initial Operation Procedure (cont)
Disconnection/Reconnection Procedures: The initial operation procedures for USB hub/USB
function disconnection and reconnection are shown in figures 7.7 to 7.10. There are three kinds of
USB function disconnection: compound device hub block upstream disconnection, upstream
disconnection in USB function standalone mode, and compound device function block
disconnection by firmware.
In the case of upstream disconnection, the USB bus continues in the idle state, and so the suspend
state is entered. In order to detect reconnection, some method independent of the USB protocol is
needed, such as detecting VBUS connection by means of an interrupt. Trigger events (such as
cutoff of the system power supply) whereby the USB function block is disconnected by firmware
also require detection by means of a separate interrupt, etc.
When USB hub upstream disconnection occurs in the compound device state, the USB function
block enters the suspend state. When upstream reconnection is detected by means of an external
interrupt, etc., initialization of both the USB hub block and USB function block is performed by
firmware.
Rev. 3.00 Mar 17, 2006 page 167 of 706
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Section 7 Universal Serial Bus Interface (USB)
The compound device upstream port disconnection/reconnection procedure is as follows:
1. Upstream port is disconnected
2. USB hub block and USB function block enter suspend state, and suspend IN interrupt is
generated in USB function block
3. Upstream port is reconnected
4. Upstream port reconnection is detected by means of external interrupt, etc.
5. HSRST and FSRST bits are set to 1 by firmware
6. Step 8 in initial operation procedure is executed
7 onward: Operations from step 12 onward in initial operation procedure are executed
The compound device USB function block disconnection/reconnection procedure is as follows:
1. State requiring disconnection of USB function is detected
2. Bits FNCSTP, FPLLRST, and FSRST are set to 1
If necessary, software standby mode is set
3. Detection of event enabling reconnection of USB function
Software standby mode is exited
4. If necessary, USB function control registers are re-set
5. FNCSTP bit is cleared to 0
6. FPLLRST bit is cleared to 0
7. FSRST bit is cleared to 0
8 onward: Operations from step 13 onward in initial operation procedure are executed
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Section 7 Universal Serial Bus Interface (USB)
External event
USB operating
clock PLL
Slave CPU
Core interface
Upstream port
disconnection
USB hub core
Suspend state
transition
USB operating
clock halted
Upstream port
reconnection
USB function core
USB operating
clock supply
halted
Reconnection
recognized by
means of
external
interrupt
Set HSRST bit
to 1 in USBCR
USBCR
HSRST = 1
USB operating
clock oscillation
Internal state
reset
USB operating
clock supply
started
Suspend state
release
Wait for DPLL
block operation
stabilization
Clear HSRST
bit to 0 in
USBCR
USBCR
HSRST = 0
Internal state
reset release
Bus reset
by host
Configuration
by host
Start of USB
hub operation
Figure 7.7 USB Hub Block Upstream Disconnection/Reconnection
Rev. 3.00 Mar 17, 2006 page 169 of 706
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Section 7 Universal Serial Bus Interface (USB)
External event
USB operating
clock PLL
Slave CPU
Core interface
USB function core
Upstream port
disconnection
Suspend state
transition
USB hub
operating clock
halted
Suspend IN
interrupt
handling
Set CKSTOP
bit to 1 in
USBCSR0
Upstream port
reconnection
USB hub core
USB operating
clock supply
halted
Suspend IN
interrupt
request
Suspend state
transition
USB function
operating clock
halted
USB operating
clock supply
halted
Reconnection
recognized by
means of
external
interrupt
Set HSRST bit
and FSRST bit
to 1 in USBCR
USBCR
HSRST = 1
FSRST = 1
USB operating
clock oscillation
Internal state
reset
USB operating
clock supply
started
Suspend state
release
Wait for DPLL
block operation
stabilization
Clear HSRST
bit to 0 in
USBCR
USBCR
HSRST = 0
Clear FSRST
bit to 0 in
USBCR
USBCR
FSRST = 0
Internal state
reset release
EPINFO write
to EPDR0I
EPINFO
transfer to core
EPINFO
recording
Set EPIVLD bit
to 1 in
USBCSR0
End of EPINFO
transfer
End of EPINFO
recording
Internal state
reset
USB operating
clock supply
started
Suspend state
release
Internal state
reset release
Bus reset
by host
Continued on next page
Figure 7.8 USB Compound Device Upstream Disconnection/Reconnection
Rev. 3.00 Mar 17, 2006 page 170 of 706
REJ09B0303-0300
Section 7 Universal Serial Bus Interface (USB)
External event
USB operating
clock PLL
Slave CPU
Core interface
USB function core
USB hub core
Continued from previous page
Configuration
by host
Start of USB
hub operation
Bus reset
interrupt
handling
(no action)
Bus reset
interrupt
request
Bus reset
by host
USB function
connection
recognized
Configuration
by host
Start of USB
function
operation
Figure 7.8 USB Compound Device Upstream Disconnection/Reconnection (cont)
Rev. 3.00 Mar 17, 2006 page 171 of 706
REJ09B0303-0300
Section 7 Universal Serial Bus Interface (USB)
External event
Upstream port
disconnection
Upstream port
reconnection
USB operating
clock PLL
Slave CPU
Core interface
USB function core
USB hub core
Suspend state
transition
Suspend IN
interrupt
handling
Set CKSTOP
bit to 1 in
USBCSR0
Suspend IN
interrupt
request
USB function
operating clock
halted
USB operating
clock supply
halted
Reconnection
recognized by
means of
external
interrupt
Set FSRST bit
to 1 in USBCR
USBCR
FSRST = 1
USB operating
clock oscillation
Internal state
reset
USB operating
clock supply
started
Suspend state
release
Wait for DPLL
block operation
stabilization
Clear FSRST
bit to 0 in
USBCR
USBCR
FSRST = 0
Internal state
reset release
EPINFO write
to EPDR0I
EPINFO
transfer to core
EPINFO
recording
Set EPIVLD
bit to 1 in
USBCSR0
End of EPINFO
transfer
End of EPINFO
recording
Bus reset
interrupt
handling
(no action)
Bus reset
interrupt
request
Bus reset
by host
Configuration
by host
Start of USB
hub operation
Figure 7.9 USB Function Standalone Mode Upstream Disconnection/Reconnection
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Section 7 Universal Serial Bus Interface (USB)
External event
Trigger event
USB operating
clock PLL
Slave CPU
USB function core
USB hub core
Detection of
state requiring
disconnection
Set bits
FNCSTP,
FPLLRST,
FSRST to 1 in
USBCR
Trigger event
Core interface
USBCR
FNCSTP = 1
FPLLRST = 1
FSRST = 1
USB function
disconnection
DPLL block
operation
halted
Internal state
reset
USB function
disconnection
recognized
Detection of
state enabling
reconnection
If necessary,
re-set USB
function related
registers
USB function
operation
re-setting
Clear FNCSTP
bit to 0 in
USBCR
USB function
connection
USB operating
clock oscillation
USB operating
clock supply
halted
USB function
connection
recognized
Clear FPLLRST
bit to 0 in
USBCR
USBCR
FPLLRST = 0
DPLL block
operation
started
Wait for DPLL
block operation
stabilization
Clear FSRST
bit to 0 in
USBCR
USBCR
FSRST = 0
Internal state
reset release
Continued on next page
Figure 7.10 USB Function Block Disconnection/Reconnection
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Section 7 Universal Serial Bus Interface (USB)
External event
USB operating
clock PLL
Slave CPU
Core interface
USB function core
USB hub core
Continued from previous page
EPINFO write
to EPDR0I
EPINFO
transfer to core
EPINFO
recording
Set EPIVLD
bit to 1 in
USBCSR0
End of EPINFO
transfer
End of EPINFO
recording
Bus reset
interrupt
handling
(no action)
Bus reset
interrupt
request
Bus reset
by host
Configuration
by host
Start of USB
function
operation
Figure 7.10 USB Function Block Disconnection/Reconnection (cont)
Rev. 3.00 Mar 17, 2006 page 174 of 706
REJ09B0303-0300
Section 7 Universal Serial Bus Interface (USB)
7.3.10
USB Module Slave CPU Interrupts
The USB module has four slave CPU interrupt sources: USBIA, USBIB, USBIC and USBID.
Table 7.6 shows the interrupt sources and their priority order. The interrupt sources are the
USBIFR and TSFR/TFFR interrupt flags. For each interrupt, the interrupt flag can be enabled or
disabled by means of the corresponding interrupt enable bit in USBIER. In the USBID interrupt
handling routine, USBIFR and TSFR/TFFR must be read to determine the interrupt source before
processing is carried out.
Table 7.6
USB Interrupt Sources
Interrupt Source
Description
Priority
USBIA
Interrupt initiated by SETUP
High
USBIB
Interrupt initiated by EPTS or EPTF of endpoint
specified by INTSELR0
USBIC
Interrupt initiated by EPTS or EPTF of endpoint
specified by INTSELR0
USBID
Interrupt initiated by SOF, SPND, BRST, TS, or TF
Low
Rev. 3.00 Mar 17, 2006 page 175 of 706
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Section 7 Universal Serial Bus Interface (USB)
Rev. 3.00 Mar 17, 2006 page 176 of 706
REJ09B0303-0300
Section 8 I/O Ports
Section 8 I/O Ports
8.1
Overview
The H8/3577 Group has six input/output ports (ports 1 to 6), and one input-only port (port 7). The
H8/3567 Group has four input/output ports (ports 1, 4, 5, and 6), and one input-only port. H8/3567
Group models with an on-chip USB have additional USB pins plus two input/output ports (ports C
and D) for controlling the USB power supply circuit.
Table 8.1 summarizes the port functions. The pins of each port also have other functions.
Each port includes a data direction register (DDR) that controls input/output (not provided for the
input-only ports), and a data register (DR) that stores output data.
H8/3577 Group ports 1 to 3 have a built-in MOS input pull-up function, and use DDR and a MOS
input pull-up control register (PCR) to control the on/off status of the MOS input pull-ups.
Ports 1 to 6 can drive one TTL load and a 30 pF capacitive load. All the input/output ports can
drive a Darlington transistor pair when in output mode.
The output type of pin P52 in port 5 and pin P47 in port 4 is NMOS push-pull.
Port C has the same load drive capacity as ports 1 to 6.
Port D also has a USB hub downstream input/output function, and operates on the USB power
supply (3.3 V).
Rev. 3.00 Mar 17, 2006 page 177 of 706
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Section 8 I/O Ports
Table 8.1
Port
Port 1
H8/3577 Group and H8/3567 Group Port Functions
Summary
Pins
• 8-bit I/O port
P17/PW7 (/SCL1)
• Built-in MOS input
pull-up (H8/3577
Group only)
P16/PW6 (/SDA1)
P15/PW5 (/CBLANK)
P14/PW4
P13/PW3
P12/PW2
Description
I/O port also functioning as PWM timer
output pins (PW7 to PW0, PWX1, PWX0)
(both H8/3577 and H8/3567 Group)
Additional functions: timer connection
output pin (CBLANK) and I2C bus interface
1 I/O pins (SCL1, SDA1) (H8/3567 Group
only)
P11/PW1/PWX1
P10/PW0/PWX0
Port 2
• 8-bit I/O port
H8/3577 Group:
Present
H8/3567 Group:
Absent
• Built-in MOS input
pull-up (H8/3577
Group only)
P27/PW15/CBLANK
P26/PW14
P25/PW13
I/O port also functioning as PWM timer
output pins (PW15 to PW8), or timer
connection output pin (CBLANK) and I2C
bus interface 1 I/O pins (SCL1, SDA1)
P24/PW12/SCL1
P23/PW11/SDA1
P22/PW10
P21/PW9
P20/PW8
Port 3
• 8-bit I/O port
P37 to P30
I/O port
P47/SDA0
I/O port also functioning as I2C bus
interface 0 I/O pin (SDA0)
P46/φ
When DDR = 0 (after reset): Input port
H8/3577 Group:
Present
H8/3567 Group:
Absent
• Built-in MOS input
pull-up (H8/3577
Group only)
Port 4
• 8-bit I/O port
When DDR = 1: φ output pin
P45 to P43
I/O ports
P42/IRQ0
I/O ports also functioning as external
interrupt input pins (IRQ0, IRQ1)
P41/IRQ1
P40/IRQ2/ADTRG
Rev. 3.00 Mar 17, 2006 page 178 of 706
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I/O port also functioning as external
interrupt input pin (IRQ2) and A/D converter
external trigger input pin (ADTRG)
Section 8 I/O Ports
Port
Port 5
Summary
• 3-bit I/O port
Pins
P52/SCK0/SCL0
P51/RxD0
P50/TxD0
Port 6
• 8-bit I/O port
P67/TMOX/TMO1/HSYNCO
P66/FTOB/TMRI1/CSYNCI
P65/FTID/TMCI1/HSYNCI
P64/FTIC/TMO0/CLAMPO
P63/FTIB/TMRI0/VFBACKI
P62/FTIA/TMIY/VSYNCI
Description
I/O port also functioning as SCI0 I/O pins
(TxD0, RxD0, SCK0) and I2C bus interface 0
I/O pin (SCL0)
I/O port also functioning as FRT I/O pins
(FTCI, FTOA, FTIA, FTIB, FTIC, FTID,
FTOB), 8-bit timer 0 and 1 I/O pins (TMCI0,
TMRI0, TMO0, TMCI1, TMRI1, TMO1), 8-bit
timer X and Y I/O pins (TMOX, TMIX,
TMIY), and timer connection I/O pins
(HSYNCO, CSYNCI, HSYNCI, CLAMPO,
VFBACKI, VSYNCI, VSYNCO, HFBACKI)
P61/FTOA/VSYNCO
P60/FTCI/TMIX/TMCI0/
HFBACKI
Port 7
• 8-bit input port
(H8/3577 Group)
P77 to P74/AN7 to AN4
P73 to P70/AN3 to AN0
I/O port also functioning as A/D converter
analog inputs (AN7 to AN0)
• 4-bit input port
(H8/3567 Group)
Port C
• 8-bit I/O port
(H8/3567 Group
version with on-chip
USB only)
Port D
• 8-bit I/O port
(H8/3567 Group
version with on-chip
USB only)
Power supply:
DrVCC (3.3 V)
PC7 to PC4/OCP5 to OCP2
PC3 to PC0/ENP5 to ENP2
PD7/DS5D–, PD6/DS5D+,
PD5/DS4D–, PD4/DS4D+,
I/O port also functioning as external power
supply circuit overcurrent detection signal
input pins (OCP5 to OCP2) and power
output enable signal output pins (ENP5 to
ENP2)
I/O port also functioning as USB
downstream I/O pins
PD3/DS3D–, PD2/DS3D+,
PD1/DS2D–, PD0/DS2D+
Rev. 3.00 Mar 17, 2006 page 179 of 706
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Section 8 I/O Ports
8.2
Port 1
8.2.1
Overview
Port 1 is an 8-bit I/O port. Port 1 is also used for 8-bit PWM output (PW7 to PW0), 14-bit PWM
output (PWX1, PWX0), timer connection output (CBLANK) [H8/3567 Group only], and IIC1
input/output (SCL1, SDA1) [H8/3567 Group only].
In the H8/3577 Group, port 1 has a built-in MOS input pull-up function that can be controlled by
software.
Figure 8.1 shows the port 1 pin configuration.
P1n: Input pin when P1DDR = 0,
output pin when P1DDR = 1 and PWOERA = 0
P17 (input/output) / SCL1 (H8/3567 Group: input/output)
P16 (input/output) / SDA1 (H8/3567 Group: input/output)
P15 (input/output) / CBLANK (H8/3567 Group: output)
Port 1
P14 (input/output)
P13 (input/output)
P12 (input/output)
P11 (input/output) / PWX1 (output)
P10 (input/output) / PWX0 (output)
When P1DDR = 1 and PWOERA = 1
PW7 (output) / SCL1 (H8/3567 Group: input/output)
PW6 (output) / SDA1 (H8/3567 Group: input/output)
PW5 (output) / CBLANK (H8/3567 Group: output)
PW4 (output)
PW3 (output)
PW2 (output)
PW1 (output) / PWX1 (output)
PW0 (output) / PWX0 (output)
Figure 8.1 Port 1 Pin Functions
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Section 8 I/O Ports
8.2.2
Register Configuration
Table 8.2 shows the port 1 register configuration.
Table 8.2
Port 1 Registers
Name
Abbreviation
R/W
Initial Value
Address
Port 1 data direction register
P1DDR
W
H'00
H'FFB0
Port 1 data register
P1DR
R/W
H'00
H'FFB2
Port 1 MOS pull-up control register*
[H8/3577 Group only]
P1PCR
R/W
H'00
H'FFAC
Note:
*
P1PCR cannot be read or written to in the H8/3567 Group. A read will return an
undefined value.
Port 1 Data Direction Register (P1DDR)
Bit
7
6
5
4
3
2
1
0
P17DDR
P16DDR
P15DDR
P14DDR
P13DDR
P12DDR
P11DDR
P10DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P1DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 1. P1DDR cannot be read; if it is, an undefined value will be returned.
P1DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Setting a P1DDR bit to 1 makes the corresponding port 1 pin an output port or PWM output, while
clearing the bit to 0 makes the pin an input port.
P10 and P11 can be used for PWMX output regardless of the P1DDR settings.
In the H8/3567 Group, P17, P16, and P15 can be used for supporting function output or input/output
regardless of the P1DDR settings.
Rev. 3.00 Mar 17, 2006 page 181 of 706
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Section 8 I/O Ports
Port 1 Data Register (P1DR)
Bit
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). If
a port 1 read is performed while P1DDR bits are set to 1, the P1DR values are read directly
regardless of the actual pin states. If a port 1 read is performed while P1DDR bits are cleared to 0,
the pin states are read.
P1DR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
software standby mode.
Port 1 MOS Pull-Up Control Register (P1PCR)
Bit
7
6
5
4
3
2
1
0
P17PCR
P16PCR
P15PCR
P14PCR
P13PCR
P12PCR
P11PCR
P10PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1PCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port 1 on a bit-by-bit basis.
When a P1DDR bit is cleared to 0 (input port setting), setting the corresponding P1PCR bit to 1
turns on the MOS input pull-up for that pin.
P1PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
8.2.3
Pin Functions
Port 1 is used for PWM output or as an I/O port, with input or output specifiable individually for
each pin. Setting a P1DDR bit to 1 makes the corresponding port 1 pin a PWM output or output
port, while clearing the bit to 0 makes the pin an input port. P10 and P11 can be used for PWMX
output regardless of the P1DDR settings.
Rev. 3.00 Mar 17, 2006 page 182 of 706
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Section 8 I/O Ports
In the H8/3567 Group, P17, P16, and P15 also function as IIC1 I/O pins (SCL1, SDA1) and the timer
connection output pin (CBLANK). P17, P16, and P15 can be used for supporting function
input/output regardless of the P1DDR settings.
Port 1 pin functions are shown in table 8.3.
Table 8.3
Port 1 Pin Functions
Pin
Pin Functions and Selection Method
P17/PW7
(/SCL1)
The pin function is selected as shown below by a combination of bit ICE in ICCR
of IIC1 (H8/3567 Group), bit OE7 in PWOERA, and bit P17DDR.
ICE
0
PWOERA: OE7
—
0
1
—
P17 input
P17 output
PW7 output
SCL1 I/O
1
—
The pin function is selected as shown below by a combination of bit ICE in ICCR
of IIC1 (H8/3567 Group), bit OE6 in PWOERA, and bit P16DDR.
ICE
0
1
P16DDR
0
PWOERA: OE6
—
0
1
—
P16 input
P16 output
PW6 output
SDA1 I/O
Pin function
P15/PW5
(/CBLANK)
1
P17DDR
Pin function
P16/PW6
(/SDA1)
0
1
—
The pin function is selected as shown below by a combination of bit CBE in timer
connection TCONR0 (H8/3567 Group), bit OE5 in PWOERA, and bit P15DDR.
CBE
P15DDR
PWOERA: OE5
Pin function
0
0
1
1
—
—
0
1
—
P15 input
P15 output
PW5 output
CBLANK
output
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Section 8 I/O Ports
Pin
P14/PW4
Pin Functions and Selection Method
P14DDR
0
PWOERA: OE4
0
0
1
P14 input
P14 output
PW4 output
Pin function
P13/PW3
P13DDR
0
PWOERA: OE3
0
0
1
P13 input
P13 output
PW3 output
Pin function
P12/PW2
0
PWOERA: OE2
0
0
1
P12 input
P12 output
PW2 output
1
The pin function is selected as shown below by a combination of bit OEB in
DACR of PWMX, bit OE1 in PWOERA, and bit P11DDR.
DACR: OEB
0
P11DDR
0
PWOERA: OE1
Pin function
P10/PW0/
PWX0
1
P12DDR
Pin function
P11/PW1/
PWX1
1
1
1
—
—
0
1
—
P11 input
P11 output
PW1 output
PWX1 output
The pin function is selected as shown below by a combination of bit OEA in
DACR of PWMX, bit OE0 in PWOERA, and bit P10DDR.
DACR: OEA
0
1
P10DDR
0
PWOERA: OE0
—
0
1
—
P10 input
P10 output
PW0 output
PWX0 output
Pin function
Rev. 3.00 Mar 17, 2006 page 184 of 706
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1
—
Section 8 I/O Ports
8.2.4
MOS Input Pull-Up Function
In the H8/3577 Group, port 1 has a built-in MOS input pull-up function that can be controlled by
software.
When a P1DDR bit is cleared to 0, setting the corresponding P1PCR bit to 1 turns on the MOS
input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
previous state is retained in software standby mode.
Table 8.4 summarizes the MOS input pull-up states.
Table 8.4
MOS Input Pull-Up States (Port 1)
Reset
Hardware Standby Mode
Software Standby Mode
In Other Operations
Off
Off
On/Off
On/Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when P1DDR = 0 and P1PCR = 1; otherwise off.
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Section 8 I/O Ports
8.3
Port 2 [H8/3577 Group Only]
8.3.1
Overview
Port 2 is an 8-bit I/O port. Port 2 is also used for 8-bit PWM output (PW15 to PW8), timer
connection output (CBLANK), and IIC1 input/output (SCL1, SDA1).
Port 2 is provided in the H8/3577 Group, but not in the H8/3567 Group. Therefore the H8/3567
Group does not have the port 2 I/O pin functions or eight 8-bit PWM output pin (PW15 to PW8)
functions, and provides the timer connection output pin (CBLANK) function and IIC1 I/O pin
(SCL1, SDA1) functions in port 1.
Port 2 has a built-in MOS input pull-up function that can be controlled by software.
Figure 8.2 shows the port 2 pin configuration.
P2n: Input pin when P2DDR = 0,
output pin when P2DDR = 1 and PWOERB = 0
P27 (input/output) / CBLANK (output)
P26 (input/output)
P25 (input/output)
Port 2
P24 (input/output) / SCL1 (input/output)
P23 (input/output) / SDA1 (input/output)
P22 (input/output)
P21 (input/output)
P20 (input/output)
When P2DDR = 1 and PWOERB = 1
PW15 (output) / CBLANK (output)
PW14 (output)
PW13 (output)
PW12 (output) / SCL1 (input/output)
PW11 (output) / SDA1 (input/output)
PW10 (output)
PW9 (output)
PW8 (output)
Figure 8.2 Port 2 Pin Functions
Rev. 3.00 Mar 17, 2006 page 186 of 706
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Section 8 I/O Ports
8.3.2
Register Configuration
Table 8.5 shows the port 2 register configuration.
Table 8.5
Port 2 Registers
Name
Abbreviation
R/W
Initial Value
Address
Port 2 data direction register
P2DDR
W
H'00
H'FFB1
Port 2 data register
P2DR
R/W
H'00
H'FFB3
Port 2 MOS pull-up control register
P2PCR
R/W
H'00
H'FFAD
Port 2 Data Direction Register (P2DDR)
Bit
7
6
5
4
3
2
1
0
P27DDR
P26DDR
P25DDR
P24DDR
P23DDR
P22DDR
P21DDR
P20DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 2. P2DDR cannot be read; if it is, an undefined value will be returned.
P2DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Setting a P2DDR bit to 1 makes the corresponding port 2 pin an output port or PWM output, while
clearing the bit to 0 makes the pin an input port.
P23, P24, and P27 can be used for supporting function output regardless of the P2DDR settings.
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Section 8 I/O Ports
Port 2 Data Register (P2DR)
Bit
7
6
5
4
3
2
1
0
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). If
a port 2 read is performed while P2DDR bits are set to 1, the P2DR values are read directly
regardless of the actual pin states. If a port 2 read is performed while P2DDR bits are cleared to 0,
the pin states are read.
P2DR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
software standby mode.
Port 2 MOS Pull-Up Control Register (P2PCR)
Bit
7
6
5
4
3
2
1
0
P27PCR
P26PCR
P25PCR
P24PCR
P23PCR
P22PCR
P21PCR
P20PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2PCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port 2 on a bit-by-bit basis.
When a P2DDR bit is cleared to 0 (input port setting), setting the corresponding P2PCR bit to 1
turns on the MOS input pull-up for that pin.
P2PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Rev. 3.00 Mar 17, 2006 page 188 of 706
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Section 8 I/O Ports
8.3.3
Pin Functions
Port 2 is used for PWM output, timer connection output (CBLANK), and IIC1 input/output
(SCL1, SDA1), or as an I/O port, with input or output specifiable individually for each pin. Setting
a P2DDR bit to 1 makes the corresponding port 2 pin a PWM output or output port, while clearing
the bit to 0 makes the pin an input port. P23, P24, and P27 can be used for supporting function
output regardless of the P2DDR settings.
Port 2 pin functions are shown in table 8.6.
Table 8.6
Port 2 Pin Functions
Pin
Pin Functions and Selection Method
P27/PW15/
CBLANK
The pin function is selected as shown below by a combination of bit CBE in timer
connection TCONR0, bit OE15 in PWOERB, and bit P27DDR.
CBE
PWOERB: OE15
—
0
1
—
P27 input
P27 output
PW15 output
CBLANK
output
—
0
PWOERB: OE14
0
0
1
P26 input
P26 output
PW14 output
P25DDR
Pin function
1
0
PWOERB: OE13
P24/PW12/
SCL1
1
P26DDR
Pin function
P25/PW13
1
0
Pin function
P26/PW14
0
P27DDR
1
0
0
1
P25 input
P25 output
PW13 output
The pin function is selected as shown below by a combination of bit ICE in ICCR
of IIC1, bit OE12 in PWOERB, and bit P24DDR.
ICE
0
1
P24DDR
0
PWOERB: OE12
—
0
1
—
P24 input
P24 output
PW12 output
SCL1 I/O
Pin function
1
—
Rev. 3.00 Mar 17, 2006 page 189 of 706
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Section 8 I/O Ports
Pin
Pin Functions and Selection Method
P23/PW11/
SDA1
The pin function is selected as shown below by a combination of bit ICE in ICCR
of IIC1, bit OE11 in PWOERB, and bit P23DDR.
ICE
PWOERB: OE11
—
0
1
—
P23 input
P23 output
PW11 output
SDA1 I/O
—
0
PWOERB: OE10
0
0
1
P22 input
P22 output
PW10 output
1
P21DDR
0
PWOERB: OE9
0
0
1
P21 input
P21 output
PW9 output
Pin function
P20/PW8
1
P22DDR
Pin function
P21/PW9
1
0
Pin function
P22/PW10
0
P23DDR
P20DDR
PWOERB: OE8
Pin function
Rev. 3.00 Mar 17, 2006 page 190 of 706
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1
0
1
0
0
1
P20 input
P20 output
PW8 output
Section 8 I/O Ports
8.3.4
MOS Input Pull-Up Function
Port 2 has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off for individual bits.
When a P2DDR bit is cleared to 0, setting the corresponding P2PCR bit to 1 turns on the MOS
input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
previous state is retained in software standby mode.
Table 8.7 summarizes the MOS input pull-up states.
Table 8.7
MOS Input Pull-Up States (Port 2)
Reset
Hardware Standby Mode
Software Standby Mode
In Other Operations
Off
Off
On/Off
On/Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when P2DDR = 0 and P2PCR = 1; otherwise off.
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Section 8 I/O Ports
8.4
Port 3 [H8/3577 Group Only]
8.4.1
Overview
Port 3 is an 8-bit I/O port.
Port 3 is provided in the H8/3577 Group, but not in the H8/3567 Group.
Port 3 has a built-in MOS input pull-up function that can be controlled by software.
Figure 8.3 shows the port 3 pin configuration.
P37 (input/output)
P36 (input/output)
P35 (input/output)
P34 (input/output)
Port 3
P33 (input/output)
P32 (input/output)
P31 (input/output)
P30 (input/output)
Figure 8.3 Port 3 Pin Functions
8.4.2
Register Configuration
Table 8.8 shows the port 3 register configuration.
Table 8.8
Port 3 Registers
Name
Abbreviation
R/W
Initial Value
Address
Port 3 data direction register
P3DDR
W
H'00
H'FFB4
Port 3 data register
P3DR
R/W
H'00
H'FFB6
Port 3 MOS pull-up control register
P3PCR
R/W
H'00
H'FFAE
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Section 8 I/O Ports
Port 3 Data Direction Register (P3DDR)
Bit
7
6
5
4
3
2
1
0
P37DDR
P36DDR
P35DDR
P34DDR
P33DDR
P32DDR
P31DDR
P30DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 3. P3DDR cannot be read; if it is, an undefined value will be returned.
P3DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Setting a P3DDR bit to 1 makes the corresponding port 3 pin an output port, while clearing the bit
to 0 makes the pin an input port.
Port 3 Data Register (P3DR)
Bit
7
6
5
4
3
2
1
0
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3DR is an 8-bit readable/writable register that stores output data for the port 3 pins (P37 to P30). If
a port 3 read is performed while P3DDR bits are set to 1, the P3DR values are read directly
regardless of the actual pin states. If a port 3 read is performed while P3DDR bits are cleared to 0,
the pin states are read.
P3DR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
software standby mode.
Port 3 MOS Pull-Up Control Register (P3PCR)
Bit
7
6
5
4
3
2
1
0
P37PCR
P36PCR
P35PCR
P34PCR
P33PCR
P32PCR
P31PCR
P30PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P3PCR is an 8-bit readable/writable register that controls the MOS input pull-up function
incorporated into port 3 on a bit-by-bit basis.
Rev. 3.00 Mar 17, 2006 page 193 of 706
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Section 8 I/O Ports
When a P3DDR bit is cleared to 0 (input port setting), setting the corresponding P3PCR bit to 1
turns on the MOS input pull-up for that pin.
P3PCR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
8.4.3
Pin Functions
Port 3 is used as an I/O port, with input or output specifiable individually for each pin. Setting a
P3DDR bit to 1 makes the corresponding port 3 pin an output port, while clearing the bit to 0
makes the pin an input port.
8.4.4
MOS Input Pull-Up Function
Port 3 has a built-in MOS input pull-up function that can be controlled by software. MOS input
pull-up can be specified as on or off for individual bits.
When a P3DDR bit is cleared to 0, setting the corresponding P3PCR bit to 1 turns on the MOS
input pull-up for that pin.
The MOS input pull-up function is in the off state after a reset and in hardware standby mode. The
previous state is retained in software standby mode.
Table 8.9 summarizes the MOS input pull-up states.
Table 8.9
MOS Input Pull-Up States (Port 3)
Reset
Hardware Standby Mode
Software Standby Mode
In Other Operations
Off
Off
On/Off
On/Off
Legend:
Off:
MOS input pull-up is always off.
On/Off: On when P3DDR = 0 and P3PCR = 1; otherwise off.
Rev. 3.00 Mar 17, 2006 page 194 of 706
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Section 8 I/O Ports
8.5
Port 4
8.5.1
Overview
Port 4 is an 8-bit I/O port. Port 4 is also used for external interrupt input (IRQ0 to IRQ2), A/D
converter input (ADTRG), IIC0 input/output (SDA0), and system clock (φ) output. The output
type of P47 is NMOS push-pull. The output type of SDA0 is NMOS open-drain with direct bus
drive capability.
Figure 8.4 shows the port 4 pin configuration.
P47 (input/output) / SDA0 (input/output)
P46 (input/output) / φ (output)
P45 (input/output)
Port 4
P44 (input/output)
P43 (input/output)
P42 (input/output) / IRQ0 (input)
P41 (input/output) / IRQ1 (input)
P40 (input/output) / IRQ2 (input) / ADTRG (input)
Figure 8.4 Port 4 Pin Functions
8.5.2
Register Configuration
Table 8.10 shows the port 4 register configuration.
Table 8.10 Port 4 Registers
Name
Abbreviation
R/W
Initial Value
Address
Port 4 data direction register
P4DDR
W
H'00
H'FFB5
Port 4 data register
P4DR
R/W
H'00
H'FFB7
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Section 8 I/O Ports
Port 4 Data Direction Register (P4DDR)
Bit
7
6
5
4
3
2
1
0
P47DDR
P46DDR
P45DDR
P44DDR
P43DDR
P42DDR
P41DDR
P40DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P4DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 4. P4DDR cannot be read; if it is, an undefined value will be returned.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
When P4DDR bits are set to 1, pin P46 functions as the φ output pin, and pins P47 and P45 to P40
function as output ports. Clearing a P4DDR bit to 0 makes the corresponding pin an input port.
Port 4 Data Register (P4DR)
Bit
7
6
5
4
3
2
1
0
P47DR
P46DR
P45DR
P44DR
P43DR
P42DR
P41DR
P40DR
Initial value
0
—*
0
0
0
0
0
0
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Determined by the state of pin P46.
P4DR is an 8-bit readable/writable register that stores output data for the port 4 pins (P47 to P40).
Except for P46, if a port 4 read is performed while P4DDR bits are set to 1, the P4DR values are
read directly regardless of the actual pin states. If a port 4 read is performed while P4DDR bits are
cleared to 0, the pin states are read.
P4DR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
software standby mode.
Rev. 3.00 Mar 17, 2006 page 196 of 706
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Section 8 I/O Ports
8.5.3
Pin Functions
Port 4 pins are also used for external interrupt input (IRQ0 to IRQ2), A/D converter input
(ADTRG), IIC0 input/output (SDA0), and system clock (φ) output.
Port 4 pin functions are shown in table 8.11.
Table 8.11 Port 4 Pin Functions
Pin
Pin Functions and Selection Method
P47/SDA0
The pin function is selected as shown below by a combination of bit ICE in ICCR
of IIC0 and bit P47DDR.
ICE
P47DDR
Pin function
0
1
0
1
—
P47 input
P47 output
SDA0 I/O
When this pin is designated as the P47 output pin, it is an NMOS push-pull
output. The output type of SDA0 is NMOS open-drain with direct bus drive
capability.
P46/φ
P46DDR
Pin function
P45
P45DDR
Pin function
P44
P44DDR
Pin function
P43
P43DDR
Pin function
P42/IRQ0
P42DDR
Pin function
0
1
P46 input
φ output
0
1
P45 input
P45 output
0
1
P44 input
P44 output
0
1
P43 input
P43 output
0
1
P42 input
P42 output
IRQ0 input
When bit IRQ0E is set to 1 in IER, this pin is used as the IRQ0 input pin.
Rev. 3.00 Mar 17, 2006 page 197 of 706
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Section 8 I/O Ports
Pin
P41/IRQ1
Pin Functions and Selection Method
P41DDR
Pin function
0
1
P41 input
P41 output
IRQ1 input
When bit IRQ1E is set to 1 in IER, this pin is used as the IRQ1 input pin.
P40/IRQ2/
ADTRG
P40DDR
Pin function
0
1
P40 input
P40 output
IRQ2 input, ADTRG input
When bit IRQ2E is set to 1 in IER, this pin is used as the IRQ2 input pin.
When bits TRGS1 and TRGS0 are both set to 1 in the A/D converter’s ADCR
register, this pin is used as the ADTRG input pin.
Rev. 3.00 Mar 17, 2006 page 198 of 706
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Section 8 I/O Ports
8.6
Port 5
8.6.1
Overview
Port 5 is a 3-bit I/O port. Port 5 is also used for SCI0 input/output (TxD0, RxD0, SCK0) and IIC0
input/output (SCL0). The output type of P52 and SCK0 is NMOS push-pull. The output type of
SCL0 is NMOS open-drain.
Figure 8.5 shows the port 5 pin configuration.
Port 5 pins
P52 (input/output) / SCK0 (input/output) / SCL0 (input/output)
Port 5
P51 (input/output) / RxD0 (input)
P50 (input/output) / TxD0 (output)
Figure 8.5 Port 5 Pin Functions
8.6.2
Register Configuration
Table 8.12 shows the port 5 register configuration.
Table 8.12 Port 5 Registers
Name
Abbreviation
R/W
Initial Value
Address
Port 5 data direction register
P5DDR
W
H'F8
H'FFB8
Port 5 data register
P5DR
R/W
H'F8
H'FFBA
Rev. 3.00 Mar 17, 2006 page 199 of 706
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Section 8 I/O Ports
Port 5 Data Direction Register (P5DDR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
P52DDR
P51DDR
P50DDR
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
P5DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 5. P5DDR cannot be read; if it is, an undefined value will be returned. Bits 7 to 3 are
reserved.
Setting a P5DDR bit to 1 makes the corresponding port 5 pin an output port, while clearing the bit
to 0 makes the pin an input port.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. It retains its previous state
in software standby mode. As SCI0 is initialized, the pin states are determined by IIC0’s ICCR,
P5DDR, and P5DR specifications.
Port 5 Data Register (P5DR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
P52DR
P51DR
P50DR
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P52 to P50). If
a port 5 read is performed while P5DDR bits are set to 1, the P5DR values are read directly
regardless of the actual pin states. If a port 5 read is performed while P5DDR bits are cleared to 0,
the pin states are read.
Bits 7 to 3 are reserved; they cannot be modified and are always read as 1.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. It retains its previous state in
software standby mode.
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Section 8 I/O Ports
8.6.3
Pin Functions
Port 5 pins are also used for SCI0 input/output (TxD0, RxD0, SCK0) and IIC0 input/output (SCL0).
Port 5 pin functions are shown in table 8.13.
Table 8.13 Port 5 Pin Functions
Pin
Pin Functions and Selection Method
P52/SCK0/
SCL0
The pin function is selected as shown below by a combination of bit C/A in SMR
of SCI0, bits CKE0 and CKE1 in SCR, bit ICE in ICCR of IIC0, and bit P52DDR.
ICE
0
CKE1
C/A
Pin function
1
0
1
—
0
1
—
—
0
0
CKE0
P52DDR
1
0
0
0
1
—
—
—
—
P52
input
P52
output
SCK0
output
SCK0
output
SCK0
input
SCL0
I/O
When this pin is used as the SCL0 I/O pin, bits CKE1 and CKE0 in SCR of SCI0
and bit C/A in SMR must all be cleared to 0. The output type of SCL0 is NMOS
open-drain with direct bus drive capability.
When this pin is designated as the P52 output pin or SCK0 output pin, it is an
NMOS push-pull output.
P51/RxD0
The pin function is selected as shown below by a combination of bit RE in SCR of
SCI0 and bit P51DDR.
RE
P51DDR
Pin function
P50/TxD0
0
1
0
1
—
P51 input
P51 output
RxD0 input
The pin function is selected as shown below by a combination of bit TE in SCR of
SCI0 and bit P50DDR.
TE
P50DDR
Pin function
0
1
0
1
—
P50 input
P50 output
TxD0 output
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Section 8 I/O Ports
8.7
Port 6
8.7.1
Overview
Port 6 is an 8-bit I/O port. It is also used for 16-bit free-running timer (FRT) input/output (FTOA,
FTOB, FTIA to FTID, FTCI), timer 0 and 1 (TMR0, TMR1) input/output (TMCI0, TMRI0, TMO0,
TMCI1, TMRI1, TMO1), timer X (TMRX) input/output (TMOX, TMIX), timer Y (TMRY) input
(TMIY), and timer connection input/output (CSYNCI, HSYNCI, HSYNCO, HFBACKI,
VSYNCI, VSYNCO, VFBACKI, CLAMPO).
Figure 8.6 shows the port 6 pin configuration.
Port 6 pins
P67 (input/output) / TMOX (output) / TMO1 (output) / HSYNCO (output)
Port 6
P66 (input/output) / FTOB (output) / TMRI1 (input)
/ CSYNCI (input)
P65 (input/output) / FTID
(input) / TMCI1 (input)
/ HSYNCI (input)
P64 (input/output) / FTIC
(input) / TMO0 (output) / CLAMPO (output)
P63 (input/output) / FTIB
(input) / TMRI0 (input)
P62 (input/output) / FTIA
(input) / VSYNCI(input) / TMIY (input)
/ VFBACKI (input)
P61 (input/output) / FTOA (output) / VSYNCO(output)
P60 (input/output) / FTCI
(input) / TMCI0 (input)
/ HFBACKI (input) / TMIX (input)
Figure 8.6 Port 6 Pin Functions
8.7.2
Register Configuration
Table 8.14 shows the port 6 register configuration.
Table 8.14 Port 6 Registers
Name
Abbreviation
R/W
Initial Value
Address
Port 6 data direction register
P6DDR
W
H'00
H'FFB9
Port 6 data register
P6DR
R/W
H'00
H'FFBB
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Section 8 I/O Ports
Port 6 Data Direction Register (P6DDR)
Bit
7
6
5
4
3
2
1
0
P67DDR
P66DDR
P65DDR
P64DDR
P63DDR
P62DDR
P61DDR
P60DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P6DDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port 6. P6DDR cannot be read; if it is, an undefined value will be returned.
Setting a P6DDR bit to 1 makes the corresponding port 6 pin an output port, while clearing the bit
to 0 makes the pin an input port.
P6DDR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Port 6 Data Register (P6DR)
Bit
7
6
5
4
3
2
1
0
P67DR
P66DR
P65DR
P64DR
P63DR
P62DR
P61DR
P60DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). If
a port 6 read is performed while P6DDR bits are set to 1, the P6DR values are read directly
regardless of the actual pin states. If a port 6 read is performed while P6DDR bits are cleared to 0,
the pin states are read.
P6DR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state in
software standby mode.
8.7.3
Pin Functions
Port 6 pins are also used for 16-bit free-running timer (FRT) input/output (FTOA, FTOB, FTIA to
FTID, FTCI), timer 0 and 1 (TMR0, TMR1) input/output (TMCI0, TMRI0, TMO0, TMCI1, TMRI1,
TMO1), timer X (TMRX) input/output (TMOX, TMIX), timer Y (TMRY) input (TMIY), and
timer connection input/output (CSYNCI, HSYNCI, HSYNCO, HFBACKI, VSYNCI, VSYNCO,
VFBACKI, CLAMPO.
Port 6 pin functions are shown in table 8.15.
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Section 8 I/O Ports
Table 8.15 Port 6 Pin Functions
Pin
Pin Functions and Selection Method
P67/TMO1/
TMOX/
HSYNCO
The pin function is selected as shown below by a combination of bits OS3 to OS0
in TCSR of TMR1 and TMRX, bit HOE of timer connection TCONRO, and bit
P67DDR.
HOE
0
TMRX: OS3–0
TMR1: OS3–0
All 0
P67DDR
Pin function
P66/FTOB/
TMRI1/CSYNCI
1
All 0
Not all 0
—
Not all 0
—
—
0
1
—
—
—
P67
input
P67
output
TMO1
output
TMOX
output
HSYNCO
output
The pin function is selected as shown below by a combination of bit OEB in
TOCR of FRT and bit P66DDR.
OEB
0
P66DDR
Pin function
1
0
1
—
P66 input
P66 output
FTOB output
TMRI1 input, CSYNCI input
When bits CCLR1 and CCLR0 are both set to 1 in TCR of TMR1, this pin is used
as the TMRI1 input pin.
P65/FTID/
TMCI1/HSYNCI
P65DDR
Pin function
0
1
P65 input
P65 output
FTID input, TMCI1 input, HSYNCI input
When an external clock is selected with bits CKS2 to CKS0 in TCR of TMR1, this
pin is used as the TMCI1 input pin.
P64/FTIC/
TMO0/
CLAMPO
The pin function is selected as shown below by a combination of bits OS3 to OS0
in TCSR of TMR0, bit CLOE of timer connection TCONRO, and bit P64DDR.
CLOE
0
OS3–0
P64DDR
Pin function
1
All 0
Not all 0
All 0
0
1
—
—
P64 input
P64 output
TMO0 output
CLAMPO
output
FTIC input
When this pin is used as the CLAMPO pin, bits OS3 to OS0 in TCSR of TMR0
must be cleared to 0.
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Section 8 I/O Ports
Pin
Pin Functions and Selection Method
P63/FTIB/
P63DDR
TMRI0/VFBACKI Pin function
0
1
P63 input
P63 output
FTIB input, TMRI0 input, VFBACKI input
When bits CCLR1 and CCLR0 are both set to 1 in TCR of TMR0, this pin is used
as the TMRI0 input pin.
P62/FTIA/
VSYNCI/TMIY
P62DDR
Pin function
0
1
P62 input
P62 output
FTIA input, VSYNCI input, TMIY input
P61/FTOA/
VSYNCO
The pin function is selected as shown below by a combination of bit OEA in
TOCR of FRT, bit VOE of timer connection TCONRO, and bit P61DDR.
VOE
0
OEA
P61DDR
Pin function
0
1
1
0
0
1
—
—
P61 input
P61 output
FTOA0 output
VSYNCO
output
When this pin is used as the VSYNCO pin, bit OEA in TOCR of FRT must be
cleared to 0.
P60/FTCI/TMCI0/
HFBACKI/TMIX
P60DDR
Pin function
0
1
P60 input
P60 output
FTCI input, TMCI0 input, HFBACKI input, TMIX input
When an external clock is selected with bits CKS1 and CKS0 in TCR of FRT, this
pin is used as the FTCI input pin.
When an external clock is selected with bits CKS2 to CKS0 in TCR of TMR0, this
pin is used as the TMCI0 input pin.
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Section 8 I/O Ports
8.8
Port 7
8.8.1
Overview
Port 7 is an 8-bit input port. Port 7 is also used for A/D converter analog input (AN7 to AN0).
Bits 7 to 4 of port 7 are provided in the H8/3577 Group, but not in the H8/3567 Group. Therefore
the H8/3567 Group does not have the input pin functions or four A/D converter analog input pin
(AN7 to AN4) functions corresponding to bits 7 to 4 of port 7.
Figure 8.7 shows the port 7 pin configuration.
Port 7 pins
P77 (input) / AN7 (input)
P76 (input) / AN6 (input)
P75 (input) / AN5 (input)
P74 (input) / AN4 (input)
Port 7
P73 (input) / AN3 (input)
P72 (input) / AN2 (input)
P71 (input) / AN1 (input)
P70 (input) / AN0 (input)
Figure 8.7 Port 7 Pin Functions
8.8.2
Register Configuration
Table 8.16 shows the port 7 register configuration. As port 7 is an input port, it has no data
direction register or data register.
Table 8.16 Port 7 Registers
Name
Abbreviation
R/W
Initial Value
Address
Port 7 input data register
P7PIN
R
Undefined
H'FFBE
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Section 8 I/O Ports
Port 7 Input Data Register (P7PIN)
Bit
7
6
5
4
3
2
1
0
P77PIN
P76PIN
P75PIN
P74PIN
P73PIN
P72PIN
P71PIN
P70PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note:
*
Determined by the state of pins P77 to P70.
When a P7PIN read is performed, the pin states are always read.
In the H8/3567 Group, reading bits 7 to 4 will return an undefined value.
8.8.3
Pin Functions
Port 7 pins are also used for A/D converter analog input (AN7 to AN0).
In the H8/3567 Group, the port 7 pins (P70 to P73) are also used for A/D converter analog input
(AN0 to AN3).
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Section 8 I/O Ports
8.9
Port C [H8/3567 Group Version with On-Chip USB Only]
8.9.1
Overview
Port C is an 8-bit I/O port.
Port C is provided only in the H8/3567 Group version with an on-chip USB.
Port C is also used for input/output to control the USB hub downstream port power supply IC.
Figure 8.8 shows the port C pin configuration.
PC7 (input/output) / OCP5 (input)
PC6 (input/output) / OCP4 (input)
PC5 (input/output) / OCP3 (input)
PC4 (input/output) / OCP2 (input)
Port C
PC3 (input/output) / ENP5 (output)
PC2 (input/output) / ENP4 (output)
PC1 (input/output) / ENP3 (output)
PC0 (input/output) / ENP2 (output)
Figure 8.8 Port C Pin Functions
8.9.2
Register Configuration
Table 8.17 shows the port C register configuration.
Table 8.17 Port C Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port C data direction register
PCDDR
W
H'00
H'FE4E
Port C output data register
PCODR
R/W
H'00
H'FE4C
Port C input data register
PCPIN
R
Undefined
H'FE4E
Note:
*
PCPIN and PCDDR have the same address.
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Section 8 I/O Ports
Port C Data Direction Register (PCDDR)
Bit
7
6
5
4
3
2
1
0
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PCDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port C. PCDDR cannot be read; if it is, an undefined value will be returned.
Setting a PCDDR bit to 1 makes the corresponding port C pin an output port, while clearing the bit
to 0 makes the pin an input port.
PCDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Port C Data Output Register (PCODR)
Bit
7
6
5
4
3
2
1
0
PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PCODR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to
PC0). PCODR can be read and written to at all times, regardless of the contents of PCDDR.
PCODR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Port C Input Data Register (PCPIN)
Bit
7
6
5
4
3
2
1
0
PC7PIN
PC6PIN
PC5PIN
PC4PIN
PC3PIN
PC2PIN
PC1PIN
PC0PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note:
*
Determined by the state of pins PC7 to PC0.
When a PCPIN read is performed, the pin states are always read.
Rev. 3.00 Mar 17, 2006 page 209 of 706
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Section 8 I/O Ports
PCPIN and PCDDR have the same address. When a write is performed, data is written to PCDDR
and the port C setting changes.
8.9.3
Pin Functions
Port C pins PC7 to PC4 are also used as input pins (OCP5 to OCP2) that receive overcurrent
detection signals (overcurrent signals) output from the USB hub downstream port power supply
IC. Port C pins PC3 to PC0 are also used as output pins (ENP5 to ENP2) for power supply output
enable signals (enable signals) input to the USB hub downstream port power supply IC. The
power supply IC control pin function can be enabled or disabled for each OCP/ENP pair by means
of bits 3 to 0 (HOC5E to HOC2E) in the USB’s HOCCR register.
When the power supply IC control pin function is disabled, port C is used as an I/O port, with
input or output specifiable individually for each pin. Setting a PCDDR bit to 1 makes the
corresponding port C pin an output port, while clearing the bit to 0 makes the pin an input port.
Rev. 3.00 Mar 17, 2006 page 210 of 706
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Section 8 I/O Ports
8.10
Port D [H8/3567 Group Version with On-Chip USB Only]
8.10.1
Overview
Port D is an 8-bit I/O port.
Port D is provided only in the H8/3567 Group version with an on-chip USB.
Port D is also used for USB hub downstream data input/output.
Port D input/output characteristics are prescribed by the USB bus driver/receiver power supply
(DrVCC) voltage.
Figure 8.9 shows the port D pin configuration.
PD7 (input/output) / DS5D− (input/output)
PD6 (input/output) / DS5D+ (input/output)
PD5 (input/output) / DS4D− (input/output)
PD4 (input/output) / DS4D+ (input/output)
Port D
PD3 (input/output) / DS3D− (input/output)
PD2 (input/output) / DS3D+ (input/output)
PD1 (input/output) / DS2D− (input/output)
PD0 (input/output) / DS2D+ (input/output)
Figure 8.9 Port D Pin Functions
8.10.2
Register Configuration
Table 8.18 shows the port D register configuration.
Table 8.18 Port D Registers
Name
Abbreviation
R/W
Initial Value
Address*
Port D data direction register
PDDDR
W
H'00
H'FE4F
Port D output data register
PDODR
R/W
H'00
H'FE4D
Port D input data register
PDPIN
R
Undefined
H'FE4F
Note:
*
PDPIN and PDDDR have the same address.
Rev. 3.00 Mar 17, 2006 page 211 of 706
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Section 8 I/O Ports
Port D Data Direction Register (PDDDR)
Bit
7
6
5
4
3
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
PDDDR is an 8-bit write-only register, the individual bits of which specify input or output for the
pins of port D. PDDDR cannot be read; if it is, an undefined value will be returned.
Setting a PDDDR bit to 1 makes the corresponding port D pin an output port, while clearing the
bit to 0 makes the pin an input port.
PDDDR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Port D Data Output Register (PDODR)
Bit
7
6
5
4
3
2
1
0
PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PDODR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to
PD0). PDODR can be read and written to at all times, regardless of the contents of PDDDR.
PDODR is initialized to H'00 by a reset and in hardware standby mode. It retains its previous state
in software standby mode.
Port D Input Data Register (PDPIN)
Bit
7
6
5
4
3
2
1
0
PD7PIN
PD6PIN
PD5PIN
PD4PIN
PD3PIN
PD2PIN
PD1PIN
PD0PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Note:
*
Determined by the state of pins PD7 to PD0.
When a PDPIN read is performed, the pin states are always read.
Rev. 3.00 Mar 17, 2006 page 212 of 706
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Section 8 I/O Ports
PDPIN and PDDDR have the same address. When a write is performed, data is written to PDDDR
and the port D setting changes.
8.10.3
Pin Functions
Port D pins are also used for USB hub downstream data input/output.
When the FONLY bit is cleared to 1 in the USBCR register, port D is used as an I/O port, with
input or output specifiable individually for each pin. Setting a PDDDR bit to 1 makes the
corresponding port D pin an output port, while clearing the bit to 0 makes the pin an input port.
When the FONLY bit is cleared to 0, port D is used for USB hub downstream data input/output.
The USB provided in the H8/3567 Group has a built-in bus driver/receiver, and port D operates on
the bus driver/receiver power supply (DrVCC) regardless of the setting of the FONLY bit.
Therefore, Port D input/output characteristics are prescribed by the DrVCC voltage.
Rev. 3.00 Mar 17, 2006 page 213 of 706
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Section 8 I/O Ports
Rev. 3.00 Mar 17, 2006 page 214 of 706
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Section 9 8-Bit PWM Timers
Section 9 8-Bit PWM Timers
9.1
Overview
The H8/3577 Group and H8/3567 Group have an on-chip PWM (pulse width modulation) timer,
with sixteen (H8/3577 Group) or eight (H8/3567 Group) outputs. Sixteen output waveforms are
generated from a common time base, enabling PWM output with a high carrier frequency to be
produced using pulse division. The PWM timer module has sixteen 8-bit PWM data registers
(PWDRs), and an output pulse with a duty cycle of 0 to 100% can be obtained as specified by
PWDR and the port data register (P1DR or P2DR).
9.1.1
Features
The PWM timer module has the following features.
• Operable at a maximum carrier frequency of 1.25 MHz using pulse division (at 20 MHz
operation)
• Duty cycles from 0 to 100% with 1/256 resolution (100% duty realized by port output)
• Direct or inverted PWM output, and PWM output enable/disable control
Rev. 3.00 Mar 17, 2006 page 215 of 706
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Section 9 8-Bit PWM Timers
9.1.2
Block Diagram
Figure 9.1 shows a block diagram of the PWM timer module.
PWDR0
P11/PW1
Comparator 1
PWDR1
P12/PW2
Comparator 2
PWDR2
P13/PW3
Comparator 3
PWDR3
P14/PW4
Comparator 4
PWDR4
Comparator 5
PWDR5
Comparator 6
PWDR6
Comparator 7
PWDR7
Comparator 8
PWDR8
P15/PW5
P16/PW6
P17/PW7
P20/PW8
P21/PW9
P22/PW10
H8/3577
Group
only
Comparator 9
PWDR9
Comparator 10
PWDR10
Comparator 11
PWDR11
P24/PW12
Comparator 12
PWDR12
P25/PW13
Comparator 13
PWDR13
P26/PW14
Comparator 14
PWDR14
P27/PW15
Comparator 15
PWDR15
TCNT
Clock
selection
P23/PW11
PWDPRB
PWDPRA
PWOERB
PWOERA
P2DDR
P1DDR
P2DR
P1DR
Legend:
PWSL:
PWDR:
PWDPRA:
PWDPRB:
PWOERA:
PWOERB:
PCSR:
P1DDR:
P2DDR:
P1DR:
P2DR:
PWM register select
PWM data register
PWM data polarity register A
PWM data polarity register B
PWM output enable register A
PWM output enable register B
Peripheral clock select register
Port 1 data direction register
Port 2 data direction register
Port 1 data register
Port 2 data register
φ/16
φ/8
φ/4
φ/2
φ
Internal clock
Figure 9.1 Block Diagram of PWM Timer Module
Rev. 3.00 Mar 17, 2006 page 216 of 706
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Module
data bus
Bus interface
Comparator 0
Port/PWM output control
P10/PW0
PWSL
PCSR
Internal
data bus
Section 9 8-Bit PWM Timers
9.1.3
Pin Configuration
Table 9.1 shows the PWM output pin.
Table 9.1
Pin Configuration
Name
Abbreviation
I/O
Function
PWM output pin 0 to 7
PW0 to PW7
Output
PWM timer pulse output 0 to 7
PWM output pin 8 to 15
PW8 to PW15
Output
PWM timer pulse output 8 to 15
(H8/3577 Group only)
9.1.4
Register Configuration
Table 9.2 lists the registers of the PWM timer module.
Table 9.2
PWM Timer Module Registers
Name
Abbreviation
R/W
Initial Value
Address
PWM register select
PWSL
R/W
H'20
H'FFD6
PWM data registers 0 to 15
PWDR0 to
PWDR15
R/W
H'00
H'FFD7
PWM data polarity register A
PWDPRA
R/W
H'00
H'FFD5
PWM data polarity register B
PWDPRB
R/W
H'00
H'FFD4
PWM output enable register A
PWOERA
R/W
H'00
H'FFD3
PWM output enable register B
PWOERB
R/W
H'00
H'FFD2
Port 1 data direction register
P1DDR
W
H'00
H'FFB0
Port 2 data direction register
P2DDR
W
H'00
H'FFB1
Port 1 data register
P1DR
R/W
H'00
H'FFB2
Port 2 data register
P2DR
R/W
H'00
H'FFB3
Peripheral clock select register
PCSR
R/W
H'00
H'FF82
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Rev. 3.00 Mar 17, 2006 page 217 of 706
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Section 9 8-Bit PWM Timers
9.2
Register Descriptions
9.2.1
PWM Register Select (PWSL)
Bit
7
6
5
4
3
2
1
0
PWCKE
PWCKS
—
—
RS3
RS2
RS1
RS0
Initial value
0
0
1
0
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
PWSL is an 8-bit readable/writable register used to select the PWM timer input clock and the
PWM data register.
PWSL is initialized to H'20 by a reset, and in the standby modes, and module stop mode.
Bits 7 and 6—PWM Clock Enable, PWM Clock Select (PWCKE, PWCKS): These bits,
together with bits PWCKA and PWCKB in PCSR, select the internal clock input to TCNT in the
PWM timer.
PWSL
PCSR
Bit 7
Bit 6
Bit 2
Bit 1
PWCKE
PWCKS
PWCKB
PWCKA
Description
0
—
—
—
Clock input is disabled
1
0
—
—
φ (system clock) is selected
1
0
0
φ/2 is selected
1
φ/4 is selected
0
φ/8 is selected
1
φ/16 is selected
1
(Initial value)
The PWM resolution, PWM conversion period, and carrier frequency depend on the selected
internal clock, and can be found from the following equations.
Resolution (minimum pulse width) = 1/internal clock frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
Thus, with a 20 MHz system clock (φ), the resolution, PWM conversion period, and carrier
frequency are as shown below.
Rev. 3.00 Mar 17, 2006 page 218 of 706
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Section 9 8-Bit PWM Timers
Resolution, PWM Conversion Period, and Carrier Frequency when φ = 20 MHz
Table 9.3
Internal Clock
Frequency
Resolution
PWM Conversion
Period
Carrier Frequency
φ
50 ns
12.8 µs
1250 kHz
φ/2
100 ns
25.6 µs
625 kHz
φ/4
200 ns
51.2 µs
312.5 kHz
φ/8
400 ns
102.4 µs
156.3 kHz
φ/16
800 ns
204.8 µs
78.1 kHz
Bit 5—Reserved: This bit is always read as 1 and cannot be modified.
Bit 4—Reserved: This bit is always read as 0 and cannot be modified.
Bits 3 to 0—Register Select (RS3 to RS0): These bits select the PWM data register.
Bit 3
Bit 2
Bit 1
Bit 0
RS3
RS2
RS1
RS0
Register Selection
0
0
0
0
PWDR0 selected
1
PWDR1 selected
1
1
0
1
1
0
0
1
1
0
1
0
PWDR2 selected
1
PWDR3 selected
0
PWDR4 selected
1
PWDR5 selected
0
PWDR6 selected
1
PWDR7 selected
0
PWDR8 selected
1
PWDR9 selected
0
PWDR10 selected
1
PWDR11 selected
0
PWDR12 selected
1
PWDR13 selected
0
PWDR14 selected
1
PWDR15 selected
Rev. 3.00 Mar 17, 2006 page 219 of 706
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Section 9 8-Bit PWM Timers
9.2.2
PWM Data Registers (PWDR0 to PWDR15)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each PWDR is an 8-bit readable/writable register that specifies the duty cycle of the basic pulse to
be output, and the number of additional pulses. The value set in PWDR corresponds to a 0 or 1
ratio in the conversion period. The upper 4 bits specify the duty cycle of the basic pulse as 0/16 to
15/16 with a resolution of 1/16. The lower 4 bits specify how many extra pulses are to be added
within the conversion period comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256
is possible for 0/1 ratios within the conversion period. For 256/256 (100%) output, port output
should be used.
PWDR is initialized to H'00 by a reset, and in the standby modes, and module stop mode.
9.2.3
PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)
PWDPRA
Bit
7
6
5
4
3
2
1
0
OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
OS15
OS14
OS13
OS12
OS11
OS10
OS9
OS8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWDPRB
Bit
Each PWDPR is an 8-bit readable/writable register that controls the polarity of the PWM output.
Bits OS0 to OS15 correspond to outputs PW0 to PW15.
Rev. 3.00 Mar 17, 2006 page 220 of 706
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Section 9 8-Bit PWM Timers
PWDPR is initialized to H'00 by a reset and in hardware standby mode.
OS
Description
0
PWM direct output (PWDR value corresponds to high width of output)
1
PWM inverted output (PWDR value corresponds to low width of output)
9.2.4
PWM Output Enable Registers A and B (PWOERA and PWOERB)
(Initial value)
PWOERA
Bit
7
6
5
4
3
2
1
0
OE7
OE6
OE5
OE4
OE3
OE2
OE1
OE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
OE15
OE14
OE13
OE12
OE11
OE10
OE9
OE8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
PWOERB
Bit
Each PWOER is an 8-bit readable/writable register that switches between PWM output and port
output. Bits OE15 to OE0 correspond to outputs PW15 to PW0. To set a pin in the output state, a
setting in the port direction register is also necessary. Bits P17DDR to P10DDR correspond to
outputs PW7 to PW0, and bits P27DDR to P20DDR correspond to outputs PW15 to PW8.
PWOER is initialized to H'00 by a reset and in hardware standby mode.
DDR
OE
Description
0
0
Port input
1
Port input
0
Port output or PWM 256/256 output
1
PWM output (0 to 255/256 output)
1
(Initial value)
Rev. 3.00 Mar 17, 2006 page 221 of 706
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Section 9 8-Bit PWM Timers
9.2.5
Peripheral Clock Select Register (PCSR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
PWCKB
PWCKA
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
PCSR is an 8-bit readable/writable register that selects the PWM timer input clock.
PCSR is initialized to H'00 by a reset, and in hardware standby mode.
Bits 7 to 3—Reserved: These bits cannot be modified and are always read as 0.
Bits 2 and 1—PWM Clock Select (PWCKB, PWCKA): Together with bits PWCKE and
PWCKS in PWSL, these bits select the internal clock input to TCNT in the PWM timer. For
details, see section 9.2.1, PWM Register Select (PWSL).
Bit 0—Reserved: Do not set this bit to 1.
9.2.6
Port 1 Data Direction Register (P1DDR)
Bit
7
6
5
4
3
2
1
0
P17DDR
P16DDR
P15DDR
P14DDR
P13DDR
P12DDR
P11DDR
P10DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P1DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for
each pin of port 1 on a bit-by-bit basis.
Port 1 pins are multiplexed with pins PW0 to PW7. The bit corresponding to a pin to be used for
PWM output should be set to 1.
For details on P1DDR, see section 8.2, Port 1.
Rev. 3.00 Mar 17, 2006 page 222 of 706
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Section 9 8-Bit PWM Timers
9.2.7
Port 2 Data Direction Register (P2DDR)
Bit
7
6
5
4
3
2
1
0
P27DDR
P26DDR
P25DDR
P24DDR
P23DDR
P22DDR
P21DDR
P20DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
P2DDR is an 8-bit write-only register that specifies the input/output direction and PWM output for
each pin of port J on a bit-by-bit basis.
Port 2 pins are multiplexed with pins PW8 to PW15. The bit corresponding to a pin to be used for
PWM output should be set to 1.
For details on P2DDR, see section 8.3, Port 2.
9.2.8
Port 1 Data Register (P1DR)
Bit
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P1DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when
OS = 1).
For details on P1DR, see section 8.2, Port 1.
9.2.9
Port 2 Data Register (P2DR)
Bit
7
6
5
4
3
2
1
0
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
P2DR is an 8-bit readable/writable register used to fix PWM output at 1 (when OS = 0) or 0 (when
OS = 1).
For details on P2DR, see section 8.3, Port 2.
Rev. 3.00 Mar 17, 2006 page 223 of 706
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Section 9 8-Bit PWM Timers
9.2.10
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP11 bit is set to 1, 8-bit PWM timer operation is halted and a transition is made to
module stop mode. For details, see section 21.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 3—Module Stop (MSTP11): Specifies PWM module stop mode.
MSTPCRH
Bit 3
MSTP11
Description
0
PWM module stop mode is cleared
1
PWM module stop mode is set
Rev. 3.00 Mar 17, 2006 page 224 of 706
REJ09B0303-0300
(Initial value)
Section 9 8-Bit PWM Timers
9.3
Operation
9.3.1
Correspondence between PWM Data Register Contents and Output Waveform
The upper 4 bits of PWDR specify the duty cycle of the basic pulse as 0/16 to 15/16 with a
resolution of 1/16, as shown in table 9.4.
Table 9.4
Upper 6 Bits
0000
Duty Cycle of Basic Pulse
Basic Pulse Waveform (Internal)
0 1 2 3 4 5 6 7 8 9 A B C D E F 0
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
Rev. 3.00 Mar 17, 2006 page 225 of 706
REJ09B0303-0300
Section 9 8-Bit PWM Timers
The lower 4 bits of PWDR specify the position of pulses added to the 16 basic pulses, as shown in
table 9.5. An additional pulse consists of a high period (when OS = 0) with a width equal to the
resolution, added before the rising edge of a basic pulse. When the upper 4 bits of PWDR are
0000, there is no rising edge of the basic pulse, but the timing for adding pulses is the same.
Table 9.5
Position of Pulses Added to Basic Pulses
Basic Pulse No.
Lower 4 Bits
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0000
0001
Yes
0010
Yes
0011
Yes
Yes
Yes
Yes
Yes
Yes
0100
Yes
Yes
0101
Yes
Yes
Yes
Yes
Yes
0110
Yes
Yes
Yes
Yes
Yes
Yes
0111
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1000
Yes
Yes
Yes
Yes
Yes
Yes
Yes
1001
Yes
Yes
Yes
Yes
Yes
Yes
Yes Yes Yes
1010
Yes
Yes
Yes Yes Yes
Yes
Yes
Yes Yes Yes
1011
Yes
Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
1100
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes
1101
Yes Yes Yes
Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
1110
Yes Yes Yes Yes Yes Yes Yes
Yes Yes Yes Yes Yes Yes Yes
1111
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No additional pulse
Resolution width
Additional pulse provided
Additional pulse
Figure 9.2 Example of Additional Pulse Timing (When Upper 4 Bits of PWDR = 1000)
Rev. 3.00 Mar 17, 2006 page 226 of 706
REJ09B0303-0300
Section 10 14-Bit PWM Timer
Section 10 14-Bit PWM Timer
10.1
Overview
The H8/3577 Group and H8/3567 Group have an on-chip 14-bit PWM (pulse width modulator)
with two output channels.
Each channel can be connected to an external low-pass filter to operate as a 14-bit D/A converter.
Both channels share the same counter (DACNT) and control register (DACR).
10.1.1
Features
The features of the 14-bit PWM D/A are listed below.
• The pulse is subdivided into multiple base cycles to reduce ripple.
• Two resolution settings and two base cycle settings are available
The resolution can be set equal to one or two system clock cycles. The base cycle can be set
equal to T × 64 or T × 256, where T is the resolution.
• Four operating rates
The two resolution settings and two base cycle settings combine to give a selection of four
operating rates.
Rev. 3.00 Mar 17, 2006 page 227 of 706
REJ09B0303-0300
Section 10 14-Bit PWM Timer
10.1.2
Block Diagram
Figure 10.1 shows a block diagram of the PWM D/A module.
Internal clock
φ
Internal data bus
φ/2
Clock
Clock selection
Bus interface
Basic cycle
compare-match A
PWX0
Fine-adjustment
pulse addition A
PWX1
Basic cycle
compare-match B
Fine-adjustment
pulse addition B
Comparator
A
DADRA
Comparator
B
DADRB
Control logic
Basic cycle overflow
DACNT
DACR
Module data bus
Legend:
DACR:
DADRA:
DADRB:
DACNT:
PWM D/A control register ( 6 bits)
PWM D/A data register A (15 bits)
PWM D/A data register B (15 bits)
PWM D/A counter (14 bits)
Figure 10.1 PWM D/A Block Diagram
Rev. 3.00 Mar 17, 2006 page 228 of 706
REJ09B0303-0300
Section 10 14-Bit PWM Timer
10.1.3
Pin Configuration
Table 10.1 lists the pins used by the PWM D/A module.
Table 10.1 Input and Output Pins
Channel
Name
Abbr.
I/O
Function
A
PWM output pin 0
PWX0
Output
PWM output, channel A
B
PWM output pin 1
PWX1
Output
PWM output, channel B
10.1.4
Register Configuration
Table 10.2 lists the registers of the PWM D/A module.
Table 10.2 Register Configuration
Name
Abbreviation
R/W
Initial value
Address
PWM D/A control register
DACR
R/W
H'30
PWM D/A data register A high
DADRAH
R/W
H'FF
H'FFA0*
H'FFA0*
PWM D/A data register A low
DADRAL
R/W
H'FF
PWM D/A data register B high
DADRBH
R/W
H'FF
PWM D/A data register B low
DADRBL
R/W
H'FF
PWM D/A counter high
DACNTH
R/W
H'00
H'FFA7*
H'FFA6*
PWM D/A counter low
DACNTL
R/W
H'03
H'FFA7*
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Note:
*
H'FFA1*
H'FFA6*
The registers of the 14-bit PWM timer are assigned to the same addresses as other
registers. Selection of each register is performed by the IICE bit of the serial timer
control register (STCR). Also, the same addresses are shared by DADRAH and DACR,
and by DADRB and DACNT. Switching is performed by the REGS bit in DACNT or
DADRB.
Rev. 3.00 Mar 17, 2006 page 229 of 706
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Section 10 14-Bit PWM Timer
10.2
Register Descriptions
10.2.1
PWM D/A Counter (DACNT)
DACNTH
DACNTL
Bit (CPU)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit (Counter)
7
6
5
4
3
2
1
0
8
9
10
11
12
13
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
— REGS
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
1
1
—
R/W
DACNT is a 14-bit readable/writable up-counter that increments on an input clock pulse. The
input clock is selected by the clock select bit (CKS) in DACR. The CPU can read and write the
DACNT value, but since DACNT is a 16-bit register, data transfers between it and the CPU are
performed using a temporary register (TEMP). See section 10.3, Bus Master Interface, for details.
DACNT functions as the time base for both PWM D/A channels. When a channel operates with
14-bit precision, it uses all DACNT bits. When a channel operates with 12-bit precision, it uses the
lower 12 (counter) bits and ignores the upper two (counter) bits.
DACNT is initialized to H'0003 by a reset, in the standby modes, and module stop mode, and by
the PWME bit.
Bit 1 of DACNTL (CPU) is not used, and is always read as 1.
DACNTL Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
Description
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
Rev. 3.00 Mar 17, 2006 page 230 of 706
REJ09B0303-0300
(Initial value)
Section 10 14-Bit PWM Timer
10.2.2
D/A Data Registers A and B (DADRA and DADRB)
DADRH
DADRL
Bit (CPU)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit (Data)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
DADRA
Initial value
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
DADRB
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS
Initial value
Read/Write
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
There are two 16-bit readable/writable D/A data registers: DADRA and DADRB. DADRA
corresponds to PWM D/A channel A, and DADRB to PWM D/A channel B. The CPU can read
and write the PWM D/A data register values, but since DADRA and DADRB are 16-bit registers,
data transfers between them and the CPU are performed using a temporary register (TEMP). See
section 10.3, Bus Master Interface, for details.
The least significant (CPU) bit of DADRA is not used and is always read as 1.
DADR is initialized to H'FFFF by a reset, and in the standby modes, and module stop mode.
Bits 15 to 2—PWM D/A Data 13 to 0 (DA13 to DA0): The digital value to be converted to an
analog value is set in the upper 14 bits of the PWM D/A data register.
In each base cycle, the DACNT value is continually compared with these upper 14 bits to
determine the duty cycle of the output waveform, and to decide whether to output a fineadjustment pulse equal in width to the resolution. To enable this operation, the data register must
be set within a range that depends on the carrier frequency select bit (CFS). If the DADR value is
outside this range, the PWM output is held constant.
A channel can be operated with 12-bit precision by keeping the two lowest data bits (DA0 and
DA1) cleared to 0 and writing the data to be converted in the upper 12 bits. The two lowest data
bits correspond to the two highest counter (DACNT) bits.
Rev. 3.00 Mar 17, 2006 page 231 of 706
REJ09B0303-0300
Section 10 14-Bit PWM Timer
Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS
Description
0
Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1
Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
(Initial value)
DADRA Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS
Description
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
10.2.3
(Initial value)
PWM D/A Control Register (DACR)
Bit
7
6
5
4
3
2
1
0
TEST
PWME
—
—
OEB
OEA
OS
CKS
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, and module stop mode.
Bit 7—Test Mode (TEST): Selects test mode, which is used in testing the chip. Normally this bit
should be cleared to 0.
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Section 10 14-Bit PWM Timer
Bit 7
TEST
Description
0
PWM (D/A) in user state: normal operation
1
PWM (D/A) in test state: correct conversion results unobtainable
(Initial value)
Bit 6—PWM Enable (PWME): Starts or stops the PWM D/A counter (DACNT).
Bit 6
PWME
Description
0
DACNT operates as a 14-bit up-counter
1
DACNT halts at H'0003
(Initial value)
Bits 5 and 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Output Enable B (OEB): Enables or disables output on PWM D/A channel B.
Bit 3
OEB
Description
0
PWM (D/A) channel B output (at the PWX1 pin) is disabled
1
PWM (D/A) channel B output (at the PWX1 pin) is enabled
(Initial value)
Bit 2—Output Enable A (OEA): Enables or disables output on PWM D/A channel A.
Bit 2
OEA
Description
0
PWM (D/A) channel A output (at the PWX0 pin) is disabled
1
PWM (D/A) channel A output (at the PWX0 pin) is enabled
(Initial value)
Bit 1—Output Select (OS): Selects the phase of the PWM D/A output.
Bit 1
OS
Description
0
Direct PWM output
1
Inverted PWM output
(Initial value)
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Section 10 14-Bit PWM Timer
Bit 0—Clock Select (CKS): Selects the PWM D/A resolution. If the system clock (φ) frequency
is 10 MHz, resolutions of 100 ns and 200 ns can be selected.
Bit 0
CKS
Description
0
Operates at resolution (T) = system clock cycle time (tcyc)
1
Operates at resolution (T) = system clock cycle time (tcyc) × 2
10.2.4
(Initial value)
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP11 bit is set to 1, 14-bit PWM timer operation is halted and a transition is made to
module stop mode. For details, see section 21.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 3—Module Stop (MSTP11): Specifies PWMX module stop mode.
MSTPCRH
Bit 3
MSTP11
Description
0
PWMX module stop mode is cleared
1
PWMX module stop mode is set
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(Initial value)
Section 10 14-Bit PWM Timer
10.3
Bus Master Interface
DACNT, DADRA, and DADRB are 16-bit registers. The data bus linking the bus master and the
on-chip supporting modules, however, is only 8 bits wide. When the bus master accesses these
registers, it therefore uses an 8-bit temporary register (TEMP).
These registers are written and read as follows (taking the example of the CPU interface).
• Write
When the upper byte is written, the upper-byte write data is stored in TEMP. Next, when the
lower byte is written, the lower-byte write data and TEMP value are combined, and the
combined 16-bit value is written in the register.
• Read
When the upper byte is read, the upper-byte value is transferred to the CPU and the lower-byte
value is transferred to TEMP. Next, when the lower byte is read, the lower-byte value in
TEMP is transferred to the CPU.
These registers should always be accessed 16 bits at a time (by word access or two consecutive
byte accesses), and the upper byte should always be accessed before the lower byte. Correct data
will not be transferred if only the upper byte or only the lower byte is accessed.
Figure 10.2 shows the data flow for access to DACNT. The other registers are accessed similarly.
Example 1: Write to DACNT
MOV.W R0, @DACNT
; Write R0 contents to DACNT
Example 2: Read DADRA
MOV.W @DADRA, R0
; Copy contents of DADRA to R0
Table 10.3 Read and Write Access Methods for 16-Bit Registers
Read
Write
Register Name
Word
Byte
Word
Byte
DADRA and DADRB
Yes
Yes
Yes
×
DACNT
Yes
×
Yes
×
Notes: Yes: Permitted type of access. Word access includes successive byte accesses to the
upper byte (first) and lower byte (second).
×:
This type of access may give incorrect results.
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Section 10 14-Bit PWM Timer
Upper-Byte Write
CPU
(H'AA)
Upper byte
Module data bus
Bus
interface
TEMP
(H'AA)
DACNTH
(
)
DACNTL
(
)
Lower-Byte Write
CPU
(H'57)
Lower byte
Module data bus
Bus
interface
TEMP
(H'AA)
DACNTH
(H'AA)
DACNTL
(H'57)
Figure 10.2 (a) Access to DACNT (CPU Writes H'AA57 to DACNT)
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Section 10 14-Bit PWM Timer
Upper-Byte Read
CPU
(H'AA)
Upper byte
Module data bus
Bus
interface
TEMP
(H'57)
DACNTH
(H'AA)
DACNTL
(H'57)
Lower-Byte Read
CPU
(H'57)
Lower byte
Module data bus
Bus
interface
TEMP
(H'57)
DACNTH
(
)
DACNTL
(
)
Figure 10.2 (b) Access to DACNT (CPU Reads H'AA57 from DACNT)
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Section 10 14-Bit PWM Timer
10.4
Operation
A PWM waveform like the one shown in figure 10.3 is output from the PWMX pin. When OS =
0, the value in DADR corresponds to the total width (TL) of the low (0) pulses output in one
conversion cycle (256 pulses when CFS = 0, 64 pulses when CFS = 1). When OS = 1, the output
waveform is inverted and the DADR value corresponds to the total width (TH) of the high (1)
output pulses. Figure 10.4 shows the types of waveform output available.
1 conversion cycle
(T × 214 (= 16384))
tf
Basic cycle
(T × 64 or T × 256)
tL
T: Resolution
m
TL = ∑ tLn (when OS = 0)
n=1
(When CFS = 0, m = 256; when CFS = 1, m = 64)
Figure 10.3 PWM D/A Operation
Table 10.4 summarizes the relationships of the CKS, CFS, and OS bit settings to the resolution,
base cycle, and conversion cycle. The PWM output remains flat unless DADR contains at least a
certain minimum value. Table 10.4 indicates the range of DADR settings that give an output
waveform like the one in figure 10.3, and lists the conversion cycle length when low-order DADR
bits are kept cleared to 0, reducing the conversion precision to 12 bits or 10 bits.
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Section 10 14-Bit PWM Timer
Table 10.4 Settings and Operation (Examples when φ = 10 MHz)
Resolution
Base Conversion
T
Cycle
CKS
CFS Cycle
(µs)
(µs)
(µs)
0
0.1
0
6.4
1638.4
Fixed DADR Bits
TL (if OS = 0)
TH (if OS = 1)
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
1
25.6
1638.4
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
1
0.2
0
12.8
3276.8
1. Always low (or high)
(DADR = H'0001 to
H'03FD)
2. (Data value) × T
(DADR = H'0401 to
H'FFFD)
1
51.2
3276.8
1. Always low (or high)
(DADR = H'0003 to
H'00FF)
2. (Data value) × T
(DADR = H'0103 to
H'FFFF)
Note:
*
Bit Data
Precision
(Bits)
3 2 1 0
Conversion
Cycle*
14
(µs)
1638.4
12
0 0
409.6
10
0 0 0 0
102.4
14
1638.4
12
0 0
409.6
10
0 0 0 0
102.4
14
3276.8
12
0 0
819.2
10
0 0 0 0
204.8
14
3276.8
12
0 0
819.2
10
0 0 0 0
204.8
This column indicates the conversion cycle when specific DADR bits are fixed.
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Section 10 14-Bit PWM Timer
1. OS = 0 (DADR corresponds to TL)
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tL1
tf2
tf255
tL2
tL3
tL255
tf256
tL256
tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64
tL1 + tL2 + tL3 + · · · + tL255 + tL256 = TL
Figure 10.4 (1) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
1 conversion cycle
tf1
tL1
tf2
tL2
tf63
tL3
tL63
tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256
tL1 + tL2 + tL3 + · · · + tL63 + tL64 = TL
Figure 10.4 (2) Output Waveform
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tf64
tL64
Section 10 14-Bit PWM Timer
2. OS = 1 (DADR corresponds to TH)
a. CFS = 0 [base cycle = resolution (T) × 64]
1 conversion cycle
tf1
tH1
tf2
tf255
tH2
tH3
tH255
tf256
tH256
tf1 = tf2 = tf3 = · · · = tf255 = tf256 = T × 64
tH1 + tH2 + tH3 + · · · + tH255 + tH256 = TH
Figure 10.4 (3) Output Waveform
b. CFS = 1 [base cycle = resolution (T) × 256]
1 conversion cycle
tf1
tH1
tf2
tH2
tf63
tH3
tH63
tf64
tH64
tf1 = tf2 = tf3 = · · · = tf63 = tf64 = T × 256
tH1 + tH2 + tH3 + · · · + tH63 + tH64 = TH
Figure 10.4 (4) Output Waveform
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Section 10 14-Bit PWM Timer
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Section 11 16-Bit Free-Running Timer
Section 11 16-Bit Free-Running Timer
11.1
Overview
The H8/3577 Group and H8/3567 Group have a single-channel on-chip 16-bit free-running timer
(FRT). Applications of the FRT module include rectangular-wave output (up to two independent
waveforms), input pulse width measurement, and measurement of external clock periods.
11.1.1
Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
 The free-running counter can be driven by an internal clock source (φ/2, φ/8, or φ/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
 Each comparator can generate an independent waveform.
• Four input capture channels
 The current count can be captured on the rising or falling edge (selectable) of an input
signal.
 The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
 The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
 Two compare-match interrupts, four input capture interrupts, and one overflow interrupt
can be requested independently.
• Special functions provided by automatic addition function
 The contents of OCRAR and OCRAF can be added to the contents of OCRA
automatically, enabling a periodic waveform to be generated without software intervention.
 The contents of ICRD can be added automatically to the contents of OCRDM × 2, enabling
input capture operations in this interval to be restricted.
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Section 11 16-Bit Free-Running Timer
11.1.2
Block Diagram
Figure 11.1 shows a block diagram of the free-running timer.
External
clock source
Internal
clock sources
φ/2
φ/8
φ/32
FTCI
Clock select
OCRA R/F (H/L)
+
Clock
OCRA (H/L)
Comparematch A
Comparator A
FTOA
Overflow
FTOB
Clear
Bus interface
FRC (H/L)
Comparematch B
OCRB (H/L)
Control
logic
Input capture
FTIA
ICRA (H/L)
ICRB (H/L)
FTIB
Internal
data bus
Module data bus
Comparator B
ICRC (H/L)
FTIC
ICRD (H/L)
FTID
+
Comparator M
Compare-match M
×1
×2
OCRDM L
TCSR
TIER
TCR
TOCR
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Legend:
OCRA, B:
FRC:
ICRA, B, C, D:
TCSR:
Interrupt signals
Output compare register A, B (16 bits)
Free-running counter (16 bits)
Input capture register A, B, C, D (16 bits)
Timer control/status register (8 bits)
TIER: Timer interrupt enable register (8 bits)
TCR: Timer control register (8 bits)
TOCR: Timer output compare control
register (8 bits)
Figure 11.1 Block Diagram of 16-Bit Free-Running Timer
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Section 11 16-Bit Free-Running Timer
11.1.3
Input and Output Pins
Table 11.1 lists the input and output pins of the free-running timer module.
Table 11.1 Input and Output Pins of Free-Running Timer Module
Name
Abbreviation
I/O
Function
Counter clock input
FTCI
Input
FRC counter clock input
Output compare A
FTOA
Output
Output compare A output
Output compare B
FTOB
Output
Output compare B output
Input capture A
FTIA
Input
Input capture A input
Input capture B
FTIB
Input
Input capture B input
Input capture C
FTIC
Input
Input capture C input
Input capture D
FTID
Input
Input capture D input
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Section 11 16-Bit Free-Running Timer
11.1.4
Register Configuration
Table 11.2 lists the registers of the free-running timer module.
Table 11.2 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address
Timer interrupt enable register
TIER
R/W
H'01
H'FF90
Timer control/status register
TCSR
R/(W)*
H'00
H'FF91
Free-running counter
FRC
R/W
H'0000
H'FF92
Output compare register A
OCRA
R/W
H'FFFF
Output compare register B
OCRB
R/W
H'FFFF
H'FF94*
2
H'FF94*
Timer control register
TCR
R/W
H'00
H'FF96
Timer output compare control
register
TOCR
R/W
H'00
H'FF97
Input capture register A
ICRA
R
H'0000
Input capture register B
ICRB
R
H'0000
H'FF98*
3
H'FF9A*
Input capture register C
ICRC
R
H'0000
3
H'FF9C*
Input capture register D
ICRD
R
H'0000
Output compare register AR
OCRAR
R/W
H'FFFF
H'FF9E
3
H'FF98*
Output compare register AF
OCRAF
R/W
H'FFFF
Output compare register DM
OCRDM
R/W
H'0000
H'FF9A*
3
H'FF9C*
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
1
2
3
3
Notes: 1. Bits 7 to 1 are read-only; only 0 can be written to clear the flags.
Bit 0 is readable/writable.
2. OCRA and OCRB share the same address. Access is controlled by the OCRS
bit in TOCR.
3. ICRA, ICRB, and ICRC share the same addresses with OCRAR, OCRAF, and
OCRDM. Access is controlled by the ICRS bit in TOCR.
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Section 11 16-Bit Free-Running Timer
11.2
Register Descriptions
11.2.1
Free-Running Counter (FRC)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from a
clock source. The clock source is selected by bits CKS1 and CKS0 in TCR.
FRC can also be cleared by compare-match A.
When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in TCSR is set to 1.
FRC is initialized to H'0000 by a reset and in hardware standby mode.
11.2.2
Output Compare Registers A and B (OCRA, OCRB)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output compare
flags (OCFA or OCFB) is set in TCSR.
In addition, if the output enable bit (OEA or OEB) in TOCR is set to 1, when OCR and FRC
values match, the logic level selected by the output level bit (OLVLA or OLVLB) in TOCR is
output at the output compare pin (FTOA or FTOB). Following a reset, the FTOA and FTOB
output levels are 0 until the first compare-match.
OCR is initialized to H'FFFF by a reset and in hardware standby mode.
Rev. 3.00 Mar 17, 2006 page 247 of 706
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Section 11 16-Bit Free-Running Timer
11.2.3
Input Capture Registers A to D (ICRA to ICRD)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
There are four input capture registers, A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture input pin (FTIA to FTID) is
detected, the current FRC value is copied to the corresponding input capture register (ICRA to
ICRD). At the same time, the corresponding input capture flag (ICFA to ICFD) in TCSR is set to
1. The input capture edge is selected by the input edge select bits (IEDGA to IEDGD) in TCR.
ICRC and ICRD can be used as ICRA and ICRB buffer registers, respectively, and made to
perform buffer operations, by means of buffer enable bits A and B (BUFEA, BUFEB) in TCR.
Figure 11.2 shows the connections when ICRC is specified as the ICRA buffer register (BUFEA =
1). When ICRC is used as the ICRA buffer, both rising and falling edges can be specified as
transitions of the external input signal by setting IEDGA ≠ IEDGC. When IEDGA = IEDGC,
either the rising or falling edge is designated. See table 11.3.
Note: The FRC contents are transferred to the input capture register regardless of the value of
the input capture flag (ICF).
IEDGA BUFEA IEDGC
FTIA
Edge detect and
capture signal
generating circuit
ICRC
ICRA
Figure 11.2 Input Capture Buffering (Example)
Rev. 3.00 Mar 17, 2006 page 248 of 706
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FRC
Section 11 16-Bit Free-Running Timer
Table 11.3 Buffered Input Capture Edge Selection (Example)
IEDGA
IEDGC
Description
0
0
Captured on falling edge of input capture A (FTIA)
1
Captured on both rising and falling edges of input capture A (FTIA)
1
(Initial value)
0
1
Captured on rising edge of input capture A (FTIA)
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock
periods (φ). When triggering is enabled on both edges, the input capture pulse width should be at
least 2.5 system clock periods (φ).
ICR is initialized to H'0000 by a reset and in hardware standby mode.
11.2.4
Output Compare Registers AR and AF (OCRAR, OCRAF)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
OCRAR and OCRAF are 16-bit readable/writable registers.
When the OCRAMS bit in TOCR is set to 1, the operation of OCRA is changed to include the use
of OCRAR and OCRAF. The contents of OCRAR and OCRAF are automatically added
alternately to OCRA, and the result is written to OCRA. The write operation is performed on the
occurrence of compare-match A. In the 1st compare-match A after setting the OCRAMS bit to 1,
OCRAF is added.
The operation due to compare-match A varies according to whether the compare-match follows
addition of OCRAR or OCRAF. The value of the OLVLA bit in TOCR is ignored, and 1 is output
on a compare-match A following addition of OCRAF, while 0 is output on a compare-match A
following addition of OCRAR.
When using the OCRA automatic addition function, do not select internal clock φ/2 as the FRC
counter input clock together with a set value of H'0001 or less for OCRAR (or OCRAF).
OCRAR and OCRAF are initialized to H'FFFF by a reset and in hardware standby mode.
Rev. 3.00 Mar 17, 2006 page 249 of 706
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Section 11 16-Bit Free-Running Timer
11.2.5
Output Compare Register DM (OCRDM)
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R/W R/W R/W R/W R/W R/W R/W R/W
OCRDM is a 16-bit readable/writable register in which the upper 8 bits are fixed at H'00.
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000,
the operation of ICRD is changed to include the use of OCRDM. The point at which input capture
D occurs is taken as the start of a mask interval. Next, twice the contents of OCRDM is added to
the contents of ICRD, and the result is compared with the FRC value. The point at which the
values match is taken as the end of the mask interval. New input capture D events are disabled
during the mask interval.
A mask interval is not generated when the ICRDMS bit is set to 1 and the contents of OCRDM are
H'0000.
OCRDM is initialized to H'0000 by a reset and in hardware standby mode.
11.2.6
Timer Interrupt Enable Register (TIER)
Bit
7
6
5
4
3
2
1
0
ICIAE
ICIBE
ICICE
ICIDE
OCIAE
OCIBE
OVIE
—
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
TIER is an 8-bit readable/writable register that enables and disables interrupts.
TIER is initialized to H'01 by a reset and in hardware standby mode.
Bit 7—Input Capture Interrupt A Enable (ICIAE): Selects whether to request input capture
interrupt A (ICIA) when input capture flag A (ICFA) in TCSR is set to 1.
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Section 11 16-Bit Free-Running Timer
Bit 7
ICIAE
Description
0
Input capture interrupt request A (ICIA) is disabled
1
Input capture interrupt request A (ICIA) is enabled
(Initial value)
Bit 6—Input Capture Interrupt B Enable (ICIBE): Selects whether to request input capture
interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6
ICIBE
Description
0
Input capture interrupt request B (ICIB) is disabled
1
Input capture interrupt request B (ICIB) is enabled
(Initial value)
Bit 5—Input Capture Interrupt C Enable (ICICE): Selects whether to request input capture
interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5
ICICE
Description
0
Input capture interrupt request C (ICIC) is disabled
1
Input capture interrupt request C (ICIC) is enabled
(Initial value)
Bit 4—Input Capture Interrupt D Enable (ICIDE): Selects whether to request input capture
interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4
ICIDE
Description
0
Input capture interrupt request D (ICID) is disabled
1
Input capture interrupt request D (ICID) is enabled
(Initial value)
Bit 3—Output Compare Interrupt A Enable (OCIAE): Selects whether to request output
compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE
Description
0
Output compare interrupt request A (OCIA) is disabled
1
Output compare interrupt request A (OCIA) is enabled
(Initial value)
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Section 11 16-Bit Free-Running Timer
Bit 2—Output Compare Interrupt B Enable (OCIBE): Selects whether to request output
compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2
OCIBE
Description
0
Output compare interrupt request B (OCIB) is disabled
1
Output compare interrupt request B (OCIB) is enabled
(Initial value)
Bit 1—Timer Overflow Interrupt Enable (OVIE): Selects whether to request a free-running
timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to 1.
Bit 1
OVIE
Description
0
Timer overflow interrupt request (FOVI) is disabled
1
Timer overflow interrupt request (FOVI) is enabled
(Initial value)
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
11.2.7
Timer Control/Status Register (TCSR)
Bit
7
6
5
4
3
2
1
0
ICFA
ICFB
ICFC
ICFD
OCFA
OCFB
OVF
CCLRA
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
Note:
*
Only 0 can be written in bits 7 to 1 to clear these flags.
TCSR is an 8-bit register used for counter clear selection and control of interrupt request signals.
TCSR is initialized to H'00 by a reset and in hardware standby mode.
Timing is described in section 11.3, Operation.
Bit 7—Input Capture Flag A (ICFA): This status flag indicates that the FRC value has been
transferred to ICRA by means of an input capture signal. When BUFEA = 1, ICFA indicates that
the old ICRA value has been moved into ICRC and the new FRC value has been transferred to
ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by software.
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Section 11 16-Bit Free-Running Timer
Bit 7
ICFA
Description
0
[Clearing condition]
(Initial value)
Read ICFA when ICFA = 1, then write 0 in ICFA
1
[Setting condition]
When an input capture signal causes the FRC value to be transferred to
ICRA
Bit 6—Input Capture Flag B (ICFB): This status flag indicates that the FRC value has been
transferred to ICRB by means of an input capture signal. When BUFEB = 1, ICFB indicates that
the old ICRB value has been moved into ICRD and the new FRC value has been transferred to
ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 6
ICFB
Description
0
[Clearing condition]
(Initial value)
Read ICFB when ICFB = 1, then write 0 in ICFB
1
[Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRB
Bit 5—Input Capture Flag C (ICFC): This status flag indicates that the FRC value has been
transferred to ICRC by means of an input capture signal. When BUFEA = 1, on occurrence of the
signal transition in FTIC (input capture signal) specified by the IEDGC bit, ICFC is set but data is
not transferred to ICRC. Therefore, in buffer operation, ICFC can be used as an external interrupt
signal (by setting the ICICE bit to 1).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5
ICFC
Description
0
[Clearing condition]
(Initial value)
Read ICFC when ICFC = 1, then write 0 in ICFC
1
[Setting condition]
When an input capture signal is received
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Section 11 16-Bit Free-Running Timer
Bit 4—Input Capture Flag D (ICFD): This status flag indicates that the FRC value has been
transferred to ICRD by means of an input capture signal. When BUFEB = 1, on occurrence of the
signal transition in FTID (input capture signal) specified by the IEDGD bit, ICFD is set but data is
not transferred to ICRD. Therefore, in buffer operation, ICFD can be used as an external interrupt
by setting the ICIDE bit to 1.
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 4
ICFD
Description
0
[Clearing condition]
(Initial value)
Read ICFD when ICFD = 1, then write 0 in ICFD
1
[Setting condition]
When an input capture signal is received
Bit 3—Output Compare Flag A (OCFA): This status flag indicates that the FRC value matches
the OCRA value. This flag must be cleared by software. It is set by hardware, however, and
cannot be set by software.
Bit 3
OCFA
Description
0
[Clearing condition]
(Initial value)
Read OCFA when OCFA = 1, then write 0 in OCFA
1
[Setting condition]
When FRC = OCRA
Bit 2—Output Compare Flag B (OCFB): This status flag indicates that the FRC value matches
the OCRB value. This flag must be cleared by software. It is set by hardware, however, and cannot
be set by software.
Bit 2
OCFB
Description
0
[Clearing condition]
Read OCFB when OCFB = 1, then write 0 in OCFB
1
[Setting condition]
When FRC = OCRB
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(Initial value)
Section 11 16-Bit Free-Running Timer
Bit 1—Timer Overflow Flag (OVF): This status flag indicates that the FRC has overflowed
(changed from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware,
however, and cannot be set by software.
Bit 1
OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
When FRC changes from H'FFFF to H'0000
Bit 0—Counter Clear A (CCLRA): This bit selects whether the FRC is to be cleared at comparematch A (when the FRC and OCRA values match).
Bit 0
CCLRA
Description
0
FRC clearing is disabled
1
FRC is cleared at compare-match A
11.2.8
(Initial value)
Timer Control Register (TCR)
Bit
7
6
5
4
3
2
1
0
IEDGA
IEDGB
IEDGC
IEDGD
BUFEA
BUFEB
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input capture
signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in hardware standby mode
Bit 7—Input Edge Select A (IEDGA): Selects the rising or falling edge of the input capture A
signal (FTIA).
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Section 11 16-Bit Free-Running Timer
Bit 7
IEDGA
Description
0
Capture on the falling edge of FTIA
1
Capture on the rising edge of FTIA
(Initial value)
Bit 6—Input Edge Select B (IEDGB): Selects the rising or falling edge of the input capture B
signal (FTIB).
Bit 6
IEDGB
Description
0
Capture on the falling edge of FTIB
1
Capture on the rising edge of FTIB
(Initial value)
Bit 5—Input Edge Select C (IEDGC): Selects the rising or falling edge of the input capture C
signal (FTIC).
Bit 5
IEDGC
Description
0
Capture on the falling edge of FTIC
1
Capture on the rising edge of FTIC
(Initial value)
Bit 4—Input Edge Select D (IEDGD): Selects the rising or falling edge of the input capture D
signal (FTID).
Bit 4
IEDGD
Description
0
Capture on the falling edge of FTID
1
Capture on the rising edge of FTID
(Initial value)
Bit 3—Buffer Enable A (BUFEA): Selects whether ICRC is to be used as a buffer register for
ICRA.
Bit 3
BUFEA
Description
0
ICRC is not used as a buffer register for input capture A
1
ICRC is used as a buffer register for input capture A
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(Initial value)
Section 11 16-Bit Free-Running Timer
Bit 2—Buffer Enable B (BUFEB): Selects whether ICRD is to be used as a buffer register for
ICRB.
Bit 2
BUFEB
Description
0
ICRD is not used as a buffer register for input capture B
1
ICRD is used as a buffer register for input capture B
(Initial value)
Bits 1 and 0—Clock Select (CKS1, CKS0): Select external clock input or one of three internal
clock sources for the FRC. External clock pulses are counted on the rising edge of signals input to
the external clock input pin (FTCI).
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
φ/2 internal clock source
1
φ/8 internal clock source
0
φ/32 internal clock source
1
External clock source (rising edge)
1
11.2.9
(Initial value)
Timer Output Compare Control Register (TOCR)
Bit
7
6
ICRDMS OCRAMS
5
4
3
2
1
0
ICRS
OCRS
OEA
OEB
OLVLA
OLVLB
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, switches access between output compare registers A and B, controls the
ICRD and OCRA operating mode, and switches access to input capture registers A, B, and C.
TOCR is initialized to H'00 by a reset and in hardware standby mode.
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Section 11 16-Bit Free-Running Timer
Bit 7—Input Capture D Mode Select (ICRDMS): Specifies whether ICRD is used in the normal
operating mode or in the operating mode using OCRDM.
Bit 7
ICRDMS
Description
0
The normal operating mode is specified for ICRD
1
The operating mode using OCRDM is specified for ICRD
(Initial value)
Bit 6—Output Compare A Mode Select (OCRAMS): Specifies whether OCRA is used in the
normal operating mode or in the operating mode using OCRAR and OCRAF.
Bit 6
OCRAMS
Description
0
The normal operating mode is specified for OCRA
1
The operating mode using OCRAR and OCRAF is specified for OCRA
(Initial value)
Bit 5—Input Capture Register Select (ICRS): The same addresses are shared by ICRA and
OCRAR, by ICRB and OCRAF, and by ICRC and OCRDM. The ICRS bit determines which
registers are selected when the shared addresses are read or written to. The operation of ICRA,
ICRB, and ICRC is not affected.
Bit 5
ICRS
Description
0
The ICRA, ICRB, and ICRC registers are selected
1
The OCRAR, OCRAF, and OCRDM registers are selected
(Initial value)
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4
OCRS
Description
0
The OCRA register is selected
1
The OCRB register is selected
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(Initial value)
Section 11 16-Bit Free-Running Timer
Bit 3—Output Enable A (OEA): Enables or disables output of the output compare A signal
(FTOA).
Bit 3
OEA
Description
0
Output compare A output is disabled
1
Output compare A output is enabled
(Initial value)
Bit 2—Output Enable B (OEB): Enables or disables output of the output compare B signal
(FTOB).
Bit 2
OEB
Description
0
Output compare B output is disabled
1
Output compare B output is enabled
(Initial value)
Bit 1—Output Level A (OLVLA): Selects the logic level to be output at the FTOA pin in
response to compare-match A (signal indicating a match between the FRC and OCRA values).
When the OCRAMS bit is 1, this bit is ignored.
Bit 1
OLVLA
Description
0
0 output at compare-match A
1
1 output at compare-match A
(Initial value)
Bit 0—Output Level B (OLVLB): Selects the logic level to be output at the FTOB pin in
response to compare-match B (signal indicating a match between the FRC and OCRB values).
Bit 0
OLVLB
Description
0
0 output at compare-match B
1
1 output at compare-match B
(Initial value)
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Section 11 16-Bit Free-Running Timer
11.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13 bit is set to 1, FRT operation is stopped at the end of the bus cycle, and
module stop mode is entered. For details, see section 21.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (MSTP13): Specifies the FRT module stop mode.
Bit 5
MSTPCRH
Description
0
FRT module stop mode is cleared
1
FRT module stop mode is set
11.3
Operation
11.3.1
FRC Increment Timing
(Initial value)
FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source.
Internal Clock: Any of three internal clocks (φ/2, φ/8, or φ/32) created by division of the system
clock (φ) can be selected by making the appropriate setting in bits CKS1 and CKS0 in TCR.
Figure 11.3 shows the increment timing.
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Section 11 16-Bit Free-Running Timer
φ
Internal
clock
FRC input
clock
FRC
N–1
N
N+1
Figure 11.3 Increment Timing with Internal Clock Source
External Clock: If external clock input is selected by bits CKS1 and CKS0 in TCR, FRC
increments on the rising edge of the external clock signal.
The pulse width of the external clock signal must be at least 1.5 system clock (φ) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
Figure 11.4 shows the increment timing.
φ
External
clock input pin
FRC input
clock
FRC
N
N+1
Figure 11.4 Increment Timing with External Clock Source
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Section 11 16-Bit Free-Running Timer
11.3.2
Output Compare Output Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or
OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 11.5 shows the
timing of this operation for compare-match A.
φ
FRC
N
OCRA
N+1
N
N
N
Compare-match A
signal
Clear*
OLVLA
Output compare A
output pin FTOA
Note: * Vertical arrows (
) indicate instructions executed by software.
Figure 11.5 Timing of Output Compare A Output
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N+1
Section 11 16-Bit Free-Running Timer
11.3.3
FRC Clear Timing
FRC can be cleared when compare-match A occurs. Figure 11.6 shows the timing of this
operation.
φ
Compare-match A
signal
FRC
N
H'0000
Figure 11.6 Clearing of FRC by Compare-Match A
11.3.4
Input Capture Input Timing
Input Capture Input Timing: An internal input capture signal is generated from the rising or
falling edge of the signal at the input capture pin, as selected by the corresponding IEDGA to
IEDGD bit in TCR. Figure 11.7 shows the usual input capture timing when the rising edge is
selected (IEDGA to IEDGD = 1).
φ
Input capture
input pin
Input capture
signal
Figure 11.7 Input Capture Signal Timing (Usual Case)
If the upper byte of ICRA to ICRAD is being read when the corresponding input capture signal
arrives, the internal input capture signal is delayed by one system clock (φ) period. Figure 11.8
shows the timing for this case.
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Section 11 16-Bit Free-Running Timer
ICRA to ICRD read cycle
T1
T2
T3
φ
Input capture
input pin
Input capture
signal
Figure 11.8 Input Capture Signal Timing
(Input Capture Input when ICRA to ICRD Is Read)
Buffered Input Capture Input Timing: ICRC and ICRD can operate as buffers for ICRA and
ICRB.
Figure 11.9 shows how input capture operates when ICRA and ICRC are used in buffer mode
(BUFEA = 1) and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or
IEDG A = 1 and IEDGC = 0), so that input capture is performed on both the rising and falling
edges of FTIA.
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Section 11 16-Bit Free-Running Timer
φ
FTIA
Input capture
signal
FRC
n
ICRA
M
ICRC
m
n+1
N
N+1
n
n
N
M
M
n
Figure 11.9 Buffered Input Capture Timing (Usual Case)
When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the edge
transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will be set, and
if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be transferred to
ICRC, however.
In buffered input capture, if the upper byte of either of the two registers to which data will be
transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal arrives,
input capture is delayed by one system clock (φ) period. Figure 11.10 shows the timing when
BUFEA = 1.
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Section 11 16-Bit Free-Running Timer
Read cycle:
CPU reads ICRA or ICRC
T1
T2
T3
φ
FTIA
Input capture
signal
Figure 11.10 Buffered Input Capture Timing
(Input Capture Input when ICRA or ICRC Is Read)
11.3.5
Timing of Input Capture Flag (ICFA to ICFD) Setting
The input capture flag ICFA to ICFD is set to 1 by the internal input capture signal. The FRC
value is simultaneously transferred to the corresponding input capture register (ICRx). Figure
11.11 shows the timing of this operation.
φ
Input capture
signal
ICFA/B/C/D
N
FRC
ICRA/B/C/D
N
Figure 11.11 Setting of Input Capture Flag (ICFA to ICFD)
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Section 11 16-Bit Free-Running Timer
11.3.6
Setting of Output Compare Flags A and B (OCFA, OCFB)
The output compare flags are set to 1 by an internal compare-match signal generated when the
FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the last
state in which the two values match, just before FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 11.12 shows the timing of the setting of OCFA
and OCFB.
φ
FRC
N
OCRA or OCRB
N+1
N
Compare-match
signal
OCFA or OCFB
Figure 11.12 Setting of Output Compare Flag (OCFA, OCFB)
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Section 11 16-Bit Free-Running Timer
11.3.7
Setting of FRC Overflow Flag (OVF)
The FRC overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to H'0000).
Figure 11.13 shows the timing of this operation.
φ
FRC
H'FFFF
H'0000
Overflow signal
OVF
Figure 11.13 Setting of Overflow Flag (OVF)
11.3.8
Automatic Addition of OCRA and OCRAR/OCRAF
When the OCRAMS bit in TOCR is set to 1, the contents of OCRAR and OCRAF are
automatically added to OCRA alternately, and when an OCRA compare-match occurs a write to
OCRA is performed. The OCRA write timing is shown in figure 11.14.
φ
FRC
N
N+1
OCRA
N
N+A
OCRAR,
OCRAF
A
Compare-match
signal
Figure 11.14 OCRA Automatic Addition Timing
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Section 11 16-Bit Free-Running Timer
11.3.9
ICRD and OCRDM Mask Signal Generation
When the ICRDMS bit in TOCR is set to 1 and the contents of OCRDM are other than H'0000, a
signal that masks the ICRD input capture function is generated.
The mask signal is set by the input capture signal. The mask signal setting timing is shown in
figure 11.15.
The mask signal is cleared by the sum of the ICRD contents and twice the OCRDM contents, and
an FRC compare-match. The mask signal clearing timing is shown in figure 11.16.
φ
Input capture
signal
Input capture
mask signal
Figure 11.15 Input Capture Mask Signal Setting Timing
φ
FRC
N
ICRD +
OCRDM × 2
N+1
N
Compare-match
signal
Input capture
mask signal
Figure 11.16 Input Capture Mask Signal Clearing Timing
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Section 11 16-Bit Free-Running Timer
11.4
Interrupts
The free-running timer can request seven interrupts (three types): input capture A to D (ICIA,
ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 11.4 lists information about these interrupts.
Table 11.4 Free-Running Timer Interrupts
Interrupt
Description
Priority
ICIA
Requested by ICFA
High
ICIB
Requested by ICFB
ICIC
Requested by ICFC
ICID
Requested by ICFD
OCIA
Requested by OCFA
OCIB
Requested by OCFB
FOVI
Requested by OVF
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Low
Section 11 16-Bit Free-Running Timer
11.5
Sample Application
In the example below, the free-running timer is used to generate pulse outputs with a 50% duty
cycle and arbitrary phase relationship. The programming is as follows:
• The CCLRA bit in TCSR is set to 1.
• Each time a compare-match interrupt occurs, software inverts the corresponding output level
bit in TOCR (OLVLA or OLVLB).
FRC
H'FFFF
Counter clear
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 11.17 Pulse Output (Example)
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Section 11 16-Bit Free-Running Timer
11.6
Usage Notes
Application programmers should note that the following types of contention can occur in the freerunning timer.
Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the state after an FRC write cycle, the clear signal takes priority and the write is not
performed.
Figure 11.18 shows this type of contention.
FRC write cycle
T1
T2
T3
φ
Address
FRC address
Internal write
signal
Counter clear
signal
FRC
N
H'0000
Figure 11.18 FRC Write-Clear Contention
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Section 11 16-Bit Free-Running Timer
Contention between FRC Write and Increment: Even if an increment pulse is generated in the
T3 state during FRC write cycle, it is not incremented and the count write takes priority.
Figure 11.19 shows this type of contention.
FRC write cycle
T1
T2
T3
φ
Address
FRC address
Internal write signal
FRC input clock
FRC
N
M
Write data
Figure 11.19 FRC Write-Increment Contention
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Section 11 16-Bit Free-Running Timer
Contention between OCR Write and Compare-Match: If a compare-match occurs in the T3
state during the OCRA or OCRB write cycle, the OCR write takes priority and the compare-match
signal is inhibited.
Figure 11.20 shows this type of contention.
When the automatic addition of OCRAR/OCRAF to OCRA is selected and a compare-match
occurs in the T3 state during the OCRA, OCRAR or OCRAF write cycle, the OCRA, OCRAR or
OCRAF write takes priority and the compare-match signal is inhibited. Consequently, the result of
automatic addition is not written.
OCRA or OCRB write cycle
T1
T2
T3
φ
Address
OCR address
Internal write signal
FRC
N
OCR
N
N+1
M
Write data
Compare-match
signal
Inhibited
Figure 11.20 Contention between OCR Write and Compare-Match
(When Not Using the Function of Automatic Addition)
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Section 11 16-Bit Free-Running Timer
φ
Address
OCRAR(OCRAF) address
Internal write signal
OCRAR
(OCRAF)
Old data
Compare-match
signal
inhibited
FRC
N
OCRA
N
New data
N+1
Since the compare-match signal is inhibited, automatic
addition does not occur.
Figure 11.21 Contention between OCRAR/OCRAF Write and Compare-Match
(When Using Automatic Addition)
Switching of Internal Clock and FRC Operation: When the internal clock is changed, the
changeover may cause FRC to increment. This depends on the time at which the clock select bits
(CKS1 and CKS0) are rewritten, as shown in table 11.5.
When an internal clock is used, the FRC clock is generated on detection of the falling edge of the
internal clock scaled from the system clock (φ). If the clock is changed when the old source is high
and the new source is low, as in case no. 3 in table 11.5, the changeover is regarded as a falling
edge that triggers the FRC increment clock pulse.
Switching between an internal and external clock can also cause FRC to increment.
Rev. 3.00 Mar 17, 2006 page 275 of 706
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Section 11 16-Bit Free-Running Timer
Table 11.5 Switching of Internal Clock and FRC Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Switching from
low to low
FRC Operation
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N+1
N
CKS bit rewrite
2
Switching from
low to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
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Section 11 16-Bit Free-Running Timer
No.
3
Timing of Switchover
by Means of CKS1
and CKS0 Bits
Switching from
high to low
FRC Operation
Clock before
switchover
Clock after
switchover
*
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
4
Switching from
high to high
Clock before
switchover
Clock after
switchover
FRC clock
FRC
N
N+1
N+2
CKS bit rewrite
Note:
*
Generated on the assumption that the switchover is a falling edge; FRC is incremented.
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Section 11 16-Bit Free-Running Timer
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Section 12 8-Bit Timers
Section 12 8-Bit Timers
12.1
Overview
The H8/3577 Group and H8/3567 Group have an on-chip 8-bit timer module with two channels
(TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers
(TCORA and TCORB) that are constantly compared with the TCNT value to detect comparematches. The 8-bit timer module can be used as a multifunction timer in a variety of applications,
such as generation of a rectangular-wave output with an arbitrary duty cycle.
The H8/3577 Group and H8/3567 Group also have two similar 8-bit timer channels (TMRX and
TMRY) that can be used in a connected configuration using the timer connection function. TMRX
and TMRY have greater input/output and interrupt function related restrictions than TMR0 and
TMR1.
12.1.1
Features
• Selection of clock sources
 TMR0, TMR1: The counter input clock can be selected from six internal clocks and an
external clock (enabling use as an external event counter).
 TMRX, TMRY: The counter input clock can be selected from three internal clocks and an
external clock (enabling use as an external event counter).
• Selection of three ways to clear the counters
 The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two compare-match signals
 The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to be used for various applications, such as the generation of
pulse output or PWM output with an arbitrary duty cycle.
(Note: TMRY does not have a timer output pin.)
• Cascading of the two channels (TMR0, TMR1)
 Operation as a 16-bit timer can be performed using channel 0 as the upper half and channel
1 as the lower half (16-bit count mode).
 Channel 1 can be used to count channel 0 compare-match occurrences (compare-match
count mode).
• Multiple interrupt sources for each channel
 TMR0, TMR1, TMRY: Two compare-match interrupts and one overflow interrupt can be
requested independently.
 TMRX: One input capture source is available.
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Section 12 8-Bit Timers
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the 8-bit timer module (TMR0 and TMR1).
TMRX and TMRY have a similar configuration, but cannot be cascaded. TMRX also has an input
capture function. For details, see section 13, Timer Connection.
External clock
sources
Internal clock
sources
TMCI0
TMCI1
TMR0
φ/8, φ/2
φ/64, φ/32
φ/1024, φ/256
TMR1
φ/8, φ/2
φ/64, φ/128
φ/1024, φ/2048
TMRX
φ
φ/2
φ/4
TMRY
φ/4
φ/256
φ/2048
Clock 1
Clock 0
Clock select
TCORA0
Compare-match A1
Compare-match A0 Comparator A0
TCNT0
Comparator A1
TCNT1
Clear 0
Clear 1
Compare-match B1
Compare-match B0 Comparator B0
TMO1
TMRI1
Comparator B1
Control logic
TCORB0
TCORB1
TCSR0
TCSR1
TCR0
TCR1
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
Figure 12.1 Block Diagram of 8-Bit Timer Module
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Internal bus
Overflow 1
Overflow 0
TMO0
TMRI0
TCORA1
Section 12 8-Bit Timers
12.1.3
Pin Configuration
Table 12.1 summarizes the input and output pins of the 8-bit timer module.
Table 12.1 8-Bit Timer Input and Output Pins
Channel
Name
Symbol*
I/O
Function
0
Timer output
TMO0
Output
Output controlled by compare-match
Timer clock input
TMCI0
Input
External clock input for the counter
Timer reset input
TMRI0
Input
External reset input for the counter
Timer output
TMO1
Output
Output controlled by compare-match
Timer clock input
TMCI1
Input
External clock input for the counter
Timer reset input
TMRI1
Input
External reset input for the counter
Timer output
TMOX
Output
Output controlled by compare-match
Timer clock/
reset input
HFBACKI/TMIX Input
(TMCIX/TMRIX)
External clock/reset input for the
counter
Timer clock/reset
input
VSYNCI/TMIY Input
(TMCIY/TMRIY)
External clock/reset input for the
counter
1
X
Y
Note:
*
The abbreviations TMO, TMCI, and TMRI are used in the text, omitting the channel
number.
Channel X and Y I/O pins have the same internal configuration as channels 0 and 1,
and therefore the same abbreviations are used.
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Section 12 8-Bit Timers
12.1.4
Register Configuration
Table 12.2 summarizes the registers of the 8-bit timer module.
Table 12.2 8-Bit Timer Registers
Channel
Name
Abbreviation*
0
Timer control register 0
Timer control/status register 0
Time constant register A0
Time constant register B0
Time counter 0
Timer control register 1
Timer control/status register 1
Time constant register A1
Time constant register B1
Timer counter 1
Serial timer control register
Module stop control register
TCR0
TCSR0
TCORA0
TCORB0
TCNT0
TCR1
TCSR1
TCORA1
TCORB1
TCNT1
STCR
MSTPCRH
MSTPCRL
TCONRS
TCRX
TCSRX
TCORAX
TCORBX
TCNTX
TCORC
TICRR
TICRF
TCRY
TCSRY
TCORAY
TCORBY
TCNTY
TISR
1
Common
X
Y
Timer connection register S
Timer control register X
Timer control/status register X
Time constant register AX
Time constant register BX
Timer counter X
Time constant register C
Input capture register R
Input capture register F
Timer control register Y
Timer control/status register Y
Time constant register AY
Time constant register BY
Timer counter Y
Timer input select register
2
R/W
Initial value
Address
R/W
1
R/(W)*
R/W
R/W
R/W
R/W
1
R/(W)*
H'00
H'00
H'FF
H'FF
H'00
H'00
H'10
H'FF
H'FF
H'00
H'00
H'3F
H'FF
H'00
H'00
H'00
H'FF
H'FF
H'00
H'FF
H'00
H'00
H'00
H'00
H'FF
H'FF
H'00
H'FE
H'FFC8
H'FFCA
H'FFCC
H'FFCE
H'FFD0
H'FFC9
H'FFCB
H'FFCD
H'FFCF
H'FFD1
H'FFC3
H'FF86
H'FF87
H'FFFE
H'FFF0
H'FFF1
H'FFF6
H'FFF7
H'FFF4
H'FFF5
H'FFF2
H'FFF3
H'FFF0
H'FFF1
H'FFF2
H'FFF3
H'FFF4
H'FFF5
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
1
R/(W)*
R/W
R/W
R/W
R/W
R
R
R/W
1
R/(W)*
R/W
R/W
R/W
R/W
Notes: 1. Only 0 can be written in bits 7 to 5, to clear these flags.
2. The abbreviations TCR, TCSR, TCORA, TCORB, and TCNT are used in the text,
omitting the channel designation (0, 1, X, or Y).
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Section 12 8-Bit Timers
Each pair of registers for channel 0 and channel 1 comprises a 16-bit register with the upper 8 bits
for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word access.
(Access is not divided into two 8-bit accesses.)
Certain of the channel X and channel Y registers are assigned to the same address. The TMRX/Y
bit in TCONRS determines which register is accessed.
12.2
Register Descriptions
12.2.1
Timer Counter (TCNT)
TCNT0
TCNT1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCNTX, TCNTY
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Each TCNT is an 8-bit readable/writable up-counter.
TCNT0 and TCNT1 comprise a single 16-bit register, so they can be accessed together by word
access.
TCNT increments on pulses generated from an internal or external clock source. This clock source
is selected by clock select bits CKS2 to CKS0 in TCR.
TCNT can be cleared by an external reset input signal or compare-match signal. Counter clear bits
CCLR1 and CCLR0 in TCR select the method of clearing.
When TCNT overflows from H'FF to H'00, the overflow flag (OVF) in TCSR is set to 1.
The timer counters are initialized to H'00 by a reset and in hardware standby mode.
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Section 12 8-Bit Timers
12.2.2
Time Constant Register A (TCORA)
TCORA0
TCORA1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORAX, TCORAY
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCORA is an 8-bit readable/writable register.
TCORA0 and TCORA1 comprise a single 16-bit register, so they can be accessed together by
word access.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag A (CMFA) in TCSR is set. Note, however, that comparison is
disabled during the T2 state of a TCORA write cycle.
The timer output can be freely controlled by these compare-match signals and the settings of
output select bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF by a reset and in hardware standby mode.
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Section 12 8-Bit Timers
12.2.3
Time Constant Register B (TCORB)
TCORB0
TCORB1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
TCORBX, TCORBY
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCORB is an 8-bit readable/writable register. TCORB0 and TCORB1 comprise a single 16-bit
register, so they can be accessed together by word access.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag B (CMFB) in TCSR is set. Note, however, that comparison is
disabled during the T2 state of a TCORB write cycle.
The timer output can be freely controlled by these compare-match signals and the settings of
output select bits OS3 and OS2 in TCSR.
TCORB is initialized to H'FF by a reset and in hardware standby mode.
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Section 12 8-Bit Timers
12.2.4
Timer Control Register (TCR)
Bit
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCR is an 8-bit readable/writable register that selects the clock source and the time at which
TCNT is cleared, and enables interrupts.
TCR is initialized to H'00 by a reset and in hardware standby mode.
For details of the timing, see section 12.3, Operation.
Bit 7—Compare-Match Interrupt Enable B (CMIEB): Selects whether the CMFB interrupt
request (CMIB) is enabled or disabled when the CMFB flag in TCSR is set to 1.
Note that a CMIB interrupt is not requested by TMRX, regardless of the CMIEB value.
Bit 7
CMIEB
Description
0
CMFB interrupt request (CMIB) is disabled
1
CMFB interrupt request (CMIB) is enabled
(Initial value)
Bit 6—Compare-Match Interrupt Enable A (CMIEA): Selects whether the CMFA interrupt
request (CMIA) is enabled or disabled when the CMFA flag in TCSR is set to 1.
Note that a CMIA interrupt is not requested by TMRX, regardless of the CMIEA value.
Bit 6
CMIEA
Description
0
CMFA interrupt request (CMIA) is disabled
1
CMFA interrupt request (CMIA) is enabled
Rev. 3.00 Mar 17, 2006 page 286 of 706
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(Initial value)
Section 12 8-Bit Timers
Bit 5—Timer Overflow Interrupt Enable (OVIE): Selects whether the OVF interrupt request
(OVI) is enabled or disabled when the OVF flag in TCSR is set to 1.
Note that an OVI interrupt is not requested by TMRX, regardless of the OVIE value.
Bit 5
OVIE
Description
0
OVF interrupt request (OVI) is disabled
1
OVF interrupt request (OVI) is enabled
(Initial value)
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1, CCLR0): These bits select the method by which
the timer counter is cleared: by compare-match A or B, or by an external reset input.
Bit 4
Bit 3
CCLR1
CCLR0
Description
0
0
Clearing is disabled
1
Cleared on compare-match A
0
Cleared on compare-match B
1
Cleared on rising edge of external reset input
1
(Initial value)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select whether the clock input to
TCNT is an internal or external clock.
The input clock can be selected from either six or three clocks, all divided from the system clock
(φ). The falling edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channel 0 and channel 1, because of the cascading function.
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Section 12 8-Bit Timers
TCR
STCR
Bit 2 Bit 1 Bit 0 Bit 1
Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0
1
Note:
*
0
0
0
—
—
Clock input disabled
(Initial value)
0
0
1
—
0
φ/8 internal clock source, counted on the falling edge
0
0
1
—
1
φ/2 internal clock source, counted on the falling edge
0
1
0
—
0
φ/64 internal clock source, counted on the falling
edge
0
1
0
—
1
φ/32 internal clock source, counted on the falling
edge
0
1
1
—
0
φ/1024 internal clock source, counted on the falling
edge
0
1
1
—
1
1
0
0
—
—
φ/256 internal clock source, counted on the falling
edge
Counted on TCNT1 overflow signal*
0
0
0
—
—
Clock input disabled
0
0
1
0
—
φ/8 internal clock source, counted on the falling edge
0
0
1
1
—
φ/2 internal clock source, counted on the falling edge
0
1
0
0
—
φ/64 internal clock source, counted on the falling
edge
0
1
0
1
—
φ/128 internal clock source, counted on the falling
edge
0
1
1
0
—
φ/1024 internal clock source, counted on the falling
edge
0
1
1
1
—
1
0
0
—
—
φ/2048 internal clock source, counted on the falling
edge
Counted on TCNT0 compare-match A*
(Initial value)
If the count input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
TCNT0 compare-match signal, no incrementing clock will be generated. Do not use this
setting.
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Section 12 8-Bit Timers
TCR
STCR
Bit 2 Bit 1 Bit 0 Bit 1
Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
X
Y
0
0
0
—
—
Clock input disabled
(Initial value)
0
0
1
—
—
Counted on φ internal clock source
0
1
0
—
—
φ/2 internal clock source, counted on the falling edge
0
1
1
—
—
φ/4 internal clock source, counted on the falling edge
1
0
0
—
—
Clock input disabled
0
0
0
—
—
Clock input disabled
0
0
1
—
—
φ/4 internal clock source, counted on the falling edge
0
1
0
—
—
φ/256 internal clock source, counted on the falling
edge
0
1
1
—
—
φ/2048 internal clock source, counted on the falling
edge
(Initial value)
1
0
0
—
—
Clock input disabled
Common 1
0
1
—
—
External clock source, counted at rising edge
1
1
0
—
—
External clock source, counted at falling edge
1
1
1
—
—
External clock source, counted at both rising and
falling edges
Rev. 3.00 Mar 17, 2006 page 289 of 706
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Section 12 8-Bit Timers
12.2.5
Timer Control/Status Register (TCSR)
TCSR0
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ADTE
OS3
OS2
OS1
OS0
0
R/(W)*
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
TCSR1
Bit
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
—
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICF
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICIE
OS3
OS2
OS1
OS0
0
R/(W)*
0
0
0
0
0
0
0
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
TCSRX
Bit
TCSRY
Bit
Initial value
Read/Write
Note:
*
Only 0 can be written in bits 7 to 5, and in bit 4 in TCSRX, to clear these flags.
TCSR is an 8-bit register that indicates compare-match and overflow statuses (and input capture
status in TMRX only), and controls compare-match output.
TCSR0, TCSRX, and TCSRY are initialized to H'00, and TCSR1 is initialized to H'10, by a reset
and in hardware standby mode.
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Section 12 8-Bit Timers
Bit 7—Compare-Match Flag B (CMFB): Status flag indicating whether the values of TCNT and
TCORB match.
Bit 7
CMFB
Description
0
[Clearing condition]
(Initial value)
Read CMFB when CMFB = 1, then write 0 in CMFB
1
[Setting condition]
When TCNT = TCORB
Bit 6—Compare-match Flag A (CMFA): Status flag indicating whether the values of TCNT and
TCORA match.
Bit 6
CMFA
Description
0
[Clearing condition]
(Initial value)
Read CMFA when CMFA = 1, then write 0 in CMFA
1
[Setting condition]
When TCNT = TCORA
Bit 5 —Timer Overflow Flag (OVF): Status flag indicating that TCNT has overflowed (changed
from H'FF to H'00).
Bit 5
OVF
Description
0
[Clearing condition]
(Initial value)
Read OVF when OVF = 1, then write 0 in OVF
1
[Setting condition]
When TCNT overflows from H'FF to H'00
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Section 12 8-Bit Timers
TCSR0 Bit 4—A/D Trigger Enable (ADTE): Enables or disables A/D converter start requests
by compare-match A.
TCSR0
Bit 4
ADTE
Description
0
A/D converter start requests by compare-match A are disabled
1
A/D converter start requests by compare-match A are enabled
(Initial value)
TCSR1 Bit 4—Reserved: This bit cannot be modified and is always read as 1.
TCSRX Bit 4—Input Capture Flag (ICF): Status flag that indicates detection of a rising edge
followed by a falling edge in the external reset signal after the ICST bit in TCONRI has been set
to 1.
TCSRX
Bit 4
ICF
Description
0
[Clearing condition]
(Initial value)
Read ICF when ICF = 1, then write 0 in ICF
1
[Setting condition]
When a rising edge followed by a falling edge is detected in the external reset signal
after the ICST bit in TCONRI has been set to 1
TCSRY Bit 4—Input Capture Interrupt Enable (ICIE): Selects enabling or disabling of the
interrupt request by ICF (ICIX) when the ICF bit in TCSRX is set to 1.
TCSRY
Bit 4
ICIE
Description
0
Interrupt request by ICF (ICIX) is disabled
1
Interrupt request by ICF (ICIX) is enabled
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(Initial value)
Section 12 8-Bit Timers
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify how the timer output level is
to be changed by a compare-match of TCOR and TCNT.
OS3 and OS2 select the effect of compare-match B on the output level, OS1 and OS0 select the
effect of compare-match A on the output level, and both of them can be controlled independently.
Note, however, that priorities are set such that: trigger output > 1 output > 0 output. If comparematches occur simultaneously, the output changes according to the compare-match with the higher
priority.
Timer output is disabled when bits OS3 to OS0 are all 0.
After a reset, the timer output is 0 until the first compare-match occurs.
Bit 3
Bit 2
OS3
OS2
Description
0
0
No change when compare-match B occurs
1
0 is output when compare-match B occurs
0
1 is output when compare-match B occurs
1
Output is inverted when compare-match B occurs (toggle output)
1
(Initial value)
Bit 1
Bit 0
OS1
OS0
Description
0
0
No change when compare-match A occurs
1
0 is output when compare-match A occurs
0
1 is output when compare-match A occurs
1
Output is inverted when compare-match A occurs (toggle output)
1
(Initial value)
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Section 12 8-Bit Timers
12.2.6
Serial Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
—
IICX1
IICX0
IICE
—
USBE
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC operating mode
(when the on-chip IIC option is included), and on-chip flash memory (in F-ZTAT versions), and
also selects the TCNT input clock.
For details on functions not related to the 8-bit timers, see section 3.2.3, Serial Timer Control
Register (STCR), and the descriptions of the relevant modules. If a module controlled by STCR is
not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: Do not write 1 to this bit.
2
2
Bits 6 to 4—I C Control (IICX1, IICX0, IICE): These bits control the operation of the I C bus
2
interface when the IIC option is included on-chip. See section 16, I C Bus Interface, for details.
Bit 3—Reserved: This bit must not be set to 1.
Bit 2—USB Enable (USBE): This bit controls CPU access to the USB data register and control
register.
Bit 2
USBE
Description
0
Prohibition of the above register access
1
Permission of the above register access
(initial value)
Bits 1 and 0—Internal Clock Select 1 and 0 (ICKS1, ICKS0): These bits, together with bits
CKS2 to CKS0 in TCR, select the clock to be input to TCNT. For details, see section 12.2.4,
Timer Control Register.
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Section 12 8-Bit Timers
12.2.7
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
Only bit 1 is described here. For details on functions not related to the 8-bit timers, see sections
3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant modules.
Bit 1—Host Interface Enable (HIE): Controls CPU access to 8-bit timer (channel X and Y) data
registers and control registers, and timer connection control registers.
Bit 1
HIE
Description
0
CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is enabled
(Initial value)
1
CPU access to 8-bit timer (channel X and Y) data registers and control registers, and
timer connection control registers, is disabled
12.2.8
Timer Connection Register S (TCONRS)
Bit
7
6
5
4
3
2
HOMOD1 HOMOD0 VOMOD1 VOMOD0
1
0
TMRX/Y
ISGENE
CLMOD1
CLMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCONRS is an 8-bit readable/writable register that controls access to the TMRX and TMRY
registers and timer connection operation.
TCONRS is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be
accessed when the HIE bit in SYSCR is cleared to 0. In the H8/3577 Group and H8/3567 Group,
some of the TMRX registers and the TMRY registers are assigned to the same memory space
addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed.
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Section 12 8-Bit Timers
Accessible Registers
Bit 7
TMRX/Y
H'FFF0
H'FFF1
H'FFF2
H'FFF3
H'FFF4
0
TCRX
(Initial value) (TMRX)
TCSRX
(TMRX)
TICRR
(TMRX)
TICRF
(TMRX)
TCNTX TCORC TCORAX TCORBX
(TMRX) (TMRX) (TMRX) (TMRX)
1
TCSRY
(TMRY)
TCORAY TCORBY TCNTY TISR
(TMRY) (TMRY) (TMRY) (TMRY)
12.2.9
TCRY
(TMRY)
H'FFF5
H'FFF6
H'FFF7
Input Capture Register (TICR) [TMRX Additional Function]
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
—
—
—
—
TICR is an 8-bit internal register to which the contents of TCNT are transferred on the falling edge
of external reset input. The CPU cannot read or write to TICR directly.
The TICR function is used in timer connection. For details, see section 13, Timer Connection.
12.2.10 Time Constant Register C (TCORC) [TMRX Additional Function]
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCORC is an 8-bit readable/writable register. The sum of the contents of TCORC and TICR is
continually compared with the value in TCNT. When a match is detected, a compare-match C
signal is generated. Note, however, that comparison is disabled during the T2 state of a TCORC
write cycle and a TICR input capture cycle.
TCORC is initialized to H'FF by a reset and in hardware standby mode.
The TCORC function is used in timer connection. For details, see section 13, Timer Connection.
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Section 12 8-Bit Timers
12.2.11 Input Capture Registers R and F (TICRR, TICRF) [TMRX Additional Functions]
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
TICRR and TICRF are 8-bit read-only registers. When the ICST bit in TCONRI is set to 1,
TICRR and TICRF capture the contents of TCNT successively on the rise and fall of the external
reset input. When one capture operation ends, the ICST bit is cleared to 0.
TICRR and TICRF are each initialized to H'00 by a reset and in hardware standby mode.
The TICRR and TICRF functions are used in timer connection. For details, see section 13, Timer
Connection.
12.2.12 Timer Input Select Register (TISR) [TMRY Additional Function]
Bit
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
IS
Initial value
1
1
1
1
1
1
1
0
Read/Write
—
—
—
—
—
—
—
R/W
TISR is an 8-bit readable/writable register that selects the external clock/reset signal source for the
counter.
TISR is initialized to H'FE by a reset and in hardware standby mode.
Bits 7 to 1—Reserved: Do not write 0.
Bit 0—Input Select (IS): Selects the internal synchronization signal (IVG signal) or the timer
clock/reset input pin (TMIY (TMCIY/TMRIY)) as the external clock/reset signal source for the
counter.
Bit 0
IS
Description
0
IVG signal is selected
1
TMIY (TMCIY/TMRIY) is selected
(Initial value)
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Section 12 8-Bit Timers
12.2.13 Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP12 bit or MSTP8 bit is set to 1, at the end of the bus cycle 8-bit timer operation is
halted on channels 0 and 1 or channels X and Y, respectively, and a transition is made to module
stop mode. For details, see section 21.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer (channel 0/1) module stop
mode.
MSTPCRH
Bit 4
MSTP12
Description
0
8-bit timer (channel 0/1) module stop mode is cleared
1
8-bit timer (channel 0/1) module stop mode is set
(Initial value)
MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer (channel X/Y) and timer
connection module stop mode.
MSTPCRH
Bit 0
MSTP8
Description
0
8-bit timer (channel X/Y) and timer connection module stop mode is cleared
1
8-bit timer (channel X/Y) and timer connection module stop mode is set
(Initial value)
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Section 12 8-Bit Timers
12.3
Operation
12.3.1
TCNT Incrementation Timing
TCNT is incremented by input clock pulses (either internal or external).
Internal Clock: An internal clock created by dividing the system clock (φ) can be selected by
setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing.
φ
Internal clock
TCNT input
clock
TCNT
N–1
N
N+1
Figure 12.2 Count Timing for Internal Clock Input
External Clock: Three incrementation methods can be selected by setting bits CKS2 to CKS0 in
TCR: at the rising edge, the falling edge, and both rising and falling edges.
Note that the external clock pulse width must be at least 1.5 states for incrementation at a single
edge, and at least 2.5 states for incrementation at both edges. The counter will not increment
correctly if the pulse width is less than these values.
Figure 12.3 shows the timing of incrementation at both edges of an external clock signal.
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Section 12 8-Bit Timers
φ
External clock
input pin
TCNT input
clock
TCNT
N–1
N
N+1
Figure 12.3 Count Timing for External Clock Input
12.3.2
Compare-Match Timing
Setting of Compare-Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in
TCSR are set to 1 by a compare-match signal generated when the TCOR and TCNT values match.
The compare-match signal is generated at the last state in which the match is true, just before the
timer counter is updated.
Therefore, when TCOR and TCNT match, the compare-match signal is not generated until the
next incrementation clock input. Figure 12.4 shows this timing.
φ
TCNT
N
TCOR
N
Compare-match
signal
CMF
Figure 12.4 Timing of CMF Setting
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N+1
Section 12 8-Bit Timers
Timer Output Timing: When compare-match A or B occurs, the timer output changes as
specified by the output select bits (OS3 to OS0) in TCSR. Depending on these bits, the output can
remain the same, be set to 0, be set to 1, or toggle.
Figure 12.5 shows the timing when the output is set to toggle at compare-match A.
φ
Compare-match A
signal
Timer output
pin
Figure 12.5 Timing of Timer Output
Timing of Compare-Match Clear: TCNT is cleared when compare-match A or B occurs,
depending on the setting of the CCLR1 and CCLR0 bits in TCR. Figure 12.6 shows the timing of
this operation.
φ
Compare-match
signal
TCNT
N
H'00
Figure 12.6 Timing of Compare-Match Clear
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Section 12 8-Bit Timers
12.3.3
TCNT External Reset Timing
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The width of the clearing pulse must be at least 1.5 states. Figure
12.7 shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
H'00
Figure 12.7 Timing of Clearing by External Reset Input
12.3.4
Timing of Overflow Flag (OVF) Setting
OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
12.8 shows the timing of this operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 12.8 Timing of OVF Setting
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Section 12 8-Bit Timers
12.3.5
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer can be used (16-bit timer
mode) or compare-matches of 8-bit channel 0 can be counted by the timer of channel 1 (comparematch count mode). In this case, the timer operates as described below.
16-Bit Count Mode: When bits CKS2 to CKS0 in TCR0 are set to B'100, the timer functions as a
single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8
bits.
• Setting of compare-match flags
 The CMF flag in TCSR0 is set to 1 when a 16-bit compare-match occurs.
 The CMF flag in TCSR1 is set to 1 when a lower 8-bit compare-match occurs.
• Counter clear specification
 If the CCLR1 and CCLR0 bits in TCR0 have been set for counter clear at compare-match,
the 16-bit counter (TCNT0 and TCNT1 together) is cleared when a 16-bit compare-match
occurs. The 16-bit counter (TCNT0 and TCNT1 together) is cleared even if counter clear
by the TMRI0 pin has also been set.
 The settings of the CCLR1 and CCLR0 bits in TCR1 are ignored. The lower 8 bits cannot
be cleared independently.
• Pin output
 Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR0 is in accordance with
the 16-bit compare-match conditions.
 Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR1 is in accordance with
the lower 8-bit compare-match conditions.
Compare-Match Count Mode: When bits CKS2 to CKS0 in TCR1 are B'100, TCNT1 counts
compare-match A’s for channel 0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clearing are in accordance with the
settings for each channel.
Usage Note: If the 16-bit count mode and compare-match count mode are set simultaneously, the
input clock pulses for TCNT0 and TCNT1 are not generated and thus the counters will stop
operating. Simultaneous setting of these two modes should therefore be avoided.
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Section 12 8-Bit Timers
12.4
Interrupt Sources
The TMR0, TMR1, and TMRY 8-bit timers can generate three types of interrupt: compare-match A
and B (CMIA and CMIB), and overflow (OVI). TMRX can generate only an ICIX interrupt. An
interrupt is requested when the corresponding interrupt enable bit is set in TCR or TCSR.
Independent signals are sent to the interrupt controller for each interrupt.
An overview of 8-bit timer interrupt sources is given in tables 12.3 to 12.5.
Table 12.3 TMR0 and TMR1 8-Bit Timer Interrupt Sources
Interrupt source
Description
Interrupt Priority
CMIA
Requested by CMFA
High
CMIB
Requested by CMFB
OVI
Requested by OVF
Low
Table 12.4 TMRX 8-Bit Timer Interrupt Source
Interrupt source
Description
ICIX
Requested by ICF
Table 12.5 TMRY 8-Bit Timer Interrupt Sources
Interrupt source
Description
Interrupt Priority
CMIA
Requested by CMFA
High
CMIB
Requested by CMFB
OVI
Requested by OVF
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Low
Section 12 8-Bit Timers
12.5
8-Bit Timer Application Example
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle,
as shown in figure 12.9. The control bits are set as follows:
• In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared by a
TCORA compare-match.
• In TCSR, bits OS3 to OS0 are set to B'0110, causing 1 output at a TCORA compare-match and
0 output at a TCORB compare-match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 12.9 Pulse Output (Example)
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Section 12 8-Bit Timers
12.6
Usage Notes
Application programmers should note that the following kinds of contention can occur in the 8-bit
timer module.
12.6.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows
this operation.
TCNT write cycle by CPU
T1
T2
T3
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N
H'00
Figure 12.10 Contention between TCNT Write and Clear
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Section 12 8-Bit Timers
12.6.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented. Figure 12.11 shows this operation.
TCNT write cycle by CPU
T1
T2
T3
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.11 Contention between TCNT Write and Increment
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Section 12 8-Bit Timers
12.6.3
Contention between TCOR Write and Compare-Match
During the T2 state of a TCOR write cycle, the TCOR write has priority even if a compare-match
occurs and the compare-match signal is disabled. Figure 12.12 shows this operation.
With TMRX, an ICR input capture contends with a compare-match in the same way as with a
write to TCORC. In this case, the input capture has priority and the compare-match signal is
inhibited.
TCOR write cycle by CPU
T1
T2
T3
φ
Address
TCOR address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare-match signal
Inhibited
Figure 12.12 Contention between TCOR Write and Compare-Match
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Section 12 8-Bit Timers
12.6.4
Contention between Compare-Matches A and B
If compare-matches A and B occur at the same time, the 8-bit timer operates in accordance with
the priorities for the output states set for compare-match A and compare-match B, as shown in
table 12.6.
Table 12.6 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
12.6.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 12.7 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in no. 3 in
table 12.7, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
Erroneous incrementation can also happen when switching between internal and external clocks.
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Section 12 8-Bit Timers
Table 12.7 Switching of Internal Clock and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from low
1
to low*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
CKS bit rewrite
2
Switching from low
2
to high*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
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Section 12 8-Bit Timers
No.
3
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from high
3
to low*
Clock before
switchover
Clock after
switchover
*4
TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
4
Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit rewrite
Notes: 1.
2.
3.
4.
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
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Section 12 8-Bit Timers
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Section 13 Timer Connection
Section 13 Timer Connection
13.1
Overview
The H8/3577 Group and H8/3567 Group allow interconnection between a combination of input
signals, the single free-running timer (FRT) channel, and the three 8-bit timer channels (TMR1,
TMRX, and TMRY). This capability can be used to implement complex functions such as PWM
decoding and clamp waveform output. All the timers are initially set for independent operation.
13.1.1
Features
The features of the timer connection facility are as follows.
• Five input pins and four output pins, all of which can be designated for phase inversion.
Positive logic is assumed for all signals used within the timer connection facility.
• An edge-detection circuit is connected to the input pins, simplifying signal input detection.
• TMRX can be used for PWM input signal decoding.
• TMRX can be used for clamp waveform generation.
• An external clock signal divided by TMR1 can be used as the FRT capture input signal.
• An internal synchronization signal can be generated using the FRT and TMRY.
• A signal generated/modified using an input signal and timer connection can be selected and
output.
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Figure 13.1 Block Diagram of Timer Connection Facility
HFBACKI/
FTCI/TMIX/
TMCI0
CSYNCI/
TMRI1/FTOB
HSYNCI/
TMCI1/FTID
FTIC
Phase
inversion
Phase
inversion
Phase
inversion
Phase
inversion
Phase
inversion
Edge
detection
Edge
detection
Edge
detection
Edge
detection
Edge
detection
IHI
signal
selection
IVI
signal
selection
FRT
input
selection
IVI signal
IHI signal
Read
flag
Read
flag
16-bit FRT
Vertical sync
signal modify
FTOA
ICR +1C
compare-match
ICR
8-bit TMRX
PWM decoding
PDC signal
TMRI
CMA
TMO
CMB
CMB
TMCI
8-bit TMR1 TMO
Clamp waveform generation
CM1C
TMRI
TMCI
TMR1
input
selection
Blanking waveform
generation
SET RES
2f H mask generation
2f H mask/flag
FTIB OCRA +VR, +VF CMA(R)
FTIC ICRD +1M, +2M CMA(F)
compare-match
FTOB
FTID
CM1M CM2M
FTIA
SET
sync
RES
CL2 signal
CL3 signal
CL1 signal
RES
Vertical
sync signal
generation
SET
CLO
signal
selection
CL4 signal
FRT
output
selection
Phase
inversion
Phase
inversion
Phase
inversion
TMOX
TMO1
output
selection
TMRI/TMCI
8-bit TMRY
TMO
IVO signal
Phase
inversion
CL4 generation
IHO
signal
selection
TMIY
signal
selection
IVG
signal
IVO
signal
selection
CLAMP0/
FTIC/
TMO0
HSYNCO/
TMO1/
TMOX
CBLANK
IHG signal
VSYNCO/
FTOA
13.1.2
VFBACKI/
FTIB/TMRI0
VSYNCI/
FTIA/TMIY
Section 13 Timer Connection
Block Diagram
Figure 13.1 shows a block diagram of the timer connection facility.
Section 13 Timer Connection
13.1.3
Input and Output Pins
Table 13.1 lists the timer connection input and output pins.
Table 13.1 Timer Connection Input and Output Pins
Name
Abbreviation
Input/
Output
Vertical synchronization
signal input pin
VSYNCI
Input
Vertical synchronization signal
input pin
or FTIA input pin/TMIY input pin
Horizontal synchronization
signal input pin
HSYNCI
Input
Horizontal synchronization signal
input pin
or FTID input pin/TMCI1 input pin
Composite synchronization
signal input pin
CSYNCI
Input
Composite synchronization signal
input pin
or TMRI1 input pin/FTOB output
pin
Spare vertical synchronization
signal input pin
VFBACKI
Input
Spare vertical synchronization
signal input pin
or FTIB input pin/TMRI0 input pin
Spare horizontal
synchronization signal input
pin
HFBACKI
Input
Spare horizontal synchronization
signal input pin
or FTCI input pin/TMCI0 input
pin/TMIX input pin
Vertical synchronization
signal output pin
VSYNCO
Output
Vertical synchronization signal
output pin
or FTOA output pin
Horizontal synchronization
signal output pin
HSYNCO
Output
Horizontal synchronization signal
output pin
or TMO1 output pin/TMOX output
pin
Clamp waveform output pin
CLAMPO
Output
Clamp waveform output pin
or TMO0 output pin/FTIC input pin
Blanking waveform output pin
CBLANK
Output
Blanking waveform output pin
Function
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Section 13 Timer Connection
13.1.4
Register Configuration
Table 13.2 lists the timer connection registers. Timer connection registers can only be accessed
when the HIE bit in SYSCR is 0.
Table 13.2 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address
Timer connection register I
TCONRI
R/W
H'00
H'FFFC
Timer connection register O
TCONRO
R/W
H'00
H'FFFD
Timer connection register S
TCONRS
R/W
H'00
H'FFFE
Edge sense register
SEDGR
1
R/(W)*
2
H'00*
H'FFFF
Module stop control register
MSTPRH
R/W
H'3F
H'FF86
MSTPRL
R/W
H'FF
H'FF87
Notes: 1. Bits 7 to 2: Only 0 can be written to clear the flags.
2. Bits 1 and 0: Undefined (reflect the pin states).
13.2
Register Descriptions
13.2.1
Timer Connection Register I (TCONRI)
Bit
7
6
SIMOD1 SIMOD0
5
4
3
2
1
0
SCONE
ICST
HFINV
VFINV
HIINV
VIINV
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCONRI is an 8-bit readable/writable register that controls connection between timers, the signal
source for synchronization signal input, phase inversion, etc.
TCONR1 is initialized to H'00 by a reset and in hardware standby mode.
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Section 13 Timer Connection
Bits 7 and 6—Input Synchronization Mode Select 1 and 0 (SIMOD1, SIMOD0): These bits
select the signal source of the IHI and IVI signals.
Bit 7
Bit 6
SIMOD1
SIMOD0
Mode
0
0
No signal
1
S-on-G mode
1
Description
(Initial value)
IHI Signal
IVI Signal
HFBACKI input
VFBACKI input
CSYNCI input
PDC input
0
Composite mode
HSYNCI input
PDC input
1
Separate mode
HSYNCI input
VSYNCI input
Bit 5—Synchronization Signal Connection Enable (SCONE): Selects the signal source of the
FRT FTI input and the TMR1 TMCI1/TMRI1 input.
Bit 5
Description
SCONE
Mode
FTIA
FTIB
FTIC
FTID
TMCI1
TMRI1
0
Normal connection (Initial value) FTIA
input
FTIB
input
FTIC
input
FTID
input
TMCI1
input
TMRI1
input
1
Synchronization signal
connection mode
TMO1
signal
VFBACKI IHI
input
signal
IHI
signal
IVI
inverse
signal
IVI
signal
Bit 4—Input Capture Start Bit (ICST): The TMRX external reset input (TMRIX) is connected
to the IHI signal. TMRX has input capture registers (TICR, TICRR, and TICRF). TICRR and
TICRF can measure the width of a short pulse by means of a single capture operation under the
control of the ICST bit. When a rising edge followed by a falling edge is detected on TMRIX after
the ICST bit is set to 1, the contents of TCNT at those points are captured into TICRR and TICRF,
respectively, and the ICST bit is cleared to 0.
Bit 4
ICST
Description
0
The TICRR and TICRF input capture functions are stopped
(Initial value)
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
1
The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
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Section 13 Timer Connection
Bits 3 to 0—Input Synchronization Signal Inversion (HFINV, VFINV, HIINV, VIINV):
These bits select inversion of the input phase of the spare horizontal synchronization signal
(HFBACKI), the spare vertical synchronization signal (VFBACKI), the horizontal
synchronization signal and composite synchronization signal (HSYNCI, CSYNCI), and the
vertical synchronization signal (VSYNCI).
Bit 3
HFINV
Description
0
The HFBACKI pin state is used directly as the HFBACKI input
1
The HFBACKI pin state is inverted before use as the HFBACKI input
(Initial value)
Bit 2
VFINV
Description
0
The VFBACKI pin state is used directly as the VFBACKI input
1
The VFBACKI pin state is inverted before use as the VFBACKI input
(Initial value)
Bit 1
HIINV
Description
0
The HSYNCI and CSYNCI pin states are used directly as the HSYNCI and CSYNCI
inputs
(Initial value)
1
The HSYNCI and CSYNCI pin states are inverted before use as the HSYNCI and
CSYNCI inputs
Bit 0
VIINV
Description
0
The VSYNCI pin state is used directly as the VSYNCI input
1
The VSYNCI pin state is inverted before use as the VSYNCI input
13.2.2
(Initial value)
Timer Connection Register O (TCONRO)
Bit
7
6
5
4
3
2
HOE
VOE
CLOE
CBOE
HOINV
VOINV
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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1
0
CLOINV CBOINV
Section 13 Timer Connection
TCONRO is an 8-bit readable/writable register that controls output signal output, phase inversion,
etc.
TCONRO is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 4—Output Enable (HOE, VOE, CLOE, CBOE): These bits control enabling/disabling
of horizontal synchronization signal (HSYNCO), vertical synchronization signal (VSYNCO),
clamp waveform (CLAMPO), and blanking waveform (CBLANK) output. When output is
disabled, the state of the relevant pin is determined by the port DR and DDR, FRT, TMR, and
PWM settings.
Output enabling/disabling control does not affect the port, FRT, or TMR input functions, but some
FRT and TMR input signal sources are determined by the SCONE bit in TCONRI.
Bit 7
HOE
Description
0
The P67/TMO1/TMOX/HSYNCO pin functions as the P67/TMO1/TMOX pin
(Initial value)
1
The P67/TMO1/TMOX/HSYNCO pin functions as the HSYNCO pin
Bit 6
VOE
Description
0
The P61/FTOA/VSYNCO pin functions as the P61/FTOA pin
1
The P61/FTOA/VSYNCO pin functions as the VSYNCO pin
(Initial value)
Bit 5
CLOE
Description
0
The P64/FTIC/TMO0/CLAMPO pin functions as the P64/FTIC/TMO0 pin
1
The P64/FTIC/TMO0/CLAMPO pin functions as the CLAMPO pin
(Initial value)
Bit 4
CBOE
Description
0
[H8/3577 Group] P27/PW15/CBLANK pin functions as the P27/PW15 pin
[H8/3567 Group] P15/PW5/CBLANK pin functions as the P15/PW5 pin
1
(Initial value)
[H8/3577 Group] P27/PW15/CBLANK pin functions as the CBLANK pin
[H8/3567 Group] P15/PW5/CBLANK pin functions as the CBLANK pin
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Section 13 Timer Connection
Bits 3 to 0—Output Synchronization Signal Inversion (HOINV, VOINV, CLOINV,
CBOINV): These bits select inversion of the output phase of the horizontal synchronization signal
(HSYNCO), the vertical synchronization signal (VSYNCO), the clamp waveform (CLAMPO),
and the blank waveform (CBLANK).
Bit 3
HOINV
Description
0
The IHO signal is used directly as the HSYNCO output
1
The IHO signal is inverted before use as the HSYNCO output
(Initial value)
Bit 2
VOINV
Description
0
The IVO signal is used directly as the VSYNCO output
1
The IVO signal is inverted before use as the VSYNCO output
(Initial value)
Bit 1
CLOINV
Description
0
The CLO signal (CL1, CL2, CL3, or CL4 signal) is used directly as the
CLAMPO output
1
The CLO signal (CL1, CL2, CL3, or CL4 signal) is inverted before use as
the CLAMPO output
(Initial value)
Bit 0
CBOINV
Description
0
The CBLANK signal is used directly as the CBLANK output
1
The CBLANK signal is inverted before use as the CBLANK output
13.2.3
(Initial value)
Timer Connection Register S (TCONRS)
Bit
7
6
5
4
3
2
1
0
TMRX/Y ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 13 Timer Connection
TCONRS is an 8-bit readable/writable register that selects 8-bit timer TMRX/TMRY access and
the synchronization signal output signal source and generation method.
TCONRS is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—TMRX/TMRY Access Select (TMRX/Y): The TMRX and TMRY registers can only be
accessed when the HIE bit in SYSCR is cleared to 0. In the H8/3577 Group and H8/3567 Group,
some of the TMRX registers and the TMRY registers are assigned to the same memory space
addresses (H'FFF0 to H'FFF5), and the TMRX/Y bit determines which registers are accessed.
Bit 7
TMRX/Y
Description
0
The TMRX registers are accessed at addresses H'FFF0 to H'FFF5
1
The TMRY registers are accessed at addresses H'FFF0 to H'FFF5
(Initial value)
Bit 6—Internal Synchronization Signal Select (ISGENE): Selects internal synchronization
signals (IHG, IVG, and CL4 signals) as the signal sources for the IHO, IVO, and CLO signals.
Bits 5 and 4—Horizontal Synchronization Output Mode Select 1 and 0 (HOMOD1,
HOMOD0): These bits select the signal source and generation method for the IHO signal.
Bit 6
Bit 5
Bit 4
ISGENE
VOMOD1
VOMOD0
Description
0
0
0
The IHI signal (without 2fH modification)
is selected
1
(Initial value)
1
The IHI signal (with 2fH modification) is selected
0
The CL1 signal is selected
1
1
0
0
The IHG signal is selected
1
1
0
1
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Section 13 Timer Connection
Bits 3 and 2—Vertical Synchronization Output Mode Select 1 and 0 (VOMOD1, VOMOD0):
These bits select the signal source and generation method for the IVO signal.
Bit 6
Bit 3
Bit 2
ISGENE
VOMOD1
VOMOD0
Description
0
0
0
The IVI signal (without fall modification or IHI
synchronization) is selected
(Initial value)
1
The IVI signal (without fall modification, with IHI
synchronization) is selected
0
The IVI signal (with fall modification, without IHI
synchronization) is selected
1
The IVI signal (with fall modification and IHI
synchronization) is selected
0
The IVG signal is selected
1
1
0
1
1
0
1
Bits 1 and 0—Clamp Waveform Mode Select 1 and 0 (CLMOD1, CLMOD0): These bits
select the signal source for the CLO signal (clamp waveform).
Bit 6
Bit 1
Bit 0
ISGENE
CLMOD1
CLMOD2
Description
0
0
0
The CL1 signal is selected
1
The CL2 signal is selected
0
The CL3 signal is selected
1
1
1
0
0
The CL4 signal is selected
1
1
0
1
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(Initial value)
Section 13 Timer Connection
13.2.4
Edge Sense Register (SEDGR)
Bit
7
6
5
4
3
2
1
0
VEDG
HEDG
CEDG
HFEDG
VFEDG
PREQF
Initial value
0
0
0
0
0
0
IHI
2
—*
IVI
2
—*
Read/Write
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
1
R/(W)*
R/(W)*
R
R
1
Notes: 1. Only 0 can be written, to clear the flags.
2. The initial value is undefined since it depends on the pin states.
SEDGR is an 8-bit readable/writable register used to detect a rising edge on the timer connection
input pins and the occurrence of 2fH modification, and to determine the phase of the IVI and IHI
signals.
The upper 6 bits of SEDGR are initialized to 0 by a reset and in hardware standby mode. The
initial value of the lower 2 bits is undefined, since it depends on the pin states.
Bit 7—VSYNCI Edge (VEDG): Detects a rising edge on the VSYNCI pin.
Bit 7
VEDG
Description
0
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
(Initial value)
Bit 6—HSYNCI Edge (HEDG): Detects a rising edge on the HSYNCI pin.
Bit 6
HEDG
Description
0
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
(Initial value)
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Section 13 Timer Connection
Bit 5—CSYNCI Edge (CEDG): Detects a rising edge on the CSYNCI pin.
Bit 5
CEDG
Description
0
[Clearing condition]
(Initial value)
When 0 is written in CEDG after reading CEDG = 1
1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
Bit 4—HFBACKI Edge (HFEDG): Detects a rising edge on the HFBACKI pin.
Bit 4
HFEDG
Description
0
[Clearing condition]
(Initial value)
When 0 is written in HFEDG after reading HFEDG = 1
1
[Setting condition]
When a rising edge is detected on the HFBACKI pin
Bit 3—VFBACKI Edge (VFEDG): Detects a rising edge on the VFBACKI pin.
Bit 3
VFEDG
Description
0
[Clearing condition]
(Initial value)
When 0 is written in VFEDG after reading VFEDG = 1
1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
Bit 2—Pre-Equalization Flag (PREQF): Detects the occurrence of an IHI signal 2fH
modification condition. The generation of a falling/rising edge in the IHI signal during a mask
interval is expressed as the occurrence of a 2fH modification condition. For details, see section
13.3.4, IHI Signal 2fH Modification.
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Section 13 Timer Connection
Bit 2
PREQF
Description
0
[Clearing condition]
(Initial value)
When 0 is written in PREQF after reading PREQF = 1
1
[Setting condition]
When an IHI signal 2fH modification condition is detected
Bit 1—IHI Signal Level (IHI): Indicates the current level of the IHI signal. Signal source and
phase inversion selection for the IHI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IHI signal at positive
phase by modifying TCONRI.
Bit 1
IHI
Description
0
The IHI signal is low
1
The IHI signal is high
Bit 0—IVI Signal Level (IVI): Indicates the current level of the IVI signal. Signal source and
phase inversion selection for the IVI signal depends on the contents of TCONRI. Read this bit to
determine whether the input signal is positive or negative, then maintain the IVI signal at positive
phase by modifying TCONRI.
Bit 0
IVI
Description
0
The IVI signal is low
1
The IVI signal is high
13.2.5
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
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Section 13 Timer Connection
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP13, MSTP12, and MSTP8 bits are set to 1, the 16-bit free-running timer, 8-bit
timer channels 0 and 1 and channels X and Y, and timer connection, respectively, halt and enter
module stop mode at the end of the bus cycle. See section 21.5, Module Stop Mode, for details.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 5—Module Stop (MSTP13): Specifies FRT module stop mode.
MSTPCRH
Bit 5
MSTP13
Description
0
FRT module stop mode is cleared
1
FRT module stop mode is set
(Initial value)
MSTPCRH Bit 4—Module Stop (MSTP12): Specifies 8-bit timer channel 0 and 1 module stop
mode.
MSTPCRH
Bit 4
MSTP12
Description
0
8-bit timer channel 0 and 1 module stop mode is cleared
1
8-bit timer channel 0 and 1 module stop mode is set
(Initial value)
MSTPCRH Bit 0—Module Stop (MSTP8): Specifies 8-bit timer channel X and Y and timer
connection module stop mode.
MSTPCRH
Bit 0
MSTP8
Description
0
8-bit timer channel X and Y and timer connection module stop mode is cleared
1
8-bit timer channel X and Y and timer connection module stop mode is set
(Initial value)
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Section 13 Timer Connection
13.3
Operation
13.3.1
PWM Decoding (PDC Signal Generation)
The timer connection facility and TMRX can be used to decode a PWM signal in which 0 and 1
are represented by the pulse width. To do this, a signal in which a rising edge is generated at
regular intervals must be selected as the IHI signal.
The timer counter (TCNT) in TMRX is set to count the internal clock pulses and to be cleared on
the rising edge of the external reset signal (IHI signal). The value to be used as the threshold for
deciding the pulse width is written in TCORB. The PWM decoder contains a delay latch which
uses the IHI signal as data and compare-match signal B (CMB) as a clock, and the state of the IHI
signal (the result of the pulse width decision) at the compare-match signal B timing after TCNT is
reset by the rise of the IHI signal is output as the PDC signal. The pulse width setting using
TICRR and TICRF of TMRX can be used to determine the pulse width decision threshold.
Examples of TCR and TCORB in TMRX settings are shown in tables 13.3 and 13.4, and the
timing chart is shown in figure 13.2.
Table 13.3 Examples of TCR Settings
Bit(s)
Abbreviation
Contents
Description
7
CMIEB
0
6
CMIEA
0
Interrupts due to compare-match and overflow
are disabled
5
OVIE
0
4 and 3
CCLR1, CCLR0
11
TCNT is cleared by the rising edge of the
external reset signal (IHI signal)
2 to 0
CKS2 to CKS0
001
Incremented on internal clock: φ
Table 13.4 Examples of TCORB (Pulse Width Threshold) Settings
φ:10 MHz
φ: 12 MHz
φ: 16 MHz
φ: 20 MHz
H'07
0.8 µs
0.67 µs
0.5 µs
0.4 µs
H'0F
1.6 µs
1.33 µs
1 µs
0.8 µs
H'1F
3.2 µs
2.67 µs
2 µs
1.6 µs
H'3F
6.4 µs
5.33 µs
4 µs
3.2 µs
H'7F
12.8 µs
10.67 µs
8 µs
6.4 µs
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Section 13 Timer Connection
Judgment of IHI signal state
in compare-match
IHI signal
PDC signal
TCNT
TCORB
(threshold)
Counter reset
by IHI signal
Counter clear
upon TCNT
overflow
The IHI signal state is
not judged in the 2nd
compare-match.
Figure 13.2 Timing Chart for PWM Decoding
13.3.2
Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)
The timer connection facility and TMRX can be used to generate signals with different duty cycles
and rising/falling edges (clamp waveforms) in synchronization with the input signal (IHI signal).
Three clamp waveforms can be generated: the CL1, CL2, and CL3 signals. In addition, the CL4
signal can be generated using TMRY.
The CL1 signal rises simultaneously with the rise of the IHI signal, and when the CL1 signal is
high, the CL2 signal rises simultaneously with the fall of the IHI signal. The fall of both the CL1
and the CL2 signal can be specified by TCORA.
The rise of the CL3 signal can be specified as simultaneous with the sampling of the fall of the IHI
signal using the system clock, and the fall of the CL3 signal can be specified by TCORC. The CL3
signal falls at the rise of the IHI signal.
TCNT in TMRX is set to count internal clock pulses and to be cleared on the rising edge of the
external reset signal (IHI signal).
The value to be used as the CL1 signal pulse width is written in TCORA. Write a value of H'02 or
more in TCORA when internal clock φ is selected as the TMRX counter clock, and a value or
H'01 or more when φ/2 is selected. When internal clock φ is selected, the CL1 signal pulse width is
(TCORA set value + 3 ± 0.5). When the CL2 signal is used, the setting must be made so that this
pulse width is greater than the IHI signal pulse width.
The value to be used as the CL3 signal pulse width is written in TCORC. The TICR register in
TMRX captures the value of TCNT at the inverse of the external reset signal edge (in this case, the
falling edge of the IHI signal). The timing of the fall of the CL3 signal is determined by the sum of
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Section 13 Timer Connection
the contents of TICR and TCORC. Caution is required if the rising edge of the IHI signal precedes
the fall timing set by the contents of TCORC, since the IHI signal will cause the CL3 signal to fall.
Examples of TMRX TCR settings are the same as those in table 13.3. The clamp waveform timing
charts are shown in figures 13.3 and 13.4.
Since the rise of the CL1 and CL2 signals is synchronized with the edge of the IHI signal, and their
fall is synchronized with the system clock, the pulse width variation is equivalent to the resolution
of the system clock.
Both the rise and the fall of the CL3 signal are synchronized with the system clock and the pulse
width is fixed, but there is a variation in the phase relationship with the IHI signal equivalent to
the resolution of the system clock.
IHI signal
CL1 signal
CL2 signal
TCNT
TCORA
Figure 13.3 Timing Chart for Clamp Waveform Generation (CL1 and CL2 Signals)
IHI signal
CL3 signal
TCNT
TICR+TCORC
TICR
Figure 13.4 Timing Chart for Clamp Waveform Generation (CL3 Signal)
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Section 13 Timer Connection
13.3.3
Measurement of 8-Bit Timer Divided Waveform Period
The timer connection facility, TMR1, and the free-running timer (FRT) can be used to measure the
period of an IHI signal divided waveform. Since TMR1 can be cleared by a rising edge of the IVI
signal, the rise and fall of the IHI signal divided waveform can be virtually synchronized with the
IVI signal. This enables period measurement to be carried out efficiently.
To measure the period of an IHI signal divided waveform, TCNT in TMR1 is set to count the
external clock (IHI signal) pulses and to be cleared on the rising edge of the external reset signal
(IVI signal). The value to be used as the division factor is written in TCORA, and the TMO output
method is specified by the OS bits in TCSR. Examples of TMR1 TCR and TCSR settings are
shown in table 13.5, and the timing chart for measurement of the IVI signal and IHI signal divided
waveform periods is shown in figure 13.5. The period of the IHI signal divided waveform is given
by (ICRD(3) – ICRD(2)) × the resolution.
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Section 13 Timer Connection
Table 13.5 Examples of TCR and TCSR Settings
Register
Bit(s)
Abbreviation
Contents
Description
TCR in TMR1
7
CMIEB
0
6
CMIEA
0
Interrupts due to compare-match
and overflow are disabled
5
OVIE
0
4, 3
CCLR1, CCLR0
11
TCNT is cleared by the rising edge
of the external reset signal (IVI
signal)
2 to 0
CKS2 to CKS0
101
TCNT is incremented on the rising
edge of the external clock (IHI
signal)
3 to 0
OS3 to OS0
0011
Not changed by compare-match B;
output inverted by compare-match A
(toggle output): division by 512
TCSR in TMR1
1001
TCR in FRT
6
IEDGB
0/1
or
when TCORB < TCORA, 1 output
on compare-match B, and 0 output
on compare-match A: division by
256
0: FRC value is transferred to ICRB
on falling edge of input capture
input B (IHI divided signal
waveform)
1: FRC value is transferred to ICRB
on rising edge of input capture
input B (IHI divided signal
waveform)
TCSR in FRT
1, 0
CKS1, CKS0
01
FRC is incremented on internal
clock: φ/8
0
CCLRA
0
FRC clearing is disabled
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Section 13 Timer Connection
IVI signal
IHI signal
divided
waveform
ICRB(4)
ICRB(3)
ICRB(2)
ICRB(1)
FRC
ICRB
Figure 13.5 Timing Chart for Measurement of IVI Signal and
IHI Signal Divided Waveform Periods
13.3.4
IHI Signal and 2fH Modification
By using the timer connection FRT, even if there is a part of the IHI signal with twice the
frequency, this can be eliminated. In order for this function to operate properly, the duty cycle of
the IHI signal must be approximately 30% or less, or approximately 70% or above.
The 8-bit OCRDM contents or twice the OCRDM contents can be added automatically to the data
captured in ICRD in the FRT, and compare-matches generated at these points. The interval
between the two compare-matches is called a mask interval. A value equivalent to approximately
1/3 the IHI signal period is written in OCRDM. ICRD is set so that capture is performed on the
rise of the IHI signal.
Since the IHI signal supplied to the IHO signal selection circuit is normally set on the rise of the
IHI signal and reset on the fall, its waveform is the same as that of the original IHI signal. When
2fH modification is selected, IHI signal edge detection is disabled during mask intervals. Capture
is also disabled during these intervals.
Examples of FRT TCR settings are shown in table 13.6, and the 2fH modification timing chart is
shown in figure 13.6.
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Section 13 Timer Connection
Table 13.6 Examples of TCR, TCSR, TCOR, and OCRDM Settings
Register
Bit(s)
Abbreviation
Contents
Description
TCR in FRT
4
IEDGD
1
FRC value is transferred to ICRD on
the rising edge of input capture input
D (IHI signal)
1, 0
CKS1, CKS0
01
FRC is incremented on internal clock:
φ/8
TCSR in FRT
0
CCLRA
0
FRC clearing is disabled
TCOR in FRT
7
ICRDMS
1
ICRD is set to the operating mode in
which OCRDM is used
OCRDM7 to
OCRDM0
H'01 to H'FF Specifies the period during which
ICRD operation is masked
OCRDM in FRT 7 to 0
IHI signal
(without 2fH
modification)
IHI signal
(with 2fH
modification)
Mask interval
ICRD + OCRDM × 2
ICRD + OCRDM
FRC
ICRD
Figure 13.6 2fH Modification Timing Chart
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Section 13 Timer Connection
13.3.5
IVI Signal Fall Modification and IHI Synchronization
By using the timer connection TMR1, the fall of the IVI signal can be shifted backward by the
specified number of IHI signal waveforms. Also, the fall of the IVI signal can be synchronized
with the rise of the IHI signal.
To perform 8-bit timer divided waveform period measurement, TCNT in TMR1 is set to count
external clock (IHI signal) pulses, and to be cleared on the rising edge of the external reset signal
(inverse of the IVI signal). The number of IHI signal pulses until the fall of the IVI signal is
written in TCORB.
Since the IVI signal supplied to the IVO signal selection circuit is normally set on the rise of the
IVI signal and reset on the fall, its waveform is the same as that of the original IVI signal. When
fall modification is selected, a reset is performed on a TMR1 TCORB compare-match.
The fall of the waveform generated in this way can be synchronized with the rise of the IHI signal,
regardless of whether or not fall modification is selected.
Examples of TMR1 TCORB, TCR, and TCSR settings are shown in table 13.7, and the fall
modification/IHI synchronization timing chart is shown in figure 13.7.
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Section 13 Timer Connection
Table 13.7 Examples of TCORB, TCR, and TCSR Settings
Register
Bit(s)
Abbreviation
Contents
Description
TCR in
TMR1
7
CMIEB
0
6
CMIEA
0
Interrupts due to compare-match and
overflow are disabled
5
OVIE
0
4, 3
CCLR1,
CCLR0
11
TCNT is cleared by the rising edge of the
external reset signal (inverse of the IVI
signal)
2 to 0
CKS2 to CKS0
101
TCNT is incremented on the rising edge
of the external clock (IHI signal)
3 to 0
OS3 to OS0
0011
Not changed by compare-match B;
output inverted by compare-match A
(toggle output)
TCSR in
TMR1
1001
TOCRB in TMR1
H'03
(example)
or
when TCORB < TCORA, 1 output on
compare-match B, 0 output on comparematch A
Compare-match on the 4th (example)
rise of the IHI signal after the rise of the
inverse of the IVI signal
IHI signal
IVI signal (PDC signal)
IVO signal
(without fall modification,
with IHI synchronization)
IVO signal
(with fall modification,
without IHI synchronization)
IVO signal
(with fall modification
and IHI synchronization)
TCNT
0
1
2
3
4
5
TCNT = TCORB (3)
Figure 13.7 Fall Modification/IHI Synchronization Timing Chart
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Section 13 Timer Connection
13.3.6
Internal Synchronization Signal Generation (IHG/IVG/CL4 Signal Generation)
By using the timer connection FRT and TMRY, it is possible to automatically generate internal
signals (IHG and IVG signals) corresponding to the IHI and IVI signals. As the IHG signal is
synchronized with the rise of the IVG signal, the IHG signal period must be made a divisor of the
IVG signal period in order to keep it constant. In addition, the CL4 signal can be generated in
synchronization with the IHG signal.
The contents of OCRA in the FRT are updated by the automatic addition of the contents of
OCRAR or OCRAF, alternately, each time a compare-match occurs. A value corresponding to the
0 interval of the IVG signal is written in OCRAR, and a value corresponding to the 1 interval of
the IVG signal is written in OCRAF. The IVG signal is set by a compare-match after an OCRAR
addition, and reset by a compare-match after an OCRAF addition.
The IHG signal is the TMRY 8-bit timer output. TMRY is set to count internal clock pulses, and
to be cleared on TCORA compare-match, to fix the period and set the timer output. TCORB is set
so as to reset the timer output. The IVG signal is connected as the TMRY reset input (TMRI), and
the rise of the IVG signal can be treated in the same way as a TCORA compare-match.
The CL4 signal is a waveform that rises within one system clock period after the fall of the IHG
signal, and has a 1 interval of 6 system clock periods.
Examples of settings of TCORA, TCORB, TCR, and TCSR in TMRY, and OCRAR, OCRAF,
and TCR in the FRT, are shown in table 13.8, and the IHG signal/IVG signal timing chart is
shown in figure 13.8.
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Section 13 Timer Connection
Table 13.8 Examples of OCRAR, OCRAF, TOCR, TCORA, TCORB, TCR, and TCSR
Settings
Register
Bit(s)
Abbreviation
Contents
Description
TCR in
TMRY
7
CMIEB
0
6
CMIEA
0
Interrupts due to compare-match and
overflow are disabled
5
OVIE
0
4, 3
CCLR1,
CCLR0
01
2 to 0
CKS2 to CKS0 001
TCNT is incremented on internal clock:
φ/4
3 to 0
OS3 to OS0
0110
0 output on compare-match B
1 output on compare-match A
TOCRA in
TMRY
H'3F
(example)
IHG signal period = φ × 256
TOCRB in
TMRY
H'03
(example)
IHG signal 1 interval = φ × 16
01
FRC is incremented on internal clock: φ/8
OCRAR in FRT
H'7FEF
(example)
IVG signal 0
interval =
φ × 262016
OCRAF in FRT
H'000F
(example)
IVG signal 1
interval = φ × 128
1
OCRA is set to the operating mode in
which OCRAR and OCRAF are used
TCSR in
TMRY
TCR in FRT
TOCR in FRT
1, 0
6
CKS1,
CKS0
OCRAMS
TCNT is cleared by compare-match A
IVG signal period =
φ × 262144 (1024
times IHG signal)
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Section 13 Timer Connection
IVG signal
OCRA (1) =
OCRA (0) +
OCRAF
OCRA (2) =
OCRA (1) +
OCRAR
OCRA (3) =
OCRA (2) +
OCRAF
OCRA (4) =
OCRA (3) +
OCRAR
OCRA
FRC
6 system clocks
6 system clocks
6 system clocks
CL4
signal
IHG
signal
TCORA
TCORB
TCNT
Figure 13.8 IVG Signal/IHG Signal/CL4 Signal Timing Chart
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Section 13 Timer Connection
13.3.7
HSYNCO Output
With the HSYNCO output, the meaning of the signal source to be selected and use or non-use of
modification varies according to the IHI signal source and the waveform required by external
circuitry. The meaning of the HSYNCO output in each mode is shown in table 13.9.
Table 13.9 Meaning of HSYNCO Output in Each Mode
Mode
IHI Signal
IHO Signal
Meaning of IHO Signal
No signal
HFBACKI
input
IHI signal (without
2fH modification)
HFBACKI input is output directly
IHI signal (with 2fH
modification)
Meaningless unless there is a double-frequency
part in the HFBACKI input
CL1 signal
HFBACKI input 1 interval is changed before output
IHG signal
Internal synchronization signal is output
IHI signal (without
2fH modification)
CSYNCI input (composite synchronization signal)
is output directly
IHI signal (with 2fH
modification)
Double-frequency part of CSYNCI input (composite
synchronization signal) is eliminated before output
CL1 signal
CSYNCI input (composite synchronization signal)
horizontal synchronization signal part is separated
before output
IHG signal
Internal synchronization signal is output
IHI signal (without
2fH modification)
HSYNCI input (composite synchronization signal)
is output directly
IHI signal (with 2fH
modification)
Double-frequency part of HSYNCI input (composite
synchronization signal) is eliminated before output
CL1 signal
HSYNCI input (composite synchronization signal)
horizontal synchronization signal part is separated
before output
IHG signal
Internal synchronization signal is output
IHI signal (without
2fH modification)
HSYNCI input (horizontal synchronization signal) is
output directly
IHI signal (with 2fH
modification)
Meaningless unless there is a double-frequency
part in the HSYNCI input (horizontal
synchronization signal)
CL1 signal
HSYNCI input (horizontal synchronization signal) 1
interval is changed before output
IHG signal
Internal synchronization signal is output
S-on-G
mode
CSYNCI
input
Composite HSYNCI
mode
input
Separate
mode
HSYNCI
input
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Section 13 Timer Connection
13.3.8
VSYNCO Output
With the VSYNCO output, the meaning of the signal source to be selected and use or non-use of
modification varies according to the IVI signal source and the waveform required by external
circuitry. The meaning of the VSYNCO output in each mode is shown in table 13.10.
Table 13.10 Meaning of VSYNCO Output in Each Mode
Mode
IVI Signal
IVO Signal
Meaning of IVO Signal
No signal
VFBACKI
input
IVI signal (without fall
modification or IHI
synchronization)
VFBACKI input is output directly
IVI signal (without fall
modification, with IHI
synchronization)
Meaningless unless VFBACKI input is
synchronized with HFBACKI input
IVI signal (with fall
modification, without IHI
synchronization)
VFBACKI input fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
VFBACKI input fall is modified and signal is
synchronized with HFBACKI input before
output
IVG signal
Internal synchronization signal is output
IVI signal (without fall
modification or IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated
before output
IVI signal (without fall
modification, with IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated, and
signal is synchronized with CSYNCI/HSYNCI
input before output
IVI signal (with fall
modification, without IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated, and
fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
CSYNCI/HSYNCI input (composite
synchronization signal) vertical
synchronization signal part is separated, fall is
modified, and signal is synchronized with
CSYNCI/HSYNCI input before output
IVG signal
Internal synchronization signal is output
S-on-G
PDC signal
mode or
composite
mode
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Section 13 Timer Connection
Mode
IVI Signal
IVO Signal
Meaning of IVO Signal
Separate
mode
VSYNCI
input
IVI signal (without fall
modification or IHI
synchronization)
VSYNCI input (vertical synchronization signal)
is output directly
IVI signal (without fall
modification, with IHI
synchronization)
Meaningless unless VSYNCI input (vertical
synchronization signal) is synchronized with
HSYNCI input (horizontal synchronization
signal)
IVI signal (with fall
modification, without IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified before output
IVI signal (with fall
modification and IHI
synchronization)
VSYNCI input (vertical synchronization signal)
fall is modified and signal is synchronized with
HSYNCI input (horizontal synchronization
signal) before output
IVG signal
Internal synchronization signal is output
13.3.9
CBLANK Output
Using the signals generated/selected with timer connection, it is possible to generate a waveform
based on the composite synchronization signal (blanking waveform).
One kind of blanking waveform is generated by combining HFBACKI and VFBACKI inputs,
with the phase polarity made positive by means of bits HFINV and VFINV in TCONRI, with the
IVO signal.
The composition logic is shown in figure 13.9.
HFBACKI input (positive)
VFBACKI input (positive)
Falling edge sensing
Reset
Rising edge sensing
Set
Q
CBLANK signal
(positive)
IVO signal (positive)
Figure 13.9 CBLANK Output Waveform Generation
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Section 14 Watchdog Timer (WDT)
Section 14 Watchdog Timer (WDT)
14.1
Overview
The H8/3577 Group and H8/3567 Group have an on-chip watchdog timer (WDT0). The WDT
outputs an overflow signal if a system crash prevents the CPU from writing to the timer counter,
allowing it to overflow. At the same time, the WDT can also generate an internal reset signal or
internal NMI interrupt signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer mode, an interval timer interrupt is generated each time the counter overflows.
14.1.1
Features
• Switchable between watchdog timer mode and interval timer mode
 WOVI interrupt generation in interval timer mode
• Internal reset or internal interrupt generated when the timer counter overflows
 Choice of internal reset or NMI interrupt generation in watchdog timer mode
• Choice of 8 counter input clocks
 Maximum WDT interval: system clock period × 131072 × 256
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Section 14 Watchdog Timer (WDT)
14.1.2
Block Diagram
Figure 14.1 shows block diagram of WDT0.
Internal NMI
interrupt request
signal
Interrupt
control
Overflow
Clock
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Clock
select
Reset
control
Internal reset
signal*
Internal clock
source
TCNT
TCSR
Module bus
Bus
interface
WDT
Legend:
TCSR: Timer control/status register
TCNT:
Timer counter
Note: * The internal reset signal can be generated by means of a register setting.
Figure 14.1 Block Diagram of WDT0
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Internal bus
WOVI
(interrupt request
signal)
Section 14 Watchdog Timer (WDT)
14.1.3
Register Configuration
The WDT has four registers, as summarized in table 14.1. These registers control clock selection,
WDT mode switching, the reset signal, etc.
Table 14.1 WDT Registers
Address
Channel
Name
0
Common
Abbreviation R/W
Initial Value
Write*
H'00
H'FFA8
H'FFA8
1
Read
Timer control/status
register 0
TCSR0
R/(W)*
Timer counter 0
TCNT0
R/W
H'00
H'FFA8
H'FFA9
System control
register
SYSCR
R/W
H'09
H'FFC4
H'FFC4
2
Notes: 1. For details of write operations, see section 14.2.4, Notes on Register Access.
2. Only 0 can be written in bit 7, to clear the flag.
14.2
Register Descriptions
14.2.1
Timer Counter (TCNT)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TCNT is an 8-bit readable/writable* up-counter.
When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal
clock source selected by bits CKS2 to CKS0 in TCSR. When the TCNT value overflows (changes
from H'FF to H'00), the OVF flag in TCSR is set to 1.
TCNT is initialized to H'00 by a reset, in hardware standby mode, or when the TME bit is cleared
to 0. It is not initialized in software standby mode.
Note: * The method of writing to TCNT is more complicated than for most other registers, to
prevent accidental overwriting. For details see section 14.2.4, Notes on Register
Access.
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Section 14 Watchdog Timer (WDT)
14.2.2
Timer Control/Status Register (TCSR0)
Bit
7
6
5
4
3
2
1
0
OVF
WT/IT
TME
RSTS
RST/NMI
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Only 0 can be written, to clear the flag.
TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be
input to TCNT, and the timer mode.
TCSR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Note: * The method of writing to TCSR is more complicated than for most other registers, to
prevent accidental overwriting. For details see section 14.2.4, Notes on Register
Access.
Bit 7—Overflow Flag (OVF): A status flag that indicates that TCNT has overflowed from H'FF
to H'00.
Bit 7
OVF
Description
0
[Clearing conditions]
1
•
Write 0 in the TME bit
•
Read TCSR when OVF = 1*, then write 0 in OVF
(Initial value)
[Setting condition]
When TCNT overflows (changes from H'FF to H'00)
(When internal reset request generation is selected in watchdog timer mode, OVF is
cleared automatically by the internal reset.)
Note:
*
When the interval timer interrupt is disabled and OVF is polled, reading OVF while set
to 1 should be performed at least twice.
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Section 14 Watchdog Timer (WDT)
Bit 6—Timer Mode Select (WT/IT
IT):
IT Selects whether the WDT is used as a watchdog timer or
interval timer. If used as an interval timer, the WDT generates an interval timer interrupt request
(WOVI) when TCNT overflows. If used as a watchdog timer, the WDT generates a reset or NMI
interrupt when TCNT overflows.
Bit 6
WT/IT
IT
Description
0
Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT
overflows
(Initial value)
1
Watchdog timer: Generates a reset or NMI interrupt when TCNT overflows
Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Bit 5
TME
Description
0
TCNT is initialized to H'00 and halted
1
TCNT counts
(Initial value)
TCSR0 Bit 4—Reset Select (RSTS): Reserved. This bit should not be set to 1.
Bit 3—Reset or NMI (RST/NMI
NMI):
NMI Specifies whether an internal reset or NMI interrupt is
requested on TCNT overflow in watchdog timer mode.
Bit 3
RST/NMI
NMI
Description
0
An NMI interrupt is requested
1
An internal reset is requested
(Initial value)
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Section 14 Watchdog Timer (WDT)
Bits 2 to 0—Clock Select 2 to 0 (CKS2 to CKS0): These bits select the clock to be input to
TCNT from internal clocks obtained by dividing the system clock.
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
Clock
Overflow Period* (when φ = 20 MHz)
0
0
0
φ/2 (Initial value)
25.6 µs
1
φ/64
819.2 µs
0
φ/128
1.6 ms
1
φ/512
6.6 ms
0
φ/2048
26.2 ms
1
φ/8192
104.9 ms
0
φ/32768
419.4 ms
1
φ/131072
1.68 s
1
1
0
1
Note:
14.2.3
Description
The overflow period is the time from when TCNT starts counting up from H'00 until
overflow occurs.
*
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
Only bit 3 is described here. For details on functions not related to the watchdog timer, see
sections 3.2.2 and 5.2.1, System Control Register (SYSCR), and the descriptions of the relevant
modules.
Bit 3—External Reset (XRST): Indicates the reset source. When the watchdog timer is used, a
reset can be generated by watchdog timer overflow in addition to external reset input. XRST is a
read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog timer overflow.
Bit 3
XRST
Description
0
Reset is generated by watchdog timer overflow
1
Reset is generated by external reset input
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(Initial value)
Section 14 Watchdog Timer (WDT)
14.2.4
Notes on Register Access
The watchdog timer’s TCNT and TCSR registers differ from other registers in being more difficult
to write to. The procedures for writing to and reading these registers are given below.
Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.
They cannot be written to with byte transfer instructions.
Figure 14.2 shows the format of data written to TCNT and TCSR. TCNT and TCSR both have the
same write address. For a write to TCNT, the upper byte of the written word must contain H'5A
and the lower byte must contain the write data. For a write to TCSR, the upper byte of the written
word must contain H'A5 and the lower byte must contain the write data. This transfers the write
data from the lower byte to TCNT or TCSR.
TCNT write
15
8 7
H'5A
Address: H'FFA8
0
Write data
TCSR write
15
Address: H'FFA8
8 7
H'A5
0
Write data
Figure 14.2 Format of Data Written to TCNT and TCSR
Reading TCNT and TCSR: These registers are read in the same way as other registers. The read
addresses are H'FFA8 for TCSR, and H'FFA9 for TCNT.
14.3
Operation
14.3.1
Watchdog Timer Operation
To use the WDT as a watchdog timer, set the WT/IT and TME bits in TCSR to 1. Software must
prevent TCNT overflows by rewriting the TCNT value (normally by writing H'00) before
overflow occurs. This ensures that TCNT does not overflow while the system is operating
normally. If TCNT overflows without being rewritten because of a system crash or other error, an
internal reset or NMI interrupt request is generated.
When the RST/NMI bit is set to 1, the chip is reset for 518 system clock periods (518 φ) by a
counter overflow. This is illustrated in figure 14.3.
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Section 14 Watchdog Timer (WDT)
An internal reset request from the watchdog timer and reset input from the RES pin are handled
via the same vector. The reset source can be identified from the value of the XRST bit in SYSCR.
If a reset caused by an input signal from the RES pin and a reset caused by WDT overflow occur
simultaneously, the RES pin reset has priority, and the XRST bit in SYSCR is set to 1.
An NMI interrupt request from the watchdog timer and an interrupt request from the NMI pin are
handled via the same vector. Simultaneous handling of a watchdog timer NMI interrupt request
and an NMI pin interrupt request must therefore be avoided.
TCNT value
Overflow
H'FF
Time
H'00
WT/IT = 1
TME = 1
H'00 written
to TCNT
OVF = 1*
WT/IT = 1 H'00 written
TME = 1 to TCNT
Internal reset
generated
Internal reset signal
518 system clock periods
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
Note: * Cleared to 0 by an internal reset when OVF is set to 1. XRST is cleared to 0.
Figure 14.3 Operation in Watchdog Timer Mode
14.3.2
Interval Timer Operation
To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1.
An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the
WDT is operating as an interval timer, as shown in figure 14.4. This function can be used to
generate interrupt requests at regular intervals.
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Section 14 Watchdog Timer (WDT)
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WT/IT = 0
TME = 1
WOVI
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 14.4 Operation in Interval Timer Mode
14.3.3
Timing of Setting of Overflow Flag (OVF)
The OVF bit in TCSR is set to 1 if TCNT overflows during interval timer operation. At the same
time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 14.5.
If NMI request generation is selected in watchdog timer mode, when TCNT overflows the OVF
bit in TCSR is set to 1 and at the same time an NMI interrupt is requested.
φ
TCNT
H'FF
H'00
Overflow signal
(internal signal)
OVF
Figure 14.5 Timing of OVF Setting
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Section 14 Watchdog Timer (WDT)
14.4
Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine. When NMI interrupt request generation is selected in
watchdog timer mode, an overflow generates an NMI interrupt request.
14.5
Usage Notes
14.5.1
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 14.6 shows this operation.
TCNT write cycle
T1
T2
T3
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 14.6 Contention between TCNT Write and Increment
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Section 14 Watchdog Timer (WDT)
14.5.2
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
14.5.3
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is
operating, errors could occur in the incrementation. Software must stop the watchdog timer (by
clearing the TME bit to 0) before switching the mode.
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Section 14 Watchdog Timer (WDT)
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Section 15 Serial Communication Interface (SCI)
Section 15 Serial Communication Interface (SCI)
15.1
Overview
The H8/3577 Group and H8/3567 Group are equipped with a single-channel serial communication
interface (SCI). The SCI can handle both asynchronous and clocked synchronous serial
communication. A function is also provided for serial communication between processors
(multiprocessor communication function).
15.1.1
Features
SCI features are listed below.
• Choice of asynchronous or synchronous serial communication mode
Asynchronous mode
 Serial data communication is executed using an asynchronous system in which
synchronization is achieved character by character
Serial data communication can be carried out with standard asynchronous communication
chips such as a Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous
Communication Interface Adapter (ACIA)
 A multiprocessor communication function is provided that enables serial data
communication with a number of processors
 Choice of 12 serial data transfer formats
Data length:
7 or 8 bits
Stop bit length:
1 or 2 bits
Parity:
Even, odd, or none
Multiprocessor bit:
1 or 0
 Receive error detection: Parity, overrun, and framing errors
 Break detection:
Break can be detected by reading the RxD pin level
directly in case of a framing error
Synchronous mode
 Serial data communication is synchronized with a clock
Serial data communication can be carried out with other chips that have a synchronous
communication function
 One serial data transfer format
Data length:
8 bits
 Receive error detection: Overrun errors detected
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Section 15 Serial Communication Interface (SCI)
• Full-duplex communication capability
 The transmitter and receiver are mutually independent, enabling transmission and reception
to be executed simultaneously
 Double-buffering is used in both the transmitter and the receiver, enabling continuous
transmission and continuous reception of serial data
• LSB-first or MSB-first transfer can be selected
 This selection can be made regardless of the communication mode (with the exception of
7-bit data transfer in asynchronous mode)*
Note: * LSB-first transfer is used in the examples in this section.
• Built-in baud rate generator allows any bit rate to be selected
• Choice of serial clock source: internal clock from baud rate generator or external clock from
SCK pin
• Four interrupt sources
 Four interrupt sources (transmit-data-empty, transmit-end, receive-data-full, and receive
error) that can issue requests independently
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Section 15 Serial Communication Interface (SCI)
15.1.2
Block Diagram
Bus interface
Figure 15.1 shows a block diagram of the SCI.
Module data bus
RxD
TxD
RDR
TDR
RSR
TSR
BRR
φ
Baud rate
generator
Transmission/
reception control
Parity generation
Parity check
SCK
Legend:
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
SCMR:
BRR:
SCMR
SSR
SCR
SMR
Internal
data bus
φ/4
φ/16
φ/64
Clock
External clock
TEI
TXI
RXI
ERI
Receive shift register
Receive data register
Transmit shift register
Transmit data register
Serial mode register
Serial control register
Serial status register
Serial interface mode register
Bit rate register
Figure 15.1 Block Diagram of SCI
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Section 15 Serial Communication Interface (SCI)
15.1.3
Pin Configuration
Table 15.1 shows the serial pins used by the SCI.
Table 15.1 SCI Pins
Channel
Pin Name
Symbol
I/O
Function
0
Serial clock pin 0
SCK0
I/O
SCI0 clock input/output
Receive data pin 0
RxD0
Input
SCI0 receive data input
Transmit data pin 0
TxD0
Output
SCI0 transmit data output
Note: The abbreviations SCK, RxD, and TxD are used in the text, omitting the channel number.
15.1.4
Register Configuration
The SCI has the internal registers shown in table 15.2. These registers are used to specify
asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the
transmitter/receiver.
Table 15.2 SCI Registers
Channel
Name
Abbreviation
R/W
Initial Value Address
0
Serial mode register 0
SMR0
R/W
H'00
Bit rate register 0
BRR0
R/W
H'FF
Common
H'FFD8*
2
H'FFD9*
2
Serial control register 0
SCR0
R/W
H'00
H'FFDA
Transmit data register 0
TDR0
R/W
H'FF
H'FFDB
Serial status register 0
SSR0
R/(W)*
H'84
H'FFDC
Receive data register 0
RDR0
R
H'00
Serial interface mode register 0
SCMR0
R/W
H'F2
H'FFDD
3
H'FFDE*
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
1
Notes: 1. Only 0 can be written, to clear flags.
2. Some serial communication interface registers are assigned to the same addresses as
other registers. In this case, register selection is performed by the IICE bit in the serial
timer control register (STCR).
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Section 15 Serial Communication Interface (SCI)
15.2
Register Descriptions
15.2.1
Receive Shift Register (RSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
RSR is a register used to receive serial data.
The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the
LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is
transferred to RDR automatically.
RSR cannot be directly read or written to by the CPU.
15.2.2
Receive Data Register (RDR)
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
RDR is a register that stores received serial data.
When the SCI has received one byte of serial data, it transfers the received serial data from RSR to
RDR where it is stored, and completes the receive operation. After this, RSR is receive-enabled.
Since RSR and RDR function as a double buffer in this way, continuous receive operations can be
performed.
RDR is a read-only register, and cannot be written to by the CPU.
RDR is initialized to H'00 by a reset, and in standby mode, and module stop mode.
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Section 15 Serial Communication Interface (SCI)
15.2.3
Transmit Shift Register (TSR)
Bit
7
6
5
4
3
2
1
0
Read/Write
—
—
—
—
—
—
—
—
TSR is a register used to transmit serial data.
To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then
sends the data to the TxD pin starting with the LSB (bit 0).
When transmission of one byte is completed, the next transmit data is transferred from TDR to
TSR, and transmission started, automatically. However, data transfer from TDR to TSR is not
performed if the TDRE bit in SSR is set to 1.
TSR cannot be directly read or written to by the CPU.
15.2.4
Transmit Data Register (TDR)
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
TDR is an 8-bit register that stores data for serial transmission.
When the SCI detects that TSR is empty, it transfers the transmit data written in TDR to TSR and
starts serial transmission. Continuous serial transmission can be carried out by writing the next
transmit data to TDR during serial transmission of the data in TSR.
TDR can be read or written to by the CPU at all times.
TDR is initialized to H'FF by a reset, and in standby mode, and module stop mode.
15.2.5
Serial Mode Register (SMR)
Bit
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
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Section 15 Serial Communication Interface (SCI)
SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate
generator clock source.
SMR can be read or written to by the CPU at all times.
SMR is initialized to H'00 by a reset, and in standby mode, and module stop mode.
Bit 7—Communication Mode (C/A
A): Selects asynchronous mode or synchronous mode as the
SCI operating mode.
Bit 7
C/A
A
Description
0
Asynchronous mode
1
Synchronous mode
(Initial value)
Bit 6—Character Length (CHR): Selects 7 or 8 bits as the data length in asynchronous mode. In
synchronous mode, a fixed data length of 8 bits is used regardless of the CHR setting.
Bit 6
CHR
Description
0
8-bit data
7-bit data*
1
Note:
*
(Initial value)
When 7-bit data is selected, the MSB (bit 7) of TDR is not transmitted, and LSBfirst/MSB-first selection is not available.
Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is
performed in transmission, and parity bit checking in reception. In synchronous mode, or when a
multiprocessor format is used, parity bit addition and checking is not performed, regardless of the
PE bit setting.
Bit 5
PE
Description
0
Parity bit addition and checking disabled
Parity bit addition and checking enabled*
1
Note:
*
(Initial value)
When the PE bit is set to 1, the parity (even or odd) specified by the O/E bit is added to
transmit data before transmission. In reception, the parity bit is checked for the parity
(even or odd) specified by the O/E bit.
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Section 15 Serial Communication Interface (SCI)
Bit 4—Parity Mode (O/E
E): Selects either even or odd parity for use in parity addition and
checking.
The O/E bit setting is only valid when the PE bit is set to 1, enabling parity bit addition and
checking, in asynchronous mode. The O/E bit setting is invalid in synchronous mode, when parity
bit addition and checking is disabled in asynchronous mode, and when a multiprocessor format is
used.
Bit 4
O/E
E
Description
0
Even parity*
2
Odd parity*
1
1
(Initial value)
Notes: 1. When even parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is even.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in transmission so that the total
number of 1 bits in the transmit character plus the parity bit is odd.
In reception, a check is performed to see if the total number of 1 bits in the receive
character plus the parity bit is odd.
Bit 3—Stop Bit Length (STOP): Selects 1 or 2 bits as the stop bit length in asynchronous mode.
The STOP bit setting is only valid in asynchronous mode. If synchronous mode is set the STOP
bit setting is invalid since stop bits are not added.
Bit 3
STOP
Description
0
1 stop bit*
2
2 stop bits*
1
1
(Initial value)
Notes: 1. In transmission, a single 1 bit (stop bit) is added to the end of a transmit character
before it is sent.
2. In transmission, two 1 bits (stop bits) are added to the end of a transmit character
before it is sent.
In reception, only the first stop bit is checked, regardless of the STOP bit setting. If the second
stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit
character.
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Section 15 Serial Communication Interface (SCI)
Bit 2—Multiprocessor Mode (MP): Selects multiprocessor format. When multiprocessor format
is selected, the PE bit and O/E bit parity settings are invalid. The MP bit setting is only valid in
asynchronous mode; it is invalid in synchronous mode.
For details of the multiprocessor communication function, see section 15.3.3, Multiprocessor
Communication Function.
Bit 2
MP
Description
0
Multiprocessor function disabled
1
Multiprocessor format selected
(Initial value)
Bits 1 and 0—Clock Select 1 and 0 (CKS1, CKS0): These bits select the clock source for the
baud rate generator. The clock source can be selected from φ, φ/4, φ/16, and φ/64, according to the
setting of bits CKS1 and CKS0.
For the relation between the clock source, the bit rate register setting, and the baud rate, see
section 15.2.8, Bit Rate Register.
Bit 1
Bit 0
CKS1
CKS0
Description
0
0
φ clock
1
φ/4 clock
0
φ/16 clock
1
φ/64 clock
1
15.2.6
(Initial value)
Serial Control Register (SCR)
Bit
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output
in asynchronous mode, and interrupt requests, and selection of the serial clock source.
SCR can be read or written to by the CPU at all times.
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Section 15 Serial Communication Interface (SCI)
SCR is initialized to H'00 by a reset, and in standby mode, and module stop mode.
Bit 7—Transmit Interrupt Enable (TIE): Enables or disables transmit-data-empty interrupt
(TXI) request generation when serial transmit data is transferred from TDR to TSR and the TDRE
flag in SSR is set to 1.
Bit 7
TIE
Description
0
Transmit-data-empty interrupt (TXI) request disabled*
1
Note:
(Initial value)
Transmit-data-empty interrupt (TXI) request enabled
*
TXI interrupt request cancellation can be performed by reading 1 from the TDRE flag,
then clearing it to 0, or clearing the TIE bit to 0.
Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI)
request and receive-error interrupt (ERI) request generation when serial receive data is transferred
from RSR to RDR and the RDRF flag in SSR is set to 1.
Bit 6
RIE
Description
0
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
disabled*
(Initial value)
1
Receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request
enabled
Note:
*
RXI and ERI interrupt request cancellation can be performed by reading 1 from the
RDRF, FER, PER, or ORER flag, then clearing the flag to 0, or clearing the RIE bit to 0.
Bit 5—Transmit Enable (TE): Enables or disables the start of serial transmission by the SCI.
Bit 5
TE
Description
0
Transmission disabled*
2
Transmission enabled*
1
1
(Initial value)
Notes: 1. The TDRE flag in SSR is fixed at 1.
2. In this state, serial transmission is started when transmit data is written to TDR and the
TDRE flag in SSR is cleared to 0.
SMR setting must be performed to decide the transmission format before setting the TE
bit to 1.
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Section 15 Serial Communication Interface (SCI)
Bit 4—Receive Enable (RE): Enables or disables the start of serial reception by the SCI.
Bit 4
RE
Description
0
1
Reception disabled*
2
Reception enabled*
1
(Initial value)
Notes: 1. Clearing the RE bit to 0 does not affect the RDRF, FER, PER, and ORER flags, which
retain their states.
2. Serial reception is started in this state when a start bit is detected in asynchronous
mode or serial clock input is detected in synchronous mode.
SMR setting must be performed to decide the reception format before setting the RE bit
to 1.
Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts.
The MPIE bit setting is only valid in asynchronous mode when receiving with the MP bit in SMR
set to 1.
The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Bit 3
MPIE
Description
0
Multiprocessor interrupts disabled (normal reception performed)
(Initial value)
[Clearing conditions]
•
When the MPIE bit is cleared to 0
•
When data with MPB = 1 is received
Multiprocessor interrupts enabled*
1
Receive interrupt (RXI) requests, receive-error interrupt (ERI) requests, and setting
of the RDRF, FER, and ORER flags in SSR are disabled until data with the
multiprocessor bit set to 1 is received.
Note:
*
When receive data including MPB = 0 is received, receive data transfer from RSR to
RDR, receive error detection, and setting of the RDRF, FER, and ORER flags in SSR,
is not performed. When receive data with MPB = 1 is received, the MPB bit in SSR is
set to 1, the MPIE bit is cleared to 0 automatically, and generation of RXI and ERI
interrupts (when the TIE and RIE bits in SCR are set to 1) and FER and ORER flag
setting is enabled.
Bit 2—Transmit End Interrupt Enable (TEIE): Enables or disables transmit-end interrupt
(TEI) request generation if there is no valid transmit data in TDR when the MSB is transmitted.
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Section 15 Serial Communication Interface (SCI)
Bit 2
TEIE
Description
0
Transmit-end interrupt (TEI) request disabled*
Transmit-end interrupt (TEI) request enabled*
1
Note:
(Initial value)
TEI cancellation can be performed by reading 1 from the TDRE flag in SSR, then
clearing it to 0 and clearing the TEND flag to 0, or clearing the TEIE bit to 0.
*
Bits 1 and 0—Clock Enable 1 and 0 (CKE1, CKE0): These bits are used to select the SCI clock
source and enable or disable clock output from the SCK pin. The combination of the CKE1 and
CKE0 bits determines whether the SCK pin functions as an I/O port, the serial clock output pin, or
the serial clock input pin.
The setting of the CKE0 bit, however, is only valid for internal clock operation (CKE1 = 0) in
asynchronous mode. The CKE0 bit setting is invalid in synchronous mode, and in the case of
external clock operation (CKE1 = 1). The setting of bits CKE1 and CKE0 must be carried out
before the SCI’s operating mode is determined using SMR.
For details of clock source selection, see table 15.9 in section 15.3, Operation.
Bit 1
Bit 0
CKE1
CKE0
Description
0
0
Asynchronous mode
Internal clock/SCK pin functions as I/O port*
Synchronous mode
Internal clock/SCK pin functions as serial clock
1
output*
Asynchronous mode
Internal clock/SCK pin functions as clock output*
Synchronous mode
Internal clock/SCK pin functions as serial clock
output
Asynchronous mode
External clock/SCK pin functions as clock input*
Synchronous mode
External clock/SCK pin functions as serial clock
input
3
External clock/SCK pin functions as clock input*
1
1
0
1
Asynchronous mode
Synchronous mode
External clock/SCK pin functions as serial clock
input
Notes: 1. Initial value
2. Outputs a clock of the same frequency as the bit rate.
3. Inputs a clock with a frequency 16 times the bit rate.
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1
2
3
Section 15 Serial Communication Interface (SCI)
15.2.7
Serial Status Register (SSR)
Bit
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Note:
*
Only 0 can be written, to clear the flag.
SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and
multiprocessor bits.
SSR can be read or written to by the CPU at all times. However, 1 cannot be written to flags
TDRE, RDRF, ORER, PER, and FER. Also note that in order to clear these flags they must be
read as 1 beforehand. The TEND flag and MPB flag are read-only flags and cannot be modified.
SSR is initialized to H'84 by a reset, and in standby mode, and module stop mode.
Bit 7—Transmit Data Register Empty (TDRE): Indicates that data has been transferred from
TDR to TSR and the next serial data can be written to TDR.
Bit 7
TDRE
Description
0
[Clearing condition]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
(Initial value)
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR and data can be written to TDR
Rev. 3.00 Mar 17, 2006 page 367 of 706
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Section 15 Serial Communication Interface (SCI)
Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Bit 6
RDRF
Description
0
[Clearing condition]
When 0 is written in RDRF after reading RDRF = 1
(Initial value)
1
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Note: RDR and the RDRF flag are not affected and retain their previous values when an error is
detected during reception or when the RE bit in SCR is cleared to 0.
If reception of the next data is completed while the RDRF flag is still set to 1, an overrun
error will occur and the receive data will be lost.
Bit 5—Overrun Error (ORER): Indicates that an overrun error occurred during reception,
causing abnormal termination.
Bit 5
ORER
Description
0
[Clearing condition]
1
(Initial value)*
When 0 is written in ORER after reading ORER = 1
1
[Setting condition]
When the next serial reception is completed while RDRF = 1*
2
Notes: 1. The ORER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. The receive data prior to the overrun error is retained in RDR, and the data received
subsequently is lost. Also, subsequent serial reception cannot be continued while the
ORER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Rev. 3.00 Mar 17, 2006 page 368 of 706
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Section 15 Serial Communication Interface (SCI)
Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in
asynchronous mode, causing abnormal termination.
Bit 4
FER
Description
0
[Clearing condition]
1
(Initial value)*
When 0 is written in FER after reading FER = 1
1
[Setting condition]
When the SCI checks the stop bit at the end of the receive data when reception ends,
2
and the stop bit is 0*
Notes: 1. The FER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. In 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit
is not checked. If a framing error occurs, the receive data is transferred to RDR but the
RDRF flag is not set. Also, subsequent serial reception cannot be continued while the
FER flag is set to 1. In synchronous mode, serial transmission cannot be continued,
either.
Bit 3—Parity Error (PER): Indicates that a parity error occurred during reception using parity
addition in asynchronous mode, causing abnormal termination.
Bit 3
PER
Description
0
[Clearing condition]
(Initial value)*
1
When 0 is written in PER after reading PER = 1
1
[Setting condition]
When, in reception, the number of 1 bits in the receive data plus the parity bit does not
2
match the parity setting (even or odd) specified by the O/E bit in SMR*
Notes: 1. The PER flag is not affected and retains its previous state when the RE bit in SCR is
cleared to 0.
2. If a parity error occurs, the receive data is transferred to RDR but the RDRF flag is not
set. Also, subsequent serial reception cannot be continued while the PER flag is set to
1. In synchronous mode, serial transmission cannot be continued, either.
Rev. 3.00 Mar 17, 2006 page 369 of 706
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Section 15 Serial Communication Interface (SCI)
Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of
the transmit character is sent, and transmission has been ended.
The TEND flag is read-only and cannot be modified.
Bit 2
TEND
Description
0
[Clearing condition]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
(Initial value)
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit of a 1-byte serial transmit character
Bit 1—Multiprocessor Bit (MPB): When reception is performed using a multiprocessor format
in asynchronous mode, MPB stores the multiprocessor bit in the receive data.
MPB is a read-only bit, and cannot be modified.
Bit 1
MPB
Description
0
[Clearing condition]
(Initial value)*
When data with a 0 multiprocessor bit is received
1
[Setting condition]
When data with a 1 multiprocessor bit is received
Note:
*
Retains its previous state when the RE bit in SCR is cleared to 0 with multiprocessor
format.
Bit 0—Multiprocessor Bit Transfer (MPBT): When transmission is performed using a
multiprocessor format in asynchronous mode, MPBT stores the multiprocessor bit to be added to
the transmit data.
The MPBT bit setting is invalid when a multiprocessor format is not used, when not transmitting,
and in synchronous mode.
Bit 0
MPBT
Description
0
Data with a 0 multiprocessor bit is transmitted
1
Data with a 1 multiprocessor bit is transmitted
Rev. 3.00 Mar 17, 2006 page 370 of 706
REJ09B0303-0300
(Initial value)
Section 15 Serial Communication Interface (SCI)
15.2.8
Bit Rate Register (BRR)
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate
generator operating clock selected by bits CKS1 and CKS0 in SMR.
BRR can be read or written to by the CPU at all times.
BRR is initialized to H'FF by a reset, and in standby mode, and module stop mode.
As baud rate generator control is performed independently for each channel, different values can
be set for each channel.
Table 15.3 shows sample BRR settings in asynchronous mode, and table 15.4 shows sample BRR
settings in synchronous mode.
Rev. 3.00 Mar 17, 2006 page 371 of 706
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Section 15 Serial Communication Interface (SCI)
Table 15.3 BRR Settings for Various Bit Rates (Asynchronous Mode)
Operating Frequency φ (MHz)
φ = 2 MHz
φ = 2.097152 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
150
1
103
0.16
1
300
0
207
0.16
600
0
103
1200
0
2400
4800
φ = 2.4576 MHz
φ = 3 MHz
N
Error
(%)
N
Error
(%)
–0.04 1
174
–0.26 1
212
0.03
108
0.21
1
127
0.00
1
155
0.16
0
217
0.21
0
255
0.00
1
77
0.16
0.16
0
108
0.21
0
127
0.00
0
155
0.16
51
0.16
0
54
–0.70 0
63
0.00
0
77
0.16
0
25
0.16
0
26
1.14
0
31
0.00
0
38
0.16
0
12
0.16
0
13
–2.48 0
15
0.00
0
19
–2.34
9600
—
—
—
0
6
–2.48 0
7
0.00
0
9
–2.34
19200
—
—
—
—
—
—
0
3
0.00
0
4
–2.34
31250
0
1
0.00
—
—
—
—
—
—
0
2
0.00
38400
—
—
—
—
—
—
0
1
0.00
—
—
—
n
n
Operating Frequency φ (MHz)
φ = 3.6864 MHz
φ = 4 MHz
φ = 4.9152 MHz
φ = 5 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
—
—
—
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
–1.70 0
4
0.00
38400
0
2
0.00
—
—
—
0
3
0.00
3
1.73
Rev. 3.00 Mar 17, 2006 page 372 of 706
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0
Section 15 Serial Communication Interface (SCI)
Operating Frequency φ (MHz)
φ = 6 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
2
106
150
2
300
φ = 6.144 MHz
φ = 7.3728 MHz
φ = 8 MHz
N
Error
(%)
n
N
Error
(%)
–0.44 2
108
0.08
2
130
77
0.16
2
79
0.00
2
1
155
0.16
1
159
0.00
1
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
–2.34 0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
–2.34 0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
—
—
—
0
7
0.00
38400
0
4
–2.34 0
4
0.00
0
5
0.00
—
—
—
n
N
Error
(%)
–0.07 2
141
0.03
95
0.00
2
103
0.16
191
0.00
1
207
0.16
n
Operating Frequency φ (MHz)
φ = 9.8304 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
2
174
150
2
300
φ = 10 MHz
N
Error
(%)
–0.26 2
177
127
0.00
2
1
255
0.00
600
1
127
1200
0
255
2400
0
4800
φ = 12 MHz
φ = 12.288 MHz
N
Error
(%)
n
N
Error
(%)
–0.25 2
212
0.03
2
217
0.08
129
0.16
2
155
0.16
2
159
0.00
2
64
0.16
2
77
0.16
2
79
0.00
0.00
1
129
0.16
1
155
0.16
1
159
0.00
0.00
1
64
0.16
1
77
0.16
1
79
0.00
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36 0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
–2.34 0
19
0.00
31250
0
9
–1.70 0
9
0.00
0
11
0.00
11
2.40
38400
0
7
0.00
7
1.73
0
9
–2.34 0
9
0.00
n
0
n
0
Rev. 3.00 Mar 17, 2006 page 373 of 706
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Section 15 Serial Communication Interface (SCI)
Operating Frequency φ (MHz)
φ = 14 MHz
φ = 14.7456 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
2
248
150
2
300
φ = 16 MHz
φ = 17.2032 MHz
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
–0.17 3
64
0.70
3
70
0.03
3
75
0.48
181
0.16
2
191
0.00
2
207
0.16
2
223
0.00
2
90
0.16
2
95
0.00
2
103
0.16
2
111
0.00
600
1
181
0.16
1
191
0.00
1
207
0.16
1
223
0.00
1200
1
90
0.16
1
95
0.00
1
103
0.16
1
111
0.00
2400
0
181
0.16
0
191
0.00
0
207
0.16
0
223
0.00
4800
0
90
0.16
0
95
0.00
0
103
0.16
0
111
0.00
9600
0
45
–0.93 0
47
0.00
0
51
0.16
0
55
0.00
19200
0
22
–0.93 0
23
0.00
0
25
0.16
0
27
0.00
31250
0
13
0.00
0
14
–1.70 0
15
0.00
0
16
1.20
38400
—
—
—
0
11
0.00
12
0.16
0
13
0.00
n
0
Operating Frequency φ (MHz)
φ = 18 MHz
Bit Rate
(bits/s)
n
N
Error
(%)
110
3
79
150
2
300
φ = 19.6608 MHz
φ = 20 MHz
N
Error
(%)
n
N
Error
(%)
–0.12 3
86
0.31
3
88
–0.25
233
0.16
2
255
0.00
3
64
0.16
2
116
0.16
2
127
0.00
2
129
0.16
600
1
233
0.16
1
255
0.00
2
64
0.16
1200
1
116
0.16
1
127
0.00
1
129
0.16
2400
0
233
0.16
0
255
0.00
1
64
0.16
4800
0
116
0.16
0
127
0.00
0
129
0.16
9600
0
58
–0.69 0
63
0.00
0
64
0.16
19200
0
28
1.02
0
31
0.00
0
32
–1.36
31250
0
17
0.00
0
19
–1.70 0
19
0.00
38400
0
14
–2.34 0
15
0.00
15
1.73
n
Rev. 3.00 Mar 17, 2006 page 374 of 706
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0
Section 15 Serial Communication Interface (SCI)
Table 15.4 BRR Settings for Various Bit Rates (Synchronous Mode)
Operating Frequency φ (MHz)
φ = 2 MHz
Bit Rate
φ = 4 MHz
(bits/s)
n
N
n
N
110
3
70
—
—
250
2
124
2
500
1
249
2
1k
1
124
2.5 k
0
5k
φ = 8 MHz
φ = 10 MHz
φ = 16 MHz
n
N
n
N
n
N
249
3
124
—
—
3
249
124
2
249
—
—
3
1
249
2
124
—
—
199
1
99
1
199
1
0
99
0
199
1
99
10 k
0
49
0
99
0
25 k
0
19
0
39
0
50 k
0
9
0
19
100 k
0
4
0
250 k
0
1
0
0*
500 k
1M
φ = 20 MHz
n
N
124
—
—
2
249
—
—
249
2
99
2
124
1
124
1
199
1
249
199
0
249
1
99
1
124
79
0
99
0
159
0
199
0
39
0
49
0
79
0
99
9
0
19
0
24
0
39
0
49
0
3
0
7
0
9
0
15
0
19
0
1
0
3
0
4
0
7
0
9
0
0*
0
1
0
3
0
4
0
1
0
0*
2.5 M
0
5M
0*
Legend:
Blank: Cannot be set.
—:
Can be set, but there will be a degree of error.
*:
Continuous transfer is not possible.
Note:
As far as possible, the setting should be made so that the error is no more than 1%.
Rev. 3.00 Mar 17, 2006 page 375 of 706
REJ09B0303-0300
Section 15 Serial Communication Interface (SCI)
The BRR setting is found from the following equations.
Asynchronous mode:
N=
φ
64 ×
22n–1
×B
× 106 – 1
Synchronous mode:
N=
Where B:
N:
φ:
n:
φ
× 106 – 1
8 × 22n–1 × B
Bit rate (bits/s)
BRR setting for baud rate generator (0 ≤ N ≤ 255)
Operating frequency (MHz)
Baud rate generator input clock (n = 0 to 3)
(See the table below for the relation between n and the clock.)
SMR Setting
n
Clock
CKS1
CKS0
0
φ
0
0
1
φ/4
0
1
2
φ/16
1
0
3
φ/64
1
1
The bit rate error in asynchronous mode is found from the following equation:


φ × 106
Error (%) = 
– 1 × 100
2n–1
(N
+
1)
×
B
×
64
×
2


Rev. 3.00 Mar 17, 2006 page 376 of 706
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Section 15 Serial Communication Interface (SCI)
Table 15.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 15.6
and 15.7 show the maximum bit rates with external clock input.
Table 15.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit Rate (bits/s)
n
N
2
62500
0
0
2.097152
65536
0
0
2.4576
76800
0
0
3
93750
0
0
3.6864
115200
0
0
4
125000
0
0
4.9152
153600
0
0
5
156250
0
0
6
187500
0
0
6.144
192000
0
0
7.3728
230400
0
0
8
250000
0
0
9.8304
307200
0
0
10
312500
0
0
12
375000
0
0
12.288
384000
0
0
14
437500
0
0
14.7456
460800
0
0
16
500000
0
0
17.2032
537600
0
0
18
562500
0
0
19.6608
614400
0
0
20
625000
0
0
Rev. 3.00 Mar 17, 2006 page 377 of 706
REJ09B0303-0300
Section 15 Serial Communication Interface (SCI)
Table 15.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.5000
31250
2.097152
0.5243
32768
2.4576
0.6144
38400
3
0.7500
46875
3.6864
0.9216
57600
4
1.0000
62500
4.9152
1.2288
76800
5
1.2500
78125
6
1.5000
93750
6.144
1.5360
96000
7.3728
1.8432
115200
8
2.0000
125000
9.8304
2.4576
153600
10
2.5000
156250
12
3.0000
187500
12.288
3.0720
192000
14
3.5000
218750
14.7456
3.6864
230400
16
4.0000
250000
17.2032
4.3008
268800
18
4.5000
281250
19.6608
4.9152
307200
20
5.0000
312500
Rev. 3.00 Mar 17, 2006 page 378 of 706
REJ09B0303-0300
Section 15 Serial Communication Interface (SCI)
Table 15.7 Maximum Bit Rate with External Clock Input (Synchronous Mode)
φ (MHz)
External Input Clock (MHz)
Maximum Bit Rate (bits/s)
2
0.3333
333333.3
4
0.6667
666666.7
6
1.0000
1000000.0
8
1.3333
1333333.3
10
1.6667
1666666.7
12
2.0000
2000000.0
14
2.3333
2333333.3
16
2.6667
2666666.7
18
3.0000
3000000.0
20
3.3333
3333333.3
Rev. 3.00 Mar 17, 2006 page 379 of 706
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Section 15 Serial Communication Interface (SCI)
15.2.9
Serial Interface Mode Register (SCMR)
Bit
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
SMIF
Initial value
1
1
1
1
0
0
1
0
Read/Write
—
—
—
—
R/W
R/W
—
R/W
SCMR is an 8-bit readable/writable register used to select SCI functions.
SCMR is initialized to H'F2 by a reset, and in standby mode, and module stop mode.
Bits 7 to 4—Reserved: These bits cannot be modified and are always read as 1.
Bit 3—Data Transfer Direction (SDIR): Selects the serial/parallel conversion format.
Bit 3
SDIR
Description
0
TDR contents are transmitted LSB-first
(Initial value)
Receive data is stored in RDR LSB-first
1
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Bit 2—Data Invert (SINV): Specifies inversion of the data logic level. The SINV bit does not
affect the logic level of the parity bit(s): parity bit inversion requires inversion of the O/E bit in
SMR.
Bit 2
SINV
Description
0
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
1
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Bit 1—Reserved: This bit cannot be modified and is always read as 1.
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(Initial value)
Section 15 Serial Communication Interface (SCI)
Bit 0—Serial Communication Interface Mode Select (SMIF): Reserved bit. 1 should not be
written in this bit.
Bit 0
SMIF
Description
0
Normal SCI mode
1
Reserved mode
(Initial value)
15.2.10 Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When bits MSTP7 is set to 1, SCI0 operation, respectively, stops at the end of the bus cycle and a
transition is made to module stop mode. For details, see section 21.5., Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Module Stop (MSTP7): Specifies the SCI0 module stop mode.
Bit 7
MSTP7
Description
0
SCI0 module stop mode is cleared
1
SCI0 module stop mode is set
(Initial value)
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Section 15 Serial Communication Interface (SCI)
15.3
Operation
15.3.1
Overview
The SCI can carry out serial communication in two modes: asynchronous mode in which
synchronization is achieved character by character, and synchronous mode in which
synchronization is achieved with clock pulses.
Selection of asynchronous or synchronous mode and the transmission format is made using SMR
as shown in table 15.8. The SCI clock is determined by a combination of the C/A bit in SMR and
the CKE1 and CKE0 bits in SCR, as shown in table 15.9.
Asynchronous Mode
• Data length: Choice of 7 or 8 bits
• Choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the
combination of these parameters determines the transfer format and character length)
• Detection of framing, parity, and overrun errors, and breaks, during reception
• Choice of internal or external clock as SCI clock source
 When internal clock is selected:
The SCI operates on the baud rate generator clock and a clock with the same frequency as
the bit rate can be output
 When external clock is selected:
A clock with a frequency of 16 times the bit rate must be input (the built-in baud rate
generator is not used)
Synchronous Mode
• Transfer format: Fixed 8-bit data
• Detection of overrun errors during reception
• Choice of internal or external clock as SCI clock source
 When internal clock is selected:
The SCI operates on the baud rate generator clock and a serial clock is output off-chip
 When external clock is selected:
The built-in baud rate generator is not used, and the SCI operates on the input serial clock
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Section 15 Serial Communication Interface (SCI)
Table 15.8 SMR Settings and Serial Transfer Format Selection
SMR Settings
Bit 7
Bit 6
Bit 2
SCI Transfer Format
Bit 5
C/A
A
CHR
MP
PE
STOP
Mode
0
0
0
0
0
Asynchronous
mode
1
1
Data
Length
Multiprocessor
Bit
Parity
Bit
Stop Bit
Length
8-bit data
No
No
1 bit
Bit 3
2 bits
0
Yes
1
1
0
2 bits
0
7-bit data
No
1
1
1
0
1
1
—
—
—
0
—
1
—
0
—
1
—
—
1 bit
2 bits
Yes
1
0
1 bit
1 bit
2 bits
Asynchronous
mode (multiprocessor format)
8-bit data
Yes
No
1 bit
2 bits
7-bit data
1 bit
2 bits
Synchronous
mode
8-bit data
No
None
Table 15.9 SMR and SCR Settings and SCI Clock Source Selection
SMR
SCR Setting
SCI Transfer Clock
Bit 7
Bit 1
Bit 0
C/A
A
CKE1
CKE0
Mode
0
0
0
Asynchronous
mode
1
1
0
Clock
Source
Internal
0
0
1
1
0
Synchronous
mode
SCI does not use SCK pin
Outputs clock with same frequency as bit
rate
External
Inputs clock with frequency of 16 times
the bit rate
Internal
Outputs serial clock
External
Inputs serial clock
1
1
SCK Pin Function
1
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Section 15 Serial Communication Interface (SCI)
15.3.2
Operation in Asynchronous Mode
In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the
start of communication and followed by one or two stop bits indicating the end of communication.
Serial communication is thus carried out with synchronization established on a character-bycharacter basis.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication. Both the transmitter and the receiver also have a double-buffered structure, so
that data can be read or written during transmission or reception, enabling continuous data
transfer.
Figure 15.2 shows the general format for asynchronous serial communication.
In asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication.
One serial communication character consists of a start bit (low level), followed by data (in LSBfirst order), a parity bit (high or low level), and finally one or two stop bits (high level).
In asynchronous mode, the SCI performs synchronization at the falling edge of the start bit in
reception. The SCI samples the data on the 8th pulse of a clock with a frequency of 16 times the
length of one bit, so that the transfer data is latched at the center of each bit.
Idle state
(mark state)
LSB
1
Serial
data
0
D0
MSB
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
1
1
Parity Stop bit(s)
bit
1 bit,
or none
1 or
2 bits
One unit of transfer data (character or frame)
Figure 15.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
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Section 15 Serial Communication Interface (SCI)
Data Transfer Format
Table 15.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected by settings in SMR.
Table 15.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
2
3
4
5
6
7
8
9
10
11
12
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P
STOP
0
1
0
1
S
8-bit data
P
STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend:
S:
Start bit
STOP: Stop bit
P:
Parity bit
MPB: Multiprocessor bit
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Section 15 Serial Communication Interface (SCI)
Clock
Either an internal clock generated by the built-in baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table
15.9.
When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate
used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is at the center of each transmit data bit, as shown in figure 15.3.
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 15.3 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Data Transfer Operations
SCI Initialization (Asynchronous Mode): Before transmitting and receiving data, first clear the
TE and RE bits in SCR to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
When an external clock is used the clock should not be stopped during operation, including
initialization, since operation is uncertain.
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Section 15 Serial Communication Interface (SCI)
Figure 15.4 shows a sample SCI initialization flowchart.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. This is not
necessary if an external clock is
used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
<Initialization completed>
Figure 15.4 Sample SCI Initialization Flowchart
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Section 15 Serial Communication Interface (SCI)
Serial Data Transmission (Asynchronous Mode): Figure 15.5 shows a sample flowchart for
serial transmission.
The following procedure should be used for serial data transmission.
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1?
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
No
TEND = 1?
Yes
No
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Read TEND flag in SSR
Break output?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, one
frame of 1s is output and
transmission is enabled.
[4]
Yes
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 15.5 Sample Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit data empty interrupt (TXI) is generated.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Parity bit or multiprocessor bit:
One parity bit (even or odd parity), or one multiprocessor bit is output.
A format in which neither a parity bit nor a multiprocessor bit is output can also be
selected.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, the data is transferred from TDR to TSR, the stop bit is sent,
and then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a TEI interrupt request is generated.
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Section 15 Serial Communication Interface (SCI)
Figure 15.6 shows an example of the operation for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 15.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
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Section 15 Serial Communication Interface (SCI)
Serial Data Reception (Asynchronous Mode): Figure 15.7 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
Initialization
[1]
Start reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling and
break detection:
Read ORER, PER, and
If a receive error occurs, read the
[2]
FER flags in SSR
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
Yes
handling, ensure that the ORER,
PER ∨ FER ∨ ORER= 1?
PER, and FER flags are all
[3]
cleared to 0. Reception cannot
No
Error handling
be resumed if any of these flags
(Continued on next page) are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
[4]
Read RDRF flag in SSR
the input port corresponding to
the RxD pin.
No
RDRF = 1?
[4] SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[5] Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0.
<End>
Figure 15.7 Sample Serial Reception Data Flowchart
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Section 15 Serial Communication Interface (SCI)
[3]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 15.7 Sample Serial Reception Data Flowchart (cont)
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Section 15 Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below.
1. The SCI monitors the transmission line, and if a 0 stop bit is detected, performs internal
synchronization and starts reception.
2. The received data is stored in RSR in LSB-to-MSB order.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI carries out the following checks.
a. Parity check:
The SCI checks whether the number of 1 bits in the receive data agrees with the parity
(even or odd) set in the O/E bit in SMR.
b. Stop bit check:
The SCI checks whether the stop bit is 1.
If there are two stop bits, only the first is checked.
c. Status check:
The SCI checks whether the RDRF flag is 0, indicating that the receive data can be
transferred from RSR to RDR.
If all the above checks are passed, the RDRF flag is set to 1, and the receive data is stored in
RDR.
If a receive error* is detected in the error check, the operation is as shown in table 15.11.
Note: *
Subsequent receive operations cannot be performed when a receive error has occurred.
Also note that the RDRF flag is not set to 1 in reception, and so the error flags must be
cleared to 0.
4. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER, PER, or FER flag changes to 1, a
receive-error interrupt (ERI) request is generated.
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Section 15 Serial Communication Interface (SCI)
Table 15.11 Receive Errors and Conditions for Occurrence
Receive Error
Abbreviation
Occurrence Condition
Data Transfer
Overrun error
ORER
When the next data reception
is completed while the RDRF
flag in SSR is set to 1
Receive data is not
transferred from RSR to
RDR
Framing error
FER
When the stop bit is 0
Receive data is transferred
from RSR to RDR
Parity error
PER
When the received data differs
from the parity (even or odd)
set in SMR
Receive data is transferred
from RSR to RDR
Figure 15.8 shows an example of the operation for reception in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
ERI interrupt request
generated by framing
error
1 frame
Figure 15.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
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Section 15 Serial Communication Interface (SCI)
15.3.3
Multiprocessor Communication Function
The multiprocessor communication function performs serial communication using a
multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous
mode. Use of this function enables data transfer to be performed among a number of processors
sharing transmission lines.
When multiprocessor communication is carried out, each receiving station is addressed by a
unique ID code.
The serial communication cycle consists of two component cycles: an ID transmission cycle
which specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used
to differentiate between the ID transmission cycle and the data transmission cycle.
The transmitting station first sends the ID of the receiving station with which it wants to perform
serial communication as data with a 1 multiprocessor bit added. It then sends transmit data as data
with a 0 multiprocessor bit added.
The receiving station skips the data until data with a 1 multiprocessor bit is sent.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID does
not match continue to skip the data until data with a 1 multiprocessor bit is again received. In this
way, data communication is carried out among a number of processors.
Figure 15.9 shows an example of inter-processor communication using a multiprocessor format.
Data Transfer Format
There are four data transfer formats.
When a multiprocessor format is specified, the parity bit specification is invalid.
For details, see table 15.10.
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Section 15 Serial Communication Interface (SCI)
Clock
See the section on asynchronous mode.
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'01
H'AA
(MPB = 1)
ID transmission cycle:
receiving station
specification
(MPB = 0)
Data transmission cycle:
data transmission to
receiving station specified
by ID
Legend:
MPB: Multiprocessor bit
Figure 15.9 Example of Inter-Processor Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
Data Transfer Operations
Multiprocessor Serial Data Transmission: Figure 15.10 shows a sample flowchart for
multiprocessor serial data transmission.
The following procedure should be used for multiprocessor serial data transmission.
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Section 15 Serial Communication Interface (SCI)
[1] [1] SCI initialization:
Initialization
Start transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
No
TDRE = 1?
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, one
frame of 1s is output and
transmission is enabled.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
[4]
Yes
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 15.10 Sample Multiprocessor Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission.
If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
The serial transmit data is sent from the TxD pin in the following order.
a. Start bit:
One 0-bit is output.
b. Transmit data:
8-bit or 7-bit data is output in LSB-first order.
c. Multiprocessor bit
One multiprocessor bit (MPBT value) is output.
d. Stop bit(s):
One or two 1-bits (stop bits) are output.
e. Mark state:
1 is output continuously until the start bit that starts the next transmission is sent.
3. The SCI checks the TDRE flag at the timing for sending the stop bit.
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, the stop bit is sent, and
then serial transmission of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the
mark state is entered in which 1 is output continuously. If the TEIE bit in SCR is set to 1 at this
time, a transmit-end interrupt (TEI) request is generated.
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Section 15 Serial Communication Interface (SCI)
Figure 15.11 shows an example of SCI operation for transmission using a multiprocessor format.
1
Start
bit
0
Multiprocessor Stop
bit
bit
Data
D0
D1
D7
0/1
1
Start
bit
0
Multiproces- Stop
1
sor bit bit
Data
D0
D1
D7
0/1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
request
generated
Data written to TDR
and TDRE flag cleared to
0 in TXI interrupt handling
routine
TXI interrupt
request generated
TEI interrupt
request generated
1 frame
Figure 15.11 Example of SCI Operation in Transmission
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Multiprocessor Serial Data Reception: Figure 15.12 shows a sample flowchart for
multiprocessor serial reception.
The following procedure should be used for multiprocessor serial data reception.
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Section 15 Serial Communication Interface (SCI)
Initialization
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2]
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
Start reception
Read MPIE bit in SCR
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
[3] SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1?
Yes
[4] SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Read receive data in RDR
No
This station's ID?
Yes
[5] Receive error handling and break
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
handling, ensure that the ORER
and FER flags are both cleared
to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
Yes
No
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR
No
All data received?
[5]
Error handling
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 15.12 Sample Multiprocessor Serial Reception Flowchart
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Section 15 Serial Communication Interface (SCI)
[5]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 15.12 Sample Multiprocessor Serial Reception Flowchart (cont)
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Section 15 Serial Communication Interface (SCI)
Figure 15.13 shows an example of SCI operation for multiprocessor format reception.
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
If not this station’s ID, RXI interrupt request is
MPIE bit is set to 1
not generated, and RDR
again
retains its state
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data2)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID2
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt handling routine
(b) Data matches station’s ID
Figure 15.13 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
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Data2
MPIE bit set to 1
again
Section 15 Serial Communication Interface (SCI)
15.3.4
Operation in Synchronous Mode
In synchronous mode, data is transmitted or received in synchronization with clock pulses, making
it suitable for high-speed serial communication.
Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex
communication by use of a common clock. Both the transmitter and the receiver also have a
double-buffered structure, so that data can be read or written during transmission or reception,
enabling continuous data transfer.
Figure 15.14 shows the general format for synchronous serial communication.
One unit of transfer data (character or frame)
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Don’t care
Note: * High except in continuous transfer
Figure 15.14 Data Format in Synchronous Communication
In synchronous serial communication, data on the transmission line is output from one falling edge
of the serial clock to the next. Data is guaranteed valid at the rising edge of the serial clock.
In synchronous serial communication, one character consists of data output starting with the LSB
and ending with the MSB. After the MSB is output, the transmission line holds the MSB state.
In synchronous mode, the SCI receives data in synchronization with the rising edge of the serial
clock.
Data Transfer Format
A fixed 8-bit data format is used.
No parity or multiprocessor bits are added.
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Section 15 Serial Communication Interface (SCI)
Clock
Either an internal clock generated by the built-in baud rate generator or an external serial clock
input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1
and CKE0 bits in SCR. For details on SCI clock source selection, see table 15.9.
When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Eight serial clock pulses are output in the transfer of one character, and when no transfer is
performed the clock is fixed high. When only receive operations are performed, however, the
serial clock is output until an overrun error occurs or the RE bit is cleared to 0. To perform receive
operations in units of one character, select an external clock as the clock source.
Data Transfer Operations
SCI Initialization (Synchronous Mode): Before transmitting and receiving data, first clear the
TE and RE bits in SCR to 0, then initialize the SCI as described below.
When the operating mode, transfer format, etc., is changed, the TE and RE bits must be cleared to
0 before making the change using the following procedure. When the TE bit is cleared to 0, the
TDRE flag is set to 1 and TSR is initialized. Note that clearing the RE bit to 0 does not change the
settings of the RDRF, PER, FER, and ORER flags, or the contents of RDR.
Figure 15.15 shows a sample SCI initialization flowchart.
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Section 15 Serial Communication Interface (SCI)
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
Start initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR
and SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
[3] Write a value corresponding to the bit
rate to BRR. This is not necessary if an
external clock is used.
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note: In simultaneous transmitting and receiving, the TE and RE bits should both be
cleared to 0 or set to 1 simultaneously.
Figure 15.15 Sample SCI Initialization Flowchart
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Section 15 Serial Communication Interface (SCI)
Serial Data Transmission (Synchronous Mode): Figure 15.16 shows a sample flowchart for
serial transmission.
The following procedure should be used for serial data transmission.
[1]
Initialization
Start transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Yes
Read TEND flag in SSR
No
TEND = 1?
Yes
Clear TE bit in SCR to 0
<End>
Figure 15.16 Sample Serial Transmission Flowchart
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Section 15 Serial Communication Interface (SCI)
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if it is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a transmit-data-empty interrupt
(TXI) is generated.
When clock output mode has been set, the SCI outputs 8 serial clock pulses. When use of an
external clock has been specified, data is output synchronized with the input clock.
The serial transmit data is sent from the TxD pin starting with the LSB (bit 0) and ending with
the MSB (bit 7).
3. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, the MSB (bit 7) is sent, and the
TxD pin maintains its state.
If the TEIE bit in SCR is set to 1 at this time, a transmit-end interrupt (TEI) request is
generated.
4. After completion of serial transmission, the SCK pin is held in a constant state.
Figure 15.17 shows an example of SCI operation in transmission.
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Section 15 Serial Communication Interface (SCI)
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
TXI interrupt
and TDRE flag
request generated
cleared to 0 in TXI
interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 15.17 Example of SCI Operation in Transmission
Serial Data Reception (Synchronous Mode): Figure 15.18 shows a sample flowchart for serial
reception.
The following procedure should be used for serial data reception.
When changing the operating mode from asynchronous to synchronous, be sure to check that the
ORER, PER, and FER flags are all cleared to 0.
The RDRF flag will not be set if the FER or PER flag is set to 1, and neither transmit nor receive
operations will be possible.
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Section 15 Serial Communication Interface (SCI)
[1]
Initialization
Start reception
[2]
Read ORER flag in SSR
Yes
[3]
ORER = 1?
No
Error handling
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
[5]
[1]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
handling, clear the ORER flag to
0. Transfer cannot be resumed if
the ORER flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0.
Clear RE bit in SCR to 0
<End>
[3]
Error handling
Overrun error handling
Clear ORER flag in SSR to 0
<End>
Figure 15.18 Sample Serial Reception Flowchart
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Section 15 Serial Communication Interface (SCI)
In serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with serial clock input or output.
2. The received data is stored in RSR in LSB-to-MSB order.
After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be
transferred from RSR to RDR.
If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR. If a
receive error is detected in the error check, the operation is as shown in table 15.11.
Neither transmit nor receive operations can be performed subsequently when a receive error
has been found in the error check.
3. If the RIE bit in SCR is set to 1 when the RDRF flag changes to 1, a receive-data-full interrupt
(RXI) request is generated.
Also, if the RIE bit in SCR is set to 1 when the ORER flag changes to 1, a receive-error
interrupt (ERI) request is generated.
Figure 15.19 shows an example of SCI operation in reception.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 15.19 Example of SCI Operation in Reception
Simultaneous Serial Data Transmission and Reception (Synchronous Mode): Figure 15.20
shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations.
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Section 15 Serial Communication Interface (SCI)
Initialization
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
Start transmission/reception
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0
to 1 can also be identified by a TXI
interrupt.
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3] Receive error handling:
Read ORER flag in SSR
ORER = 1?
No
Read RDRF flag in SSR
Yes
[3]
Error handling
[4]
No
RDRF = 1?
Yes
No
Yes
Clear TE and RE bits in SCR to 0
[4] SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[5] Serial transmission/reception
Read receive data in RDR, and
clear RDRF flag in SSR to 0
All data received?
If a receive error occurs, read the
ORER flag in SSR , and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to
1.
[5]
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR and clear the
TDRE flag to 0.
<End>
Note: When switching from transmit or receive operation to simultaneous transmit and receive operations, first
clear the TE bit and RE bit to 0, then set both these bits to 1 simultaneously.
Figure 15.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 15 Serial Communication Interface (SCI)
15.4
SCI Interrupts
The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt
(ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI)
request. Table 15.12 shows the interrupt sources and their relative priorities. Individual interrupt
sources can be enabled or disabled with the TIE, RIE, and TEIE bits in SCR. Each kind of
interrupt request is sent to the interrupt controller independently.
Table 15.12 SCI Interrupt Sources
Interrupt Source
Description
Priority
ERI
Receive error (ORER, FER, or PER)
High
RXI
Receive data register full (RDRF)
TXI
Transmit data register empty (TDRE)
TEI
Transmit end (TEND)
Low
The TEI interrupt is requested when the TEND flag is set to 1 while the TEIE bit is set to 1. The
TEND flag is cleared at the same time as the TDRE flag. Consequently, if a TEI interrupt and a
TXI interrupt are requested simultaneously, the TXI interrupt will have priority for acceptance,
and the TDRE flag and TEND flag may be cleared. Note that the TEI interrupt will not be
accepted in this case.
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Section 15 Serial Communication Interface (SCI)
15.5
Usage Notes
The following points should be noted when using the SCI.
Relation between Writes to TDR and the TDRE Flag: The TDRE flag in SSR is a status flag
that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers
data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
Operation when Multiple Receive Errors Occur Simultaneously: If a number of receive errors
occur at the same time, the state of the status flags in SSR is as shown in table 15.13. If there is an
overrun error, data is not transferred from RSR to RDR, and the receive data is lost.
Table 15.13 State of SSR Status Flags and Transfer of Receive Data
SSR Status Flags
RDRF
ORER
FER
PER
Receive Data Transfer
RSR to RDR
Receive Errors
1
1
0
0
X
Overrun error
0
0
1
0
O
Framing error
0
0
0
1
O
Parity error
1
1
1
0
X
Overrun error + framing error
1
1
0
1
X
Overrun error + parity error
0
0
1
1
O
Framing error + parity error
1
1
1
1
X
Overrun error + framing error +
parity error
Legend:
O: Receive data is transferred from RSR to RDR.
X: Receive data is not transferred from RSR to RDR.
Break Detection and Processing: When a framing error (FER) is detected, a break can be
detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all
0s, and so the FER flag is set, and the parity error flag (PER) may also be set.
Note that, since the SCI continues the receive operation after receiving a break, even if the FER
flag is cleared to 0, it will be set to 1 again.
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Section 15 Serial Communication Interface (SCI)
Sending a Break: The TxD pin has a dual function as an I/O port whose direction (input or
output) is determined by DR and DDR. This feature can be used to send a break.
Between serial transmission initialization and setting of the TE bit to 1, the mark state is replaced
by the value of DR (the pin does not function as the TxD pin until the TE bit is set to 1).
Consequently, DDR and DR for the port corresponding to the TxD pin should first be set to 1.
To send a break during serial transmission, first clear DR to 0, then clear the TE bit to 0.
When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission
state, the TxD pin becomes an I/O port, and 0 is output from the TxD pin.
Receive Error Flags and Transmit Operations (Synchronous Mode Only): Transmission
cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if the TDRE
flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting transmission.
Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared to 0.
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode:
In asynchronous mode, the SCI operates on a base clock with a frequency of 16 times the transfer
rate.
In reception, the SCI samples the falling edge of the start bit using the base clock, and performs
internal synchronization. Receive data is latched internally at the rising edge of the 8th pulse of the
base clock. This is illustrated in figure 15.21.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal base
clock
Receive data
(RxD)
Start bit
D0
Synchronization
sampling timing
Data sampling
timing
Figure 15.21 Receive Data Sampling Timing in Asynchronous Mode
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D1
Section 15 Serial Communication Interface (SCI)
Thus the receive margin in asynchronous mode is given by equation (1) below.
M = 0.5 –
Where M:
N:
D:
L:
F:
1
D – 0.5
(1 + F) × 100%
– (L – 0.5)F –
2N
N
.......... (1)
Receive margin (%)
Ratio of bit rate to clock (N = 16)
Clock duty (D = 0 to 1.0)
Frame length (L = 9 to 12)
Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in equation (1), a receive margin of 46.875% is given by
equation (2) below.
When D = 0.5 and F = 0,
M = 0.5 –
1
× 100%
2 × 16
= 46.875%
.......... (2)
However, this is only a theoretical value, and a margin of 20% to 30% should be allowed in
system design.
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Section 15 Serial Communication Interface (SCI)
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2
Section 16 I C Bus Interface (IIC)
2
Section 16 I C Bus Interface (IIC)
16.1
Overview
2
2
The H8/3577 Group and H8/3567 Group have an on-chip two-channel I C bus interface. The I C
2
bus interface conforms to and provides a subset of the Philips I C bus (inter-IC bus) interface
2
functions. The register configuration that controls the I C bus differs partly from the Philips
configuration, however.
2
Each I C bus interface channel uses only one data line (SDA) and one clock line (SCL) to transfer
data, saving board and connector space.
16.1.1
Features
• Selection of addressing format or non-addressing format
 I C bus format: addressing format with acknowledge bit, for master/slave operation
2
 Serial format: non-addressing format without acknowledge bit, for master operation only
• Conforms to Philips I C bus interface (I C bus format)
2
2
• Two ways of setting slave address (I C bus format)
2
• Start and stop conditions generated automatically in master mode (I C bus format)
2
• Selection of acknowledge output levels when receiving (I C bus format)
2
• Automatic loading of acknowledge bit when transmitting (I C bus format)
2
• Wait function in master mode (I C bus format)
2
A wait can be inserted by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait can be cleared by clearing the interrupt flag.
• Wait function in slave mode (I C bus format)
2
A wait request can be generated by driving the SCL pin low after data transfer, excluding
acknowledgement. The wait request is cleared when the next transfer becomes possible.
• Three interrupt sources
 Data transfer end (including transmission mode transition with I C bus format and address
reception after loss of master arbitration)
2
 Address match: when any slave address matches or the general call address is received in
2
slave receive mode (I C bus format)
 Stop condition detection
• Selection of 16 internal clocks (in master mode)
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Section 16 I C Bus Interface (IIC)
• Direct bus drive (with SCL and SDA pins)
 Two pins—P52/SCL0 and P47/SDA0—(normally NMOS push-pull outputs) function as
NMOS open-drain outputs when the bus drive function is selected.
 Two pins—P24/SCL1 and P23/SDA1 in the H8/3577 Group, and P17/SCL1 and P16/SDA1 in
the H8/3567 Group—(normally CMOS pins) function as NMOS-only outputs when the bus
drive function is selected.
• Automatic switching from formatless mode to I C bus format (channel 0 only)
2
 Formatless operation (no start/stop conditions, non-addressing mode) in slave mode
 Operation using a common data pin (SDA) and independent clock pins (VSYNCI, SCL)
 Automatic switching from formatless mode to I C bus format on the fall of the SCL pin
2
16.1.2
Block Diagram
2
Figure 16.1 shows a block diagram of the I C bus interface.
Figure 16.2 shows an example of I/O pin connections to external circuits. Channel 0 I/O pins and
channel 1 I/O pins differ in structure, and have different specifications for permissible applied
voltages. For details, see section 22, Electrical Characteristics.
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Section 16 I C Bus Interface (IIC)
Formatless dedicated
clock (channel 0 only)
φ
PS
ICCR
SCL
Clock
control
Noise
canceler
Bus state
decision
circuit
SDA
ICSR
Arbitration
decision
circuit
ICDRT
Output data
control
circuit
ICDRS
Internal data bus
ICMR
ICDRR
Noise
canceler
Address
comparator
SAR, SARX
Interrupt
generator
Legend:
ICCR: I2C bus control register
ICMR: I2C bus mode register
ICSR: I2C bus status register
ICDR: I2C bus data register
SAR: Slave address register
SARX: Slave address register X
PS:
Prescaler
Interrupt
request
2
Figure 16.1 Block Diagram of I C Bus Interface
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Section 16 I C Bus Interface (IIC)
Vcc
Vcc
SCL
SCL
SDA
SDA
SCL in
SDA in
SCL
SDA
SDA out
(Master)
SCL in
H8/3577 Group or
H8/3567 Group
chip
SCL out
SCL out
SDA in
SDA in
SDA out
SDA out
SCL
SDA
SCL out
SCL in
(Slave 1)
(Slave 2)
2
Figure 16.2 I C Bus Interface Connections
(Example: H8/3577 Group or H8/3567 Group Chip as Master)
16.1.3
Input/Output Pins
2
Table 16.1 summarizes the input/output pins used by the I C bus interface.
2
Table 16.1 I C Bus Interface Pins
Channel
Name
Abbreviation*
I/O
Function
0
Serial clock
SCL0
I/O
IIC0 serial clock input/output
Serial data
SDA0
I/O
IIC0 serial data input/output
Formatless
serial clock
VSYNCI
Input
IIC0 formatless
serial clock input
Serial clock
SCL1
I/O
IIC1 serial clock input/output
Serial data
SDA1
I/O
IIC1 serial data input/output
1
Note:
*
In the text, the channel subscript is omitted, and only SCL and SDA are used.
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Section 16 I C Bus Interface (IIC)
16.1.4
Register Configuration
2
Table 16.2 summarizes the registers of the I C bus interface.
Table 16.2 Register Configuration
Channel
Name
Abbreviation
R/W
Initial Value
Address
2
ICCR0
R/W
H'01
H'FFD8
2
ICSR0
R/W
H'00
H'FFD9
2
ICDR0
R/W
—
I C bus mode register
ICMR0
R/W
H'00
H'FFDE*
H'FFDF*
Slave address register
SAR0
R/W
H'00
Second slave address
register
SARX0
R/W
H'01
H'FFDF*
H'FFDE*
2
ICCR1
R/W
H'01
H'FF88
2
ICSR1
R/W
H'00
H'FF89
2
ICDR1
R/W
—
2
I C bus mode register
ICMR1
R/W
H'00
H'FF8E*
H'FF8F*
Slave address register
SAR1
R/W
H'00
Second slave address
register
SARX1
R/W
H'01
H'FF8F*
H'FF8E*
Serial timer control
register
STCR
R/W
H'00
H'FFC3
DDC switch register
DDCSWR
R/W
H'0F
H'FEE6
Module stop control
register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
I C bus control register
0
I C bus status register
I C bus data register
2
1
I C bus control register
I C bus status register
I C bus data register
Common
Note:
*
H'FF87
2
The register that can be written or read depends on the ICE bit in the I C bus control
2
register. The slave address register can be accessed when ICE = 0, and the I C bus
mode register can be accessed when ICE = 1.
2
The I C bus interface registers are assigned to the same addresses as other registers.
Register selection is performed by means of the IICE bit in the serial timer control
register (STCR).
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Section 16 I C Bus Interface (IIC)
16.2
Register Descriptions
16.2.1
I C Bus Data Register (ICDR)
2
Bit
7
6
5
4
3
2
1
0
ICDR7
ICDR6
ICDR5
ICDR4
ICDR3
ICDR2
ICDR1
ICDR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
• ICDRR
Bit
ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
• ICDRS
Bit
ICDRS7 ICDRS6 ICDRS5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0
Initial value
—
—
—
—
—
—
—
—
Read/Write
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
ICDRT4
ICDRT3
ICDRT2
ICDRT1
ICDRT0
• ICDRT
Bit
ICDRT7
ICDRT6 ICDRT5
Initial value
—
—
—
—
—
—
—
—
Read/Write
W
W
W
W
W
W
W
W
• TDRE, RDRF (internal flags)
Bit
—
—
TDRE
RDRF
Initial value
0
0
Read/Write
—
—
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Section 16 I C Bus Interface (IIC)
ICDR is an 8-bit readable/writable register that is used as a transmit data register when
transmitting and a receive data register when receiving. ICDR is divided internally into a shift
register (ICDRS), receive buffer (ICDRR), and transmit buffer (ICDRT). ICDRS cannot be read or
written by the CPU, ICDRR is read-only, and ICDRT is write-only. Data transfers among the
three registers are performed automatically in coordination with changes in the bus state, and
affect the status of internal flags such as TDRE and RDRF.
If IIC is in transmit mode and the next data is in ICDRT (the TDRE flag is 0) following
transmission of one frame of data using ICDRS, data is transferred automatically from ICDRT to
ICDRS. If the IIC is in receive mode and none of the previous data remains in ICDRR (the RDRF
flag is 0), after one frame of data has been received normally in ICDRS, the data is transferred
automatically from ICDRS to ICDRR.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
ICDR is assigned to the same address as SARX, and can be written and read only when the ICE
bit is set to 1 in ICCR.
The value of ICDR is undefined after a reset.
The TDRE and RDRF flags are set and cleared under the conditions shown below. Setting the
TDRE and RDRF flags affects the status of the interrupt flags.
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Section 16 I C Bus Interface (IIC)
TDRE
Description
0
The next transmit data is in ICDR (ICDRT), or transmission cannot
be started
(Initial value)
[Clearing conditions]
•
When transmit data is written in ICDR (ICDRT) in transmit mode (TRS = 1)
•
When a stop condition is detected in the bus line state after a stop condition is
2
issued with the I C bus format or serial format selected
•
When a stop condition is detected with the I C bus format selected
•
In receive mode (TRS = 0)
2
(A 0 write to TRS during transfer is valid after reception of a frame containing an
acknowledge bit)
1
The next transmit data can be written in ICDR (ICDRT)
[Setting conditions]
•
In transmit mode (TRS = 1), when a start condition is detected in the bus line state
2
after a start condition is issued in master mode with the I C bus format or serial
format selected
•
When using formatless mode in transmit mode (TRS = 1)
•
When data is transferred from ICDRT to ICDRS
(Data transfer from ICDRT to ICDRS when TRS = 1 and TDRE = 0, and ICDRS is
empty)
•
When a switch is made from receive mode (TRS = 0) to transmit mode (TRS = 1 )
after detection of a start condition
RDRF
Description
0
The data in ICDR (ICDRR) is invalid
(Initial value)
[Clearing condition]
When ICDR (ICDRR) receive data is read in receive mode
1
The ICDR (ICDRR) receive data can be read
[Setting condition]
When data is transferred from ICDRS to ICDRR
(Data transfer from ICDRS to ICDRR in case of normal termination with TRS = 0 and
RDRF = 0)
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Section 16 I C Bus Interface (IIC)
16.2.2
Slave Address Register (SAR)
Bit
7
6
5
4
3
2
1
0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SAR is an 8-bit readable/writable register that stores the slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SAR match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SAR is assigned to the same
address as ICMR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SAR is initialized to H'00 by a reset and in hardware standby mode.
Bits 7 to 1—Slave Address (SVA6 to SVA0): Set a unique address in bits SVA6 to SVA0,
2
differing from the addresses of other slave devices connected to the I C bus.
Bit 0—Format Select (FS): Used together with the FSX bit in SARX and the SW bit in
DDCSWR to select the communication format.
• I C bus format: addressing format with acknowledge bit
2
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
• Formatless mode (channel 0 only): non-addressing format with or without acknowledge bit,
slave mode only, start/stop conditions not detected
The FS bit also specifies whether or not SAR slave address recognition is performed in slave
mode.
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Section 16 I C Bus Interface (IIC)
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW
FS
FSX
Operating Mode
0
0
0
I C bus format
2
•
1
1
0
1
0
1
SAR slave address recognized
•
SARX slave address ignored
2
I C bus format
•
SAR slave address ignored
•
SARX slave address recognized
Synchronous serial format
Formatless mode (start/stop conditions not detected)
1
•
Acknowledge bit used
0
Formatless mode* (start/stop conditions not detected)
•
*
SAR and SARX slave addresses ignored
0
1
Note:
(Initial value)
•
•
1
SAR and SARX slave addresses recognized
2
I C bus format
No acknowledge bit
2
Do not set this mode when automatic switching to the I C bus format is performed by
means of the DDCSWR setting.
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Section 16 I C Bus Interface (IIC)
16.2.3
Second Slave Address Register (SARX)
Bit
7
6
5
4
3
2
1
0
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
SARX is an 8-bit readable/writable register that stores the second slave address and selects the
communication format. When the chip is in slave mode (and the addressing format is selected), if
the upper 7 bits of SARX match the upper 7 bits of the first frame received after a start condition,
the chip operates as the slave device specified by the master device. SARX is assigned to the same
address as ICDR, and can be written and read only when the ICE bit is cleared to 0 in ICCR.
SARX is initialized to H'01 by a reset and in hardware standby mode.
Bits 7 to 1—Second Slave Address (SVAX6 to SVAX0): Set a unique address in bits SVAX6 to
2
SVAX0, differing from the addresses of other slave devices connected to the I C bus.
Bit 0—Format Select X (FSX): Used together with the FS bit in SAR and the SW bit in
DDCSWR to select the communication format.
• I C bus format: addressing format with acknowledge bit
2
• Synchronous serial format: non-addressing format without acknowledge bit, for master mode
only
• Formatless mode: non-addressing format with or without acknowledge bit, slave mode only,
start/stop conditions not detected
The FSX bit also specifies whether or not SARX slave address recognition is performed in slave
mode. For details, see the description of the FS bit in SAR.
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Section 16 I C Bus Interface (IIC)
16.2.4
2
I C Bus Mode Register (ICMR)
Bit
7
6
5
4
3
2
1
0
MLS
WAIT
CKS2
CKS1
CKS0
BC2
BC1
BC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ICMR is an 8-bit readable/writable register that selects whether the MSB or LSB is transferred
first, performs master mode wait control, and selects the master mode transfer clock frequency and
the transfer bit count. ICMR is assigned to the same address as SAR. ICMR can be written and
read only when the ICE bit is set to 1 in ICCR.
ICMR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—MSB-First/LSB-First Select (MLS): Selects whether data is transferred MSB-first or
LSB-first.
If the number of bits in a frame, excluding the acknowledge bit, is less than 8, transmit data and
receive data are stored differently. Transmit data should be written justified toward the MSB side
when MLS = 0, and toward the LSB side when MLS = 1. Receive data bits read from the LSB
side should be treated as valid when MLS = 0, and bits read from the MSB side when MLS = 1.
2
Do not set this bit to 1 when the I C bus format is used.
Bit 7
MLS
Description
0
MSB-first
1
LSB-first
(Initial value)
Bit 6—Wait Insertion Bit (WAIT): Selects whether to insert a wait between the transfer of data
2
and the acknowledge bit, in master mode with the I C bus format. When WAIT is set to 1, after the
fall of the clock for the final data bit, the IRIC flag is set to 1 in ICCR, and a wait state begins
(with SCL at the low level). When the IRIC flag is cleared to 0 in ICCR, the wait ends and the
acknowledge bit is transferred. If WAIT is cleared to 0, data and acknowledge bits are transferred
consecutively with no wait inserted.
The IRIC flag in ICCR is set to 1 on completion of the acknowledge bit transfer, regardless of the
WAIT setting.
The setting of this bit is invalid in slave mode.
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Section 16 I C Bus Interface (IIC)
Bit 6
WAIT
Description
0
Data and acknowledge bits transferred consecutively
1
Wait inserted between data and acknowledge bits
(Initial value)
Bits 5 to 3—Serial Clock Select (CKS2 to CKS0): These bits, together with the IICX1 (channel
1) or IICX0 (channel 0) bit in the STCR register, select the serial clock frequency in master mode.
They should be set according to the required transfer rate.
STCR
Bit 5 or 6 Bit 5 Bit 4 Bit 3
Transfer Rate
IICX
CKS2 CKS1 CKS0 Clock
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note:
*
φ=
5 MHz
φ=
8 MHz
φ=
10 MHz
φ=
16 MHz
φ=
20 MHz
0
φ/28
179 kHz
286 kHz
357 kHz
571 kHz*
1
φ/40
125 kHz
200 kHz
250 kHz
400 kHz
714 kHz*
500 kHz*
0
φ/48
104 kHz
167 kHz
208 kHz
333 kHz
417 kHz*
1
φ/64
78.1 kHz
125 kHz
156 kHz
250 kHz
313 kHz
0
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
1
φ/100
50.0 kHz
80.0 kHz
100 kHz
160 kHz
200 kHz
0
φ/112
44.6 kHz
71.4 kHz
89.3 kHz
143 kHz
179 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
0
φ/56
89.3 kHz
143 kHz
179 kHz
286 kHz
357 kHz
1
φ/80
62.5 kHz
100 kHz
125 kHz
200 kHz
250 kHz
0
φ/96
52.1 kHz
83.3 kHz
104 kHz
167 kHz
208 kHz
1
φ/128
39.1 kHz
62.5 kHz
78.1 kHz
125 kHz
156 kHz
0
φ/160
31.3 kHz
50.0 kHz
62.5 kHz
100 kHz
125 kHz
1
φ/200
25.0 kHz
40.0 kHz
50.0 kHz
80.0 kHz
100 kHz
0
φ/224
22.3 kHz
35.7 kHz
44.6 kHz
71.4 kHz
89.3 kHz
1
φ/256
19.5 kHz
31.3 kHz
39.1 kHz
62.5 kHz
78.1 kHz
2
Outside the I C bus interface specification range (normal mode: max. 100 kHz; highspeed mode: max. 400 kHz).
Bits 2 to 0—Bit Counter (BC2 to BC0): Bits BC2 to BC0 specify the number of bits to be
2
transferred next. With the I C bus format (when the FS bit in SAR or the FSX bit in SARX is 0),
the data is transferred with one addition acknowledge bit. Bits BC2 to BC0 settings should be
made during an interval between transfer frames. If bits BC2 to BC0 are set to a value other than
000, the setting should be made while the SCL line is low.
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Section 16 I C Bus Interface (IIC)
The bit counter is initialized to 000 by a reset and when a start condition is detected. The value
returns to 000 at the end of a data transfer, including the acknowledge bit.
Bit 2
Bit 1
Bit 0
BC2
BC1
BC0
Synchronous Serial Format
I C Bus Format
0
0
0
8
9
1
1
2
0
2
3
1
3
4
0
4
5
1
5
6
0
6
7
1
7
8
1
1
0
1
Bits/Frame
2
(Initial value)
2
16.2.5
I C Bus Control Register (ICCR)
Bit
7
6
5
4
3
2
1
0
ICE
IEIC
MST
TRS
ACKE
BBSY
IRIC
SCP
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*
W
Note:
*
Only 0 can be written, to clear the flag.
2
ICCR is an 8-bit readable/writable register that enables or disables the I C bus interface, enables or
disables interrupts, selects master or slave mode and transmission or reception, enables or disables
2
acknowledgement, confirms the I C bus interface bus status, issues start/stop conditions, and
performs interrupt flag confirmation.
ICCR is initialized to H'01 by a reset and in hardware standby mode.
2
2
Bit 7—I C Bus Interface Enable (ICE): Selects whether or not the I C bus interface is to be
used. When ICE is set to 1, port pins function as SCL and SDA input/output pins and transfer
operations are enabled. When ICE bit is cleared to 0, the module stops the functions and clears the
internal state.
The SAR and SARX registers can be accessed when ICE is 0. The ICMR and ICDR registers can
be accessed when ICE is 1.
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Section 16 I C Bus Interface (IIC)
Bit 7
ICE
Description
0
I C bus interface module disabled, with SCL and SDA signal pins set to port function
(Initial value)
2
Initialization of IIC module internal state
SAR and SARX can be accessed
2
1
I C bus interface module enabled for transfer operations (pins SCL and SCA are
driving the bus)
ICMR and ICDR can be accessed
2
2
Bit 6—I C Bus Interface Interrupt Enable (IEIC): Enables or disables interrupts from the I C
bus interface to the CPU.
Bit 6
IEIC
Description
0
Interrupts disabled
1
Interrupts enabled
(Initial value)
Bit 5—Master/Slave Select (MST)
Bit 4—Transmit/Receive Select (TRS)
2
MST selects whether the I C bus interface operates in master mode or slave mode.
2
TRS selects whether the I C bus interface operates in transmit mode or receive mode.
2
In master mode with the I C bus format, when arbitration is lost, MST and TRS are both reset by
hardware, causing a transition to slave receive mode. In slave receive mode with the addressing
format (FS = 0 or FSX = 0), hardware automatically selects transmit or receive mode according to
the R/W bit in the first frame after a start condition.
Modification of the TRS bit during transfer is deferred until transfer of the frame containing the
acknowledge bit is completed, and the changeover is made after completion of the transfer.
MST and TRS select the operating mode as follows.
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Section 16 I C Bus Interface (IIC)
Bit 5
Bit 4
MST
TRS
Operating Mode
0
0
Slave receive mode
1
Slave transmit mode
0
Master receive mode
1
Master transmit mode
1
(Initial value)
Bit 5
MST
Description
0
Slave mode
(Initial value)
[Clearing conditions]
1. When 0 is written by software
2
2. When bus arbitration is lost after transmission is started in I C bus format master
mode
1
Master mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing condition 2)
2. When 1 is written in MST after reading MST = 0 (in case of clearing condition 2)
Bit 4
TRS
Description
0
Receive mode
(Initial value)
[Clearing conditions]
1. When 0 is written by software (in cases other than setting condition 3)
2. When 0 is written in TRS after reading TRS = 1 (in case of clearing condition 3)
2
3. When bus arbitration is lost after transmission is started in I C bus format master
mode
4. When the SW bit in DDCSWR changes from 1 to 0
1
Transmit mode
[Setting conditions]
1. When 1 is written by software (in cases other than clearing conditions 3 and 4)
2. When 1 is written in TRS after reading TRS = 0 (in case of clearing conditions 3
and 4)
2
3. When a 1 is received as the R/W bit of the first frame in I C bus format slave mode
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Section 16 I C Bus Interface (IIC)
Bit 3—Acknowledge Bit Judgement Selection (ACKE): Specifies whether the value of the
2
acknowledge bit returned from the receiving device when using the I C bus format is to be ignored
and continuous transfer is performed, or transfer is to be aborted and error handling, etc.,
performed if the acknowledge bit is 1. When the ACKE bit is 0, the value of the received
acknowledge bit is not indicated by the ACKB bit, which is always 0.
Bit 3
ACKE
Description
0
The value of the acknowledge bit is ignored, and continuous transfer is performed
(Initial value)
1
If the acknowledge bit is 1, continuous transfer is interrupted
2
Bit 2—Bus Busy (BBSY): The BBSY flag can be read to check whether the I C bus (SCL, SDA)
is busy or free. In master mode, this bit is also used to issue start and stop conditions.
A high-to-low transition of SDA while SCL is high is recognized as a start condition, setting
BBSY to 1. A low-to-high transition of SDA while SCL is high is recognized as a stop condition,
clearing BBSY to 0.
To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit start condition is issued in
the same way. To issue a stop condition, use a MOV instruction to write 0 in BBSY and 0 in SCP.
2
It is not possible to write to BBSY in slave mode; the I C bus interface must be set to master
transmit mode before issuing a start condition. MST and TRS should both be set to 1 before
writing 1 in BBSY and 0 in SCP.
Bit 2
BBSY
Description
0
Bus is free
(Initial value)
[Clearing condition]
When a stop condition is detected
1
Bus is busy
[Setting condition]
When a start condition is detected
2
2
Bit 1—I C Bus Interface Interrupt Request Flag (IRIC): Indicates that the I C bus interface has
issued an interrupt request to the CPU. IRIC is set to 1 at the end of a data transfer, when a slave
address or general call address is detected in slave receive mode, when bus arbitration is lost in
master transmit mode, and when a stop condition is detected. IRIC is set at different times
depending on the FS bit in SAR and the WAIT bit in ICMR. See section 16.3.6, IRIC Setting
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Section 16 I C Bus Interface (IIC)
Timing and SCL Control. The conditions under which IRIC is set also differ depending on the
setting of the ACKE bit in ICCR.
IRIC is cleared by reading IRIC after it has been set to 1, then writing 0 in IRIC.
Bit 1
IRIC
Description
0
Waiting for transfer, or transfer in progress
[Clearing condition]
When 0 is written in IRIC after reading IRIC = 1
1
Interrupt requested
[Setting conditions]
• I2C bus format master mode
 When a start condition is detected in the bus line state after a start condition is issued
(when the TDRE flag is set to 1 because of first frame transmission)
 When a wait is inserted between the data and acknowledge bit when WAIT = 1
 At the end of data transfer
(at the rise of the 9th transmit/receive clock pulse, and, when a wait is inserted, at the fall
of the 8th transmit/receive clock pulse)
 When a slave address is received after bus arbitration is lost
(when the AL flag is set to 1)
 When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
• I2C bus format slave mode
 When the slave address (SVA, SVAX) matches
(when the AAS and AASX flags are set to 1)
and at the end of data transfer up to the subsequent retransmission start condition or
stop condition detection
(when the TDRE or RDRF flag is set to 1)
 When the general call address is detected
(when the FS = 0 and the ADZ flag is set to 1)
and at the end of data transfer up to the subsequent retransmission start condition or
stop condition detection
(when the TDRE or RDRF flag is set to 1)
 When 1 is received as the acknowledge bit when the ACKE bit is 1
(when the ACKB bit is set to 1)
 When a stop condition is detected
(when the STOP or ESTP flag is set to 1)
• Synchronous serial format, and formatless mode
 At the end of data transfer
(when the TDRE or RDRF flag is set to 1)
 When a start condition is detected with serial format selected
 When the SW bit is set to 1 in DDCSWR
Besides the above, when a condition that sets the TDRE or RDRF internal flag to 1 occurs
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(Initial value)
2
Section 16 I C Bus Interface (IIC)
2
When, with the I C bus format selected, IRIC is set to 1 and an interrupt is generated, other flags
must be checked in order to identify the source that set IRIC to 1. Although each source has a
corresponding flag, caution is needed at the end of a transfer.
When the TDRE or RDRF internal flag is set, the readable IRTR flag may or may not be set. The
IRTR flag is not set at the end of a data transfer up to detection of a retransmission start condition
2
or stop condition after a slave address (SVA) or general call address match in I C bus format slave
mode.
Even when the IRIC flag and IRTR flag are set, the TDRE or RDRF internal flag may not be set.
Table 16.3 shows the relationship between the flags and the transfer states.
Table 16.3 Flags and Transfer States
MST TRS BBSY ESTP STOP IRTR AASX AL
AAS ADZ
ACKB State
1/0
1/0
0
0
0
0
0
0
0
0
0
Idle state (flag
clearing required)
1
1
0
0
0
0
0
0
0
0
0
Start condition
issuance
1
1
1
0
0
1
0
0
0
0
0
Start condition
established
1
1/0
1
0
0
0
0
0
0
0
0/1
Master mode wait
1
1/0
1
0
0
1
0
0
0
0
0/1
Master mode
transmit/receive end
0
0
1
0
0
0
1/0
1
1/0
1/0
0
Arbitration lost
0
0
1
0
0
0
0
0
1
0
0
SAR match by first
frame in slave mode
0
0
1
0
0
0
0
0
1
1
0
General call
address match
0
0
1
0
0
0
1
0
0
0
0
SARX match
0
1/0
1
0
0
0
0
0
0
0
0/1
Slave mode
transmit/receive end
(except after SARX
match)
0
1/0
1
0
0
1
1
0
0
0
0
0
1
1
0
0
0
1
0
0
0
1
Slave mode
transmit/receive end
(after SARX match)
0
1/0
0
1/0
1/0
0
0
0
0
0
0/1
Stop condition
detected
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Section 16 I C Bus Interface (IIC)
Bit 0—Start Condition/Stop Condition Prohibit (SCP): Controls the issuing of start and stop
conditions in master mode. To issue a start condition, write 1 in BBSY and 0 in SCP. A retransmit
start condition is issued in the same way. To issue a stop condition, write 0 in BBSY and 0 in SCP.
This bit is always read as 1. If 1 is written, the data is not stored.
Bit 0
SCP
Description
0
Writing 0 issues a start or stop condition, in combination with the BBSY flag
1
Reading always returns a value of 1
(Initial value)
Writing is ignored
2
16.2.6
I C Bus Status Register (ICSR)
Bit
7
6
5
4
3
2
1
0
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
Note:
*
Only 0 can be written, to clear the flags.
ICSR is an 8-bit readable/writable register that performs flag confirmation and acknowledge
confirmation and control.
ICSR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Error Stop Condition Detection Flag (ESTP): Indicates that a stop condition has been
2
detected during frame transfer in I C bus format slave mode.
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Section 16 I C Bus Interface (IIC)
Bit 7
ESTP
Description
0
No error stop condition
(Initial value)
[Clearing conditions]
1
•
When 0 is written in ESTP after reading ESTP = 1
•
When the IRIC flag is cleared to 0
•
In I C bus format slave mode
2
Error stop condition detected
[Setting condition]
When a stop condition is detected during frame transfer
•
In other modes
No meaning
Bit 6—Normal Stop Condition Detection Flag (STOP): Indicates that a stop condition has been
2
detected after completion of frame transfer in I C bus format slave mode.
Bit 6
STOP
Description
0
No normal stop condition
(Initial value)
[Clearing conditions]
1
•
When 0 is written in STOP after reading STOP = 1
•
When the IRIC flag is cleared to 0
•
In I C bus format slave mode
2
Normal stop condition detected
[Setting condition]
When a stop condition is detected after completion of frame transfer
•
In other modes
No meaning
2
Bit 5—I C Bus Interface Continuous Transmission/Reception Interrupt Request Flag
2
(IRTR): Indicates that the I C bus interface has issued an interrupt request to the CPU, and the
source is completion of reception/transmission of one frame in continuous transmission/reception
for which DTC activation is possible. As the H8/3577 Group and H8/3567 Group do not have an
on-chip DTC, the IRTR flag is used by the CPU to determine the source that set IRIC. When the
IRTR flag is set to 1, the IRIC flag is also set to 1 at the same time.
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Section 16 I C Bus Interface (IIC)
IRTR flag setting is performed when the TDRE or RDRF flag is set to 1. IRTR is cleared by
reading IRTR after it has been set to 1, then writing 0 in IRTR. IRTR is also cleared automatically
when the IRIC flag is cleared to 0.
Bit 5
IRTR
Description
0
Waiting for transfer, or transfer in progress
(Initial value)
[Clearing conditions]
1
•
When 0 is written in IRTR after reading IRTR = 1
•
When the IRIC flag is cleared to 0
Continuous transfer state
[Setting conditions]
•
2
In I C bus interface slave mode
When the TDRE or RDRF flag is set to 1 when AASX = 1
•
In other modes
When the TDRE or RDRF flag is set to 1
2
Bit 4—Second Slave Address Recognition Flag (AASX): In I C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition matches bits SVAX6 to SVAX0 in
SARX.
AASX is cleared by reading AASX after it has been set to 1, then writing 0 in AASX. AASX is
also cleared automatically when a start condition is detected.
Bit 4
AASX
Description
0
Second slave address not recognized
(Initial value)
[Clearing conditions]
1
•
When 0 is written in AASX after reading AASX = 1
•
When a start condition is detected
•
In master mode
Second slave address recognized
[Setting condition]
When the second slave address is detected in slave receive mode while FSX = 0
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Section 16 I C Bus Interface (IIC)
Bit 3—Arbitration Lost (AL): This flag indicates that arbitration was lost in master mode. The
2
I C bus interface monitors the SDA. When two or more master devices attempt to seize the bus at
2
nearly the same time, if the I C bus interface detects data differing from the data it sent, it sets AL
to 1 to indicate that the bus has been taken by another master.
AL is cleared by reading AL after it has been set to 1, then writing 0 in AL. In addition, AL is
reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 3
AL
Description
0
Bus arbitration won
(Initial value)
[Clearing conditions]
1
•
When ICDR data is written (transmit mode) or read (receive mode)
•
When 0 is written in AL after reading AL = 1
Arbitration lost
[Setting conditions]
•
If the internal SDA and SDA pin disagree at the rise of SCL in master transmit
mode
•
If the internal SCL line is high at the fall of SCL in master transmit mode
2
Bit 2—Slave Address Recognition Flag (AAS): In I C bus format slave receive mode, this flag is
set to 1 if the first frame following a start condition matches bits SVA6 to SVA0 in SAR, or if the
general call address (H'00) is detected.
AAS is cleared by reading AAS after it has been set to 1, then writing 0 in AAS. In addition, AAS
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
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Section 16 I C Bus Interface (IIC)
Bit 2
AAS
Description
0
Slave address or general call address not recognized
(Initial value)
[Clearing conditions]
1
•
When ICDR data is written (transmit mode) or read (receive mode)
•
When 0 is written in AAS after reading AAS = 1
•
In master mode
Slave address or general call address recognized
[Setting condition]
When the slave address or general call address is detected in slave receive mode
while FS = 0
2
Bit 1—General Call Address Recognition Flag (ADZ): In I C bus format slave receive mode,
this flag is set to 1 if the first frame following a start condition is the general call address (H'00).
ADZ is cleared by reading ADZ after it has been set to 1, then writing 0 in ADZ. In addition, ADZ
is reset automatically by write access to ICDR in transmit mode, or read access to ICDR in receive
mode.
Bit 1
ADZ
Description
0
General call address not recognized
(Initial value)
[Clearing conditions]
1
•
When ICDR data is written (transmit mode) or read (receive mode)
•
When 0 is written in ADZ after reading ADZ = 1
•
In master mode
General call address recognized
[Setting condition]
When the general call address is detected in slave receive mode while FSX = 0 or
FS = 0
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Section 16 I C Bus Interface (IIC)
Bit 0—Acknowledge Bit (ACKB): Stores acknowledge data. In transmit mode, after the
receiving device receives data, it returns acknowledge data, and this data is loaded into ACKB. In
receive mode, after data has been received, the acknowledge data set in this bit is sent to the
transmitting device.
When this bit is read, in transmission (when TRS = 1), the value loaded from the bus line
(returned by the receiving device) is read. In reception (when TRS = 0), the value set by internal
software is read.
Also, when this bit is written, the set value of the acknowledge data to be issued upon receiving is
rewritten, regardless of the TRS value. Since the value loaded from the receiving device is held, as
is, in this case, care is required when rewriting this register using a bit operation command.
Bit 0
ACKB
Description
0
Receive mode: 0 is output at acknowledge output timing
(Initial value)
Transmit mode: Indicates that the receiving device has acknowledged the data (signal
is 0)
1
Receive mode: 1 is output at acknowledge output timing
Transmit mode: Indicates that the receiving device has not acknowledged the data
(signal is 1)
16.2.7
Serial Timer Control Register (STCR)
Bit
7
6
5
4
3
2
1
0
—
IICX1
IICX0
IICE
—
USBE
ICKS1
ICKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
STCR is an 8-bit readable/writable register that controls register access, the IIC interface operating
mode (when the on-chip IIC option is included), selects the TCNT input clock source, and controls
2
the USB. For details of functions not related to the I C bus interface, see section 3.2.3, Serial
Timer Control Register (STCR), and the descriptions of the relevant modules. If a module
controlled by STCR is not used, do not write 1 to the corresponding bit.
STCR is initialized to H'00 by a reset and in hardware standby mode.
Bit 7—Reserved: This bit must not be set to 1.
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Section 16 I C Bus Interface (IIC)
2
Bits 6 and 5—I C Transfer Select 1 and 0 (IICX1, IICX0): These bits, together with bits CKS2
2
to CKS0 in ICMR, select the transfer rate in master mode. For details, see section 16.2.4, I C Bus
Mode Register (ICMR).
2
2
Bit 4—I C Master Enable (IICE): Controls CPU access to the I C bus interface data and control
registers (ICCR, ICSR, ICDR/SARX, ICMR/SAR).
Bit 4
IICE
Description
0
CPU access to I C bus interface data and control registers is disabled
2
(Initial value)
2
1
CPU access to I C bus interface data and control registers is enabled
Bit 3—Reserved: This bit must not be set to 1.
Bit 2—USB Enable (USBE): This bit controls CPU access to the USB data register and control
register.
Bit 2
USBE
Description
0
Prohibition of the above register access
1
Permission of the above register access
(Initial value)
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICSK0): These bits, together with
bits CKS2 to CKS0 in TCR, select the clock input to the timer counters (TCNT). For details, see
section 12.2.4, Timer Control Register.
16.2.8
DDC Switch Register (DDCSWR)
Bit
Initial value
Read/Write
7
6
5
4
3
2
1
0
SWE
SW
IE
IF
CLR3
CLR2
CLR1
CLR0
0
0
0
0
R/W
R/(W)*
1
2
W*
1
2
W*
1
2
W*
1
2
W*
R/W
R/W
1
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
DDCSWR is an 8-bit readable/writable register that controls the IIC channel 0 automatic format
switching function.
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Section 16 I C Bus Interface (IIC)
DDCSWR is initialized to H'0F by a reset and in hardware standby mode.
Bit 7—DDC Mode Switch Enable (SWE): Selects the function for automatically switching IIC
2
channel 0 from formatless mode to the I C bus format.
Bit 7
SWE
Description
0
Automatic switching of IIC channel 0 from formatless mode to I C bus format is
disabled
(Initial value)
1
Automatic switching of IIC channel 0 from formatless mode to I C bus format is
enabled
2
2
2
Bit 6—DDC Mode Switch (SW): Selects either formatless mode or the I C bus format for IIC
channel 0.
Bit 6
SW
Description
0
IIC channel 0 is used with the I C bus format
2
(Initial value)
[Clearing conditions]
1
•
When 0 is written by software
•
When a falling edge is detected on the SCL pin when SWE = 1
IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
Bit 5—DDC Mode Switch Interrupt Enable Bit (IE): Enables or disables an interrupt request to
the CPU when automatic format switching is executed for IIC channel 0.
Bit 5
IE
Description
0
Interrupt when automatic format switching is executed is disabled
1
Interrupt when automatic format switching is executed is enabled
(Initial value)
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Section 16 I C Bus Interface (IIC)
Bit 4—DDC Mode Switch Interrupt Flag (IF): Flag that indicates an interrupt request to the
CPU when automatic format switching is executed for IIC channel 0.
Bit 4
IF
Description
0
No interrupt is requested when automatic format switching is executed (Initial value)
[Clearing condition]
When 0 is written in IF after reading IF = 1
1
An interrupt is requested when automatic format switching is executed
[Setting condition]
When a falling edge is detected on the SCL pin when SWE = 1
Bits 3 to 0—IIC Clear 3 to 0 (CLR3 to CLR0): These bits control initialization of the internal
state of IIC0 and IIC1.
These bits can only be written to; if read they will always return a value of 1.
When a write operation is performed on these bits, a clear signal is generated for the internal latch
circuit of the corresponding module(s), and the internal state of the IIC module(s) is initialized.
The write data for these bits is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be
written to simultaneously using an MOV instruction. Do not use a bit manipulation instruction
such as BCLR.
When clearing is required again, all the bits must be writen to in accordance with the setting.
Bit 3
Bit 2
Bit 1
Bit 0
CLR3
CLR2
CLR1
CLR0
Description
0
0
—
—
Setting prohibited
1
0
0
Setting prohibited
1
IIC0 internal latch cleared
0
IIC1 internal latch cleared
1
IIC0 and IIC1 internal latches cleared
—
Invalid setting
1
1
—
—
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Section 16 I C Bus Interface (IIC)
16.2.9
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers, and is used to perform module stop
mode control.
When the MSTP4 or MSTP3 bit is set to 1, operation of the corresponding IIC channel is halted at
the end of the bus cycle, and a transition is made to module stop mode. For details, see section
21.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRL Bit 4—Module Stop (MSTP4): Specifies IIC channel 0 module stop mode.
MSTPCRL
Bit 4
MSTP4
Description
0
IIC channel 0 module stop mode is cleared
1
IIC channel 0 module stop mode is set
(Initial value)
MSTPCRL Bit 3—Module Stop (MSTP3): Specifies IIC channel 1 module stop mode.
MSTPCRL
Bit 3
MSTP3
Description
0
IIC channel 1 module stop mode is cleared
1
IIC channel 1 module stop mode is set
(Initial value)
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Section 16 I C Bus Interface (IIC)
16.3
Operation
16.3.1
I C Bus Data Format
2
2
2
The I C bus interface has serial and I C bus formats.
2
The I C bus formats are addressing formats with an acknowledge bit. These are shown in figures
16.3 (a) and (b). The first frame following a start condition always consists of 8 bits.
IIC channel 0 only is capable of formatless operation, as shown in figure 16.3 (c).
The serial format is a non-addressing format with no acknowledge bit. This is shown in figure
16.4.
2
Figure 16.5 shows the I C bus timing.
The symbols used in figures 16.3 to 16.5 are explained in table 16.4.
(a) I2C bus format (FS = 0 or FSX = 0)
S
SLA
R/W
A
DATA
A
A/A
P
1
7
1
1
n
1
1
1
1
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
m
(b) I2C bus format (start condition retransmission, FS = 0 or FSX = 0)
S
SLA
R/W
A
DATA
A/A
S
SLA
R/W
A
DATA
A/A
P
1
7
1
1
n1
1
1
7
1
1
n2
1
1
1
m1
1
m2
n1 and n2: transfer bit count (n1 and n2 = 1 to 8)
m1 and m2: transfer frame count (m1 and m2 ≥ 1)
(c) Formatless (IIC0 only, FS = 0 or FSX = 0)
DATA
A
8
1
DATA
n
A
A/A
1
1
1
m
2
n: transfer bit count (n = 1 to 8)
m: transfer frame count (m ≥ 1)
2
Figure 16.3 I C Bus Data Formats (I C Bus Formats)
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Section 16 I C Bus Interface (IIC)
FS = 1 and FSX = 1
S
DATA
DATA
P
1
8
n
1
1
m
n: transfer bit count
(n = 1 to 8)
m: transfer frame count
(m ≥ 1)
2
Figure 16.4 I C Bus Data Format (Serial Format)
SDA
SCL
S
1-7
8
9
SLA
R/W
A
1-7
8
DATA
9
A
1-7
8
DATA
9
A/A
P
2
Figure 16.5 I C Bus Timing
2
Table 16.4 Description of I C Bus Data Format Symbols
S
Indicates a start condition. When SCL is high level, the master device changes SDA
from high to low level.
SLA
Indicates a slave address. The master device selects the slave device.
R/W
Indicates the transmit/receive direction. When the value of the R/W bit is 1, data is
transferred from the slave device to the master device. When it is 0, data is transferred
from the master device to the slave device.
A
Indicates an acknowledge response. The receiving device drives SDA low level.
(In master transmit mode the slave device, and in master receive mode the master
device, returns the acknowledge response.)
DATA
Indicates transmit/receive data. The bit length of the transmit/receive data is set by bits
BC2 to BC0 in ICMR. The MLS bit in ICMR is used to select between MSB-first or LSBfirst format.
P
Indicates a stop condition. When SCL is high level, the master device changes SDA
from low to high level.
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Section 16 I C Bus Interface (IIC)
16.3.2
Master Transmit Operation
2
In I C bus format master transmit mode, the master device outputs the transmit clock and transmit
data, and the slave device returns an acknowledge signal.
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR write operations, are described below.
[1] Set the ICE bit in ICCR to 1. Set bits MLS, WAIT, and CKS2 to CKS0 in ICMR, and bit
IICX in STCR, according to the operation mode.
[2] Read the BBSY flag to confirm that the bus is free.
[3] Set the MST and TRS bits to 1 in ICCR to select master transmit mode.
[4] Write 1 to BBSY and 0 to SCP. This switches SDA from high to low when SCL is high, and
generates the start condition.
[5] When the start condition is generated, the IRIC and IRTR flags are set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU.
[6] Write data to ICDR (slave address + R/W)
With the I2C bus format (when the FS bit in SAR or the FSX bit in SARX is 0), the first
frame data following the start condition indicates the 7-bit slave address and transmit/receive
direction.
Then clear the IRIC flag to indicate the end of transfer.
Writing to ICDR and clearing of the IRIC flag must be executed continuously, so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
The master device sequentially sends the transmit clock and the data written to ICDR with
the timing shown in Figure 16.6. The selected slave device (i.e., the slave device with the
matching slave address) drives SDA low at the 9th transmit clock pulse and returns an
acknowledge signal.
[7] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[8] Read the ACKB bit to confirm that ACKB is 0.
When the slave device has not returned an acknowledge signal and ACKB remains 1, execute
the transmit end processing described in step [12] and perform transmit operation again.
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Section 16 I C Bus Interface (IIC)
[9] Write the next data to be transmitted in ICDR. To identify the end of data transfer, clear the
IRIC flag to 0.
As described in step [6] above, writing to ICDR and clearing of the IRIC flag must be
executed continuously so that no interrupt is inserted.
The next frame is transmitted in synchronization with the internal clock.
[10] When one frame of data has been transmitted, the IRIC flag is set to 1 at the rise of the 9th
transmit clock pulse. After one frame has been transmitted, SCL is automatically fixed low in
synchronization with the internal clock until the next transmit data is written.
[11] Read the ACKB bit of ICSR. Confirm that the slave device has returned an acknowledge
signal and ACKB is 0. When more data is to be transmitted, return to step [9] to execute next
transmit operation. If the slave device has not returned an acknowledge signal and ACKB is
1, execute the transmit end processing described in step [12].
[12] Clear the IRIC flag to 0. Write BBSY and CSP of ICCR to 0. By doing so, SDA is changed
from low to high while SCL is high and the transmit stop condition is generated.
Start condition generation
SCL
(Master output)
1
2
3
4
5
6
7
SDA
(Master output)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Slave address
SDA
(Slave output)
8
Bit 0
R/W
1
2
Bit 7
Bit 6
9
[7]
Data 1
A
[5]
IRIC
IRTR
ICDR
Data 1
Address + R/W
Precaution:
Data set timing to
ICDR
Incorrect operation
Normal
operation
User processing [4] Write 1 to BBSY [6] ICDR write
and 0 to SCP
(start condition
generation)
[6] IRIC clear
[9] ICDR write
[9] IRIC clear
Figure 16.6 Example of Master Transmit Mode Operating Timing (MLS = WAIT = 0)
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Section 16 I C Bus Interface (IIC)
16.3.3
Master Receive Operation
In master receive mode, the master device outputs the receive clock, receives data, and returns an
acknowledge signal. The slave device transmits data.
The transmission procedure and operations by which data is sequentially transmitted in
synchronization with ICDR write operations, are described below.
[1] Clear the TRS bit of ICCR to 0 and switch from transmit mode to receive mode. Set the
WAIT bit to 1 and clear the ACKB bit of ICSR to 0 (acknowledge data setting).
[2] When ICDR is read (dummy data read), reception is started and the receive clock is output,
and data is received, in synchronization with the internal clock. To indicate the wait, clear the
IRIC flag to 0.
Reading from ICDR and clearing of the IRIC flag must be executed continuously so that no
interrupt is inserted.
If a period of time that is equal to transfer one byte has elapsed by the time the IRIC flag is
cleared, the end of transfer cannot be identified.
[3] The IRIC flag is set to 1 at the fall of the 8th clock of a one-frame reception clock. At this
point, if the IEIC bit of ICCR is set to 1, an interrupt request is generated to the CPU.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag
is cleared. If the first frame is the final reception frame, execute the end processing as
described in [10].
[4] Clear the IRIC flag to 0 to negate the wait.
The master device outputs the 9th receive clock pulse, sets SDA to low, and returns an
acknowledge signal.
[5] When one frame of data has been transmitted, the IRIC and IRTR flags are set to 1 at the rise
of the 9th transmit clock pulse.
The master device continues to output the receive clock for the next receive data.
[6] Read the ICDR receive data.
[7] Clear the IRIC flag to indicate the next wait.
From clearing of the IRIC flag to negation of a wait as described in step [4] (and [9]) to
clearing of the IRIC flag as described in steps [5], [6], and [7], must be performed within the
time taken to transfer one byte.
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Section 16 I C Bus Interface (IIC)
[8] The IRIC flag is set to 1 at the fall of the 8th one-frame reception clock pulse.
SCL is automatically fixed low in synchronization with the internal clock until the IRIC flag
is cleared.
If this frame is the final reception frame, execute the end processing as described in [10].
[9] Clear the IRIC flag to 0 to negate the wait.
The master device outputs the 9th reception clock pulse, sets SDA to low, and returns an
acknowledge signal.
By repeating steps [5] to [9] above, more data can be received.
[10] Set the ACKB bit of ICSR to 1 and set the acknowledge data for the final reception.
Set the TRS bit of ICCR to 1 to change receive mode to transmit mode.
[11] Clear the IRIC flag to negate the wait.
[12] When one frame of data has been received, the IRIC flag is set to 1 at the rise of the 9th
reception clock pulse.
[13] Clear the WAIT bit of ICMR to 0 to cancel wait mode. Read the ICDR receive data and clear
the IRIC flag to 0.
Clear the IRIC flag only when WAIT = 0.
If the stop-condition generation command is executed after clearing the IRIC flag to 0 and
then clearing the WAIT bit to 0, the SDA line is fixed low and the stop condition cannot be
generated.
[14] Write 0 to BBSY and SCP. This changes SDA from low to high when SCL is high, and
generates the stop condition.
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Section 16 I C Bus Interface (IIC)
Master transmit mode
Master receive mode
SCL
(Master output)
9
1
2
3
4
5
6
7
8
SDA
(Slave output)
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
[3]
Data 1
SDA
(Master output)
[5]
1
2
3
4
5
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Data 2
A
IRIC
IRTR
Data 1
ICDR
User processing
[1] TRS = 0 clear [2] ICDR read
WAIT = 1 set
(dummy read)
ACKB = 0 clear
[6] ICDR read
(Data 1)
[4] IRIC clear
[7] IRIC clear
[2] IRIC clear
Figure 16.7 (1) Example of Master Receive Mode Operating Timing
(MLS = ACKB = 0 and WAIT = 1)
SCL
(Master output)
8
9
SDA
Bit 0
(Slave output)
Data 2
[8]
SDA
(Master output)
1
2
3
4
5
6
7
8
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Data 3
[5]
A
9
[8]
1
2
Bit 7
Bit 6
[5]
Data 4
A
IRIC
IRTR
ICDR
Data 1
User processing
Data 2
[6] ICDR read
(Data 2)
[9] IRIC clear
Data 3
[6] ICDR read
(Data 3)
[7] IRIC clear
[9] IRIC clear
[7] IRIC clear
Figure 16.7 (2) Example of Master Receive Mode Operating Timing
(MLS = ACKB = 0 and WAIT = 1)
16.3.4
Slave Receive Operation
In slave receive mode, the master device outputs the transmit clock and transmit data, and the
slave device returns an acknowledge signal. The reception procedure and operations in slave
receive mode are described below.
[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
[2] When the start condition output by the master device is detected, the BBSY flag in ICCR is set
to 1.
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Section 16 I C Bus Interface (IIC)
[3] When the slave address matches in the first frame following the start condition, the device
operates as the slave device specified by the master device. If the 8th data bit (R/W) is 0, the
TRS bit in ICCR remains cleared to 0, and slave receive operation is performed.
[4] At the 9th clock pulse of the receive frame, the slave device drives SDA low and returns an
acknowledge signal. At the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in
ICCR has been set to 1, an interrupt request is sent to the CPU. If the RDRF internal flag has
been cleared to 0, it is set to 1, and the receive operation continues. If the RDRF internal flag
has been set to 1, the slave device drives SCL low from the fall of the receive clock until data
is read into ICDR.
[5] Read ICDR and clear the IRIC flag in ICCR to 0. The RDRF flag is cleared to 0.
Receive operations can be performed continuously by repeating steps [4] and [5]. When SDA is
changed from low to high when SCL is high, and the stop condition is detected, the BBSY flag in
ICCR is cleared to 0.
Start condition
generation
SCL
(master output)
1
2
3
Bit 7
Bit 6
Bit 5
4
5
6
7
Bit 4
Bit 3
Bit 2
8
9
1
2
SCL
(slave output)
SDA
(master output)
Slave address
SDA
(slave output)
Bit 1
Bit 0
R/W
Bit 7
Bit 6
Data 1
[4]
A
RDRF
IRIC
Interrupt request
generation
ICDRS
Address + R/W
ICDRR
User processing
Address + R/W
[5] ICDR read
[5] IRIC clearance
Figure 16.8 Example of Slave Receive Mode Operation Timing (1) (MLS = ACKB = 0)
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Section 16 I C Bus Interface (IIC)
SCL
(master output)
7
8
Bit 1
Bit 0
9
1
2
3
4
5
6
7
8
9
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SCL
(slave output)
SDA
(master output)
Data 1
SDA
(slave output)
Bit 7
[4]
Bit 6
Data 2
A
[4]
A
RDRF
IRIC
ICDRS
Data 1
ICDRR
Data 1
User processing
Interrupt
request
generation
Interrupt
request
generation
[5] ICDR read
Data 2
Data 2
[5] IRIC clearance
Figure 16.9 Example of Slave Receive Mode Operation Timing (2) (MLS = ACKB = 0)
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Section 16 I C Bus Interface (IIC)
16.3.5
Slave Transmit Operation
In slave transmit mode, the slave device outputs the transmit data, while the master device outputs
the receive clock and returns an acknowledge signal. The transmission procedure and operations in
slave transmit mode are described below.
[1] Set the ICE bit in ICCR to 1. Set the MLS bit in ICMR and the MST and TRS bits in ICCR
according to the operating mode.
[2] When the slave address matches in the first frame following detection of the start condition,
the slave device drives SDA low at the 9th clock pulse and returns an acknowledge signal. At
the same time, the IRIC flag in ICCR is set to 1. If the IEIC bit in ICCR has been set to 1, an
interrupt request is sent to the CPU. If the 8th data bit (R/W) is 1, the TRS bit in ICCR is set to
1, and the mode changes to slave transmit mode automatically. The TDRF internal flag is set to
1. The slave device drives SCL low from the fall of the transmit clock until ICDR data is
written.
[3] After clearing the IRIC flag to 0, write data to ICDR. The TDRE internal flag is cleared to 0.
The written data is transferred to ICDRS, and the TDRE internal flag and the IRIC and IRTR
flags are set to 1 again. After clearing the IRIC flag to 0, write the next data to ICDR. The
slave device sequentially sends the data written into ICDR in accordance with the clock output
by the master device at the timing shown in figure 16.10.
[4] When one frame of data has been transmitted, the IRIC flag in ICCR is set to 1 at the rise of
the 9th transmit clock pulse. If the TDRE internal flag has been set to 1, this slave device
drives SCL low from the fall of the transmit clock until data is written to ICDR. The master
device drives SDA low at the 9th clock pulse, and returns an acknowledge signal. As this
acknowledge signal is stored in the ACKB bit in ICSR, this bit can be used to determine
whether the transfer operation was performed normally. When the TDRE internal flag is 0, the
data written into ICDR is transferred to ICDRS, transmission is started, and the TDRE internal
flag and the IRIC and IRTR flags are set to 1 again.
[5] To continue transmission, clear the IRIC flag to 0, then write the next data to be transmitted
into ICDR. The TDRE flag is cleared to 0.
Transmit operations can be performed continuously by repeating steps [4] and [5]. To end
transmission, write H'FF to ICDR to release SDA on the slave side. When SDA is changed from
low to high when SCL is high, and the stop condition is detected, the BBSY flag in ICCR is
cleared to 0.
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Section 16 I C Bus Interface (IIC)
Slave receive mode
SCL
(master output)
8
Slave transmit mode
9
1
2
3
4
5
6
7
8
A
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
9
1
2
SCL
(slave output)
SDA
(slave output)
SDA
(master output) R/W
Bit 7
Data 1
[2]
Bit 6
Data 2
A
TDRE
Interrupt
request
generation
IRIC
[3]
Interrupt
request
generation
Interrupt
request
generation
Data 1
ICDRT
ICDRS
Data 2
Data 1
User processing
[3] IRIC
[3] ICDR write
clearance
[3] ICDR write
Data 2
[5] IRIC
clearance
[5] ICDR write
Figure 16.10 Example of Slave Transmit Mode Operation Timing (MLS = 0)
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Section 16 I C Bus Interface (IIC)
16.3.6
IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the TDRE or RDRF internal flag is set to 1, SCL is
automatically held low after one frame has been transferred; this timing is synchronized with the
internal clock. Figure 16.11 shows the IRIC set timing and SCL control.
(a) When WAIT = 0, and FS = 0 or FSX = 0 (I2C bus format, no wait)
SCL
7
8
9
1
SDA
7
8
A
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
(b) When WAIT = 1, and FS = 0 or FSX = 0 (I2C bus format, wait inserted)
SCL
8
9
1
SDA
8
A
1
IRIC
Clear
IRIC
User processing
Clear Write to ICDR (transmit)
IRIC or read ICDR (receive)
(c) When FS = 1 and FSX = 1 (synchronous serial format)
SCL
7
8
1
SDA
7
8
1
IRIC
User processing
Clear IRIC
Write to ICDR (transmit)
or read ICDR (receive)
Figure 16.11 IRIC Setting Timing and SCL Control
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Section 16 I C Bus Interface (IIC)
16.3.7
2
Automatic Switching from Formatless Mode to I C Bus Format
Setting the SW bit to 1 in DDCSWR enables formatless mode to be selected as the IIC0 operating
2
mode. Switching from formatless mode to the I C bus format (slave mode) is performed
automatically when a falling edge is detected on the SCL pin.
The following four preconditions are necessary for this operation:
• A common data pin (SDA) for formatless and I C bus format operation
2
• Separate clock pins for formatless operation (VSYNCI) and I C bus format operation (SCL)
2
• A fixed 1 level for the SCL pin during formatless operation (is not driven to low)
• Settings of bits other than TRS in ICCR that allow I C bus format operation
2
2
Automatic switching is performed from formatless mode to the I C bus format when the SW bit in
DDCSWR is automatically cleared to 0 on detection of a falling edge on the SCL pin. Switching
2
from the I C bus format to formatless mode is achieved by having software set the SW bit in
DDCSWR to 1.
2
In formatless mode, bits (such as MSL and TRS) that control the I C bus interface operating mode
2
must not be modified. When switching from the I C bus format to formatless mode, set the TRS
bit to 1 or clear it to 0 according to the transmit data (transmission or reception) in formatless
2
mode, then set the SW bit to 1. After automatic switching from formatless mode to the I C bus
format (slave mode), in order to wait for slave address reception, the TRS bit is automatically
cleared to 0.
2
If a falling edge is detected on the SCL pin during formatless operation, I C bus interface
operation is deferred until a stop condition is detected.
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Section 16 I C Bus Interface (IIC)
16.3.8
Noise Canceler
The logic levels at the SCL and SDA pins are routed through noise cancelers before being latched
internally. Figure 16.12 shows a block diagram of the noise canceler circuit.
The noise canceler consists of two cascaded latches and a match detector. The SCL (or SDA)
input signal is sampled on the system clock, but is not passed forward to the next circuit unless the
outputs of both latches agree. If they do not agree, the previous value is held.
Sampling clock
C
SCL or
SDA input
signal
D
C
Q
Latch
D
Q
Match
detector
Latch
Internal
SCL or
SDA
signal
System clock
period
Sampling
clock
Figure 16.12 Block Diagram of Noise Canceler
16.3.9
Sample Flowcharts
2
Figures 16.13 to 16.16 show sample flowcharts for using the I C bus interface in each mode.
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Section 16 I C Bus Interface (IIC)
Start
Initialize
[1]
Initialize
[2]
Test the status of the SCL and SDA lines.
[3]
Select master transmit mode.
[4]
Start condition issuance
[5]
Wait for a start condition
[6]
Set transmit data for the first byte
(slave address + R/W).
(After writing ICDR, clear IRIC
immediately)
[7]
Wait for 1 byte to be transmitted.
[8]
Test the acknowledge bit,
transferred from slave device.
Read BBSY in ICCR
No
BBSY = 0 ?
Yes
Set MST = 1 and
TRS = 1 in ICCR
Write BBSY = 1 and
SCP = 0 in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRCI in ICCR
No
IRIC = 1 ?
Yes
Read ACKB in ICSR
ACKB = 0 ?
No
Yes
Transmit mode ?
No
Master receive mode
Yes
Write transmit data in ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
[9]
Set transmit data for the second and
subsequent bytes.
(After writing ICDR, clear IRIC immediately.)
[10] Wait for 1 byte to be transmitted.
IRIC = 1 ?
Yes
Read ACKB in ICSR
No
[11] Test for end of transfer
End of transmission ?
or ACKB = 1 ?
Yes
Clear IRIC in ICCR
[12] Stop condition issuance
Write BBSY = 0
and SCP = 0 in ICCR
End
Figure 16.13 Flowchart for Master Transmit Mode (Example)
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Section 16 I C Bus Interface (IIC)
Master receive operation
Set TRS = 0 in ICCR
[1]
Select receive mode.
[2]
Start receiving. The first read
is a dummy read. After reading
ICDR, please clear IRIC immediately.
[3]
Wait for 1 byte to be received
(8th clock falling edge)
[4]
Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
[5]
Wait for 1 byte to be received.
(9th clock rising edge)
Read ICDR
[6]
Read the receive data.
Clear IRIC in ICCR
[7]
Clear IRIC.
[8]
Wait for the next data to be
received.
(8th clock falling edge)
[9]
Clear IRIC to trigger the 9th clock.
(to end the wait insertion)
Set WAIT = 1 in ICMR
Set ACKB = 0 in ICSR
Read ICDR
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Last receive ?
Yes
No
Clear IRIC in ICCR
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Read IRIC in ICCR
No
IRIC = 1 ?
Yes
Last receive ?
Yes
No
Clear IRIC in ICCR
Set ACKB = 1 in ICSR
Set TRS = 1 in ICCR
Clear IRIC in ICCR
[10] Set ACKB = 1 so as to return No
acknowledge, or set TRS = 1 so as
not to issue Extra clock.
[11] Clear IRIC to trigger the 9th clock
(to end the wait insertion)
Read IRIC in ICCR
No
IRIC = 1 ?
[12] Wait for 1 byte to be received.
Yes
Set WAIT = 0 in ICMR
Read ICDR
Clear IRIC in ICCR
Write BBSY = 0
and SCP = 0 in ICCR
[13] Set WAIT = 0.
Read ICDR.
Clear IRIC.
(Note: After setting WAIT = 0, IRIC
should be cleared to 0.)
[14] Stop condition issuance.
End
Figure 16.14 Flowchart for Master Receive Mode (Example)
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Section 16 I C Bus Interface (IIC)
Start
Initialize
Set MST = 0
and TRS = 0 in ICCR
[1]
Set ACKB = 0 in ICSR
Read IRIC in ICCR
[2]
No
IRIC = 1?
Yes
Read AAS and ADZ in ICSR
AAS = 1
and ADZ = 0?
No
General call address processing
* Description omitted
Yes
Read TRS in ICCR
No
TRS = 0?
Slave transmit mode
Yes
Last receive?
Yes
No
Read ICDR
[3]
[1] Select slave receive mode.
[2] Wait for the first byte to be received (slave
address).
Clear IRIC in ICCR
[3] Start receiving. The first read is a dummy read.
Read IRIC in ICCR
No
[4] Wait for the transfer to end.
[4]
IRIC = 1?
[5] Set acknowledge data for the last receive.
[6] Start the last receive.
Yes
[7] Wait for the transfer to end.
Set ACKB = 1 in ICSR
[5]
Read ICDR
[6]
[8] Read the last receive data.
Clear IRIC in ICCR
Read IRIC in ICCR
No
[7]
IRIC = 1?
Yes
Read ICDR
[8]
Clear IRIC in ICCR
End
Figure 16.15 Flowchart for Slave Receive Mode (Example)
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Section 16 I C Bus Interface (IIC)
Slave transmit mode
Clear IRIC in ICCR
Write transmit data in ICDR
[1]
[1] Set transmit data for the second and
subsequent bytes.
[2] Wait for 1 byte to be transmitted.
Clear IRIC in ICCR
[3] Test for end of transfer.
[4] Select slave receive mode.
Read IRIC in ICCR
No
[2]
[5] Dummy read (to release the SCL line).
IRIC = 1?
Yes
Read ACKB in ICSR
No
[3]
End
of transmission
(ACKB = 1)?
Yes
Set TRS = 0 in ICCR
[4]
Read ICDR
[5]
Clear IRIC in ICCR
End
Figure 16.16 Flowchart for Slave Transmit Mode (Example)
16.3.10 Initialization of Internal State
The IIC has a function for forcible initialization of its internal state if a deadlock occurs during
communication.
Initialization is executed in accordance with the setting of bits CLR3 to CLR0 in the DDCSWR
register or clearing ICE bit. For details the setting of bits CLR3 to CLR0, see section 16.2.8, DDC
Switch Register (DDCSWR).
Scope of Initialization: The initialization executed by this function covers the following items:
• TDRE and RDRF internal flags
• Transmit/receive sequencer and internal operating clock counter
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Section 16 I C Bus Interface (IIC)
• Internal latches for retaining the output state of the SCL and SDA pins (wait, clock, data
output, etc.)
The following items are not initialized:
• Actual register values (ICDR, SAR, SARX, ICMR, ICCR, ICSR, DDCSWR, STCR)
• Internal latches used to retain register read information for setting/clearing flags in the ICMR,
ICCR, ICSR, and DDCSWR registers
• The value of the ICMR register bit counter (BC2 to BC0)
• Generated interrupt sources (interrupt sources transferred to the interrupt controller)
Notes on Initialization:
• Interrupt flags and interrupt sources are not cleared, and so flag clearing measures must be
taken as necessary.
• Basically, other register flags are not cleared either, and so flag clearing measures must be
taken as necessary.
• When initialization is executed by the DDCSWR register, the write data for bits CLR3 to
CLR0 is not retained. To perform IIC clearance, bits CLR3 to CLR0 must be written to
simultaneously using an MOV instruction. Do not use a bit manipulation instruction such as
BCLR. Similarly, when clearing is required again, all the bits must be written to
simultaneously in accordance with the setting.
• If a flag clearing setting is made during transmission/reception, the IIC module will stop
transmitting/receiving at that point and the SCL and SDA pins will be released. When
transmission/reception is started again, register initialization, etc., must be carried out as
necessary to enable correct communication as a system.
The value of the BBSY bit cannot be modified directly by this module clear function, but since the
stop condition pin waveform is generated according to the state and release timing of the SCL and
SDA pins, the BBSY bit may be cleared as a result. Similarly, state switching of other bits and
flags may also have an effect.
To prevent problems caused by these factors, the following procedure should be used when
initializing the IIC state.
1. Execute initialization of the internal state according to the setting of bits CLR3 to CLR0.
2. Execute a stop condition issuance instruction (write 0 to BBSY and SCP) to clear the BBSY
bit to 0, and wait for two transfer rate clock cycles.
3. Re-execute initialization of the internal state according to the setting of bits CLR3 to CLR0.
4. Initialize (re-set) the IIC registers.
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Section 16 I C Bus Interface (IIC)
16.4
Usage Notes
• In master mode, if an instruction to generate a start condition is immediately followed by an
instruction to generate a stop condition, neither condition will be output correctly. To output
consecutive start and stop conditions, after issuing the instruction that generates the start
condition, read the relevant ports, check that SCL and SDA are both low, then issue the
instruction that generates the stop condition. Note that SCL may not yet have gone low when
BBSY is cleared to 0.
• Either of the following two conditions will start the next transfer. Pay attention to these
conditions when reading or writing to ICDR.
 Write access to ICDR when ICE = 1 and TRS = 1 (including automatic transfer from
ICDRT to ICDRS)
 Read access to ICDR when ICE = 1 and TRS = 0 (including automatic transfer from
ICDRS to ICDRR)
• Table 16.5 shows the timing of SCL and SDA output in synchronization with the internal
clock. Timings on the bus are determined by the rise and fall times of signals affected by the
bus load capacitance, group resistance, and parallel resistance.
2
Table 16.5 I C Bus Timing (SCL and SDA Output)
Item
Symbol
Output Timing
Unit
Notes
SCL output cycle time
tSCLO
28tcyc to 256tcyc
ns
SCL output high pulse width
tSCLHO
0.5tSCLO
ns
Figure 22.18
(reference)
SCL output low pulse width
tSCLLO
0.5tSCLO
ns
SDA output bus free time
tBUFO
0.5tSCLO – 1tcyc
ns
Start condition output hold time
tSTAHO
0.5tSCLO – 1tcyc
ns
Retransmission start condition output
setup time
tSTASO
1tSCLO
ns
Stop condition output setup time
tSTOSO
0.5tSCLO + 2tcyc
ns
Data output setup time (master)
tSDASO
1tSCLLO – 3tcyc
ns
1tSCLL – (6tcyc or 12tcyc*)
Data output setup time (slave)
Data output hold time
Note:
*
tSDAHO
3tcyc
ns
6tcyc when IICX is 0, 12tcyc when 1.
Rev. 3.00 Mar 17, 2006 page 465 of 706
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2
Section 16 I C Bus Interface (IIC)
• SCL and SDA input is sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle tcyc, as shown in table 22.8 in section 22, Electrical
2
Characteristics. Note that the I C bus interface AC timing specifications will not be met with a
system clock frequency of less than 5 MHz.
• The I C bus interface specification for the SCL rise time tsr is under 1000 ns (300 ns for high2
speed mode). In master mode, the I C bus interface monitors the SCL line and synchronizes
one bit at a time during communication. If tsr (the time for SCL to go from low to VIH) exceeds
2
the time determined by the input clock of the I C bus interface, the high period of SCL is
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in the table
below.
2
Table 16.6 Permissible SCL Rise Time (tSR) Values
Time Indication
2
IICX
tcyc
Indication
0
7.5tcyc
1
17.5tcyc
I C Bus
Specification
(Max.)
φ=
5 MHz
Normal mode
1000 ns
High-speed mode
φ=
8 MHz
φ=
10 MHz
φ=
φ=
16 MHz 20 MHz
1000 ns 937 ns
750 ns
468 ns
375 ns
300 ns
300 ns
300 ns
300 ns
300 ns
Normal mode
1000 ns
1000 ns 1000 ns 1000 ns 1000 ns 875 ns
High-speed mode
300 ns
300 ns
300 ns
300 ns
300 ns
300 ns
300 ns
• The I C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
2
and 300 ns. The I C bus interface SCL and SDA output timing is prescribed by tcyc, as shown in
2
table 16.6. However, because of the rise and fall times, the I C bus interface specifications may
not be satisfied at the maximum transfer rate. Table 16.7 shows output timing calculations for
different operating frequencies, including the worst-case influence of rise and fall times.
2
2
tBUFO fails to meet the I C bus interface specifications at any frequency. The solution is either (a)
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
2
permits this output timing for use as slave devices connected to the I C bus.
2
tSCLLO in high-speed mode and tSTASO in standard mode fail to satisfy the I C bus interface
specifications for worst-case calculations of tSr/tSf. Possible solutions that should be investigated
include (a) adjusting the rise and fall times by means of a pull-up resistor and capacitive load,
(b) reducing the transfer rate to meet the specifications, or (c) selecting devices whose input
2
timing permits this output timing for use as slave devices connected to the I C bus.
Rev. 3.00 Mar 17, 2006 page 466 of 706
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2
Section 16 I C Bus Interface (IIC)
2
Table 16.7 I C Bus Timing (with Maximum Influence of tSr/tSf)
Time Indication (at Maximum Transfer Rate) [ns]
Item
tSCLHO
tSCLLO
tBUFO
tSTAHO
tSTASO
tSTOSO
tcyc
Indication
I2C Bus
tSr/tSf
SpecifiInfluence cation
(Min.)
(Max.)
φ=
5 MHz
φ=
8 MHz
φ=
φ=
φ=
10 MHz 16 MHz 20 MHz
0.5tSCLO
(–tSr)
Standard mode
–1000
4000
4000
4000
4000
4000
4000
High-speed mode
–300
600
950
950
950
950
950
0.5tSCLO
(–tSf )
Standard mode
–250
4700
4750
4750
4750
4750
4750
–250
1300
1000*1 1000*1 1000*1 1000*1 1000*1
–1000
4700
3800*1 3875*1 3900*1 3938*1 3950*1
–300
1300
750*1
825*1
850*1
888*1
900*1
–250
4000
4550
4625
4650
4688
4700
–250
600
800
875
900
938
950
Standard mode
–1000
4700
9000
9000
9000
9000
9000
High-speed mode
–300
600
2200
2200
2200
2200
2200
High-speed mode
0.5tSCLO
Standard mode
–1tcyc ( –tSr )
High-speed mode
0.5tSCLO
Standard mode
–1tcyc (–tSf )
High-speed mode
1tSCLO
(–tSr )
Standard mode
–1000
4000
4400
4250
4200
4125
4100
High-speed mode
–300
600
1350
1200
1150
1075
1050
–1000
250
3100
3325
3400
3513
3550
(master)
1tSCLLO*3
Standard mode
–3tcyc (–tSr )
High-speed mode
–300
100
400
625
700
813
850
tSDASO
(slave)
1tSCLL*3
–12t *2
–1000
250
1300
2200
2500
2950
3100
400
tSDASO
0.5tSCLO +
2tcyc (–tSr )
cyc
(–tSr )
tSDAHO
3tcyc
Standard mode
High-speed mode
–300
100
–1400*1 –500*1 –200*1 250
Standard mode
0
0
600
375
300
188
150
High-speed mode
0
0
600
375
300
188
150
2
Notes: 1. Does not meet the I C bus interface specification. Remedial action such as the following
is necessary: (a) secure a start/stop condition issuance interval; (b) adjust the rise and
fall times by means of a pull-up resistor and capacitive load; (c) reduce the transfer rate;
(d) select slave devices whose input timing permits this output timing.
The values in the above table will vary depending on the settings of the IICX bit and bits
CKS0 to CKS2. Depending on the frequency it may not be possible to achieve the
2
maximum transfer rate; therefore, whether or not the I C bus interface specifications are
met must be determined in accordance with the actual setting conditions.
2. Value when the IICX bit is set to 1. When the IICX bit is cleared to 0, the value is (tSCLL –
6tcyc).
2
3. Calculated using the I C bus specification values (standard mode: 4700 ns min.; highspeed mode: 1300 ns min.).
Rev. 3.00 Mar 17, 2006 page 467 of 706
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2
Section 16 I C Bus Interface (IIC)
• Note on ICDR Read at End of Master Reception
To halt reception at the end of a receive operation in master receive mode, set the TRS bit to 1
and write 0 to BBSY and SCP in ICCR. This changes SDA from low to high when SCL is
high, and generates the stop condition. After this, receive data can be read by means of an
ICDR read, but if data remains in the buffer the ICDRS receive data will not be transferred to
ICDR, and so it will not be possible to read the second byte of data.
If it is necessary to read the second byte of data, issue the stop condition in master receive
mode (i.e. with the TRS bit cleared to 0). When reading the receive data, first confirm that the
BBSY bit in the ICCR register is cleared to 0, the stop condition has been generated, and the
bus has been released, then read the ICDR register with TRS cleared to 0.
Note that if the receive data (ICDR data) is read in the interval between execution of the
instruction for issuance of the stop condition (writing of 0 to BBSY and SCP in ICCR) and the
actual generation of the stop condition, the clock may not be output correctly in subsequent
master transmission.
Clearing of the MST bit after completion of master transmission/reception, or other
modifications of IIC control bits to change the transmit/receive operating mode or settings,
must be carried out during interval (a) in figure 16.17 (after confirming that the BBSY bit has
been cleared to 0 in the ICCR register).
Stop condition
Start condition
(a)
SDA
Bit 0
A
SCL
8
9
Internal clock
BBSY bit
Master receive mode
ICDR reading
prohibited
Execution of stop
condition issuance
instruction
(0 written to BBSY
and SCP)
Confirmation of stop
condition generation
(0 read from BBSY)
Start condition
issuance
Figure 16.17 Points for Attention Concerning Reading of Master Receive Data
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2
Section 16 I C Bus Interface (IIC)
• Notes on Start Condition Issuance for Retransmission
Figure 16.18 shows the timing of start condition issuance for retransmission, and the timing for
subsequently writing data to ICDR, together with the corresponding flowchart. After start
condition issuance is done and determined the start condition, write the transmit data to ICDR,
as shown below.
IRIC = 1 ?
No
[1]
Yes
Clear IRIC in ICSR
Start condition
issuance ?
No
Wait for end of 1-byte transfer
[2]
Determine whether SCL is low
[3]
Issue restart condition instruction for transmission
[4]
Detremine whether start condition is generated or not
[5]
Set transmit data (slave address + R/W)
Other processing
Yes
[2]
Read SCL pin
SCL = Low ?
[1]
Note: Program so that processing from [3] to [5] is
executed continuously.
No
Yes
Write BBSY = 1,
SCP = 0 (ICSR)
IRIC = 1 ?
[3]
No
[4]
Yes
[5]
Write transmit data to ICDR
start condition
(retransmission)
9
SCL
SDA
ACK
bit7
Data output
IRIC
[3] Start condition instruction
issuance
[1] IRIC determination [2] Determination
of SCL = Low
[4] IRIC determination
[5] ICDR write (next transmit data)
Figure 16.18 Flowchart and Timing of Start Condition Instruction Issuance for
Retransmission
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2
Section 16 I C Bus Interface (IIC)
• Notes on I C Bus Interface Stop Condition Instruction Issuance
2
If the rise time of the 9th SCL clock exceeds the specification because the bus load capacitance
is large, or if there is a slave device of the type that drives SCL low to effect a wait, after rising
of the 9th SCL clock, issue the stop condition after reading SCL and determining it to below,
as shown below.
SCL
9th clock
VIH
High period secured
As waveform rise is late,
SCL is detected as low
SDA
Stop condition
IRIC
[1] Determination of SCL = Low
[2] Stop condition instruction isuuance
Figure 16.19 Timing of Stop Condition Issuance
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Section 17 A/D Converter
Section 17 A/D Converter
17.1
Overview
The H8/3577 Group and H8/3567 Group have an on-chip 10-bit successive-approximations A/D
converter that allows up to eight analog input channels to be selected.
The H8/3577 Group has eight analog input channels, and the H8/3567 Group has four.
17.1.1
Features
A/D converter features are listed below.
• 10-bit resolution (analog input)
• Input channels
 8 channels (H8/3577 Group)
 4 channels (H8/3567 Group)
• Settable analog conversion voltage range
 The analog conversion voltage range is set using the analog power supply voltage pin
(AVcc) as the analog reference voltage
• High-speed conversion
 Minimum conversion time: 6.7 µs per channel (at 20 MHz operation)
• Choice of single mode or scan mode
 Single mode: Single-channel A/D conversion
 Scan mode:
Continuous A/D conversion on 1 to 4 channels
• Four data registers
 Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three kinds of conversion start
 Choice of software or timer conversion start trigger (8-bit timer), or ADTRG pin
• A/D conversion end interrupt generation
 An A/D conversion end interrupt (ADI) request can be generated at the end of A/D
conversion
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Section 17 A/D Converter
17.1.2
Block Diagram
Figure 17.1 shows a block diagram of the A/D converter.
Internal
data bus
AVSS
ADCR
ADCSR
ADDRD
ADDRC
ADDRB
+
–
Multiplexer
H8/3577
Group
only
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
ADDRA
10-bit D/A
Successive approximations
register
AVCC
Bus interface
Module data bus
Comparator
φ/8
Control circuit
Sample-andhold circuit
φ/16
ADI interrupt
signal
ADTRG
Legend:
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
Conversion start
trigger from 8-bit
timer
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
Figure 17.1 Block Diagram of A/D Converter
Rev. 3.00 Mar 17, 2006 page 472 of 706
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Section 17 A/D Converter
17.1.3
Pin Configuration
Table 17.1 summarizes the input pins used by the A/D converter.
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter.
Table 17.1 A/D Converter Pins
Pin Name
Symbol
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground and A/D conversion
reference voltage
Analog input pin 0
AN0
Input
Analog input channel 0
Analog input pin 1
AN1
Input
Analog input channel 1
Analog input pin 2
AN2
Input
Analog input channel 2
Analog input pin 3
AN3
Input
Analog input channel 3
Analog input pin 4
AN4
Input
Analog input channel 4 (H8/3577 Group only)
Analog input pin 5
AN5
Input
Analog input channel 5 (H8/3577 Group only)
Analog input pin 6
AN6
Input
Analog input channel 6 (H8/3577 Group only)
Analog input pin 7
AN7
Input
Analog input channel 7 (H8/3577 Group only)
A/D external trigger input pin
ADTRG
Input
External trigger input for starting A/D
conversion
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Section 17 A/D Converter
17.1.4
Register Configuration
Table 17.2 summarizes the registers of the A/D converter.
Table 17.2 A/D Converter Registers
Name
Abbreviation
R/W
Initial Value
Address
A/D data register AH
ADDRAH
R
H'00
H'FFE0
A/D data register AL
ADDRAL
R
H'00
H'FFE1
A/D data register BH
ADDRBH
R
H'00
H'FFE2
A/D data register BL
ADDRBL
R
H'00
H'FFE3
A/D data register CH
ADDRCH
R
H'00
H'FFE4
A/D data register CL
ADDRCL
R
H'00
H'FFE5
A/D data register DH
ADDRDH
R
H'00
H'FFE6
A/D data register DL
ADDRDL
R
H'00
H'FFE7
A/D control/status register
ADCSR
R/(W)*
H'00
H'FFE8
A/D control register
ADCR
R/W
H'3F
H'FFE9
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
Note:
Only 0 can be written in bit 7, to clear the flag.
*
17.2
Register Descriptions
17.2.1
A/D Data Registers A to D (ADDRA to ADDRD)
Bit
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
14
13
12
11
10
9
8
7
6
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of
A/D conversion.
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Section 17 A/D Converter
The 10-bit data resulting from A/D conversion is transferred to the ADDR register for the selected
channel and stored there. The upper 8 bits of the converted data are transferred to the upper byte
(bits 15 to 8) of ADDR, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and
stored. Bits 5 to 0 are always read as 0.
The correspondence between the analog input channels and ADDR registers is shown in table
17.3.
The ADDR registers can always be read by the CPU. The upper byte can be read directly, but for
the lower byte, data transfer is performed via a temporary register (TEMP). For details, see section
17.3, Interface to Bus Master.
The ADDR registers are initialized to H'0000 by a reset, and in standby mode, and module stop
mode.
Table 17.3 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Group 0
Group 1
A/D Data Register
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
17.2.2
A/D Control/Status Register (ADCSR)
Bit
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Note:
*
Only 0 can be written in bit 7, to clear the flag.
ADCSR is an 8-bit readable/writable register that controls A/D conversion operations.
ADCSR is initialized to H'00 by a reset, and in standby mode, and module stop mode.
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Section 17 A/D Converter
Bit 7—A/D End Flag (ADF): Status flag that indicates the end of A/D conversion.
Bit 7
ADF
Description
0
[Clearing condition]
(Initial value)
When 0 is written in the ADF flag after reading ADF = 1
1
[Setting conditions]
•
Single mode: When A/D conversion ends
•
Scan mode:
When A/D conversion ends on all specified channels
Bit 6—A/D Interrupt Enable (ADIE): Selects enabling or disabling of interrupt (ADI) requests
at the end of A/D conversion.
Bit 6
ADIE
Description
0
A/D conversion end interrupt (ADI) request is disabled
1
A/D conversion end interrupt (ADI) request is enabled
(Initial value)
Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1
during A/D conversion.
The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external
trigger input pin (ADTRG).
Bit 5
ADST
Description
0
A/D conversion stopped
1
Single mode: A/D conversion is started. Cleared to 0 automatically when conversion
on the specified channel ends
(Initial value)
Scan mode: A/D conversion is started. Conversion continues sequentially on the
selected channels until ADST is cleared to 0 by software, a reset, or a
transition to standby mode or module stop mode
Rev. 3.00 Mar 17, 2006 page 476 of 706
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Section 17 A/D Converter
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode as the A/D conversion operating
mode. See section 17.4, Operation, for single mode and scan mode operation. Only set the SCAN
bit while conversion is stopped.
Bit 4
SCAN
Description
0
Single mode
1
Scan mode
(Initial value)
Bit 3—Clock Select (CKS): Sets the A/D conversion time. Only change the conversion time
while ADST = 0.
Bit 3
CKS
Description
0
Conversion time = 266 states (max.)
1
Conversion time = 134 states (max.)
(Initial value)
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): Together with the SCAN bit, these bits select
the analog input channel(s).
Only set the input channel while conversion is stopped.
Group
Selection
H8/3577 Group
and
H8/3567 Group
H8/3577 Group
only
Channel Selection
Description
CH2
CH1
CH0
Single Mode
Scan Mode
0
0
0
AN0
(Initial value)
AN0
1
AN1
AN0, AN1
1
0
AN2
AN0 to AN2
1
AN3
AN0 to AN3
0
0
AN4
AN4
1
AN5
AN4, AN5
0
AN6
AN4, AN5, AN6
1
AN7
AN4 to AN7
1
1
Rev. 3.00 Mar 17, 2006 page 477 of 706
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Section 17 A/D Converter
17.2.3
A/D Control Register (ADCR)
Bit
7
6
5
4
3
2
1
0
TRGS1
TRGS0
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/W
R/W
—
—
—
—
—
—
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion operations.
ADCR is initialized to H'3F by a reset, and in standby mode, and module stop mode.
Bits 7 and 6—Timer Trigger Select 1 and 0 (TRGS1, TRGS0): These bits select enabling or
disabling of the start of A/D conversion by a trigger signal. Only set bits TRGS1 and TRGS0
while conversion is stopped.
Bit 7
Bit 6
TRGS1
TRGS0
Description
0
0
Start of A/D conversion by external trigger is disabled
1
Start of A/D conversion by external trigger is disabled
0
Start of A/D conversion by external trigger (8-bit timer) is enabled
1
Start of A/D conversion by external trigger pin is enabled
1
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
Rev. 3.00 Mar 17, 2006 page 478 of 706
REJ09B0303-0300
(Initial value)
Section 17 A/D Converter
17.2.4
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR, comprising two 8-bit readable/writable registers, performs module stop mode control.
When the MSTP9 bit in MSTPCR is set to 1, A/D converter operation stops at the end of the bus
cycle and a transition is made to module stop mode. Registers cannot be read or written to in
module stop mode. For details, see section 21.5, Module Stop Mode.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTPCRH Bit 1—Module Stop (MSTP9): Specifies the A/D converter module stop mode.
MSTPCRH
Bit 1
MSTP9
Description
0
A/D converter module stop mode is cleared
1
A/D converter module stop mode is set
(Initial value)
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Section 17 A/D Converter
17.3
Interface to Bus Master
ADDRA to ADDRD are 16-bit registers, but the data bus to the bus master is only 8 bits wide.
Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is
accessed via a temporary register (TEMP).
A data read from ADDR is performed as follows. When the upper byte is read, the upper byte
value is transferred to the CPU and the lower byte value is transferred to TEMP. Next, when the
lower byte is read, the TEMP contents are transferred to the CPU.
When reading ADDR, always read the upper byte before the lower byte. It is possible to read only
the upper byte, but if only the lower byte is read, incorrect data may be obtained.
Figure 17.2 shows the data flow for ADDR access.
Upper byte read
Bus master
(H'AA)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Lower byte read
Bus master
(H'40)
Module data bus
Bus interface
TEMP
(H'40)
ADDRnH
(H'AA)
ADDRnL
(H'40)
(n = A to D)
Figure 17.2 ADDR Access Operation (Reading H'AA40)
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Section 17 A/D Converter
17.4
Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
17.4.1
Single Mode (SCAN = 0)
Single mode is selected when A/D conversion is to be performed on a single channel only. A/D
conversion is started when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends.
On completion of conversion, the ADF flag is set to 1. If the ADIE bit is set to 1 at this time, an
ADI interrupt request is generated. The ADF flag is cleared by writing 0 after reading ADCSR.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit
can be set at the same time as the operating mode or input channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure
17.3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH1 = 0, CH0 = 1), the
A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred to ADDRB. At the same time the
ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 to the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
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Idle
Idle
Idle
State of channel 1
(AN1)
State of channel 2
(AN2)
State of channel 3
(AN3)
A/D conversion 1
Set*
A/D conversion 2
Set*
A/D conversion result 1
Read conversion result
Idle
Clear*
Note: * Vertical arrows ( ) indicate instructions executed by software.
ADDRD
ADDRC
ADDRB
ADDRA
Idle
A/D
conversion
starts
State of channel 0
(AN0)
ADF
ADST
ADIE
Set*
A/D conversion result 2
Read conversion result
Idle
Clear*
Section 17 A/D Converter
Figure 17.3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
Section 17 A/D Converter
17.4.2
Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the
first channel in the group (AN0 when CH2 = 0; AN4 when CH2 = 1). When two or more channels
are selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDR
registers corresponding to the channels.
When the operating mode or analog input channel must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit
can be set at the same time as the operating mode or input channel is changed.
Typical operations when three channels (AN0 to AN2) are selected in scan mode are described
next. Figure 17.4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input channels
AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1)
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred to
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to
1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1 at this time,
an ADI interrupt is requested after A/D conversion ends.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
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Figure 17.4 Example of A/D Converter Operation
(Scan Mode, Channels AN0 to AN2 Selected)
Idle
Idle
Idle
A/D conversion 1
Transfer
2. Data currently being converted is ignored.
Idle
A/D conversion 3
Idle
A/D conversion result 3
A/D conversion result 2
A/D conversion result 4
Idle
Idle
Idle
Clear*1
A/D conversion 5 *2
A/D conversion time
A/D conversion 4
A/D conversion result 1
A/D conversion 2
Idle
Notes: 1. Vertical arrows ( ) indicate instructions executed by software.
ADDRD
ADDRC
ADDRB
ADDRA
State of channel 3
(AN3)
State of channel 2
(AN2)
State of channel 1
(AN1)
State of channel 0
(AN0)
ADF
ADST
Set*1
Continuous A/D conversion execution
Clear*1
Section 17 A/D Converter
Section 17 A/D Converter
17.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 17.5 shows the A/D
conversion timing. Table 17.4 indicates the A/D conversion time.
As indicated in figure 17.5, the A/D conversion time includes tD and the input sampling time. The
length of tD varies depending on the timing of the write access to ADCSR. The total conversion
time therefore varies within the ranges indicated in table 17.4.
In scan mode, the values given in table 17.4 apply to the first conversion time. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1.
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tD
t SPL
t CONV
Legend:
(1):
ADCSR write cycle
(2):
ADCSR address
tD:
A/D conversion start delay
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 17.5 A/D Conversion Timing
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Section 17 A/D Converter
Table 17.4 A/D Conversion Time (Single Mode)
CKS = 0
CKS = 1
Item
Symbol
Min
Typ
Max
Min
Typ
Max
A/D conversion start delay
tD
10
—
17
6
—
9
Input sampling time
tSPL
—
63
—
—
31
—
A/D conversion time
tCONV
259
—
266
131
—
134
Note: Values in the table are the number of states.
17.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the ADST bit is set to 1 by software. Figure 17.6 shows the timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 17.6 External Trigger Input Timing
17.5
Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
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Section 17 A/D Converter
17.6
Usage Notes
The following points should be noted when using the A/D converter.
Setting Range of Analog Power Supply and Other Pins
1. Analog input voltage range
The voltage applied to the ANn analog input pins during A/D conversion should be in the
range AVSS ≤ ANn ≤ AVCC (n = 0 to 7).
2. Relation between AVCC, AVSS and VCC, VSS
As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS. If the A/D converter is
not used, the AVCC and AVSS pins must on no account be left open.
If conditions 1 and 2 above are not met, the reliability of the device may be adversely affected.
Notes on Board Design: In board design, digital circuitry and analog circuitry should be as
mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit
signal lines cross or are in close proximity should be avoided as far as possible. Failure to do so
may result in incorrect operation of the analog circuitry due to inductance, adversely affecting A/D
conversion values.
Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7), and analog
power supply (AVCC) by the analog ground (AVSS). Also, the analog ground (AVSS) should be
connected at one point to a stable digital ground (VSS) on the board.
Notes on Noise Countermeasures: A protection circuit connected to prevent damage due to an
abnormal voltage such as an excessive surge at the analog input pins (AN0 to AN7) should be
connected between AVCC and AVSS as shown in figure 17.7.
Also, the bypass capacitors connected to AVCC and the filter capacitor connected to AN0 to AN7
must be connected to AVSS.
If a filter capacitor is connected as shown in figure 17.7, the input currents at the analog input pins
(AN0 to AN7) are averaged, and so an error may arise. Also, when A/D conversion is performed
frequently, as in scan mode, if the current charged and discharged by the capacitance of the
sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance
(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required
when deciding the circuit constants.
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Section 17 A/D Converter
AVCC
100 Ω
Rin* 2
AN0 to AN7
*1
0.1 µF
AVSS
Notes:
Figures are reference values.
1.
10 µF
0.01 µF
2. Rin: Input impedance
Figure 17.7 Example of Analog Input Protection Circuit
Table 17.5 Analog Pin Specifications
Item
Min
Max
Unit
Analog input capacitance
—
20
pF
—
10*
kΩ
Permissible signal source impedance
Note:
*
When VCC = 4.5 V to 5.5 V and φ ≤ 12 MHz
10 kΩ
AN0 to
AN7
To A/D
converter
20 pF
Note: Figures are reference values.
Figure 17.8 Analog Input Pin Equivalent Circuit
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Section 17 A/D Converter
A/D Conversion Precision Definitions: A/D conversion precision definitions for the H8/3577
Group and H8/3567 Group are given below.
• Resolution
The number of A/D converter digital output codes
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 17.10).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'111111111 (H'3FF) (see
figure 17.10).
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 17.9).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error.
• Absolute precision
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
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Section 17 A/D Converter
Digital output
Ideal A/D conversion
characteristic
H'3FF
H'3FE
H'3FD
H'004
H'003
H'002
Quantization error
H'001
H'000
2
1
1024 1024
1022 1023 FS
1024 1024
Analog
input voltage
Figure 17.9 A/D Conversion Precision Definitions (1)
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
FS
Offset error
Analog
input voltage
Figure 17.10 A/D Conversion Precision Definitions (2)
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Section 17 A/D Converter
Permissible Signal Source Impedance: Analog input is designed so that conversion precision is
guaranteed for an input signal for which the signal source impedance is 10 kΩ (when AVCC = 4.5
to 5.5 V and φ ≤ 12 MHz, or when CSK = 0) or less. This specification is provided to enable the
A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling time;
if the sensor output impedance exceeds 10 kΩ (when AVCC = 4.5 to 5.5 V and φ ≤ 12 MHz, or
when CSK = 0), charging may be insufficient and it may not be possible to guarantee the A/D
conversion precision.
However, if a large capacitance is provided externally, the input load will essentially comprise
only the internal input resistance of 10 kΩ, and the signal source impedance is ignored.
But since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog
signal with a large differential coefficient (e.g., 5 mV/µsec or greater).
When converting a high-speed analog signal, a low-impedance buffer should be inserted.
Influences on Absolute Precision: Adding capacitance results in coupling with GND, and
therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to
an electrically stable GND such as AVSS.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, so acting as antennas.
Sensor output
impedance,
up to 10 kΩ
H8/3577 Group or
H8S/3567 Group
chip
A/D converter
equivalent circuit
10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
20 pF
Note: Figures are reference values.
Figure 17.11 Example of Analog Input Circuit
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Section 17 A/D Converter
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Section 18 RAM
Section 18 RAM
18.1
Overview
The H8/3577 Group and H8/3567 Group have 2 kbytes of on-chip high-speed static RAM. The
on-chip RAM is connected to the bus master by a 16-bit data bus, enabling both byte data and
word data to be accessed in two states. This makes it possible to perform fast word data transfer.
The on-chip RAM can be enabled or disabled by means of the RAM enable bit (RAME) in the
system control register (SYSCR).
18.1.1
Block Diagram
Figure 18.1 shows a block diagram of the on-chip RAM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'E080
H'E081
H'E082
H'E083
H'E084
H'E085
H'EFFE
H'EFFF
H'FF00
H'FF01
H'FF7E
H'FF7F
Figure 18.1 Block Diagram of RAM
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Section 18 RAM
18.1.2
Register Configuration
The on-chip RAM is controlled by SYSCR. Table 18.1 shows the register configuration.
Table 18.1 Register Configuration
Name
Abbreviation
R/W
Initial Value
Address
System control register
SYSCR
R/W
H'09
H'FFC4
18.2
System Control Register (SYSCR)
Bit
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. For details of other bits in
SYSCR, see section 3.2.2, System Control Register.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized when the reset state is released. It is not initialized in software standby mode.
Bit 0
RAME
Description
0
On-chip RAM is disabled
1
On-chip RAM is enabled
18.3
(Initial value)
Operation
When the RAME bit is set to 1, accesses to addresses H'E880 to H'EFFF and H'FF00 to H'FF7F
are directed to the on-chip RAM. When the RAME bit is cleared to 0, the on-chip RAM is not
accessed; a read will return an undefined value, and writes are invalid.
Since the on-chip RAM is connected to the bus master by a 16-bit data bus, it can be written to
and read in byte or word units. Each type of access is performed in two states.
Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. Word data must start
at an even address.
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Section 19 ROM
Section 19 ROM
19.1
Overview
The H8/3577, H8/3567, and H8/3567U have 56 kbytes of on-chip ROM (PROM or mask ROM),
and the H8/3574, H8/3564, and H8/3564U have 32 kbytes. The ROM is connected to the bus
master by a 16-bit data bus. The CPU accesses both byte and word data in two states, enabling
faster instruction fetches and higher processing speed.
Figure 19.1 shows a block diagram of the ROM.
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
H'0000
H'0001
H'0002
H'0003
H'DFFE
H'DFFF
Figure 19.1 ROM Block Diagram (H8/3577, H8/3567, H8/3567U)
19.2
Operation
The on-chip ROM is connected to the CPU by a 16-bit data bus, and both byte and word data is
accessed in two states. Even addresses are connected to the upper 8 bits, and odd addresses to the
lower 8 bits. Word data must start at an even address.
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Section 19 ROM
19.3
Writer Mode (H8/3577, H8/3567, H8/3567U)
19.3.1
Writer Mode Setup
In writer mode the PROM versions of the H8/3577, H8/3567, and H8/3567U suspend the usual
microcomputer functions to allow the on-chip PROM to be programmed. The programming
method is the same as for the HN27C101.
To select writer mode, apply the signal inputs listed in table 19.1.
Table 19.1 Selection of Writer Mode
Pin
H8/3577
H8/3567, H8/3567U
Input
Mode pin MD1
Low
Mode pin MD0
Low
STBY pin
Low
Pins P63 and P64
High
Mode pin TEST
Low
STBY pin
Low
Pins P47 and P52
High
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Section 19 ROM
19.3.2
Socket Adapter Pin Assignments and Memory Map
The H8/3577, H8/3567, and H8/3567U can be programmed with a general-purpose PROM
programmer by using a socket adapter to change the pin-out to 32 pins. See table 19.2. The same
socket adapter can be used for H8/3577, H8/3567, and H8/3567U. Figures 19.2 to 19.4 show the
socket adapter pin assignments.
Table 19.2 Socket Adapter
Package
Socket Adapter
64-pin QFP (H8/3577)
HS3297ESHS1H
64-pin shrink DIP (H8/3577)
HS3297ESSS1H
44-pin QFP (H8/3567)
TBD
42-pin shrink DIP (H8/3567)
TBD
64-pin QFP (H8/3567U)
TBD
64-pin shrink DIP (H8/3567U)
TBD
The PROM size is 56 kbytes for the H8/3577, H8/3567, and H8/3567U. Figure 19.5 shows
memory maps of the H8/3577, H8/3567, and H8/3567U in writer mode. H'FF data should be
specified for unused address areas in the on-chip PROM.
When programming with a PROM programmer, limit the program address range to H'0000 to
H'DFFF for the H8/3577, H8/3567, and H8/3567U. Specify H'FF data for addresses H'E000 and
above. If these addresses are programmed by mistake, it may become impossible to program or
verify the PROM data. The same problem may occur if an attempt is made to program the chip in
page programming mode. Note that the PROM versions are one-time programmable (OTP)
microcomputers, packaged in plastic packages, and cannot be reprogrammed.
Rev. 3.00 Mar 17, 2006 page 497 of 706
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Section 19 ROM
EPROM Socket
H8/3577
DP-64S FP-64A
Pin
Pin
HN27C101
(32 pins)
12
4
RES
VPP
1
13
5
NMI
EA 9
26
57
49
P3 0
EO0
13
58
50
P3 1
EO1
14
59
51
P3 2
EO2
15
60
52
P3 3
EO3
17
61
53
P3 4
EO4
18
62
54
P3 5
EO5
19
63
55
P3 6
EO6
20
64
56
P3 7
EO7
21
56
48
P1 0
EA 0
12
55
47
P1 1
EA 1
11
54
46
P1 2
EA 2
10
53
45
P1 3
EA 3
9
52
44
P1 4
EA 4
8
51
43
P1 5
EA 5
7
50
42
P1 6
EA 6
6
49
41
P1 7
EA 7
5
47
39
P2 0
EA 8
27
46
38
P2 1
OE
24
45
37
P2 2
EA10
23
44
36
P2 3
EA11
25
43
35
P2 4
EA12
4
42
34
P2 5
EA13
28
41
33
P2 6
EA14
29
40
32
P2 7
CE
22
1
57
P40
EA16
2
2
58
P41
EA15
3
3
59
P42
PGM
31
34
26
P6 3
VCC
32
35
27
P6 4
30
22
AVCC
14, 39
6, 31
VCC
VSS
16
20
12
MD0
19
11
MD1
15
7
STBY
21
13
AVSS
16, 48
8, 40
VSS
Note: All pins not listed in this figure should be left open.
Legend:
VPP:
EO7 to EO0:
EA16 to EA0:
OE:
CE:
PGM:
Programming power supply (12.5 V)
Data input/output
Address input
Output enable
Chip enable
Program enable
Figure 19.2 Socket Adapter Pin Assignments (H8/3577)
Rev. 3.00 Mar 17, 2006 page 498 of 706
REJ09B0303-0300
Section 19 ROM
EPROM Socket
H8/3567
DP-42S FP-44A
Pin
Pin
HN27C101
(32 pins)
7
2
RES
VPP
1
8
3
NMI
EA 9
26
21
16
P60
EO0
13
28
24
P61
EO1
14
27
23
P62
EO2
15
26
22
P63
EO3
17
22
18
P64
EO4
18
23
19
P65
EO5
19
24
20
P66
EO6
20
25
21
P67
EO7
21
37
33
P1 0
EA 0
12
36
32
P1 1
EA 1
11
35
31
P1 2
EA 2
10
34
30
P1 3
EA 3
9
33
29
P1 4
EA 4
8
31
27
P1 5
EA 5
7
30
26
P1 6
EA 6
6
29
25
P1 7
EA 7
5
40
36
P43
EA 8
27
41
37
P44
OE
24
42
38
P45
EA10
23
4
43
P46
EA11
25
16
11
P70
EA12
4
17
12
P71
EA13
28
18
13
P72
EA14
29
2
41
P41
CE
22
1
40
P40
EA16
2
19
14
P73
EA15
3
3
42
P42
PGM
31
5
44
P47
VCC
32
6
1
P52
20
15
AVCC
9, 10
4, 5
VCC
VSS
16
14
9
TEST
11
6
STBY
15, 32
10, 28
VSS
(/AVSS)
Note: All pins not listed in this figure should be left open.
Legend:
VPP:
EO7 to EO0:
EA16 to EA0:
OE:
CE:
PGM:
Programming power supply (12.5 V)
Data input/output
Address input
Output enable
Chip enable
Program enable
Figure 19.3 Socket Adapter Pin Assignments (H8/3567)
Rev. 3.00 Mar 17, 2006 page 499 of 706
REJ09B0303-0300
Section 19 ROM
EPROM Socket
H8/3567U
DP-64S FP-64A
Pin
Pin
HN27C101
(32 pins)
7
63
RES
VPP
1
8
64
NMI
EA 9
26
43
35
P60
EO0
13
50
42
P61
EO1
14
49
41
P62
EO2
15
48
40
P63
EO3
17
44
36
P64
EO4
18
45
37
P65
EO5
19
46
38
P66
EO6
20
47
39
P67
EO7
21
59
51
P1 0
EA 0
12
58
50
P1 1
EA 1
11
57
49
P1 2
EA 2
10
56
48
P1 3
EA 3
9
55
47
P1 4
EA 4
8
53
45
P1 5
EA 5
7
52
44
P1 6
EA 6
6
51
43
P1 7
EA 7
5
62
54
P43
EA 8
27
63
55
P44
OE
24
64
56
P45
EA10
23
4
60
P46
EA11
25
16
8
P70
EA12
4
17
9
P71
EA13
28
18
10
P72
EA14
29
2
58
P41
CE
22
1
57
P40
EA16
2
19
11
P73
EA15
3
3
59
P42
PGM
31
5
61
P47
VCC
32
6
62
P52
20
12
AVCC
21
13
DrVCC
9, 10
1, 2
VCC
VSS
16
14
6
TEST
11
3
STBY
32
24
DrVSS
15, 54
7, 46
VSS
(/AVSS)
Note: All pins not listed in this figure should be left open.
Legend:
VPP:
EO7 to EO0:
EA16 to EA0:
OE:
CE:
PGM:
Programming power supply (12.5 V)
Data input/output
Address input
Output enable
Chip enable
Program enable
Figure 19.4 Socket Adapter Pin Assignments (H8/3567U)
Rev. 3.00 Mar 17, 2006 page 500 of 706
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Section 19 ROM
Address in MCU mode
Address in writer mode
H'0000
H'0000
On-chip
PROM
H'DFFF
H'DFFF
Undetermined
value output*
H'1FFFF
Note: * If this address area is read in writer mode, the output data is not guaranteed.
Figure 19.5 Memory Map in Writer Mode
Rev. 3.00 Mar 17, 2006 page 501 of 706
REJ09B0303-0300
Section 19 ROM
19.4
PROM Programming
The write, verify, and other sub-modes of the writer mode are selected as shown in table 19.3.
Table 19.3 Selection of Sub-Modes in Writer Mode
Sub-Mode
CE
OE
PGM
VPP
VCC
EO7 to EO0
EA16 to EA0
Write
Low
High
Low
VPP
VCC
Data input
Address input
Verify
Low
Low
High
VPP
VCC
Data output
Address input
Programming
inhibited
Low
Low
High
High
Low
High
Low
High
Low
High
Low
High
VPP
VCC
High impedance
Address input
The H8/3577, H8/3567, and H8/3567U PROM have the same standard read/write specifications as
the HN27C101 EPROM. Page programming is not supported, however, so do not select page
programming mode. PROM programmers that provide only page programming cannot be used.
When selecting a PROM programmer, check that it supports a byte-at-a-time high-speed
programming mode. Be sure to set the address range to H'0000 to H'DFFF for the H8/3577,
H8/3567, and H8/3567U.
19.4.1
Programming and Verification
An efficient, high-speed programming procedure can be used to program and verify PROM data.
This procedure programs data quickly without subjecting the chip to voltage stress and without
sacrificing data reliability. It leaves the data undefined in unused addresses.
Figure 19.6 shows the basic high-speed programming flowchart.
Tables 19.4 and 19.5 list the electrical characteristics of the chip in writer mode. Figure 19.7
shows a program/verify timing chart.
Rev. 3.00 Mar 17, 2006 page 502 of 706
REJ09B0303-0300
Section 19 ROM
Start
Set program/verify mode
VCC = 6.0 V ±0.25 V,
VPP = 12.5 V ±0.3 V
Address = 0
n=0
n + 1→ n
Program tPW = 0.2 ms ±5%
No
Yes
n < 25?
No
Address + 1 → address
Verify OK?
Yes
Program tOPW = 0.2n ms
Last address?
No
Yes
Set read mode
VCC = 5.0 V ±0.25 V,
VPP = VCC
Error
No go
Read all
addresses
Go
End
Figure 19.6 High-Speed Programming Flowchart
Rev. 3.00 Mar 17, 2006 page 503 of 706
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Section 19 ROM
Table 19.4 DC Characteristics
When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Input high
voltage
EO7–EO0,
EA16–EA0,
OE, CE, PGM
VIH
2.4
—
VCC + 0.3
V
Input low
voltage
EO7–EO0,
EA16–EA0,
OE, CE, PGM
VIL
–0.3
—
0.8
V
Output high
voltage
EO7–EO0
VOH
2.4
—
—
V
IOH = –200 µA
Output low
voltage
EO7–EO0
VOL
—
—
0.45
V
IOL = 1.6 mA
Input leakage EO7–EO0,
current
EA16–EA0,
OE, CE, PGM
|ILI|
—
—
2
µA
Vin = 5.25 V/0.5 V
VCC current
ICC
—
—
40
mA
VPP current
IPP
—
—
40
mA
Rev. 3.00 Mar 17, 2006 page 504 of 706
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Section 19 ROM
Table 19.5 AC Characteristics
When VCC = 6.0 V ±0.25 V, VPP = 12.5 V ±0.3 V, Ta = 25°C ±5°C
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Address setup time
tAS
2
—
—
µs
See figure 19.7*
OE setup time
tOES
2
—
—
µs
Data setup time
tDS
2
—
—
µs
Address hold time
tAH
0
—
—
µs
Data hold time
tDH
2
—
—
µs
Data output disable time
tDF
—
—
130
ns
VPP setup time
tVPS
2
—
—
µs
Program pulse width
tPW
0.19
0.20
0.21
ms
OE pulse width for
overwrite-programming
tOPW
0.19
—
5.25
ms
VCC setup time
tVCS
2
—
—
µs
CE setup time
tCES
2
—
—
µs
Data output delay time
tOE
0
—
150
ns
Note: * Input pulse level: 0.8 V to 2.2 V
Input rise/fall time ≤ 20 ns
Timing reference levels: input—1.0 V, 2.0 V; output—0.8 V, 2.0 V
Rev. 3.00 Mar 17, 2006 page 505 of 706
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Section 19 ROM
Write
Verify
Address
tAH
tAS
Data
Input data
tDS
VPP
VCC
Output data
tDH
tDF
VPP
VCC
tVPS
VCC + 1
VCC
tVCS
CE
tCES
PGM
tPW
OE
tOES
tOE
tOPW
Figure 19.7 PROM Program/Verify Timing
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Section 19 ROM
19.4.2
Notes on Programming
(1) Program with the specified voltages and timing. The programming voltage (VPP) is
12.5 V.
Caution: Applied voltages in excess of the specified values can permanently destroy the chip. Be
particularly careful about the PROM programmer’s overshoot characteristics.
If the PROM programmer is set to HN27C101 specifications, VPP will be 12.5 V.
(2) Before writing data, check that the socket adapter and chip are correctly mounted in the
PROM writer. Overcurrent damage to the chip can result if the index marks on the PROM
programmer, socket adapter, and chip are not correctly aligned.
(3) Don’t touch the socket adapter or chip while writing. Touching either of these can cause
contact faults and write errors.
(4) Page programming is not supported. Do not select page programming mode.
(5) The PROM size is 56 kbytes. Set the address range to H'0000 to H'DFFF for the H8/3577,
H8/3567, and H8/3567U. When programming, specify H'FF data for unused address areas
(H'E000 to H'1FFFF).
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Section 19 ROM
19.4.3
Reliability of Programmed Data
An effective way to assure the data holding characteristics of the programmed chips is to bake
them at 150°C, then screen them for data errors. This procedure quickly eliminates chips with
PROM memory cells prone to early failure.
Figure 19.8 shows the recommended screening procedure.
Write and verify program
Bake with power off
125° to 150°C, 24 to 48Hr
Read and check program
Mount
Figure 19.8 Recommended Screening Procedure
If a group of write errors occurs while the same PROM programmer is in use, stop programming
and check the PROM programmer and socket adapter for defects.
Please inform Renesas Technology of any abnormal conditions noted during programming or in
screening of program data after high-temperature baking.
Rev. 3.00 Mar 17, 2006 page 508 of 706
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Section 20 Clock Pulse Generator
Section 20 Clock Pulse Generator
20.1
Overview
The H8/3577 Group and H8/3567 Group have an on-chip clock pulse generator (CPG) that
generates the system clock (φ), the bus master clock, and internal clocks.
The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, clock
selection circuit, medium-speed clock divider, bus master clock selection circuit.
20.1.1
Block Diagram
Figure 20.1 shows a block diagram of the clock pulse generator.
EXTAL
Duty
adjustment
circuit
Oscillator
XTAL
Medium-speed
clock divider
Clock
selection
circuit
φ/2 to φ/32
Bus master
clock
selection
circuit
φ
System clock
To φ pin
Internal clock
To supporting
modules
Bus master clock
To CPU, DTC
Figure 20.1 Block Diagram of Clock Pulse Generator
20.1.2
Register Configuration
The clock pulse generator is controlled by the standby control register (SBYCR). Table 20.1
shows the register configuration.
Table 20.1 CPG Registers
Name
Abbreviation
R/W
Initial Value
Address
Standby control register
SBYCR
R/W
H'00
H'FF84
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Section 20 Clock Pulse Generator
20.2
Register Descriptions
20.2.1
Standby Control Register (SBYCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
—
SCK2
SCK1
SCK0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
Only bits 0 to 2 are described here. For a description of the other bits, see section 21.2.1, Standby
Control Register (SBYCR).
SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bits 2 to 0—System Clock Select 2 to 0 (SCK2 to SCK0): These bits select the bus master clock
for high-speed mode and medium-speed mode.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
Description
0
0
0
Bus master is in high-speed mode
1
Medium-speed clock is φ/2
0
Medium-speed clock is φ/4
1
Medium-speed clock is φ/8
0
0
Medium-speed clock is φ/16
1
Medium-speed clock is φ/32
1
—
—
1
1
Rev. 3.00 Mar 17, 2006 page 510 of 706
REJ09B0303-0300
(Initial value)
Section 20 Clock Pulse Generator
20.3
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
20.3.1
Connecting a Crystal Resonator
Circuit Configuration: A crystal resonator can be connected as shown in the example in figure
20.2. Select the damping resistance Rd according to table 20.2. An AT-cut parallel-resonance
crystal should be used.
CL1
EXTAL
XTAL
Rd
CL2
CL1 = CL2 = 10 to 22 pF
Figure 20.2 Connection of Crystal Resonator (Example)
Table 20.2 Damping Resistance Value
Frequency (MHz)
2
4
8
10
12
16
20
Rd (Ω)
1k
500
200
0
0
0
0
Crystal resonator: Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal
resonator that has the characteristics shown in table 20.3 and the same frequency as the system
clock (φ).
CL
L
Rs
XTAL
EXTAL
C0
AT-cut parallel-resonance type
Figure 20.3 Crystal Resonator Equivalent Circuit
Rev. 3.00 Mar 17, 2006 page 511 of 706
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Section 20 Clock Pulse Generator
Table 20.3 Crystal Resonator Parameters
Frequency (MHz)
2
4
8
10
12
16
20
RS max (Ω)
500
120
80
70
60
50
40
C0 max (pF)
7
7
7
7
7
7
7
Note on Board Design: When a crystal resonator is connected, the following points should be
noted.
Other signal lines should be routed away from the oscillator circuit to prevent induction from
interfering with correct oscillation. See figure 20.4.
When designing the board, place the crystal resonator and its load capacitors as close as possible
to the XTAL and EXTAL pins.
Avoid
Signal A Signal B
CL2
H8/3577 Group or
H8/3567 Group
chip
XTAL
EXTAL
CL1
Figure 20.4 Example of Incorrect Board Design
Rev. 3.00 Mar 17, 2006 page 512 of 706
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Section 20 Clock Pulse Generator
20.3.2
External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
20.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF.
In example (b), make sure that the external clock is held high in standby mode.
EXTAL
XTAL
External clock input
Open
(a) XTAL pin left open
EXTAL
External clock input
XTAL
(b) Complementary clock input at XTAL pin
Figure 20.5 External Clock Input (Examples)
External Clock: The external clock signal should have the same frequency as the system clock
(φ).
Table 20.4 and figure 20.6 show the input conditions for the external clock.
Rev. 3.00 Mar 17, 2006 page 513 of 706
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Section 20 Clock Pulse Generator
Table 20.4 External Clock Input Conditions
VCC = 5.0 V ±10%
Item
Symbol
Min
Max
Unit
Test Conditions
External clock input low pulse
width
tEXL
20
—
ns
Figure 20.6
External clock input high pulse
width
tEXH
20
—
ns
External clock rise time
tEXr
—
5
ns
External clock fall time
tEXf
—
5
ns
Clock low pulse width
tCL
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
ns
φ < 5 MHz
0.4
0.6
tcyc
φ ≥ 5 MHz
80
—
ns
φ < 5 MHz
Clock high pulse width
tCH
tEXH
Figure 22.4
tEXL
VCC × 0.5
EXTAL
tEXr
tEXf
Figure 20.6 External Clock Input Timing
Table 20.5 shows the external clock output settling delay time, and figure 20.7 shows the external
clock output settling delay timing. The oscillator and duty adjustment circuit have a function for
adjusting the waveform of the external clock input at the EXTAL pin. When the prescribed clock
signal is input at the EXTAL pin, internal clock signal output is fixed after the elapse of the
external clock output settling delay time (tDEXT). As the clock signal output is not fixed during the
tDEXT period, the reset signal should be driven low to maintain the reset state.
Rev. 3.00 Mar 17, 2006 page 514 of 706
REJ09B0303-0300
Section 20 Clock Pulse Generator
Table 20.5 External Clock Output Settling Delay Time
Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V
Item
External clock
output settling
delay time
Note:
*
VCC
STBY
Symbol
Min
Max
Unit
Notes
*
500
—
µs
Figure 20.7
tDEXT
tDEXT includes a 10tcyc RES pulse width (tRESW).
4.5 V
VIH
EXTAL
φ
(internal or external)
RES
tDEXT*
Note: * tDEXT includes a RES pulse width (tRESW).
Figure 20.7 External Clock Output Settling Delay Timing
Rev. 3.00 Mar 17, 2006 page 515 of 706
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Section 20 Clock Pulse Generator
20.4
Duty Adjustment Circuit
When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty
cycle of the clock signal from the oscillator to generate the system clock (φ).
20.5
Medium-Speed Clock Divider
The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32
clocks.
20.6
Bus Master Clock Selection Circuit
The bus master clock selection circuit selects the system clock (φ) or one of the medium-speed
clocks (φ/2, φ/4, φ/8, φ/16, or φ/32) to be supplied to the bus master, according to the settings of
bits SCK2 to SCK0 in SBYCR.
20.7
Universal Clock Pulse Generator
[H8/3567 Group Version with On-Chip USB]
The H8/3567 Group version with an on-chip USB has a USB clock pulse generator (UCPG) that
generates the 48 MHz USB clock (CLK48) from an 8, 12, 16, or 20 MHz input clock. The input
clock can be selected from (1) the 12 MHz crystal oscillator or (2) the system clock (only when
the system clock is 8, 12, 16, or 20 MHz).
The USB clock pulse generator consists of an oscillator, clock selection circuit, and frequency
division/multiplication circuit.
20.7.1
Block Diagram
Figure 20.8 shows a block diagram of the USB clock pulse generator.
EXTAL12
Oscillator
XTAL12
φ (system clock)
12 MHz
Clock
selection
circuit
frequency
48 MHz
division/
multiplication
circuit
Figure 20.8 Block Diagram of USB Clock Pulse Generator
Rev. 3.00 Mar 17, 2006 page 516 of 706
REJ09B0303-0300
To USB
Section 20 Clock Pulse Generator
20.7.2
Registers
Table 20.6 USB Clock Pulse Generator Registers
Name
Abbreviation
R/W
Initial Value
Address
USB control/status register 0
USBCSR0
R/W
H'00
H'FDF5
USB control register
USBCR
R/W
H'7F
H'FDFD
USB PLL control register
UPLLCR
R/W
H'01
H'FDFE
USB Control/Status Register 0 (USBCSR0)
Bit
7
6
5
4
3
DP5CNCT DP4CNCT DP3CNCT DP2CNCT EP0STOP
2
1
0
EPIVLD
EP0OTC
CKSTOP
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
USBCSR0 contains flags (DPCNCT) that indicate the USB hubs’ downstream port connection
status, and bits that control the operation of the USB function.
Only bit 0 is described here. For details of the other bits, see section 7.2.11, USB Control/Status
Register 0 (USBCSR0).
USBCSR0 is initialized to H'00 by a system reset, and bits 3 to 0 are also cleared to 0 by a
function soft reset.
Bit 0—Clock Stop (CKSTOP): Controls the USB function operating clock. When the USB
function is placed in the suspend state due to a bus idle condition, this bit should be set to 1 after
the necessary processing is completed. The clock supply to the USB function is then stopped,
reducing power consumption.
When the CKSTOP bit is set to 1, writes to USB module registers are invalid. If these registers are
read, the contents of the read data are not guaranteed, but there are no read-related status changes
(such as decrementing of FVSR).
If a bus idle condition of the specified duration or longer is detected, the suspend IN interrupt flag
is set, and when a change in the bus status is subsequently detected the suspend OUT interrupt flag
is set. When the suspend OUT interrupt flag is set, the CKSTOP bit is simultaneously cleared to 0.
Rev. 3.00 Mar 17, 2006 page 517 of 706
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Section 20 Clock Pulse Generator
Bit 0
CKSTOP
Description
0
Clock is supplied to USB function
(Initial value)
[Clearing conditions]
1
•
System reset
•
Function soft reset
•
Suspend OUT interrupt flag setting
Clock supply to USB function is stopped
[Setting condition]
When 1 is written to CKSTOP after reading CKSTOP = 0 in the function suspend
state.
USB Control Register (USBCR)
Bit
7
6
5
4
3
2
1
0
FADSEL
FONLY
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FNCSTP UIFRST HPLLRST HSRST FPLLRST FSRST
USBCR contains bits (FADSEL, FONLY, FNCSTP) that control USB function and USB hub
internal connection, and reset control bits for sequential enabling of the operation of each part
according to the procedure in USB module initialization.
Only bits 3 and 1 are described here. For details of the other bits, see section 7.2.18, USB Control
Register (USBCR).
USBCR is initialized to H'7F by a system reset [in an H8/3567 reset (by RES input or the
watchdog timer), and in hardware standby mode]. It is not initialized in software standby mode.
Bit 3—Hub Block PLL Soft Reset (HPLLRST): Resets the USB bus clock synchronization
circuit (DPLL) in the hub.
When HPLLRST is set to 1, the DPLL circuit in the USB hub block is reset, and bus clock
synchronous operation halts. HPLLRST is cleared to 0 after PLL operation stabilizes.
Rev. 3.00 Mar 17, 2006 page 518 of 706
REJ09B0303-0300
Section 20 Clock Pulse Generator
Bit 3
HPLLRST
Description
0
USB hub block DPLL is placed in operational state
1
USB hub block DPLL is placed in reset state
(Initial value)
Bit 1—Function Block PLL Soft Reset (FPLLRST): Resets the USB bus clock synchronization
circuit (DPLL) in the USB function block.
When FPLLRST is set to 1, the DPLL circuit in the USB function block is reset, and bus clock
synchronous operation halts. FPLLRST is cleared to 0 after PLL operation stabilizes.
Bit 1
FPLLRST
Description
0
USB function block DPLL is placed in operational state
1
USB function block DPLL is placed in reset state
(Initial value)
USB PLL Control Register (UPLLCR)
Bit
7
6
5
—
—
—
4
3
2
1
Initial value
0
0
0
0
0
0
0
1
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
CKSEL2 CKSEL1 CKSEL0 PFSEL1
0
PFSEL0
UPLLCR contains bits that control the method of generating the USB function and USB hub
operating clock.
UPLLCR is initialized to H'01 by a system reset [in an H8/3567 reset (by RES input or the
watchdog timer), and in hardware standby mode]. It is not initialized in software standby mode.
Bits 4 to 2—Clock Source Select 2 to 0 (CKSEL2 to CKSEL0): These bits select the source of
the clock supplied to the USB operating clock generator (PLL).
CKSEL0 selects either the USB clock pulse generator (XTAL12) or the system clock pulse
generator (XTATL) as the clock source. The USB clock pulse generator starts operating when it is
selected as a clock source. It operates with CKSEL2 = 1, CKSEL0 = 1.
When CKSEL2 = 1 and CKSEL1 = 1, the PLL operates.
Rev. 3.00 Mar 17, 2006 page 519 of 706
REJ09B0303-0300
Section 20 Clock Pulse Generator
When CKSEL1 is cleared to 0, a clock is not input to the PLL, and PLL operation halts. The 48
MHz signal from the USB clock pulse generator can be input directly as the USB operating clock.
When CKSEL2 is cleared to 0, a clock is not input to the PLL, and PLL operation halts.
Bit 4
Bit 3
Bit 2
CKSEL2
CKSEL1
CKSEL0
0
1
Description
0
0
PLL operation halted, clock input halted
—
—
PLL operation halted, clock input halted
0
0
Setting prohibited
1
PLL operation halted
(Initial value)
USB clock pulse generator (XTAL12: 48 MHz) used
directly instead of PLL output
1
0
PLL operates with system clock pulse generator (XTAL)
as clock source
1
PLL operates with USB clock pulse generator (XTAL12)
as clock source
Bits 1 and 0—PLL Frequency Select 1 and 0 (PFSEL1, PFSEL0): These bits select the
frequency of the clock supplied to the USB operating clock generator (PLL).
The PLL generates the 48 MHz USB operating clock using the frequency selected with these bits
as the clock source frequency.
Bit 1
Bit 0
PFSEL1
PFSEL0
Description
0
0
PLL input clock is 8 MHz
1
PLL input clock is 12 MHz
0
PLL input clock is 16 MHz
1
PLL input clock is 20 MHz
1
Rev. 3.00 Mar 17, 2006 page 520 of 706
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(Initial value)
Section 21 Power-Down State
Section 21 Power-Down State
21.1
Overview
In addition to the normal program execution state, the H8/3577 Group and H8/3567 Group have a
power-down state in which operation of the CPU and oscillator is halted and power dissipation is
reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip
supporting modules, and so on.
The operating modes are as follows:
1. High-speed mode
2. Medium-speed mode
3. Sleep mode
4. Module stop mode
5. Software standby mode
6. Hardware standby mode
Of these, 2 to 6 are power-down modes. Sleep mode is a CPU mode, medium-speed mode is a
CPU operating clock state, and module stop mode is an on-chip supporting module mode. Certain
combinations of these modes can be set.
After a reset, the MCU is in high-speed mode and module stop mode.
Table 21.1 shows the internal chip states in each mode, and table 21.2 shows the conditions for
transition to the various modes. Figure 21.1 shows a mode transition diagram.
Rev. 3.00 Mar 17, 2006 page 521 of 706
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Section 21 Power-Down State
Table 21.1 H8/3577 Group and H8/3567 Group Internal States in Each Mode
Function
HighSpeed
MediumSpeed
Sleep
Module
Stop
Software
Standby
Hardware
Standby
System clock oscillator
Functioning
Functioning
Functioning
Functioning
Halted
Halted
CPU
operation
Instructions
Functioning
Mediumspeed
Halted
Functioning
Halted
Halted
Registers
Functioning
Mediumspeed
Retained
Functioning
Retained
Undefined
NMI
Functioning
Functioning
Functioning
Functioning
Functioning
Halted
WDT0
Functioning
Functioning
Functioning
Functioning
Halted
(retained)
Halted
(reset)
TMR0, TMR1
Functioning
Functioning
Functioning
Functioning/ Halted
(retained)
halted
(retained)
Halted
(reset)
Functioning
Functioning
Functioning
Functioning/ Halted
(reset)
halted
(reset)
Halted
(reset)
External
interrupts
IRQ0
IRQ1
IRQ2
On-chip
supporting
module
operation
FRT
TMRX, Y
Timer
connection
IIC0
IIC1
SCI0
PWM
PWMX
A/D
RAM
Functioning
Functioning
Functioning
Functioning
Retained
Retained
I/O
Functioning
Functioning
Functioning
Functioning
Retained
High
impedance
USB
Functioning
Functioning
Functioning
Functioning/ Functioning/ Halted
halted*
halted*
(reset)
Note: “Halted (retained)” means that internal register values are retained. The internal state is
“operation suspended.”
“Halted (reset)” means that internal register values and internal states are initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
* Functioning (USB hub part only) when the USB clock (XTAL12, EXTAL12) is selected as
a USB operating clock, and halted (retained) when not selected.
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Section 21 Power-Down State
Program-halted state
STBY pin = low
Reset state
STBY pin = high
RES pin = low
Hardware
standby mode
RES pin = high
Program execution state
SSBY = 0
SLEEP
instruction
Sleep mode
High-speed
mode
Any interrupt
SCK2 to
SCK0 ≠ 0
SCK2 to
SCK0 = 0
Medium-speed
mode
SLEEP
instruction
External
interrupt*
: Transition after exception handling
SSBY = 1
Software
standby mode
: Power-down mode
Notes: When a transition is made between modes by means of an interrupt, transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs whenever
RES goes low.
From any state, a transition to hardware standby mode occurs when STBY goes low.
* NMI, IRQ0 to IRQ2
Figure 21.1 Mode Transitions
Table 21.2 Power-Down Mode Transition Conditions
State before
Transition
High-speed/
medium-speed
Control Bit States
at Time of Transition
SSBY
State after Transition
by SLEEP Instruction
State after Return
by Interrupt
0
Sleep
High-speed/
medium-speed
1
Software standby
High-speed/
medium-speed
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Section 21 Power-Down State
21.1.1
Register Configuration
The power-down state is controlled by the SBYCR and MSTPCR registers. Table 21.3
summarizes these registers.
Table 21.3 Power-Down State Registers
Name
Abbreviation
R/W
Initial Value
Address
Standby control register
SBYCR
R/W
H'00
H'FF84
Module stop control register
MSTPCRH
R/W
H'3F
H'FF86
MSTPCRL
R/W
H'FF
H'FF87
21.2
Register Descriptions
21.2.1
Standby Control Register (SBYCR)
Bit
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
—
SCK2
SCK1
SCK0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
SBYCR is an 8-bit readable/writable register that performs power-down mode control.
SBYCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit 7—Software Standby (SSBY): Determines the operating mode, in combination with other
control bits, when a power-down mode transition is made by executing a SLEEP instruction. The
SSBY setting is not changed by a mode transition due to an interrupt, etc.
Bit 7
SSBY
Description
0
Transition to sleep mode after execution of SLEEP instruction in high-speed mode or
medium-speed mode
(Initial value)
1
Transition to software standby mode, after execution of SLEEP instruction in highspeed mode or medium-speed mode
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Section 21 Power-Down State
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the time the MCU
waits for the clock to stabilize when software standby mode is cleared and a transition is made to
high-speed mode or medium-speed mode by means of a specific interrupt or instruction. With
crystal oscillation, refer to table 21.4 and make a selection according to the operating frequency so
that the standby time is at least 8 ms (the oscillation settling time). With an external clock, any
selection can be made.
Bit 6
Bit 5
Bit 4
STS2
STS1
STS0
Description
0
0
0
Standby time = 8192 states
1
Standby time = 16384 states
0
Standby time = 32768 states
1
Standby time = 65536 states
0
Standby time = 131072 states
1
Standby time = 262144 states
0
Reserved
1
Standby time = 16 states
1
1
0
1
(Initial value)
Bit 3—Reserved: This bit cannot be modified and is always read as 0.
Bits 2 to 0—System Clock Select (SCK2 to SCK0): These bits select the clock for the bus
master in high-speed mode and medium-speed mode.
Bit 2
Bit 1
Bit 0
SCK2
SCK1
SCK0
Description
0
0
0
Bus master is in high-speed mode
1
Medium-speed clock is φ/2
0
Medium-speed clock is φ/4
1
Medium-speed clock is φ/8
0
Medium-speed clock is φ/16
1
Medium-speed clock is φ/32
—
—
1
1
0
1
(Initial value)
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Section 21 Power-Down State
21.2.2
Module Stop Control Register (MSTPCR)
MSTPCRH
Bit
7
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP MSTP
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
Read/Write
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
MSTPCR comprises two 8-bit readable/writable registers that perform module stop mode control.
MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
MSTRCRH and MSTPCRL Bits 7 to 0—Module Stop (MSTP 15 to MSTP 0): These bits
specify module stop mode. See table 21.3 for the method of selecting on-chip supporting modules.
MSTPCRH, MSTPCRL
Bits 7 to 0
MSTP15 to MSTP0
Description
0
Module stop mode is cleared
(Initial value of MSTP15, MSTP14)
1
Module stop mode is set
(Initial value of MSTP13 to MSTP0)
21.3
Medium-Speed Mode
When the SCK2 to SCK0 bits in SBYCR are set to 1 in high-speed mode, the operating mode
changes to medium-speed mode at the end of the bus cycle. In medium-speed mode, the CPU
operates on the operating clock (φ/2, φ/4, φ/8, φ/16, or φ/32) specified by the SCK2 to SCK0 bits.
On-chip supporting modules other than the bus masters always operate on the high-speed clock
(φ).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if φ/4 is selected as the operating clock, on-chip
memory is accessed in 8 states, and internal I/O registers in 12 states.
Medium-speed mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode and medium-speed mode is cleared at the end of the current bus cycle.
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Section 21 Power-Down State
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made
to software standby mode. When software standby mode is cleared by an external interrupt,
medium-speed mode is restored.
When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is
cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
When the STBY pin is driven low, a transition is made to hardware standby mode.
Figure 21.2 shows the timing for transition to and clearance of medium-speed mode.
Medium-speed mode
φ,
supporting module
clock
Bus master clock
Internal address
bus
SBYCR
SBYCR
Internal write signal
Figure 21.2 Medium-Speed Mode Transition and Clearance Timing
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Section 21 Power-Down State
21.4
Sleep Mode
21.4.1
Sleep Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, the CPU enters
sleep mode. In sleep mode, CPU operation stops but the contents of the CPU’s internal registers
are retained. Other supporting modules do not stop.
21.4.2
Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or with the RES pin or STBY pin.
Clearing with an Interrupt: When an interrupt request signal is input, sleep mode is cleared and
interrupt exception handling is started. Sleep mode will not be cleared if interrupts are disabled, or
if interrupts other than NMI have been masked by the CPU.
Clearing with the RES Pin: When the RES pin is driven low, the reset state is entered. When the
RES pin is driven high after the prescribed reset input period, the CPU begins reset exception
handling.
Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware
standby mode.
21.5
Module Stop Mode
21.5.1
Module Stop Mode
Module stop mode can be set for individual on-chip supporting modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
Table 21.4 shows MSTP bits and the corresponding on-chip supporting modules.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating again at the end of the bus cycle. In module stop mode, the internal states of
modules other than the SCI, A/D converter, 8-bit PWM module, and 14-bit PWM module, are
retained. Additionally, when the USB clock (XTAL12, EXTAL12) is selected as a USB operating
clock, the USB module does not stop operating even when the MSTP1 bit is set to 1. To stop the
Rev. 3.00 Mar 17, 2006 page 528 of 706
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Section 21 Power-Down State
USB module, initialize UPLLCR to H'01 before setting the MSTP1 bit to 1. Also, it is
recommended to initialize USBCR to H'7F to prepare for cancellation of the module stop state.
After reset release, all modules other than the DTC are in module stop mode.
When an on-chip supporting module is in module stop mode, read/write access to its registers is
disabled.
Table 21.4 MSTP Bits and Corresponding On-Chip Supporting Modules
Register
Bit
MSTPCRH
MSTP15*
—
MSTP14*
—
MSTPCRL
Note:
21.5.2
*
Module
MSTP13
16-bit free-running timer (FRT)
MSTP12
8-bit timers (TMR0, TMR1)
MSTP11
8-bit PWM timer (PWM), 14-bit PWM timer (PWMX)
MSTP10*
—
MSTP9
A/D converter
MSTP8
8-bit timers (TMRX, TMRY), timer connection
MSTP7
MSTP6*
Serial communication interface 0 (SCI0)
—
MSTP5*
—
MSTP4
I C bus interface (IIC) channel 0
MSTP3
I C bus interface (IIC) channel 1
MSTP2*
—
MSTP1
MSTP0*
—
2
2
Universal serial bus interface (USB)
Bits 15, 14, 10, 6, 5, 2, and 0 can be read or written to, must be set to 1.
Usage Note
The MSTP bit for modules not included on-chip must be set to 1.
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Section 21 Power-Down State
21.6
Software Standby Mode
21.6.1
Software Standby Mode
If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby
mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop.
However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip
supporting modules other than the SCI, PWM, and PWMX, and of the I/O ports, are retained.*
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
Note: * When the USB clock (XTAL12, EXTAL12) is selected as a USB operating clock, the
USB module does not stop operating even under the software standby mode. To realize
the power save state, initialize UPLLCR to H'01 and USBCR to H'7F.
21.6.2
Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, or pin IRQ0, IRQ1, or IRQ2),
or by means of the RES pin or STBY pin.
Clearing with an Interrupt: When an NMI, IRQ0, IRQ1, or IRQ2 interrupt request signal is
input, clock oscillation starts, and after the elapse of the time set in bits STS2 to STS0 in SYSCR,
stable clocks are supplied to the entire chip, software standby mode is cleared, and interrupt
exception handling is started.
Software standby mode cannot be cleared with an IRQ0, IRQ1, or IRQ2 interrupt if the
corresponding enable bit has been cleared to 0 or has been masked by the CPU.
Clearing with the RES Pin: When the RES pin is driven low, clock oscillation is started. At the
same time as clock oscillation starts, clocks are supplied to the entire chip. Note that the RES pin
must be held low until clock oscillation stabilizes. When the RES pin goes high, the CPU begins
reset exception handling.
Clearing with the STBY Pin: When the STBY pin is driven low, a transition is made to hardware
standby mode.
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Section 21 Power-Down State
21.6.3
Setting Oscillation Settling Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the
oscillation settling time).
Table 21.5 shows the standby times for different operating frequencies and settings of bits STS2 to
STS0.
Table 21.5 Oscillation Settling Time Settings
20
STS2 STS1 STS0 Standby Time MHz
16
MHz
12
MHz
10
MHz
8
MHz
6
MHz
4
MHz
2
MHz
Unit
0
4.1
ms
0
0
8192 states
0.41
0.51
0.65
0.8
1.0
1.3
2.0
1
16384 states
0.82
1.0
1.3
1.6
2.0
2.7
4.1
0
32768 states
1.6
2.0
2.7
3.3
4.1
5.5
1
65536 states
3.3
4.1
5.5
6.6
0
0
131072 states 6.6
8.2
10.9
13.1 16.4
1
262144 states
13.1 16.4
21.8
26.2
32.8
43.6
65.6
131.2
1
0
Reserved
—
—
—
—
—
—
—
—
1
16 states
0.8
1.0
1.3
1.6
2.0
2.7
4.0
8.0
1
1
8.2
8.2
16.4
10.9 16.4
32.8
21.8
65.5
8.2
32.8
µs
Legend:
: Recommended time setting
—: Don’t care
Using an External Clock: Any value can be set. Normally, use of the minimum time is
recommended.
21.6.4
Software Standby Mode Application Example
Figure 21.3 shows an example in which a transition is made to software standby mode at the
falling edge on the NMI pin, and software standby mode is cleared at the rising edge on the NMI
pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Rev. 3.00 Mar 17, 2006 page 531 of 706
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Section 21 Power-Down State
Oscillator
φ
NMI
NMIEG
SSBY
NMI
exception
handling
NMIEG = 1
SSBY = 1
Software standby mode
(power-down state)
Oscillation
settling time
tOSC2
NMI exception
handling
SLEEP instruction
Figure 21.3 Software Standby Mode Application Example
21.6.5
Usage Note
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
Current dissipation increases while waiting for oscillation to settle.
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Section 21 Power-Down State
21.7
Hardware Standby Mode
21.7.1
Hardware Standby Mode
When the STBY pin is driven low, a transition is made to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low.
Do not change the state of the mode pins (MD1 and MD0, TEST) while the chip is in hardware
standby mode.
Hardware standby mode is cleared by means of the STBY pin and the RES pin. When the STBY
pin is driven high while the RES pin is low, the reset state is set and clock oscillation is started.
Ensure that the RES pin is held low until the clock oscillation settles (at least 8 ms—the oscillation
settling time—when using a crystal oscillator). When the RES pin is subsequently driven high, a
transition is made to the program execution state via the reset exception handling state.
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Section 21 Power-Down State
21.7.2
Hardware Standby Mode Timing
Figure 21.4 shows an example of hardware standby mode timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation settling time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
settling time
Figure 21.4 Hardware Standby Mode Timing
Rev. 3.00 Mar 17, 2006 page 534 of 706
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Reset exception
handling
Section 22 Electrical Characteristics
Section 22 Electrical Characteristics
22.1
Absolute Maximum Ratings
Table 22.1 lists the absolute maximum ratings.
Table 22.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +7.0
V
Program voltage
VPP
–0.3 to +13.5
V
Bus driver power supply voltage
(H8/3567U Group only)
DrVCC
–0.3 to +4.3
V
Input voltage (except port 7)
Vin
–0.3 to VCC + 0.3
V
Input voltage (port 7)
Vin
–0.3 to AVCC + 0.3
V
Analog power supply voltage
AVCC
–0.3 to +7.0
V
Analog input voltage
VAN
–0.3 to AVCC + 0.3
V
Operating temperature
Topr
–20 to +75
°C
Storage temperature
Tstg
–55 to +125
°C
Caution: Permanent damage to the chip may result if absolute maximum ratings are exceeded.
Rev. 3.00 Mar 17, 2006 page 535 of 706
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Section 22 Electrical Characteristics
22.2
DC Characteristics
Table 22.2 lists the DC characteristics. Table 22.3 lists the permissible output currents.
Table 22.2 DC Characteristics
1
1
Conditions: VCC = 5.0 V ±10%, AVCC* = 5.0 V ±10%, VSS = AVSS* = 0 V,
Ta = –20 to +75°C
Item
Symbol
Min
Typ
Max
Unit Test Conditions
1.0
—
—
V
—
—
VCC × 0.7
V
VT – VT
0.4
—
—
V
VIH
VCC – 0.7 —
VCC + 0.3
V
EXTAL
VCC × 0.7 —
VCC + 0.3
V
Port 7
2.0
—
AVCC + 0.3 V
Input pins
except (1) and
(2) above
2.0
—
VCC + 0.3
V
–0.3
—
0.5
V
–0.3
—
0.8
V
VCC – 0.5 —
—
V
IOH = –200 µA
3.5
—
—
V
IOH = –1 mA
2.0
—
—
V
IOH = –200 µA
Schmitt
P67 to P60* ,
3
trigger input IRQ2 to IRQ0*
voltage
2
Input high
voltage
RES, STBY,
7
NMI, MD1* ,
7
8
MD * , TEST*
(1)
–
VT
+
VT
+
(2)
–
0
Input low
voltage
RES, STBY,
7
7
MD1* , MD0* ,
8
TEST*
(3)
VIL
NMI, EXTAL,
input pins except
(1) and (3)
above
Output
All output pins
high voltage (except P47, and
P52)
4
P4 , P5 *
VOH
Output low
voltage
All output pins
VOL
—
—
0.4
V
IOL = 1.6 mA
Input
leakage
current
RES
Iin
—
—
10.0
µA
Vin = 0.5 to
VCC – 0.5 V
—
—
1.0
µA
—
—
1.0
µA
7
2
7
STBY, NMI, MD1* ,
7
8
MD0* , TEST*
Port 7
Rev. 3.00 Mar 17, 2006 page 536 of 706
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Vin = 0.5 to
AVCC – 0.5 V
Section 22 Electrical Characteristics
Item
Symbol
Min
Typ
Max
Unit Test Conditions
Three-state Ports 1 to 6
leakage
current
(off state)
7
Input
Ports 1 to 3*
pull-up
MOS
current
ITSI
—
—
1.0
µA
Vin = 0.5 to
VCC – 0.5 V
–IP
30
—
300
µA
Vin = 0 V
Cin
—
—
80
pF
Vin = 0 V
f = 1 MHz
Ta = 25°C
Input
RES
capacitance NMI
(4)
—
—
50
pF
7
P52, P47, P24* ,
7
P23* , P17, P16,
8
TEST*
—
—
20
pF
Input pins
except (4) above
—
—
15
pF
—
80
100
mA
Normal operation
(other than the above)
—
60
80
mA
Sleep mode
(with on-chip USB)
—
60
80
mA
Sleep mode
(other than the above)
6
Standby mode*
—
45
63
mA
—
0.2
5.0
µA
Ta ≤ 50°C
—
—
20.0
µA
50°C < Ta
—
1.5
3.0
mA
—
0.01
5.0
µA
AVCC =
2.0 V to 5.5 V
4.5
—
5.5
V
Operating
Idle/not used
Current
Normal operation
5
dissipation* (with on-chip USB)
Analog
power
supply
current
During A/D
conversion
ICC
AlCC
Idle
1
Analog power supply voltage*
AVCC
RAM standby voltage
VRAM
2.0
—
5.5
V
2.0
—
—
V
f = 20 MHz
Notes: 1. Do not leave the AVCC, and AVSS pins open even if the A/D converter is not used.
Even if the A/D converter is not used, apply a value in the range 2.0 V to 5.5 V to AVCC
by connection to the power supply (VCC), or some other method.
2. P67 to P60 include supporting module inputs multiplexed on those pins.
3. IRQ2 includes the ADTRG signal multiplexed on that pin.
Rev. 3.00 Mar 17, 2006 page 537 of 706
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Section 22 Electrical Characteristics
4. P52/SCK0/SCL0 and P47/SDA0 are NMOS push-pull outputs.
An external pull-up resistor is necessary to provide high-level output from SCL0 and
SDA0 (ICE = 1).
P52/SCK0 and P47 (ICE = 0) high levels are driven by NMOS.
5. Current dissipation values are for VIH min = VCC – 0.2 V and VIL max = 0.2 V with all
output pins unloaded and the on-chip pull-up MOSs in the off state.
6. The values are for VRAM ≤ VCC < 4.5 V, VIH min = VCC × 0.9, and VIL max = 0.3 V.
7. In the H8/3577
8. In the H8/3567
Table 22.3 Permissible Output Currents
Conditions: VCC = 4.0 to 5.5 V, AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V, Ta = –20 to +75°C
Item
Permissible output
low current (per pin)
SCL1, SCL0, SDA1,
SDA0
Symbol Min
Typ
Max
Unit
IOL
—
—
20
mA
—
—
2
mA
Permissible output
low current (total)
Other output pins
Total of all output pins,
including the above
∑ IOL
—
—
120
mA
Permissible output
high current (per pin)
All output pins
–IOH
—
—
2
mA
Permissible output
high current (total)
Total of all output pins
∑ –IOH
—
—
40
mA
Notes: 1. To protect chip reliability, do not exceed the output current values in table 22.3.
2. When driving a Darlington pair or LED, always insert a current-limiting resistor in the
output line, as show in figure 22.1.
Rev. 3.00 Mar 17, 2006 page 538 of 706
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Section 22 Electrical Characteristics
Table 22.4 Bus Drive Characteristics
Conditions: VCC = 4.5 to 5.5 V, VSS = 0 V, Ta = –20 to +75°C
Applicable Pins: SCL1, SCL0, SDA1, SDA0 (bus drive function selected)
Item
Schmitt trigger
input voltage
Symbol
–
VT
Min
Typ
Max
Unit
VCC × 0.3
—
—
V
Test Conditions
—
—
VCC × 0.7
VT – VT
VCC × 0.05
—
—
Input high voltage
VIH
VCC × 0.7
—
VCC + 0.5
V
Input low voltage
VIL
–0.5
—
VCC × 0.3
V
Output low voltage
VOL
—
—
0.8
V
—
—
0.5
IOL = 8 mA
—
—
0.4
IOL = 3 mA
—
—
20
pF
Vin = 0 V, f = 1 MHz,
Ta = 25°C
Three-state leakage | ITSI |
current (off state)
—
—
1.0
µA
Vin = 0.5 to VCC – 0.5 V
SCL, SDA output
fall time
20 + 0.1Cb —
250
ns
+
VT
+
Input capacitance
Cin
tOf
–
IOL = 16 mA
H8/3577 Group or
H8/3567 Group
chip
2 kΩ
Port
Darlington pair
Figure 22.1 Darlington Pair Drive Circuit (Example)
Rev. 3.00 Mar 17, 2006 page 539 of 706
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Section 22 Electrical Characteristics
22.3
AC Characteristics
Figure 22.2 shows the test conditions for the AC characteristics.
VCC
RL
Chip output
pin
C
RH
Figure 22.2 Output Load Circuit
Rev. 3.00 Mar 17, 2006 page 540 of 706
REJ09B0303-0300
C = 30 pF: All ports
RL = 2.4 kΩ
RH = 12 kΩ
I/O timing test levels
• Low level: 0.8 V
• High level: 2.0 V
(except P47 and P52)
Section 22 Electrical Characteristics
22.3.1
Clock Timing
Table 22.5 shows the clock timing. The clock timing specified here covers clock (φ) output and
clock pulse generator (crystal) and external clock input (EXTAL pin) oscillation settling times.
For details of external clock input (EXTAL pin) timing, see section 20, Clock Pulse Generator.
Table 22.5 Clock Timing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A
20 MHz
Item
Symbol
Min
Max
Unit
Test Conditions
Clock cycle time
tcyc
50
500
ns
Figure 22.3
Clock high pulse width
tCH
17
—
ns
Clock low pulse width
tCL
17
—
ns
Clock rise time
tCr
—
8
ns
Clock fall time
tCf
—
8
ns
Oscillation settling time at
reset (crystal)
tOSC1
10
—
ms
Oscillation settling time in
software standby (crystal)
tOSC2
8
—
ms
External clock output
stabilization delay time
tDEXT
500
—
µs
Figure 22.4
Figure 22.5
tcyc
tCH
tCf
φ
tCL
tCr
Figure 22.3 System Clock Timing
Rev. 3.00 Mar 17, 2006 page 541 of 706
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Section 22 Electrical Characteristics
EXTAL
tDEXT
tDEXT
VCC
STBY
tOSC1
tOSC1
RES
φ
Figure 22.4 Oscillation Settling Timing
φ
NMI
IRQi
(i = 0, 1, 2)
tOSC2
Figure 22.5 Oscillation Setting Timing (Exiting Software Standby Mode)
Rev. 3.00 Mar 17, 2006 page 542 of 706
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Section 22 Electrical Characteristics
22.3.2
Control Signal Timing
Table 22.6 shows the control signal timing.
Table 22.6 Control Signal Timing
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A
20 MHz
Item
Symbol
Min
Max
Unit
Test Conditions
RES setup time
tRESS
200
—
ns
Figure 22.6
RES pulse width
tRESW
20
—
tcyc
NMI setup time (NMI)
tNMIS
150
—
ns
NMI hold time (NMI)
tNMIH
10
—
NMI pulse width (exiting software
standby mode)
tNMIW
200
—
ns
IRQ setup time (IRQ2 to IRQ0)
tIRQS
150
—
ns
IRQ hold time (IRQ2 to IRQ0)
tIRQH
10
—
ns
IRQ pulse width (IRQ2 to IRQ0)
(exiting software standby mode)
tIRQW
200
—
ns
Figure 22.7
φ
tRESS
tRESS
RES
tRESW
Figure 22.6 Reset Input Timing
Rev. 3.00 Mar 17, 2006 page 543 of 706
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Section 22 Electrical Characteristics
φ
tNMIH
tNMIS
NMI
tNMIW
IRQi
(i = 2 to 0)
tIRQW
tIRQS
tIRQH
IRQ
Edge input
tIRQS
IRQ
Level input
Figure 22.7 Interrupt Input Timing
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Section 22 Electrical Characteristics
22.3.3
Timing of On-Chip Supporting Modules
Tables 22.7 and 22.8 show the on-chip supporting module timing.
Table 22.7 Timing of On-Chip Supporting Modules
Condition A: VCC = 5.0 V ±10%, VSS = 0 V, φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A
20 MHz
Item
Symbol
I/O ports Output data delay time
FRT
TMR
Min
Max
Unit
Test Conditions
ns
Figure 22.8 (1)
tPWDA, tPWDB —
50
Input data setup time
tPRSA, tPRSB
30
—
Input data hold time
tPRHA, tPRHB
30
—
Timer output delay time
tFTOD
—
50
Timer input setup time
tFTIS
30
—
Timer clock input setup time
tFTCS
30
—
Timer clock
pulse width
Single edge
tFTCWH
1.5
—
Both edges
tFTCWL
2.5
—
Timer output delay time
tTMOD
—
50
Timer reset input setup time
tTMRS
30
—
Figure 22.13
Timer clock input setup time
tTMCS
30
—
Figure 22.12
Single edge
tTMCWH
1.5
—
Both edges
tTMCWL
2.5
—
tPWOD
—
50
ns
Figure 22.14
Asynchronous tScyc
4
—
tcyc
Figure 22.15
Synchronous
6
—
Timer clock
pulse width
PWM,
PWMX
Pulse output delay time
SCI
Input clock
cycle
Figure 22.8 (2)
ns
Figure 22.9
Figure 22.10
tcyc
ns
Figure 22.11
tcyc
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
1.5
tcyc
Input clock fall time
tSCKf
—
1.5
Transmit data delay time
(synchronous)
tTXD
—
50
Receive data setup time
(synchronous)
tRXS
50
—
ns
Figure 22.16
Rev. 3.00 Mar 17, 2006 page 545 of 706
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Section 22 Electrical Characteristics
Condition A
20 MHz
Item
SCI
Receive data hold time
(synchronous)
A/D
Trigger input setup time
converter
Symbol
Min
Max
Unit
Test Conditions
tRXH
50
—
ns
Figure 22.16
tTRGS
30
—
ns
Figure 22.17
T1
T2
φ
tPRSA
tPRHA
Ports 1 to 7
(read)
tPWDA
Ports 1 to 6
(write)
Figure 22.8 (1) I/O Port Input/Output Timing
T1
T2
φ
tPRSB tPRHB
Ports C and D
(read)
tPWDB
Ports C and D
(write)
Figure 22.8 (2) I/O Port Input/Output Timing (USB On-Chip Version)
Rev. 3.00 Mar 17, 2006 page 546 of 706
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Section 22 Electrical Characteristics
φ
tFTOD
FTOA, FTOB
tFTIS
FTIA, FTIB,
FTIC, FTID
Figure 22.9 FRT Input/Output Timing
φ
tFTCS
FTCI
tFTCWL
tFTCWH
Figure 22.10 FRT Clock Input Timing
φ
tTMOD
TMO0, TMO1
TMOX
Figure 22.11 8-Bit Timer Output Timing
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Section 22 Electrical Characteristics
φ
tTMCS
tTMCS
TMCI0, TMCI1
TMIX, TMIY
tTMCWL
tTMCWH
Figure 22.12 8-Bit Timer Clock Input Timing
φ
tTMRS
TMRI0, TMRI1
TMIX, TMIY
Figure 22.13 8-Bit Timer Reset Input Timing
φ
tPWOD
PW7 to PW0*1
PW15 to PW0*2
PWX1, PWX0
Notes: 1. In the H8/3577
2. In the H8/3567
Figure 22.14 PWM, PWMX Output Timing
tSCKW
tSCKr
tSCKf
SCK0, SCK1
tScyc
Figure 22.15 SCK Clock Input Timing
Rev. 3.00 Mar 17, 2006 page 548 of 706
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Section 22 Electrical Characteristics
SCK0
tTXD
TxD0
(transmit data)
tRXS
tRXH
RxD0
(receive data)
Figure 22.16 SCI Input/Output Timing (Synchronous Mode)
φ
tTRGS
ADTRG
Figure 22.17 A/D Converter External Trigger Input Timing
Rev. 3.00 Mar 17, 2006 page 549 of 706
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Section 22 Electrical Characteristics
2
Table 22.8 I C Bus Timing
Conditions: VCC = 4.5 V to 5.5 V, VSS = 0 V, φ = 5 MHz to maximum operating frequency,
Ta = –20 to +75°C
Item
Symbol
Min
Typ
Max
Unit
SCL clock cycle
time
tSCL
12
—
—
tcyc
SCL clock high
pulse width
tSCLH
3
—
—
tcyc
SCL clock low
pulse width
tSCLL
5
—
—
tcyc
SCL, SDA input
rise time
tSr
—
—
7.5*
tcyc
SCL, SDA input
fall time
tSf
—
—
300
ns
SCL, SDA input
spike pulse
elimination time
tSP
—
—
1
tcyc
SDA input bus
free time
tBUF
5
—
—
tcyc
Start condition
input hold time
tSTAH
3
—
—
tcyc
Retransmission
start condition
input setup time
tSTAS
3
—
—
tcyc
Stop condition
input setup time
tSTOS
3
—
—
tcyc
Data input setup
time
tSDAS
0.5
—
—
tcyc
Data input hold
time
tSDAH
0
—
—
ns
SCL, SDA
capacitive load
Cb
—
—
400
pF
Note:
*
Test Conditions Notes
Figure 22.18
2
17.5tcyc can be set according to the clock selected for use by the I C module. For details,
see section 16.4, Usage Notes.
Rev. 3.00 Mar 17, 2006 page 550 of 706
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Section 22 Electrical Characteristics
VIH
SDA0,
SDA1
VIL
tBUF
tSTAH
SCL0,
SCL1
P*
tSCLH
tSTAS
S*
tSf
tSP tSTOS
Sr*
tSCLL
tSr
tSCL
P*
tSDAS
tSDAH
Note: * S, P, and Sr indicate the following conditions.
S: Start condition
P: Stop condition
Sr: Retransmission start condition
2
Figure 22.18 I C Bus Interface Input/Output Timing
Rev. 3.00 Mar 17, 2006 page 551 of 706
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Section 22 Electrical Characteristics
22.4
A/D Conversion Characteristics
Table 22.9 lists the A/D conversion characteristics.
Table 22.9 A/D Conversion Characteristics
1
(AN7 to AN0 Input* : 134/266-State Conversion)
Condition A: VCC = 5.0 V ±10%, AVCC = 4.5 V to 5.5 V
2
VSS = AVSS = 0 V* , φ = 2 MHz to maximum operating frequency,
Ta = –20 to +75°C
Condition A
20 MHz
Item
Resolution
Conversion time (single mode)*
5
Analog input capacitance
Permissible signal-source impedance
Min
Typ
Max
Unit
10
10
10
Bits
—
—
6.7
µs
—
—
20
pF
—
3
10*
kΩ
—
4
5*
Nonlinearity error
—
—
±3.0
LSB
Offset error
—
—
±3.5
LSB
Full-scale error
—
—
±3.5
LSB
Quantization error
—
—
±0.5
LSB
±4.0
LSB
Absolute accuracy
Notes: 1. In the H8/3577
(AN3 to AN0 in the H8/3567)
2. The voltage applied to the ANn analog input pins during A/D conversion must be in the
range AVSS ≤ ANn ≤ AVCC (where n = 0 to 3). For the relationship between AVCC/AVSS
and VCC/VSS, set AVSS = VSS. The AVCC and AVSS pins must not be left open when the A/D
converter is not used.
3. When conversion time ≥ 11. 17 µs (CKS = 1 and φ ≤ 12 MHz, or CKS = 0)
4. When conversion time < 11. 17 µs (CKS = 1 and φ > 12 Mhz)
5. Value when using the maximum operating frequency.
Rev. 3.00 Mar 17, 2006 page 552 of 706
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Section 22 Electrical Characteristics
22.5
USB Function Pin Characteristics
Table 22.10 shows the USB function pin characteristics.
Table 22.10 DC Characteristics
Conditions:
VCC = 5.0 V ±10%, DrVCC = 3.3 V ± 0.3 V, DrVSS = VSS = 0 V, Ta = –20°C to
+75°C
Pin Functions: Transceiver input/output (USD+, USD−, DS2D+, DS2D−, DS3D+, DS3D−,
DS4D+, DS4D−, DS5D+, DS5D−), ports C and D, ENP2 to ENP5, OCP2 to OCP5,
EXTAL12, XTAL12
Item
Symbol
Min
Typ
Max
Unit
Test Conditions
Differential input
sensitivity
VDI
0.2
—
—
V
| (D+) − (D−) |
Differential common
mode range
VCM
0.8
—
2.5
V
Including VDI
Schmitt
OCP2 to
trigger input OCP5
voltages
VT
1.0
—
—
V
—
—
VCC × 0.7
V
VT – VT
0.4
—
—
V
VIH
VCC × 0.7
—
VCC + 0.3
V
Port D
2.0
—
DrVCC + 0.3 V
Other than
the above
2.0
—
VCC + 0.3
V
–0.3
—
VCC × 0.2
V
–0.3
—
0.8
V
2.8
—
3.6
V
RL = 15 kΩ
connected between
pin and GND
DrVCC – 0.5 —
—
V
IOH = –200 µA
DrVCC – 1.0 —
—
V
IOH = –1 mA
VCC – 0.5
—
—
V
IOH = –200 µA
3.5
—
—
V
IOH = –1 mA
–
+
VT
+
1
Input high* EXTAL12
voltage
1
Input low*
voltage
EXTAL12
VIL
Other than
the above
Output high Transceiver VOH
voltage
Port D
Other than
the above
–
Rev. 3.00 Mar 17, 2006 page 553 of 706
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Section 22 Electrical Characteristics
Item
Output low
voltage
Symbol
Min
Typ
Max
Unit
Test Conditions
Transceiver VOL
—
—
0.3
V
RL = 1.5 kΩ
connected between
pin and power
supply
Other than
the above
—
—
0.4
V
IOL = 1.6 mA
Output resistance
ZDRV
28
—
44
Ω
Input pin capacitance
CIN
—
—
35
pF
Between pin and
GND
Three-state leakage
current
ILO
—
—
1.0
µA
0.5 V < Vin < DrVCC
– 0.5 V
0.5 V < Vin < VCC –
2
0.5 V*
DrVCC
current
dissipation
Normal
operation
Standby
mode
DICC
—
5
10
mA
—
0.2
5.0
µA
Notes: 1. Excluding transceiver input/output (USD+, USD−, DS2D+, DS2D−, DS3D+, DS3D−,
DS4D+, DS4D−, DS5D+, DS5D−)
2. Upper row applies to transceiver input/output and port D, and lower row to other pins.
Rev. 3.00 Mar 17, 2006 page 554 of 706
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Section 22 Electrical Characteristics
Table 22.11 AC Characteristics
Conditions:
VCC = 5.0 V ±10%, DrVCC = 3.3 V ± 0.3 V, DrVSS = VSS = 0 V, Ta = –20°C to
+75°C
Pin Functions: Transceiver input/output (USD+, USD−, DS2D+, DS2D−, DS3D+, DS3D−,
DS4D+, DS4D−, DS5D+, DS5D−), ports C and D, ENP2 to ENP5, OCP2 to OCP5,
EXTAL12, XTAL12
Item
Symbol
Min
Max
Unit
Figure
Rise time
tFR
4
20
ns
Figure
22.19
Fall time
tFF
4
20
Differential signal
time difference
tFRFM
90.0
111.11
%
Rise time
tLR
75
300
ns
Fall time
tLF
75
300
Differential signal
time difference
tLRFM
80.0
125
%
Transceiver output signal crossing
voltage
VCRS
1.3
2.0
V
Ports C and
D
Output data delay
time
tPWDB
—
50
ns
Input data setup
time
tPRSB
30
—
Input data hold
time
tPRHB
30
—
tOSCU
10
—
tFR
tLR
tFF
tLF
Transceiver
full speed
Transceiver
low speed
USB clock oscillation settling time
(crystal)
Notes
tFR/tFF
Figure
22.19
tLR/tLF
Figure
22.8 (2)
ms
VOH
VOL
Figure 22.19 Transceiver Output Timing
Rev. 3.00 Mar 17, 2006 page 555 of 706
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Section 22 Electrical Characteristics
22.6
Usage Notes
ZTAT Version and Mask ROM Version: The ZTAT and mask ROM versions satisfy the
electrical characteristics shown in this manual, but actual electrical characteristic values, operating
margins, noise margins, and other properties may vary due to differences in manufacturing
process, on-chip ROM, layout patterns, and so on.
When system evaluation testing is carried out using the ZTAT version, the same evaluation testing
should also be conducted for the mask ROM version when changing over to that version.
Models with Internal Step-Down Circuit: H8/3577, H8/3567, and H8/3567U mask ROM
models (HD6433577, HD6433574, HD6433567, HD6433564-20, HD6433564-10, HD6433567U,
and HD6433564U) incorporate an internal step-down circuit to lower the MCU’s internal power
supply voltage to the optimum level automatically.
One or two (in-parallel) 0.47 µF internal voltage stabilization capacitors must be connected
between the internal step-down pin (VCL) and the VSS pin.
The method of connecting the external capacitor(s) is shown in figure 22.20. Do not apply a
voltage exceeding 3.6 V to the VCL pin.
When switching from a ZTAT version with no internal step-down capability to a mask ROM
version with the step-down facility, the differences in the circuitry before and after the changeover
must be taken into consideration when designing the board pattern.
Rev. 3.00 Mar 17, 2006 page 556 of 706
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Section 22 Electrical Characteristics
External capacitor(s)
for power supply
stabilization
Vcc power supply
VCL
One or two
(in-parallel)
0.47 µF
capacitors
VSS
Model with
internal
step-down
capability
(mask ROM
version)
VCC
10 µF
bypass
capacitor
0.01 µF
VSS
Model without
internal
step-down
capability
(ZTAT version)
Do not connect the VCC power supply to the VCL pin
of a model with internal step-down capability.
(Connect the VCC power supply to other VCC pins as
usual.)
A power supply stabilization capacitor must be
connected to the VCL pin. Use one or two (in-parallel)
0.47 µF laminated ceramic capacitors, placed close to
the pin.
Models with no internal step-down capability have a
VCC pin (VCC power supply pin) in the pin position
occupied by the VCL pin in internal step-down
models.
It is recommended that a bypass capacitor be
connected to the power supply pins. (Values are for
reference.)
Models with internal step-down capability:
HD6433577, HD6433574, HD6433567,
HD6433564-20, HD6433564-10,
HD6433567U, HD6433564U
Models without internal step-down capability:
HD6473577, HD6473567, HD6473567U
Figure 22.20 Method of Connecting VCL Capacitor(s) to Mask ROM Model
with Internal Step-Down Capability, and Differences between Models with
and without Internal Step-Down Capability
Rev. 3.00 Mar 17, 2006 page 557 of 706
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Section 22 Electrical Characteristics
Rev. 3.00 Mar 17, 2006 page 558 of 706
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Appendix A CPU Instruction Set
Appendix A CPU Instruction Set
A.1
Instruction Set List
Operation Notation
Rd8/16
General register (destination) (8 or 16 bits)
Rs8/16
General register (source) (8 or 16 bits)
Rn8/16
General register (8 or 16 bits)
CCR
Condition code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#xx:3/8/16
Immediate data (3, 8, or 16 bits)
d:8/16
Displacement (8 or 16 bits)
@aa:8/16
Absolute address (8 or 16 bits)
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Exclusive logical OR
→
—
Move
NOT (logical complement)
Condition Code Notation
Modified according to the instruction result
*
Undetermined (unpredictable)
0
Always cleared to 0
—
Not affected by the instruction result
Rev. 3.00 Mar 17, 2006 page 559 of 706
REJ09B0303-0300
Appendix A CPU Instruction Set
Instruction Set
B @(d:16, Rs16) → Rd8
MOV.B @Rs+, Rd
B @Rs16 → Rd8
Rs16+1 → Rs16
MOV.B @aa:8, Rd
B @aa:8 → Rd8
MOV.B @aa:16, Rd
B @aa:16 → Rd8
MOV.B Rs, @Rd
B Rs8 → @Rd16
MOV.B Rs, @(d:16, Rd)
B Rs8 → @(d:16, Rd16)
MOV.B Rs, @–Rd
B Rd16–1 → Rd16
Rs8 → @Rd16
MOV.B Rs, @aa:8
B Rs8 → @aa:8
Implied
@aa: 8/16
@(d:8, PC)
@@aa
@–Rn/@Rn+
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
MOV.B @(d:16, Rs), Rd
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
B @Rs16 → Rd8
0 — 4
↔ ↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔ ↔
B Rs8 → Rd8
MOV.B @Rs, Rd
0 — 2
0 — 4
0 — 6
MOV.W Rs, @–Rd
W Rd16–2 → Rd16
Rs16 → @Rd16
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
MOV.B Rs, Rd
I H N Z V C
MOV.W Rs, @aa:16
W Rs16 → @aa:16
0 — 6
POP Rd
W @SP → Rd16
SP+2 → SP
2
— —
↔ ↔
↔ ↔
B #xx:8 → Rd8
Condition Code
PUSH Rs
W SP–2 → SP
Rs16 → @SP
2
— —
↔
↔
MOV.B #xx:8, Rd
Rn
@Rn
@(d:16, Rn)
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length
No. of States*
Table A.1
0 — 6
MOV.B Rs, @aa:16
B Rs8 → @aa:16
MOV.W #xx:16, Rd
W #xx:16 → Rd16
MOV.W Rs, Rd
W Rs16 → Rd16
MOV.W @Rs, Rd
W @Rs16 → Rd16
2
— —
2
— —
2
4
W @Rs16 → Rd16
Rs16+2 → Rs16
MOV.W @aa:16, Rd
W @aa:16 → Rd16
MOV.W Rs, @Rd
W Rs16 → @Rd16
MOV.W Rs, @(d:16, Rd) W Rs16 → @(d:16, Rd16)
Rev. 3.00 Mar 17, 2006 page 560 of 706
REJ09B0303-0300
— —
2
— —
2
— —
4
— —
2
— —
4
— —
2
— —
2
— —
4
— —
4
— —
2
— —
2
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) → Rd16
MOV.W @Rs+, Rd
— —
— —
4
— —
2
— —
4
2
— —
— —
4
— —
2
— —
4
— —
0 — 2
0 — 4
0 — 6
0 — 6
0 — 6
0 — 4
0 — 6
0 — 6
0 — 6
0 — 4
0 — 2
0 — 4
0 — 6
0 — 6
0 — 4
0 — 6
0 — 6
0 — 6
Appendix A CPU Instruction Set
MOVTPE Rs, @aa:16
B Not supported
ADD.B #xx:8, Rd
B Rd8+#xx:8 → Rd8
2
—
H N Z V C
No. of States*
@(d:8, PC)
@@aa
Implied
@aa: 8/16
I
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔
B Not supported
Condition Code
↔ ↔
↔ ↔
↔ ↔ ↔ ↔ ↔
↔ ↔ ↔
MOVFPE @aa:16, Rd
@Rn
@(d:16, Rn)
@–Rn/@Rn+
Operation
#xx: 8/16
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length
2
B Rd8+Rs8 → Rd8
2
—
ADD.W Rs, Rd
W Rd16+Rs16 → Rd16
2
— (1)
ADDX.B #xx:8, Rd
B Rd8+#xx:8 +C → Rd8
ADDX.B Rs, Rd
B Rd8+Rs8 +C → Rd8
2
—
ADDS.W #1, Rd
W Rd16+1 → Rd16
2
— — — — — — 2
ADDS.W #2, Rd
W Rd16+2 → Rd16
2
— — — — — — 2
INC.B Rd
B Rd8+1 → Rd8
2
— —
DAA.B Rd
B Rd8 decimal adjust → Rd8
2
— *
SUB.B Rs, Rd
B Rd8–Rs8 → Rd8
2
—
SUB.W Rs, Rd
W Rd16–Rs16 → Rd16
2
— (1)
SUBX.B #xx:8, Rd
B Rd8–#xx:8 –C → Rd8
SUBX.B Rs, Rd
B Rd8–Rs8 –C → Rd8
2
—
SUBS.W #1, Rd
W Rd16–1 → Rd16
2
— — — — — — 2
SUBS.W #2, Rd
W Rd16–2 → Rd16
2
— — — — — — 2
DEC.B Rd
B Rd8–1 → Rd8
2
— —
DAS.B Rd
B Rd8 decimal adjust → Rd8
2
— *
NEG.B Rd
B 0–Rd8 → Rd8
2
—
CMP.B #xx:8, Rd
B Rd8–#xx:8
2
—
(2)
2
2
2
— 2
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
(2)
2
* (3) 2
↔
—
(2)
2
2
2
2
— 2
* — 2
↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
2
(2)
↔ ↔
↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔
—
↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
2
↔
ADD.B Rs, Rd
2
2
B Rd8–Rs8
2
—
CMP.W Rs, Rd
W Rd16–Rs16
2
— (1)
MULXU.B Rs, Rd
B Rd8 × Rs8 → Rd16
2
— — — — — — 14
DIVXU.B Rs, Rd
B Rd16÷Rs8 → Rd16
(RdH: remainder,
RdL: quotient)
2
— — (6) (7) — — 14
AND.B #xx:8, Rd
B Rd8∧#xx:8 → Rd8
AND.B Rs, Rd
B Rd8∧Rs8 → Rd8
— —
2
2
— —
↔ ↔
↔ ↔
CMP.B Rs, Rd
2
2
0 — 2
0 — 2
Rev. 3.00 Mar 17, 2006 page 561 of 706
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Appendix A CPU Instruction Set
H N Z V C
2
— —
2
— — 0
2
— —
2
— —
2
— —
2
— —
SHLL.B Rd
B
C
B
C
0
B
C
C
B
C
2
0
2
0
2
0
2
0
2
b0
C
b7
ROTR.B Rd
0
b0
B
b7
ROTL.B Rd
2
b0
b7
ROTXR.B Rd
0
b0
0
b7
ROTXL.B Rd
2
b0
b7
SHLR.B Rd
0
b0
B
b7
↔
↔
— —
SHAR.B Rd
↔
2
b7
2
↔
— —
0
↔
2
C
↔
B
0 — 2
↔
SHAL.B Rd
0 — 2
↔
— —
0 — 2
↔
— —
2
0 — 2
↔
↔
2
B Rd8 → Rd8
— —
↔
↔
B Rd8⊕Rs8 → Rd8
NOT.B Rd
— —
↔
XOR.B Rs, Rd
2
2
↔
↔
B Rd8⊕#xx:8 → Rd8
0 — 2
↔
↔
B Rd8∨Rs8 → Rd8
XOR.B #xx:8, Rd
— —
↔
↔
OR.B Rs, Rd
2
↔
↔
B Rd8∨#xx:8 → Rd8
↔ ↔ ↔ ↔ ↔ ↔
↔ ↔ ↔ ↔ ↔ ↔
I
OR.B #xx:8, Rd
No. of States*
Condition Code
Implied
@aa: 8/16
@(d:8, PC)
@@aa
@–Rn/@Rn+
Rn
@Rn
@(d:16, Rn)
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length
b0
B
C
b7
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REJ09B0303-0300
b0
Appendix A CPU Instruction Set
B (#xx:3 of Rd8) ← 1
BSET #xx:3, @Rd
B (#xx:3 of @Rd16) ← 1
BSET #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 1
BSET Rn, Rd
B (Rn8 of Rd8) ← 1
BSET Rn, @Rd
B (Rn8 of @Rd16) ← 1
BSET Rn, @aa:8
B (Rn8 of @aa:8) ← 1
BCLR #xx:3, Rd
B (#xx:3 of Rd8) ← 0
BCLR #xx:3, @Rd
B (#xx:3 of @Rd16) ← 0
BCLR #xx:3, @aa:8
B (#xx:3 of @aa:8) ← 0
BCLR Rn, Rd
B (Rn8 of Rd8) ← 0
BCLR Rn, @Rd
B (Rn8 of @Rd16) ← 0
BCLR Rn, @aa:8
B (Rn8 of @aa:8) ← 0
BNOT #xx:3, Rd
B (#xx:3 of Rd8) ←
(#xx:3 of Rd8)
BNOT #xx:3, @Rd
B (#xx:3 of @Rd16) ←
(#xx:3 of @Rd16)
BNOT #xx:3, @aa:8
B (#xx:3 of @aa:8) ←
(#xx:3 of @aa:8)
BNOT Rn, Rd
B (Rn8 of Rd8) ←
(Rn8 of Rd8)
BNOT Rn, @Rd
B (Rn8 of @Rd16) ←
(Rn8 of @Rd16)
BNOT Rn, @aa:8
B (Rn8 of @aa:8) ←
(Rn8 of @aa:8)
BTST #xx:3, Rd
B (#xx:3 of Rd8) → Z
BTST #xx:3, @Rd
B (#xx:3 of @Rd16) → Z
BTST #xx:3, @aa:8
B (#xx:3 of @aa:8) → Z
BTST Rn, Rd
B (Rn8 of Rd8) → Z
BTST Rn, @Rd
B (Rn8 of @Rd16) → Z
BTST Rn, @aa:8
B (Rn8 of @aa:8) → Z
I
H N Z V C
No. of States*
@(d:8, PC)
@@aa
Implied
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
2
Condition Code
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — —
4
— — —
4
2
— — —
— — —
4
— — —
4
— — —
↔ ↔ ↔ ↔ ↔ ↔
BSET #xx:3, Rd
@Rn
Operation
#xx: 8/16
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length
— — 2
— — 6
— — 6
— — 2
— — 6
— — 6
Rev. 3.00 Mar 17, 2006 page 563 of 706
REJ09B0303-0300
Appendix A CPU Instruction Set
BLD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BLD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BILD #xx:3, Rd
B (#xx:3 of Rd8) → C
BILD #xx:3, @Rd
B (#xx:3 of @Rd16) → C
BILD #xx:3, @aa:8
B (#xx:3 of @aa:8) → C
BST #xx:3, Rd
B C → (#xx:3 of Rd8)
BST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BIST #xx:3, Rd
B C → (#xx:3 of Rd8)
BIST #xx:3, @Rd
B C → (#xx:3 of @Rd16)
BIST #xx:3, @aa:8
B C → (#xx:3 of @aa:8)
BAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BIAND #xx:3, Rd
B C∧(#xx:3 of Rd8) → C
BIAND #xx:3, @Rd
B C∧(#xx:3 of @Rd16) → C
BIAND #xx:3, @aa:8
B C∧(#xx:3 of @aa:8) → C
BOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BIOR #xx:3, Rd
B C∨(#xx:3 of Rd8) → C
BIOR #xx:3, @Rd
B C∨(#xx:3 of @Rd16) → C
BIOR #xx:3, @aa:8
B C∨(#xx:3 of @aa:8) → C
BXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
BXOR #xx:3, @Rd
B C⊕(#xx:3 of @Rd16) → C
BXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BIXOR #xx:3, Rd
B C⊕(#xx:3 of Rd8) → C
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H N Z V C
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
— — — — —
No. of States*
I
— — — — —
4
2
6
6
2
6
6
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — — — 2
4
— — — — — — 8
4
2
— — — — — — 8
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
— — — — —
— — — — —
4
— — — — —
4
2
Implied
@aa: 8/16
@(d:8, PC)
@@aa
@Rn
@(d:16, Rn)
@–Rn/@Rn+
2
↔ ↔ ↔ ↔ ↔ ↔
B (#xx:3 of Rd8) → C
Condition Code
— — — — —
— — — — —
↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔
BLD #xx:3, Rd
Rn
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length
2
6
6
2
6
6
2
6
6
2
6
6
2
6
6
2
Appendix A CPU Instruction Set
B C⊕(#xx:3 of @Rd16) → C
4
I H N Z V C
— — — — —
No. of States*
@(d:8, PC)
@@aa
Implied
@(d:16, Rn)
@–Rn/@Rn+
@aa: 8/16
@Rn
Branching
Condition
Condition Code
↔ ↔
BIXOR #xx:3, @Rd
Operation
#xx: 8/16
Rn
Mnemonic
Operand Size
Addressing Mode/
Instruction Length
6
BIXOR #xx:3, @aa:8
B C⊕(#xx:3 of @aa:8) → C
BRA d:8 (BT d:8)
— PC ← PC+d:8
2
— — — — — — 4
BRN d:8 (BF d:8)
— PC ← PC+2
2
— — — — — — 4
BHI d:8
C∨Z=0
2
— — — — — — 4
C∨Z=1
2
— — — — — — 4
C=0
2
— — — — — — 4
C=1
2
— — — — — — 4
Z=0
2
— — — — — — 4
BEQ d:8
— If
condition
—
is true
— then
— PC ←
PC+d:8
— else next;
—
Z=1
2
— — — — — — 4
BVC d:8
—
V=0
2
— — — — — — 4
BVS d:8
—
V=1
2
— — — — — — 4
BPL d:8
—
N=0
2
— — — — — — 4
BMI d:8
—
N=1
2
— — — — — — 4
BGE d:8
—
N⊕V = 0
2
— — — — — — 4
BLT d:8
—
N⊕V = 1
2
— — — — — — 4
BGT d:8
—
Z ∨ (N⊕V) = 0
2
— — — — — — 4
BLE d:8
—
Z ∨ (N⊕V) = 1
2
— — — — — — 4
JMP @Rn
— PC ← Rn16
JMP @aa:16
— PC ← aa:16
JMP @@aa:8
— PC ← @aa:8
BSR d:8
— SP–2 → SP
PC → @SP
PC ← PC+d:8
JSR @Rn
— SP–2 → SP
PC → @SP
PC ← Rn16
JSR @aa:16
— SP–2 → SP
PC → @SP
PC ← aa:16
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
4
— — — — —
2
6
— — — — — — 4
4
— — — — — — 6
2
2
2
— — — — — — 8
— — — — — — 6
— — — — — — 6
4
— — — — — — 8
Rev. 3.00 Mar 17, 2006 page 565 of 706
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Appendix A CPU Instruction Set
I
H N Z V C
No. of States*
Condition Code
Implied
@aa: 8/16
@(d:8, PC)
@@aa
@–Rn/@Rn+
Rn
@Rn
@(d:16, Rn)
Operation
#xx: 8/16
Mnemonic
Operand Size
Addressing Mode/
Instruction Length
JSR @@aa:8
— SP–2 → SP
PC → @SP
PC ← @aa:8
RTS
— PC ← @SP
SP+2 → SP
2 — — — — — — 8
RTE
— CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2
SLEEP
— Transit to sleep mode.
2 — — — — — — 2
LDC #xx:8, CCR
B #xx:8 → CCR
LDC Rs, CCR
B Rs8 → CCR
STC CCR, Rd
B CCR → Rd8
ANDC #xx:8, CCR
B CCR∧#xx:8 → CCR
2
ORC #xx:8, CCR
B CCR∨#xx:8 → CCR
2
XORC #xx:8, CCR
B CCR⊕#xx:8 → CCR
2
NOP
— PC ← PC+2
EEPMOV
— EEPMOV
Notes: *
(1)
(2)
(3)
(5)
(6)
(7)
↔
↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔
↔ ↔
↔
↔
↔
↔ ↔ ↔
↔ ↔ ↔
↔ ↔ ↔
— — — — — — 2
↔ ↔ ↔
2
2
2
2
2
2
2 — — — — — — 2
These cannot be used in this LSI.
The number of states is the number of states required for execution when the
instruction and its operands are located in on-chip memory. For other cases, see
section A.3, Number of Instruction Execution States.
Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
Set to 1 if decimal adjustment produces a carry; otherwise cleared to 0.
These instructions are not supported by the H8/3577 Group and H8/3567 Group.
Set to 1 if the divisor is negative; otherwise cleared to 0.
Set to 1 if the divisor is 0; otherwise cleared to 0.
Rev. 3.00 Mar 17, 2006 page 566 of 706
REJ09B0303-0300
10
2
2
↔ ↔
↔ ↔
↔ ↔
↔
— — — — — — 8
↔ ↔
2
(5)
Appendix A CPU Instruction Set
A.2
Operation Code Map
Table A.2 is a map of the operation codes contained in the first byte of the instruction code (bits
15 to 8 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
Rev. 3.00 Mar 17, 2006 page 567 of 706
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REJ09B0303-0300
OR
XOR
AND
MOV
C
D
E
F
SUB
ADD
MOV
BVS
9
JMP
BPL
DEC
INC
A
EEPMOV
C
CMP
MOV
BLT
D
JSR
BGT
SUBX
ADDX
E
Bit manipulation instructions
BGE
MOV*1
BMI
SUBS
ADDS
B
Notes: 1. The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word).
The PUSH and POP instructions are identical in machine language to MOV instructions.
2. The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively.
SUBX
BILD
8
BVC
B
BIAND
BAND
BIST
BLD
BST
BEQ
MOV
NEG
NOT
CMP
BIXOR
BXOR
RTE
BNE
AND
A
BIOR
BOR
BSR
BCS*2
XOR
LDC
ANDC
XORC
ADDX
BTS
RTS
BCC*2
OR
7
6
5
9
BCLR
BLS
ROTR
ROTXR
ORC
4
ADD
BNOT
BHI
ROTL
LDC
3
8
7
BSET
DIVXU
MULXU
5
6
BRN*2
SHAR
ROTXL
STC
SLEEP
SHLR
2
1
BRA*2
SHAL
SHLL
NOP
0
4
3
2
Low
BLE
DAS
DAA
F
Table A.2
1
0
High
Appendix A CPU Instruction Set
Operation Code Map
Appendix A CPU Instruction Set
A.3
Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction execution.
Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation). Table A.4 indicates
the number of cycles of each type occurring in each instruction. The total number of states
required for execution of an instruction can be calculated from these two tables as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: Mode 1, stack located in external memory, 1 wait state inserted in external memory
access.
1. BSET #0, @FFC7
From table A.4: I = L = 2, J = K = M = N= 0
From table A.3: SI = 8, SL = 3
Number of states required for execution: 2 × 8 + 2 × 3 =22
2. JSR @@30
From table A.4: I = 2, J = K = 1, L = M = N = 0
From table A.3: SI = SJ = SK = 8
Number of states required for execution: 2 × 8 + 1 × 8 + 1 × 8 = 32
Table A.3
Number of States Taken by Each Cycle in Instruction Execution
Access Location
Execution Status
(Instruction Cycle)
Instruction fetch
SI
Branch address read
SJ
On-Chip Memory
On-Chip Reg. Field
External Memory
2
6
6 + 2m
Stack operation
SK
Byte data access
SL
3
3+m
Word data access
SM
6
6 + 2m
Internal operation
SN
1
1
1
Note: m: Number of wait states inserted in access to external device.
Rev. 3.00 Mar 17, 2006 page 569 of 706
REJ09B0303-0300
Appendix A CPU Instruction Set
Table A.4
Number of Cycles in Each Instruction
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
ADD
ADD.B #xx:8, Rd
1
ADD.B Rs, Rd
1
ADD.W Rs, Rd
1
ADDS
ADDS.W #1/2, Rd
1
ADDX
ADDX.B #xx:8, Rd
1
AND
ADDX.B Rs, Rd
1
AND.B #xx:8, Rd
1
AND.B Rs, Rd
1
ANDC
ANDC #xx:8, CCR
1
BAND
BAND #xx:3, Rd
1
BAND #xx:3, @Rd
2
1
BAND #xx:3, @aa:8
2
1
BRA d:8 (BT d:8)
2
Bcc
BCLR
BRN d:8 (BF d:8)
2
BHI d:8
2
BLS d:8
2
BCC d:8 (BHS d:8)
2
BCS d:8 (BLO d:8)
2
BNE d:8
2
BEQ d:8
2
BVC d:8
2
BVS d:8
2
BPL d:8
2
BMI d:8
2
BGE d:8
2
BLT d:8
2
BGT d:8
2
BLE d:8
2
BCLR #xx:3, Rd
1
BCLR #xx:3, @Rd
2
2
BCLR #xx:3, @aa:8
2
2
BCLR Rn, Rd
1
BCLR Rn, @Rd
2
2
BCLR Rn, @aa:8
2
2
Rev. 3.00 Mar 17, 2006 page 570 of 706
REJ09B0303-0300
Appendix A CPU Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
BIAND
BIAND #xx:3, Rd
1
BIAND #xx:3, @Rd
2
1
BIAND #xx:3, @aa:8 2
1
BILD
BIOR
BIST
BIXOR
BLD
BNOT
BOR
BSET
BILD #xx:3, Rd
1
BILD #xx:3, @Rd
2
1
BILD #xx:3, @aa:8
2
1
BIOR #xx:3, Rd
1
BIOR #xx:3, @Rd
2
1
BIOR #xx:3, @aa:8
2
1
BIST #xx:3, Rd
1
BIST #xx:3, @Rd
2
2
BIST #xx:3, @aa:8
2
2
BIXOR #xx:3, Rd
1
BIXOR #xx:3, @Rd
2
1
BIXOR #xx:3, @aa:8 2
1
BLD #xx:3, Rd
1
BLD #xx:3, @Rd
2
1
BLD #xx:3, @aa:8
2
1
BNOT #xx:3, Rd
1
BNOT #xx:3, @Rd
2
2
BNOT #xx:3, @aa:8
2
2
BNOT Rn, Rd
1
BNOT Rn, @Rd
2
2
BNOT Rn, @aa:8
2
2
BOR #xx:3, Rd
1
BOR #xx:3, @Rd
2
1
BOR #xx:3, @aa:8
2
1
BSET #xx:3, Rd
1
BSET #xx:3, @Rd
2
2
BSET #xx:3, @aa:8
2
2
BSET Rn, Rd
1
BSET Rn, @Rd
2
2
BSET Rn, @aa:8
2
2
Rev. 3.00 Mar 17, 2006 page 571 of 706
REJ09B0303-0300
Appendix A CPU Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
BSR
2
BST
BTST
BXOR
CMP
BSR d:8
1
BST #xx:3, Rd
1
BST #xx:3, @Rd
2
2
BST #xx:3, @aa:8
2
2
BTST #xx:3, Rd
1
BTST #xx:3, @Rd
2
1
BTST #xx:3, @aa:8
2
1
BTST Rn, Rd
1
BTST Rn, @Rd
2
1
BTST Rn, @aa:8
2
1
BXOR #xx:3, Rd
1
BXOR #xx:3, @Rd
2
1
BXOR #xx:3, @aa:8 2
1
CMP.B #xx:8, Rd
1
CMP.B Rs, Rd
1
CMP.W Rs, Rd
1
DAA
DAA.B Rd
1
DAS
DAS.B Rd
1
DEC
DEC.B Rd
1
DIVXU
DIVXU.B Rs, Rd
1
EEPMOV
EEPMOV
This cannot be used in these H8/3577 Group and H8/3567 Group.
INC
INC.B Rd
1
JMP
JMP @Rn
2
JMP @aa:16
2
JMP @@aa:8
2
JSR @Rn
2
JSR @aa:16
2
JSR @@aa:8
2
JSR
LDC
LDC #xx:8, CCR
1
LDC Rs, CCR
1
Rev. 3.00 Mar 17, 2006 page 572 of 706
REJ09B0303-0300
12
2
1
2
1
1
1
1
2
Appendix A CPU Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
MOV
MOV.B #xx:8, Rd
1
MOV.B Rs, Rd
1
MOV.B @Rs, Rd
1
1
MOV.B @(d:16,Rs),
Rd
2
1
MOV.B @Rs+, Rd
1
1
MOV.B @aa:8, Rd
1
1
MOV.B @aa:16, Rd
2
1
MOV.B Rs, @Rd
1
1
MOV.B Rs, @(d:16,
Rd)
2
1
2
MOV.B Rs, @–Rd
1
1
MOV.B Rs, @aa:8
1
1
MOV.B Rs, @aa:16
2
1
MOV.W #xx:16, Rd
2
MOV.W Rs, Rd
1
MOV.W @Rs, Rd
1
1
MOV.W @(d:16, Rs), 2
Rd
1
MOV.W @Rs+, Rd
2
1
1
MOV.W @aa:16, Rd 2
1
MOV.W Rs, @Rd
1
1
MOV.W Rs, @(d:16, 2
Rd)
1
MOV.W Rs, @–Rd
1
1
1
MOV.W Rs, @aa:16 2
MOVFPE
MOVFPE @aa:16,
Rd
Not supported
MOVTPE
MOVTPE.Rs,
@aa:16
Not supported
MULXU
MULXU.B Rs, Rd
1
NEG
NEG.B Rd
1
NOP
NOP
1
NOT
NOT.B Rd
1
2
2
12
Rev. 3.00 Mar 17, 2006 page 573 of 706
REJ09B0303-0300
Appendix A CPU Instruction Set
Instruction Mnemonic
Instruction Branch
Stack
Byte Data Word Data Internal
Fetch
Addr. Read Operation Access
Access
Operation
I
J
K
L
M
N
OR
OR.B #xx:8, Rd
1
OR.B Rs, Rd
1
ORC
ORC #xx:8, CCR
1
POP
POP Rd
1
1
2
PUSH
PUSH Rd
1
1
2
ROTL
ROTL.B Rd
1
ROTR
ROTR.B Rd
1
ROTXL
ROTXL.B Rd
1
ROTXR
ROTXR.B Rd
1
RTE
RTE
2
2
2
RTS
RTS
2
1
2
SHAL
SHAL.B Rd
1
SHAR
SHAR.B Rd
1
SHLL
SHLL.B Rd
1
SHLR
SHLR.B Rd
1
SLEEP
SLEEP
1
STC
STC CCR, Rd
1
SUB
SUB.B Rs, Rd
1
SUB.W Rs, Rd
1
SUBS
SUBS.W #1/2, Rd
1
SUBX
SUBX.B #xx:8, Rd
1
SUBX.B Rs, Rd
1
XOR
XORC
XOR.B #xx:8, Rd
1
XOR.B Rs, Rd
1
XORC #xx:8, CCR
1
Note: All values left blank are zero.
Rev. 3.00 Mar 17, 2006 page 574 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
Appendix B Internal I/O Registers
B.1
Addresses
Register
Address Name
Bit 7
Bit 6
Bit 5
H'FDC0 UPRTCR
—
—
DSPSEL2 DSPSEL1 DSPSEL0 PCNMD2 PCNMD1 PCNMD0 USB
D7
D6
D5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
Bus
Width
8
H'FDC1 UTESTR0
H'FDC2 UTESTR1
H'FDE1 EPDR2
D4
D3
D2
D1
D0
H'FDE2 FVSR2H
—
—
—
—
—
—
N9
N8
H'FDE3 FVSR2L
N7
N6
N5
N4
N3
N2
N1
N0
H'FDE4 EPSZR1
EP1SZ3
EP1SZ2
EP1SZ1
EP1SZ0
EP2SZ3
EP2SZ2
EP2SZ1
EP2SZ0
H'FDE5 EPDR1
D7
D6
D5
D4
D3
D2
D1
D0
H'FDE6 FVSR1H
—
—
—
—
—
—
N9
N8
H'FDE7 FVSR1L
N7
N6
N5
N4
N3
N2
N1
N0
H'FDE9 EPDR0O
D0
D7
D6
D5
D4
D3
D2
D1
H'FDEA FVSR0OH —
—
—
—
—
—
N9
N8
H'FDEB FVSR0OL N7
N6
N5
N4
N3
N2
N1
N0
H'FDED EPDR0I
D7
D6
D5
D4
D3
D2
D1
D0
H'FDEE FVSR0IH
—
—
—
—
—
—
N9
N8
H'FDEF FVSR0IL
N7
N6
N5
N4
N3
N2
N1
N0
H'FDF0
PTTER
—
—
—
—
EP2TE
EP1TE
EP0ITE
—
H'FDF1
USBIER
—
—
BRSTE
SOFE
SPNDE
TFE
TSE
SETUPE
H'FDF2
USBIFR
TS
TF
—
BRSTF
SOFF
SPNDOF SPNDIF
SETUPF
H'FDF3
TSFR
—
—
—
—
EP2TS
EP1TS
EP0ITS
EP0OTS
H'FDF4
TFFR
—
—
—
—
EP2TF
EP1TF
EP0ITF
EP0OTF
H'FDF5
USBCSR0 DP5CNCT DP4CNCT DP3CNCT DP2CNCE EP0STOP EPIVLD
EP0OTC CKSTOP
H'FDF6
EPSTLR
—
—
—
—
EP2STL
EP1STL
—
EP0STL
H'FDF7
EPDIR
—
—
—
—
EP2DIR
EP1DIR
—
—
H'FDF8
EPRSTR
—
—
—
—
EP2RST EP1RST EP0IRST —
H'FDF9
DEVRSMR —
—
—
—
—
—
—
DVR
H'FDFA INTSELR0 TSELB
EPIBS2
EPIBS1
EPIBS0
TSELC
EPICS2
EPICS1
EPICS0
H'FDFB INTSELR1 —
—
—
—
—
—
DTCBE
DTCCE
H'FDFC HOCCR
—
PCSP
OCDSP
HOC5E
HOC4E
HOC3E
HOC2E
—
H'FDFD USBCR
FADSEL FONLY
FNCSTP UIFRST
HPLLRST HSRST
FPLLRST FSRST
H'FDFE UPLLCR
—
—
—
CKSEL2
CKSEL1
CKSEL0
PFSEL1
PFSEL0
TESTB
TESTC
TESTD
TESTE
TESTF
TESTG
TESTH
H'FDFF UTESTR2 TESTA
Rev. 3.00 Mar 17, 2006 page 575 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
Register
Address Name
Bit 7
H'FE4C PCODR
PC7ODR PC6ODR PC5ODR
PC4ODR PC3ODR PC2ODR
PC1ODR PC0ODR Ports
H'FE4D PDODR
PD7ODR PD6ODR PD5ODR
PD4ODR PD3ODR PD2ODR
PD1ODR PD0ODR
H'FE4E
PCDDR
PC7DDR
PC6DDR
PC5DDR
PC4DDR
PC3DDR
PC2DDR
PC1DDR
PC0DDR
PCPIN
PC7PIN
PC6PIN
PC5PIN
PC4PIN
PC3PIN
PC2PIN
PC1PIN
PC0PIN
H'FE4F
H'FEE6
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PD7DDR
PD6DDR
PD5DDR
PD4DDR
PD3DDR
PD2DDR
PD1DDR
PD0DDR
PD7PIN
PD6PIN
PD5PIN
PD4PIN
PD3PIN
PD2PIN
PD1PIN
PD0PIN
SW
IE
IF
CLR3
CLR2
CLR1
CLR0
IIC0
8
—
—
—
—
IRQ2F
IRQ1F
IRQ0F
8
—
—
—
—
—
Interrupt
controller
—
PWM
8
SCK0
System
8
IIC1
8
FRT
8
DDCSWR SWE
—
—
—
—
H'FEED ISCRL
—
—
IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
H'FF82
PCSR
—
—
—
—
—
PWCKB
PWCKA
H'FF84
SBYCR
SSBY
STS2
STS1
STS0
—
SCK2
SCK1
H'FF86
MSTPCRH MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9
MSTP8
H'FF87
MSTPCRL MSTP7
MSTP0
MSTP6
MSTP5
MSTP4
MSTP3
MSTP2
MSTP1
H'FF88
ICCR1
ICE
IEIC
MST
TRS
ACKE
BBSY
IRIC
SCP
H'FF89
ICSR1
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
H'FF8E
ICDR1
ICDR7
ICDR6
ICDR5
ICDR4
ICDR3
ICDR2
ICDR1
ICDR0
SARX
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
H'FF8F
ICMR1
MLS
WAIT
CKS2
CKS1
CKS0
BC2
BC1
BC0
SAR
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
H'FF90
TIER
ICIAE
ICIBE
ICICE
ICIDE
OCIAE
OCIBE
OVIE
—
H'FF91
TCSR
ICFA
ICFB
ICFC
ICFD
OCFA
OCFB
OVF
CCLRA
H'FF92
FRCH
H'FF93
FRCL
16
OCRAH
OCRBH
H'FF95
OCRAL
H'FF96
TCR
IEDGA
H'FF97
TOCR
ICRDMS OCRAMS ICRS
OCRBL
IEDGB
IEDGC
ICRAH
OCRARH
H'FF99
ICRAL
OCRARL
H'FF9A
8
PDDDR
H'FEEC ISCRH
H'FF98
Bus
Width
PDPIN
H'FEEB ISR
H'FF94
Module
Name
ICRBH
OCRAFH
Rev. 3.00 Mar 17, 2006 page 576 of 706
REJ09B0303-0300
IEDGD
BUFEA
BUFEB
CKS1
CKS0
OCRS
OEA
OEB
OLVLA
OLVLB
Appendix B Internal I/O Registers
Register
Address Name
H'FF9B
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
ICRBL
Module
Name
Bus
Width
FRT
16
PWMX
8
OCRAFL
H'FF9C
ICRCH
OCRDMH
H'FF9D
ICRCL
OCRDML
H'FF9E
ICRDH
H'FF9F
ICRDL
H'FFA0
DADRAH
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DACR
TEST
PWME
—
—
OEB
OEA
OS
CKS
H'FFA1
DADRAL
DA5
DA4
DA3
DA2
DA1
DA0
CFS
—
H'FFA6
DADRBH
DA13
DA12
DA11
DA10
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
CFS
REGS
—
REGS
OVF
WT/IT
TME
RSTS
RST/NMI CKS2
CKS1
CKS0
WDT0
16
H'FFAC P1PCR
P17PCR
P16PCR
P15PCR
P14PCR
P13PCR
P12PCR
P11PCR
P10PCR
Port
8
H'FFAD P2PCR
P27PCR
P26PCR
P25PCR
P24PCR
P23PCR
P22PCR
P21PCR
P20PCR
H'FFAE P3PCR
P37PCR
P36PCR
P35PCR
P34PCR
P33PCR
P32PCR
P31PCR
P30PCR
H'FFB0
P1DDR
P17DDR
P16DDR
P15DDR
P14DDR
P13DDR
P12DDR
P11DDR
P10DDR
H'FFB1
P2DDR
P27DDR
P26DDR
P25DDR
P24DDR
P23DDR
P22DDR
P21DDR
P20DDR
H'FFB2
P1DR
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
H'FFB3
P2DR
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
H'FFB4
P3DDR
P37DDR
P36DDR
P35DDR
P34DDR
P33DDR
P32DDR
P31DDR
P30DDR
H'FFB5
P4DDR
P47DDR
P46DDR
P45DDR
P44DDR
P43DDR
P42DDR
P41DDR
P40DDR
H'FFB6
P3DR
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
H'FFB7
P4DR
P47DR
P46DR
P45DR
P44DR
P43DR
P42DR
P41DR
P40DR
H'FFB8
P5DDR
—
—
—
—
—
P52DDR
P51DDR
P50DDR
H'FFB9
P6DDR
P67DDR
P66DDR
P65DDR
P64DDR
P63DDR
P62DDR
P61DDR
P60DDR
—
—
—
—
—
P52DR
P51DR
P50DR
DACNTH
H'FFA7
DADRBL
H'FFA8
TCSR0
DACNTL
TCNT0
(write)
H'FFA9
TCNT0
(read)
H'FFBA P5DR
H'FFBB P6DR
P67DR
P66DR
P65DR
P64DR
P63DR
P62DR
P61DR
P60DR
H'FFBE P7PIN
P77PIN
P76PIN
P75PIN
P74PIN
P73PIN
P72PIN
P71PIN
P70PIN
H'FFC2
—
—
—
—
—
IRQ2E
IRQ1E
IRQ0E
IER
Interrupts 8
Rev. 3.00 Mar 17, 2006 page 577 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
Register
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
Bus
Width
H'FFC3
STCR
—
IICX1
IICX0
IICE
—
USBE
ICKS1
ICKS0
System
8
H'FFC4
SYSCR
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
H'FFC5
MDCR
EXPE
—
—
—
—
—
MDS1
MDS0
H'FFC6
BCR
ICIS1
ICIS0
BRSTRM BRSTS1 BRSTS0 —
IOS1
IOS0
TMR0,
TMR1
8
TMR0,
TMR1
16, 8
PWM
8
SCI0
8
H'FFC7
WSCR
RAMS
RAM0
ABW
AST
WMS1
WMS0
WC1
WC0
H'FFC8
TCR0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
H'FFC9
TCR1
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
H'FFCA TCSR0
CMFB
CMFA
OVF
ADTE
OS3
OS2
OS1
OS0
H'FFCB TCSR1
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
H'FFCC TCORA0
H'FFCD TCORA1
H'FFCE TCORB0
H'FFCF TCORB1
H'FFD0
TCNT0
H'FFD1
TCNT1
H'FFD2
PWOERB OE15
OE14
OE13
OE12
OE11
OE10
OE9
OE8
H'FFD3
PWOERA OE7
OE6
OE5
OE4
OE3
OE2
OE1
OE0
H'FFD4
PWDPRB OS15
OS14
OS13
OS12
OS11
OS10
OS9
OS8
H'FFD5
PWDPRA OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
H'FFD6
PWSL
PWCKE
PWCKS
—
—
RS3
RS2
RS1
RS0
H'FFD7
PWDR0
to
PWDR15
H'FFD8
SMR0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
ICCR0
ICE
IEIC
MST
TRS
ACKE
BBSY
IRIC
SCP
H'FFD9
BRR0
ICSR0
H'FFDA SCR0
IIC0
SCI0
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
IIC0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
SCI0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
H'FFDB TDR0
H'FFDC SSR0
H'FFDD RDR0
H'FFDE SCMR0
—
—
—
—
SDIR
SINV
—
SMIF
ICDR0
ICDR7
ICDR6
ICDR5
ICDR4
ICDR3
ICDR2
ICDR1
ICDR0
SARX0
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
H'FFDF ICMR0
MLS
WAIT
CKS2
CKS1
CKS0
BC2
BC1
BC0
SAR0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
H'FFE0
ADDRAH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FFE1
ADDRAL
AD1
AD0
—
—
—
—
—
—
Rev. 3.00 Mar 17, 2006 page 578 of 706
REJ09B0303-0300
IIC0
A/D
8
Appendix B Internal I/O Registers
Register
Address Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
Name
Bus
Width
H'FFE2
ADDRBH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
A/D
8
H'FFE3
ADDRBL
AD1
AD0
—
—
—
—
—
—
H'FFE4
ADDRCH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
H'FFE5
ADDRCL
AD1
AD0
—
—
—
—
—
—
AD2
8
H'FFE6
ADDRDH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
H'FFE7
ADDRDL
AD1
AD0
—
—
—
—
—
—
H'FFE8
ADCSR
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
H'FFE9
ADCR
TRGS1
TRGS0
—
—
—
—
—
—
H'FFF0
H'FFF1
H'FFF2
H'FFF3
H'FFF4
H'FFF5
TCRX
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
TMRX
TCRY
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
TMRY
TCSRX
CMFB
CMFA
OVF
ICF
OS3
OS2
OS1
OS0
TMRX
TCSRY
CMFB
CMFA
OVF
ICIE
OS3
OS2
OS1
OS0
TMRY
TICRR
TMRX
TCORAY
TMRY
TICRF
TMRX
TCORBY
TMRY
TCNTX
TMRX
TCNTY
TMRY
TCORC
TMRX
TISR
H'FFF6
TCORAX
H'FFF7
TCORBX
H'FFFC TCONRI
—
—
—
—
—
—
—
IS
TMRY
TMRX
SIMOD1
H'FFFD TCONRO HOE
SIMOD0
SCONE
ICST
HFINV
VFINV
HIINV
VIINV
VOE
CLOE
CBOE
HOINV
VOINV
CLOINV
CBOINV
H'FFFE
TCONRS
TMRX/Y
ISGENE
HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0
H'FFFF
SEDGR
VEDG
HEDG
CEDG
HFEDG
VFEDG
PREQF
IHI
Timer
connection
IVI
Rev. 3.00 Mar 17, 2006 page 579 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
B.2
Address
Register Selection Conditions
Register
Name
Register Selection Conditions
H'FDC0
UPRTCR
MSTP1 = 0
H'FDC1
UTESTR0
USBE = 1 in STCR
H'FDC2
UTESTR1
H'FDE1
EPDR2
H'FDE2
FVSR2H
H'FDE3
FVSR2L
H'FDE4
EPSZR1
H'FDE5
EPDR1
H'FDE6
FVSR1H
H'FDE7
FVSR1L
H'FDE9
EPDR0O
H'FDEA
FVSR0OH
H'FDEB
FVSR0OL
H'FDED
EPDR0I
H'FDEE
FVSR0IH
H'FDEF
FVSR0IL
H'FDF0
PTTER
H'FDF1
USBIER
H'FDF2
USBIFR
H'FDF3
TSFR0
H'FDF4
TFFR0
H'FDF5
USBCSR0
H'FDF6
EPSTLR
H'FDF7
EPDIR
H'FDF8
EPRSTR
H'FDF9
DEVRSMR
H'FDFA
INTSELR0
H'FDFB
INTSELR1
H'FDFC
HOCCR
H'FDFD
USBCR
H'FDFE
UPLLCR
H'FDFF
UTESTR2
Rev. 3.00 Mar 17, 2006 page 580 of 706
REJ09B0303-0300
Module
Name
USB
Appendix B Internal I/O Registers
Address
Register
Name
H'FE4C
PCODR
H'FE4D
PDODR
H'FE4E
PCDDR
Register Selection Conditions
Module
Name
Port
PCPIN
H'FE4F
PDDDR
PDPIN
H'FEE6
DDCSWR
MSTP4 = 0
IIC0
H'FEEB
ISR
No conditions
H'FEEC
ISCRH
Interrupt
controller
H'FEED
ISCRL
H'FF82
PCSR
FLSHE = 0 in STCR
PWM
H'FF84
SBYCR
FLSHE = 0 in STCR
System
H'FF86
MSTPCRH
H'FF87
MSTPCRL
H'FF88
ICCR1
MSTP3 = 0, IICE = 1 in STCR
IIC1
H'FF89
ICSR1
H'FF8E
ICDR1
H'FF8F
MSTP3 = 0, IICE = 1 in STCR
ICE = 1 in ICCR1
SARX1
ICE = 0 in ICCR1
ICMR1
ICE = 1 in ICCR1
SAR1
ICE = 0 in ICCR1
H'FF90
TIER
H'FF91
TCSR
H'FF92
FRCH
H'FF93
FRCL
H'FF94
OCRAH
OCRS = 0 in TOCR
OCRBH
OCRS = 1 in TOCR
H'FF95
OCRAL
OCRS = 0 in TOCR
OCRBL
OCRS = 1 in TOCR
H'FF96
TCR
H'FF97
TOCR
MSTP13 = 0
FRT
Rev. 3.00 Mar 17, 2006 page 581 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
Address
H'FF98
Register
Name
ICRAH
Register Selection Conditions
MSTP13 = 0
OCRARH
H'FF99
H'FF9A
H'FF9B
H'FF9C
ICRS = 0 in TOCR
Module
Name
FRT
ICRS = 1 in TOCR
ICRAL
ICRS = 0 in TOCR
OCRARL
ICRS = 1 in TOCR
ICRBH
ICRS = 0 in TOCR
OCRAFH
ICRS = 1 in TOCR
ICRBL
ICRS = 0 in TOCR
OCRAFL
ICRS = 1 in TOCR
ICRCH
ICRS = 0 in TOCR
OCRDMH
ICRS = 1 in TOCR
H'FF9D
ICRCL
ICRS = 0 in TOCR
OCRDML
ICRS = 1 in TOCR
H'FF9E
ICRDH
H'FF9F
ICRDL
H'FFA0
DADRAH
MSTP11 = 0, IICE = 1 in STCR
DACR
REGS=0 in DACNT/DADRB PWMX
REGS=1 in DACNT/DADRB
H'FFA1
DADRAL
MSTP11 = 0, IICE = 1 in STCR
REGS=0 in DACNT/DADRB
H'FFA6
DADRBH
MSTP11 = 0, IICE = 1 in STCR
REGS=0 in DACNT/DADRB
DACNTH
REGS=1 in DACNT/DADRB
H'FFA7
DADRBL
REGS=0 in DACNT/DADRB
H'FFA8
TCSR0
DACNTL
REGS=1 in DACNT/DADRB
No conditions
WDT0
No conditions
Ports
TCNT0
(write)
H'FFA9
TCNT0
(read)
H'FFAC
P1PCR
H'FFAD
P2PCR
H'FFAE
P3PCR
H'FFB0
P1DDR
Rev. 3.00 Mar 17, 2006 page 582 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
Address
Register
Name
H'FFB1
P2DDR
H'FFB2
P1DR
H'FFB3
P2DR
H'FFB4
P3DDR
H'FFB5
P4DDR
H'FFB6
P3DR
H'FFB7
P4DR
H'FFB8
P5DDR
H'FFB9
P6DDR
H'FFBA
P5DR
H'FFBB
P6DR
Register Selection Conditions
Module
Name
No conditions
Ports
H'FFBE
P7PIN
H'FFC2
IER
No conditions
Interrupts
H'FFC3
STCR
No conditions
System
H'FFC4
SYSCR
H'FFC5
MDCR
H'FFC6
BCR
No conditions
Bus controller
H'FFC7
WSCR
H'FFC8
TCR0
MSTP12 = 0
TMR0, TMR1
H'FFC9
TCR1
H'FFCA
TCSR0
H'FFCB
TCSR1
H'FFCC
TCORA0
H'FFCD
TCORA1
H'FFCE
TCORB0
H'FFCF
TCORB1
H'FFD0
TCNT0
H'FFD1
TCNT1
H'FFD2
PWOERB
No conditions
PWM
H'FFD3
PWOERA
H'FFD4
PWDPRB
H'FFD5
PWDPRA
Rev. 3.00 Mar 17, 2006 page 583 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
Address
Register
Name
H'FFD6
PWSL
H'FFD7
PWDR0 to 15
H'FFD8
Register Selection Conditions
Module
Name
MSTP11 = 0
PWM
SMR0
MSTP7 = 0, IICE = 0 in STCR
SCI0
ICCR0
MSTP4 = 0, IICE = 1 in STCR
IIC0
BRR0
MSTP7 = 0, IICE = 0 in STCR
SCI0
ICSR0
MSTP4 = 0, IICE = 1 in STCR
IIC0
H'FFDA
SCR0
MSTP7 = 0
SCI0
H'FFDB
TDR0
H'FFD9
H'FFDC
SSR0
H'FFDD
RDR0
H'FFDE
SCMR0
MSTP7 = 0, IICE = 0 in STCR
ICDR0
MSTP4 = 0, IICE = 1 in STCR
H'FFDF
ICE = 0 in ICCR0
ICMR0
ICE = 1 in ICCR0
SAR0
ICE = 0 in ICCR0
H'FFE0
ADDRAH
H'FFE1
ADDRAL
H'FFE2
ADDRBH
H'FFE3
ADDRBL
H'FFE4
ADDRCH
H'FFE5
ADDRCL
H'FFE6
ADDRDH
H'FFE7
ADDRDL
H'FFE8
ADCSR
H'FFE9
ADCR
H'FFF0
TCRX
MSTP9 = 0
MSTP8 = 0, HIE = 0 in SYSCR
TCRY
H'FFF1
TCSRX
MSTP8 = 0, HIE = 0 in SYSCR
TCSRY
H'FFF2
ICE = 1 in ICCR0
SARX0
TICRR
MSTP8 = 0, HIE = 0 in SYSCR
TCORAY
Rev. 3.00 Mar 17, 2006 page 584 of 706
REJ09B0303-0300
IIC0
A/D
TMRX/Y = 0 in TCONRS
TMRX
TMRX/Y = 1 in TCONRS
TMRY
TMRX/Y = 0 in TCONRS
TMRX
TMRX/Y = 1 in TCONRS
TMRY
TMRX/Y = 0 in TCONRS
TMRX
TMRX/Y = 1 in TCONRS
TMRY
Appendix B Internal I/O Registers
Address
H'FFF3
Register
Name
TICRF
Register Selection Conditions
MSTP8 = 0, HIE = 0 in SYSCR
TCORBY
H'FFF4
TCNTX
MSTP8 = 0, HIE = 0 in SYSCR
TCNTY
H'FFF5
TCORC
MSTP8 = 0, HIE = 0 in SYSCR
TISR
H'FFF6
TCORAX
H'FFF7
TCORBX
H'FFFC
TCONRI
H'FFFD
TCONRO
H'FFFE
TCONRS
H'FFFF
SEDGR
MSTP8 = 0, HIE = 0 in SYSCR
MSTP8 = 0, HIE = 0 in SYSCR
Module
Name
TMRX/Y = 0 in TCONRS
TMRX
TMRX/Y = 1 in TCONRS
TMRY
TMRX/Y = 0 in TCONRS
TMRX
TMRX/Y = 1 in TCONRS
TMRY
TMRX/Y = 0 in TCONRS
TMRX
TMRX/Y = 1 in TCONRS
TMRY
TMRX/Y = 0 in TCONRS
TMRX
Timer
connection
Rev. 3.00 Mar 17, 2006 page 585 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
B.3
Functions
Register
acronym
Register
name
Address to which the
register is mapped
Name of
on-chip
supporting
module
H'FEE6
DDCSWR—DDC Switch Register
IIC0
Bit
numbers
Bit
Initial bit
values
7
6
5
4
3
2
1
0
SWE
SW
IE
IF
—
—
—
—
1
1
1
1
—
—
—
—
Initial value
0
0
0
0
Read/Write
R/W
R/W
R/W
R/(W)*
DDC Mode Switch Interrupt Flag
0
Possible types of access
R
Read only
W
Write only
1
R/W Read and write
No interrupt is requested when automatic
format switching is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
Full name
of bit
An interrupt is requested when automatic
format switching is executed
[Setting condition]
When a falling edge is detected on the SCL
pin when SWE = 1
Descriptions
of bit settings
DDC Mode Switch Interrupt Enable Bit
0
Interrupt when automatic format switching is executed
is disabled
1
Interrupt when automatic format switching is executed
is enabled
DDC Mode Switch
0
IIC channel 0 is used with the I2C bus format
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when SWE = 1
1
IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
DDC Mode Switch Enable
0
Automatic switching of IIC channel 0 from formatless mode
to I2C bus format is disabled
1
Automatic switching of IIC channel 0 from formatless mode
to I2C bus format is enabled
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 586 of 706
REJ09B0303-0300
Names of the
bits. Dashes
(—) indicate
reserved bits.
Appendix B Internal I/O Registers
UPRTCR—USB Port Control Register
Bit
7
6
—
—
H'FDC0
4
5
3
USB
2
1
0
DSPSEL2 DSPSEL1 DSPSEL0 PCNMD2 PCNMD1 PCNMD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Port Connection Mode Select 2 to 0
0
0
1
1
0
0
User mode
1
Digital upstream mode
0
Digital downstream mode
1
Digital upstream/downstream mode
0
Upstream transceiver/receiver monitor mode
1
Downstream transceiver/receiver monitor mode
1 — Reserved
Downstream Port Select 2 to 0
0
0
1
0
Downstream port 2 selected
1
Downstream port 3 selected
0
Downstream port 4 selected
1
Downstream port 5 selected
1 — — Downstream port 1 selected
UTESTR0—USB Test Register 0
UTESTR1—USB Test Register 1
H'FDC1
H'FDC2
USB
USB
UTESTR0
Bit
7
6
5
4
3
2
TEST15 TEST14 TEST13 TEST12 TEST11 TEST10
1
0
TEST9
TEST8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UTESTR1
Bit
7
6
5
4
3
2
1
0
TEST7
TEST6
TEST5
TEST4
TEST3
TEST2
TEST1
TEST0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.00 Mar 17, 2006 page 587 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
EPDR2—Endpoint Data Register 2
H'FDE1
USB
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
Bit
Mediates data transfer between CPU and FIFO for each USB function endpoint
host input transfer/host output transfer
Note: * The EPDR2 transfer direction is determined by the endpoint direction register. EPDR2
is a write-only register when designated for host input transfer, and a read-only register
when designated for host output transfer.
FVSR2H—FIFO Valid Size Register 2H
FVSR2L—FIFO Valid Size Register 2L
H'FDE2
H'FDE3
FVSR2H
Bit
USB
USB
FVSR2L
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
—
—
—
—
—
—
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Indicates number of valid data bytes in FIFO for each USB function endpoint host
input/host output
Rev. 3.00 Mar 17, 2006 page 588 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
EPSZR1—Endpoint Size Register 1
7
Bit
6
H'FDE4
5
4
3
USB
2
1
0
EP1SZ3 EP1SZ2 EP1SZ1 EP1SZ0 EP2SZ3 EP2SZ2 EP2SZ1 EP2SZ0
Initial value
0
1
0
0
0
1
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Specifies number of FIFO bytes used
Bits 7 to 4
EP1 FIFO size
Bits 3 to 0
EP2 FIFO size
EPnSZ3 EPnSZ2 EPnSZ1 EPnSZ0
0
0
0
FIFO size = 0 bytes (settable for EP2 only)
1
Setting prohibited
0
Setting prohibited
1
Setting prohibited
0
FIFO size = 16 bytes
1
FIFO size = 32 bytes (settable for EP1 only)
1
0
Setting prohibited
1
Setting prohibited
—
—
Setting prohibited
1
1
0
—
1
Operating Mode
0
(Initial value)
n = 1, 2
EPDR1—Endpoint Data Register 1
Bit
H'FDE5
USB
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Mediates data transfer between CPU and FIFO for each USB function endpoint
host input transfer/host output transfer
Rev. 3.00 Mar 17, 2006 page 589 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
FVSR1H—FIFO Valid Size Register 1H
FVSR1L—FIFO Valid Size Register 1H
H'FDE6
H'FDE7
USB
USB
FVSR1H
Bit
FVSR1L
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
—
—
—
—
—
—
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Indicates number of valid data bytes in FIFO for each USB function endpoint host
input/host output
EPDR0O—Endpoint Data Register 0O
Bit
H'FDE9
USB
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Mediates data transfer between CPU and FIFO for each USB function endpoint
host input transfer/host output transfer
FVSR0OH—FIFO Valid Size Register 0OH
FVSR0OL—FIFO Valid Size Register 0OL
H'FDEA
H'FDEB
FVSR0OH
USB
USB
FVSR0OL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
—
—
—
—
—
—
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Indicates number of valid data bytes in FIFO for each USB function endpoint host
input/host output
Rev. 3.00 Mar 17, 2006 page 590 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
EPDR0I—Endpoint Data Register 0I
Bit
H'FDED
USB
7
6
5
4
3
2
1
0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Mediates data transfer between CPU and FIFO for each USB function endpoint
host input transfer/host output transfer
FVSR0IH—FIFO Valid Size Register 0IH
FVSR0IL—FIFO Valid Size Register 0IL
H'FDEE
H'FDEF
FVSR0IH
USB
USB
FVSR0IL
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
—
—
—
—
—
—
N9
N8
N7
N6
N5
N4
N3
N2
N1
N0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Indicates number of valid data bytes in FIFO for each USB function endpoint host
input/host output
Rev. 3.00 Mar 17, 2006 page 591 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PTTER—Packet Transmit Enable Register
H'FDF0
USB
7
6
5
4
3
2
1
0
—
—
—
—
EP2TE
EP1TE
EP0ITE
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/(W)*
R/(W)*
R/(W)*
R
Bit
Endpoint 0I Packet Transmit Enable
0
Initial set value
(1) [1 write]
Endpoint 0 IN-FIFO FVSR0I is updated
Endpoint 1 Packet Transmit Enable
0
Initial set value
(1) [1 write]
Endpoint 1 IN-FIFO FVSR1 is updated
Endpoint 2 Packet Transmit Enable
0
Initial set value
(1) [1 write]
Endpoint 2 IN-FIFO FVSR2 is updated
Note: * Only 1 can be written.
Rev. 3.00 Mar 17, 2006 page 592 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
USBIER—USB Interrupt Enable Register
H'FDF1
USB
7
6
5
4
3
2
1
0
—
—
BRSTE
SOFE
SPNDE
TFE
TSE
SETUPE
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Setup Interrupt Enable
0
USB function setup
interrupts disabled
1
USB function setup
interrupts enabled
Transfer Successful Interrupt Enable
0
USB function transfer successful
interrupts disabled
1
USB function transfer successful
interrupts enabled
Transfer Failed Interrupt Enable
0
USB function transfer failed interrupts
disabled
1
USB function transfer failed interrupts
enabled
Suspend Interrupt Enable
0
USB function suspend OUT interrupts and
suspend IN interrupts disabled
1
USB function suspend OUT interrupts and
suspend IN interrupts enabled
SOF Interrupt Enable
0
USB function SOF interrupts disabled
1
USB function SOF interrupts enabled
Bus Reset Interrupt Enable
0
USB function bus reset interrupts disabled
1
USB function bus reset interrupts enabled
Rev. 3.00 Mar 17, 2006 page 593 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
USBIFR—USB Interrupt Flag Register
Bit
H'FDF2
7
6
5
4
3
TS
TF
—
BRSTF
SOFF
USB
2
1
0
SPNDOF SPNDIF SETUPF
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Setup Interrupt Flag
0
[Clearing condition]
When 0 is written in SETUPF
after reading SETUPF = 1
1
[Setting condition]
When USB function endpoint
0 receives SETUP token
Suspend IN Interrupt Flag
0
[Clearing condition]
When 0 is written in SPNDIF
after reading SPNDIF = 1
1
[Setting condition]
When USB function switches from
normal state to suspend state
Suspend OUT Interrupt Flag
0
[Clearing condition]
When 0 is written in SPNDOF
after reading SPNDOF = 1
1
[Setting condition]
When USB function switches from
suspend state to normal state
SOF Interrupt Flag
0
[Clearing condition]
When 0 is written in SOFF after reading SOFF = 1
1
[Setting condition]
When USB function detects SOF (Start of Frame)
Bus Reset Interrupt Flag
0
[Clearing condition]
When 0 is written in BRSTF after reading BRSTF = 1
1
[Setting condition]
When USB function detects a bus reset from upstream
Transfer Failed Interrupt Status
0
All bits in transfer fail flag register (TFFR) are 0
1
At least one bit in transfer fail flag register (TFFR) is 1
Transfer Successful Interrupt Status
0
All bits in transfer success flag register (TSFR) are 0
1
At least one bit in transfer success flag register (TSFR) is 1
Note: * Only 0 can be written, after reading 1, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 594 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TSFR—Transfer Success Flag Register
Bit
H'FDF3
USB
7
6
5
4
3
2
—
—
—
—
EP2TS
EP1TS
1
0
EP0ITS EP0OTS
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Endpoint 0 Host Output Transfer Success Flag
0
Endpoint 0 is in host output transfer standby state
[Clearing conditions]
• When 0 is written in EP0OTS after reading EP0OTS = 1
• When endpoint 0 receives a SETUP token
1
Endpoint 0 host output transfer (OUT transaction
or SETUP transaction) has ended normally
[Setting conditions]
• ACK handshake established after OUT token reception
and data transfer (ACK transmission)
• When command received after SETUP token reception
requires processing by the slave CPU
Endpoint 0 Host Input Transfer Success Flag
0
Endpoint 0 is in host input transfer standby state
[Clearing conditions]
• When 0 is written in EP0ITS after reading EP0ITS = 1
• When endpoint 0 receives a SETUP token
1
Endpoint 0 host input transfer (IN transaction) has
ended normally
[Setting condition]
ACK handshake established after IN token reception
and data transfer (ACK reception)
Endpoint 1 Transfer Success Flag
0
Endpoint 1 is in transfer standby state
[Clearing condition]
When 0 is written in EP1TS after reading EP1TS = 1
1
Endpoint 1 host input transfer (IN transaction) has
ended normally
[Setting condition]
ACK handshake established after IN token reception
and data transfer (ACK reception)
Endpoint 2 Transfer Success Flag
0
Endpoint 2 is in transfer standby state)
[Clearing condition]
When 0 is written in EP2TS after reading EP2TS = 1
1
Endpoint 2 host input transfer (IN transaction) or host
output transfer (OUT transaction) has ended normally
[Setting conditions]
• ACK handshake established after IN token reception
and data transfer (ACK reception)
• ACK handshake established after OUT token reception
and data transfer (ACK transmission)
Note: * Only 0 can be written, after reading 1, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 595 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TFFR—Transfer Fail Flag Register
Bit
H'FDF4
USB
7
6
5
4
3
2
—
—
—
—
EP2TF
EP1TF
1
0
EP0ITF EP0OTF
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/(W)*
R/(W)*
R/(W)*
R/(W)*
Endpoint 0 Host Output Transfer Fail Flag
0
Endpoint 0 is in host output transfer standby state
[Clearing conditions]
• When 0 is written in EP0OTF after reading EP0OTF = 1
• When endpoint 0 receives a SETUP token
1
Endpoint 0 host output transfer (OUT transaction or
SETUP transaction) has ended abnormally
[Setting conditions]
• Data transfer not possible due to FIFO full condition
after OUT token reception (NAK transmission)
• Data transfer not possible because EP0OTC = 1
after OUT token reception (NAK transmission)
• Communication error after OUT token reception
• When command received after SETUP token reception
can be processed within the USB function core
Endpoint 0 Host Input Transfer Fail Flag
0
Endpoint 0 is in host input transfer standby state
[Clearing conditions]
• When 0 is written in EP0ITF after reading EP0ITF = 1
• When endpoint 0 receives a SETUP token
1
Endpoint 0 host input transfer (IN transaction) has ended abnormally
[Setting conditions]
• ACK handshake not established after IN token reception and
data transfer
• Data transfer not possible due to FIFO empty condition after
IN token reception (NAK transmission)
Endpoint 1 Transfer Fail Flag
0
Endpoint 1 is in transfer standby state
[Clearing condition]
When 0 is written in EP1TF after reading EP1TF = 1
1
Endpoint 1 host input transfer (IN transaction) has ended abnormally
[Setting conditions]
• ACK handshake not established after IN token reception and
data transfer
• Data transfer not possible due to FIFO empty condition after
IN token reception (NAK transmission)
Endpoint 2 Transfer Fail Flag
0
Endpoint 2 is in transfer standby state
[Clearing condition]
When 0 is written to EP2TF after reading EP2TF = 1
1
Endpoint 2 host input transfer (IN transaction) or host output transfer (OUT transaction) has ended abnormally
[Setting conditions]
• ACK handshake not established after IN token reception and data transfer
• Data transfer not possible due to FIFO empty condition after IN token reception (NAK transmission)
• Data reception not possible due to FIFO full condition after OUT token reception (NAK transmission)
• DATA0/DATA1 PID toggle error after OUT token reception
Note: * Only 0 can be written, after reading 1, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 596 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
USBCSR0—USB Control/Status Register 0
7
Bit
6
H'FDF5
5
4
3
USB
2
DP5CNCT DP4CNCT DP3CNCT DP2CNCT EP0STOP EPIVLD
1
0
EP0OTC CKSTOP
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/W
R/W
R/W
R/W
Clock Stop
0
Clock is supplied to USB function
[Clearing conditions]
• System reset
• Function soft reset
• Suspend OUT interrupt flag setting
1
Clock supply to USB function is stopped
[Setting condition]
When 1 is written in CKSTOP after
reading CKSTOP = 0
Endpoint 0O Transfer Control
0
EP0 OUT-FIFO writing stopped
• Subsequent writes to EP0 OUT-FIFO are invalid
[Clearing conditions]
• System reset
• Function soft reset
• Command data reception in SETUP transaction
(EP0OTS flag setting)
1
EP0 OUT-FIFO operational
[Setting conditions]
• SETUP token reception
• When 1 is written in EP0OTC after reading EP0OTC = 0
Endpoint Information Valid
0
Endpoint information (EPINFO) has not been set
[Clearing conditions]
• System reset
• Function soft reset
1
Endpoint information (EPINFO) has been set
Endpoint 0 Stop
0
EP0 OUT-FIFO, IN-FIFO operational
[Clearing conditions]
• System reset
• Function soft reset
1
EP0 OUT-FIFO reading stopped
• FVSR0O contents are not changed by an EPDR0O read
EP0 IN-FIFO writing and transfer stopped
• FIFO contents are not changed by an EPDR0I write
• FVSR0I contents are not changed by setting EP0IPTE
Downstream Port Connect 5 to 2
0
Cable is not connected to downstream port
[Clearing conditions]
• System reset
• Downstream port disconnect
• USB hub upstream port disconnect
(Total downstream disconnect by software in reconnect process)
1
Cable is connected to downstream port, and power is being supplied
[Setting condition]
Downstream port connect
Rev. 3.00 Mar 17, 2006 page 597 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
EPSTLR—Endpoint Stall Register
H'FDF6
7
6
5
4
—
—
—
—
Initial value
0
0
0
0
0
Read/Write
R
R
R
R
R/W
Bit
3
USB
2
1
0
—
EP0STL
0
0
0
R/W
R
R/W
EP2STL EP1STL
Endpoint 0 Stall
0
Endpoint 0 is operational
[Clearing condition]
When endpoint 0 receives a SETUP token
1
Endpoint 0 is in stall state
[Setting condition]
When 1 is written in EP0STL after reading EP0STL = 0
Endpoint 1 Stall
0
Endpoint 1 is operational
1
Endpoint 1 is in stall state
Endpoint 2 Stall
0
Endpoint 2 is operational
1
Endpoint 2 is in stall state
Rev. 3.00 Mar 17, 2006 page 598 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
EPDIR—Endpoint Direction Register
Bit
H'FDF7
7
6
5
4
3
USB
2
1
0
—
—
—
—
—
—
Initial value
1
1
1
1
1
1
0
0
Read/Write
R
R
R
R
R/W
R/W
R
R
EP2DIR EP1DIR
Endpoint 1 Data Transfer Direction Control Flag
0
Setting prohibited
1
Endpoint 1 is designated for host input transfer
Endpoint 2 Data Transfer Direction Control Flag
0
Endpoint 2 is designated for host output transfer
1
Endpoint 2 is designated for host input transfer
Rev. 3.00 Mar 17, 2006 page 599 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
EPRSTR—Endpoint Reset Register
H'FDF8
USB
7
6
5
4
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R/(W)*
R/(W)*
R/(W)*
R
Bit
3
2
1
EP2RST EP1RST EP0IRST
0
—
Endpoint 0I Reset
0
Initial set value
(1) [1 write]
FVSR0I is initialized to H'0010
Endpoint 1 Reset
0
Initial set value
(1) [1 write]
EP1 FIFO size = 16 bytes: FVSR1 is initialized to H'0010
EP1 FIFO size = 32 bytes: FVSR1 is initialized to H'0020
Endpoint 2 Reset
0
Initial set value
(1) [1 write]
EP2DIR = 0: FVSR2 is initialized to H'0000
EP2DIR = 1: FVSR2 is initialized to H'0010
Note: * Only 1 can be written.
Rev. 3.00 Mar 17, 2006 page 600 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
DEVRSMR—Device Resume Register
H'FDF9
USB
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
DVR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R/(W)*
Bit
Device Resume (DVR)
0
(Initial value)
(1) [1 write]
Suspend state is cleared (remote wakeup)
Note: * Only 1 can be written.
Rev. 3.00 Mar 17, 2006 page 601 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
INTSELR0—Interrupt Source Select Register 0
Bit
H'FDFA
USB
7
6
5
4
3
2
1
0
TSELB
EPIBS2
EPIBS1
EPIBS0
TSELC
EPICS2
EPICS1
EPICS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interrupt C Endpoint Select 2 to 0
0
0
1
0
Initial set value
1
Endpoint 1 selected
0
Endpoint 2 selected
1
Setting prohibited
1 — — Setting prohibited
Transfer Select C
0
USBIC is requested by a TS interrupt;
the endpoint constituting the TS interrupt
source is specified by bits EPICS2 to EPICS0
1
USBIC is requested by a TF interrupt;
the endpoint constituting the TF interrupt
source is specified by bits EPICS2 to EPICS0
Interrupt B Endpoint Select 2 to 0
0
0
1
0
Initial set value
1
Endpoint 1 selected
0
Endpoint 2 selected
1
Setting prohibited
1 — — Setting prohibited
Transfer Select B
0
USBIB is requested by a TS interrupt; the endpoint constituting
the TS interrupt source is specified by bits EPIBS2 to EPIBS0
1
USBIB is requested by a TF interrupt; the endpoint constituting
the TF interrupt source is specified by bits EPIBS2 to EPIBS0
Rev. 3.00 Mar 17, 2006 page 602 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
INTSELR1—Interrupt Source Select Register 1
H'FDFB
USB
7
6
5
4
3
2
1
0
—
—
—
—
—
—
DTCBE
DTCCE
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R/W
R/W
Bit
Note: Do not write 1 to the bits in this register.
Rev. 3.00 Mar 17, 2006 page 603 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
HOCCR—Hub Overcurrent Control Register
H'FDFC
USB
7
6
5
4
3
2
1
0
—
—
PCSP
OCDSP
HOC5E
HOC4E
HOC3E
HOC2E
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R/W
R/W
R/W
R/W
R/W
R/W
Overcurrent Detection Control Enable 2
0
Pins ENP2 and OCP2 are
general ports (PC4, PC0)
1
Pins ENP2 and OCP2 have
output enable and overcurrent
detection functions
Overcurrent Detection Control Enable 3
0
Pins ENP3 and OCP3 are
general ports (PC5, PC1)
1
Pins ENP3 and OCP3 have
output enable and overcurrent
detection functions
Overcurrent Detection Control Enable 4
0
Pins ENP4 and OCP4 are
general ports (PC6, PC2)
1
Pins ENP4 and OCP4 have
output enable and overcurrent
detection functions
Overcurrent Detection Control Enable 5
0
Pins ENP5 and OCP5 are
general ports (PC7, PC3)
1
Pins ENP5 and OCP5 have
output enable and overcurrent
detection functions
Overcurrent Detection Polarity
0
Power supply control IC outputs low level in case of overcurrent detection
1
Power supply control IC outputs high level in case of overcurrent detection
Power Supply Enable Control Polarity
0
Power supply control IC requires low-level input for enabling
1
Power supply control IC requires high-level input for enabling
Rev. 3.00 Mar 17, 2006 page 604 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
USBCR—USB Control Register
7
Bit
H'FDFD
6
5
4
USB
2
3
1
0
FADSEL FONLY FNCSTP UIFRST HPLLRST HSRST FPLLRST FSRST
Initial value
0
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Function Block Internal State Soft Reset
0
Internal state of USB function block
is set to operational state
1
Internal state of USB function block
is set to reset state (excluding DPLL)
Function Block PLL Soft Reset
0
Function DPLL is placed in operational
state
1
Function DPLL is placed in reset state
Hub Block Internal State Soft Reset
0
Internal state of USB hub block is set
to operational state
1
Internal state of USB hub block is set
to reset state (excluding DPLL)
Hub Block PLL Soft Reset
0
Hub DPLL is placed in operational state
1
Hub DPLL is placed in reset state
USB Interface Soft Reset
0
EPSZR1, USBIER, EPDIR, INTSELR0,
and INTSELR1 are placed in operational state
1
EPSZR1, USBIER, EPDIR, INTSELR0,
and INTSELR1 are placed in reset state
USB Function Stop/Suspend
0
For USB function block, USB hub downstream port 1 internal connection
is set to connected state
1
For USB function block, USB hub downstream port 1 internal connection
is set to disconnected state, and power-down state is set
USB Function Select
0
USB function block is connected internally to USB hub downstream port 1;
USB hub block is enabled
1
USB function block is directly connected to upstream port; USB hub block is disabled
USB Function I/O Analog/Digital Select
0
USD+ and USD– pins are used for USB function block data input/output
1
USB function block data input/output is implemented by multiplexing Philips transceiver/receiver (PIDUSB11A)
compatible control input/output with port C pins
Rev. 3.00 Mar 17, 2006 page 605 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
UPLLCR—USB PLL Control Register
Bit
7
6
5
H'FDFE
4
3
USB
2
1
0
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R/W
R/W
R/W
R/W
R/W
CKSEL2 CKSEL1 CKSEL0 PFSEL1 PFSEL0
PLL Frequency Select
0
1
0
PLL input clock is 8 MHz
1
PLL input clock is 12 MHz
0
PLL input clock is 16 MHz
1
PLL input clock is 20 MHz
Clock Source Select 2 to 0
0
0
0
PLL operation halted, clock input halted
— — PLL operation halted, clock input halted
1
0
1
0
Setting prohibited
1
PLL operation halted
USB clock pulse generator (XTAL12: 48 MHz)
used directly instead of PLL output
0
PLL operates with system clock pulse
generator (XTAL) as clock source
1
PLL operates with USB clock pulse
generator (XTAL12) as clock source
UTESTR2—USB Test Register 2
H'FDFF
USB
UTESTR2
Bit
7
6
5
4
3
2
1
0
TESTA
TESTB
TESTC
TESTD
TESTE
TESTF
TESTG
TESTH
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Rev. 3.00 Mar 17, 2006 page 606 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PCODR—Port C Data Output Register
Bit
7
6
H'FE4C
5
4
Port C
3
2
1
0
PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for port C pins
PDODR—Port D Data Output Register
Bit
7
6
H'FE4D
5
4
Port D
3
2
1
0
PD7ODR PD6ODR PD5ODR PD4ODR PD3ODR PD2ODR PD1ODR PD0ODR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for port D pins
PCDDR—Port C Data Direction Register
Bit
7
6
5
H'FE4E
4
3
Port C
2
1
0
PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Specify input or output for port C pins
Rev. 3.00 Mar 17, 2006 page 607 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PCPIN—Port C Input Data Register
H'FE4E
Port C
7
6
5
4
3
2
1
0
PC7PIN
PC6PIN
PC5PIN
PC4PIN
PC3PIN
PC2PIN
PC1PIN
PC0PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Bit
Port C pin states
Note: * Determined by the state of pins PC7 to PC0.
PDDDR—Port D Data Direction Register
Bit
7
6
5
H'FE4F
4
3
Port D
2
1
0
PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Specify input or output for port D pins
PDPIN—Port D Input Data Register
H'FE4F
Port D
7
6
5
4
3
2
1
0
PD7PIN
PD6PIN
PD5PIN
PD4PIN
PD3PIN
PD2PIN
PD1PIN
PD0PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Bit
Port D pin states
Note: * Determined by the state of pins PD7 to PD0.
Rev. 3.00 Mar 17, 2006 page 608 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
DDCSWR—DDC Switch Register
Bit
H'FEE6
IIC0
7
6
5
4
3
2
1
0
SWE
SW
IE
IF
CLR3
CLR2
CLR1
CLR0
Initial value
0
0
0
0
1
1
Read/Write
R/W
R/W
R/W
R/(W)*1
W*2
W*2
1
1
W*2
W*2
IIC Clear 3 to 0
0
0 — — Setting prohibited
1
0
1
0
Setting prohibited
1
IIC0 internal latch clearance
0
IIC1 internal latch clearance
1
IIC0 and IIC1 internal latch clearance
1 — — — Invalid setting
DDC Mode Switch Interrupt Flag
0
No interrupt is requested when automatic format
switching is executed
[Clearing condition]
When 0 is written in IF after reading IF = 1
1
An interrupt is requested when automatic format
switching is executed
[Setting condition]
When a falling edge is detected on the SCL pin
when SWE = 1
DDC Mode Switch Interrupt Enable Bit
0
Interrupt when automatic format switching is executed is disabled
1
Interrupt when automatic format switching is executed is enabled
DDC Mode Switch
0
IIC channel 0 is used with the I2C bus format
[Clearing conditions]
• When 0 is written by software
• When a falling edge is detected on the SCL pin when SWE = 1
1
IIC channel 0 is used in formatless mode
[Setting condition]
When 1 is written in SW after reading SW = 0
DDC Mode Switch Enable
0
Automatic switching of IIC channel 0 from formatless mode to I2C bus format is disabled
1
Automatic switching of IIC channel 0 from formatless mode to I2C bus format is enabled
Notes: 1. Only 0 can be written, to clear the flag.
2. Always read as 1.
Rev. 3.00 Mar 17, 2006 page 609 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
ISR—IRQ Status Register
Bit
H'FEEB
Interrupt Controller
7
6
5
4
3
2
1
0
—
—
—
—
—
IRQ2F
IRQ1F
IRQ0F
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R/(W)*
R/(W)*
R/(W)*
IRQ2 to IRQ0 Flags
0
[Clearing conditions]
• When 0 is written in IRQnF after reading IRQnF = 1
• When interrupt exception handling is executed while low-level detection
is set (IRQnSCB = IRQnSCA = 0) and IRQn input is high
• When IRQn interrupt exception handling is executed while falling, rising,
or both-edge detection is set (IRQnSCB = 1 or IRQnSCA = 1)
1
[Setting conditions]
• When IRQn input goes low while low-level detection is set (IRQnSCB =
IRQnSCA = 0)
• When a falling edge occurs in IRQn input while falling edge detection is
set (IRQnSCB = 0, IRQnSCA = 1)
• When a rising edge occurs in IRQn input while rising edge detection is
set (IRQnSCB = 1, IRQnSCA = 0)
• When a falling or rising edge occurs in IRQn input while both-edge
detection is set (IRQnSCB = IRQnSCA = 1)
Notes: n = 2 to 0
* Only 0 can be written, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 610 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
ISCRH—IRQ Sense Control Register H
ISCRL—IRQ Sense Control Register L
H'FEEC
H'FEED
Interrupt Controller
Interrupt Controller
ISCRH
15
14
13
12
11
10
9
8
—
—
—
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
2
1
0
Bit
Reserved
ISCRL
Bit
7
6
5
4
3
IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
IRQ2 to IRQ0 Sense Control A and B
ISCRL bits 5 to 0
Description
IRQ2SCB to
IRQ0SCB
IRQ2SCA to
IRQ0SCA
0
0
Interrupt request generated by low level
of IRQ2–IRQ0 input
1
Interrupt request generated by falling edge
of IRQ2–IRQ0 input
0
Interrupt request generated by rising edge
of IRQ2–IRQ0 input
1
Interrupt request generated by rising and falling
edges of IRQ2–IRQ0 input
1
Rev. 3.00 Mar 17, 2006 page 611 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PCSR—Peripheral Clock Select Register
H'FF82
PWM
7
6
5
4
3
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Bit
2
1
PWCKB PWCKA
PWM Clock Select
PWSL
Bit 7
PCSR
Bit 6
Bit 2
Bit 1
Description
PWCKE PWCKS PWCKB PWCKA
0
—
—
—
Clock input stopped
1
0
—
—
φ (system clock) selected
1
0
0
φ/2 selected
1
φ/4 selected
0
φ/8 selected
1
φ/16 selected
1
Rev. 3.00 Mar 17, 2006 page 612 of 706
REJ09B0303-0300
0
—
Appendix B Internal I/O Registers
SBYCR—Standby Control Register
H'FF84
System
7
6
5
4
3
2
1
0
SSBY
STS2
STS1
STS0
—
SCK2
SCK1
SCK0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
—
R/W
R/W
R/W
Bit
System Clock Select 2 to 0
0
0
1
1
0
0
Bus master is in high-speed mode
1
Medium-speed clock = φ/2
0
Medium-speed clock = φ/4
1
Medium-speed clock = φ/8
0
Medium-speed clock = φ/16
1
Medium-speed clock = φ/32
1 — —
Standby Timer Select 2 to 0
0
0
1
1
0
1
0
Standby time = 8,192 states
1
Standby time = 16,384 states
0
Standby time = 32,768 states
1
Standby time = 65,536 states
0
Standby time = 131,072 states
1
Standby time = 262,144 states
0
Reserved
1
Standby time = 16 states
Software Standby
0
Transition to sleep mode on execution of SLEEP instruction in
high-speed mode or medium-speed mode
1
Transition to software standby mode on execution of SLEEP
instruction in high-speed mode or medium-speed mode
Rev. 3.00 Mar 17, 2006 page 613 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
MSTPCRH—Module Stop Control Register H
MSTPCRL—Module Stop Control Register L
H'FF86
H'FF87
System
System
MSTPCRH
7
Bit
6
5
4
3
MSTPCRL
2
1
0
7
6
5
4
3
2
1
0
MSTP15 MSTP14 MSTP13 MSTP12 MSTP11 MSTP10 MSTP9 MSTP8 MSTP7 MSTP6 MSTP5 MSTP4 MSTP3 MSTP2 MSTP1 MSTP0
Initial value
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Module Stop
0
Module stop mode cleared
1
Module stop mode set
The correspondence between MSTPCR bits and on-chip supporting modules is shown below.
Register
Bit
MSTPCRH
MSTP15*
—
MSTP14*
—
MSTP13
16-bit free-running timer (FRT)
MSTP12
8-bit timers (TMR0, TMR1)
MSTP11
8-bit PWM timer (PWM), 14-bit PWM timer (PWMX)
MSTP10*
—
MSTP9
A/D converter
MSTP8
8-bit timers (TMRX, TMRY), timer connection
MSTP7
Serial communication interface 0 (SCI0)
MSTP6*
—
MSTP5*
—
MSTP4
I2C bus interface (IIC) channel 0
MSTP3
I2C bus interface (IIC) channel 1
MSTP2*
—
MSTP1
Universal serial bus interface (USB)
MSTP0*
—
MSTPCRL
Module
Note: * Bits 15, 14, 10, 6, 5, 2, and 0 can be read and written but must always be set to 1.
Rev. 3.00 Mar 17, 2006 page 614 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICCR1—I C Bus Control Register 1
Bit
H'FF88
IIC1
7
6
5
4
3
2
1
0
ICE
IEIC
MST
TRS
ACKE
BBSY
IRIC
SCP
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*
W
Start Condition/Stop Condition Prohibit
0
Writing issues a start or
stop condition, in combination
with the BBSY flag
1
Reading always returns a
value of 1; writing is invalid
I2C Bus Interface Interrupt Request Flag
0
Waiting for transfer, or transfer in progress
1
Interrupt requested
Note: For the clearing and setting conditions,
see section 16.2.5, I2C Bus Control
Register (ICCR).
Bus Busy
0
Bus is free
[Clearing condition]
When a stop condition is detected
1
Bus is busy
[Setting condition]
When a start condition is detected
Acknowledge Bit Judgement Select
0
Acknowledge bit is ignored and continuous
transfer is performed
1
If acknowledge bit is 1, continuous transfer
is interrupted
Master/Slave Select (MST), Transmit/Receive Select (TRS)
0
1
0
Slave receive mode
1
Slave transmit mode
0
Master receive mode
1
Master transmit mode
Note: For details see section 16.2.5, I2C Bus Control Register (ICCR).
I2C Bus Interface Interrupt Enable
I2C
0
Interrupt requests disabled
1
Interrupt requests enabled
Bus Interface Enable
0
I2C bus interface module disabled, with SCL and SDA signal pins set to port function
SAR and SARX can be accessed
1
I2C bus interface module enabled for transfer operations (pins SCL and SDA are driving the bus)
ICMR and ICDR can be accessed
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 615 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICSR1—I C Bus Status Register 1
Bit
H'FF89
IIC1
7
6
5
4
3
2
1
0
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
Initial value
0
0
Read/Write
R/(W)*1
0
0
0
0
0
1
1
1
1
1
*
*
*
*
*
R/(W)
R/(W)
R/(W)
R/(W)
R/(W)*1
R/(W)
0
R/W
Acknowledge Bit
0
Receive mode: 0 is output at
acknowledge output timing
Transmit mode: indicates that the
receiving device has acknowledged
the data (0 value)
1
Receive mode: 1 is output at
acknowledge output timing
Transmit mode: indicates that
the receiving device has not
acknowledged the data (1 value)
General Call Address Recognition Flag*2
0
General call address not recognized
1
General call address recognized
Slave Address Recognition Flag*2
0
Slave address or general call address
not recognized
1
Slave address or general call address
recognized
Arbitration Lost Flag*2
0
Bus arbitration won
1
Bus arbitration lost
Second Slave Address Recognition Flag*2
I2C
0
Second slave address not recognized
1
Second slave address recognized
Bus Interface Continuous Transmission/Reception Interrupt Request Flag*2
0
Waiting for transfer, or transfer in progress
1
Continuous transfer state
Normal Stop Condition Detection Flag*2
0
No normal stop condition
1
In I2C bus format slave mode: Normal stop condition detected
In other modes: No meaning
Error Stop Condition Detection Flag*2
0
No error stop condition
1
In I2C bus format slave mode: Error stop condition detected
In other modes: No meaning
Notes: 1. Only 0 can be written, to clear the flag.
2. For the clearing and setting conditions, see section 16.2.6, I2C Bus Status Register (ICSR).
Rev. 3.00 Mar 17, 2006 page 616 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICDR1—I C Bus Data Register 1
Bit
H'FF8E
IIC1
7
6
5
4
3
2
1
0
ICDR7
ICDR6
ICDR5
ICDR4
ICDR3
ICDR2
ICDR1
ICDR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
• ICDRR
Bit
ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
• ICDRS
Bit
ICDRS7 ICDRS6 ICDRS5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0
Initial value
—
—
—
—
—
—
—
—
Read/Write
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
• ICDRT
Bit
ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0
Initial value
—
—
—
—
—
—
—
—
Read/Write
W
W
W
W
W
W
W
W
—
—
TDRE
RDRF
• TDRE, RDRF (internal flags)
Bit
Initial value
0
0
Read/Write
—
—
Note: For details see section 16.2.1, I2C Bus Data Register (ICDR).
Rev. 3.00 Mar 17, 2006 page 617 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SARX—Second Slave Address Register 1
Bit
H'FF8E
IIC1
7
6
5
4
3
2
1
0
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Second Slave Address
Format Select X
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW
FS
FSX
0
0
0
I2C bus format
• SAR and SARX slave addresses recognized
1
I2C bus format
• SAR slave address recognized
• SARX slave address ignored
0
I2C bus format
• SAR slave address ignored
• SARX slave address recognized
1
Synchronous serial format
• SAR and SARX slave addresses ignored
0
Formatless mode
(start/stop conditions not detected)
• Acknowledge bit present
1
1
0
1
1
0
1
Operating Mode
Formatless mode*
(start/stop conditions not detected)
• No acknowledge bit
Note: * Do not select this mode when automatic switching to the I2C bus format is
performed by means of a DDCSWR setting.
Rev. 3.00 Mar 17, 2006 page 618 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SAR—Slave Address Register
H'FF8F
IIC1
7
6
5
4
3
2
1
0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Slave Address
Format Select
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW
FS
FSX
0
0
0
I2C bus format
• SAR and SARX slave addresses recognized
1
I2C bus format
• SAR slave address recognized
• SARX slave address ignored
0
I2C bus format
• SAR slave address ignored
• SARX slave address recognized
1
Synchronous serial format
• SAR and SARX slave addresses ignored
0
Formatless mode
(start/stop conditions not detected)
• Acknowledge bit present
1
1
0
1
1
0
1
Operating Mode
Formatless mode*
(start/stop conditions not detected)
• No acknowledge bit
Note: * Do not select this mode when automatic switching to the I2C bus format is
performed by means of a DDCSWR setting.
Rev. 3.00 Mar 17, 2006 page 619 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICMR1—I C Bus Mode Register 1
H'FF8F
IIC1
7
6
5
4
3
2
1
0
MLS
WAIT
CKS2
CKS1
CKS0
BC2
BC1
BC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Counter
BC2
BC1
BC0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
Synchronous
Serial Format
8
1
2
3
4
5
6
7
Transfer Clock Select
IICX
0
CKS2
0
CKS1
0
1
1
0
1
1
0
0
1
1
0
1
CKS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock
φ/28
φ/40
φ/48
φ/64
φ/80
φ/100
φ/112
φ/128
φ/56
φ/80
φ/96
φ/128
φ/160
φ/200
φ/224
φ/256
Wait Insertion Bit
0
Data and acknowledge transferred consecutively
1
Wait inserted between data and acknowledge
MSB-First/LSB-First Select*
0
MSB-first
1
LSB-first
Note: * Do not set this bit to 1 when using the I2C bus format.
Rev. 3.00 Mar 17, 2006 page 620 of 706
REJ09B0303-0300
I2C Bus
Format
9
2
3
4
5
6
7
8
Appendix B Internal I/O Registers
TIER—Timer Interrupt Enable Register
H'FF90
FRT
7
6
5
4
3
2
1
0
ICIAE
ICIBE
ICICE
ICIDE
OCIAE
OCIBE
OVIE
—
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
—
Bit
Timer Overflow Interrupt Enable
0
OVF interrupt request
(FOVI) is disabled
1
OVF interrupt request
(FOVI) is enabled
Output Compare Interrupt B Enable
0
OCFB interrupt request (OCIB)
is disabled
1
OCFB interrupt request (OCIB)
is enabled
Output Compare Interrupt A Enable
0
OCFA interrupt request (OCIA)
is disabled
1
OCFA interrupt request (OCIA)
is enabled
Input Capture Interrupt D Enable
0
ICFD interrupt request (ICID) is disabled
1
ICFD interrupt request (ICID) is enabled
Input Capture Interrupt C Enable
0
ICFC interrupt request (ICIC) is disabled
1
ICFC interrupt request (ICIC) is enabled
Input Capture Interrupt B Enable
0
ICFB interrupt request (ICIB) is disabled
1
ICFB interrupt request (ICIB) is enabled
Input Capture Interrupt A Enable
0
ICFA interrupt request (ICIA) is disabled
1
ICFA interrupt request (ICIA) is enabled
Rev. 3.00 Mar 17, 2006 page 621 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCSR—Timer Control/Status Register
Bit
H'FF91
FRT
7
6
5
4
3
2
1
0
ICFA
ICFB
ICFC
ICFD
OCFA
OCFB
OVF
CCLRA
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
Counter Clear A
0
1
FRC clearing is
disabled
FRC is cleared at
compare-match A
Timer Overflow
0
1
[Clearing condition]
When 0 is written in OVF after
reading OVF = 1
[Setting condition]
When the FRC value overflows
from H'FFFF to H'0000
Output Compare Flag B
0
1
[Clearing condition]
When 0 is written in OCFB after reading OCFB = 1
[Setting condition]
When FRC = OCRB
Output Compare Flag A
0
1
[Clearing condition]
When 0 is written in OCFA after reading OCFA = 1
[Setting condition]
When FRC = OCRA
Input Capture Flag D
0
1
[Clearing condition]
When 0 is written in ICFD after reading ICFD = 1
[Setting condition]
When an input capture signal is generated
Input Capture Flag C
0
1
[Clearing condition]
When 0 is written in ICFC after reading ICFC = 1
[Setting condition]
When an input capture signal is generated
Input Capture Flag B
0
1
[Clearing condition]
When 0 is written in ICFB after reading ICFB = 1
[Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRB
Input Capture Flag A
0
1
[Clearing condition]
When 0 is written in ICFA after reading ICFA = 1
[Setting condition]
When an input capture signal causes the FRC value to be transferred to ICRA
Note: * Only 0 can be written in bits 7 to 1, to clear the flags.
Rev. 3.00 Mar 17, 2006 page 622 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
FRCH—Free-Running Counter H
FRCL—Free-Running Counter L
H'FF92
H'FF93
FRT
FRT
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
OCRAH—Output Compare Register AH
OCRAL—Output Compare Register AL
OCRBH—Output Compare Register BH
OCRBL—Output Compare Register BL
H'FF94
H'FF95
H'FF94
H'FF95
FRT
FRT
FRT
FRT
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Constantly compared with FRC value; OCF is set when OCR = FRC
Rev. 3.00 Mar 17, 2006 page 623 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCR—Timer Control Register
H'FF96
FRT
7
6
5
4
3
2
1
0
IEDGA
IEDGB
IEDGC
IEDGD
BUFEA
BUFEB
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Clock Select
0
1
0
φ/2 internal clock source
1
φ/8 internal clock source
0
φ/32 internal clock source
1
External clock source
(rising edge)
Buffer Enable B
0
ICRD is not used as ICRB buffer
register
1
ICRD is used as ICRB buffer
register
Buffer Enable A
0
ICRC is not used as ICRA buffer register
1
ICRC is used as ICRA buffer register
Input Edge Select D
0
Capture on falling edge of input capture input D
1
Capture on rising edge of input capture input D
Input Edge Select C
0
Capture on falling edge of input capture input C
1
Capture on rising edge of input capture input C
Input Edge Select B
0
Capture on falling edge of input capture input B
1
Capture on rising edge of input capture input B
Input Edge Select A
0
Capture on falling edge of input capture input A
1
Capture on rising edge of input capture input A
Rev. 3.00 Mar 17, 2006 page 624 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TOCR—Timer Output Compare Control Register
7
Bit
FRT
5
4
3
2
1
0
ICRS
OCRS
OEA
OEB
OLVLA
OLVLB
6
ICRDMS OCRAMS
H'FF97
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output Level B
0
0 output at comparematch B
1
1 output at comparematch B
Output Level A
0
0 output at comparematch A
1
1 output at comparematch A
Output Enable B
0
Output compare B output disabled
1
Output compare B output enabled
Output Enable A
0
Output compare A output disabled
1
Output compare A output enabled
Output Compare Register Select
0
OCRA register selected
1
OCRB register selected
Input Capture Register Select
0
ICRA, ICRB, and ICRC registers selected
1
OCRAR, OCRAF, and OCRDM registers selected
Output Compare A Mode Select
0
OCRA set to normal operating mode
1
OCRA set to operating mode using OCRAR and OCRAF
Input Capture D Mode Select
0
ICRD set to normal operating mode
1
ICRD set to operating mode using OCRDM
Rev. 3.00 Mar 17, 2006 page 625 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
OCRARH—Output Compare Register ARH
OCRARL—Output Compare Register ARL
OCRAFH—Output Compare Register AFH
OCRAFL—Output Compare Register AFL
H'FF98
H'FF99
H'FF9A
H'FF9B
FRT
FRT
FRT
FRT
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Used for OCRA operation when OCRAMS = 1 in TOCR
(For details see section 11.2.4, Output Compare Registers
AR and AF (OCRAR, OCRAF).)
ICRAH—Input Capture Register AH
ICRAL—Input Capture Register AL
ICRBH—Input Capture Register BH
ICRBL—Input Capture Register BL
H'FF98
H'FF99
H'FF9A
H'FF9B
FRT
FRT
FRT
FRT
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Stores FRC value when input capture signal is input
Rev. 3.00 Mar 17, 2006 page 626 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
OCRDMH—Output Compare Register DMH
OCRDML—Output Compare Register DML
H'FF9C
H'FF9D
FRT
FRT
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Used for ICRD operation when ICRDMS = 1 in TOCR
(For details see section 11.2.5, Output Compare Register
DM (OCRDM).)
ICRCH—Input Capture Register CH
ICRCL—Input Capture Register CL
ICRDH—Input Capture Register DH
ICRDL—Input Capture Register DL
H'FF9C
H'FF9D
H'FF9E
H'FF9F
FRT
FRT
FRT
FRT
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Stores FRC value when input capture signal is input
(ICRC and ICRD can be used for buffer operation.
For details see section 11.2.3, Input Capture Registers
A to D (ICRA to ICRD).)
Rev. 3.00 Mar 17, 2006 page 627 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
DACR—PWM (D/A) Control Register
H'FFA0
PWMX
7
6
5
4
3
2
1
0
TEST
PWME
—
—
OEB
OEA
OS
CKS
Initial value
0
0
1
1
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
Bit
Clock Select
0
Operates at resolution (T) =
system clock cycle time (tcyc)
1
Operates at resolution (T) =
system clock cycle time (tcyc) × 2
Output Select
0
Direct PWM output
1
Inverted PWM output
Output Enable A
0
PWM (D/A) channel A output
(PWX0 output pin) disabled
1
PWM (D/A) channel A output
(PWX0 output pin) enabled
Output Enable B
0
PWM (D/A) channel B output
(PWX1 output pin) disabled
1
PWM (D/A) channel B output
(PWX1 output pin) enabled
PWM Enable
0
DACNT operates as 14-bit up-counter
1
DACNT halts at H'0003
Test Mode
0
PWM (D/A) in user state, normal operation
1
PWM (D/A) in test state, correct conversion results unobtainable
Rev. 3.00 Mar 17, 2006 page 628 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
DADRAH—PWM (D/A) Data Register AH
DADRAL—PWM (D/A) Data Register AL
DADRBH—PWM (D/A) Data Register BH
DADRBL—PWM (D/A) Data Register BL
H'FFA0
H'FFA1
H'FFA6
H'FFA7
DADRH
PWMX
PWMX
PWMX
PWMX
DADRL
Bit (CPU)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Bit (data)
13
12
11
10
9
8
7
6
5
4
3
2
1
0
—
—
DADRA
Initial value
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
—
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W —
DADRB
Initial value
DA13 DA12 DA11 DA10 DA9 DA8 DA7 DA6 DA5 DA4 DA3 DA2 DA1 DA0 CFS REGS
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Register Select (DADRB Only)
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
Carrier Frequency Select
0
Base cycle = resolution (T) × 64
DADR range = H'0401 to H'FFFD
1
Base cycle = resolution (T) × 256
DADR range = H'0103 to H'FFFF
D/A Data 13 to 0
D/A conversion data.
Rev. 3.00 Mar 17, 2006 page 629 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
DACNTH—PWM (D/A) Counter H
DACNTL—PWM (D/A) Counter L
H'FFA6
H'FFA7
DACNTH
PWMX
PWMX
DACNTL
Bit (CPU)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Bit (counter)
7
6
5
4
3
2
1
0
8
9
10
11
12
13
—
—
—
REGS
1
1
Initial value
Read/Write
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W —
0
R/W
Register Select
Up-counter
Rev. 3.00 Mar 17, 2006 page 630 of 706
REJ09B0303-0300
0
DADRA and DADRB can be accessed
1
DACR and DACNT can be accessed
Appendix B Internal I/O Registers
TCSR0—Timer Control/Status Register 0
Bit
7
6
5
OVF
WT/IT
TME
H'FFA8
4
3
RSTS RST/NMI
WDT0
2
1
0
CKS2
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select 2 to 0
CKS1
CKS0
0
0
0
φ/2
25.6 µs
1
φ/64
819.2 µs
0
φ/128
1.6 ms
1
φ/512
6.6 ms
0
φ/2048
26.2 ms
1
φ/8192
104.9 ms
0
φ/32768
419.4 ms
1
φ/131072 1.68 s
1
1
0
1
Clock
Overflow Period
(when φ = 20 MHz)
CKS2
Reset or NMI
0
NMI interrupt requested
1
Internal reset requested
Reserved
Timer Enable
0
TCNT is initialized to H'00 and halted
1
TCNT counts
Timer Mode Select
0
Interval timer mode: Sends the CPU an interval timer interrupt
request (WOVI) when TCNT overflows
1
Watchdog timer mode: Generates a reset or NMI interrupt
when TCNT overflows
Overflow Flag
0
[Clearing conditions]
• When 0 is written in the TME bit
• When 0 is written in OVF after reading TCSR when OVF = 1
1
[Setting condition]
When TCNT overflows from H'FF to H'00
(When internal reset request generation is selected in watchdog timer mode,
OVF is cleared automatically by the internal reset)
Notes: The method of writing to TCSR is more complicated that for most other registers, to
prevent accidental overwriting. For details see section 14.2.4, Notes on Register Access.
* Only 0 can be written, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 631 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCNT0—Timer Counter 0
H'FFA8 (W), H'FFA9 (R)
WDT0
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Up-counter
P1PCR—Port 1 MOS Pull-Up Control Register
Bit
7
6
5
4
H'FFAC
3
Port 1
2
1
0
P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Control port 1 MOS input pull-ups
P2PCR—Port 2 MOS Pull-Up Control Register
Bit
7
6
5
4
H'FFAD
3
Port 2
2
1
0
P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Control port 2 MOS input pull-ups
Rev. 3.00 Mar 17, 2006 page 632 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
P3PCR—Port 3 MOS Pull-Up Control Register
Bit
7
6
5
4
H'FFAE
3
Port 3
2
1
0
P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Control port 3 MOS input pull-ups
P1DDR—Port 1 Data Direction Register
Bit
7
6
5
H'FFB0
4
3
Port 1
2
1
0
P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Specify input or output for port 1 pins
P2DDR—Port 2 Data Direction Register
Bit
7
6
5
H'FFB1
4
3
Port 2
2
1
0
P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Specify input or output for port 2 pins
Rev. 3.00 Mar 17, 2006 page 633 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
P1DR—Port 1 Data Register
Bit
H'FFB2
Port 1
7
6
5
4
3
2
1
0
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for port 1 pins
P2DR—Port 2 Data Register
Bit
H'FFB3
Port 2
7
6
5
4
3
2
1
0
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for port 2 pins
P3DDR—Port 3 Data Direction Register
Bit
7
6
5
H'FFB4
4
3
Port 3
2
1
0
P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Specify input or output for port 3 pins
Rev. 3.00 Mar 17, 2006 page 634 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
P4DDR—Port 4 Data Direction Register
Bit
7
6
5
H'FFB5
4
3
Port 4
2
1
0
P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Specify input or output for port 4 pins
P3DR—Port 3 Data Register
Bit
H'FFB6
Port 3
7
6
5
4
3
2
1
0
P37DR
P36DR
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for port 3 pins
P4DR—Port 4 Data Register
Bit
H'FFB7
Port 4
7
6
5
4
3
2
1
0
P47DR
P46DR
P45DR
P44DR
P43DR
P42DR
P41DR
P40DR
Initial value
0
—*
0
0
0
0
0
0
Read/Write
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
Output data for port 4 pins
Note: * Determined by the state of pin P46.
Rev. 3.00 Mar 17, 2006 page 635 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
P5DDR—Port 5 Data Direction Register
Bit
H'FFB8
7
6
5
4
3
Port 5
2
1
0
P52DDR P51DDR P50DDR
—
—
—
—
—
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
W
W
W
Specify input or output
for port 5 pins
P6DDR—Port 6 Data Direction Register
Bit
7
6
5
H'FFB9
4
Port 6
3
2
1
0
P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR
Initial value
0
0
0
0
0
0
0
0
Read/Write
W
W
W
W
W
W
W
W
Specify input or output for port 6 pins
P5DR—Port 5 Data Register
Bit
H'FFBA
Port 5
7
6
5
4
3
2
1
0
—
—
—
—
—
P52DR
P51DR
P50DR
Initial value
1
1
1
1
1
0
0
0
Read/Write
—
—
—
—
—
R/W
R/W
R/W
Output data for port 5 pins
Rev. 3.00 Mar 17, 2006 page 636 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
P6DR—Port 6 Data Register
Bit
H'FFBB
Port 6
7
6
5
4
3
2
1
0
P67DR
P66DR
P65DR
P64DR
P63DR
P62DR
P61DR
P60DR
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Output data for port 6 pins
P7PIN—Port 7 Input Data Register
Bit
H'FFBE
Port 7
7
6
5
4
3
2
1
0
P77PIN
P76PIN
P75PIN
P74PIN
P73PIN
P72PIN
P71PIN
P70PIN
Initial value
—*
—*
—*
—*
—*
—*
—*
—*
Read/Write
R
R
R
R
R
R
R
R
Port 7 pin states
Note: * Determined by the state of pins P77 to P70.
IER—IRQ Enable Register
Bit
H'FFC2
Interrupt Controller
7
6
5
4
3
2
1
0
—
—
—
—
—
IRQ2E
IRQ1E
IRQ0E
Initial value
1
1
1
1
1
0
0
0
Read/Write
R
R
R
R
R
R/W
R/W
R/W
IRQ2 to IRQ0 Enable
0
IRQn interrupt disabled
1
IRQn interrupt enabled
(n = 2 to 0)
Rev. 3.00 Mar 17, 2006 page 637 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
STCR—Serial Timer Control Register
Bit
:
Initial value :
R/W
:
H'FFC3
System
7
6
5
4
3
2
1
0
—
IICX1
IICX0
IICE
—
USBE
ICKS1
ICKS0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Internal Clock Source
select*1
USB Enable
0
CPU access to USB data registers and control
registers is disabled
1
CPU access to USB data registers and control
registers is enabled
Reserved
I2C Master Enable
0
CPU access to I2C bus interface data registers and
control registers is disabled
1
CPU access to I2C bus interface data registers and
control registers is enabled
I2C Transfer Rate Select 1 and 0*2
Reserved
Notes: 1. Used for 8-bit timer input clock selection. For details see section 12.2.4, Timer
Control Register (TCR).
2. Used for I2C bus interface transfer clock selection. For details see section 16.2.4,
I2C Bus Mode Register (ICMR).
Rev. 3.00 Mar 17, 2006 page 638 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SYSCR—System Control Register
Bit
H'FFC4
System
7
6
5
4
3
2
1
0
CS2E
IOSE
INTM1
INTM0
XRST
NMIEG
HIE
RAME
Initial value
0
0
0
0
1
0
0
1
Read/Write
R/W
R/W
R
R
R
R/W
R/W
R/W
RAM Enable
0
On-chip RAM is disabled
1
On-chip RAM is enabled
Host Interface Enable
0 In areas H'FFF0 to H'FFF7 and
H'FFFC to H'FFFF, CPU access to
8-bit timer (channel X and Y) data
registers and control registers,
and timer connection control registers,
is permitted
1
In areas H'FFF0 to H'FFF7 and
H'FFFC to H'FFFF, CPU access to
8-bit timer (channel X and Y) data
registers and control registers,
and timer connection control registers,
is not permitted
NMI Edge Select
0
Interrupt request generated by NMI falling edge
1
Interrupt request generated by NMI rising edge
External Reset
0
Reset generated by watchdog timer overflow
1
Reset generated by external reset
Interrupt Control Mode 1 and 0
INTM1 INTM0
0
1
Interrupt
Control Mode
Description
0
0
Interrupts are controlled by I bit
1
1
Cannot be used in these groups
0
2
Cannot be used in these groups
1
3
Cannot be used in these groups
IOS Enable
Do not set this bit to 1.
Chip Select 2 Enable
Do not set this bit to 1.
Rev. 3.00 Mar 17, 2006 page 639 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
MDCR—Mode Control Register
H'FFC5
System
7
6
5
4
3
2
1
0
EXPE
—
—
—
—
—
MDS1
MDS0
Initial value
0*
0
0
0
0
0
1*
1*
Read/Write
R
—
—
—
—
—
R
R
Bit
Mode Select 1 and 0
Mode pin states.
Expanded Mode Enable
Note: * Determined by the MD1 and MD0 pins (H8/3577 Group) or the TEST pin (H8/3567
Group).
BCR—Bus Control Register
H'FFC6
7
6
ICIS1
ICIS0
Initial value
1
1
0
1
Read/Write
R/W
R/W
R
R/W
Bit
5
4
3
Bus Controller
2
1
0
—
IOS1
IOS0
0
1
1
1
R
R/W
R/W
R/W
BRSTRM BRSTS1 BRSTS0
Do not write any values other than the initial values.
WSCR—Wait State Control Register
Bit
H'FFC7
Bus Controller
7
6
5
4
3
2
1
0
RAMS
RAM0
ABW
AST
WMS1
WMS0
WC1
WC0
Initial value
0
0
1
1
0
0
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Do not write any values other than the initial values.
Rev. 3.00 Mar 17, 2006 page 640 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCR0—Timer Control Register 0
TCR1—Timer Control Register 1
H'FFC8
H'FFC9
TMR0
TMR1
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter Clear 1 and 0
0
0
Clearing is disabled
1
Cleared on comparematch A
0
Cleared on comparematch B
1
Cleared on rising edge
of external reset input
Clock Select 2 to 0
Channel
1
Bit 2
Bit 1
Bit 0
Description
CKS2 CKS1 CKS0
0
0
0
0
Clock input disabled
1*1 φ/8 internal clock source, counted on falling edge
φ/2 internal clock source, counted on falling edge
1
0*1 φ/64 internal clock source, counted on falling edge
φ/32 internal clock source, counted on falling edge
1*1 φ/1024 internal clock source, counted on falling edge
Timer Overflow Interrupt Enable
0
OVF interrupt request (OVI) is disabled
1
OVF interrupt request (OVI) is enabled
φ/256 internal clock source, counted on falling edge
1
1
0
0
Counted on TCNT1 overflow signal*2
0
0
0
Clock input disabled
1*1 φ/8 internal clock source, counted on falling edge
Compare-Match Interrupt Enable A
0
CMFA interrupt request (CMIA) is disabled
1
CMFA interrupt request (CMIA) is enabled
φ/2 internal clock source, counted on falling edge
1
0*1 φ/64 internal clock source, counted on falling edge
φ/128 internal clock source, counted on falling edge
1*1 φ/1024 internal clock source, counted on falling edge
Compare-Match Interrupt Enable B
0
CMFB interrupt request (CMIB) is disabled
1
CMFB interrupt request (CMIB) is enabled
φ/2048 internal clock source, counted on falling edge
X
1
0
0
Counted on TCNT0 compare-match A*2
0
0
0
Clock input disabled
1
Counted on φ internal clock source
0
φ/2 internal clock source, counted on falling edge
1
φ/4 internal clock source, counted on falling edge
1
Y
1
0
0
Clock input disabled
0
0
0
Clock input disabled
1
φ/4 internal clock source, counted on falling edge
0
φ/256 internal clock source, counted on falling edge
1
φ/2048 internal clock source, counted on falling edge
1
Common
1
0
0
Clock input disabled
1
0
1
External clock source, counted on rising edge
1
0
External clock source, counted on falling edge
1
External clock source, counted on both rising and
falling edges
Notes: 1. Selected by ICKS1 and ICKS0 in STCR. For details see section 12.2.4,
Timer Control Register (TCR).
2. If the count input of channel 0 is the TCNT1 overflow signal and
that of channel 1 is the TCNT0 compare-match signal, no incrementing
clock will be generated. Do not use this setting.
Rev. 3.00 Mar 17, 2006 page 641 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCSR0—Timer Control/Status Register 0
H'FFCA
TMR0
TCSR0
Bit
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ADTE
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
Output Select 1 and 0
0
0
1
No change when compare-match A occurs
1
0 output when compare-match A occurs
0
1 output when compare-match A occurs
1
Output inverted when compare-match A
occurs (toggle output)
Output Select 3 and 2
0
1
0
No change when compare-match B occurs
1
0 output when compare-match B occurs
0
1 output when compare-match B occurs
1
Output inverted when compare-match B
occurs (toggle output)
A/D Trigger Enable
0
A/D converter start requests by compare-match A
are disabled
1
A/D converter start requests by compare-match A
are enabled
Timer Overflow Flag
0
[Clearing condition]
When 0 is written in OVF after reading OVF = 1
1
[Setting condition]
When TCNT overflows from H'FF to H'00
Compare-Match Flag A
0
[Clearing condition]
When 0 is written in CMFA after reading CMFA = 1
1
[Setting condition]
When TCNT = TCORA
Compare-Match Flag B
0
[Clearing condition]
When 0 is written in CMFB after reading CMFB = 1
1
[Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written in bits 7 to 5, to clear the flags.
Rev. 3.00 Mar 17, 2006 page 642 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCSR1—Timer Control/Status Register 1
H'FFCB
TMR1
TCSR1
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
Initial value
0
0
0
1
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
—
R/W
R/W
R/W
R/W
Bit
Output Select 1 and 0
0
1
0
No change when compare-match A occurs
1
0 output when compare-match A occurs
0
1 output when compare-match A occurs
1
Output inverted when compare-match A
occurs (toggle output)
Output Select 3 and 2
0
1
0
No change when compare-match B occurs
1
0 output when compare-match B occurs
0
1 output when compare-match B occurs
1
Output inverted when compare-match B
occurs (toggle output)
Timer Overflow Flag
0
[Clearing condition]
When 0 is written in OVF after reading OVF = 1
1
[Setting condition]
When TCNT overflows from H'FF to H'00
Compare-Match Flag A
0
[Clearing condition]
When 0 is written in CMFA after reading CMFA = 1
1
[Setting condition]
When TCNT = TCORA
Compare-Match Flag B
0
[Clearing condition]
When 0 is written in CMFB after reading CMFB = 1
1
[Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written in bits 7 to 5, to clear the flags.
Rev. 3.00 Mar 17, 2006 page 643 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCORA0—Time Constant Register A0
TCORA1—Time Constant Register A1
TCORB0—Time Constant Register B0
TCORB1—Time Constant Register B1
H'FFCC
H'FFCD
H'FFCE
H'FFCF
TCORA0
TCORB0
TMR0
TMR1
TMR0
TMR1
TCORA1
TCORB1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Compare-match flag (CMF) is set when TCOR and TCNT values match
TCNT0—Timer Counter 0
TCNT1—Timer Counter 1
H'FFD0
H'FFD1
TCNT0
TMR0
TMR1
TCNT1
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Up-counter
Rev. 3.00 Mar 17, 2006 page 644 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PWOERB—PWM Output Enable Register B
PWOERA—PWM Output Enable Register A
Bit
PWOERB
H'FFD2
H'FFD3
PWM
PWM
7
6
5
4
3
2
1
0
OE15
OE14
OE13
OE12
OE11
OE10
OE9
OE8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
PWOERA
OE7
OE6
OE5
OE4
OE3
OE2
OE1
OE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Switching between PWM output and port output
DDR
OE
0
0
Port input
1
Port input
0
Port output or PWM 256/256 output
1
PWM output (0 to 255/256 output)
1
Description
Rev. 3.00 Mar 17, 2006 page 645 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PWDPRB—PWM Data Polarity Register B
PWDPRA—PWM Data Polarity Register A
Bit
PWDPRB
H'FFD4
H'FFD5
PWM
PWM
7
6
5
4
3
2
1
0
OS15
OS14
OS13
OS12
OS11
OS10
OS9
OS8
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
OS7
OS6
OS5
OS4
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
PWDPRA
PWM output polarity control
0 PWM direct output (PWDR value corresponds to high width of output)
1 PWM inverted output (PWDR value corresponds to low width of output)
Rev. 3.00 Mar 17, 2006 page 646 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PWSL—PWM Register Select
7
Bit
H'FFD6
6
PWCKE PWCKS
PWM
5
4
3
2
1
0
—
—
RS3
RS2
RS1
RS0
Initial value
0
0
1
0
0
0
0
0
Read/Write
R/W
R/W
—
—
R/W
R/W
R/W
R/W
Register Select
0
0
0
0 PWDR0 selected
1 PWDR1 selected
1
0 PWDR2 selected
1 PWDR3 selected
1
0
0 PWDR4 selected
1 PWDR5 selected
1
0 PWDR6 selected
1 PWDR7 selected
1
0
0
0 PWDR8 selected
1 PWDR9 selected
1
0 PWDR10 selected
1 PWDR11 selected
1
0
0 PWDR12 selected
1 PWDR13 selected
1
0 PWDR14 selected
1 PWDR15 selected
PWM Clock Enable, PWM Clock Select
PWSL
Bit 7
PCSR
Bit 6
Bit 2
Bit 1
Description
PWCKE PWCKS PWCKB PWCKA
0
—
—
—
Clock input disabled
1
0
—
—
φ (system clock) selected
1
0
0
φ/2 selected
1
φ/4 selected
0
φ/8 selected
1
φ/16 selected
1
Rev. 3.00 Mar 17, 2006 page 647 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
PWDR0 to PWDR15—PWM Data Registers
H'FFD7
PWM
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Specifies duty cycle of basic output pulse and number of additional pulses
Rev. 3.00 Mar 17, 2006 page 648 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICCR0—I C Bus Control Register 0
Bit
H'FFD8
IIC0
7
6
5
4
3
2
1
0
ICE
IEIC
MST
TRS
ACKE
BBSY
IRIC
SCP
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/(W)*
W
Start Condition/Stop Condition Prohibit
0
Writing issues a start or
stop condition, in combination
with the BBSY flag
1
Reading always returns a
value of 1; writing is invalid
I2C Bus Interface Interrupt Request Flag
0
Waiting for transfer, or transfer in progress
1
Interrupt requested
Note: For the clearing and setting conditions,
see section 16.2.5, I2C Bus Control
Register (ICCR).
Bus Busy
0
Bus is free
[Clearing condition]
When a stop condition is detected
1
Bus is busy
[Setting condition]
When a start condition is detected
Acknowledge Bit Judgement Select
0
Acknowledge bit is ignored and continuous
transfer is performed
1
If acknowledge bit is 1, continuous transfer
is interrupted
Master/Slave Select (MST), Transmit/Receive Select (TRS)
0
1
0
Slave receive mode
1
Slave transmit mode
0
Master receive mode
1
Master transmit mode
Note: For details see section 16.2.5, I2C Bus Control Register (ICCR).
I2C Bus Interface Interrupt Enable
I2C
0
Interrupt requests disabled
1
Interrupt requests enabled
Bus Interface Enable
0
I2C bus interface module disabled, with SCL and SDA signal pins set to port function
SAR and SARX can be accessed
1
I2C bus interface module enabled for transfer operations (pins SCL and SDA are driving the bus)
ICMR and ICDR can be accessed
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 649 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SMR0—Serial Mode Register 0
Bit
H'FFD8
SCI0
7
6
5
4
3
2
1
0
C/A
CHR
PE
O/E
STOP
MP
CKS1
CKS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Select 1 and 0
0
1
0
φ clock
1
φ/4 clock
0
φ/16 clock
1
φ/64 clock
Multiprocessor Mode
0
Multiprocessor function disabled
1
Multiprocessor format selected
Stop Bit Length
0 1 stop bit*1
1
2 stop bits*2
Notes: 1. In transmission, a single 1 bit (stop bit) is added to
the end of a transmit character before it is sent.
2. In transmission, two 1 bits (stop bits) are added to
the end of a transmit character before it is sent.
Parity Mode
0 Even parity*1
1
Odd parity*2
Notes: 1. When even parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is even.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is even.
2. When odd parity is set, parity bit addition is performed in
transmission so that the total number of 1 bits in the transmit
character plus the parity bit is odd.
In reception, a check is performed to see if the total number
of 1 bits in the receive character plus the parity bit is odd.
Parity Enable
0
Parity bit addition and checking disabled
1
Parity bit addition and checking enabled*
Note: * When the PE bit is set to 1, the parity (even or odd) specified by the O/E
bit is added to transmit data before transmission. In reception, the parity
bit is checked for the parity (even or odd) specified by the O/E bit.
Character Length
0
8-bit data
1
7-bit data*
Note: * When 7-bit data is selected, the MSB (bit 7) of TDR is not
transmitted, and LSB-first/MSB-first selection is not available.
Communication Mode
0
Asynchronous mode
1
Synchronous mode
Rev. 3.00 Mar 17, 2006 page 650 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
BRR0—Bit Rate Register 0
H'FFD9
SCI0
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Sets the serial transmit/receive bit rate
Rev. 3.00 Mar 17, 2006 page 651 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICSR0—I C Bus Status Register 0
Bit
H'FFD9
IIC0
7
6
5
4
3
2
1
0
ESTP
STOP
IRTR
AASX
AL
AAS
ADZ
ACKB
0
0
0
0
0
0
Initial value
0
Read/Write
R/(W)*1
R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1 R/(W)*1
0
R/W
Acknowledge Bit
0
Receive mode: 0 is output at
acknowledge output timing
Transmit mode: indicates that the
receiving device has acknowledged
the data (0 value)
1
Receive mode: 1 is output at
acknowledge output timing
Transmit mode: indicates that
the receiving device has not
acknowledged the data (1 value)
General Call Address Recognition Flag*2
0
General call address not recognized
1
General call address recognized
Slave Address Recognition Flag*2
0
Slave address or general call address
not recognized
1
Slave address or general call address
recognized
Arbitration Lost Flag*2
0
Bus arbitration won
1
Bus arbitration lost
Second Slave Address Recognition Flag*2
0
Second slave address not recognized
1
Second slave address recognized
I2C Bus Interface Continuous Transmission/Reception Interrupt Request Flag*2
0
Waiting for transfer, or transfer in progress
1
Continuous transfer state
Normal Stop Condition Detection Flag*2
0
No normal stop condition
1
In I2C bus format slave mode: Normal stop condition detected
In other modes: No meaning
Error Stop Condition Detection Flag*2
0
No error stop condition
1
In I2C bus format slave mode: Error stop condition detected
In other modes: No meaning
Notes: 1. Only 0 can be written, to clear the flag.
2. For the clearing and setting conditions, see section 16.2.6, I2C Bus Status Register (ICSR).
Rev. 3.00 Mar 17, 2006 page 652 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SCR0—Serial Control Register 0
Bit
H'FFDA
SCI0
7
6
5
4
3
2
1
0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clock Enable 1 and 0
0
1
0 Asynchronous
mode
Synchronous
mode
1 Asynchronous
mode
Synchronous
mode
0 Asynchronous
mode
Synchronous
mode
1 Asynchronous
mode
Synchronous
mode
Internal clock/SCK pin functions
as I/O port
Internal clock/SCK pin functions
as serial clock output
Internal clock/SCK pin functions
as clock output
Internal clock/SCK pin functions
as serial clock output
External clock/SCK pin functions
as clock input
External clock/SCK pin functions
as serial clock input
External clock/SCK pin functions
as clock input
External clock/SCK pin functions
as serial clock input
Transmit End Interrupt Enable
0 Transmit end interrupt (TEI) request disabled
1 Transmit end interrupt (TEI) request enabled
Multiprocessor Interrupt Enable
0 Multiprocessor interrupts disabled (normal reception performed)
[Clearing conditions]
• When the MPIE bit is cleared to 0
• When data with MPB = 1 is received
1 Multiprocessor interrupts enabled
Receive interrupt (RXI) requests, receive error interrupt (ERI)
requests, and setting of the RDRF, FER, and ORER flags in
SSR are disabled until data with the multiprocessor bit set to 1
is received
Receive Enable
0 Reception disabled
1 Reception enabled
Transmit Enable
0 Transmission disabled
1 Transmission enabled
Receive Interrupt Enable
0 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request disabled
1 Receive data full interrupt (RXI) request and receive error interrupt (ERI) request enabled
Transmit Interrupt Enable
0 Transmit data empty interrupt (TXI) request disabled
1 Transmit data empty interrupt (TXI) request enabled
Rev. 3.00 Mar 17, 2006 page 653 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TDR0—Transmit Data Register 0
H'FFDB
SCI0
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Serial transmit data
Rev. 3.00 Mar 17, 2006 page 654 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SSR0—Serial Status Register 0
H'FFDC
SCI0
7
6
5
4
3
2
1
0
TDRE
RDRF
ORER
FER
PER
TEND
MPB
MPBT
Initial value
1
0
0
0
0
1
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R
R
R/W
Bit
Multiprocessor Bit Transfer
0
Data with a 0 multiprocessor
bit is transmitted
1
Data with a 1 multiprocessor
bit is transmitted
Multiprocessor Bit
0
[Clearing condition]
When data with a 0 multiprocessor
bit is received
1
[Setting condition]
When data with a 1 multiprocessor
bit is received
Transmit End
0
[Clearing condition]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
• When the TE bit in SCR is 0
• When TDRE = 1 at transmission of the last bit of
a 1-byte serial transmit character
Parity Error
0
Clearing condition]
When 0 is written in PER after reading PER = 1
1
[Setting condition]
When, in reception, the number of 1 bits in the receive
data plus the parity bit does not match the parity setting
(even or odd) specified by the O/E bit in SMR
Framing Error
0
[Clearing condition]
When 0 is written in FER after reading FER = 1
1
[Setting condition]
When the SCI checks the stop bit at the end of the receive data
when reception ends, and the stop bit is 0
Overrun Error
0
[Clearing condition]
When 0 is written in ORER after reading ORER = 1
1
[Setting condition]
When the next serial reception is completed while RDRF = 1
Receive Data Register Full
0
[Clearing condition]
When 0 is written in RDRF after reading RDRF = 1
1
[Setting condition]
When serial reception ends normally and receive data is transferred from RSR to RDR
Transmit Data Register Empty
0
[Clearing condition]
When 0 is written in TDRE after reading TDRE = 1
1
[Setting conditions]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR and data can be written in TDR
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 655 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
RDR0—Receive Data Register 0
H'FFDD
SCI0
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Serial receive data
SCMR0—Serial Interface Mode Register 0
Bit
H'FFDE
SCI0
7
6
5
4
3
2
1
0
—
—
—
—
SDIR
SINV
—
SMIF
Initial value
1
1
1
1
0
0
1
0
Read/Write
—
—
—
—
R/W
R/W
—
R/W
Serial Communication
Interface Mode Select
0
Normal SCI mode
1
Setting prohibited
Data Invert
0
TDR contents are transmitted without modification
Receive data is stored in RDR without modification
1
TDR contents are inverted before being transmitted
Receive data is stored in RDR in inverted form
Data Transfer Direction
0
TDR contents are transmitted LSB-first
Receive data is stored in RDR LSB-first
1
TDR contents are transmitted MSB-first
Receive data is stored in RDR MSB-first
Rev. 3.00 Mar 17, 2006 page 656 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICDR0—I C Bus Data Register 0
Bit
H'FFDE
IIC0
7
6
5
4
3
2
1
0
ICDR7
ICDR6
ICDR5
ICDR4
ICDR3
ICDR2
ICDR1
ICDR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
7
6
5
4
3
2
1
0
• ICDRR
Bit
ICDRR7 ICDRR6 ICDRR5 ICDRR4 ICDRR3 ICDRR2 ICDRR1 ICDRR0
Initial value
—
—
—
—
—
—
—
—
Read/Write
R
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
• ICDRS
Bit
ICDRS7 ICDRS6 ICDRS5 ICDRS4 ICDRS3 ICDRS2 ICDRS1 ICDRS0
Initial value
—
—
—
—
—
—
—
—
Read/Write
—
—
—
—
—
—
—
—
7
6
5
4
3
2
1
0
• ICDRT
Bit
ICDRT7 ICDRT6 ICDRT5 ICDRT4 ICDRT3 ICDRT2 ICDRT1 ICDRT0
Initial value
—
—
—
—
—
—
—
—
Read/Write
W
W
W
W
W
W
W
W
—
—
TDRE
RDRF
• TDRE, RDRF (internal flags)
Bit
Initial value
0
0
Read/Write
—
—
Note: For details see section 16.2.1, I2C Bus Data Register (ICDR).
Rev. 3.00 Mar 17, 2006 page 657 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SARX0—Second Slave Address Register 0
H'FFDE
IIC0
7
6
5
4
3
2
1
0
SVAX6
SVAX5
SVAX4
SVAX3
SVAX2
SVAX1
SVAX0
FSX
Initial value
0
0
0
0
0
0
0
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Second Slave Address
Format Select
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW
FS
FSX
0
0
0
I2C bus format
• SAR and SARX slave addresses recognized
1
I2C bus format
• SAR slave address recognized
• SARX slave address ignored
0
I2C bus format
• SAR slave address ignored
• SARX slave address recognized
1
Synchronous serial format
• SAR and SARX slave addresses ignored
0
Formatless mode
(start/stop conditions not detected)
• Acknowledge bit present
1
1
0
1
1
0
1
Operating Mode
Formatless mode*
(start/stop conditions not detected)
• No acknowledge bit
Note: * Do not select this mode when automatic switching to the I2C bus format is
performed by means of a DDCSWR setting.
Rev. 3.00 Mar 17, 2006 page 658 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SAR0—Slave Address Register 0
H'FFDF
IIC0
7
6
5
4
3
2
1
0
SVA6
SVA5
SVA4
SVA3
SVA2
SVA1
SVA0
FS
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Slave Address
Format Select
DDCSWR
Bit 6
SAR
Bit 0
SARX
Bit 0
SW
FS
FSX
0
0
0
I2C bus format
• SAR and SARX slave addresses recognized
1
I2C bus format
• SAR slave address recognized
• SARX slave address ignored
0
I2C bus format
• SAR slave address ignored
• SARX slave address recognized
1
Synchronous serial format
• SAR and SARX slave addresses ignored
0
Formatless mode
(start/stop conditions not detected)
• Acknowledge bit present
1
1
0
1
1
0
1
Operating Mode
Formatless mode*
(start/stop conditions not detected)
• No acknowledge bit
Note: * Do not select this mode when automatic switching to the I2C bus format is
performed by means of a DDCSWR setting.
Rev. 3.00 Mar 17, 2006 page 659 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
2
ICMR0—I C Bus Mode Register 0
H'FFDF
IIC0
7
6
5
4
3
2
1
0
MLS
WAIT
CKS2
CKS1
CKS0
BC2
BC1
BC0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Bit Counter
BC2
BC1
BC0
0
0
0
1
0
1
0
1
0
1
1
1
0
1
Synchronous
Serial Format
8
1
2
3
4
5
6
7
Transfer Clock Select
IICX
0
CKS2
0
CKS1
0
1
1
0
1
1
0
0
1
1
0
1
CKS0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Clock
φ/28
φ/40
φ/48
φ/64
φ/80
φ/100
φ/112
φ/128
φ/56
φ/80
φ/96
φ/128
φ/160
φ/200
φ/224
φ/256
Wait Insertion Bit
0
Data and acknowledge transferred consecutively
1
Wait inserted between data and acknowledge
MSB-First/LSB-First Select*
0
MSB-first
1
LSB-first
Note: * Do not set this bit to 1 when using the I2C bus format.
Rev. 3.00 Mar 17, 2006 page 660 of 706
REJ09B0303-0300
I2C Bus
Format
9
2
3
4
5
6
7
8
Appendix B Internal I/O Registers
ADDRAH—A/D Data Register AH
ADDRAL—A/D Data Register AL
ADDRBH—A/D Data Register BH
ADDRBL—A/D Data Register BL
ADDRCH—A/D Data Register CH
ADDRCL—A/D Data Register CL
ADDRDH—A/D Data Register DH
ADDRDL—A/D Data Register DL
H'FFE0
H'FFE1
H'FFE2
H'FFE3
H'FFE4
H'FFE5
H'FFE6
H'FFE7
ADDRH
Bit
14
12
A/D
A/D
A/D
A/D
A/D
A/D
A/D
A/D
ADDRL
10
8
6
5
4
3
2
1
0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 —
15
13
11
9
7
—
—
—
—
—
Initial value
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
A/D data
Correspondence between analog input channels and ADDR registers
Analog Input Channel
A/D Data Register
Group 0
Group 1
AN0
AN4
ADDRA
AN1
AN5
ADDRB
AN2
AN6
ADDRC
AN3
AN7
ADDRD
Rev. 3.00 Mar 17, 2006 page 661 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
ADCSR—A/D Control/Status Register
H'FFE8
A/D Converter
7
6
5
4
3
2
1
0
ADF
ADIE
ADST
SCAN
CKS
CH2
CH1
CH0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Bit
Channel Select
Group
Selection
Channel
Selection
Description
CH2
CH1
CH0
H8/3577
Group /
H8/3567
Group
0
0
0
AN0
AN0
1
AN1
AN0, AN1
0
AN2
AN0, AN1, AN2
1
AN3
AN0, AN1, AN2, AN3
H8/3577
Group
only
1
0
AN4
AN4
1
AN5
AN4, AN5
0
AN6
AN4, AN5, AN6
1
AN7
AN4, AN5, AN6, AN7
1
0
1
Single Mode
Scan Mode
Clock Select
0
Conversion time = 266 states (max.)
1
Conversion time = 134 states (max.)
Scan Mode
0
Single mode
1
Scan mode
A/D Start
0
A/D conversion stopped
1
• Single mode: A/D conversion is started. Cleared to 0 automatically
when conversion on the specified channel ends
• Scan mode: A/D conversion is started. Conversion continues
consecutively on the selected channels until ADST is cleared to 0
by software, a reset, or a transition to standby mode or module
stop mode
A/D Interrupt Enable
0
A/D conversion end interrupt (ADI) request disabled
1
A/D conversion end interrupt (ADI) request enabled
A/D end flag
0
[Clearing condition]
When 0 is written in ADF after reading ADF = 1
1
[Setting conditions]
• Single mode: When A/D conversion ends
• Scan mode: When A/D conversion ends on all specified channels
Note: * Only 0 can be written, to clear the flag.
Rev. 3.00 Mar 17, 2006 page 662 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
ADCR—A/D Control Register
H'FFE9
A/D
7
6
5
4
3
2
1
0
TRGS1
TRGS0
—
—
—
—
—
—
Initial value
0
0
1
1
1
1
1
1
Read/Write
R/W
R/W
—
—
—
—
—
—
Bit
Timer Trigger Select
0
1
0
Start of A/D conversion by external trigger is disabled
1
Start of A/D conversion by external trigger is disabled
0
Start of A/D conversion by external trigger (8-bit timer) is enabled
1
Start of A/D conversion by external trigger pin is enabled
Rev. 3.00 Mar 17, 2006 page 663 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCRX—Timer Control Register X
TCRY—Timer Control Register Y
H'FFF0
H'FFF0
TMRX
TMRY
7
6
5
4
3
2
1
0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
Bit
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Counter Clear 1 and 0
0
0
Clearing is disabled
1
Cleared on comparematch A
0
Cleared on comparematch B
1
Cleared on rising edge
of external reset input
Clock Select 2 to 0
Channel
1
Bit 2
Bit 1
Bit 0
Description
CKS2 CKS1 CKS0
0
0
0
0
Clock input disabled
1*1 φ/8 internal clock source, counted on falling edge
φ/2 internal clock source, counted on falling edge
1
0*1 φ/64 internal clock source, counted on falling edge
φ/32 internal clock source, counted on falling edge
1*1 φ/1024 internal clock source, counted on falling edge
Timer Overflow Interrupt Enable
0
OVF interrupt request (OVI) is disabled
1
OVF interrupt request (OVI) is enabled
φ/256 internal clock source, counted on falling edge
1
1
0
0
Counted on TCNT1 overflow signal*2
0
0
0
Clock input disabled
1*1 φ/8 internal clock source, counted on falling edge
Compare-Match Interrupt Enable A
0
CMFA interrupt request (CMIA) is disabled
1
CMFA interrupt request (CMIA) is enabled
φ/2 internal clock source, counted on falling edge
1
0*1 φ/64 internal clock source, counted on falling edge
φ/128 internal clock source, counted on falling edge
1*1 φ/1024 internal clock source, counted on falling edge
Compare-Match Interrupt Enable B
0
CMFB interrupt request (CMIB) is disabled
1
CMFB interrupt request (CMIB) is enabled
φ/2048 internal clock source, counted on falling edge
X
1
0
0
Counted on TCNT0 compare-match A*2
0
0
0
Clock input disabled
1
Counted on φ internal clock source
0
φ/2 internal clock source, counted on falling edge
1
φ/4 internal clock source, counted on falling edge
1
Y
1
0
0
Clock input disabled
0
0
0
Clock input disabled
1
φ/4 internal clock source, counted on falling edge
0
φ/256 internal clock source, counted on falling edge
1
φ/2048 internal clock source, counted on falling edge
1
Common
1
0
0
Clock input disabled
1
0
1
External clock source, counted on rising edge
1
0
External clock source, counted on falling edge
1
External clock source, counted on both rising and
falling edges
Notes: 1. Selected by ICKS1 and ICKS0 in STCR. For details see section 12.2.4,
Timer Control Register (TCR).
2. If the count input of channel 0 is the TCNT1 overflow signal and
that of channel 1 is the TCNT0 compare-match signal, no incrementing
clock will be generated. Do not use this setting.
Rev. 3.00 Mar 17, 2006 page 664 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCSRX—Timer Control/Status Register X
H'FFF1
TMRX
TCSRX
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICF
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
Bit
Output Select 1 and 0
0
1
0
No change when compare-match A occurs
1
0 output when compare-match A occurs
0
1 output when compare-match A occurs
1
Output inverted when compare-match A
occurs (toggle output)
Output Select 3 and 2
0
0
1
0 output when compare-match B occurs
1
0
1 output when compare-match B occurs
1
Output inverted when compare-match B
occurs (toggle output)
No change when compare-match B occurs
Input Capture Flag
0
[Clearing condition]
When 0 is written in ICF after reading ICF = 1
1
[Setting condition]
When a rising edge followed by a falling edge is
detected in the external reset signal after the ICST bit
in TCONRI has been set to 1
Timer Overflow Flag
0
[Clearing condition]
When 0 is written in OVF after reading OVF = 1
1
[Setting condition]
When TCNT overflows from H'FF to H'00
Compare-Match Flag A
0
[Clearing condition]
When 0 is written in CMFA after reading CMFA = 1
1
[Setting condition]
When TCNT = TCORA
Compare-Match Flag B
0
[Clearing condition]
When 0 is written in CMFB after reading CMFB = 1
1
[Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written in bits 7 to 4, to clear the flags.
Rev. 3.00 Mar 17, 2006 page 665 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCSRY—Timer Control/Status Register Y
H'FFF1
TMRY
TCSRY
Bit
7
6
5
4
3
2
1
0
CMFB
CMFA
OVF
ICIE
OS3
OS2
OS1
OS0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/(W)*
R/(W)*
R/(W)*
R/W
R/W
R/W
R/W
R/W
Output Select 1 and 0
0
1
0
No change when compare-match A occurs
1
0 output when compare-match A occurs
0
1 output when compare-match A occurs
1
Output inverted when compare-match A
occurs (toggle output)
Output Select 3 and 2
0
1
0
No change when compare-match B occurs
1
0 output when compare-match B occurs
0
1 output when compare-match B occurs
1
Output inverted when compare-match B
occurs (toggle output)
Input Capture Interrupt Enable
0
ICF interrupt request (ICIX) is disabled
1
ICF interrupt request (ICIX) is enabled
Timer Overflow Flag
0
[Clearing condition]
When 0 is written in OVF after reading OVF = 1
1
[Setting condition]
When TCNT overflows from H'FF to H'00
Compare-Match Flag A
0
[Clearing condition]
When 0 is written in CMFA after reading CMFA = 1
1
[Setting condition]
When TCNT = TCORA
Compare-Match Flag B
0
[Clearing condition]
When 0 is written in CMFB after reading CMFB = 1
1
[Setting condition]
When TCNT = TCORB
Note: * Only 0 can be written in bits 7 to 5, to clear the flags.
Rev. 3.00 Mar 17, 2006 page 666 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TICRR—Input Capture Register R
TICRF—Input Capture Register F
H'FFF2
H'FFF3
TMRX
TMRX
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R
R
R
R
R
R
R
R
Stores TCNT value at fall of external reset input
TCORAY—Time Constant Register AY
TCORBY—Time Constant Register BY
H'FFF2
H'FFF3
TMRY
TMRY
TCORAY, TCORBY
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare-match flag (CMF) is set when TCOR and TCNT values match
TCNTX—Timer Counter X
TCNTY—Timer Counter Y
H'FFF4
H'FFF4
TMRX
TMRY
Bit
7
6
5
4
3
2
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Up-counter
Rev. 3.00 Mar 17, 2006 page 667 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TISR—Timer Input Select Register
Bit
H'FFF5
TMRY
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
IS
Initial value
1
1
1
1
1
1
1
0
Read/Write
—
—
—
—
—
—
—
R/W
Input Select
TCORC—Time Constant Register C
TCORAX—Time Constant Register AX
TCORBX—Time Constant Register BX
0
IVG signal is selected
1
TMIY (TMCIY/TMRIY) is selected
H'FFF5
H'FFF6
H'FFF7
TMRX
TMRX
TMRX
TCORC
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare-match C signal is generated when sum of TCORC and
TICR contents match TCNT value
TCORAX, TCORBX
Bit
7
6
5
4
3
2
1
0
Initial value
1
1
1
1
1
1
1
1
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Compare-match flag (CMF) is set when TCOR and TCNT values match
Rev. 3.00 Mar 17, 2006 page 668 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCONRI—Timer Connection Register I
Bit
7
6
H'FFFC
5
SIMOD1 SIMOD0 SCONE
Timer Connection
4
3
2
1
0
ICST
HFINV
VFINV
HIINV
VIINV
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Input Synchronization
Signal Inversion
0
The VSYNCI pin state
is used directly as the
VSYNCI input
1
The VSYNCI pin state
is inverted before use
as the VSYNCI input
Input Synchronization Signal Inversion
0
The HSYNCI and CSYNCI pin states are used
directly as the HSYNCI and CSYNCI inputs
1
The HSYNCI and CSYNCI pin states are inverted
before use as the HSYNCI and CSYNCI inputs
Input Synchronization Signal Inversion
0
The VFBACKI pin state is used directly as the VFBACKI input
1
The VFBACKI pin state is inverted before use as the VFBACKI input
Input Synchronization Signal Inversion
0
The HFBACKI pin state is used directly as the HFBACKI input
1
The HFBACKI pin state is inverted before use as the HFBACKI input
Input Capture Start Bit
0
The TICRR and TICRF input capture functions are stopped
[Clearing condition]
When a rising edge followed by a falling edge is detected on TMRIX
1
The TICRR and TICRF input capture functions are operating
(Waiting for detection of a rising edge followed by a falling edge on TMRIX)
[Setting condition]
When 1 is written in ICST after reading ICST = 0
Synchronization Signal Connection Enable
SCONE
Mode
FTIA
0
Normal
connection
1
Synchronization IVI
signal connecsignal
tion mode
FTIA
input
FTID
TMCI1
TMRI1
FTIB
input
FTIC
input
FTIC
FTID
input
TMCI1
input
TMRI1
input
TMO1
signal
VFBACKI
input
IHI
signal
IHI
signal
IVI
inverse
signal
FTIB
Input Synchronization Mode Select 1 and 0
SIMOD1
SIMOD0
IHI Signal
IVI Signal
0
0
No signal
HFBACKI input
VFBACKI input
1
S-on-G mode
CSYNCI input
PDC input
0
Composite mode
HSYNCI input
PDC input
1
Separate mode
HSYNCI input
VSYNCI input
1
Mode
Rev. 3.00 Mar 17, 2006 page 669 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCONRO—Timer Connection Register O
Bit
H'FFFD
Timer Connection
7
6
5
4
3
2
HOE
VOE
CLOE
CBOE
HOINV
VOINV
1
0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
CLOINV CBOINV
Output Synchronization
Signal Inversion
0
The CBLANK signal is
used directly as the
CBLANK output
1
The CBLANK signal is
inverted before use as
the CBLANK output
Output Synchronization Signal Inversion
0
The CLO signal (CL1, CL2, CL3,
or CL4 signal) is used directly as
the CLAMPO output
1
The CLO signal (CL1, CL2, CL3,
or CL4 signal) is inverted before
use as the CLAMPO output
Output Synchronization Signal Inversion
0
The IVO signal is used directly as
the VSYNCO output
1
The IVO signal is inverted before
use as the VSYNCO output
Output Synchronization Signal Inversion
0
The IHO signal is used directly as the HSYNCO output
1
The IHO signal is inverted before use as the HSYNCO output
Output Enable
0
[H8/3577 Group] The P27/PW15/CBLANK pin functions as the P27/PW15 pin
[H8/3567 Group] The P15/PW5/CBLANK pin functions as the P15/PW5 pin
1
[H8/3577 Group] The P27/PW15/CBLANK pin functions as the CBLANK pin
[H8/3567 Group] The P15/PW5/CBLANK pin functions as the CBLANK pin
Output Enable
0
The P64/FTIC/TMO0/CLAMPO pin functions as the P64/FTIC/TMO0 pin
1
The P64/FTIC/TMO0/CLAMPO pin functions as the CLAMPO pin
Output Enable
0
The P61/FTOA/VSYNCO pin functions as the P61/FTOA pin
1
The P61/FTOA/VSYNCO pin functions as the VSYNCO pin
Output Enable
0
The P67/TMO1/TMOX/HSYNCO pin functions as the P67/TMO1/TMOX pin
1
The P67/TMO1/TMOX/HSYNCO pin functions as the HSYNCO pin
Rev. 3.00 Mar 17, 2006 page 670 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
TCONRS—Timer Connection Register S
7
Bit
6
TMRX/Y
5
H'FFFE
4
3
Timer Connection
2
1
0
ISGENE HOMOD1 HOMOD0 VOMOD1 VOMOD0 CLMOD1 CLMOD0
Initial value
0
0
0
0
0
0
0
0
Read/Write
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Clamp Waveform Mode Select 1 and 0
ISGENE CLMOD1 CLMOD0
Description
0
0
The CL1 signal is selected
1
The CL2 signal is selected
0
The CL3 signal is selected
0
1
1
0
1
The CL4 signal is selected
0
1
1
0
1
Vertical Synchronization Output Mode Select 1 and 0
ISGENE VOMOD1 VOMOD0
0
0
1
1
0
Description
0
The IVI signal (without fall modification
or IHI synchronization) is selected
1
The IVI signal (without fall modification,
with IHI synchronization) is selected
0
The IVI signal (with fall modification,
without IHI synchronization) is selected
1
The IVI signal (with fall modification and
IHI synchronization) is selected
0
The IVG signal is selected
1
1
0
1
Horizontal Synchronization Output Mode Select 1 and 0
ISGENE HOMOD1 HOMOD0
0
0
1
Description
0
The IHI signal (without 2fH modification) is selected
1
The IHI signal (with 2fH modification) is selected
0
The CL1 signal is selected
1
1
0
0
The IHG signal is selected
1
1
0
1
Internal Synchronization Signal Select
TMRX/TMRY Access Select
0
The TMRX registers are accessed at addresses H'FFF0 to H'FFF5
1
The TMRY registers are accessed at addresses H'FFF0 to H'FFF5
Rev. 3.00 Mar 17, 2006 page 671 of 706
REJ09B0303-0300
Appendix B Internal I/O Registers
SEDGR—Edge Sense Register
Bit
7
6
5
VEDG
HEDG
CEDG
0
0
0
Initial value
Read/Write
H'FFFF
*1
R/(W)
*1
R/(W)
4
R/(W)
2
3
HFEDG VFEDG PREQF
0
*1
Timer Connection
0
*1
R/(W)
0
*1
*1
R/(W)
R/(W)
1
0
IHI
IVI
—*2
—*2
R
R
IVI Signal Level
0
The IVI signal is low
1
The IVI signal is high
IHI Signal Level
0
The IHI signal is low
1
The IHI signal is high
Pre-Equalization Flag
0
[Clearing condition]
When 0 is written in PREQF after
reading PREQF = 1
1
[Setting condition]
When an IHI signal 2fH modification
condition is detected
VFBACKI Edge
0
[Clearing condition]
When 0 is written in VFEDG after reading VFEDG = 1
1
[Setting condition]
When a rising edge is detected on the VFBACKI pin
HFBACKI Edge
0
[Clearing condition]
When 0 is written in HFEDG after reading HFEDG = 1
1
[Setting condition]
When a rising edge is detected on the HFBACKI pin
CSYNCI Edge
0
[Clearing condition]
When 0 is written in CEDG after reading CEDG = 1
1
[Setting condition]
When a rising edge is detected on the CSYNCI pin
HSYNCI Edge
0
[Clearing condition]
When 0 is written in HEDG after reading HEDG = 1
1
[Setting condition]
When a rising edge is detected on the HSYNCI pin
VSYNCI Edge
0
[Clearing condition]
When 0 is written in VEDG after reading VEDG = 1
1
[Setting condition]
When a rising edge is detected on the VSYNCI pin
Notes: 1. Only 0 can be written, to clear the flag.
2. The initial value is undefined since it depends on the pin states.
Rev. 3.00 Mar 17, 2006 page 672 of 706
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Appendix C I/O Port Block Diagrams
Appendix C I/O Port Block Diagrams
C.1
Port 1 Block Diagrams
Reset
*
R
D
Q
P1nPCR
RP1P
C
WP1D
Reset
R
D
Q
P1nDDR
C
WP1D
Internal data bus
Hardware
standby
Reset
P1n
8-bit PWM
PWM output enable
PWM output
R
Q
D
P1nDR
C
WP1
14-bit PWM
PWX0 and PWX1 output
Output enable
RP1
Legend:
WP1D: Write to P1DDR
WP1P: Write to P1PCR
RP1P: Read P1PCR
WP1: Write to port 1
RP1:
Read port 1
Notes: n = 0 or 1
* MOS input pull-up applies to the H8/3577 Group only.
Figure C.1 Port 1 Block Diagram (Pins P10 and P11)
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REJ09B0303-0300
Appendix C I/O Port Block Diagrams
Reset
*
R
D
Q
P1nPCR
RP1P
C
WP1D
Reset
R
D
Q
P1nDDR
C
WP1D
Reset
P1n
Internal data bus
Hardware
standby
8-bit PWM
PWM output enable
PWM output
R
Q
D
P1nDR
C
WP1
RP1
Legend:
WP1D: Write to P1DDR
WP1P: Write to P1PCR
RP1P: Read P1PCR
WP1: Write to port 1
RP1:
Read port 1
Notes: n = 2 to 7
* MOS input pull-up applies to the H8/3577 Group only.
Figure C.2 Port 1 Block Diagram
(Pins P12 to P17 in H8/3577 Group, Pins P12 to P14 in H8/3567 Group)
Rev. 3.00 Mar 17, 2006 page 674 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P15DDR
C
WP1D
Reset
P15
Internal data bus
Appendix C I/O Port Block Diagrams
8-bit PWM
PWM output enable
PWM output
R
Q
D
P15DR
C
WP1
Timer connection
CBLANK
CBLANK output enable
RP1
Legend:
WP1D: Write to P1DDR
WP1: Write to port 1
RP1:
Read port 1
Figure C.3 Port 1 Block Diagram (Pin P15 in H8/3567 Group)
Rev. 3.00 Mar 17, 2006 page 675 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P16DDR
C
WP1D
*1
Reset
P16
R
Q
D
P16DR
C
*2
WP1
Internal data bus
Appendix C I/O Port Block Diagrams
8-bit PWM
PWM output enable
PWM output
IIC1
SDA1 output
Transmit enable
RP1
SDA1 input
Legend:
WP1D: Write to P1DDR
WP1: Write to port 1
RP1:
Read port 1
Notes: 1. Output enable signal
2. Open drain control signal
Figure C.4 Port 1 Block Diagram (Pin P16 in H8/3567 Group)
Rev. 3.00 Mar 17, 2006 page 676 of 706
REJ09B0303-0300
Hardware
standby
Mode 1
Reset
S R
D
Q
P17DDR
C
WP1D
*1
Reset
P17
R
Q
D
P17DR
C
*2
WP1
Internal data bus
Appendix C I/O Port Block Diagrams
8-bit PWM
PWM output enable
PWM output
IIC1
SCL1 output
Transmit enable
RP1
SCL1 input
Legend:
WP1D: Write to P1DDR
WP1: Write to port 1
RP1:
Read port 1
Notes: 1. Output enable signal
2. Open drain control signal
Figure C.5 Port 1 Block Diagram (Pin P17 in H8/3567 Group)
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Appendix C I/O Port Block Diagrams
C.2
Port 2 Block Diagrams
Port 2 is provided only in the H8/3577 Group, and not in the H8/3567 Group.
Reset
Hardware
standby
WP2D
Reset
R
D
Q
P2nDDR
C
WP2D
Reset
P2n
Internal data bus
R
D
Q
P2nPCR
RP2P
C
8-bit PWM
PWM output enable
PWM output
R
Q
D
P2nDR
C
WP2
RP2
Legend:
WP2D: Write to P2DDR
WP2P: Write to P2PCR
RP2P: Read P2PCR
WP2: Write to port 2
RP2:
Read port 2
Note: n = 0 to 2, 5, 6
Figure C.6 Port 2 Block Diagram (Pins P20 to P22, P25, and P26 in H8/3577 Group)
Rev. 3.00 Mar 17, 2006 page 678 of 706
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Appendix C I/O Port Block Diagrams
Reset
Hardware
standby
WP2D
Reset
R
D
Q
P23DDR
C
WP2D
*1
Reset
P23
R
Q
D
P23DR
C
*2
WP2
Internal data bus
R
D
Q
P23PCR
RP2P
C
8-bit PWM
PWM output enable
PWM output
IIC1
SDA1 output
Transmit enable
RP2
SDA1 input
Legend:
WP2D: Write to P2DDR
WP2P: Write to P2PCR
RP2P: Read P2PCR
WP2: Write to port 2
RP2:
Read port 2
Notes: 1. Output enable signal
2. Open drain control signal
Figure C.7 Port 2 Block Diagram (Pin P23 in H8/3577 Group)
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Appendix C I/O Port Block Diagrams
Reset
Hardware
standby
WP2D
Reset
R
D
Q
P24DDR
C
WP2D
*1
Reset
P24
R
Q
D
P24DR
C
*2
WP2
Internal data bus
R
D
Q
P24PCR
RP2P
C
8-bit PWM
PWM output enable
PWM output
IIC1
SCL1 output
Transmit enable
RP2
SCL1 input
Legend:
WP2D: Write to P2DDR
WP2P: Write to P2PCR
RP2P: Read P2PCR
WP2: Write to port 2
RP2:
Read port 2
Notes: 1. Output enable signal
2. Open drain control signal
Figure C.8 Port 2 Block Diagram (Pin P24 in H8/3577 Group)
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REJ09B0303-0300
Appendix C I/O Port Block Diagrams
Reset
R
D
Q
P27PCR
C
RP2P
Reset
R
D
Q
P27DDR
C
WP2D
P27
Reset
Internal data bus
WP2D
Hardware
standby
8-bit PWM
PWM output enable
PWM output
R
Q
D
P27DR
C
WP2
Timer connection
CBLANK
CBLANK output enable
RP2
Legend:
WP2D: Write to P2DDR
WP2P: Write to P2PCR
RP2P: Read P2PCR
WP2: Write to port 2
RP2:
Read port 2
Figure C.9 Port 2 Block Diagram (Pin P27 in H8/3577 Group)
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Appendix C I/O Port Block Diagrams
C.3
Port 3 Block Diagram
Port 3 is provided only in the H8/3577 Group, and not in the H8/3567 Group.
Reset
R
D
Q
P3nPCR
RP3P
C
Reset
R
D
Q
P3nDDR
C
WP3D
Internal data bus
WP3D
Hardware
standby
Reset
R
Q
D
P3nDR
C
P3n
WP3
RP3
Legend:
WP3D: Write to P3DDR
WP3P: Write to P3PCR
RP3P: Read P3PCR
WP3: Write to port 3
RP3:
Read port 3
Note: n = 0 to 7
Figure C.10 Port 3 Block Diagram (Pins P30 to P37 in H8/3577 Group)
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Appendix C I/O Port Block Diagrams
Port 4 Block Diagrams
Hardware
standby
Reset
R
D
Q
P40DDR
C
WP4D
Internal data bus
C.4
Reset
R
Q
D
P40DR
C
P40
WP4
RP4
A/D converter
External trigger input
IRQ2 input
Legend:
WP4D: Write to P4DDR
WP4: Write to port 4
RP4:
Read port 4
Figure C.11 Port 4 Block Diagram (Pin P40)
Rev. 3.00 Mar 17, 2006 page 683 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P4nDDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
WP4D
Reset
R
Q
D
P4nDR
C
P4n
WP4
RP4
IRQ1 input
IRQ0 input
Legend:
WP4D: Write to P4DDR
WP4: Write to port 4
RP4:
Read port 4
Note: n = 1 or 2
Figure C.12 Port 4 Block Diagram (Pins P41 and P42)
Rev. 3.00 Mar 17, 2006 page 684 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P4nDDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
WP4D
Reset
R
Q
D
P4nDR
C
P4n
WP4
RP4
Legend:
WP4D: Write to P4DDR
WP4: Write to port 4
RP4:
Read port 4
Note: n = 3 to 5
Figure C.13 Port 4 Block Diagram (Pins P43 to P45)
Rev. 3.00 Mar 17, 2006 page 685 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P46DDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
WP4D
φ output
P46
RP4
Legend:
WP4D: Write to P4DDR
RP4:
Read port 4
Figure C.14 Port 4 Block Diagram (Pin P46)
Rev. 3.00 Mar 17, 2006 page 686 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P47DDR
C
WP4D
Internal data bus
Appendix C I/O Port Block Diagrams
Reset
*1
R
Q
D
P47DR
C
P47
*2
WP4
IIC0
SDA0 output
Transmit enable
RP4
SDA0 input
Legend:
WP4D: Write to P4DDR
WP4: Write to port 4
RP4:
Read port 4
Notes: 1. Output enable signal
2. Open drain control signal
Figure C.15 Port 4 Block Diagram (Pin P47)
Rev. 3.00 Mar 17, 2006 page 687 of 706
REJ09B0303-0300
Appendix C I/O Port Block Diagrams
Port 5 Block Diagrams
Hardware
standby
Reset
R
D
Q
P50DDR
C
WP5D
Internal data bus
C.5
SCI0
Serial transmit data
Output enable
P50
Reset
R
Q
D
P50DR
C
WP5
RP5
Legend:
WP5D: Write to P5DDR
WP5: Write to port 5
RP5:
Read port 5
Figure C.16 Port 5 Block Diagram (Pin P50)
Rev. 3.00 Mar 17, 2006 page 688 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P51DDR
C
Internal data bus
Appendix C I/O Port Block Diagrams
WP5D
SCI0
Input enable
Reset
R
Q
D
P51DR
C
P51
WP5
RP5
Serial receive data
Legend:
WP5D: Write to P5DDR
WP5: Write to port 5
RP5:
Read port 5
Figure C.17 Port 5 Block Diagram (Pin P51)
Rev. 3.00 Mar 17, 2006 page 689 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P52DDR
C
WP5D
*1
Reset
R
Q
D
P52DR
C
P52
*2
WP5
Internal data bus
Appendix C I/O Port Block Diagrams
SCI0
Input enable
Clock output
Output enable
Clock input
IIC0
SCL0 output
Transmit enable
RP5
SCL0 input
Legend:
WP5D: Write to P5DDR
WP5: Write to port 5
RP5:
Read port 5
Notes: 1. Output enable signal
2. Open drain control signal
Figure C.18 Port 5 Block Diagram (Pin P52)
Rev. 3.00 Mar 17, 2006 page 690 of 706
REJ09B0303-0300
Appendix C I/O Port Block Diagrams
Port 6 Block Diagrams
Hardware
standby
Reset
R
D
Q
P6nDDR
C
WP6D
Internal data bus
C.6
Reset
R
Q
D
P6nDR
C
P6n
WP6
RP6
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6:
Read port 6
16-bit FRT
FTCI input
FTIA input
FTIB input
FTID input
Timer connection
8-bit timers 0 and 1
8-bit timers Y and X
HFBACKI input, TMCI0 input
TMIX input, VSYNCI input
TMIY input, VFBACKI input
TMRI0 input, HSYNCI input
TMCI1 input
Note: n = 0, 2, 3, 5
Figure C.19 Port 6 Block Diagram (Pins P60, P62, P63, and P65)
Rev. 3.00 Mar 17, 2006 page 691 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P61DDR
C
WP6D
Internal data bus
Appendix C I/O Port Block Diagrams
16-bit FRT
FTOA output
Output enable
Reset
R
Q
D
P61DR
C
P61
WP6
RP6
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6:
Read port 6
Figure C.20 Port 6 Block Diagram (Pin P61)
Rev. 3.00 Mar 17, 2006 page 692 of 706
REJ09B0303-0300
Timer connection
VSYNCO output
Output enable
Hardware
standby
Reset
R
D
Q
P64DDR
C
WP6D
Internal data bus
Appendix C I/O Port Block Diagrams
Timer connection
CLAMPO output
Output enable
Reset
R
Q
D
P64DR
C
P64
WP6
8-bit timer 0
TMO0 output
Output enable
RP6
16-bit FRT
FTIC input
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6:
Read port 6
Figure C.21 Port 6 Block Diagram (Pin P64)
Rev. 3.00 Mar 17, 2006 page 693 of 706
REJ09B0303-0300
Hardware
standby
Reset
R
D
Q
P66DDR
C
WP6D
Internal data bus
Appendix C I/O Port Block Diagrams
16-bit FRT
FTOB output
Output enable
Reset
P66
R
Q
D
P66DR
C
WP6
RP6
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6:
Read port 6
Figure C.22 Port 6 Block Diagram (Pin P66)
Rev. 3.00 Mar 17, 2006 page 694 of 706
REJ09B0303-0300
8-bit timer 1
timer connection
TMRI1 input
CSYNCI input
Hardware
standby
Reset
R
D
Q
P67DDR
C
WP6D
Internal data bus
Appendix C I/O Port Block Diagrams
8-bit timer X
TMOX output
Output enable
Reset
R
Q
D
P67DR
C
P67
WP6
8-bit timer 1
TMO1 output
Output enable
Timer connection
HSYNCO output
Output enable
RP6
Legend:
WP6D: Write to P6DDR
WP6: Write to port 6
RP6:
Read port 6
Figure C.23 Port 6 Block Diagram (Pin P67)
Rev. 3.00 Mar 17, 2006 page 695 of 706
REJ09B0303-0300
Appendix C I/O Port Block Diagrams
C.7
Port 7 Block Diagram
RP7
P7n
Internal data bus
The H8/3577 Group has an 8-bit input port (pins P70 to P77) and the H8/3567 Group has a 4-bit
input port (pins P70 to P73).
A/D converter
Analog input
Legend:
RP7: Read port 7
Note: n = 0 to 7
Figure C.24 Port 7 Block Diagram
(Pins P70 to P77 in H8/3577 Group, Pins P70 to P73 in H8/3567 Group)
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Appendix C I/O Port Block Diagrams
C.8
Port 8 Block Diagrams
Port C is provided only in the H8/3567 Group version with an on-chip USB.
Hardware
standby
Reset
R
D
Q
PCnDDR
C
Internal data bus
RPCO
WPCD
Reset
R
Q
D
PCnODR
C
PCn
WPC
USB
ENP output
Output enable
RPC
Legend:
WPCD: Write to PCDDR
WPC: Write to port C
RPC: Read port C
RPCO: Read to ODR
Note: n = 0 to 3
Figure C.25 Port C Block Diagram
(Pins PC0 to PC3 in H8/3567 Group Version with On-Chip USB)
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Appendix C I/O Port Block Diagrams
Hardware
standby
Reset
R
D
Q
PCnDDR
C
WPCD
Internal data bus
RPCO
Reset
R
Q
D
PCnODR
C
PCn
WPC
RPC
USB
OCP input
Input enable
Legend:
WPCD: Write to PCDDR
WPC: Write to port C
RPC:
Read port C
RPCO: Read to ODR
Note: n = 4 to 7
Figure C.26 Port C Block Diagram
(Pins PC4 to PC7 in H8/3567 Group Version with On-Chip USB)
Rev. 3.00 Mar 17, 2006 page 698 of 706
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Appendix C I/O Port Block Diagrams
C.9
Port D Block Diagram
Port D is provided only in the H8/3567 Group version with an on-chip USB.
USB
FONLY bit
Hardware
standby
Reset
R
D
Q
PDnDDR
C
Internal data bus
RPDO
WPDD
Reset
R
Q
D
PDnODR
C
PDn
WPD
RPC
DSmD+/DSMDLegend:
WPDD: Write to PDDDR
WPD: Write to port D
RPD:
Read port D
RPDO: Read to ODR
USB bus
driver/
receiver
Note: n = 0 to 7
m = 2 to 5
Figure C.27 Port D Block Diagram
(Pins PD0 to PD7 in H8/3567 Group Version with On-Chip USB)
Rev. 3.00 Mar 17, 2006 page 699 of 706
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Appendix D Pin States
Appendix D Pin States
D.1
Port States in Each Mode
Table D.1
I/O Port States in Each Processing State
Port Name
Pin Name
Reset
Hardware
Standby Mode
Software
Standby Mode
Program Execution State
Port 1
T
T
kept
I/O port
Port 2
T
T
kept
I/O port
Port 3
T
T
kept
I/O port
Port 47
T
T
kept
I/O port
Port 46
T
T
[DDR = 1] H
Clock output/input port
[DDR = 0] T
Port 45 to 40
T
T
kept
I/O port
Port 5
T
T
kept
I/O port
Port 6
T
T
kept
I/O port
Port 7
T
T
T
Input port
Port C
T
T
Functioning
(HOCnE = 1)
USB input/output
I/O port
kept (HOCnE = 0)
Port D
T
T
Functioning
(FONLY = 0)
USB input/output
I/O port
kept (FONLY = 1)
Legend:
H:
High level
L:
Low level
T:
High impedance
kept:
Input pins are in the high-impedance state (when DDR = 0 and PCR = 1, MOS input pullups remain in the on state).
Output ports retain their state.
In some cases, the on-chip supporting module is initialized and the pin is an input/output
port, determined by the DDR and DR settings.
DDR: Data direction register
HOCnE: HOCnE bit in HOCCR of USB
FONLY: FONLY bit in USBCR of USB
Note: n = 2 to 5
Rev. 3.00 Mar 17, 2006 page 700 of 706
REJ09B0303-0300
Appendix E Timing of Transition to and Recovery from Hardware Standby Mode
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
E.1
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents when the RAME bit in SYSCR is set to 1, drive the RES signal low
10 system clock cycles before the STBY signal goes low, as shown in figure E.1. RES must
remain low until STBY goes low (minimum delay from STBY low to RES high: 0 ns).
STBY
t1 ≥ 10tcyc
t2 ≥ 0 ns
RES
Figure E.1 Timing of Transition to Hardware Standby Mode
(2) When the RAME bit in SYSCR is cleared to 0 or when it is not necessary to retain RAM
contents, RES does not have to be driven low as in (1).
E.2
Timing of Recovery from Hardware Standby Mode
Drive the RES signal low approximately 100 ns or more before STBY goes high.
STBY
t ≥ 100 ns
tOSC
RES
Figure E.2 Timing of Recovery from Hardware Standby Mode
Rev. 3.00 Mar 17, 2006 page 701 of 706
REJ09B0303-0300
Appendix F Product Code Lineup
Appendix F Product Code Lineup
Table F.1
H8/3577 Group and H8/3567 Group Product Code Lineup
Product Type
H8/3577 H8/3577
Group
ZTAT version
Mask ROM version
H8/3574
H8/3567 H8/3567
Group
H8/3564
Product
Code
Mark Code
Package
(Package Code)
HD6473577
HD6473577P20
64-pin shrink DIP (DP-64S)
HD6476577F20
64-pin QFP (FP-64A)
HD6433577
HD6433577(***)P20
64-pin shrink DIP (DP-64S)
HD6433577(***)F20
64-pin QFP (FP-64A)
64-pin shrink DIP (DP-64S)
Mask ROM version
HD6433574
HD6433574(***)P20
HD6433574(***)F20
64-pin QFP (FP-64A)
ZTAT version
HD6473567
HD6473567P20
42-pin shrink DIP (DP-42S)
Mask ROM version
HD6433567
Mask ROM version
HD6433564
(10 MHz limit version)
H8/3567U ZTAT version
(on-chip USB)
HD6476567F20
44-pin QFP (FP-44A)
HD6433567(***)P20
42-pin shrink DIP (DP-42S)
HD6433567(***)F20
44-pin QFP (FP-44A)
HD6433564(***)P20
42-pin shrink DIP (DP-42S)
HD6433564(***)F20
44-pin QFP (FP-44A)
HD6433564(***)P10
HD6473567U HD6473567UP20
HD6473567UF20
42-pin shrink DIP (DP-42S)
64-pin shrink DIP (DP-64S)
64-pin QFP (FP-64A)
Mask ROM version
(on-chip USB)
HD6433567U HD6433567U(***)P20 64-pin shrink DIP (DP-64S)
H8/3564U Mask ROM version
(on-chip USB)
HD6433564U HD6433564U(***)P20 64-pin shrink DIP (DP-64S)
HD6433567U(***)F20 64-pin QFP (FP-64A)
HD6433564U(***)F20 64-pin QFP (FP-64A)
Note: (***) is the ROM code.
When ordering, the frequency selection (20 or 10) is not indicated by the model name, but
is identified by the ROM code.
Rev. 3.00 Mar 17, 2006 page 702 of 706
REJ09B0303-0300
Appendix G Package Dimensions
Appendix G Package Dimensions
Figures G.1 to G.4 show package dimensions of H8/3577 Group and H8/3567 Group.
JEITA Package Code
P-SDIP64-17x57.6-1.78
RENESAS Code
PRDP0064BB-A
Previous Code
DP-64S/DP-64SV
MASS[Typ.]
8.8g
D
33
E
64
1
32
b3
Reference Dimension in Millimeters
Symbol
Min
L
A1
A
Z
e
bp
θ
c
e1
e1
D
E
A
A1
bp
b3
c
θ
e
Z
L
Nom Max
19.05
57.6 58.5
17.0 18.6
5.08
0.51
0.38 0.48 0.58
1.0
0.20 0.25 0.36
0°
15°
1.53 1.78 2.03
1.46
2.54
Figure G.1 DP-64S Package Dimensions
Rev. 3.00 Mar 17, 2006 page 703 of 706
REJ09B0303-0300
Appendix G Package Dimensions
JEITA Package Code
P-QFP64-14x14-0.80
RENESAS Code
PRQP0064GB-A
Previous Code
FP-64A/FP-64AV
MASS[Typ.]
1.2g
HD
*1
D
48
33
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
32
49
bp
c
c1
HE
*2
E
b1
Reference Dimension in Millimeters
Symbol
Terminal cross section
ZE
Min
17
64
16
c
F
A
ZD
A2
1
θ
A1
L
L1
Detail F
e
*3
y
bp
x
M
Figure G.2 FP-64A Package Dimensions
Rev. 3.00 Mar 17, 2006 page 704 of 706
REJ09B0303-0300
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
14
14
2.70
16.9 17.2 17.5
16.9 17.2 17.5
3.05
0.00 0.10 0.25
0.29 0.37 0.45
0.35
0.12 0.17 0.22
0.15
0°
8°
0.8
0.15
0.10
1.0
1.0
0.5 0.8 1.1
1.6
Appendix G Package Dimensions
JEITA Package Code
P-SDIP42-14x37.3-1.78
RENESAS Code
PRDP0042BB-A
Previous Code
DP-42S/DP-42SV
MASS[Typ.]
4.8g
D
22
E
42
1
21
b3
A
Reference Dimension in Millimeters
Symbol
Min
L
A1
Z
e
bp
θ
c
e1
e1
D
E
A
A1
bp
b3
c
θ
e
Z
L
Nom Max
15.24
37.3 38.6
14.0 14.6
5.10
0.51
0.38 0.48 0.58
1.0
0.20 0.25 0.35
0°
15°
1.53 1.78 2.03
1.38
2.54
Figure G.3 DP-42S Package Dimensions
Rev. 3.00 Mar 17, 2006 page 705 of 706
REJ09B0303-0300
Appendix G Package Dimensions
JEITA Package Code
P-QFP44-14x14-0.80
RENESAS Code
PRQP0044GC-A
Previous Code
FP-44A/FP-44AV
MASS[Typ.]
1.2g
HD
*1
D
33
23
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
34
bp
22
c
c1
HE
*2
E
b1
Reference Dimension in Millimeters
Symbol
Terminal cross section
12
44
ZE
Min
c
F
A2
11
A
1
ZD
θ
A1
L
L1
Detail F
e
*3
bp
x
M
y
Figure G.4 FP-44A Package Dimensions
Rev. 3.00 Mar 17, 2006 page 706 of 706
REJ09B0303-0300
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
14
14
2.70
16.9 17.2 17.5
16.9 17.2 17.5
3.05
0.00 0.10 0.25
0.29 0.37 0.45
0.35
0.12 0.17 0.22
0.15
0°
8°
0.8
0.15
0.10
3.0
3.0
0.5 0.8 1.1
1.6
Renesas 8-Bit Single-Chip Microcomputer
Hardware Manual
H8/3577 Group, H8/3567 Group
Publication Date: 1st Edition, September 1999
Rev.3.00, March 17, 2006
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
RENESAS SALES OFFICES
http://www.renesas.com
Refer to "http://www.renesas.com/en/network" for the latest and detailed information.
Renesas Technology America, Inc.
450 Holger Way, San Jose, CA 95134-1368, U.S.A
Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501
Renesas Technology Europe Limited
Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900
Renesas Technology (Shanghai) Co., Ltd.
Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120
Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898
Renesas Technology Hong Kong Ltd.
7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong
Tel: <852> 2265-6688, Fax: <852> 2730-6071
Renesas Technology Taiwan Co., Ltd.
10th Floor, No.99, Fushing North Road, Taipei, Taiwan
Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999
Renesas Technology Singapore Pte. Ltd.
1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632
Tel: <65> 6213-0200, Fax: <65> 6278-8001
Renesas Technology Korea Co., Ltd.
Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea
Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
Renesas Technology Malaysia Sdn. Bhd
Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia
Tel: <603> 7955-9390, Fax: <603> 7955-9510
Colophon 6.0
H8/3577 Group, H8/3567 Group
Hardware Manual
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