TI1 ONET8521T 11.3 gbps limiting transimpedance amplifier with rssi Datasheet

ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
11.3 Gbps Limiting Transimpedance Amplifier With RSSI
Check for Samples: ONET8521T
FEATURES
1
•
•
•
•
•
•
•
•
•
9 GHz Bandwidth
2.4 kΩ Differential Small Signal
Transimpedance
-20dBm Sensitivity
0.95 µARMS Input Referred Noise
2.5 mAPP Input Overload Current
Received Signal Strength Indication (RSSI)
90 mW Typical Power Dissipation
CML Data Outputs with On-Chip 50Ω
Back-Termination
On Chip Supply Filter Capacitor
•
•
Single 3.3 V Supply
Die Size: 870 µm × 1036 μm
APPLICATIONS
•
•
•
•
•
•
•
10G Ethernet
8G and 10G Fibre Channel
10G EPON
SONET OC-192
6G CPRI and OBSAI
PIN Preamplifier Receivers
APD Preamplifier Receivers
DESCRIPTION
The ONET8521T is a high-speed, limiting transimpedance amplifier used in optical receivers with data rates up
to 11.3Gbps. It features low input referred noise, 9GHz bandwidth, 2.4kΩ small signal transimpedance, and a
received signal strength indicator (RSSI).
The ONET8521T is available in die form, includes an on-chip VCC bypass capacitor and is optimized for
packaging in a TO can.
The ONET8521T requires a single 3.3V ±10% supply and its power efficient design typically dissipates less than
90mW. The device is characterized for operation from –40°C to 100°C case (IC back side) temperature.
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2011, Texas Instruments Incorporated
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
BLOCK DIAGRAM
A simplified block diagram of the ONET8521T is shown in Figure 1.
The ONET8521T consists of the signal path, supply filters, a control block for dc input bias, automatic gain
control (AGC) and received signal strength indication (RSSI). The RSSI provides the bias for the TIA stage and
the control for the AGC.
The signal path consists of a transimpedance amplifier stage, a voltage amplifier, and a CML output buffer. The
on-chip filter circuit provides a filtered VCC for the PIN photodiode and for the transimpedance amplifier.
The dc input bias circuit and automatic gain control use internal low pass filters to cancel the dc current on the
input and to adjust the transimpedance amplifier gain. Furthermore, circuitry is provided to monitor the received
signal strength.
VCC_OUT
To Voltage Amplifier and Output Buffer
To TIA
VCC_IN
GND
220 W
FILTER1/2
RSSI_IB
AGC and DC
Offset
Cancellation
RF
OUT+
IN
OUTTIA
Voltage Amplifier
CML Output Buffer
RSSI_EB
Figure 1. Simplified Block Diagram of the ONET8521T
2
Copyright © 2011, Texas Instruments Incorporated
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
BOND PAD ASSIGNMENT
GND
GND
The ONET8521T is available in die form. The locations of the bondpads are shown in Figure 2.
18 17 8541T
L
2
15
OUT–
GND
3
14
GND
VCC_OUT
4
13
RSSI_EB
VCC_IN
5
12
RSSI_IB
7
8
9
10 11
NC
6
GND
OUT+
FILTER2
GND
IN
16
FILTER1
1
GND
GND
Figure 2. Bond Pad Assignment of ONET8521T
PIN FUNCTIONS
PIN
NAME
NO.
GND
1, 3, 6, 10
14, 16 – 18
OUT+
TYPE
DESCRIPTION
Supply
Circuit ground. All GND pads are connected on die. Bonding all pads is optional; however, for
optimum performance a good ground connection is mandatory.
2
Analog
output
Non-inverted CML data output. On-chip 50Ω back-terminated to VCC.
VCC_OUT
4
Supply
2.97V–3.63V supply voltage for the voltage and CML amplifiers.
VCC_IN
5
Supply
2.97V–3.63V supply voltage for input TIA stage.
FILTER
7, 9
Analog
Bias voltage for photodiode cathode. These pads are internally connected to an 220Ω resistor to
VCC and a filter capacitor to ground (GND).
IN
8
Analog input Data input to TIA (photodiode anode).
NC
11
No Connect Do not connect
12
Analog
output
Analog output current proportional to the input data amplitude. Indicates the strength of the
received signal (RSSI) if the photo diode is biased from the TIA. Connected to an external resistor
to ground (GND). For proper operation, ensure that the voltage at the RSSI pad does not exceed
VCC – 0.65V. If the RSSI feature is not used this pad should be left open.
RSSI_EB
13
Analog
output
Optional use when operated with external PD bias (e.g. APD). Analog output current proportional
to the input data amplitude. Indicates the strength of the received signal (RSSI).Connected to an
external resistor to ground (GND). For proper operation, ensure that the voltage at the RSSI pad
does not exceed VCC – 0.65V. If the RSSI feature is not used this pad should be left open.
OUT–
15
Analog
output
Inverted CML data output. On-chip 50Ω back-terminated to VCC.
RSSI_IB
Copyright © 2011, Texas Instruments Incorporated
3
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted) (1)
(2)
MIN
MAX
UNIT
–0.3
4.0
V
VCC_IN,
VCC_OUT
Supply voltage
VFILTER1,
VFILTER2,
VOUT+, VOUT–,
VRSSI_IB,
VRSSI_EB
Voltage at FILTER1, FILTER2, OUT+, OUT–, RSSI_IB, RSSI_EB (2)
–0.3
4.0
V
IIN
Current into IN
–0.7
3.5
mA
IFILTER
Current into FILTER1, FILTER2
–8
8
mA
IOUT+, IOUT-
Continuous current at outputs
–8
8
ESD rating at all pins except input IN
2
ESD
TJ,max
(1)
(2)
ESD rating at input IN
mA
kV (HBM)
0.5
Maximum junction temperature
kV(HBM)
°C
125
Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
All voltage values are with respect to network ground terminal.
RECOMMENDED OPERATING CONDITIONS
MIN
NOM
MAX
VCC
Supply voltage
PARAMETER
2.97
3.3
3.63
V
TA
Operating backside die temperature
–40
100 (1)
°C
LFILTER,
LIN
Wire-bond inductor at pins FILTER and IN
0.3
0.5
nH
CPD
Photodiode capacitance
0.2
(1)
CONDITIONS
UNIT
pF
105°C maximum junction temperature
DC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted). Typical values are at VCC = 3.3 V and TA = 25°C
PARAMETER
VCC
IVCC
Supply current
VIN
Input bias voltage
ROUT
Output resistance
RFILTER
Photodiode filter resistance
(1)
4
TEST CONDITIONS
Supply voltage
MIN
TYP
MAX
UNIT
2.97
3.3
3.63
V
27
(1)
Input current iIN < 1000 μAPP
0.75
Single-ended to VCC
40
45 (1)
Input current iIN < 2500 μAPP
40
mA
0.85
0.98
V
50
60
Ω
220
Ω
Including RSSI current
Copyright © 2011, Texas Instruments Incorporated
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
AC ELECTRICAL CHARACTERISTICS
over recommended operating conditions (unless otherwise noted). Typical values are at VCC = +3.3 V and TA = 25°C
PARAMETER
Small signal
transimpedance
Z21
TEST CONDITIONS
Differential output; Input current iIN = 20 μAPP
(1)
fHSS,3dB
Small signal bandwidth
iIN = 16 μAPP
fL,3dB
Low frequency –3 dB
bandwidth
16 μA < iIN < 2000 μAPP
iN,IN
Input referred RMS noise
SUS
Unstressed sensitivity
DJ
Deterministic jitter
DJOL
Overload deterministic jitter
MIN
TYP
1500
2400
7
MAX
Ω
9
GHz
30
100
10 GHz bandwidth (2)
0.95
1.4
10.3125 Gbps, PRBS31 pattern, 1310 nm, BER 10–12
–20
kHz
μA
dBm
25 μAPP < iIN < 500 μAPP (10.3125 Gbps, K28.5 pattern)
6
12
500 μAPP < iIN < 2000 μAPP (10.3125 Gbps, K28.5 pattern)
6
14
2000 μAPP < iIN < 2500 μAPP (10.3125 Gbps, K28.5 pattern)
UNIT
psPP
7
16
psPP
VOUT,D,MAX Maximum differential output
voltage
Input current iIN = 500 μAPP
180
300
420
mVPP
ARSSI_IB
Resistive load to GND (3)
0.48
0.5
0.52
A/A
2
7
16
μA
0.6
A/A
RSSI gain internal bias
RSSI internal bias output
offset current (no light) (4)
ARSSI_EB
RSSI gain external bias
Resistive load to GND (3)
RSSI external bias output
offset current (no light)
PSNR
(1)
(2)
(3)
(4)
(5)
Power supply noise
rejection
F < 10 MHz (5), Supply filtering according to SFF8431
0.43
25
μA
–15
dB
The small signal bandwidth is specified over process corners, temperature, and supply voltage variation. The assumed photodiode
capacitance is 0.2 pF and the bond-wire inductance is 0.3 nH. The small signal bandwidth strongly depends on environmental parasitics.
Careful attention to layout parasitics and external components is necessary to achieve optimal performance.
Input referred RMS noise is (RMS output noise)/ (gain at 100 MHz).
The RSSI output is a current output, which requires a resistive load to ground (GND). The voltage gain can be adjusted for the intended
application by choosing the external resistor; however, for proper operation, ensure that the voltage at RSSI does not exceed
VCC – 0.65V.
Offset is added to improve accuracy below 5μA. When measured without input current (no light) the offset can be subtracted as a
constant offset from RSSI measurements.
PSNR is the differential output amplitude divided by the voltage ripple on supply; no input current at IN.
Copyright © 2011, Texas Instruments Incorporated
5
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
DETAILED DESCRIPTION
SIGNAL PATH
The first stage of the signal path is a transimpedance amplifier which converts the photodiode current into a
voltage. If the input signal current exceeds a certain value, the transimpedance gain is reduced by means of a
nonlinear AGC circuit to limit the signal amplitude.
The second stage is a limiting voltage amplifier that provides additional limiting gain and converts the single
ended input voltage into a differential data signal. The output stage provides CML outputs with an on-chip 50Ω
back-termination to VCC.
FILTER CIRCUITRY
The FILTER pins provide a filtered VCC for a PIN photodiode bias. The on-chip low pass filter for the photodiode
is implemented using a filter resistor of 220Ω and a capacitor. The corresponding corner frequency is below
5MHz. The supply voltages for the transimpedance amplifier are filtered by means of on-chip capacitors, thus
avoiding the necessity to use an external supply filter capacitor. The input stage has a separate VCC supply
(VCC_IN) which is not connected on chip to the supply of the limiting and CML stages (VCC_OUT).
AGC AND RSSI
The voltage drop across the internal photodiode supply-filter resistor is monitored by the bias and RSSI control
circuit block in the case where a PIN diode is biased using the FILTER pins.
If the dc input current exceeds a certain level then it is partially cancelled by means of a controlled current
source. This keeps the transimpedance amplifier stage within sufficient operating limits for optimum performance.
The automatic gain control circuitry adjusts the voltage gain of the AGC amplifier to ensure limiting behavior of
the complete amplifier.
Finally this circuit block senses the current through the filter resistor and generates a mirrored current that is
proportional to the input signal strength. The mirrored current is available at the RSSI_IB output and can be sunk
to ground (GND) using an external resistor. For proper operation, ensure that the voltage at the RSSI_IB pad
does not exceed VCC – 0.65V.
If an APD or PIN photodiode is used with an external bias then the RSSI_EB pin should be used. However, for
greater accuracy under external photo diode biasing conditions, it is recommended to derive the RSSI from the
external bias circuitry.
6
Copyright © 2011, Texas Instruments Incorporated
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
TYPICAL OPERATION CHARACTERISTICS
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
SMALL SIGNAL TRANSIMPENDANCE
vs
AMBIENT TEMPERATURE
2.5
5000
2.0
4000
Transimpedance - W
Transimpedance - kW
TRANSIMPEDANCE
vs
INPUT CURRENT
1.5
1.0
0.5
3000
2000
1000
0
0
200
400
600
800
IIN - Input Current - mAPP
0
-40
1000
-20
0
20
40
60
80
TA - Ambient Temperature - °C
Figure 3.
Figure 4.
SMALL SIGNAL TRANSFER
CHARACTERISTICS
SMALL SIGNAL BANDWIDTH
vs
AMBIENT TEMPERATURE
100
14
6
3
12
0
10
Bandwidth - GHz
Gain - dB
-3
-6
-9
-12
8
6
4
-15
2
-18
-21
0.1
1
10
f - Frequency - GHz
Figure 5.
Copyright © 2011, Texas Instruments Incorporated
100
0
-40
-20
0
20
40
60
80
TA - Ambient Temperature - °C
100
Figure 6.
7
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
OUTPUT VOLTAGE
vs
INPUT CURRENT
DETERMINISTIC JITTER
vs
INPUT CURRENT
10
250
8
Deterministic Jitter - ps
Differential Output Voltage - mVPP
300
200
150
100
0
0
200
400
600
800
IIN - Input Current - mAPP
1000
0
200 400 600 800 1000 1200 1400 1600 1800 2000
IIN - Input Current - mAPP
Figure 7.
Figure 8.
INPUT REFERRED NOISE
vs
TEMPERATURE
RSSI_IB OUTPUT CURRENT
vs
AVERAGE INPUT CURRENT
2.00
1000
900
1.75
800
RSSI_IB Output Current - mA
Input Referred Noise - mArms
4
2
50
0
1.50
1.25
1.00
0.75
0.50
0.25
0
-40
700
600
500
400
300
200
100
-20
0
20
40
60
80
TA - Ambient Temperature - °C
Figure 9.
8
6
100
0
0
200
400
600
800
1000
1200
Average Input Current - mA
Figure 10.
Copyright © 2011, Texas Instruments Incorporated
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
TYPICAL OPERATION CHARACTERISTICS (continued)
Typical operating condition is at VCC = 3.3 V and TA = 25°C (unless otherwise noted)
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 20 μAPP INPUT CURRENT
25 mVdiv
20 ps/div
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 100 μAPP INPUT CURRENT
20 ps/div
50 mV/div
Figure 11.
Figure 12.
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 500 μAPP INPUT CURRENT
OUTPUT EYE-DIAGRAM AT 10.3 GBPS
AND 2 mAPP INPUT CURRENT
60 mV/div
20 ps/div
Figure 13.
Copyright © 2011, Texas Instruments Incorporated
60 mV/div
20 ps/div
Figure 14.
9
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
APPLICATION INFORMATION
Figure 15 shows the ONET8521T used in a typical fiber optic receiver using the internal photodiode bias. The
ONET8521T converts the electrical current generated by the PIN photodiode into a differential output voltage.
The FILTER inputs provide a dc bias voltage for the PIN that is low pass filtered by the combination of an internal
220Ω resistor and a capacitor. Because the voltage drop across the 220Ω resistor is sensed and used by the
bias circuit, the photodiode must be connected to the FILTER pads for the bias to function correctly.
The RSSI output is used to mirror the photodiode output current and can be connected via a resistor to GND.
The voltage gain can be adjusted for the intended application by choosing the external resistor; however, for
proper operation of the ONET8521T, ensure that the voltage at RSSI never exceeds VCC – 0.65V. If the RSSI
output is not used while operating with internal PD bias, it should be left open.
The OUT+ and OUT– pins are internally terminated by 50Ω pull-up resisters to VCC. The outputs must be ac
coupled, for example by using 0.1μF capacitors, to the succeeding device.
VCC_OUT
VCC_IN
0.1μF
OUT+
0.1μF
OUT-
1
RSSI
R RSSI
GND
Figure 15. Basic Application Circuit for PIN Receivers
Figure 16 shows the ONET8521T being used in a typical fiber optic receiver using an external photodiode bias
for an APD photodiode. This configuration can also be used for a PIN diode if desired. The external bias RSSI
signal is based on a dc offset value and is not as accurate as the internal bias RSSI signal which is based upon
the photodiode current.
10
Copyright © 2011, Texas Instruments Incorporated
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
VCC_OUT
0.1μF
OUT+
0.1μF
OUT-
VCC_IN
V_BIAS
RSSI
R RSSI
GND
Figure 16. Basic Application Circuit for APD Receivers
ASSEMBLY RECOMMENDATIONS
Careful attention to assembly parasitics and external components is necessary to achieve optimal performance.
Recommendations that optimize performance include:
1. Minimize the total capacitance on the IN pad by using a low capacitance photodiode and paying attention to
stray capacitances. Place the photodiode close to the ONET8521T die in order to minimize the bond wire
length and thus the parasitic inductance.
2. Use identical termination and symmetrical transmission lines at the ac coupled differential output pins OUT+
and OUT–.
3. Use short bond wire connections for the supply terminals VCC_IN, VCC_OUT, and GND. Supply voltage
filtering is provided on chip but filtering may be improved by using an additional external capacitor.
Copyright © 2011, Texas Instruments Incorporated
11
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
CHIP DIMENSIONS AND PAD LOCATIONS
1036μm
18 17 8541T
L
1
16
2
15
3
14
4
13
5
12
y
8
7
6
9
10 11
870μm
x
Die Thickness: 203 ± 13 μm
Pad Dimensions: 105 µm × 65 μm
Die Size: 870 ± 40 μm × 1036 ± 40 μm
PAD
COORDINATES
(referenced to pad 1)
x (μm)
12
SYMBOL
TYPE
DESCRIPTION
y (μm)
1
0
0
GND
Supply
Circuit ground
2
0
-115
OUT+
Analog output
Non-inverted data output
3
0
-230
GND
Supply
Circuit ground
4
0
-460
VCC_OUT
Supply
3.3V supply voltage
5
0
-575
VCC_IN
Supply
3.3V supply voltage
6
115.5
-728
GND
Supply
Circuit ground
7
225.5
-728
FILTER1
Analog
Bias voltage for photodiode
8
335.5
-728
IN
Analog input
Data input to TIA
9
445.5
-728
FILTER2
Analog
Bias voltage for photodiode
10
555.5
-728
GND
Supply
Circuit ground
11
665.5
-728
NC
No connect
Do not connect
12
671
-575
RSSI_IB
Analog output
RSSI output signal for internally biased receivers
13
671
-460
RSSI_EB
Analog output
RSSI output signal for externally biased receivers
14
671
-230
GND
Supply
Circuit ground
15
671
-115
OUT–
Analog output
Inverted data output
16
671
0
GND
Supply
Circuit ground
17
393
109
GND
Supply
Circuit ground
18
278
109
GND
Supply
Circuit ground
Copyright © 2011, Texas Instruments Incorporated
ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
TO46 LAYOUT EXAMPLE
An example for a layout using an external bias voltage for the photodiode in a 5 pin TO46 can is shown in
Figure 17. Figure 18 shows an example with a backside cathode contact photodiode using the internal bias
voltage.
OUT–
OUT+
Capacitor
Capacitor or
ceramic
substrate
VCC
VAPD
Capacitor
Figure 17. TO46 5 Pin Layout Using the ONET8521T with an Avalanche Photodiode
OUT–
OUT+
Capacitor
Backside
Cathode
Capacitor or
ceramic
substrate
VCC
RSSI
Figure 18. TO46 5 Pin Layout Using the Internal Bias Voltage for a Backside Cathode Contact
Photodiode
Copyright © 2011, Texas Instruments Incorporated
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ONET8521T
SLLSE87A – JULY 2011 – REVISED AUGUST 2011
www.ti.com
REVISION HISTORY
Changes from Original (July 2011) to Revision A
Page
•
Changed die size .................................................................................................................................................................. 1
•
Changed die size ................................................................................................................................................................ 12
14
Copyright © 2011, Texas Instruments Incorporated
PACKAGE OPTION ADDENDUM
www.ti.com
9-Sep-2011
PACKAGING INFORMATION
Orderable Device
ONET8521TY
Status
(1)
ACTIVE
Package Type Package
Drawing
DIESALE
Y
Pins
Package Qty
0
360
Eco Plan
(2)
Green (RoHS
& no Sb/Br)
Lead/
Ball Finish
Call TI
MSL Peak Temp
(3)
Samples
(Requires Login)
N / A for Pkg Type
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
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Addendum-Page 1
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